© 2009 Microchip Technology Inc. DS22145A-page 1
MCP6L71/1R/2/4
Features
• Gain Bandwidth Product: 2 MHz (typical)
• Supply Current: IQ = 150 µA (typical)
• Supply Voltage: 2.0V to 6.0V
• Rail-to-Rail Input/Outp ut
• Extended Temperature Range: –40°C to +125°C
• Available in Single, Dual and Quad Packages
Typical Applications
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery Powered Systems
Design Aids
• FilterLab® Software
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Typical Application
Description
The Microchip Technology Inc. MCP6L71/1R/2/4 family
of operational amplifiers (op amps) supports general
purpose applications. The combination of rail-to-rail
input and output, l ow quie scent curre nt an d b andwidth
fit into many applicaitons.
This family has a 2 MHz Gain Bandwidth Product
(GBWP) and a low 150 µA per amplifier quiescent cur-
rent. These op amps operate on supply voltages
between 2.0V and 6.0V , with rail-to-rail input and output
swing. They are available in the extended temperature
range.
Package Types
Inverting Amplifier
MCP6L71
R1R2
VREF
VIN VOUT
R3
VIN–
MCP6L71
SOIC, MSOP
VDD
1
2
3
4
8
7
6
5NC
NC
NC
VIN+
VSS
VOUT
VINA–
MCP6L72
SOIC, MSOP
VOUTB
1
2
3
4
8
7
6
5VINB+
VDD
VOUTA
VINA+
VSS
VINB–
VINA–
MCP6L74
SOIC, TSSOP
VIND–
1
2
3
4
14
13
12
11 VSS
VOUTD
VOUTA
VINA+
VDD
VIND+
5
6
7
10
9
8
VINB+VINC+
VOUTC
VINB–
VOUTB
VINC–
VSS
MCP6L71
SOT-23-5
1
2
3
5
4
VDD
VOUT
VIN+V
IN–VDD
MCP6L71R
SOT-23-5
1
2
3
5
4
VSS
VOUT
VIN+V
IN–
2 MHz, 150 µA Op Amps
MCP6L71/1R/2/4
DS22145A-page 2 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22145A-page 3
MCP6L71/1R/2/4
1.0 ELECTRICAL CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) ††.. VSS –1.0VtoV
DD +1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................–65°C to +150°C
Junction Temperature (TJ) .........................................+150°C
ESD Protection On All Pins (HBM/MM)................ ≥ 4 kV/400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
1.2 Specifications
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD =5.0V, V
SS = GND, VCM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2 and RL=10kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min
(Note 1) Typ Max
(Note 1) Units Conditions
Input Offset
Input Offset Voltage VOS –4 ±1 +4 mV
Input Offset Temperature Drift ΔVOS/ΔTA— ±1.3 — µV/°C TA = –40°C to +125°C,
Power Supply Rejection Ratio PSRR — 89 — dB
Input Bias Curr ent and Impedance
Input Bias Current IB—1—pA
IB—50—pAT
A= +85°C
IB— 2000 — pA TA= +125°C
Input Offset Current IOS —±1—pA
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF
Common Mode
Common Mode Input Voltage
Range VCMR -0.3 — +5.3 V
Common Mode Rejection Ratio CMRR — 91 — dB VCM = –0.3V to 5.3V
Open-Loop Gain
DC Open-Loop Gain
(Large Signal) AOL —105—dBV
OUT = 0.2V to 4.8V,
VCM =V
SS
Output
Maximum Output Voltage Swing VOL — — 0.020 V G = +2 V/V,
0.5V input overdrive
VOH 4.980 — — V G = +2 V/V,
0.5V input overdrive
Output Short Circui t Current ISC —±25—mA
Note 1: For design guidance only; not tested.
MCP6L71/1R/2/4
DS22145A-page 4 © 2009 Microchip Technology Inc.
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
TABLE 1-3: TEMPERATURE SPECIFICATIONS
Power Supply
Supply Voltage VDD 2.0 — 6.0 V
Quiescent Current per Amplifier IQ50 150 240 µA IO = 0
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND,
VCM =V
DD2, VOUT ≈VDD/2, VL = VDD/2, RL=10kΩ to VL and CL= 60 pF. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 2.0 — MHz
Phase Margin PM — 65 — ° G = +1 V/V
Slew Rate SR — 0.9 — V/µs
Noise
Input Noise Voltage Eni —4.6 — µVP-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —19 — nV/√Hz f = 10 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD =5.0V, V
SS = GND, VCM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2 and RL=10kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min
(Note 1) Typ Max
(Note 1) Units Conditions
Note 1: For design guidance only; not tested.
Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS =GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA–40 — +125 °C
Operating Temperature Range TA–40 — +125 °C Note 1
Storage Temperature Range TA–65 — +150 °C
Thermal Package Resist ances
Thermal Resistance, 5L-SOT-23 θJA —256—°C/W
Thermal Resistance, 8L-SOIC θJA —163—°C/W
Thermal Resistance, 8L-MSOP θJA —206—°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note 1: The Junction Temperature (TJ) must not exceed the Absolute Maximum specific ation of +150°C.
© 2009 Microchip Technology Inc. DS22145A-page 5
MCP6L71/1R/2/4
1.3 Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s common mode voltage ((VP+V
M)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
EQUATION 1-1:
FIGURE 1-1: AC and DC Test Circuit for
Most Specifications.
GDM RFRG
⁄=
VCM VPVDD 2⁄+()2⁄=
VOUT VDD 2⁄()VPVM
–()VOST 1GDM
+()++=
Where:
GDM = Differential Mode Gain (V/V)
VCM = Op Amp’s Common Mode
Input Voltage (V)
VOST = Op Amp’s Tot a l Input Offset
Voltage (mV)
VOST VIN–VIN+
–=
VDD
MCP6L7X
RGRF
VOUT
VM
CB2
CL
RL
VL
CB1
100 kΩ
100 kΩ
RGRF
VDD/2
VP100 kΩ
100 kΩ
60 pF10 kΩ
1µF100 nF
VIN–
VIN+
CF
6.8 pF
CF
6.8 pF
MCP6L71/1R/2/4
DS22145A-page 6 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22145A-page 7
MCP6L71/1R/2/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA= +25°C, VDD =5.0V, V
SS = GND, VCM =V
DD/2, VOUT ≈VDD/2, VL=V
DD/2,
RL=10kΩ to VL and CL=60pF.
FIGURE 2-1: Input Offset Voltage vs.
Common Mode Input Voltage at VDD =2.0V.
FIGURE 2-2: Input Offset Voltage vs.
Common Mode Input Voltage at VDD =5.5V.
FIGURE 2-3: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-4: Input Common Mode Range
Voltage vs. Ambient Temperature.
FIGURE 2-5: CMRR, PSRR vs.
Temperature.
FIGURE 2-6: CMRR, PSRR vs.
Frequency.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed here in
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified pow er supply range) and therefore outside the warranted range.
-100
-50
0
50
100
150
200
250
300
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.0V
Representitive Part
T
A = +125°C
T
A = +85°C
T
A = +25°C
T
A = -40°C
-100
-50
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
Representitive Part
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
-100
-50
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Outpu t Voltage (V)
Input Offset Voltage (µV)
VDD = 2.0V
VCM = VSS
Representative Part
VDD = 5.5V
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Common Mode Range (V)
VCMRH – VDD
VCMRL – VSS
One Wafer Lot
60
70
80
90
100
110
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
(VCM = VSS)
CMRR (V
CM
= -0.3V to +5.3V)
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
1 10k 100k 1M10010 1k
PSRR–
PSRR+
CMRR
MCP6L71/1R/2/4
DS22145A-page 8 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C, VDD =5.0V, V
SS = GND, VCM =V
DD/2, VOUT ≈VDD/2, VL=V
DD/2,
RL=10kΩ to VL and CL=60pF.
FIGURE 2-7: Input Current vs. Input
Voltage.
FIGURE 2-8: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-9: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-10: The MCP6L71/1R/2/4 Show
No Phase Reversal.
FIGURE 2-11: Quiescent Current vs.
Supply Voltage.
FIGURE 2-12: Output Short Circuit Current
vs. Supply Voltage.
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Op en- Loop Phase (°)
Gain
Phase
0.1
1 10 100 1k 10k 100k 1M 10M
10
100
1,000
1.E-
01 1.E+0
01.E+0
11.E+0
21.E+0
31.E+0
41.E+0
51.E+0
6Frequency (H z)
Inp u t Noise Volt age Density
(nV/√Hz)
0.1
100
10 1k
100k
10k 1M1
-1
0
1
2
3
4
5
6
Time (1 ms/div)
Inp ut, Outp ut Vo ltage ( V)
VDD = 5.0V
G = +2 V/V
VIN
VOUT
0
50
100
150
200
250
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Q u ie sc ent Current
(µA/amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ouptut Short-Circuit Current
(mA)
TA
= +125°C
TA
= +85°C
TA
= +25°C
TA
= -40°C
© 2009 Microchip Technology Inc. DS22145A-page 9
MCP6L71/1R/2/4
Note: Unless otherwise indicated, TA= +25°C, VDD =5.0V, V
SS = GND, VCM =V
DD/2, VOUT ≈VDD/2, VL=V
DD/2,
RL=10kΩ to VL and CL=60pF.
FIGURE 2-13: Ratio of Output Voltage
Headroom vs. Output Current Magnitude.
FIGURE 2-14: Large Signal Non-inverting
Pulse Response.
FIGURE 2-15: Small Signal Non-inverting
Pulse Response.
FIGURE 2-16: Slew Rate vs. Ambient
Temperature.
FIGURE 2-17: Maximum Output Voltag e
Swing vs. Frequency.
0
5
10
15
20
25
30
35
40
45
50
0.1 1 10
Output Current Magnitude (mA)
Ratio of Output Headroom to
Output Curre nt (mV/mA)
VDD – VOH
IOUT
VOL – VSS
-IOUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 µs/div)
Output Voltage (V)
G = +1 V/V
VDD = 5.0V
Time (2 µs/d iv)
Output Voltage (10 mV/div )
G = +1 V/V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew R ate (V/µs)
Falling Edge
VDD = 5.5V
V
DD = 2.0V
Rising Edge
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Ma ximum Output V oltage
Swing (VP-P)
VDD = 2. 0V
1k 10k 100k 1M
VDD = 5. 5V
10M
MCP6L71/1R/2/4
DS22145A-page 10 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22145A-page 11
MCP6L71/1R/2/4
3.0 PIN DESCRIPTIONS
Description s of the pi ns are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
3.1 Analog Outputs
The output pins are low impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high
impedance CMOS inputs with low bias currents.
3.3 Power Supply Pins
The positive power supply (VDD) is 2.0V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
MCP6L71 MCP6L71R Symbol Description
MSOP, SOIC SOT-23-5 SOT-23-5
244V
IN– Inverting Input
333V
IN+ Non-inverting Input
425V
SS Negative Power Supply
611V
OUT Analog Output
752V
DD Positive Power Supply
1,5,8 — — NC No Internal Connection
MCP6L72 MCP6L74 Symbol Description
MSOP, SOIC SOIC, TSSOP
11V
OUTA Analog Output (op amp A)
22V
INA– Inverting Input (op amp A)
33V
INA+ Non-inverting Input (op amp A)
84V
DD Positive Power Supply
55V
INB+ Non-inverting Input (op amp B)
66V
INB– Inverting Input (op amp B)
77V
OUTB Analog Output (op amp B)
—8V
OUTC Analog Output (op amp C)
—9V
INC– Inverting Input (op amp C)
—10V
INC+ Non-inverting Input (op amp C)
411V
SS Negative Power Supply
—12V
IND+ Non-inverting Input (op amp D)
—13V
IND– Inverting Input (op amp D)
—14V
OUTD Analog Output (op amp D)
MCP6L71/1R/2/4
DS22145A-page 12 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22145A-page 13
MCP6L71/1R/2/4
4.0 APPLICATION INFORMATION
The MCP6L71/1R/2/4 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low cost, low power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
make the MCP6L71/1R/2/4 ideal for battery powered
applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP6L71/1R/2/4 op amps are designed to pre-
vent phase inversion when the input pins exceed the
supply voltages. Figure 2-10 shows an input voltage
exceeding both supplies without any phase reversal.
4.1.2 INP UT VOLTAGE AND CURRENT
LIMITS
In order to prevent damag e and/or improper operation
of these amplifiers, the circuit they are in must limit the
currents (and voltages) at the input pins (see
Section 1.1 “Absolute Maximum Ratings †”).
Figure 4-1 shows the recommended approach to pro-
tecting these inputs. The internal ESD diodes prevent
the input pins (VIN+ and VIN–) from going too far below
ground, and the resistors R1 and R2 limit the possible
current drawn out of the input pins. Diodes D1 and D2
prevent the input pins (VIN+ and VIN–) from going too
far above VDD, and dump any currents onto VDD.
FIGURE 4-1: Protecting the Analog
Inputs.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-7. Applications that are high impedance may
need to limit the usable voltage range.
4.1.3 NORMAL OPERATIONS
The input stage of the MCP6L71/1R/2/4 op amps uses
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other at high VCM. With this topology, and at
room temperature, the device operates with VCM up to
0.3V above VDD and 0.3V below VSS (typically at
+25°C).
The transition between the two input stage occurs
when VCM =VDD – 1.1V. For the best distortion and
gain linearity , with non-inverting gains, avoid this region
of operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6L71/1R/2/4 op
amps is VDD – 20 mV (minimum) and VSS +20mV
(maximum) when RL=10kΩ is connected to VDD/2
and VDD = 5.0V. Refer to Figure 2-13 for more informa-
tion.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peakin g in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-2) improv es the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-2: Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Bench measurements are helpful in choosing RISO.
Adjust RISO so that a small signal step response (see
Figure 2-15) has reasonable oversh oot (e.g., 4%).
V1
MCP6L7X
R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
VOUT
R2>VSS – (minimum expected V2)
2mA
V2R2
D2
R3
RISO VOUT
CL
MCP6L7X
RF
RG
RN
MCP6L71/1R/2/4
DS22145A-page 14 © 2009 Microchip Technology Inc.
4.4 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supp ly) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high frequency perfo rmance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.5 Unused Amplifiers
An unused op amp in a quad package (MCP6L74)
should be configured as shown in Figure 4-3. These
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R1 and R2 produce a voltage
within its output voltage range (VOH, VOL). The op amp
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
FIGURE 4-3: Unused Op Amps.
4.6 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6L71/1R/2/4 family’s bias current at +25°C (1 pA,
typical).
The easiest way to reduce surface leaka ge is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-4 shows an example of this typ e of layout.
FIGURE 4-4: Example Guard Ring
Layout.
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detect ors):
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases th e guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity Gain Buffer:
a) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
b) Connect the non-inverting pi n (VIN+) to the
input with a wire that does not touch the
PCB surface.
4.7 Application Circuits
4.7.1 INVERTING INTEGRATOR
An inverting integrator is shown in Figure 4-5. The
circuit provides an output voltage that is proportional to
the negative time-integral of the input. The additional
resistor R2 limits DC gain and controls output clipping.
To minimize the integrator ’s error for slow sign als, the
value of R2 should be much la rger than the valu e of R1.
FIGURE 4-5: Inverting Integrator.
¼MCP6L74(A)
VDD
¼ MCP6L74 (B)
R1
R2
VDD
VDD
VREF
VREF VDD R2
R1R2
+
------------------
⋅=
Guard Ring VIN–V
IN+
+
_C1
R2
VIN
VOUT
MCP6L71
R2R1
»
VOUT 1
R1C1
-------------VIN td
0
t
∫
–=
R1
© 2009 Microchip Technology Inc. DS22145A-page 15
MCP6L71/1R/2/4
5.0 DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6L71/1R/2/4 family of op amps.
5.1 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the Micro-
chip web site at www .microchip.com/filterlab, the Filter-
Lab design tool provides full schematic diagrams of the
filter circuit with component va lues. It also outputs the
filter circuit in SPICE format, which can be used with
the macro model to simulate actual filter performance.
5.2 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require-
ment. Available at no cost from the Microchip web site
at www.microchip.com/ maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory , MCUs and DSCs. Using this
tool you can define a filter to sort features for a para-
metric search of devices and export side-by-side tech-
nical comparison reports. Helpful links are also
provided for Data sheets, Purchase, and Sampling of
Microchip parts.
5.3 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
• 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5.4 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended a s supplemental ref-
erence resources.
•ADN003: “Select the Right Operational Amp lifier
for your Filtering Circuits”, DS21821
•AN722: “Operational Amplifier T opologies and DC
Specifications”, DS00722
•AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
•AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
•AN990: “Analog Se nsor Conditioning Circuits –
An Overview”, DS00990
MCP6L71/1R/2/4
DS22145A-page 16 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22145A-page 17
MCP6L71/1R/2/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead SOIC (150 mil) (MCP6L71, MCP6L72)Example:
XXXXXXXX
XXXXYYWW
NNN
8-Lead MSOP (MCP6L71, MCP6L72) Example:
XXXXXX
YWWNNN
6L72E
911256
5-Lead SOT-23 (MCP6L71, MCP6L71R)Example:
XXNN WG25
Device Code
MCP6L71 WGNN
MCP6L71R WFNN
Note: Applies to 5-Lead SOT-23
MCP6L72E
SN^^0911
256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘0 1’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
MCP6L71/1R/2/4
DS22145A-page 18 © 2009 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead TSSOP (MCP6L74) Example:
14-Lead SOIC (150 mil) (MCP6L74) Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXX
YYWW
NNN
6L74EST
0911
256
XXXXXXXXXX MCP6L74
0911256
E/SL^^
3
e
© 2009 Microchip Technology Inc. DS22145A-page 19
MCP6L71/1R/2/4
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DS22145A-page 20 © 2009 Microchip Technology Inc.
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© 2009 Microchip Technology Inc. DS22145A-page 21
MCP6L71/1R/2/4
#$%&'()*+,
1, $!&%#$,08$#$ #8#!-###!
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MCP6L71/1R/2/4
DS22145A-page 22 © 2009 Microchip Technology Inc.
#$%&'()*+,
.# #$#/!- 0 #1/%##!#
##+22---2/
© 2009 Microchip Technology Inc. DS22145A-page 23
MCP6L71/1R/2/4
-.#$%&'()*+,
1, $!&%#$,08$#$ #8#!-###!
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A1
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L
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c
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β
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- *=()
MCP6L71/1R/2/4
DS22145A-page 24 © 2009 Microchip Technology Inc.
.# #$#/!- 0 #1/%##!#
##+22---2/
© 2009 Microchip Technology Inc. DS22145A-page 25
MCP6L71/1R/2/4
-.//!#.&.)*
1, $!&%#$,08$#$ #8#!-###!
!"!#$!!% #$ !% #$ #&!( !
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3# 44""
4# 5 56 7
5$8%1 5
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6,9# : :
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#!%% ( : (
6,<!# " =)*
!!1/<!# " (
!!1/4# ( (
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.## 4 ".
.# I> : ;>
4!/ :
4!<!# 8 :
NOTE 1
D
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c
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MCP6L71/1R/2/4
DS22145A-page 26 © 2009 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS22145A-page 27
MCP6L71/1R/2/4
APPENDIX A: REVISION HISTORY
Revision A (March 2009)
• Original data sheet release .
MCP6L71/1R/2/4
DS22145A-page 28 © 2008 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22145A-page 29
MCP6L71/1R/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6L71T: Single Op Amp (Tape and Reel)
(MSOP, SOIC, SOT-23-5)
MCP6L71RT: Single Op Amp (Tape and Reel)
(SOT-23-5)
MCP6L72T: D ual Op Amp (Tape and Reel)
(MSOP, SOIC)
MCP6L74T: Quad Op Amp (Tape and Reel)
(SOIC, TSSOP)
Temperature Range: E = -40°C to +125°C
Package: OT = Plastic Small Outline Transistor (SO T-23), 5-lead
(MCP6L71, MCP6L71R)
MS = Plastic MSOP, 8-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4. 4 mm Body), 14-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6L71T-E/OT: Tape and Reel,
5LD SOT-23 package.
b) MCP6L71T-E/MS: Tape and Reel,
8LD MSOP package.
c) MCP6L71T-E/SN: Tape and Reel,
8LD SOIC package.
a) MCP6L71RT-E/OT: Tape and Reel,
5LD SOT-23 package.
a) MCP6L72T-E/MS: Tape and Reel,
8LD MSOP package.
b) MCP6L72T-E/SN: Tape and Reel,
8LD SOIC package.
a) MCP6L74T-E/SL: Tape and Reel,
14LD SOIC package.
b) MCP6L74-E/ST: Tape and Reel,
14LD TSSOP package.
–
MCP6L71/1R/2/4
DS22145A-page 30 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22145A-page 31
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22145A-page 32 © 2009 Microchip Technology Inc.
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