GaAs, pHEMT, MMIC, Low Noise Amplifier,
6 GHz to 17 GHz
Data Sheet
HMC903LP3E
Rev. G Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Low noise figure: 1.7 dB typical at 6 GHz to 16 GHz
High gain: 18.5 dB typical at 6 GHz to 16 GHz
Output power for 1 dB compression (P1dB): 14.5 dBm typical
at 6 GHz to 16 GHz
Single-supply voltage: 3.5 V at 80 mA typical
Output third-order intercept (IP3): 25 dBm typical
50 Ω matched input/output
Self biased with optional bias control for IDQ reduction
16-lead, 3 mm × 3 mm, LFCSP package
APPLICATIONS
Point to point radios
Point to multipoint radios
Military and space
Test instrumentation
FUNCTIONAL BLOCK DIAGRAM
PACKAGE
BASE
GND
1
2
3
4
NIC
GND
RFIN
NIC
NIC
GND
RFOUT
NIC
12
11
10
9
NIC
VDD1
VDD2
NIC
16
15
14
13
NIC
VGG1
VGG2
NIC
5
6
7
8
HMC903LP3E
14479-001
Figure 1.
GENERAL DESCRIPTION
The HMC903LP3E is a self biased, gallium arsenide (GaAs),
monolithic microwave integrated circuit (MMIC), pseudomorphic
(pHEMT), low noise amplifier (LNA) with an option bias
control for IDQ reduction. It is housed in a 16-lead, 3 mm × 3 mm,
LFCSP package. The HMC903LP3E amplifier operates from 6 GHz
to 17 GHz, providing 18.5 dB of small signal gain and 1.7 dB noise
figure in the 6 GHz to 16 GHz band, and an output IP3 of
25 dBm full band 6 GHz to 17 GHz, while requiring only
80 mA from a 3.5 V supply.
The P1dB output power of 14.5 dBm enables the LNA to function
as a local oscillator (LO) driver for balanced, I/Q or image reject
mixers. The HMC903LP3E also features an input and an output
that are dc blocked and internally matched to 50 Ω, making it
ideal for high capacity microwave radios and video satellite
(VSAT) applications.
HMC903LP3E Data Sheet
Rev. G | Page 2 of 13
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
6 GHz to 16 GHz Frequency Range ........................................... 3
16 GHz to 17 GHz Frequency Range ......................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ..............................5
Interface Schematics .....................................................................5
Typical Performance Characteristics ..............................................6
Theory of Operation .........................................................................9
Applications Information .............................................................. 10
Recommended Bias Sequence During Power Up .................. 10
Recommended Bias Sequence During Power Down ............ 10
Evaluation PCB ........................................................................... 11
Typical Application Circuits ..................................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
7/2017—Rev. F to Rev. G
Changed HMC903 to HMC903LP3E ......................... Throughout
Changes to Figure 1 .......................................................................... 1
Changes to RF Input Parameter, Table 3 ....................................... 4
This Hittite Microwave product data sheet has been reformatted
to the styles and standards of Analog Devices, Inc.
1/2017—v06.0816 (HMC903LP3E) to Rev. F
Updated Format .................................................................. Universal
Changes to Features Section, Figure 1, and General Description
Section ................................................................................................. 1
Add Thermal Resistance Section and Table 5; Renumbered
Sequentially ........................................................................................ 4
Changes to Figure 2 and Table 5 ...................................................... 5
Added Theory of Operation Section .............................................. 9
Added Applications Information Section ................................... 10
Updated Outline Dimensions ....................................................... 13
Added Ordering Guide .................................................................. 13
Data Sheet HMC903LP3E
Rev. G | Page 3 of 13
SPECIFICATIONS
TA = 25°C, VDD1 = VDD2 = 3.5 V, IDQ = 80 mA (VGG1 = VGG2 = open for normal, self biased operation), unless otherwise noted.
6 GHz TO 16 GHz FREQUENCY RANGE
Table 1.
Parameter
Min
Typ
Max
Unit
GAIN 16.5 18.5 dB
Gain Variation over Temperature 0.012 dB/°C
NOISE FIGURE1 1.7 2.2 dB
RETURN LOSS
Input 12 dB
Output 12 dB
OUTPUT POWER
For 1 dB Compression (P1dB)1 13 14.5 dBm
Saturated (PSAT )1 16.5 dBm
OUTPUT THIRD-ORDER INTERCEPT (IP3) 22 25 dBm
SUPPLY CURRENT (IDQ) 80 110 mA
1 Board loss removed from gain, power, and noise figure measurements.
16 GHz TO 17 GHz FREQUENCY RANGE
Table 2.
Parameter Min Typ Max Unit
GAIN 15 18 dB
Gain Variation over Temperature 0.012 dB/°C
NOISE FIGURE1 2.2 2.5 dB
RETURN LOSS
Input 11 dB
Output
14
dB
OUTPUT POWER
For 1 dB Compression (P1dB)1 12 13 dBm
Saturated (PSAT )1 16.5 dBm
OUTPUT THIRD-ORDER INTERCEPT (IP3) 22 25 dBm
SUPPLY CURRENT (IDQ) 80 110 mA
1 Board loss removed from gain, power, and noise figure measurements.
HMC903LP3E Data Sheet
Rev. G | Page 4 of 13
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Drain Bias Voltage 4.5 V
RF Input Power 20 dBm
Gate Bias Voltage
VGG1 −0.8 V to +0.2 V
VGG2 −0.8 V to +0.2 V
Continuous Power Dissipation, PDISS (TA =
85°C, Derate 6.9 mW/°C Above 85°C)
0.45 W
Channel Temperature
150°C
Maximum Peak Reflow Temperature 260°C
Storage Temperature −65°C to +85°C
Operating Temperature −40°C to +85°C
ESD Sensitivity (Human Body Model) Class 0, Passed 150 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 4. Thermal Resistance
Package Type
1
θ
JC
Unit
HCP-16-1 144.8 °C/W
1 Thermal impedance simulated values are based on JEDEC 2s2p thermal test
board. See JEDEC JESD51.
ESD CAUTION
Data Sheet HMC903LP3E
Rev. G | Page 5 of 13
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC903LP3E
TOP VIEW
(Not to S cale)
NOTES
1. NIC = NOT INTERNALLY CONNECTE D.
2. EXPOSED P AD. T HE P ACKAGE BO TT OM HAS
AN EXPOSED METAL GROUND PADDLE
THAT MUST CONNECT TO RF/DC GRO UND.
PACKAGE
BASE
GND
1
2
3
4
NIC
GND
RFIN
NIC
NIC
GND
RFOUT
NIC
12
11
10
9
NIC
V
DD1
V
DD2
NIC
16
15
14
13
NIC
V
GG1
V
GG2
NIC
5
6
7
8
14479-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 5, 8, 9,
12, 13, 16
NIC Not Internally Connected. However, all data shown was measured with these pins connected to RF/dc ground
externally.
2, 11 GND Ground. Connect these pins to RF/dc ground. See Figure 3 for the interface schematic.
3 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic.
6, 7 VGG1, VGG2 Optional Gate Controls for the Amplifier. If left open, the amplifier runs self biased at the standard current.
Applying a negative voltage reduces the drain current. External capacitors are required (see Figure 24). See
Figure 5 for the interface schematic.
10 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic.
14, 15 VDD1, VDD2 Power Supply Voltages for the Amplifier. See assembly for the required external components (see Figure 23 and
Figure 24). See Figure 7 for the interface schematic.
EPAD Exposed Pad. The package bottom has an exposed metal ground paddle that must connect to RF/dc ground.
INTERFACE SCHEMATICS
GND
14479-003
Figure 3. GND Interface Schematic
RFIN
14479-004
Figure 4. RFIN Interface Schematic
V
GG1
, V
GG2
14479-005
Figure 5. VGG1 and VGG2 Interface Schematic
RFOUT
14479-006
Figure 6. RFOUT Interface Schematic
V
DD1
,
V
DD2
14479-007
Figure 7. VDD1 and VDD2 Interface Schematic
HMC903LP3E Data Sheet
Rev. G | Page 6 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
25
15
–5
5
–15
–25 31917151311975
RESPONSE (dB)
FRE QUENCY ( GHz)
S11
S21
S22
14479-008
Figure 8. Broadband Gain and Return Loss (Board Loss Removed from Gain,
Power, and Noise Figure Measurements) vs. Frequency
0
–5
–10
–15
–20
–25 618161412108
INP UT RETURN L OSS (dB)
FREQUENCY ( G Hz )
–40°C
+25°C
+85°C
14479-009
Figure 9. Input Return Loss vs. Frequency for Various Temperatures
6
4
5
3
2
1
0618161412108
NOISE FI GURE ( dB)
FREQUENCY ( G Hz )
–40°C
+25°C
+85°C
14479-010
Figure 10. Noise Figure vs. Frequency for Various Temperatures (Board Loss
Removed from Gain, Power, and Noise Figure Measurements)
24
10
12
14
16
18
20
22
618161412108
GAIN (dB)
FRE QUENCY (GHz )
–40°C
+25°C
+85°C
14479-011
Figure 11. Gain vs. Frequency for Various Temperatures (Board Loss
Removed from Gain, Power, and Noise Figure Measurements)
0
–5
–10
–15
–20
–25 618161412108
OUTPUT RETURN LOS S (dB)
FRE QUENCY (GHz )
–40°C
+25°C
+85°C
14479-012
Figure 12. Output Return Loss vs. Frequency for Various Temperatures
30
25
20
15
10
5618161412108
OUTPUT IP3 (dBm)
FRE QUENCY (GHz )
–40°C
+25°C
+85°C
14479-013
Figure 13. Output Third-Order Intercept (IP3) vs. Frequency for Various
Temperatures
Data Sheet HMC903LP3E
Rev. G | Page 7 of 13
25
20
15
10
0
5
618161412108
P1dB (d Bm)
FREQUENCY (GHz)
–40°C
+25°C
+85°C
14479-014
Figure 14. Output Power for 1 dB Compression (P1dB) vs. Frequency for
Various Temperatures (Board Loss Removed from Gain, Power, and
Noise Figure Measurements)
0
–10
–20
–30
–40
–60
–50
618161412108
REVERSE ISOLATIO N (dB)
FRE QUENCY (GHz )
–40°C
+25°C
+85°C
14479-015
Figure 15. Reverse Isolation vs. Frequency for Various Temperatures
22
8
10
12
14
16
18
20
7
0
1
2
3
4
5
6
3.0 4.03.5
GAIN (dB), P1dB (dBm)
NOISE FIGURE (dB)
V
DD
(V)
NOI S E F IG URE
P1dB
GAIN
14479-016
Figure 16. Gain, Output Power for 1 dB Compression (P1dB), and Noise
Figure vs. Supply Voltage (VDD) at 12 GHz (Board Loss Removed from Gain,
Power, and Noise Figure Measurements)
25
20
15
10
0
5
618161412108
P
SAT
(dBm)
FRE QUENCY (GHz )
–40°C
+25°C
+85°C
14479-017
Figure 17. Saturated Output Power (PSAT) vs. Frequency for
Various Temperatures (Board Loss Removed from Gain, Power, and
Noise Figure Measurements)
24
20
16
12
8
4
0
–4
–20 –17 –14 –11 –8 –5 –2 1 4
P
OUT
(dBm), GAIN (dB), PAE (%)
INPUT POWER (dBm)
PAE
P
OUT
GAIN
14479-018
Figure 18. Output Power (POUT), Gain, and Power Added Efficiency (PAE) vs.
Input Power (Board Loss Removed from Gain, Power, and
Noise Figure Measurements)
94
92
90
88
86
84
82
80
78
–30 –27 –24 –21 –18 –15 –12 –9 –6 –3 0 3
I
DD
(mA)
INPUT POWER (dBm)
14479-019
Figure 19. Supply Current (IDD) vs. Input Power (Board Loss Removed from
Gain Measurement and Data Taken at VDD1 = VDD2 = 3 V)
HMC903LP3E Data Sheet
Rev. G | Page 8 of 13
30
25
20
15
10
5
0
120
100
80
60
40
20
0
–0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0
GAIN (dB), IP3 (dBm)
I
DD
(mA)
V
GG1
, V
GG2
GATE VOLTAGE (V dc)
I
DD
GAIN
IP3
14479-020
Figure 20. Gain, Output Third-Order Intercept (IP3), and Supply Current (IDD) vs.
VGG1, VGG2 Gate Voltage
Data Sheet HMC903LP3E
Rev. G | Page 9 of 13
THEORY OF OPERATION
The HMC903LP3E is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic (pHEMT),
low noise amplifier. The HMC903LP3E amplifier uses two gain
stages in series, and the basic schematic of the amplifier is shown in
Figure 21, which forms a low noise amplifier operating from 6 GHz
to 17 GHz with excellent noise figure performance.
VDD1
VGG1
VDD2
VGG2
RFIN RFOUT
14479-021
Figure 21. Basic Schematic of the Amplifier
The HMC903LP3E has single-ended input and output ports
whose impedances are nominally equal to 50 Ω over the 6 GHz
to 17 GHz frequency range. Consequently, it can directly insert
into a 50 Ω system with no required impedance matching
circuitry, which also means that multiple HMC903LP3E
amplifiers can be cascaded back to back without the need for
external matching circuitry.
The input and output impedances are sufficiently stable vs.
variations in temperature and supply voltage that no impedance
matching compensation is required.
Note that it is critical to supply very low inductance ground
connections to the GND pins and to the package base exposed
pad to ensure stable operation. To achieve optimal performance
from the HMC903LP3E and to prevent damage to the device, do
not exceed the absolute maximum ratings.
HMC903LP3E Data Sheet
Rev. G | Page 10 of 13
APPLICATIONS INFORMATION
Figure 22 shows the basic connections for operating the
HMC903LP3E. Both the RFIN and RFOUT ports have on-chip
dc block capacitors that eliminate the need for external ac
coupling capacitors.
The HMC903LP3E has VGG1 and VGG2 optional gate bias pins.
When these pins are left open, the amplifier runs in self biased
operation with a typical IDQ = 80 mA, when VDD1/VDD2 = 3.5 V.
When using the VGG1 and VGG2 gate bias pins, follow the
recommended bias sequencing so that the amplifier is not
damaged.
RECOMMENDED BIAS SEQUENCE DURING
POWER UP
The recommended bias sequence to power up the
HMC903LP3E is as follows:
1. Connect to GND.
2. Set VGG1 and VGG2 to −2 V.
3. Set VDD1 and VDD2 to 3.5 V.
4. Increase VGG1 and VGG2 to achieve a typical IDQ = 80 mA.
5. Apply the RF signal.
RECOMMENDED BIAS SEQUENCE DURING POWER
DOWN
The recommended bias sequence to power down the
HMC903LP3E is as follows:
1. Turn off the RF signal.
2. Decrease VGG1 and VGG2 to −2 V to achieve a typical IDQ =
0 mA.
3. Decrease VDD1 and VDD2 to 0 V.
4. Increase VGG1 and VGG2 to 0 V.
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 23), with
the evaluation board (see Figure 22) and biased per the conditions
in this section. The VDD1 and VDD2 pins are connected together,
similarly the VGG1 and VGG2 pins are also connected together.
The bias conditions shown in this section are the operating
points recommended to optimize the overall performance.
Operation using other bias conditions may provide
performance that differs from what is shown in this data sheet.
Decreasing the VDD1 and VDD2 levels has negligible effect on the
gain and noise figure performance; however, they reduce the
P1dB. This behavior is shown in Figure 8 thru Figure 20. For
applications where the P1dB requirement is not stringent, the
HMC903LP3E can be down biased to reduce power
consumption.
Data Sheet HMC903LP3E
Rev. G | Page 11 of 13
EVALUATION PCB
The circuit board used in this application must use RF circuit
design techniques. Signal lines must have 50 Ω impedance, and
the package ground leads and exposed paddle must be connected
directly to the ground plane similar to that shown in Figure 22.
Use a sufficient number of via holes to connect the top and
bottom ground planes. Mount the evaluation PCB to an
appropriate heat sink. The evaluation PCB shown is available
from Analog Devices, Inc., upon request.
14479-022
Figure 22. Evaluation PCB (128395-1)
Table 6. List of Materials for the Evaluation PCB
Component Description
J1, J2 SMA connectors
J3, J4, J6 to J8 DC pins
C1, C4, C7, C10 100 pF capacitors, 0402 package
C2, C5, C8, C11 0.01 μF capacitors, 0402 package
C3, C6, C9, C12 4.7 μF tantalum capacitors
U1 HMC903LP3E amplifier
PCB 128395-1 evaluation PCB; circuit board material: Rogers 4350 or Arlon 25FR
HMC903LP3E Data Sheet
Rev. G | Page 12 of 13
TYPICAL APPLICATION CIRCUITS
1
2
3
4
RFIN RFOUT
12
11
10
9
16
15
14
13
5
6
7
8
V
DD1
C9
4.7µF
+C8
0.01µF C7
100pF
V
DD2
C10
100pF +
C11
0.01µF C12
4.7µF
C1
100pF
C4
100pF
14479-023
Figure 23. Standard (Self Biased) Operation Typical Application Circuit
1
2
3
4
RFIN RFOUT
12
11
10
9
16
15
14
13
5
6
7
8
VDD1 C9
4.7µF
+C8
0.01µF C7
100pF
VDD2
C10
100pF +
C11
0.01µF C12
4.7µF
VGG1 C6
4.7µF
+C5
0.01µF C4
100pF
VGG2
C1
100pF +
C2
0.01µF C3
4.7µF
14479-024
Figure 24. Gate Control, Reduced Current Operation Typical Application Circuit
Data Sheet HMC903LP3E
Rev. G | Page 13 of 13
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.20
1.95
1.70 SQ
1.50
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
0.45
0.40
0.35
0.05 M AX
0.02 NO M
0.20 REF
0.20 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.90
0.85
0.80
03-15-2017-B
PKG-004863
COM P LIANT WITH JE DE C S TANDARDS MO-220- V E E D- 4.
FOR PRO P E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATION AND
FUNCTION DESCRIPT IONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTI ONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 25. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(HCP-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Lead Finish Package Description Package Option Branding2
HMC903LP3E −40°C to +85°C 100% Matte Sn 16-Lead LFCSP HCP-16-1 903
XXXX
HMC903LP3ETR −40°C to +85°C 100% Matte Sn 16-Lead LFCSP HCP-16-1 903
XXXX
129798-HMC903LP3E Evaluation Board
1 The HMC903LP3E is a RoHS Compliant Part.
2 The four digital lot number for the HMC903LP3E is XXXX.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14479-0-7/17(G)
