PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD44164082, 44164182, 44164362 18M-BIT DDRII SRAM 2-WORD BURST OPERATION Description The PD44164082 is a 2,097,152-word by 8-bit, the PD44164182 is a 1,048,576-word by 18-bit and the PD44164362 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The PD44164082, PD44164182 and PD44164362 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC FBGA. Features * 1.8 0.1 V power supply and HSTL I/O * DLL circuitry for wide output data valid window and future frequency scaling * Pipelined double data rate operation * Common data input/output bus * Two-tick burst for low DDR transaction size * Two input clocks (K and /K) for precise DDR timing at clock rising edges only * Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device * Internally self-timed write control * Clock-stop capability with s restart * User programmable impedence output * Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz) * Simple control logic for easy depth expansion * JTAG boundary scan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M15821EJ2V0DS00 (2nd edition) Date Published April 2002 NS CP(K) Printed in Japan The mark shows major revised points. (c) 2001 PD44164082, 44164182, 44164362 Ordering Information Part number Cycle Clock Time Frequency ns MHz PD44164082F5-E30-EQ1 3.0 333 PD44164082F5-E33-EQ1 3.3 300 PD44164082F5-E40-EQ1 4.0 250 PD44164082F5-E50-EQ1 5.0 200 PD44164082F5-E60-EQ1 6.0 167 PD44164182F5-E30-EQ1 3.0 333 PD44164182F5-E33-EQ1 3.3 300 PD44164182F5-E40-EQ1 4.0 250 PD44164182F5-E50-EQ1 5.0 200 PD44164182F5-E60-EQ1 6.0 167 PD44164362F5-E30-EQ1 3.0 333 PD44164362F5-E33-EQ1 3.3 300 PD44164362F5-E40-EQ1 4.0 250 PD44164362F5-E50-EQ1 5.0 200 PD44164362F5-E60-EQ1 6.0 167 2 Organization Core Supply (word x bit) Voltage I/O Package Interface V 2 M x 8-bit 1.8 0.1 HSTL 165-pin PLASTIC FBGA (13 x 15) 1 M x 18-bit 512 K x 36-bit Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 Pin Configurations (Marking Side) /xxx indicates active low signal. 165-pin PLASTIC FBGA (13 x 15) (Top View) [PD44164082F5-EQ1] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS A R, /W /NW1 /K NC /LD A VSS CQ B NC NC NC A NC K /NW0 A NC NC DQ3 C NC NC NC VSS A A A VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS A A A VSS NC NC NC P NC NC DQ7 A A C A A NC NC NC R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input DQ0 to DQ7 : Data inputs / outputs TDI : IEEE 1149.1 Test input /LD : Synchronous load TCK : IEEE 1149.1 Clock input R, /W : Read Write input TDO : IEEE 1149.1 Test output /NW0, /NW1 : Nybble Write data select CQ, /CQ : Echo clock K, /K : Input clock VREF : HSTL input reference input C, /C : Output clock VDD : Power Supply ZQ : Output impedance matching VDDQ : Power Supply /DLL : DLL disable VSS : Ground NC : No connection Remark Refer to Package Drawing for the index mark. Preliminary Data Sheet M15821EJ2V0DS 3 PD44164082, 44164182, 44164362 165-pin PLASTIC FBGA (13 x 15) (Top View) [PD44164182F5-EQ1] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS A R, /W /BW1 /K NC /LD A VSS CQ B NC DQ9 NC A NC K /BW0 A NC NC DQ8 C NC NC NC VSS A A0 A VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS A A A VSS NC NC NC P NC NC DQ17 A A C A A NC NC DQ0 R TDO TCK A A A /C A A A TMS TDI A0, A : Address inputs TMS : IEEE 1149.1 Test input DQ0 to DQ17 : Data inputs / outputs TDI : IEEE 1149.1 Test input /LD : Synchronous load TCK : IEEE 1149.1 Clock input R, /W : Read Write input TDO : IEEE 1149.1 Test output /BW0, /BW1 : Byte Write data select CQ, /CQ : Echo clock K, /K : Input clock VREF : HSTL input reference input C, /C : Output clock VDD : Power Supply ZQ : Output impedance matching VDDQ : Power Supply /DLL : DLL disable VSS : Ground NC : No connection Remark Refer to Package Drawing for the index mark. 4 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 165-pin PLASTIC FBGA (13 x 15) (Top View) [PD44164362F5-EQ1] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS NC R, /W /BW2 /K /BW1 /LD A VSS CQ B NC DQ27 DQ18 A /BW3 K /BW0 A NC NC DQ8 C NC NC DQ28 VSS A A0 A VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS A A A VSS NC NC DQ10 P NC NC DQ26 A A C A A NC DQ9 DQ0 R TDO TCK A A A /C A A A TMS TDI A0, A : Address inputs TMS : IEEE 1149.1 Test input DQ0 to DQ35 : Data inputs / outputs TDI : IEEE 1149.1 Test input /LD : Synchronous load TCK : IEEE 1149.1 Clock input R, /W : Read Write input TDO : IEEE 1149.1 Test output /BW0 to /BW3 : Byte Write data select CQ, /CQ : Echo clock K, /K : Input clock VREF : HSTL input reference input C, /C : Output clock VDD : Power Supply ZQ : Output impedance matching VDDQ : Power Supply /DLL : DLL disable VSS : Ground NC : No connection Remark Refer to Package Drawing for the index mark. Preliminary Data Sheet M15821EJ2V0DS 5 PD44164082, 44164182, 44164362 Pin Identification Symbol A0 A /LD R, /W /NWx /BWx K, /K C, /C Description Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on future devices. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used as the lowest order address bit permitting a random starting address within the burst operation. These inputs are ignored when device is deselected. Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock periods of bus activity). Synchronous Read/Write Input: When /LD is LOW, this input designates the access type (READ when /R, W is HIGH, WRITE when /R, W is LOW) for the loaded address. /R, W must meet the setup and hold times around the rising edge of K. Synchronous Byte Writes (Nybble Writes on x8): When LOW these inputs cause their respective byte or nybble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data relationships. Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of C is used as the output timing reference for first output data. The rising edge of /C is used as the output reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation. /DLL DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation. ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not used in the circuit. IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the circuit. TMS TDI TCK VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and /K. Output data is synchronized to the respective C and /C data clocks or to K and /K if C and /C are tied to HIGH. x8 device uses DQ0-DQ7. Remaining signals are NC. x18 device uses DQ0-DQ17. Remaining signals are NC. x36 device uses DQ0-DQ35. Remaining signals are NC. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. CQ, /CQ TDO IEEE 1149.1 Test Output: 1.8V I/O level. VDD Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range. VDDQ Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics and Operating Conditions for range. VSS Power Supply: Ground NC No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation. 6 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 Block Diagram CLK Burst Logic A0 D0 A0' Q0 R Address Register Address /LD /W E Compare /C A0'' Write address Register K E Output control A0''' Logic A0' Input Register /A0' A0' C Output Register /A0' Memory Array Sense Amps CLK WRITE Driver A0' WRITE Register E C 0 ZQ 2 :1 MUX 1 Output Buffer E DQ 0 /K E Input Register 1 A0''' Output Enable Register C R, /W Register R, /W E Burst Sequence Linear Burst Sequence Table [PD44164182, PD44164362] A0 A0 External Address 0 1 1st Internal Burst Address 1 0 Preliminary Data Sheet M15821EJ2V0DS 7 PD44164082, 44164182, 44164362 Truth Table Operation WRITE cycle /LD R, /W CLK DQ L L LH Data in Load address, input write data on two Input data D(A1) D(A2) consecutive K and /K rising edge Input clock K(t+1) /K(t+1) READ cycle L H LH Data out Load address, read data on two Output data Q(A1) Q(A2) consecutive C and /C rising edge Output clock /C(t+1) C(t+2) NOP (No operation) H X LH Hi-Z STANDBY(Clock stopped) X X Stopped Previous state Remarks 1. H : High level, L : Low level, x : don't care, : rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges. 3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of K. All control inputs are registered during the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst address in accordance with the linear burst sequence. 7. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 8 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 Byte Write Operation [PD44164082] Operation Write D0-7 Write D0-3 Write D4-7 Write nothing K /K /NW0 /NW1 LH - 0 0 - LH 0 0 LH - 0 1 - LH 0 1 LH - 1 0 - LH 1 0 LH - 1 1 - LH 1 1 /BW0 /BW1 Remark H : High level, L : Low level, : rising edge. [PD44164182] Operation K /K LH - 0 0 - LH 0 0 Write D0-8 LH - 0 1 - LH 0 1 Write D9-17 LH - 1 0 - LH 1 0 Write nothing LH - 1 1 - LH 1 1 Write D0-17 Remark H : High level, L : Low level, : rising edge. [PD44164362] Operation Write D0-35 Write D0-8 K /K /BW0 /BW1 /BW2 /BW3 LH - 0 0 0 0 - LH 0 0 0 0 LH - 0 1 1 1 - LH 0 1 1 1 LH - 1 0 1 1 - LH 1 0 1 1 LH - 1 1 0 1 - LH 1 1 0 1 Write D27-35 LH - 1 1 1 0 - LH 1 1 1 0 Write nothing LH - 1 1 1 1 - LH 1 1 1 1 Write D9-17 Write D18-26 Remark H : High level, L : Low level, : rising edge. Preliminary Data Sheet M15821EJ2V0DS 9 PD44164082, 44164182, 44164362 Bus Cycle State Diagram LOAD NEW ADDRESS Count = 0 Load, Count = 2 Load, Count = 2 Write Read READ DOUBLE Count = Count + 2 WRITE DOUBLE COUNT = Count + 2 NOP, Count = 2 NOP, Count = 2 NOP NOP Power UP Supply voltage provided Remarks 1. A0 is internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 2. 2. State machine control timing sequence is controlled by K. 10 Preliminary Data Sheet M15821EJ2V0DS Load PD44164082, 44164182, 44164362 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD -0.5 +2.9 V VDDQ -0.5 VDD V Input voltage VIN -0.5 VDD + 0.5 (2.9 V MAX.) V Input / Output voltage VI/O -0.5 VDDQ + 0.5 (2.9 V MAX.) V Junction temperature Tj +125 C Storage temperature Tstg +125 C Supply voltage Output supply voltage Caution -55 Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (Tj = 20 to 110 C) Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit Note VDD 1.7 1.9 V VDDQ 1.4 VDD V High level input voltage VIH VREF + 0.1 VDDQ + 0.3 V 1 Low level input voltage VIL -0.3 VREF - 0.1 V 1 Clock input voltage VIN -0.3 VDDQ + 0.3 V 1 Reference voltage VREF 0.68 0.95 V Output supply voltage Note1 Overshoot: VIH (AC) VDD + 0.7 V for t TKHKH/2 Undershoot: VIL (AC) - 0.5V for t TKHKH/2 Power-up: VIH VDDQ + 0.3V and VDD 1.7V and VDDQ 1.4V for t 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than TKHKL (MIN) or operate at cycle rates less than TKHKH (MIN). Capacitance (TA = 25 C, f = 1MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 4 5 pF Input / Output capacitance CI/O VI/O = 0 V 6 7 pF Clock Input capacitance Cclk Vclk = 0 V 5 6 pF Remark These parameters are periodically sampled and not 100% tested. Preliminary Data Sheet M15821EJ2V0DS 11 PD44164082, 44164182, 44164362 DC Characteristics (Tj = 20 to 110C, VDD = 1.8 0.1 V) Parameter Symbol Test condition MIN. TYP. MAX. x8, x18 Unit x36 Input leakage current ILI -2 - +2 A I/O leakage current ILO -2 - +2 A Operating supply current IDD (Read Write cycle) Standby supply current ISB1 (NOP) High level output voltage VOH Low level output voltage VIN VIL or VIN VIH, -E30 525 710 II/O = 0 mA -E33 475 640 Cycle = MAX. -E40 400 545 -E50 330 445 -E60 280 380 VIN VIL or VIN VIH, -E30 255 265 II/O = 0 mA -E33 235 240 Cycle = MAX. -E40 200 210 -E50 170 180 -E60 150 160 VOH(Low) |IOH| 0.1 mA Note1 VOL(Low) IOL 0.1 mA VOL Note2 mA mA VDDQ - 0.2 - VDDQ V 3, 4 VDDQ/2-0.08 - VDDQ/2+0.08 V 3, 4 VSS - 0.2 V 3, 4 VDDQ/2-0.08 - VDDQ/2+0.08 V 3, 4 Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 3. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 4. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 12 Note Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 AC Characteristics (Tj = 20 C to 110 C, VDD = 1.8 0.1 V) AC Test Conditions Input waveform (Rise / Fall time 0.3 ns) 1.25 V 0.75 V Test Points 0.75 V 0.25 V Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition Figure 1. External load at test VDDQ / 2 0.75 V 50 VREF ZO = 50 SRAM 250 ZQ Remark CL includes capacitances of the probe and jig, and stray capacitances. Preliminary Data Sheet M15821EJ2V0DS 13 PD44164082, 44164182, 44164362 Read and Write Cycle Parameter Symbol -E30 -E33 -E40 -E50 -E60 (333 MHz) (300 MHz) (250 MHz) (200 MHz) (167 MHz) Unit Note MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Clock Average Clock cycle time (K, /K, C, /C) TKHKH Clock phase jitter (K, /K, C, /C) Clock HIGH time (K, /K, C, /C) Clock LOW time (K, /K, C, /C) 3.6 TKC var - TKHKL 1.20 4.0 5.0 0.2 - - 1.6 3.3 4.0 0.2 - - 1.32 6.0 7.5 ns 1 0.2 - 0.2 ns 2 - 2.4 - ns 5.0 6.0 0.2 - - 2.0 TKLKH 1.20 - 1.32 - 1.6 - 2.0 - 2.4 - ns Clock to /clock (K/K., C/C.) TKH /KH 1.35 - 1.49 - 1.8 - 2.2 - 2.7 - ns Clock to /clock (/KK., /CC.) T /KHKH 1.35 - 1.49 - 1.8 - 2.2 - 2.7 - ns TKHCH 0 Clock to data clock (KC., /K/C.) 3.0 1.30 0 1.45 0 1.8 0 2.3 0 2.8 ns DLL lock time (K, C) TKC lock 1,024 - 1,024 - 1,024 - 1,024 - 1,024 - Cycle K static to DLL reset TKC reset 30 - 30 - 30 - 30 - 30 - ns 3 Output Times C, /C HIGH to output valid TCHQV - 0.27 - 0.29 - 0.35 - 0.38 - 0.40 ns C, /C HIGH to output hold TCHQX - 0.27 - - 0.29 - - 0.35 - - 0.38 - - 0.40 - ns C, /C HIGH to echo clock valid TCHCQV - 0.25 - 0.27 - 0.33 - 0.36 - 0.38 ns C, /C HIGH to echo clock hold TCHCQX - 0.25 - - 0.27 - - 0.33 - - 0.36 - - 0.38 - ns CQ, /CQ HIGH to output valid TCQHQV 0.27 - 0.29 - 0.35 - 0.38 - 0.40 ns 4 CQ, /CQ HIGH to output hold TCQHQX - 0.27 - - 0.29 - - 0.35 - - 0.38 - - 0.40 - ns 4 0.27 - 0.29 - 0.35 - 0.38 - 0.40 ns - - 0.29 - - 0.35 - - 0.38 - - 0.40 - ns C HIGH to output High-Z C HIGH to output Low-Z TCHQZ - - TCHQX1 - 0.27 Setup Times Address valid to K rising edge TAVKH 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 Control inputs valid to K rising edge TIVKH 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 Data-in valid to K, /K rising edge TDVKH 0.3 - 0.33 - 0.4 - 0.5 - 0.6 - ns 5 TKHAX 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 K rising edge to control inputs hold TKHIX 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 K, /K rising edge to data-in hold TKHDX 0.3 - 0.33 - 0.4 - 0.5 - 0.6 - ns 5 Hold Times K rising edge to address hold Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.). 2. Clock phase jitter is the variance from clock rising edge to the next expected colck rising edge. 3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations. 5. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. Remarks 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than TKHKL (MIN). 4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters. 5. VDDQ is 1.5 VDC. 14 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 Read and Write Timing NOP READ NOP READ (burst of 2) (burst of 2) 1 2 3 READ WRITE WRITE (burst of 2) (burst of 2) (burst of 2) NOP 4 5 6 7 8 A2 A3 A4 9 10 TKHKH K TKHKL TKLKH TKLKH TKH/KH T/KHKH /K /LD TIVKH TKHIX R, /W TAVKH TKHAX A0 Address A1 TKHDX TKHDX TDVKH TDVKH DQ Qx2 Q01 TCHQX1 TKHCH TKHCH Q02 Q11 TCHQX TCHQV TCHQV D21 Q12 D22 D23 D24 Q41 Q42 TCQHQX TCHQZ TCHQX TCQHQV CQ TCHCQX TCHCQV /CQ TCHCQX TCHCQV C TKHKL TKLKH TKHKH TKH/KH T/KHKH /C Remarks 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disable (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. Preliminary Data Sheet M15821EJ2V0DS 15 PD44164082, 44164182, 44164362 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name TCK Pin assignments 2R Description Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 10R Test Mode Select. This is the command input for the TAP controller state machine. TDI 11R Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is deter-mined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP. JTAG DC Characteristics (20 C Tj 110 C, 1.7 V VDD 1.9 V, unless otherwise noted) Parameter Symbol Conditions MIN. TYP. MAX. Unit JTAG Input leakage current ILI 0 V VIN VDD -5.0 - +5.0 A JTAG I/O leakage current ILO 0 V VIN VDDQ, -5.0 - +5.0 A Outputs disabled JTAG input high voltage VIH 1.3 - VDD+0.3 V JTAG input low voltage VIL -0.3 - +0.5 V JTAG output high voltage JTAG output low voltage 16 VOH1 | IOHC | = 100 A 1.6 - - V VOH2 | IOHT | = 2 mA 1.4 - - V VOL1 IOLC = 100 A - - 0.2 V VOL2 IOLT = 2 mA - - 0.4 V Preliminary Data Sheet M15821EJ2V0DS Note PD44164082, 44164182, 44164362 JTAG AC Test Conditions Input waveform (Rise / Fall time 1 ns) 1.8 V 0.9 V Test Points 0.9 V 0.9 V Test Points 0.9 V 0V Output waveform Output load Figure 2. External load at test VTT = 0.9 V 50 ZO = 50 TDO 20 pF Preliminary Data Sheet M15821EJ2V0DS 17 PD44164082, 44164182, 44164362 JTAG AC Characteristics (Tj = 5 to 110 C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 100 - - ns Clock Clock cycle time tTHTH Clock frequency fTF - - 10 MHz Clock high time tTHTL 40 - - ns Clock low time tTLTH 40 - - ns TCK low to TDO unknown tTLOX 0 - - ns TCK low to TDO valid tTLOV - - 20 ns TDI valid to TCK high tDVTH 10 - - ns TCK high to TDI invalid tTHDX 10 - - ns tMVTH 10 - - ns tCS 10 - - ns tTHMX 10 - - ns tCH 10 - - ns Output time Setup time TMS setup time Capture setup time Hold time TDI hold time Capture hold time JTAG Timing Diagram 18 Preliminary Data Sheet M15821EJ2V0DS Note PD44164082, 44164182, 44164362 Scan Register Definition (1) Register name Instruction register Description The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit's position in the boundary register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. Scan Register Definition (2) Register name Bit size Unit Instruction register 3 bit Bypass register 1 bit ID register 32 bit Boundary register 107 bit ID Register Definition Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit PD44164082 2M x 8 XXXX 0000 0000 0001 0010 00000010000 1 PD44164182 1M x 18 XXXX 0000 0000 0001 0011 00000010000 1 PD44164362 512K x 36 XXXX 0000 0000 0001 0100 00000010000 1 Preliminary Data Sheet M15821EJ2V0DS 19 PD44164082, 44164182, 44164362 SCAN Exit Order Bit no. Signal name x8 x36 Bit Signal name ID no. x8 x18 Bump Bit Signal name Bump x36 ID no. x8 x18 x36 ID NC NC 2C 1 /C 6R 37 NC NC NC 10D 73 NC 2 C 6P 38 NC NC NC 9E 74 DQ4 3 A 6N 39 NC 10C 75 NC NC DQ29 2D 4 A 7P 40 NC NC DQ16 11D 76 NC NC NC 2E 5 A 7N 41 NC NC NC 9C 77 NC NC NC 1E 6 A 7R 42 NC NC NC 9D 78 NC 7 A 8R 43 DQ3 DQ8 DQ8 11B 79 NC NC DQ21 3F 8 A 8P 44 NC NC DQ7 11C 80 NC NC NC 1G 9 A 9R 45 NC NC NC 9B 81 NC NC NC 1F 11P 46 NC NC NC 10B 82 DQ5 DQ0 DQ0 DQ7 DQ17 DQ11 DQ20 DQ12 DQ30 2F NC 11 NC NC DQ9 10P 47 CQ 11A 83 NC NC DQ31 2G 12 NC NC NC 10N 48 VSS 10A 84 NC NC NC 1J 13 NC NC NC 9P 49 A 9A 85 NC NC NC 2J 14 NC DQ1 DQ11 10M 50 A 8B 86 NC 15 NC NC DQ10 11N 51 A 7C 87 NC NC DQ32 3J 16 NC NC NC 9M 52 6C 88 NC NC NC 2K 17 NC NC NC 9N 53 8A 89 NC NC NC 1K 11L 54 /BW1 7A 90 DQ6 DQ0 DQ2 DQ2 A A0 A0 /LD NC NC DQ13 DQ22 3E 10 18 DQ14 DQ23 DQ15 DQ33 3G 3K 2L 19 NC NC DQ1 11M 55 /NW0 /BW0 /BW0 7B 91 NC NC DQ24 3L 20 NC NC NC 9L 56 K 6B 92 NC NC NC 1M 21 NC NC NC 10L 57 /K 6A 93 NC NC NC 1L 22 NC DQ3 DQ3 11K 58 /BW3 5B 94 NC 23 NC NC DQ12 10K 59 /NW1 /BW1 /BW2 5A 95 NC NC DQ34 3M 24 NC NC NC 9J 60 R, /W 4A 96 NC NC NC 1N 25 NC NC NC 9K 61 A 5C 97 NC NC NC 2M 10J 62 A 4B 98 DQ7 11J 63 3A 99 NC NC DQ35 2N 11H 64 VSS 2A 100 NC NC NC 2P /CQ 1A 101 NC NC NC 1P DQ9 DQ27 2B 102 A 3R 26 27 DQ1 DQ4 DQ13 NC 28 NC DQ4 ZQ NC A NC A NC DQ16 DQ25 DQ17 DQ26 3N 3P 29 NC NC NC 10G 65 30 NC NC NC 9G 66 NC 31 NC DQ5 DQ5 11F 67 NC NC DQ18 3B 103 A 4R 32 NC NC DQ14 11G 68 NC NC NC 1C 104 A 4P 33 NC NC NC 9F 69 NC NC NC 1B 105 A 5P 34 NC NC NC 10F 70 NC 3D 106 A 5N 11E 71 NC NC DQ28 3C 107 A 5R 10E 72 NC NC NC 1D 35 36 20 x18 Bump DQ2 DQ6 DQ6 NC NC DQ15 DQ10 DQ19 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 JTAG Instructions Instructions EXTEST Description EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the RAM output are forced to Hi-Z any time the instruction is loaded. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE SAMPLE is a Standard 1149.1 mandatory public instruction. When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1 compliant. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (Hi-Z) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. JTAG Instruction Coding IR2 IR1 IR0 Instruction Note 0 0 0 EXTEST 1 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 RESERVED 1 0 0 SAMPLE 1 0 1 RESERVED 1 1 0 RESERVED 1 1 1 BYPASS 1 Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH. Preliminary Data Sheet M15821EJ2V0DS 21 PD44164082, 44164182, 44164362 TAP Controller State Diagram Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor. TDO should be left unconnected. 22 Preliminary Data Sheet M15821EJ2V0DS Test Logic Operation (Instruction Scan) TCK Run-Test/Idle Update-IR Exit1-IR Shift-IR TDI 23 PD44164082, 44164182, 44164362 Output from Instruction Register Output from Instruction Register Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR Output Inactive New Instruction IDCODE Instruction Register state Select-IR-Scan Select-DR-Scan Run-Test/Idle TDO Test-Logic-Reset Controller state Preliminary Data Sheet M15821EJ2V0DS TMS 24 Test Logic Operation (Data Scan) TCK Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR TDI PD44164082, 44164182, 44164362 Output from Instruction Register Output from Instruction Register Exit2-DR Pause-DR Exit1-DR Shift-DR Output Inactive IDCODE Instruction Instruction Register state Capture-DR Select-DR-Scan TDO Run-Test/Idle Controller state Preliminary Data Sheet M15821EJ2V0DS TMS PD44164082, 44164182, 44164362 Package Drawing 165-PIN PLASTIC FBGA (13x15) E w S B ZD ZE B 11 10 9 8 7 6 5 4 3 2 1 A D R P N M L K J H G F E D C B A w S A INDEX MARK A2 y1 S h A S e y S b x M A1 S AB This package drawing is a preliminary version. It may be changed in the future. Preliminary Data Sheet M15821EJ2V0DS ITEM D E ZD ZE e h A A1 A2 b y x w y1 MILLIMETERS 13.00 15.00 1.50 0.50 1.00 0.60 1.40 0.40 1.00 0.45 0.08 0.08 0.15 0.20 25 PD44164082, 44164182, 44164362 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices PD44164082F5-EQ1: 165-pin PLASTIC FBGA (13 x 15) PD44164182F5-EQ1: 165-pin PLASTIC FBGA (13 x 15) PD44164362F5-EQ1: 165-pin PLASTIC FBGA (13 x 15) 26 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 Revision History Edition/ Date 2nd edition/ Page Type of This Previous edition edition Location (Previous edition This edition) revision Throughout Throughout Modification Pin Configurations, Pin Identification, April 2002 Description Address inputs: Ax A Scan Exit Order p.1 p.1 Modification Function Name 18M-BIT CMOS SYNCHRONOUS FAST SRAM DOUBLE DATA RATE 18M-BIT DDRII SRAM Addition p.2 p.2 Description PD44164362 Modification Ordering Information Package code: Fx-EQx F5-EQ1 Deletion Remark Modification Pin Configurations Package code: Fx F5-EQ1 p.3-5 p. 3-5 p.6 p.6 Modification Pin Identification ZQ: VDD VDDQ p.7 p.7 Modification Block Diagram /K K Linear Burst Sequence Table Internal Burst Address 1st Internal Burst Address p.14 p.14 Deletion Item of Ax Modification TKC var (MAX.) -E30: 0.08 0.2, -E33: 0.08 0.2, -E40: 0.10 0.2, -E50: 0.13 0.2, -E60: 0.15 0.2 TKH /KH (MAX.) -E30: 1.65 -, -E33: 1.82 -, -E40: 2.2 -, -E50: 2.75 -, -E60: 3.3 - Addition T /KHKH Modification TAVKH, TIVKH, TKHAX, TKHIX (MIN.) -E40: 0.4 0.5 TDVKH, TKHDX (MIN.) -E30: 0.4 0.3, -E33: 0.4 0.33, -E50: 0.6 0.5, -E60: 0.7 0.6 Addition Note 1, 2, 4 Modification Note 1 5, Note 2 3 Modification Note 3 Addition Remark 5 p.15 p.15 Addition Read and Write Timing p.20 p.20 Modification Scan Exit Order Bit no. 48, 64: NC VSS p.25 p.25 Addition Package drawing (Preliminary version) p.26 p.26 Modification Types of Surface Mount Devices Package Drawing Preliminary Data Sheet M15821EJ2V0DS T /KHKH Package code: Fx F5-EQ1 27 PD44164082, 44164182, 44164362 [MEMO] 28 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 [MEMO] Preliminary Data Sheet M15821EJ2V0DS 29 PD44164082, 44164182, 44164362 [MEMO] 30 Preliminary Data Sheet M15821EJ2V0DS PD44164082, 44164182, 44164362 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet M15821EJ2V0DS 31 PD44164082, 44164182, 44164362 * The information in this document is current as of April, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4