5 kV RMS and 3.75 kV RMS,
Dual-Channel LVDS Gigabit Isolators
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D Document Feedback
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Technical Support www.analog.com
FEATURES
5 kV rms and 3.75 kV rms LVDS isolators
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Any data rate up to 1.1 Gbps switching with low jitter
4 ns typical propagation delay
2.6 ps rms typical random jitter, rms
90 ps typical peak-to-peak total jitter at 1.1 Gbps
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection, phase spur level
Glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN 55022 Class B radiated emissions limits with
1.1 Gbps PRBS
Safety and regulatory approvals (20-lead SOIC_W package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 VPEAK
Fail-safe output high for open, short, and terminated input
conditions (ADN4655/ADN4656)
Operating temperature range: −40°C to +125°C
7.8 mm minimum creepage and clearance
APPLICATIONS
Isolated video and imaging data
Analog front-end isolation
Data plane isolation
Isolated high speed clock and data links
FUNCTIONAL BLOCK DIAGRAMS
LVDS LVDS
GND
1
GND
2
V
DD1
V
IN1
V
IN2
D
IN1+
D
IN1–
D
IN2–
D
IN2+
V
DD2
D
OUT2+
D
OUT2–
D
OUT1–
D
OUT1+
ADN4654
LDO LDO
DIGITAL ISOLATOR
ISOLATION
BARRIER
17011-001
Figure 1.
LVDS LVDS
GND
1
GND
2
V
DD1
V
IN1
V
IN2
D
IN1+
D
IN1–
D
OUT2–
D
OUT2+
V
DD2
D
IN2+
D
IN2–
D
OUT1–
D
OUT1+
ADN4655
LDO LDO
DIGITAL ISOLATOR
ISOLATION
BARRIER
17011-102
Figure 2.
LVDS LVDS
GND
1
GND
2
V
DD1
V
IN1
V
IN2
D
IN1+
D
IN1–
D
OUT2–
D
OUT2+
V
DD2
D
IN2+
D
IN2–
D
OUT1–
D
OUT1+
ADN4656
LDO LDO
DIGITAL ISOLATOR
ISOLATION
BARRIER
17011-050
Figure 3.
GENERAL DESCRIPTION
The ADN4654/ADN4655/ADN46561 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 1.1 Gbps with low jitter. The devices integrate Analog
Devices, Inc., iCoupler® technology, enhanced for high speed
operation to provide galvanic isolation of the TIA/EIA-644-A
compliant LVDS drivers and receivers. This integration allows
drop-in isolation of an LVDS signal chain.
The ADN4654/ADN4655/ADN4656 comprise multiple
channel configurations, and the LVDS receivers on the ADN4655
and ADN4656 include a fail-safe mechanism to ensure a Logic
1 on the corresponding LVDS driver output when the inputs are
floating, shorted, or terminated but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
(LDO) regulator can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and come in a 20-lead, wide body
SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP
package with 3.75 kV rms isolation.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 2 of 25
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 4
Insulation and Safety Related Specifications ............................ 5
Package Characteristics ............................................................... 6
Regulatory Information ............................................................... 6
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending) ............................................................ 7
Recommended Operating Conditions ...................................... 7
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions ............................9
Typical Performance Characteristics ........................................... 12
Test Circuits and Switching Characteristics ................................ 17
Theory of Operation ...................................................................... 18
Truth Table and Fail-Safe Receiver .......................................... 18
Isolation ....................................................................................... 19
Applications Information .............................................................. 20
PCB Layout ................................................................................. 20
Application Examples ................................................................ 20
Magnetic Field Immunity .......................................................... 22
Insulation Lifetime ..................................................................... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
9/2019—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 25
6/2019—Rev. B to Rev. C
Added ADN4656 ................................................................ Universal
Changes to Features Section............................................................ 1
Added Figure 3; Renumbered Sequentially .................................. 1
Added Note 1, Table 8 ...................................................................... 7
Added Figure 8 and Table 15; Renumbered Sequentially ......... 11
Changes to Magnetic Field Immunity Section ........................... 22
Changes to Ordering Guide .......................................................... 25
3/2019—Rev. A to Rev. B
Changes to Title, Features Section, General Description
Section, and Figure 2 ........................................................................ 1
Changes to Table 4 ............................................................................ 5
Added Table 5 .................................................................................... 5
Changes to Table 7 ............................................................................ 6
Changes to Table 8 and Figure 4 ..................................................... 7
Changes to Table 10, Table 11, and Table 12 ................................. 8
Added Figure 44 .............................................................................. 23
Changes to Ordering Guide .......................................................... 23
1/2019—Rev. 0 to Rev. A
Added ADN4655 ................................................................ Universal
Added Figure 2; Renumbered Sequentially ................................... 1
Changes to General Description Section ....................................... 1
Changes to Table 1 ............................................................................. 3
Changes to Table 3 ............................................................................. 4
Added Timing Diagram Section and Figure 3 .............................. 5
Changes to Figure 5 Caption and Table 12 Title ........................... 9
Added Figure 6 and Table 13; Renumbered Sequentially ......... 10
Changes to Theory of Operation Section and Truth Table and
Fail Safe Receiver Section .............................................................. 17
Added Table 15 ............................................................................... 17
Moved Isolation Section ................................................................ 18
Moved PCB Layout Section .......................................................... 19
Changes to PCB Layout Section ................................................... 19
Changes to Ordering Guide .......................................................... 23
11/2018—Revision 0: Initial Version
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 3 of 25
SPECIFICATIONS
For all minimum and maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = −40°C to +125°C, unless otherwise noted. For all
typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUTS (RECEIVERS)
Input Threshold See Figure 38 and Table 2
High VTH 100 mV
Low VTL −100 mV
Differential Input Voltage |VID| 100 mV See Figure 38 and Table 2
Input Common-Mode Voltage VIC 0.5|VID| 2.4 − 0.5|VID| V See Figure 38 and Table 2
Input Current, High and Low IIH, IIL −5 +5 µA
DINx± = VDDx or 0 V, other input = 1.2 V, VDDx =
2.5 V or 0 V
Differential Input Capacitance1 C
INx± 2 pF
DINx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V2
OUTPUTS (DRIVERS)
Differential Output Voltage |VOD| 250 310 450 mV
See Figure 36 and Figure 37, load resistance (RL) =
100 Ω
VOD Magnitude Change |∆VOD| 50 mV See Figure 36 and Figure 37, RL = 100 Ω
Offset Voltage VOS 1.125 1.17 1.375 V See Figure 36, RL = 100 Ω
VOS Magnitude Change ∆VOS 50 mV See Figure 36, RL = 100 Ω
VOS, Peak to Peak1 V
OS(PP) 150 mV See Figure 36, RL = 100 Ω
Output Short-Circuit Current IOS −20 mA DOUTx± = 0 V
12 mA |VOD| = 0 V
Differential Output
Capacitance1
COUTx± 5 pF DOUTx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
POWER SUPPLY
Supply Current IDD1, IIN1,
IDD2, or IIN2
ADN4655/ADN4656 only 55 mA No output load, inputs with 100 Ω, no applied |VID|
58 82 mA All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
ADN4654 only 50 65 mA No output load, inputs with 100 Ω, |VID| = 200 mV
60 80 mA All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
LDO Input Range VIN1 or
VIN2
3.0 3.3 3.6 V No external supply on VDD1 or VDD2
LDO Output Range VDD1 or
VDD2
2.375 2.5 2.625 V
Power Supply Ripple Rejection,
Phase Spur Level
PSRR −75 dBc
Phase spur level on DOUTx± with 0.55 GHz clock on
DINx± and applied ripple of 100 kHz, 100 mV p-p on
a 2.5 V supply to VDD1 or VDD2
COMMON-MODE TRANSIENT
IMMUNITY3
|CM| 25 50 kV/µs
Common-mode voltage (VCM) = 1000 V, transient
magnitude = 800 V
1 These specifications are guaranteed by design and characterization.
2 t denotes time.
3 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx−
pin (no change in output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data
transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 4 of 25
RECEIVER INPUT THRESHOLD TEST VOLTAGES
Table 2. Test Voltages for Receiver Operation
Applied Voltages
Input Voltage, Differential, VID (V) Input Voltage, Common-Mode, VIC (V) Driver Output, Differential VOD (mV) DINx+ (V) DINx− (V)
1.25 1.15 0.1 1.2 >250
1.15 1.25 −0.1 +1.2 <−250
2.4 2.3 0.1 2.35 >250
2.3 2.4 −0.1 +2.35 <−250
0.1 0 0.1 0.05 >250
0 0.1 −0.1 +0.05 <−250
1.5 0.9 0.6 1.2 >250
0.9 1.5 −0.6 +1.2 <−250
2.4 1.8 0.6 2.1 >250
1.8 2.4 −0.6 +2.1 <−250
0.6 0 0.6 0.3 >250
0 0.6 −0.6 +0.3 <−250
TIMING SPECIFICATIONS
For all minimum and maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. All typical
specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max1 Unit Test Conditions/Comments
PROPAGATION DELAY tPLH, tPHL 4 4.5 ns See Figure 39, from any DINx+/DINx− to DOUTx+/DOUTx−
SKEW See Figure 39, across all DOUTx+/DOUTx−
Duty Cycle2 t
SK(D) 100 ps
Channel to Channel3 t
SK(CH) 150 300 ps ADN4654 only
200 500 ps ADN4655 and ADN4656 only
Part to Part4 t
SK(PP) 500 ps ADN4654 to ADN4654 only
600 ps ADN4654, ADN4655, ADN4656, or combinations
JITTER5 See Figure 39, for any DOUTx+/DOUTx−
Random Jitter, RMS6 (1σ) tRJ(RMS) 2.6 4.8 ps rms 0.55 GHz clock input
Deterministic Jitter, Peak to
Peak7, 8
tDJ(PP) 50 116 ps 1.1 Gbps, 223 − 1 pseudorandom bit stream (PRBS)
With Crosstalk tDJC(PP) 50 ps 1.1 Gbps, 223 − 1 PRBS
Total Jitter at Bit Error Rate
(BER) 1 × 10−12
tTJ(PP) 90 171 ps 0.55 GHz, 1.1 Gbps, 223 − 1 PRBS9
Additive Phase Jitter tADDJ 387 fs rms 100 Hz to 100 kHz, output frequency (fOUT) = 10 MHz10
288 fs rms 12 kHz to 20 MHz, fOUT = 0.55 GHz11
RISE AND FALL TIME tR, tF 350 ps
See Figure 39, any DOUTx+/DOUTx−, 20% to 80%, RL = 100 Ω, load
capacitance (CL) = 5 pF
FAIL-SAFE DELAY12 t
FSH, tFSL 1 1.2 µs ADN4655 and ADN4656 only; see Figure 39 and Figure 4,
any DOUTx+/DOUTx−, RL = 100 Ω
MAXIMUM DATA RATE 1.1 1.25 Gbps
1 These specifications are guaranteed by design and characterization.
2 Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPLHx – tPHLx|, where x denotes either
Channel 1 or Channel 2 propagation delay.
3 Channel to channel or output skew is the difference between the largest and smallest values of tPLHx within a device or the difference between the largest and smallest
values of tPHLx within a device, whichever of the two is greater.
4 Part to part output skew is the difference between the largest and smallest values of tPLHx across multiple devices or the difference between the largest and smallest
values of tPHLx across multiple devices, whichever of the two is greater.
5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, tR = tF = 0.3 ns (20% to 80%).
6 This specification is measured over a population of ~7,000,000 edges.
7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)).
8 This specification is measured over a population of ~3,000,000 edges.
9 Using the formula: tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP).
10 With input phase jitter of 250 fs rms subtracted.
11 With input phase jitter of 100 fs rms subtracted.
12 The fail-safe delay is the delay before DOUTx± is switched high to reflect an idle input to DINx± (|VID| < 100 mV, with open, short, or terminated input condition).
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 5 of 25
Timing Diagram
>1.3
V
1.2V
0V
0V
~1.3V
~1.0V
~ +0.3V
~ –0.3V
<1.1V
D
INx+
V
ID
D
OUTx+
D
OUTx–
V
OD
t
FSH
t
FSL
+0.1V
+0.1V +0.1V
–0.1V
(D
INx–
= 1.2V)
17011-103
Figure 4. Fail-Safe Timing Diagram
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 4. 20-Lead SOIC_W Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 5 kV rms 1 minute duration
Minimum External Air Gap (Clearance) L (I01) 7.8 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L (I02) 7.8 mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 8.1 mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance) 22 µm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
Table 5. 20-Lead SSOP Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation
Voltage
3.75 kV rms 1 minute duration
Minimum Clearance L (I01) 5.3 mm min Measured from input terminals to output terminals, shortest distance
through air
Minimum Creepage L (I02) 5.3 mm min Measured from input terminals to output terminals, shortest distance path
along body
Minimum PCB Clearance L (PCB) 5.6 mm min Measured from input terminals to output terminals, shortest distance
through air, line of sight, in the PCB mounting plane
Minimum Internal Clearance 22 µm min Insulation distance through insulation
Comparative Tracking Index CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 6 of 25
PACKAGE CHARACTERISTICS
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 R
I-O 1013 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF Frequency = 1 MHz
Input Capacitance2 C
I 3.7 pF
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation
waveforms and insulation levels.
Table 7.
UL (Pending) CSA (Pending) VDE (Pending)
To Be Recognized Under UL 1577
Component Recognition Program1
To be approved under CSA
Component Acceptance Notice 5A
To be certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Single Protection, Isolation Voltage Reinforced insulation, VIORM = 424 VPEAK, VIOSM = 8000 VPEAK
20-Lead SOIC, 5000 V rms
20-Lead SSOP, 3750 V rms
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 6000 V rms (20-lead SOIC_W) or ≥ 4500 V rms (20-lead
SSOP) for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 795 VPEAK for 1 sec (partial discharge
detection limit = 5 pC).
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 7 of 25
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of
the safety data.
Table 8.
Description Test Conditions/Comments1 Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 424 VPEAK
Input to Output Test Voltage, Method B1 VIORM × 1.875 = VPD (M), 100% production test,
tINI = tM = 1 sec, partial discharge < 5 pC
VPD (M) 795 VPEAK
Input to Output Test Voltage, Method A VPD (M)
After Environmental Tests Subgroup 1 VIORM × 1.5 = VPD (M), tINI = 60 sec, tM = 10 sec,
partial discharge < 5 pC
636 VPEAK
After Input or Safety Test Subgroup 2 and
Subgroup 3
VIORM × 1.2 = VPD (M), tINI = 60 sec, tM = 10 sec,
partial discharge < 5 pC
509 VPEAK
Highest Allowable Overvoltage VIOTM 7000 VPEAK
Surge Isolation Voltage
Basic VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 10,000 VPEAK
Reinforced VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 8000 VPEAK
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 5)
Maximum Junction Temperature TS 150 °C
Total Power Dissipation at 25°C PS
20-Lead SOIC 2.78 W
20-Lead SSOP 1.8 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
1 For information about tM, tINI, and VIO, see DIN V VDE V 0884-10.
17011-002
3.0
2.5
2.0
1.5
0.5
1.0
0020015010050
SAFE LIMITING POWER (W)
AMBIENT TEMPERATURE (°C)
20-LEAD SSOP
20-LEAD SOIC
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 9.
Parameter Symbol Rating
Operating Temperature TA −40°C to +125°C
Supply Voltages
Supply to LDO Regulator VIN1, VIN2 3.0 V to 3.6 V
LDO Bypass, VINx Shorted to VDDx V
DD1, VDD2 2.375 V to 2.625 V
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 8 of 25
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter Rating
VIN1 to GND1/VIN2 to GND2 −0.3 V to +6.5 V
VDD1 to GND1/VDD2 to GND2 −0.3 V to +2.8 V
Input Voltage (DINx+, DINx−) to GNDx on
the Same Side
−0.3 V to VDD + 0.3 V
Output Voltage (DOUTx+, DOUTx−) to
GNDx on the Same Side
−0.3 V to VDD + 0.3 V
Short-Circuit Duration (DOUTx+, DOUTx−)
to GNDx on the Same Side
Continuous
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ Maximum) 150°C
Power Dissipation (TJ maximum − TA)/θJA
Electrostatic Discharge (ESD)
Human Body Model (All Pins to
Respective GNDx, 1.5 kΩ, 100 pF)
±4 kV
IEC 61000-4-2 (LVDS Pins to Isolated
GNDx Across Isolation Barrier)
20-Lead SOIC ±8 kV
20-Lead SSOP ±7 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operation environment. Close attention to PCB thermal design
is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one-cubic foot sealed enclosure.
Table 11. Thermal Resistance
Package Type1 θ
JA Unit
RW-20 45.7 °C/W
RS-20 69.6 °C/W
1 Test Condition 1: thermal impedance simulated with 4-layer standard JEDEC PCB.
ESD CAUTION
Table 12. Maximum Continuous Working Voltage1
Parameter
Rating
Constraint RW-20 RS-20
AC Voltage
Bipolar Waveform
Basic Insulation 424 VPEAK 424 V
PEAK 50-year minimum insulation lifetime for 1% failure
Reinforced Insulation 424 VPEAK 424 V
PEAK 50-year minimum insulation lifetime for 1% failure
Unipolar Waveform
Basic Insulation 848 VPEAK 848 V
PEAK 50-year minimum insulation lifetime for 1% failure
Reinforced Insulation 875 VPEAK 620 V
PEAK Lifetime limited by package creepage, maximum approved working voltage
DC Voltage
Basic Insulation 1079 VPEAK 754 V
PEAK Lifetime limited by package creepage, maximum approved working voltage
Reinforced Insulation 536 VPEAK 380 V
PEAK Lifetime limited by package creepage, maximum approved working voltage
1 The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for
more details.
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 9 of 25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
IN1 1
GND
12
V
DD1 3
GND
14
20
19
18
17
D
IN1+ 5
D
IN1– 6
D
IN2+ 7
D
IN2– 8
V
DD1 912
GND
1
V
IN2
GND
2
V
DD2
GND
2
D
OUT1+
D
OUT1–
D
OUT2+
D
OUT2–
V
DD2
GND
2
10 11
16
15
14
13
ADN4654
TOP VIEW
(Not to Scale)
17011-003
Figure 6. ADN4654 Pin Configuration
Table 13. ADN4654 Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN1 Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1.
2, 4, 10 GND1 Ground, Side 1.
3, 9 VDD1 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If supplying
3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
5 DIN1+ Noninverted Differential Input 1.
6 DIN1− Inverted Differential Input 1.
7 DIN2+ Noninverted Differential Input 2.
8 DIN2− Inverted Differential Input 2.
11, 17, 19 GND2 Ground, Side 2.
12, 18 VDD2 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If supplying
3.3 V to VIN2, connect a 1 µF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
13 DOUT2− Inverted Differential Output 2.
14 DOUT2+ Noninverted Differential Output 2.
15 DOUT1− Inverted Differential Output 1.
16 DOUT1+ Noninverted Differential Output 1.
20 VIN2 Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2.
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 10 of 25
VIN1 1
GND12
VDD1 3
GND14
20
19
18
17
DIN1+ 5
DIN1– 6
DOUT2+ 7
DOUT2– 8
VDD1 912
GND1
VIN2
GND2
VDD2
GND2
DOUT1+
DOUT1–
DIN2+
DIN2–
VDD2
GND2
10 11
16
15
14
13
ADN4655
TOP VIEW
(Not to Scale)
17011-106
Figure 7. ADN4655 Pin Configuration
Table 14. ADN4655 Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN1 Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1.
2, 4, 10 GND1 Ground, Side 1.
3, 9 VDD1 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If supplying
3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
5 DIN1+ Noninverted Differential Input 1.
6 DIN1− Inverted Differential Input 1.
7 DOUT2+ Noninverted Differential Output 2.
8 DOUT2− Inverted Differential Output 2.
11, 17, 19 GND2 Ground, Side 2.
12, 18 VDD2 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If supplying
3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
13 DIN2− Inverted Differential Input 2.
14 DIN2+ Noninverted Differential Input 2.
15 DOUT1− Inverted Differential Output 1.
16 DOUT1+ Noninverted Differential Output 1.
20 VIN2 Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2.
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 11 of 25
V
IN1 1
GND
12
V
DD1 3
GND
14
20
19
18
17
D
IN1+
5
D
IN1–
6
D
OUT2+
7
D
OUT2–
8
V
DD1 912
GND
1
V
IN2
GND
2
V
DD2
GND
2
D
OUT1+
D
OUT1–
D
IN2+
D
IN2–
V
DD2
GND
2
10 11
16
15
14
13
ADN4656
TOP VIEW
(Not to Scale)
17011-051
Figure 8. ADN4656 Pin Configuration
Table 15. ADN4656 Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN1 Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1.
2, 4, 10 GND1 Ground, Side 1.
3, 9 VDD1 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If supplying
3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
5 DOUT1+ Noninverted Differential Output 1.
6 DOUT1− Inverted Differential Output 1.
7 DIN2+ Noninverted Differential Input 2.
8 DIN2− Inverted Differential Input 2.
11, 17, 19 GND2 Ground, Side 2.
12, 18 VDD2 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If supplying
3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
13 DOUT2− Inverted Differential Output 2.
14 DOUT2+ Noninverted Differential Output 2.
15 DIN1− Inverted Differential Input 1.
16 DIN1+ Noninverted Differential Input 1.
20 VIN2 Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2.
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 12 of 25
TYPICAL PERFORMANCE CHARACTERISTICS
VDD1 = VDD2 = 2.5 V, TA = 25°C, RL = 100 , 0.55 GHz input with |VID| = 200 mV, and VIC = 1.1 V for ADN4654, unless otherwise noted.
0
10
20
30
40
50
60
70
0 50 100 150 200 250 300 350 400 450 500 550
SUPPLY CURRENT (mA)
INPUT CLOCK FREQUENCY (MHz)
I
DD1
I
DD2
I
IN1
I
IN2
17011-004
Figure 9. Supply Current vs. Input Clock Frequency
(DIN1± Switching, DIN2± Not Switching)
0
10
20
30
40
50
60
70
80
0 50 100 150 200 250 300 350 400 450 500 550
SUPPLY CURRENT (mA)
INPUT CLOCK FREQUENCY (MHz)
I
DD1
I
DD2
I
IN1
I
IN2
17011-005
Figure 10. Supply Current vs. Input Clock Frequency
(DIN1± and DIN2± Switching)
0
10
20
30
40
50
60
70
–50 –25 0 25 50 75 100 125
SUPPLY CURRENT (mA)
AMBIENT TEMPERATURE (°C)
I
DD1
I
DD2
I
IN1
I
IN2
17011-006
Figure 11. Supply Current vs. Ambient Temperature
(DIN1± with 550 MHz Clock Input, DIN2± Not Switching)
0
10
20
30
40
50
60
70
80
90
–50 –25 0 25 50 75 100 125
SUPPLY CURRENT (mA)
AMBIENT TEMPERATURE (°C)
I
DD1
I
DD2
I
IN1
I
IN2
17011-007
Figure 12. Supply Current vs. Ambient Temperature
(DIN1± and DIN2± with 550 MHz Clock Inputs)
0
10
20
30
40
50
60
70
3.00 3.15 3.30 3.45 3.60
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE, V
IN1
/V
IN2
(V)
I
IN1
(D
IN1±
ACTIVE)
I
IN2
(D
IN1±
ACTIVE)
I
IN1
(D
IN2±
ACTIVE)
I
IN2
(D
IN2±
ACTIVE)
17011-008
Figure 13. Supply Current vs. Supply Voltage, VIN1/VIN2
0
10
20
30
40
50
60
70
2.35 2.50 2.65
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE, V
DD1
/V
DD2
(V)
I
DD1
(D
IN1±
ACTIVE)
I
DD2
(D
IN1±
ACTIVE)
I
DD1
(D
IN2±
ACTIVE)
I
DD2
(D
IN2±
ACTIVE)
17011-009
Figure 14. Supply Current vs. Supply Voltage, VDD1/VDD2
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 13 of 25
2.65
2.35
2.40
2.45
2.50
2.55
2.60
3.0 3.1 3.2 3.3 3.4 3.5 3.6
LDO OUTPUT VOLTAGE,
V
DD1
/
V
DD2
(V)
LDO INPUT VOLTAGE, V
IN1
/V
IN2
(V)
V
DD1
V
DD2
17011-010
Figure 15. LDO Output Voltage, VDD1/VDD2 vs. LDO Input Voltage, VIN1/VIN2
250
260
270
280
290
300
310
320
330
340
350
0 50 100 150 200 250 300 350 400 450 500 550
DRIVER DIFFERENTI
A
L OUTPUT V
O
LTAGE (mV)
INPUT CLOCK FREQUENCY (MHz)
17011-011
V
OD
CHANNEL 1
V
OD
CHANNEL 2
Figure 16. Driver Differential Output Voltage vs. Input Clock Frequency
450
0
50
100
150
200
250
300
350
400
50 12510075 150
DRIVER DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV)
OUTPUT LOAD, RL (Ω)
VOD CHANNEL 1
VOD CHANNEL 2
17011-012
Figure 17. Driver Differential Output Voltage, VOD vs. Output Load, RL
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
2.35 2.652.602.552.502.452.40
DRIVER OUTPUT HIGH VOLTAGE, VOH (V)
SUPPLY VOLTAGE, VDD1/VDD2 (V)
VOH CHANNEL 1
VOH CHANNEL 2
17011-013
Figure 18. Driver Output High Voltage, VOH vs. Supply Voltage, VDD1/VDD2
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
2.35 2.652.602.552.502.452.40
DRIVER OUTPUT LOW VOLTAGE, V
OL
(V)
SUPPLY VOLTAGE, V
DD1
/V
DD2
(V)
V
OL
CHANNEL 1
V
OL
CHANNEL 2
17011-014
Figure 19. Driver Output Low Voltage, VOL vs. Supply Voltage, VDD1/VDD2
1.375
1.325
1.275
1.225
1.175
1.125
2.35 2.652.602.552.502.452.40
DRIVER OUTPUT OFFSET VOLTAGE, V
OS
(V)
SUPPLY VOLTAGE, V
DD1
/V
DD2
(V)
V
OS
CHANNEL 1
V
OS
CHANNEL 2
17011-015
Figure 20. Driver Output Offset Voltage, VOS vs. Supply Voltage, VDD1/VDD2
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 14 of 25
3.60
3.55
3.50
3.45
3.40
3.35
3.30
2.35 2.652.602.552.502.452.40
DIFFERENTIAL PROPAGATION DELAY (ns)
SUPPLY VOLTAGE, VDD1 AND VDD2 (V)
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
17011-016
Figure 21. Differential Propagation Delay vs. Supply Voltage, VDD1 and VDD2
4.0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
–50 12575 10050250–25
DIFFERENTIAL PROPAGATION DELAY (ns)
AMBIENT TEMPERATURE (°C)
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
17011-017
Figure 22. Differential Propagation Delay vs. Ambient Temperature
3.60
3.55
3.50
3.45
3.40
3.35
3.30
01.41.0 1.20.80.60.40.2
DIFFERENTIAL PROPAGATION DELAY (ns)
DIFFERENTIAL INPUT VOLTAGE, V
ID (V)
t
PHL CHANNEL 2
t
PLH CHANNEL 2
t
PHL CHANNEL 1
t
PLH CHANNEL 1
17011-018
Figure 23. Differential Propagation Delay vs. Differential Input Voltage, VID
3.60
3.55
3.50
3.45
3.40
3.35
3.30
02.52.01.51.00.5
DIFFERENTIAL PROPAGATION DELAY (ns)
RECEIVER INPUT OFFSET VOLTAGE, V
IC (V)
t
PHL CHANNEL 2
t
PLH CHANNEL 2
t
PHL CHANNEL 1
t
PLH CHANNEL 1
17011-019
Figure 24. Differential Propagation Delay vs. Receiver Input Offset Voltage, VIC
240
220
200
180
160
140
120
2.35 2.652.602.552.502.452.40
DIFFERENTIAL OUTPUT TRANSITION TIME (ps)
SUPPLY VOLTAGE, VDD1/VDD2 (V)
t
F CHANNEL 2
t
R CHANNEL 2
t
F CHANNEL 1
t
R CHANNEL 1
17011-020
Figure 25. Differential Output Transition Time vs. Supply Voltage, VDD1/VDD2
240
120
140
160
180
200
220
–50 12575 10050250–25
DIFFERENTIAL OUTPUT TRANSITION TIME (ps)
AMBIENT TEMPERATURE (°C)
t
F CHANNEL 2
t
R CHANNEL 2
t
F CHANNEL 1
t
R CHANNEL 1
17011-021
Figure 26. Differential Output Transition Time vs. Ambient Temperature
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 15 of 25
30
0
5
10
15
20
25
2.35 2.652.602.552.502.452.40
DUTY CYCLE SKEW,
t
SK(D)
(ps)
SUPPLY VOLTAGE, V
DD1
AND V
DD2
(V)
t
SK(D)
CHANNEL 2
t
SK(D)
CHANNEL 1
17011-122
Figure 27. Duty Cycle Skew, tSK(D) vs. Supply Voltage, VDD1 and VDD2
30
0
5
10
15
20
25
–50 12575 10050250–25
DUTY CYCLE SKEW, t
SK(D)
(ps)
AMBIENT TEMPERATURE (°C)
t
SK(D)
CHANNEL 2
t
SK(D)
CHANNEL 1
17011-123
Figure 28. Duty Cycle Skew, tSK(D) vs. Ambient Temperature
0
10
20
30
40
50
60
70
80
90
0 200 400 600 800 1000 1200
DETERMINISTIC JITTER (ps)
DATA RATE (Mbps)
CHANNEL 1
CHANNEL 2
17011-024
Figure 29. Deterministic Jitter vs. Data Rate
0
10
20
30
40
50
60
70
80
90
2.35 2.40 2.45 2.50 2.55 2.60 2.65
DETERMINISTIC JITTER (ps)
SUPPLY VOLTAGE, V
DD1
/V
DD2
(V)
CHANNEL 1
CHANNEL 2
17011-025
Figure 30. Deterministic Jitter vs. Supply Voltage, VDD1/VDD2
0
10
20
30
40
50
60
70
80
90
-40 -25 -10 5 20 35 50 65 80 95 110 125
DETERMINISTIC JITTER (ps)
AMBIENT TEMPERATURE (°C)
CHANNEL 1
CHANNEL 2
17011-026
Figure 31. Deterministic Jitter vs. Ambient Temperature
200k
HITS
180k
160k
140k
120k
100k
80k
60k
40k
20k
–80 –60 –40 –20 0
TIME (ps)
20 40 60
0
17011-128
Figure 32. Time Interval Error (TIE) Histogram for DOUT1± at 550 MHz
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 16 of 25
CH1 50mVCH1 50mV CH2 50mV 300ps/DIV
DELAY 61.0828ns
17011-127
Figure 33. Eye Diagram for DOUT1± at 300 MHz
400
VOLTAGE (mV)
300
200
100
0
–100
–200
–300
–600 –400 –200 0
TIME (ps)
200 400 600
–400
17011-130
Figure 34. Eye Diagram for DOUT1± at 550 MHz
CH1 50mVCH1 50mV CH2 50mV 300ps/DIV
DELAY 61.0828ns
17011-129
Figure 35. Eye Diagram for DOUT2± at 300 MHz
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 17 of 25
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
R
L
/2
R
L
/2
D
OUTx+
D
OUTx–
V
OS
V
OD
V
V
D
D
INx+
D
INx–
R
17011-029
Figure 36. Driver Test Circuit
3.75kΩ
3.75kΩ
NOTES
1. V
TEST
= 0V TO 2.4V
R
L
D
OUTx+
D
OUTx–
V
TEST
V
OD
V
V
D
D
INx+
D
INx–
R
17011-030
Figure 37. Driver Test Circuit (Full Load Across Common-Mode Range)
NOTES
1. V
ID
= V
IN+
– V
IN–
2. V
IC
= (V
IN+
+ V
IN–
)/2
3. V
OD
= V
OUT+
– V
OUT–
4. V
OS
= (V
OUT+
+ V
OUT–
)/2
D
OUTx+
D
OUTx–
D
INx+
D
INx–
DR V
OD
V
ID
V
OUT–
V
IN–
V
OUT+
V
IN+
17011-031
Figure 38. Voltage Definitions
NOTES
1. C
L
INCLUDES PROBE AND JIG CAPACITANCE.
R
L
C
L
C
L
D
OUTx+
D
OUTx–
D
INx+
D
INx–
50Ω
SIGNAL
GENERATOR DR
50Ω
17011-032
Figure 39. Timing Test Circuit
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 18 of 25
THEORY OF OPERATION
The ADN4654/ADN4655/ADN4656 are TIA/EIA-644-A LVDS
compliant isolated buffers. LVDS signals applied to the inputs are
transmitted on the outputs of the buffer, and galvanic isolation
is integrated between the two sides of the device. This integration
allows drop-in isolation of the LVDS signal chains.
The LVDS receiver detects the differential voltage present across
a termination resistor on an LVDS input. An integrated digital
isolator transmits the input state across the isolation barrier,
and an LVDS driver outputs the same state as the input.
When there is a positive differential voltage of ≥100 mV across
any DINx± pin, the corresponding DOUTx+ pin sources current.
This current flows across the connected transmission line and
termination at the receiver at the far end of the bus, while
DOUTx− sinks the return current. When there is a negative
differential voltage of ≤−100 mV across any DINx± pin, the
corresponding DOUTx+ pin sinks current and the DOUTx− pin
sources current. Table 16 and Table 17 show these input and
output combinations.
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.1 mA), developing between ±250 mV and ±450 mV
across a 100 termination resistor (RT). The received voltage is
centered around 1.2 V. Because the differential voltage (VID)
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage magnitude (|VID|).
TRUTH TABLE AND FAIL-SAFE RECEIVER
The LVDS standard, TIA/EIA-644-A, defines normal receiver
operation under two conditions: an input differential voltage
of ≥+100 mV corresponding to one logic state, and a voltage of
≤−100 mV for the other logic state. Between these thresholds,
standard LVDS receiver operation is undefined (the LVDS receiver
can detect either state), as shown in Table 16 for the ADN4654. The
ADN4655/ADN4656 incorporates a fail-safe circuit to ensure
that the LVDS outputs are in a known state (logic high) when
the input state is undefined (−100 mV < VID < +100 mV), as
shown in Table 17.
This input state occurs when the inputs are floating (unconnected
with no termination resistor), shorted, or when there is no
active driver connected to the inputs with a termination resistor
present. Open-circuit, short-circuit, and terminated or idle bus
fail-safes, respectively, ensure a known output state for these
conditions, as implemented by the ADN4655/ADN4656.
After these input states (−100 mV < VID < +100 mV) trigger
the fail-safe circuit, there is a delay of up to 1.2 µs before the
output is guaranteed to be high (VOD ≥ 250 mV). During this
time, the output may transition to, or stay in, a logic low state
(VOD ≤ −250 mV).
The fail-safe circuit triggers as soon as the input differential voltage
remains between +100 mV and −100 mV for some nanoseconds.
Therefore, very slow rise and fall times on the input signal,
outside typical LVDS operation (350 ps maximum tR/tF), can
potentially trigger the fail-safe circuit on a high to low crossover.
At the minimum |VID| of 100 mV for normal operation, the rise
and fall time must be ≤5 ns to avoid triggering a fail-safe state.
Increasing |VID| to 200 mV allows an input rise and fall time of
up to 10 ns without triggering a fail-safe state. For speed applica-
tions with restricting data rates less than 30 Mbps, where slow
high to low transitions in excess of this limit are expected, use
external biasing resistors to introduce a minimum |VID| of
100 mV if the fail-safe cannot trigger.
Table 16. ADN4654 Input and Output Operation
Input (DINx±) Output (DOUTx±)
Powered On VID (mV) Logic Powered On VOD (mV) Logic
Yes ≥100 High Yes ≥250 High
Yes ≤−100 Low Yes ≤−250 Low
Yes −100 < VID < +100 Indeterminate Yes Indeterminate Indeterminate
No Don’t care Don’t care Yes ≥250 High
Table 17. ADN4655/ADN4656 Input and Output Operation
Input (DINx±) Output (DOUTx±)
Powered On VID (mV) Logic Powered On VOD (mV) Logic
Yes ≥100 High Yes ≥250 High
Yes ≤−100 Low Yes ≤−250 Low
Yes −100 < VID < +100 Indeterminate Yes ≥250 High
No Don’t care Don’t care Yes ≥250 High
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 19 of 25
ISOLATION
In response to any change in the input state detected by the
integrated LVDS receiver, an encoder circuit sends narrow (~1 ns)
pulses to a decoder circuit using integrated transformer coils.
The decoder is bistable and is, therefore, either set or reset by
the pulses that indicate input transitions. The decoder state
determines the LVDS driver output state in normal operation,
which reflects the isolated LVDS buffer input state.
In the absence of input transitions for more than approximately
1 µs, a periodic set of refresh pulses, indicative of the correct input
state, ensures dc correctness at the output (including the fail-safe
output state, if applicable).
On power-up, the output state may initially be in the incorrect
dc state if there are no input transitions. The output state is
corrected within 1 µs by the refresh pulses.
If the decoder receives no internal pulses for more than
approximately 1 µs, the device assumes that the input side is
unpowered or nonfunctional, in which case, the output is set to
a positive differential voltage (logic high).
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 20 of 25
APPLICATIONS INFORMATION
PCB LAYOUT
The ADN4654/ADN4655/ADN4656 can operate with high
speed LVDS signals up to 0.55 GHz clock, or 1.1 Gbps nonreturn to
zero (NRZ) data. When operating with such high frequencies,
apply best practices for the LVDS trace layout and termination.
Place a 100 Ω termination resistor as close as possible to the
receiver, across the DINx+ and DINx− pins.
Controlled 50 Ω impedance traces are needed on LVDS signal
lines for full signal integrity, reduced system jitter, and minimizing
electromagnetic interference (EMI) from the PCB. Trace widths,
lateral distance within each pair, and distance to the ground plane
underneath all must be chosen appropriately. Via fencing to the
PCB ground between pairs is also a best practice to minimize
crosstalk between adjacent pairs.
The ADN4654/ADN4655/ADN4656 pass EN 55022 Class B
emissions limits without extra considerations required for the
isolator when operating with up to 1.1 Gbps PRBS data. When
isolating high speed clocks (for example, 0.55 GHz), a reduced
PCB clearance (isolation gap) may be required with the 20-lead
SOIC_W model to reduce dipole antenna effects and provide
sufficient margin below Class B emissions limits.
The best practice for high speed PCB design avoids any other
emissions from PCBs in applications that use the ADN4654/
ADN4655/ADN4656. Take care when configuring off-board
connections, where switching transients from high speed LVDS
signals (clocks in particular) can conduct onto cabling, resulting
in radiated emissions. Use common-mode chokes, ferrites, or
other filters as appropriate at the LVDS connectors, as well as
cable shield or PCB ground connections to earth or chassis.
The ADN4654/ADN4655/ADN4656 require appropriate
decoupling of the VDDx pins with 100 nF capacitors. If the
integrated LDO regulator is not used, and a 2.5 V supply is
connected directly, connect the appropriate VINx pin to the supply
as well, as shown in Figure 40, using the ADN4654 as an
example.
1
2
3
4
20
19
18
17
516
615
714
813
9
V
DD2
12
10 11
100n
F
100n
F
100nF 100nF
V
DD1
V
IN2
V
DD2
V
DD1
100Ω
GND
1
V
IN1
GND
1
GND
2
GND
1
GND
2
GND
2
D
IN1+
D
IN1–
D
IN2+
D
IN2–
D
OUT2–
D
OUT2+
D
OUT1–
D
OUT1+
ADN4654
TOP VIEW
(Not to Scale)
100Ω
17011-033
Figure 40. Required PCB Layout When Not Using LDO Regulator (2.5 V Supply)
When the integrated LDO regulator is used, bypass capacitors
of 1 µF are required on the VINx pins and on the nearest VDDx
pins (LDO output), as shown in Figure 41.
1
2
3
4
20
19
18
17
516
615
714
813
9
V
DD2
12
10 11
100n
F
100n
F
100nF 100nF
V
DD1
V
IN2
V
DD2
V
DD1
100Ω
GND
1
V
IN1
GND
1
GND
2
GND
1
GND
2
GND
2
D
IN1+
D
IN1–
D
IN2+
D
IN2–
D
OUT2–
D
OUT2+
D
OUT1–
D
OUT1+
ADN4654
TOP VIEW
(Not to Scale)
100Ω
1µF1µF 1µF 1µF
17011-034
Figure 41. Required PCB Layout When Using LDO Regulator (3.3 V Supply)
APPLICATION EXAMPLES
High speed LVDS interfaces for the analog front-end (AFE),
processor to processor communication, or video and imaging data
can be isolated using the ADN4654, as an example, between
components, between boards, or at a cable interface. The ADN4654
provides the galvanic isolation required for robust external ports,
and the low jitter and high drive strength of the device allow
communication along short cable runs of a few meters. High
common-mode immunity ensures communication integrity
even in harsh, noisy environments, and isolation can protect
against electromagnetic compatibility (EMC) transients up to
±8 kV peak, such as ESD, electrical fast transient (EFT), and
surge. The ADN4654 can isolate a range of video and imaging
protocols, including protocols that use current mode logic
(CML) rather than LVDS for the physical layer. One example is
High-Definition Multimedia Interface (HDMI), where
ac coupling and biasing and termination resistor networks are
used as shown in Figure 42 to convert between CML (used by
the transition minimized differential signaling (TMDS) data
and clock lanes) and the LVDS levels required by the ADN4654.
Additional Analog Devices isolator components, such as the
ADuM1250/ADuM1251 I2C isolators, can be used to isolate
control signals and power (ADuM5020 isoPower integrated,
isolated dc-to-dc converter). This circuit supports resolutions
up to 720p.
Other circuits can use the ADN4654 for isolating MIPI CSI-2,
DisplayPort, and LVDS-based protocols such as FPD-Link. Use
of a field-programmable gate array (FPGA) or an application-
specific integrated circuit (ASIC) serializer/deserializer (SERDES)
expands bandwidth through multiple ADN4654 devices to
support 1080p or 4K video resolutions, providing an alternative
to short reach fiber links.
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 21 of 25
ADN4654 (×2)
ISOLATIONISOLATION
NOTES
1. SUPPLY BIASED TERMINATION
2. AC COUPLING
3. COMMON-MODE BIASING
4. DIFFERENTIAL TERMINATION
TMDS D0+
TMDS D0–
SDA
SCK
CEC
HPD
+5V
SDA
SCK
CEC
HPD
TMDS D1+
TMDS D1–
TMDS D2+
TMDS D2–
TMDS CLK+
TMDS CLK–
TMDS D0+
TMDS D0–
TMDS D1+
TMDS D1–
TMDS D2+
TMDS D2–
TMDS CLK+
TMDS CLK–
TERMINATION, AC COUPLING,
AND BIASING NETWORKS
1
1
2
2
3
4
TVS NETWORK, CONNECTORS,
CABLE, AND BIASING NETWORKS
TVS NETWORK,
CONNECTORS,
AND CABLE
HDMI SINK
HDMI SOURCE
ADuM1250
ADuM1251
ADuM5020 (×2)
OSC REC
REG VISO (3.3V)
SUPPLY FOR ISOLATORS
VDDP
OSC REC
REG
VISO (5V, 100mA)
VDDP
17011-038
Figure 42. Example Isolated Video Interface (HDMI) Using the ADN4654
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 22 of 25
MAGNETIC FIELD IMMUNITY
The limitation on the magnetic field immunity of the device is
set by the condition in which the induced voltage in the trans-
former receiving coil is sufficiently large, either to falsely set or
reset the decoder. The following analysis defines such conditions.
The ADN4654/ADN4655/ADN4656 are examined in a 2.375 V
operating condition because this operating condition represents
the most susceptible mode of operation for these products.
The pulses at the transformer output have an amplitude greater
than 0.5 V. The decoder has a sensing threshold of about 0.25 V,
therefore establishing a 0.25 V margin in which induced voltages
are tolerated. The voltage (V) induced across the receiving coil
is given by
V = (−dβ/dt)∑πrn2; n = 1, 2, …, N
where:
dβ is the change in magnetic flux density.
dt is the change in time.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADN4654/
ADN4655/ADN4656 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.25 V margin at the
decoder, a maximum allowable external magnetic flux density is
calculated as shown in Figure 43.
MAGNETIC FIELD FREQUENCY (Hz)
1k
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
17011-035
Figure 43. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.92 kgauss induces a
voltage of 0.125 V at the receiving coil. This voltage is about
50% of the sensing threshold and does not cause a faulty output
transition. If such an event occurs with the worst case polarity
during a transmitted pulse, the applied magnetic field reduces
the received pulse from >0.5 V to 0.375 V. This voltage is still
higher than the 0.25 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADN4654/
ADN4655/ADN4656 transformers. Figure 44 expresses these
allowable current magnitudes as a function of frequency for
selected distances. The ADN4654/ADN4655/ADN4656 are
insensitive to external fields. Only extremely large, high frequency
currents that are close to the component can potentially be a
concern. For the 1 MHz example noted, a 2.29 kA current must be
placed 5 mm from the ADN4654/ADN4655/ADN4656 to affect
component operation.
MAGNETIC FIELD FREQUENCY (Hz)
10k
1k
100
MAXIMUM ALLOWABLE CURRENT (kA)
0.01
1M
10
1k 10k 10M
0.1
1
100M100k
DISTANCE = 1m
DISTANCE = 100mm
DISTANCE = 5mm
17011-036
Figure 44. Maximum Allowable Current for Various Current to ADN4654
Spacings
In combinations of strong magnetic field and high frequency,
any loops formed by PCB traces can induce sufficiently large
error voltages to trigger the thresholds of succeeding circuitry.
Avoid PCB structures that form loops.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation as well as on
the materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components, which allows the components to
be categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation barrier, pollution degree, and material group. The
material group and creepage for ADN4654/ADN4655/ADN4656
are detailed in Table 4 and Table 5.
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 23 of 25
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
the thickness of the insulation, material properties, and the voltage
stress applied. It is important to verify that the product lifetime
is adequate at the application working voltage. The working
voltage supported by an isolator for wear out may not be the
same as the working voltage supported for tracking. The working
voltage applicable to tracking is specified in most standards.
Testing and modeling show that the primary driver of long-term
degradation is displacement current in the polyimide insulation
causing incremental damage. The stress on the insulation can be
broken down into broad categories, such as dc stress, which causes
little wear out because there is no displacement current, and an
ac component time varying voltage stress, which causes wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this type of waveform reflects
isolation from line voltage. However, many practical applications
have combinations of 60 Hz ac and dc across the isolation barrier,
as shown in Equation 1. Because only the ac portion of the
stress causes wear out, the equation can be rearranged to solve
for the ac rms voltage, as shown in Equation 2. For insulation
wear out with the polyimide materials used in this product, the
ac rms voltage determines the product lifetime.
22
DCRMSACRMS VVV (1)
or
22
DCRMSRMSAC VVV (2)
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 45 and
the following equations.
The working voltage across the barrier from Equation 1 is
22
DCRMSACRMS VVV
22 400240
RMS
V
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
22
DCRMSRMSAC VVV
22 400466
RMSAC
V
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. Table 12 compares the value to the limits for the
working voltage for the expected lifetime. Note that the dc
working voltage limit in Table 12 is set by the creepage of the
package as specified in IEC 60664-1. This value can differ for
specific system level standards.
ISO
L
A
TION V
O
LTAGE
TIME
V
AC RMS
V
RMS
V
DC
V
PEAK
17011-037
Figure 45. Critical Voltage Example
ADN4654/ADN4655/ADN4656 Data Sheet
Rev. D | Page 24 of 25
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-150-AE
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
COPLANARITY
0.10
PKG-004600
06-01-2006-A
TOP VIEW
SIDE VIEW END VIEW
PIN 1
INDICATOR
SEATING
PLANE
Figure 46. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
20 11
10
1
1.27
(0.0500)
BSC
06-07-2006-A
Figure 47. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
Data Sheet ADN4654/ADN4655/ADN4656
Rev. D | Page 25 of 25
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADN4654BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4654BRSZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4654BRWZ −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4654BRWZ-RL7 −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4655BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4655BRSZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4655BRWZ −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4655BRWZ-RL7 −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4656BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4656BRSZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4656BRWZ −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4656BRWZ-RL7 −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20
EVAL-ADN4654EBZ ADN4654 SSOP Evaluation Board
EVAL-ADN4654EB1Z ADN4654 SOIC_W Evaluation Board
EVAL-ADN4655EBZ ADN4655 SSOP Evaluation Board
EVAL-ADN4655EB1Z ADN4655 SOIC_W Evaluation Board
EVAL-ADN4656EBZ ADN4656 SSOP Evaluation Board
EVAL-ADN4656EB1Z ADN4656 SOIC_W Evaluation Board
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
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registered trademarks are the property of their respective owners.
D17011-0-9/19(D)
