DSPIC30F2010-20E/MMG - Microchip Technology

dsPIC30F2010

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

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Trademarks

The Microchip name and logo, the Microchip logo, Accur on,

dsPIC, KEELOQ, micro ID, MPLAB, PIC , PIC, PIC START,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MX DEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

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intended manner and under normal conditions.

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mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h a c t s

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dsPIC30F2010

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized in struction set architecture

• 83 base instructions wit h flexible addressing

modes

• 24-bit wide instructions, 16-bit wide data path

• 12 Kbytes on -chip Flash p rogr am spac e

• 512 bytes on-chip data RAM

• 1 Kbyte nonvolatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPs operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with

PLL active (4x, 8x, 16x)

• 27 interrupt sources

• Three external interrupt sources

• 8 user-selectable priority levels for each interrupt

• 4 processor exceptions and software traps

DSP Engine Features:

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturati on log ic

• 17-bit x 17-bit si ngl e-cyc le hard w are frac tio nal /

integer multiplier

• Single-cycle Multiply-Accumulate (MAC)

operation

• 40-stage Barrel Shifter

• Dual data fetch

Peripheral Feat ures:

• High current sink/source I/O pins: 25 mA/25 mA

• Three 16-bit timers/counters; optionally pair up

16-bit timers into 32-bit timer modules

• Four 16-bit capture input functions

• Two 16-bit compare/PWM output functions

- Dual Compare mode available

• 3-wire SPI modules (supports 4 Frame modes)

•I

2CTM module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Addressable UART modules with FIFO buffers

Motor Control PWM Module Features:

• 6 PWM output channels

- Complement ary or Indepe ndent Outpu t

modes

- Edge and Center-Aligned modes

• 4 duty cycle generators

• Dedicated time base with 4 modes

• Programmable output polarity

• Dead-time control for Complementary mode

• Manual output control

• Trigger for sync hron iz ed A/D conv ers ion s

Quadrature Encoder Interface Module

Features:

• Phase A, Phase B and Index Puls e input

• 16-bit up/down position counter

• Count direction status

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Interrupt on position counter roll over/underflow

Analog Features:

• 10-bit Analog-to-Digital Converter (ADC) with:

- 1 Msps (for 10-bit A/D) conversion rate

- Six input channels

- Conversion available during Sleep and Idle

• Programmable Brown-out Reset

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

28-Pin dsPIC30F2010 Enhanced Flash

16-Bit Digital Signal Controller

dsPIC30F2010

Special Digital Signal Controller

Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T )

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low-

power RC oscillator for reliable operation

• Fail-Safe clock monitor operation

• Detects clock failure and switches to on-chip low-

power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

programming capabil ity

• Selectable Power Ma nag em ent mo des

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

dsPIC30F Motor Control and Powe r Conversion Family*

Device Pins Program

Mem. Bytes/

Instructions

SRAM

Bytes EEPROM

Bytes Timer

16-bit Input

Cap

Output

Comp/Std

PWM

Motor

Control

PWM

A/D 10-bit

1 Msps Quad

Enc

UART

SPI

I2CTM

CAN

dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 –

dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Yes 1 1 1 –

dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Yes 1 1 1 1

dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Yes 2 1 1 –

dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Yes 2 1 1 1

dsPIC30F5015 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1

dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2

dsPIC30F6010A 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2

* This t abl e provi des a summ ary of the ds PIC30F20 10 peri pheral feat ures. Oth er avai lable devic es in the ds PIC30F

Motor Control and Power Conversion Family are shown for feature comparison.

dsPIC30F2010

Pin Diagrams

MCLR

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5VSS

VDD

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AVDD

AVSS

AN2/SS1/LVDIN/CN4/RB2

EMUD2/OC2/IC2/INT2/RD1 EMUC2/OC1/IC1/INT1/RD0

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 VSSOSC2/CLKO/RC15

OSC1/CLKI VDD

FLTA/INT0/SCK1/OCFA/RE8

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

AN5/QEB/IC8/CN7/RB5

AN4/QEA/IC7/CN6/RB4

AN3/INDX/CN5/RB3

28-Pin SDIP and SOIC

dsPIC30F2010

28-Pin QFN

dsPIC30F2010

716

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

AVDD

AVSS

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

VDD

VSS

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

FLTA/INT0/SCK1/OCFA/RE8

EMUC2/OC1/IC1/INT1/RD0

MCLR

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF- /CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/INDX/CN5 RB3

AN4/QEA/IC7/CN6/RB4

AN5/QEB/IC8/CN7/RB5

VSS

OSC1/CLKI

OSC2/CLKO/RC15

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

EMUD2/OC2/IC2/INT2/RD1 10

dsPIC30F2010
DS70118G-page 4 © 2006 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 CPU Architecture Overview.......................................................................................................................................................... 9
3.0 Memory O rganization................................................................................................................................................................. 19
4.0 Address Generato r Units............................................................................................................................................................ 31
5.0 Interrupts.................................................................................................................................................................................... 37
6.0 Flash Pro g ram Memory....... ..................... ..................... ........................... ............................ ...................................................... 43
7.0 Data EEPR OM Mem o ry.... ............... ........................... ........................... ........................... ......................................................... 49
8.0 I/O Ports . ........................... ........................... ........................... ............................ ....................................................................... 53
9.0 Timer1 Module ........................................................................................................................................................................... 57
10.0 Timer2/3 Module ............... .. .. .... .. .. ..... .... .. .. .. .. .... ..... .. .. .... .. .. .. .. ....... .. .. .. .... .. .. ....... .. .. .. .. ............................................................... 61
11.0 Input Capture Module.............. .... .. ....... .. .. .... .. .. ....... .. .... .. .. .... .. ....... .. .. .... .. .. ....... .. .... .. .. .... ........................................................... 67
12.0 Output Compa re Module............. ............................ ..................... ........................... ............. ...................................................... 71
13.0 Quadrature Encoder Interface (QEI ) Module ............................................................................................................................. 75
14.0 Mot or Control PWM Module....................................................................................................................................................... 81
15.0 SP I Module................................................................................................................................................................................. 91
16.0 I2C Module................................................................................................................................................................................. 95
17.0 U nivers al Asynchr onous Receiver  Transmi tter (UART) Module .............................................................................................. 103
18.0 10-bit High-Speed Analog-to-Digital Converter (ADC) Module .......... .... .... .. ......... .. .... .... .. ......... .... .. .... .................................... 111
19.0 System Inte g r a tion ........ ..................... ..................... ........................... ..................... ................................................................. 123
20.0 Instruction Set Summary.......................................................................................................................................................... 137
21.0 Development Support............................................................................................................................................................... 145
22.0 Electrical Characteristics.......................................................................................................................................................... 149
23.0 Packagin g  In fo r mation................. ............................ ..................... ..................... ....................................................................... 187
The Micro chip Web Site...................... ............................ ................................. .................................................................................. 199
Customer Change Notification Service ........................ ............... ...... ............. ...... ............... ...... ......................................................... 199
Customer Support.......... ............. ...... .... ............. ...... .... ............. ...... ............. ...... .... ............................................................................ 199
Reader Response.............................................................................................................................................................................. 200
Product Identification System............................................................................................................................................................. 201
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dsPIC30F2010

1.0 DEVICE OVERVIEW This document contains device specific information for

the dsPIC30F2010 device. The dsPIC30F devices

contain extensive Digital Signal Processor (DSP) func-

tionality within a high-performance 16-bit microcontroller

(MCU) architecture. Figure 1-1 shows a device block

diagram for the dsPIC30F2010 devi ce.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F2010

FIGU RE 1-1 : dsPI C30F 2010 BLO CK DI AGRAM

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

AN4/QEA/IC7/CN6/RB4

UART1SPI1 Motor C ont rol

PWM

Timing

Generation

AN5/QEB/IC8/CN7/RB5

PCH PCL

Progr am Coun ter

ALU<16>

Address Latch

Prog ram Memory

(12 Kbytes)

Data Latch

X Data Bus

I2C™

QEI

PCU

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

10-bit ADC

Timers

PWM3H/RE5

FLTA/INT0/SCK1/OCFA/RE8

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC1

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

PORTB

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

PORTF

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/INDX/CN5/RB3

OSC2/CLKO/RC15

PORTC

PORTE

Interrupt

Controller

PSV & Table

Data Access

Control Bl ock

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(256 bytes )

RAM X Data

(256 bytes)

RAM

Address

Latch

Address

Latch

Control Signals

to Various Blocks

EMUC2/OC1/IC1/INT1/RD0

EMUD2/OC2/IC2/INT2/RD1

Data EE PROM

(1 Kbyt e)

dsPIC30F2010

Table 1-1 provides a brief description of device I/O

pinouts and the functions that may be multiplexed to a

port pin. Multiple functions may exist on one port pin.

When multiplexing occurs, the peripheral module’s

functional requirements may force an override of the

data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type Buffer

Type Description

AN0-AN5 I Analog Analog input channels.

AVDD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKI

CLKO I

OST/CMOS

—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always

associated with OSC2 pin function.

CN0-CN7 I ST Input change notification inputs.

Can be software programmed for internal weak pull-ups on all inputs.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

ICD Quaternary Communication Channel data input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

IC1, IC2, IC7,

IC8 I ST Capture inputs. The dsPIC30F2010 has 4 capture inputs. The inputs are

numbered for consistency with the inputs on larger device variants.

INDX

QEA

QEB

Quadratu re Enco der Inde x Puls e inpu t.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

INT0

INT1

INT2

External interrupt 0

External interrupt 1

External interrupt 2

FLTA

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

—

PWM Fault A input

PWM 1 Low output

PWM 1 High output

PWM 2 Low output

PWM 2 High output

PWM 3 Low output

PWM 3 High output

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-

low Reset to the device.

OCFA

OC1-OC2 I

OST

—Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compar e outputs.

OSC1

OSC2

I/O

ST/CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes.

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F2010

PGD

PGC I/O

IST

ST In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

RB0-RB5 I/O ST PORTB is a bidirectional I/O port.

RC13-RC14 I/O ST PORTC is a bidirectional I/O port.

RD0-RD1 I/O ST PORTD is a bidirectional I/O port.

RE0-RE5,

RE8 I/O ST PORTE is a bidirectional I/O port.

RF2, RF3 I/O ST PORTF is a bidirectional I/O port.

SCK1

SDI1

SDO1

SS1

I/O

—

Synchronous serial clock input/output for SPI #1.

SPI #1 Data In.

SPI #1 Data Out.

SPI #1 Slave Synchronization.

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/output for I2C™.

Synchronous serial data input/output for I2C.

SOSCO

SOSCI O

I—

ST/CMOS 32 kHz low-power oscillator crystal output.

32 kHz low-power oscillator crystal input. ST buffer when configured in RC

mode; CMOS otherwise.

T1CK

T2CK I

IST

ST Timer1 external clock input.

Timer2 external clock input.

U1RX

U1TX

U1ARX

U1ATX

—

UART1 Receive.

UART1 Transmit.

UART1 Alternate R ecei ve.

UART1 Alternate Transmit.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog Voltage Reference (High) input.

VREF- I Analog Analog Voltage Reference (Low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F2010

2.0 CPU ARCHITECTURE

OVERVIEW

This document provides a summary of the

dsPIC30F2010 CPU and peripheral function. For a

complete description of this functionality, please refer

to the “dsPIC30F Family Reference Manual”

(DS70046).

2.1 Core Overview

The core has a 24-bit instruction word. The Program

Counter (PC) is 23 bits wide with the Least Significant

bit (LSb) always clear (see Section 3.1 “Program

Address Space”), and the Most Significant bit (MSb)

is ign ored du ring no rmal program executi on, ex cept for

certain specialized instructions. Thus, the PC can

address up to 4M instruction words of user program

space. An instruction prefetch mechanism is used to

help maintain throughput. Program loop constructs,

free from loop count management overhead, are sup-

ported using the DO and REPEAT instructions, both of

which are interruptible at any point.

The working register array consists of 16x16-bit regis-

ters, each of which can act as data, address or offset

registers. One working register (W15) operates as a

software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2 “Data Address Space”). The X and Y

data space boundary is device specific and cannot be

alter ed by the user . Each dat a word consis ts of 2 bytes,

and mos t instruction s can address data eith er as words

or bytes.

There are two methods of accessing data stored in

program memory:

• The upper 32 Kbyte s of data sp ace memory can be

mapped into the low er half (user space) of pro gram

space at any 16K program word bound ary, defined

by the 8-bit Program Sp ace V is ibility Page

(PSVP AG) register . This lets any instruction access

program space as if it were da t a sp ace , with a lim i-

tation that the access requires an additional c ycle.

Moreover, only the lower 16 bit s o f each instruction

word can be acces sed usi ng this meth od.

• Linear indirect access of 32K word pages within

progra m spac e is also possibl e using any w orking

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing)

are supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports Bit-Reversed Addressing on

destination ef fective addresses, to greatly simplify input

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 “Address Generator Units” for

details on Modulo and Bit-Reversed Addressing.

The core s up ports Inherent (n o op era nd), Re lat iv e, Lit-

eral, Memory Direct, Register Direct, Register Indirect,

Instruct ions ar e associat ed with p redefined Addressin g

modes, depending upon their functional requirements.

For m os t i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3-operand instructions are supported, allowing

C = A + B operations to be executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capab ility and throughput.

It features a high-speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit b idi rec tio nal b arrel shifter. Dat a in th e a cc umul a-

tor or any worki ng r egist er can be shif ted up to 15 bits

right or 16 bits left in a single cycle. The DSP instruc-

tions ope rate sea mles sly with all other in struct ions an d

have be en desi gned for o ptimal re al-time p erforma nce.

The MAC class of instructions can concurrently fetch

two data operands from memory, while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space has been split for these

instructions and linear for all others. This has been

achieved in a transparent and flexible manner, by

dedicating certain working registers to each address

spac e for the MAC class of instructions.

The core does not support a multi-stage instruction

pipeline. However, a single stage instruction prefetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle, with certain

exceptions.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are res erv ed ) an d 54 interrupts . Eac h in terru pt

is prioritized based on a user-assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest) in conjunction with a predetermined ‘natural

order’. T raps hav e fixed prio rities, rangi ng from 8 to 15.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F2010

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16x16-bit working registers (W0 through

W15), 2x40-bit accumulators (ACCA and ACCB),

STATUS Register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT) and Program

Counter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Some of these registers have a shadow register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary h olding register

and can tr ansfer its con tents to or fro m i t s hos t reg is ter

upon the occurrence of an event. None of the shadow

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

•PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

•DO instruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start, and popped on loop end.

When a byte operation is performed on a working reg-

ister, only the L eas t S ign ifi can t By te of t he target regi s-

ter is affected. However, a benefit of memory mapped

working registers is that both the Least and Most Sig-

nificant Bytes can be manipulated through byte wide

data m emory space accesses .

2.2.1 SOFTWARE STACK POINTER/

FRAM E POIN TE R

The dsPIC® DSC devices contain a software stack.

W15 is the dedicated software Stack Pointer (SP), and

will be automatically modified by exception processing

and sub routine calls and return s. However , W15 can be

referenced by any instruction in the same manner as all

other W registers. This simplifies the reading, writing

and manipulation of the Stack Pointer (e.g., creating

stac k fram es ).

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a Stack Frame Pointer as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS Register

(SR), the LSB of which is referred to as the SR Low

Byte (SRL) and the MSB as the SR High Byte (SRH).

See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags

(includ ing the Z bit ), as well as the CPU Inter rupt Prior-

ity Level status bits, IPL<2:0>, and the REPEAT active

status bit, RA. During exception processing, SRL is

concate na ted with the MSB of the PC to form a

complete word value which is then stacked.

The upper byte of the STATUS register contains the

DSP adder/subtracter status bits, the DO Loop Active

bit (DA) and the Digit Carry (DC) status bit.

2.2.3 PROGRAM COUNTER

The Program Counter is 23 bits wide. Bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

dsPIC30F2010

FIGURE 2-1 : PRO GRAMMER’ S MOD EL

TABPAG

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand

Registers

W10

W11

W12/DSP Offset

W13/DSP Write-Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address

Registers

AD39 AD0AD31

DSP

Accumulators ACCA

ACCB

PSVPAG

7 0Program Space Visibility Page Address

OA OB SA SB

RCOUNT

15 0

REPEAT Loop Counter

DCOUNT

15 0

DO Loop Counter

DOSTART

22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0 Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

dsPIC30F2010

2.3 Divide Suppor t

The dsPIC DSC devices feature a 16/16-bit signed

fraction al d iv ide ope rati on , as w ell as 32/1 6-b it a nd 1 6/

16-bit signed and unsigned integer divide operations, in

the form of single instruction iterative divides. The fol-

lowing instructions and data sizes are supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.sw – 16/16 signed divide

5. DIV.uw – 16/16 unsigned divide

The 16/16 divides are simila r to the 32/16 (same number

of iterations), but the dividend is eithe r zero-extended or

sign-extended during the first iteration.

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g. a series

of disc rete div ide ins tructions) will not function correctl y

because the instruction flow depends on RCOUNT.

The divi de instru ction does not autom aticall y set up th e

RCOUNT value, and it must, therefore, be explicitly

and correctly specified in the REPEAT instruction, as

shown in Table 2-1 (REPEAT will execute the target

instruction {operand value + 1} times). The REPEAT

loop coun t mus t be se t up for 18 ite rati ons of the DIV/

DIVF instruction. Thus, a complete divide operation

requires 19 cycles.

TABLE 2-1: DIVIDE INSTRUCTIONS

Note: The Divide flow is interruptible. However,

the user needs to save the context as

appropriate.

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1

DIV.sw (or DIV.s) Signed divide: Wm/Wn → W0; Rem → W1

DIV.uw (or DIV.u) Unsigned divide: Wm/Wn → W0; Rem → W1

dsPIC30F2010

2.4 DSP Engine

The DSP engine consists of a high-speed 17-bit x

17-bit mu ltiplier , a barrel shifter , and a 40-bit adde r/sub-

tracter (with two target accumulators, round and

saturati on log ic ).

The DSP engine also has the capability to perform inher-

ent accumulator-to-accumulator operations, which

require no additional data. These instructions are ADD,

SUB and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration Register

(CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for ACCA (SATA).

5. Automatic saturation on/off for ACCB (SATB).

6. Automatic saturation on/off for writes to data

memory (SATDW).

7. Accumulator Saturation mode selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

Note: For CORCON layout, see Table 3-3.

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)2No

EDAC A = A + (x – y)2No

MAC A = A + (x * y) Yes

MAC A = A + x2No

MOVSAC No change in A Yes

MPY A = x * y No

MPY.N A = – x * y No

MSC A = A – x * y Yes

dsPIC30F2010

FIGU RE 2-2: DSP E NGI NE BLO CK DI AGRA M

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumulator A

40-bit Accumulator B Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

16 16

40 40

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

dsPIC30F2010

2.4.1 MULTIPLIER

The 17x17-bit multiplier is capable of signed or

unsign ed ope ration an d can m ultiplex its output u sing a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. Unsigned operands are zero-extended

into the 17th bit of the multiplier input value. Signed

operands are sign-exten ded into the 17th bit of the mul-

tiplier input value. The output of the 17x17-bit multiplier/

scaler is a 33-bit value, which is sign-extended to 40

bits. Integer data is inheren tly represented as a s igned

two’s complement value, where the MSB is defined as

a sign bit. Generally speaking, the range of an N-bit

two’s complement integer is -2N-1 to 2N-1 – 1. For a 16-

bit integ er, the dat a ran ge i s -3276 8 (0x 800 0) to 3276 7

(0x7FFF), including 0. For a 32-bit integer, the data

range is -2,147,483,648 (0x8000 0000) to

2,147,48 3,6 45 (0x7FFF FFFF).

When the multiplier is configured for fractional multipli-

cation, the data is represented as a two’s complement

fraction , where the M SB is define d as a sign b it and the

radix po int is im plied to lie just a fter the si gn bit (QX f or-

mat). The range of an N-bit two’s complement fraction

with this implied radix point is -1.0 to (1-21-N). For a

16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF), including ‘0’ and has a preci-

sion of 3 .01518 x10-5. In F ractional mode, a 16x 16 mul-

tiply operation generates a 1.31 product, which has a

precision of 4.65661x10-10.

The same multiplier is used to support the MCU multi-

ply instructions, which include integer 16-bit signed,

unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or

word-size d operands . Byte operan ds will dire ct a 16-bit

result, and word operands will direct a 32-bit result to

the specified register(s) in the W array.

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/sub-

tracter wi th automatic si gn extension logi c. It can select

one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADD and LAC instructions, the data to be

accum ulated or l oaded ca n be optio nally sca led via th e

barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and

Saturation

The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true or complement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtrac tion, the carry/borrow input is active low and the

other input is complemented. The adder/subtracter

generates overflow status bits SA/SB and OA/OB,

which are latched and reflected in the STATUS

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all

the guard bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation, if selected. It

uses the result of the adder, the overflow status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

Six STATUS register bits have been provided to

support saturation and overflow; they are:

1. OA:

ACCA overflowed into guard bits

2. OB:

ACCB overflowed into guard bits

3. SA:

ACCA saturated (bit 31 overflo w and saturatio n)

ACCA overflowed into guard bits and saturated

(bit 39 over flow and saturation)

4. SB:

ACCB saturated (bit 31 overflo w and saturatio n)

ACCB overflowed into guard bits and saturated

(bit 39 over flow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing overflow trap flag enable bit (OVATE, OVBTE) in

the INTCON1 register (refer to Section 5.0 “Inter-

rupts”) is set. This allows the user to take immediate

action, for example, to correct system gain.

dsPIC30F2010

The SA and SB bit s are modified each time da ta passes

through the adder/subtracter, but can only be cleared by

the user. When set, they indicate that the accumulator

has overflowed its maximum range (bit 31 for 32 -bit sat-

uration, or bit 39 for 40-bit saturation) and will be satu-

rated (if saturation is enabled). When saturation is not

enabled, SA and SB default to bit 39 overflow and thus

indicate that a cat astrophic overfl ow has occurred. If the

COVTE bit in the INTCON1 register is set, SA and SB

bits wil l generate an arithmetic w arning trap when

saturation is disabled .

The overflow and saturation status bits can optionally

be view ed in the S tat us Register (SR) as the logi cal OR

of OA and OB (in bit OAB), and the logical OR of SA

and SB (in bit SAB). Th is allows programm ers to check

one bit in the STATUS register to determine if either

accumulator has overflowed, or one bit to determine if

either a ccum ulator has satu rated. T his w ould be usefu l

for complex number arithmetic which typically uses

both the accu mulators.

The device supports three Saturation and Overflow

modes.

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic load s the maximally positive 9.31

(0x7FFFFFFFFF) or maximally negative 9.31

value (0x8000000000) into the target accumula-

tor. The SA or SB bit is set and remains set until

cleared by the user. This is referred to as ‘super

saturation’ and provides protection against erro-

neous data or unexpected algorithm problems

(e.g., gain calculations).

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then load s the maximally positive

1.31 value (0x007FFFFFFF) or maximally nega-

tive 1.31 value (0x0080000000) into the target

accumulator. The SA or SB bit is set and remains

set until cleared by the user . When this Saturation

mode is in effect, the guard bits are not used (so

the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow

The bit 39 overflow status bit from the adder is

used to set the SA or SB bit, which remain set

until cleared by the user. No saturation operation

is performed and the accumulator is allowed to

overflow (destroying its sign). If the COVTE bit in

the INTCON1 register is set, a catastrophic

ove rflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write-Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the acc umulator that is not t argeted by the instruction

into dat a spac e memory. The write is performe d across

the X bus into combined X and Y address space. The

following addressing modes are supported:

1. W13, Registe r Dire ct:

The rounded contents of the non-target

accumulator are written into W13 as a 1.15

fraction.

2. [W13]+=2, Register Indirect with Post-Increment:

The round ed contents of the non- target accumu-

lator are written into the address pointed to by

W13 as a 1.15 fraction. W13 is then

incremented by 2 (fo r a wo rd wr ite).

2.4.2.3 Round Logic

The round logic is a combinational block, which per-

forms a conventional (biased) or convergent (unbiased)

round function during an accumulator write (store). The

Round mode is det ermined by the state of the RND bit

in the CORCON register. It generates a 16-bit, 1.15 data

value which is passed to the data space write saturation

logic. If rounding is not indicated by the instruction, a

truncated 1.15 data value is stored and the least

significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and ad ds it to the AC CxH word (bi t s 16

through 31 of the accumulator). If the ACCxL wo rd (bits

0 through 15 of the accumulator) is between 0x8000

and 0xFFFF (0x8000 included), ACCxH is incre-

mented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left unchanged. A consequence of this

algorith m is that over a su ccessio n of random roun ding

operations, the value will tend to be biased slightly

positive.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equals 0x8000 . If this is the case, the Least Sig-

nificant bit (bit 16 of the accumulator) of ACCxH is

examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,

ACCxH is not modified. Assuming that bit 16 is effec-

tively random in nature, this scheme will remove any

rounding bias that may accumulate.

The SAC and SAC.R instructions store either a trun-

cated (SAC) or rounded (SAC.R) version of the cont ents

of the t arget accumul ator to data mem ory , via the X bu s

(subject to data saturation, see Section 2.4.2.4 “Data

Space Write Saturation”). Note that for the MAC cl as s

of instructions, the accumulator write-back operation

will fu nction in t he same ma nner , a ddressing combine d

MCU (X and Y) data space though the X bus. For this

class of instructions, the data is always subject to

rounding.

dsPIC30F2010

2.4.2.4 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data

space may also be saturated, but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15 frac-

tional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combin ed and used t o sele ct the a ppropri ate 1.1 5 frac-

tional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data

(after roundi ng or trun ca tio n) is tes te d for ove rflo w and

adjusted accordingly. For input data greater than

0x007FF F, dat a written to me mory is forced to the max-

imum posit ive 1. 15 val ue, 0x7FFF. F or inp ut da ta less

than 0x FF8000, dat a wri tten to memo ry is f orced to the

maximum negative 1.15 value, 0x8000. The Most Sig-

nificant bit of the source (bit 39) is used to determine

the sign of the operand being tested.

If the SATDW bit in the CORCON register is n ot set, the

input data is always passed through unmodified under

all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 15-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators or the X bus (to support multi-bit

shifts of register or memory data).

The sh ifter requires a s ign ed bi nary v al ue to de term in e

both the m agnitude (number of bits) and direction of the

shift operation. A positive value will shift the operand

right. A negative value will shift the operand left. A

value of 0 will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit res ult for DSP shift ope rations an d a 16-bit resu lt

for MCU shift operations. Data from the X bus is pre-

sented to the barrel shifter between bit positions 16 to

31 for right sh ifts, and bit positio ns 0 to 15 for left sh ifts.

dsPIC30F2010

NOTES:

dsPIC30F2010

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit

PC, table instruction Effective Address (EA), or data

space EA, when program space is mapped into data

space, as defined by Table 3-1. Note that the program

spa ce add ress i s increm ented b y tw o betwee n suc ces-

sive program words, in order to provide compatibility

with data space addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) , for all access es other than TBLRD/TBLWT,

which use TBLPAG<7> to dete rmine user or c onfigura-

tion space access. In Table 3-1, Read/Write instruc-

tions, b it 23 allows a ccess to the Devic e ID, the User ID

and the Configuration bits. Otherwise, bit 23 is always

clear.

FIGURE 3-1:

PROGRAM SPACE MEMORY

MAP F OR dsPIC 30F20 10

Note: This data sheet summarizes features of this

group of dsPIC30F de vice s and is n ot inte nded to b e

a complete reference source. For more information

on the CPU, peripherals, register descriptions and

general device functionality, refer to the “dsPIC30F

Family Reference Manual” (DS70046). For more

information on the device instruction set and pro-

grammi ng, refe r to the “dsPIC30F/33F

Programmer’s Reference Manual” (DS70157).

Note: The address map shown in Figure 3-1 is

conceptual, and the actual memory con-

figuration may vary across individual

devices depending on available memory.

Reset - Target Address

User Memory

Space

000000

7FFFFE

00007E

Ext. Osc. Fail Trap

000002

000080

User Flash

Progra m Mem ory

002000

001FFE

Data EEPROM

Address Error Trap

Stack Error Trap

Arithmetic Warn. Trap

Reserved

Vector 0

Vector 1

Vector 52

Vector 53

(4K instructions)

(1 Kbyte)

Reserved

7FFC00

7FFBFE

(Read 0’s)

0000FE

000100

000014

Al terna te Vector Table

Reset - GOTO Instruction

000004

Reserved

Device Configuration

Configuration Memory

Space

800000

F80000

Registers F8000E

F80010

DEVID (2) FEFFFE

FF0000

FFFFFE

Reserved F7FFFE

8005FE

800600

UNITID (32 instr.)

8005BE

8005C0

Reserved

Vector Tables

dsPIC30F2010

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Access Type Access

Space Program Spac e Address

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0 PC<22:1> 0

TBLRD/TBLWT User

(TBLPAG<7> = 0)TBLPAG<7:0> Data EA <15:0>

TBLRD/TBLWT Configuration

(TBLPAG<7> = 1)TBLPAG<7:0> Data EA <15:0>

Program Space Visibility User 0 PSVPAG<7:0> Data EA <14:0>

0Program Counter

23 bits

PSVPAG Reg

8 bits

15 bits

Program

Using

Select

TBLPAG Reg

8 bits

16 bits

Using

Byte

24-bit EA

1/0

Select

User/

Configuration

Table

Instruction

Program

Space

Counter

Using

Space

Select

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.

Visibility

dsPIC30F2010

3.1.1 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

This arc hit ec ture f etc hes 24 -bi t w ide prog ram me mo ry.

Consequently, instructions are always aligned. How-

ever, as the architecture is modified Harvard, data can

also be present in prog ram space.

There are two methods by which program space can

be accessed: via special table instructions, or through

the rema ppi ng of a 16K w ord prog ram space page into

the u pp e r half o f da ta space (s ee Section 3.1.2 “Data

Access from Program Memory Using Program

Space Visibility”). The TBLRDL and TBLWTL instruc-

tions offer a direct method of reading or writing the lsw

of any address within program space, without going

through da ta spac e. The TBLRDH and TBLWTH instru c-

tions are th e only metho d whereby the upp er 8 bits of a

program space word can be accessed as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide add res s s p ac es , res id ing sid e by si de, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDH and TBLWTH ac cess the sp ac e

which contains the Most Significant data Byte.

Figure 3-2 shows h ow th e EA is cre ate d for table op er-

ations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

A set of Table Instruct ions are provided to mo ve byte or

wor d-sized data to and from program space.

1. TBLRDL: Table Read Low

Word: Read the least significant word of the

program address;

P<15:0> maps to D<15:0>.

Byte: Read one of the LSBs of the program

address;

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> m aps to the d estination byte when byte

select = 1.

2. TBLWTL: Ta ble Write Low (ref er to Section 6.0

“Flash Program Memory” for details on Flash

Programming).

3. TBLRDH: Table Read High

Word: Read the most significant word of the

program address;

P<23:16> maps to D<7:0>; D<15:8> always

be = 0.

Byte: Read one of the MSBs of the program

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be = 0 when

byte select = 1.

4. TBLWTH: Table W ri te High (refer to Section 6.0

“Flash Program Memory” for details on Flash

Programming).

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SI GNIFICANT W OR D)

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’).

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

dsPIC30F2010

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFI CANT BYTE)

3.1.2 DATA ACCESS FROM PROGRAM

MEMORY USING PROGRAM

SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This

provides transparent access of stored constant data

from X data space, without the need to use special

instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs

if the MSb of the data space EA is set and program

space visibility is enabled, by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 2.4 “DSP

Engine”, DSP Engine.

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetch es are requ ire d.

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP ope ration uses p rogram sp ace mapp ing to acces s

this m em ory reg ion , Y d ata sp ac e s ho uld ty pic al ly co n-

tain state (variable) data for DSP operations, whereas

X data space should typically contain coefficient

(constant) da ta.

Although each dat a sp ace address, 0x8000 and higher ,

maps directly into a corresponding program memory

address (see Figure 3-5), only the lower 16-bits of the

24-bit program word are used to contain the data. The

upper 8 bits shoul d be progra mmed to forc e an illeg al

instruction to maintain machine robustness. Refer to

the “dsPIC30F/33F Programmer ’s Reference Manual”

(DS70157) for details on instruction encoding.

Note that by incrementing the PC by 2 for each pro-

gram memory word, the Least Significant 15 bits of

data space addresses directly map to the Least Signif-

icant 15 bits in the corresponding program space

address es. The remainin g bits are prov ided by the Pro-

gram Sp ace V is ibilit y Page regi ster, PSVPAG<7:0>, as

shown in Figure 3-5.

For instructions that use PSV which are executed

outside a REPEAT loop:

• The following instructions will require one instruc-

tion cycle in addition to the specified execution

time:

-MAC class of instructions with data operand

prefetch

-MOV instr ucti ons

-MOV.D instructions

• All other instructions will require two instruction

cycl es in addition to th e specified execution time

of the instruction.

For instructions that use PSV which are executed

inside a REPEAT loop:

• The follo wing inst ances will re quire two ins truction

cycl es in addition to th e specified execution time

of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interr upt is servi ced

• Any other iteration of the REPEAT loop will allow

the instruction, accessing data using PSV, to

execute in a single cycle.

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’)

TBLRDH.W

TBLRDH.B (Wn<0> = 1)

TBLRDH.B (Wn<0> = 0)

Note: PSV acc ess is tempo raril y disabl ed durin g

table reads/wr ites.

dsPIC30F2010

FIGU RE 3- 5 : DATA SP AC E W I NDO W I NT O PRO GR AM SPACE OPER AT ION

3.2 Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), o r as o ne u nified linear a ddre ss ran ge (fo r MC U

instruc tions). The dat a spaces are acces s ed usi ng two

Address Generation Units (AGUs) and separate data

paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key ele me nt of th is archi tec tur e is th at

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent linear

addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MAC class of instructions, the X block consists of the

256 byte data address space (including all Y

addresses). When executing one of the MAC class of

instructions, the X block consists of the 256 bytes data

address space excluding the Y address block (for data

reads on ly). In other word s, all other i nstructions rega rd

the entire data memory as one composite address

space. The MAC class instructions extract the Y

address space from data space and address it using

EAs source d from W10 and W1 1. The remaining X dat a

space is addressed using W8 and W9. Both address

spaces are concurrently accessed only with the MAC

class instructions.

A data space memory map is shown in Figure 3-6.

23 15 0

PSVPAG(1)

EA<15> =

EA<15> = 1

Data

Space

Data Space Program Space

15 23

0x0000

0x8000

0xFFFF

0x00

0x100100

0x001FFE

Data Read

Upper half of Data

Space is mapped

into Program Space

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address

(i.e., it defines the page in program space to which the upper half of data space is being mapped).

0x001200

Address

Con cat enat i on

BSET CORCON,#2 ; PSV bit set

MOV #0x00, W0 ; Set PSVPAG register

MOV W0, PSVPAG

MOV 0x9200, W0 ; Access program memory location

; using a data space access

dsPIC30F2010

FIGU RE 3-6 : DATA SPACE MEM ORY MA P

0x0000

0x07FE

0x08FE

0xFFFE

LSB

Address

16 b i ts

LSBMSB

MSB

Address

0x0001

0x07FF

0x08FF

0xFFFF

0x8001 0x8000

Optionally

Mapped

into Program

Memory

0x09FF 0x0A00

0x0801 0x0800

0x0901 0x0900

Near

Data

SFR Space

512 bytes

SRAM Space

2560 bytes

Note: Unimplemented SFR or SRAM locations read as ‘0’.

Space

Unimplemented (X)

X Data

SFR Space

X Data RAM (X)

Y Data RAM (Y)

(Note)

256 bytes

(Note)

dsPIC30F2010

FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS

SFR SPACE

(Y SPACE)

X SPACE

SFR SPACE

UNUSED

X SPACE

Y SPACE

UNUSED

Non-MAC Class Ops (Read/Write) MAC Class Ops Read-Only

Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11

MAC Class Ops (W ri te)

dsPIC30F2010

3.2.2 DATA SPACES

The X data space is used by all instructions and sup-

ports all addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The X dat a sp ace also su pports Modulo Address ing for

all instructions, subject to addressing mode restric-

tions. Bit-Reversed addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to pro-

vide two concurrent data read paths. No writes occur

across the Y bus. This class of instructions dedicates

two W register pointers, W10 and W11, to always

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write-back, the data

address space is consi dere d a c om bin ati on of X and Y

data spaces, so the write occurs across the X bus.

Consequently, the write can be to any address in the

entire data space.

The Y data space can only be used for the data

prefetch operation associated with the MAC class of

instructions. It also supports Modulo Addressing for

automat ed c irc ul ar bu f fe r s. Of c ours e, all othe r ins tru c-

tions ca n access the Y dat a address sp ace thro ugh the

X data path, as part of the composite linear space.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-6 and is not user pro-

gramma ble. Shoul d an EA poin t to d ata out side it s own

assigned address space, or to a location outside phys-

ical mem ory, an all-z ero word/ byte wi ll be returne d. For

example, although Y address space is visible by all

non-MAC instructions using any Addressing mode, an

attempt by a MAC instruction to fetch data from that

space , using W 8 or W9 (X space p ointer s), wi ll ret urn

0x0000.

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

All effective addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

3.2.3 DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are

organ ized as 16-bit wide words. Data space mem ory is

organized in byte addressable, 16-bit wide blocks.

3.2.4 DATA ALIGNMENT

To help maintain backward compatibility with PIC®

MCU devices and improve data space memory usage

efficiency, the dsPIC30F instruction set supports both

word and byte operation s. Data is al igned in dat a mem-

ory and registers as words, but all data space EAs

resolve to bytes. Data byte re ads will rea d the comp lete

word, whi ch contain s the byte, using the LSb of any EA

to determine which byte to select. The selected byte is

placed onto the LSB of the X data path (no byte

acces ses are possible fro m the Y data pa th as the MAC

class of instruction can only fetch words). That is, data

memory and registers are organized as two parallel

byte wide entities with shared (word) address decode,

but separate write lines. Data byte writes only write to

the corresponding side of the array or register which

matches the byte address.

As a conse quence of this byte access ibility, all ef fective

address c alc ul atio ns (in cl udi ng tho se ge nera ted by th e

DSP operations, which are restricted to word-sized

data) a re internally scale d to step through word-aligned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode,

[Ws ++], will result in a value of Ws + 1 for byte

operations and Ws + 2 for word operations.

All word accesses must be al igned to an even a ddress.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. Shoul d a mis-

aligned read or write be attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed, whereas if it

occurred on a write, th e instructi on will be execu ted but

the write will not occur. In either case, a trap will then

be exec uted, a llow ing the syste m and/ or user to exam-

ine the machine state prior to execution of the address

fault.

FIGURE 3-8: DATA ALIGNMENT

Attempted Operation Data Returned

EA = an unimplemented address 0 x0000

W8 or W9 used to access Y data

spa ce in a MAC instru ction 0x0000

W10 or W11 used to access X

data space in a MAC instruction 0x0000

15 8 7 0

0001

0003

0005

0000

0002

0004

Byte 1 Byte 0

Byte 3 Byte 2

Byte 5 Byte 4

LSBMSB

dsPIC30F2010

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

A sign-extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

zero-extend (ZE) instruction on the appropriate

address.

Although m os t i ns truc tio ns are capable of op era t ing o n

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words .

3.2.5 NEAR DATA SPACE

An 8 Kbyte ‘near’ data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is

directly add res sab le via a 13-bit absolut e address field

within all memory direct instructions. The remaining X

address space and all of the Y address space is

address able indirec tly. Additional ly, the whole of X da ta

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

3.2.6 SOFTWARE STACK

The dsPI C DSC de vice c ontain s a softwa re st ack. W15

is used as the Stack Pointer.

The Stack Pointer always points to the first available

free word, and grows from lower addresses towards

higher addresses. It pre-decrements for stack pops,

and post-increments for stack pushes, as shown in

Figure 3-9. Note that for a PC push during any CALL

instruc tion, the M SB of the PC is zero-ext ende d before

the push, ensuring that the MSB is always clear.

There is a Stack Pointer Limit register (SPLIM) associ-

ated with the Stack Pointer. SPLIM is uninitialized at

Reset. As is t he case f or t h e Stack Point er, SPL IM < 0>

is forced to ‘0’, because all stack operations must be

word-aligned. Whenever an EA is generated using

W15 as a source or destination pointer, the address

thus gene rated is compa red with the value in SPLIM. If

the cont ent s of the Stack Poin ter (W15) and the SPLIM

stack error trap will not occur. The stack error trap will

occur on a subsequent push operation. T hus, for exam-

ple, if it is desirable to cause a stack error trap when the

stack grows beyond address 0x2000 in RAM, initialize

the SPLIM with the value, 0x1FFE.

Similarly, a stack pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM register should no t be immediately

follow ed by an ind irec t read ope rati on usi ng W15.

FIGURE 3-9: CALL ST ACK FRAME

Note: A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Toward s

Higher Address

PUSH: [W15++]

POP: [--W15]

0x0000

PC<22:16>

dsPIC30F2010

TABLE 3-3: CORE REGISTER MAP

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

W0 0000 W0 / WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000

W2 0004 W2 0000 0000 0000 0000

W3 0006 W3 0000 0000 0000 0000

W4 0008 W4 0000 0000 0000 0000

W5 000A W5 0000 0000 0000 0000

W6 000C W6 0000 0000 0000 0000

W7 000E W7 0000 0000 0000 0000

W8 0010 W8 0000 0000 0000 0000

W9 0012 W9 0000 0000 0000 0000

W10 0014 W10 0000 0000 0000 0000

W11 0016 W11 0000 0000 0000 0000

W12 0018 W12 0000 0000 0000 0000

W13 001A W13 0000 0000 0000 0000

W14 001C W14 0000 0000 0000 0000

W15 001E W15 0000 1000 0000 0000

SPLIM 0020 SPLIM 0000 0000 0000 0000

ACCAL 0022 ACCAL 0000 0000 0000 0000

ACCAH 0024 ACCAH 0000 0000 0000 0000

ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000

ACCBL 0028 ACCBL 0000 0000 0000 0000

ACCBH 002A ACCBH 0000 0000 0000 0000

ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000

PCL 002E PCL 0000 0000 0000 0000

PCH 0030 — — — — — — — — —PCH

0000 0000 0000 0000

TBLPAG 0032 — — — — — — — —TBLPAG

0000 0000 0000 0000

PSVPAG 0034 — — — — — — — —PSVPAG

0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu

DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu

DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0

DOSTARTH 003C — — — — — — — — —DOSTARTH

0000 0000 0uuu uuuu

DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0

DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000

MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000

XMODSRT 0048 XS<15:1> 0uuuu uuuu uuuu uuu0

XMODEND 004A XE<15:1> 1uuuu uuuu uuuu uuu1

YMODSRT 004C YS<15:1> 0uuuu uuuu uuuu uuu0

YMODEND 004E YE<15:1> 1uuuu uuuu uuuu uuu1

XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu

DISICNT 0052 —— DISICNT<13:0> 0000 0000 0000 0000

TABLE 3-3: CORE REGISTER MAP (CONTINUED)

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

NOTES:

dsPIC30F2010

4.0 ADDRESS GENERATOR UNITS

The dsPIC DSC core contains two independent

address generator un its: the X AGU and Y AGU. The Y

AGU supports word-sized data reads for the DSP MAC

class of instructions only. The dsPIC DSC AGUs

support three types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Revers ed Addre ss in g

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

Addressi ng is on ly appli cable to data s pace a ddresses .

4.1 Instruction Addressing Modes

The Addressing modes in Table 4-1 form the basis of

the Addressing mode s optimized to support the specific

features of individual instructions. The Addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

4.1.1 FILE REGISTER INSTRUCTIONS

Most fil e re gis ter i ns truc tio ns use a 13-bit ad dres s f iel d

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

whic h is den oted as WREG in these i nstruc tions. The

destination is typically either the same file register, or

WREG (with the exception of the MUL instruction),

which w rites the re sult t o a re gister or regi ster p air. The

MOV instruction allows additional flexibility and can

access the entire data space.

TABLE 4-1: FUNDAMENTA L ADDRESSING MODES SUPPORTED

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

dsPIC30F2010

4.1.2 MCU INSTRU CTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Ope r and 1 is alwa ys a w orking register (i. e., th e

Addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory, or 5-bit literal. The result

location can be either a W register or an address

location. The following Addressing modes are

supported by MCU instructions:

• Register Direc t

• Register Indi rec t

• Register Indi rec t Post-mod ifi ed

• Register Indi rec t Pre- mo dif ied

• 5-bit or 10-bit Literal

4.1.3 MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP Accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tions, Move and Accumulator instructions also support

mode, also referred to as Register Indexed mode.

In summary, the following Addressing modes are

supported by Move and Accumulator instructions:

• Register Direc t

• Register Indi rec t

• Register Indi rec t Post-mod ifi ed

• Register Indi rec t Pre- mo dif ied

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

4.1.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also

referred to a s MAC instruction s, utilize a si mplified set of

Addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The two source operand prefetch registers must be a

member of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 will always be directed to the X

RAGU and W10 and W11 will al ways be dire cted to the

Y AGU. The effective add resses generated (before and

after modification) must, therefore, be valid addresses

within X data space for W8 and W9 and Y data space

for W10 and W11.

In summary, the following Addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5 OTHER INSTRU CTIONS

Besides the various Ad dressing mo des outlined above,

some i nstructio ns use li teral con sta nts of various sizes.

For example, BRA (branch) instructions use 16-bit

signed l iterals to spe cify the branch de stination dire ctly ,

whereas the DISI instruction uses a 14-bit unsigned

literal fiel d. In som e in stru cti ons , suc h as ADD Acc, the

source of an operand or result is implied by the opc ode

it self. Cert ain opera tions, such as NOP, do not have any

operands.

Note: Not all instructions support all the

Addressi ng modes given abo ve. Individual

instructions may support different subsets

of these Addressin g modes.

Note: For the MOV instructions, the Addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Regi ste r Offset) field is

shared between both source and

destination (but typically only used by

one).

Note: Not all instructions support all the

Addressi ng modes given abo ve. Individual

instructions may support different subsets

of these Addressin g modes.

Note: Register Indirect with Register Offset

Addressing is only available for W9 (in X

spac e) and W11 (in Y space).

dsPIC30F2010

4.2 Modulo Addressing

Modulo addressing is a method of providing an auto-

mated means to support circular data buffers using

hardwa re. The ob jectiv e is to remo ve t he need for soft-

ware to perform data address boundary checks when

executing tightly looped code, as is typical in many

DSP algorithms.

Modulo addressing can operate in either data or pro-

gram space (since the data pointer mechanism is essen-

tially the same for both). One circular buffer can be

supported in each of the X (which also provides the

pointers into Program space) and Y data spaces. Mod-

ulo addressing can operate on any W register pointer.

However, it is not advisab le to use W14 o r W15 for Mod-

ulo Addressing, since these two registers are used as

the S tack Frame Pointer and S tack Pointer , respectively .

In general, any particular circular buffer can only be

configu red to operate in one direct ion, as ther e are c er-

tain restrictions on the buffer start address (for incre-

menting buffers) or end address (for decrementing

buffers) based upon the dire ct ion of the buffer.

The only exception to the usage restrictions is for buff-

ers which have a power-of-2 length. As these buffers

satisfy the start and end address criteria, they may

operate in a Bidirectional mode, (i.e., address bound-

ary checks will be performed on both the lower and

upper address boundaries).

4.2.1 START AND END ADDRESS

The Modulo Addressing scheme requires that a

starting and an end address be specified and loaded

into the 16-bit modulo buffer address registers:

XMODSRT, XMODEND, YMODSRT and YMODEND

(see Table 3-3).

The leng th of a ci rcular buf fer is not di rectly spec ified. It

is determined by the difference between the corre-

sponding start and end addresses. The maximum

possible length of the circular buffer is 32K words

(64 Kbytes).

4.2.2 W ADDRESS REGISTER

SELECTION

The Mod ulo an d Bi t-Rev ers ed Add ress in g Co ntro l re g-

ister M O DCON <1 5:0 > c on t ai ns enable fla gs as w ell a s

a W register field to specify the W address registers.

The XWM and YWM fields select which registers will

operate with Modulo Addressing. If XWM = 15, X

RAGU and X WAGU Modulo Addressing are disabled.

Similarly, if YWM = 15, Y AGU Modulo Addressing is

disabled.

The X Address Space Pointer W register (XWM) to

which Modulo Addressing is to be applied, is stored in

MODCON <3 :0> (s ee Tabl e 3-3). Modulo ad dres si ng is

enabled for X data sp ace when XWM is set to any v alue

other than 15 and the XMODEN bit is set at

MODCON<15>.

The Y Address Space Pointer W register (YWM) to

which Modulo Addressing is to be applied, is stored in

MODCON<7:4>. Modulo addressing is enabled for Y

data space when YWM is set to any value other than 15

and the YMODEN bit is set at MODCON<14>.

Note: Y space Modulo Addressing EA calcula-

tions assume word-sized data (LSb of

every EA is always clear).

dsPIC30F2010

FIGURE 4-1: MODULO ADDRESSI NG OPERATION EXAMPLE

0x1100

0x1163

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x0032 words

Byte

Address MOV #0x1100,W0

MOV W0, XMODSRT ;set modulo start address

MOV #0x1163,W0

MOV W0,MODEND ;set modulo end address

MOV #0x8001,W0

MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x1110,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations

MOV W0, [W1++] ;fill the next location

AGAIN: INC W0,W0 ;increment the fill value

dsPIC30F2010

4.2.3 MODULO ADDRESSING

APPLICABILITY

Modulo addressing can be applied to the effective

address calculation associated with any W register. It is

important to realize that the address boundaries check

for addresses less than or greater than the upper (for

increm enting buf fers) and lo wer (for decreme nting buf f-

ers) boundary addresses (not just equal to). Address

changes may, therefore, jump beyond boundaries and

still be adjusted correctly.

4.3 Bit-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

reorderin g for radix-2 FFT al gorithms. It is supported by

the X AGU for data wr ites only.

The modifier , which may be a constant value or register

contents, is regarded as having its bit order reversed.

The addres s sourc e and dest inat ion are ke pt in norma l

order. Thus, the only operand requiring reversal is the

modifier.

4.3.1 BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

1. BWM (W register selection) in the MODCON

not be accessed using Bit-Reversed Address-

ing) and

2. the BREN bit is set in the XBREV register and

3. the Addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes,

then the last ‘N’ bits of the data buffer start address

must be zero s.

XB<14:0> is th e b it-re vers ed ad dres s modifier o r ‘p iv ot

point’ which is typically a constant. In the case of an

FFT computation, its value is equal to half of the FFT

dat a buffer size.

When enabled, Bit-Reversed Addressing will only be

executed for register indirect with pre-increment or

post -increment add ressing a nd word-siz ed data wri tes.

It will n ot fun ct ion for an y ot her addressing mo de o r for

byte-sized data, and normal addresses will be gener-

ated instea d. When Bit-R eversed Addr essin g is active,

the W Address Pointer will always be added to the

address modifier (XB) and the offset associated with

the register Indirect Addressing mode will be ignored.

In addition, as word-sized data is a requirement, the

LSb of the EA is ignored (and always clear).

If Bit-Reversed Addressing has already been enabled

by setting the BREN (XBREV<15>) bit, then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W register that

has been designated as the bit-reversed pointer.

FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

Note: The m odu lo corr ected effe cti ve add res s i s

written back to the re giste r only when Pre-

Modify or Post-Modify Addressing mode is

used to compute the effective address.

When an address offset (e.g., [W7 + W2])

is used , m odu lo a dd res s c orrec ti on i s p er-

formed, but the contents of the register

remains unchanged.

Note: All Bit-Reversed EA calculations assume

word-sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note: Modulo addressing and Bit-Reversed

Addressing should not be enabled

together. In the event that the user

attempts to do this, bit reversed address-

ing wil l assume priori ty when activ e for the

X WAGU, and X WAGU Modulo Address-

ing will be disabled. However, Modulo

Addressing will continue to function in the

X RAGU.

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4

b11 b10 b9 b8

b15 b14 b13 b12

Sequenti al Addre ss

Pivot Point

dsPIC30F2010

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Normal

Address Bit-Reversed

Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 00000 0

0001 11000 8

0010 20100 4

0011 31100 12

0100 40010 2

0101 51010 10

0110 60110 6

0111 71110 14

1000 80001 1

1001 91001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value(1)

32768 0x4000

16384 0x2000

8192 0x1000

4096 0x0800

2048 0x0400

1024 0x0200

512 0x0100

256 0x0080

128 0x0040

64 0x0020

32 0x0010

16 0x0008

80x0004

40x0002

20x0001

Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F2010 device

dsPIC30F2010

5.0 INTERRUPTS

The dsPIC30F2010 has 24 interrupt sources and 4

processor exceptions (traps), which must be arbitrated

bas ed on a priority scheme.

The CPU is responsible for reading the Interrupt Vec-

tor Table (IVT) and transferring the address contained

in the interrupt vector to the program counter. The

interrupt vector is transferred from the program data

bus into the program counter, via a 24-bit wide

multiplexer on the input of the program counter.

The Interrupt Vector Table (IVT) and Alternate Inter-

rupt Vector Tabl e (AIVT) are plac ed near the be ginnin g

of program memory (0x000004). The IVT and AIVT

are shown in Figure 5-1.

The interrupt controller is responsible for pre-

processing the interrupts and processor exceptions,

prior to their being presented to the processor core.

The peripheral interrupts and traps are enabled, priori-

tized and controlled using centralized special function

registers:

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their respec-

tive peripherals or external signals, and they are

cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All interrupt enable control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

• IPC0<15:0>... IPC11<7:0>

The user-as s ign abl e prio rity lev el assoc iate d with

eac h of these i nterrupts is held centrally in these

twelve registe rs.

• IPL<3:0> The current CPU priority level is explic-

itly stored in the IPL bits. IPL<3> is present in the

CORCON reg ister , whereas IPL<2:0 > are present

in the STATUS Register (SR) in the processor

core.

• INTCON1< 15:0>, INTCON2<15 :0>

Global interrupt control functions are deriv ed from

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 register controls the external inter-

rupt request signal behavior and the use of the

alternate vector table.

All interrupt sources can be user-assigned to one of 7

priority levels, 1 through 7, via the IPCx registers.

Each interrupt source is associated with an interrupt

vector, as shown in Figure 5-1. Levels 7 and 1 repre-

sent the highest and lowest maskable priorities,

respectively.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prev en ted . Th us, i f an interrupt is c urrentl y

being serviced, processing of a new interrupt is

preve nte d, e ven if th e ne w inte rrup t is of hi gher priority

than the one currently being serviced.

Certain interrupts have specialized control bits for

features like edge or level triggered interrupts, inter-

rupt-on-change, etc. Control of these features remains

within the peripheral module which generates the

interrupt.

The DISI instruction can be used to disable the

processing of interrupts of priorities 6 and lower for a

certain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the

address stor ed in the vecto r locati on in Program Mem-

ory that cor res ponds to the interru pt. There are 63 dif-

fer ent vect ors with in the I VT (ref er to Fig ure 5-1). T hese

vectors are contained in locations 0x000004 through

0x0000FE of program memory (refer to Figure 5-1).

These locations contain 24-bit addresses, and in order

to preserve robustness, an address error trap will take

place should the PC attempt to fetch any of these

words during normal execution. This prevents execu-

tion of random data as a result of accidentally decre-

menting a PC into vector space, accidentally mapping

a data space address into vector space or the PC roll-

ing over to 0x000000 after reaching the end of imple-

mented program memory space. Execution of a GOTO

instruction to this vector space will also generate an

address error trap.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157). Note: Interru pt flag bit s get set when an interru pt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit. User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

Note: Assigning a priority level of 0 to an inter-

rupt source is equivalent to disabling that

interrupt.

Note: The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

dsPIC30F2010

5.1 Interrupt Priority

The user-a ssig nable In terrupt Prio rity (IP<2:0>) b its for

each ind ividual interrupt source are located in the Least

Significant 3 bits of each nibble, within the IPCx regis-

ter(s). Bit 3 of each nibble is not used and is read as a

‘0’. These bits define the priority level assigned to a

particular interrupt by the user.

Since more than one interrupt request source may be

assigned to a specific user specified priority level, a

means is provided to assign prio rity within a given level.

This method is called “Natural Order Priority” and is

final.

Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

Table 5-1 lists the interrupt numbers and interrupt

sources for the dsPIC DSC devices and their

associated vector numbers.

The ability for the user to assign every interrupt to one

of seven pri ority levels means that the user can as sig n

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD (Low-

Voltage Detect) can be given a priority of 7. The INT0

(external interrupt 0) may be assigned to priority level

1, thus giving it a very low effective priority.

TABLE 5-1: dsPIC30F2010 INTERRUPT

VECTOR TABLE

Note: The user-selectable priority levels are

from 0, as th e lo wes t pri orit y, to lev el 7, a s

the highest priority.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The natural order priority number is the

same as the INT number.

INT

Number Vector

Number Interrupt Source

Highest Natural Order Priority

0 8 INT0 – Ex ternal Inte rrupt 0

1 9 IC 1 – I nput Captur e 1

2 10 OC1 – Output Compare 1

3 11 T1 – Ti m er 1

4 12 IC2 – I nput Captur e 2

5 13 OC2 – Output Compare 2

6 14 T2 – Timer 2

7 15 T3 – Timer 3

8 16 SPI1

9 17 U1R X – UART1 Receiv er

10 18 U1TX – UAR T1 T rans m i t ter

11 19 ADC – ADC Convert Done

12 20 NVM – NVM Write Complete

13 21 SI2C – I 2C™ Slave Inte rrupt

14 22 M I 2C – I 2C Master Interrupt

15 23 I npu t Change I nterrupt

16 24 IN T1 – Exte rn al In te rrupt 1

17 25 I C7 – I nput Captur e 7

18 26 I C8 – I nput Captur e 8

19 27 Reserved

20 28 Reserved

21 29 Reserved

22 30 Reserved

23 31 INT2 - External Interrupt 2

24 32 Reserved

25 33 Reserved

26 34 Reserved

27 35 Reserved

28 36 Reserved

29 37 Reserved

30 38 Reserved

31 39 Reserved

32 40 Reserved

33 41 Reserved

34 42 Reserved

35 43 Reserved

36 44 IN T3 – Exte rn al In te rrupt 3

37 45 Reserved

38 46 Reserved

39 47 PWM – PWM Period Match

40 48 QEI – QEI Interrupt

41 49 Reserved

42 50 Reserved

43 51 FLTA – PWM Fault A

44 52 Reserved

45-53 53-61 Reserved

Lowest Natural Order Priority

dsPIC30F2010

5.2 Reset Sequence

A Reset is not a true exception, because the interrupt

controll er is not involv ed in the Reset proce ss. The pro-

cessor initializes its registers in response to a Reset,

which forces the PC to zero. The processor then begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory loca-

tion, im media tel y follo wed by th e addres s t arget for th e

GOTO instruction. The processor executes the GOTO to

the speci f ie d add res s and then begi ns op erat ion at the

specified target (start) address.

5.2.1 RES ET SOURCES

In addition to External Reset and Power-on Reset

(POR), there are 6 sources of error conditions which

‘trap’ to the Reset vector.

• Watchdog Time-out:

The watchdog has timed out, indicating that the

process or is no longer ex ecu tin g the corre ct flo w

of code.

• Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an Address Pointer will cause a Reset.

• Illegal Instruction Trap:

Attempted execution of any unused opcodes will

result in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

• Brown-out Reset (BOR):

A momentary dip in the power supply to the

device has been detected, which may result in

malfunction.

• Trap Lockout:

Occurrence of multiple trap condit ions

simultaneously will cause a Reset.

5.3 Traps

Traps can be considered as non-maskable interrupts

indicating a software or hardware error, which adhere

to a predefined priority as shown in Figure 5-1. They

are intended to provide the user a means to correct

errone ous o pera tio n d urin g debug and w he n o pera tin g

within the application.

Note that many of these trap conditions can only be

detected when th ey occur. Conseque ntly, the ques tion-

able instruction is allowed to complete prior to trap

exception processing. If the user chooses to recover

from the error, the result of the erroneous action that

caused the trap may have to be corrected.

There are 8 fixed priority levels for traps: Level 8

through Le vel 15, which m ea ns that t he IPL 3 is al way s

set during processing of a trap.

If the us er is n ot cur rentl y execu ting a trap, a nd he s et s

the IP L<3:0> bit s to a value of ‘0111’ (Level 7), t hen al l

interr upts are disabled, b ut traps c an still b e processed.

5.3.1 TRAP SOURCES

The following traps are provided with increasing prior-

ity. However, since all traps can be nested, priority has

little effect.

Math Error Trap:

The math error t r ap e xe cutes und er th e following thre e

circumstances:

1. Should an attempt be made to divide by zero,

the divide operation will be aborted on a cycle

boundary and the trap taken.

2. If enabled, a math error trap will be taken when

an arithmetic operation on either accumulator A

or B causes an overflow from bit 31 and the

accumulator guard bits are not utilized.

3. If enabled, a math error trap will be taken when

an arithmetic operation on either accumulator A

or B causes a catastrophic overflow from bit 39

and all saturation is disabled.

4. If the shift amount specified in a shift instruction

is greater than the maximum allowed shift

amount, a trap will occur.

Note: If the user does not intend to take correc-

tive actio n in the ev ent of a trap error co n-

dition, these vectors must be loaded with

the address of a default handler that sim-

ply contains the RESET instruction. If, on

the ot her hand, one of the vector s cont ain-

ing an invalid address is called, an

address error trap is generated.

dsPIC30F2010

Address Error Trap:

This trap is initiated when any of the following

circumstances occurs:

1. A misaligned data word access is attempted.

2. A data fetch from an unimplemented data

memory location is attempted.

3. A data access of an unimplemented program

memory location is attempted.

4. An instruction fetch from vector space is

attempted.

5. Execution of a “BRA #literal” instruction or a

“GOTO #literal” ins truc ti on, w he re literal

is an u nimplem ented pr ogram me mory addr ess.

6. Executing instructions after modifying the PC to

point to unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

1. The Stack Pointer is loaded with a value which

is greater than the (user programmable) limit

value written into the SPLIM register (stack

overflow).

2. The Stack Pointer is loaded with a value which

is less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

5.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 5-1 is implemented,

whic h may requir e the user t o check if oth er traps are

pending, in order to completely correct the fault.

‘Soft’ traps incl ude exceptions of priority lev el 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Each hard trap that occurs must be acknowledged

before code execution of any type may continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict will occur.

The devic e is automatic ally Reset in a hard trap conflict

condition. The TRAPR status bit (RCON<15>) is set

when the Reset occurs, so that the condition may be

detected in software.

FIGURE 5-1: TRAP VECTORS

Note: In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

Address Error Trap Vector

Oscillator Fail Trap Vector

Stack Error T rap Vector

Reser ved Vector

Math E rror Trap Vector

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Reser ved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

Math E rror Trap Vector

Decreasing

Priority

0x000000

0x000014

Reserved

Stack Error T rap Vector

Reser ved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

IVT

AIVT

0x000080

0x00007E

0x0000FE

Reserved

0x000094

Reset - GOTO Instruction

Reset - GOTO Addr ess 0x000002

Reserved 0x000082

0x000084

0x000004

Reser ved Vector

dsPIC30F2010

5.4 Interrupt Sequence

All inte rrupt event flags are sampled in the be ginning of

each instruction cycle by the IFSx registers. A pending

interr upt reque st (IRQ) i s indic ated by the flag bit being

equal t o a ‘1’ in an IFSx register . The IRQ will cause an

interrupt to occur if the corresponding bit in the interrupt

enable (IECx) register is set. For the remainder of the

instruction cycle, the priorities of all pending interrupt

requests are evaluated.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor will be interrupted.

The pr ocessor then st acks the curren t program counter

and the low byte of the processor STATUS register

(SRL), a s sh own in Fi gure 5-2. The l ow b yte o f the s ta-

tus r egist er con tains t he pro cess or pri orit y leve l at t he

time, prior to the beginning of the interrupt cycle. The

processor then loads the priority level for this interrupt

into the STATUS register. This action will disable all

lower priority interrupts until the completion of the

Interrupt Service Routine (ISR).

FIGURE 5-2: INTERRUPT STACK

FRAME

The RETFIE (Return from Interrupt) instruction will

unstack the program counter and status registers to

return the processor to its state prior to the interrupt

sequence.

5.5 Alternate Vector Table

In Program Memory, the Interrupt Vector Table (IVT) is

follow ed by the Altern ate Interr upt Vector Table (AIVT),

as show n in Fig ure 5-1. Access to the Alte rnat e Vector

Table is provided by the ALTIVT bit in the INTCON2

tion processes will use the alternate vectors instead of

the defa ult vectors. The alternate vectors are org anized

in the same manner as the default vectors. The AIVT

supports emulation and debugging efforts by providing

a means to switch between an application and a sup-

port environment, without requiring the interrupt vec-

tors to be reprogrammed. This feature also enables

switching between applications for evaluation of

different software algorithms at run time.

If the AIVT is not required, the program memory allo-

cated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

5.6 Fast Context Saving

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z an d C bits in SR, and the re gisters W 0 through

W3. The shadows are only one level deep. The shadow

registers are accessible using the PUSH.S and POP.S

inst ruc tion s onl y.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority IS R shou ld no t inc lude the s ame ins truc-

tions. Users must save the key registers in software

during a lower priorit y interrupt, if t he higher prio rity ISR

uses fast context saving.

5.7 External Interrupt Requests

The interrupt controller supports five external interrupt

request signals, INT0-INT4. These inputs are edge

sensitive; they require a low-to-high or a high-to-low

transition to generate an interrupt request. The

INTCON2 re gister has thre e bits, INT0EP-INT2EP, that

select the polarity of the edge detection circuitry.

5.8 Wake-up from Sleep and Idl e

The interrupt controller may be used to wake up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor will wake-up from Sleep or

Idle and begin execution of the Interrupt Service

Routine needed to process the interrupt request.

Note 1: The user can always lower the priority

level by writing a new value into SR. The

Interrupt Service Routine must clear the

interrupt flag bits in the IFSx register

before lowering the processor interrupt

priority, in order to avoid recursive

interrupts.

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being pro-

cessed. It is set only during execution of

traps.

015

W15 (befor e CALL

)

W15 (after CALL)

Stack Grows Towards

Higher Address

PUSH : [W15++]

POP : [--W15]

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

dsPIC30F2010

TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000

IFS1 0086 — — — — — — — —INT2IF— — — — IC8IF IC7IF INT1IF 0000 0000 0000 0000

IFS2 0088 ————FLTAIF——QEIIFPWMIF— — — — — — — 0000 0000 0000 0000

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000

IEC1 008E — — — — — — — —INT2IE— — — — IC8IE IC7IE INT1IE 0000 0000 0000 0000

IEC2 0090 ————FLTAIE—— QEIIE PWMIE — — — — — — — 0000 0000 0000 0000

IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100

IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> —IC2IP<2:0>

0100 0100 0100 0100

IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100

IPC3 009A — CNIP<2:0> —MI2CIP<2:0>—SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100

IPC4 009C — — — — — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100

IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0000 0000 0000

IPC6 00A0 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC7 00A2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC9 00A6 —PWMIP<2:0>— — — — — — — — — — — — 0000 0000 0000 0000

IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0100

IPC11 00AA — — — — — — — — — — — — — — — — 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

6.0 FLASH PROGRAM MEMORY

The dsPIC30F family of devices contains internal

program Flash memory for executing user code. There

are two methods by which the user can program this

memory:

1. In-Circuit Serial Programming (ICSP)

programming capability

2. Run-Time Self-Programming (RTSP)

6.1 In-Circuit Serial Programming

(ICSP)

dsPIC30F devices can be serially programmed while i n

the end ap plica tion ci rcuit. Th is is s imply do ne wit h two

lines for Programming Clock and Programming Data

(which are named PGC and PGD respectively), and

three other lines for Power (VDD), Ground (VSS) and

Master Clear (MCLR). this allows customers to manu-

facture boards with unprogrammed devices, and then

program the digital signal controller just before shipping

the product. This also allows the most recent firmware

or a custom firmware to be programmed.

6.2 Run-Time Self-Programming

(RTSP)

RTSP is accomplished using TBLRD (table read) and

TBLWT (table wr ite) ins tru cti ons .

With RTSP, the user may erase program memory, 32

instruc tions (96 bytes) at a tim e an d c an wr it e pro gram

memory data, 32 instructions (96 bytes) at a time.

6.3 Table Instruction Operation Summary

The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

Word or Byte mode.

The TBLRDH and TBLWTH i nstructio ns are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTH can access program memory in Word or

Byte mode.

A 24-bit program memory address is formed using

bits <7:0 > o f the TBLPAG regis ter an d the EA from a W

Figure 6-1.

FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

0Program Counter

24 bi ts

NVMADRU Reg

8 bit s 16 bit s

Program

Using

TBLPA G Reg

8 bits

Wor k i ng Re g EA

16 bits

Using

Byte

24-bit EA

1/0

Select

Table

Instruction

NVMADR

Addressing

Counter

Using

NVMADR Reg EA

User/Configuration

Space Select

dsPIC30F2010

6.4 RTSP Operation

The dsPIC30F Flash program memory is organized

into rows and panels. Each row consists of 32 instruc-

tions, or 96 bytes. Each panel consists of 128 rows, or

4K x 24 instructions. RTSP allows the user to erase one

row (32 instructions) at a time and to program 32

instructions at one time. RTSP may be used to program

multiple program memory panels, but the table pointer

must be changed at each panel boundary.

Each panel of program memory contains write latches

that hold 32 instructions of programming data. Prior to

the actual programming operation, the write data must

be loaded into the panel write latches. The data to be

programmed into the panel is loaded in sequential

order into the write latches; instruction 0, instruction 1,

etc. T he i ns truc tio n words loaded m us t a lway s b e fro m

a 32 address boundary.

The basi c sequence for R TSP programming is to set up

a table point er, th en do a serie s of TBLWT instructions

to load th e wri te latc hes. Program ming is perfo rmed by

setting the special bits in the NVMCON register. 32

TBLWTL and four TBLWTH instructions are required to

load the 32 instructions. If multiple panel programming

is required, the table pointer needs to be changed and

the next set of multiple write latches written.

All of the table write operations are single word writes

(2 instruction cycles), because only the table latches

are written. A programming cycle is required for

programming each row.

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

6.5 Control Registers

The four SFRs used to read and write the program

Flash memory are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

6.5.1 NVMCON REGISTER

The NVMCON register controls which blocks are to be

erased, which memory type is to be programmed, and

the start of the programming cycle.

6.5.2 NVMADR REGISTER

The NVMADR register is used to hold the lower two

bytes of the effective address. The NVMADR register

captures the EA<15 :0> of the last table instru ct ion that

has been executed and selects the row to write.

6.5.3 NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte

of the effective address. The NVMADRU register cap-

tures the EA<23:16> of the last table instruction that

has been exec uted.

6.5. 4 NVMKEY REGISTER

NVMKEY is a write-only register that is used for write

protection. To start a programming or an erase

sequence, the user must consecutively write 0x55 and

0xAA to the NVMKEY register. Refer to Section 6.6

“Programming Operations” for further details.

Note: The user can also directly write to the

NVMADR and NVMADRU registers to

specify a program memory address for

erasing or programming.

dsPIC30F2010

6.6 Programming Operati ons

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A progra mming operati on is nominally 2 ms ec in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation, and the WR bit is automatically

cleared when the operation is finished.

6.6.1 PROGRAMMING ALGORITHM FOR

PROGRAM FLASH

The user can erase and program one row of program

Flash memory at a time. The general process is:

1. Read one row of program Flash (32 instruction

words) and store into data RAM as a data

“image”.

2. Update the data image with the desired new

data.

3. Erase program Flash row.

a) Setup NVMCON register for multi-word,

program Flash, erase and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR.

c) Write ‘55’ to NVMKEY.

d) Write ‘AA’ to NVMKEY.

e) Set the WR bit. This will begin erase cycle.

f) CPU will stall for the duration of the erase

cycle.

g) The WR bit is cleared when erase cycle

ends.

4. Write 32 instruction words of data from data

RAM “image” into the program Flash write

latches.

5. Program 32 instruction words into program

Flash.

a) Setup NVMCON register for multi-word,

progra m Flash, program and set WREN bit.

b) Write ‘55’ to NVMKEY.

c) Write ‘AA’ to NVMKEY.

d) Set the WR bit. This will begin program

cycle.

e) CPU will stall for duration of the program

cycle.

f) The WR bit is cleared by the hardware

when program cycle ends.

6. Repeat step s 1 through 5 as needed to program

desired amount of program Flash memory.

6.6.2 ERASING A ROW OF PROGRAM

MEMORY

Example 6-1 show s a code seque nce that can be used

to erase a row (32 instructions) of program memory.

EXAMPL E 6-1: ERASIN G A ROW O F PROGR AM MEMO RY

; Setup NVMCON for erase operation, multi word write

; program memory selected, and writes enabled

MOV #0x4041,W0 ;

MOV W0,NVMCON ; Init NVMCON SFR

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR),W0 ;

MOV W0,NVMADRU ; Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer

MOV W0, NVMADR ; Intialize NVMADR SFR

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F2010

6.6.3 LOADING WRITE LATCHES

Example 6-2 shows a sequence of instructions that

can be used to load the 96 bytes of write latches. 32

TBLWTL and 32 TBLWTH instructions are needed to

load the writ e latches selected by the table pointer.

EXAMPLE 6-2: LOADING WRITE LATCHES

6.6.4 INITIATING THE PROGRAMMING

SEQUENCE

For protec tion, the w rite i nitiate sequenc e for N VMKEY

must be used to allow any erase or program operation

to procee d. After the prog ramming comm and has bee n

executed, the user must wait for the programming time

until programming is complete. The two instructions

following the start of the programming sequence

should be NOPs.

EXAMPLE 6-3: INITIATING A PROGRAMMIN G SEQUENCE

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV #0x0000,W0 ;

MOV W0,TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000,W0 ; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV #LOW_WORD_0,W2 ;

MOV #HIGH_BYTE_0,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 1st_program_word

MOV #LOW_WORD_1,W2 ;

MOV #HIGH_BYTE_1,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 2nd_program_word

MOV #LOW_WORD_2,W2 ;

MOV #HIGH_BYTE_2,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 31st_program_word

MOV #LOW_WORD_31,W2 ;

MOV #HIGH_BYTE_31,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

Note: In Example 6-2, the contents of the upper byte of W3 has no effect.

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F2010

TABLE 6-1: NVM REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMCON 0760 WR WREN WRERR — — — — TWRI —PROGOP<6:0> 0000 0000 0000 0000

NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu

NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu

NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference ManuaI” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

NOTES:

dsPIC30F2010

7.0 DAT A EEPROM MEMORY

The Data EEPROM Memory is readable and writable

during no rmal operatio n over the enti re VDD range. The

data EEPROM memory is directly mapped in the

program memory address space.

The four SFRs used to read and write the program

Flash memory are used to access data EEPROM

memory as well. As described in Section 4.0, these

registers are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

The EEPROM data memory allows read and write of

single words and 16-word blocks. When interfacing to

data memory, NVMADR, in conjunction with the

NVMADRU register, is used to address the EEPROM

location being accessed. TBLRDL and TBLWTL

instructions are used to read and write data EEPROM.

The dsPIC30F devices have up to 1 Kbyte of data

EEPROM, with an address range from 0x7FFC00 to

0x7FFFFE.

A word wri te operatio n should be prec eded by an e rase

of the corresponding memory location(s). The write

typically requires 2 ms to complete, but the write time

will vary with voltage and temperature.

A program or erase operation on the data EEPROM

does n ot sto p the ins truc tion fl ow. The us er is r espon -

sible for waiting for the appropriate duration of time

before initiating another data EEPROM write/erase

operation. Attempting to read the data EEPROM while

a programming or erase operation is in progress results

in unspecified data.

Control bit WR ini tia tes write operations , s imilar to pro-

gram Flash writ es . Th is bi t c an not be cleared, only se t,

in software. This bit is cleared in hardware at the com-

pletion of the write operation. The inability to clear the

WR bit in software prevents the accidental or

premature termination of a write operation.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRERR bi t is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset, during normal oper-

ation . In these si tuatio ns, foll owing Re set, the us er can

check the WRERR bit and rewrite the location. The

address register NVMADR remains unchanged.

7.1 Reading the Data EEPROM

A TBLRD instruction reads a word at the current pro-

gram word address. This example uses W0 as a

pointer to data EEPROM. The result is placed in

EXAMPLE 7-1: DAT A EEPROM READ

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Note: Interrupt flag bit NVMIF in the IFS0 regis-

ter is set when write is complete. It must be

cleared in software.

MOV #LOW_ADDR_WORD,W0 ; Init Pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1

TBLPAG

TBLRDL [ W0 ], W4 ; read data EEPROM

dsPIC30F2010

7.2 Erasing Data EEPROM

7.2.1 ERASING A BLOCK OF DATA

EEPROM

In order to erase a block of data EEPROM, the

NVMADRU and NVMADR registers must initially

point to th e block of memor y to be erased. Co nfigure

NVMCON for erasing a block of data EEPROM, and

set the WR and WREN bits in NVMCON register. Set-

ting the WR bit initiates the erase, as shown in

Example 7-2.

EXAMPLE 7-2: DATA EEPROM BLOCK ERASE

7.2.2 ERASING A WORD OF DATA

EEPROM

The NVMADRU and NV MADR r egisters must point t o

the block . S el ect er ase a bl ock of data Flas h, and set

the WR and WREN bits in NV MCON regi ster. S ett ing

the WR bit initiates the erase, as shown in Example 7-

EXAMPLE 7-3: DAT A EEPROM WOR D ERASE

; Select data EEPROM block, ERASE, WREN bits

MOV #4045,W0

MOV W0,NVMCON ; Initialize NVMCON SFR

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate erase sequence

NOP

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

; Select data EEPROM word, ERASE, WREN bits

MOV #4044,W0

MOV W0,NVMCON

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate erase sequence

NOP

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

dsPIC30F2010

7.3 Writing to the Data EEPROM

To write an EEPROM data location, the following

sequen ce must be followed :

1. Erase data EEPROM word.

a) Select word, data EEPROM, erase and set

WREN bit in NVMCO N regis ter.

b) Write address of word to be erased into

NVMADRU/NVMADR.

c) Enable NVM interrupt (optional).

d) Write ‘55’ to NVMKEY.

e) Write ‘AA’ to NVMKEY.

f) Set the WR bit. This will begin erase cycle.

g) Either poll NVMIF bit or wait for NVMIF

interrupt.

h) The W R bit is cle ared whe n the era se cy cle

ends.

2. Write data word into data EEPROM write

latches.

3. Program 1 data word into data EEPROM.

a) Select word, data EEPROM, program and

set WREN bit in NVMCON register.

b) Enable N VM wri te don e inte rrupt (o ptiona l).

c) Write ‘55’ to NVMKEY.

d) Write ‘AA’ to NVMKEY.

e) Set The WR bit. This will begin program

cycle.

f) Either poll NVMIF bit or wait for NVM

interrupt.

g) The WR bit is cleared when the write cycle

ends.

The write will not initiate if the above sequence is not

exactly followed (write 0x55 to NVMKEY, write 0xAA to

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM, due to unexpected code exe-

cution. The WR EN b it sho ul d be k ept clear at a ll tim es ,

except when updating the EEPROM. The WREN bit is

not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not affect the current write cycle. The WR

bit will be inhibited from being set unless the WREN bit

is set. The WREN bit must be set o n a previous instruc -

tion. Both WR a nd WREN c an not be se t with th e s am e

instruction.

At the completion of the write cycle, the WR bit is

cleared in ha rdware and the No nv ola til e M emory Write

Complete Interrupt Flag bit (NVMIF) is set. The user

may either enable this interrupt, or poll this bit. NVMIF

must be cleared by software.

7.3.1 WRITING A WORD OF DATA

EEPROM

Once the user has erased the word to be programme d,

then a table write instruction is used to write one write

latch, as shown in Example 7-4.

EXAMPLE 7-4: DAT A EEPROM WOR D WRITE

; Point to data memory

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #LOW(WORD),W2 ; Get data

TBLWTL W2,[ W0] ; Write data

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV #0x4004,W0

MOV W0,NVMCON

; Operate key to allow write operation

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate program sequence

NOP

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

dsPIC30F2010

7.3.2 WRITING A BLOCK OF DATA

EEPROM

To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and

progra m the block .

EXAMPLE 7-5: DAT A EEPROM BLOCK WRITE

7.4 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

7.5 Protection Against Spurious W rite

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared;

also, the Power-up Ti mer prevents EEPROM write.

The writ e in iti ate sequence an d the WR EN bi t tog eth er

help prevent an accidental write during brown-out,

power glitch or software malfunction.

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #data1,W2 ; Get 1st data

TBLWTL W2,[ W0]++ ; write data

MOV #data2,W2 ; Get 2nd data

TBLWTL W2,[ W0]++ ; write data

MOV #data3,W2 ; Get 3rd data

TBLWTL W2,[ W0]++ ; write data

MOV #data4,W2 ; Get 4th data

TBLWTL W2,[ W0]++ ; write data

MOV #data5,W2 ; Get 5th data

TBLWTL W2,[ W0]++ ; write data

MOV #data6,W2 ; Get 6th data

TBLWTL W2,[ W0]++ ; write data

MOV #data7,W2 ; Get 7th data

TBLWTL W2,[ W0]++ ; write data

MOV #data8,W2 ; Get 8th data

TBLWTL W2,[ W0]++ ; write data

MOV #data9,W2 ; Get 9th data

TBLWTL W2,[ W0]++ ; write data

MOV #data10,W2 ; Get 10th data

TBLWTL W2,[ W0]++ ; write data

MOV #data11,W2 ; Get 11th data

TBLWTL W2,[ W0]++ ; write data

MOV #data12,W2 ; Get 12th data

TBLWTL W2,[ W0]++ ; write data

MOV #data13,W2 ; Get 13th data

TBLWTL W2,[ W0]++ ; write data

MOV #data14,W2 ; Get 14th data

TBLWTL W2,[ W0]++ ; write data

MOV #data15,W2 ; Get 15th data

TBLWTL W2,[ W0]++ ; write data

MOV #data16,W2 ; Get 16th data

TBLWTL W2,[ W0]++ ; write data. The NVMADR captures last table access address.

MOV #0x400A,W0 ; Select data EEPROM for multi word op

MOV W0,NVMCON ; Operate Key to allow program operation

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start write cycle

NOP

dsPIC30F2010

8.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

8.1 P a ra l le l I/O (PIO) Po rts

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

All port pins have three registers directly associated

with the operation of the port pin. The data direction

or an output. If the data direction bit is a ‘1’, t hen the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch (LATx). Reads from

the port (PORTx), read the port pins, and writes to the

port pins, write the latch (LATx).

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

A parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has own ership of the outp ut dat a and co ntrol si gnals of

the I/O pad cell. Figure 8-1 shows how ports are shared

with o ther periphe rals, and th e associa ted I/O cell (pad)

to which they are connected. Table 8-1 shows the

formats of the registers for the shared ports, PORTB

through PORTF.

FIGURE 8-1: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

WR LAT +

TRIS Latch

I/O P a d

WR Port

Data Bus

Data Latch

Read LAT

Read Po rt

Read TRIS

W R TRIS

Peripheral Ou tput Data Output Enable

Peripheral In put D ata

I/O Cell

Peripheral Module

Peripheral Ou tput Enable

PIO Module

Output Multiplexers

Output Data

Inp u t Dat a

Peripheral Module Enable

dsPIC30F2010

8.2 Configur ing Analog Port Pins

The use of the ADPC FG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared (out-

put), the digital output level (VOH or VOL) will be

converted.

When read ing the POR T register, all pins c onfigured a s

analog in put channel w ill read as cleare d (a low lev el).

Pins configured as digital inp uts will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins), may cause the

input buffer to consume current that exceeds the

device specifications.

8.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

EXAMPLE 8-1: PORT WRITE/READ

EXAMPLE

8.3 Input Change Noti fication Module

The Input Change Notification module provides the

dsPIC30F devices the ability to generate interrupt

requests to the processor in response to a change-of-

state on selected input pins. This module is capable of

detecting input change-of-states even in Sleep mode,

when t he cloc ks are di sabled. There ar e up to 2 2 exter-

nal signals (CN0 through CN21) that may be selected

(enabled) for generating an interrupt request on a

change-of-state.

MOV 0xFF00, W0; Configure PORTB<15:8>

; as inputs

MOV W0, TRISBB; and PORTB<7:0> as outputs

NOP ; Delay 1 cycle

btssPORTB, #13; Next Instruction

dsPIC30F2010

TABLE 8-1: dsPIC30F2010 PORT REGISTER MAP

TABLE 8-2: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-0)

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISB 02C6 — — — — — — — — — — TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 0011 1111

PORTB 02C8 — — — — — — — — — — RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

LATB 02CA — — — — — — — — — — LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000

TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000

PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000

LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000

TRISD 02D2 — — — — — — — — — — — — — — TRISD1 TRISD0 0000 0000 0000 0111

PORTD 02D4 — — — — — — — — — — — — — — RD1 RD0 0000 0000 0000 0000

LATD 02D6 — — — — — — — — — — — — — — LATD1 LATD0 0000 0000 0000 0000

TRISE 02D8 — — — — — — — TRISE8 — — TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0001 0011 1111

PORTE 02DA — — — — — — — RE8 — — RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000

LATE 02DC — — — — — — — LATE8 — — LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000

TRISF 02DE — — — — — — — — — — — — TRISF3 TRISF2 — — 0000 0000 0000 1100

PORTF 02E0 — — — — — — — — — — — — RF3 RF2 — — 0000 0000 0000 0000

LATF 02E2 — — — — — — — — — — — — LATF3 LATF2 — — 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

SFR Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset St ate

CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

0000 0000 0000 0000

CNEN2 00C2 — — — — — — — — — — CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE

0000 0000 0000 0000

CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

0000 0000 0000 0000

CNPU2 00C6 — — — — — — — — — — CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE

0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

NOTES:

dsPIC30F2010

9.0 TIMER1 MODULE

This section describes the 16-bit general purpose

Timer1 module and associated operational modes.

Figure 9-1 depicts the simplified block diagram of the

16-bit Ti mer1 Module.

The f ollowin g sec tions provid e a det ail ed descripti on of

the operational modes of the timers, including setup

and control registers along with associated block

diagrams.

The T imer1 mo dule is a 16-bit timer which can serv e as

the time count er for the rea l-time clo ck, o r operate as a

free runnin g interva l timer/c ounter . The 16-bit tim er has

the following modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

Further, the following operational characteristics are

supported:

• Timer gate operation

• Selectable prescaler set tings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit period register match or falling

edge of external gate signal

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1

presents a block diagram of the 16-bit timer module.

16-bit T imer Mode: In t he 16-bi t T imer m ode, the timer

increments on every instruction cycle up to a match

value, preloaded into the period register PR1, then

resets to ‘0’ and continues to count.

When the CPU goes into the Idle mode, the timer will

stop incrementing unless the TSIDL (T1CON<13>)

bit = 0. If TSIDL = 1, t he timer module log ic will resum e

the incrementing sequence upon termination of the

CPU Idle mode.

16-bit Synchronous Counter Mode: In the 16-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal,

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in PR1,

then reset s to ‘0’ and conti nue s.

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless the respective TSIDL bit = 0.

If TSIDL = 1, the timer module logic will resume the

incrementing sequence upon termination of the CPU

Idle mode.

16-bit Asynchronous Counter Mode: In the 16-bit

Asynchronous Counter mode, the timer increments on

every rising edge of the applied external clock signal.

The timer counts up to a match value preloaded in PR1,

then reset s to ‘0’ and conti nue s.

When the timer is configured for the Asynchronous mode

of operation and the CPU goes into the Idle mode, the

timer w ill s to p increm en ti ng if TSIDL = 1.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: Timer1 is a ‘Ty pe A’ timer. Please refer to

the specifications for a Type A timer in

Section 22.0 “Electrical Characteris-

tics” of this document.

dsPIC30F2010

FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)

9.1 Timer Gate Operation

The 16-bi t timer can be pl aced in the Ga ted Ti me Accu-

mulation mode. This mode allows the internal TCY to

increm ent the respec tive timer when the gate input si g-

nal (T1CK pin) is asserted high. Control bit TGATE

(T1CON<6>) must be set to enable this mode. The

timer must be enabled (TON = 1) and the timer clock

source se t to interna l (TCS = 0).

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless TSIDL = 0. If TSIDL = 1, the

timer will resume the incrementing sequence upon

termination of the CPU Idle mode.

9.2 Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit

Timer, has a prescale option of 1:1, 1:8, 1:64, and

1:256 selected by control bits TCKPS<1:0>

(T1CON< 5:4 >). T he pres ca le r counter is c le are d whe n

any of the following occurs:

• a write to the TMR1 register

• cl earing of the TON bit (T1C ON<1 5>)

• device Reset such as POR and BOR

However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler

clock is halted.

TMR1 is not cleared when T1CON is written. It is

cleared by writin g to the TMR1 register.

9.3 Timer Operation During Sleep

Mode

During CPU Sleep mode, the timer will operate if:

• The timer module is enabled (TON = 1) and

• The timer clock s ource is selected as extern al

(TCS = 1) and

• The TSYNC bit (T1CON<2>) is asser ted to a logic

‘0’, which defines the external clock source as

asynchronous

When all three conditions are true, the timer will

continu e to count up to the period register and be Reset

to 0x0000.

When a ma tch between the ti me r and the peri od re gis -

ter occurs, an interrupt can be generated, if the

respective timer interrupt enable bit is asserted.

TON

Sync

SOSCI

SOSCO/

PR1

T1IF

Equal Comparator x 16

TMR1

Reset

LPOSCEN

Event Flag

TSYNC

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

TCS

1 X

0 1

TGATE

0 0

(3)

Gate

Sync

dsPIC30F2010

9.4 Timer Interrupt

The 16-bit tim er ha s the ab ili ty to ge nerate an interrupt

on period match. When the timer count matches the

period reg ister , th e T1IF bit is asserted and an interrupt

will be generated, if enabled. The T1IF bit must be

cleared in software. The timer interrupt flag T1IF is

located in the IFS0 control register in the Interrupt

Controller.

When the Gated Time Accumulation mode is enabled,

an interr upt will al so be generat ed on the f alling edge of

the gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.

9.5 Real-Time Clock

Timer1, when operating in Real-Time Clock (RTC)

mode, provides time-of-day and event time stamping

capabilities. Key operational features of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

• Low power

• Real-Time Clock Interrupts

• These Operating modes are determined by

setting the appropriate bit(s) in the T1CON

Control register

FIGURE 9-2: RECOMMENDED

COMPONENTS FOR

TIMER1 LP OSCILLATOR

RTC

9.5.1 RTC OSCILLATOR OPERATION

When the TON = 1, T CS = 1 an d TGATE = 0, the timer

increme nt s on the risin g e dge of the 32 kHz LP oscill a-

tor output si gnal, up to the val ue specifi ed in the period

The TSYNC bit must be asserted to a logic ‘0’

(Asynchronous mode) for correct operation.

Enabling LPOSCEN (OSCCON<1>) will disable the

normal Ti mer and Counter modes, and enable a timer

carry-out wake-up event.

When the CPU enters Sleep mode, the RTC will con-

tinue to operate, provided the 32 kHz external crystal

oscillator is active and the control bits have not been

changed. The TSIDL bit should be cleared to ‘0’ in

order for R TC to contin ue ope rati on in Idle mode .

9.5.2 RTC INTERRUPTS

When an interrupt event occurs, the respective inter-

rupt flag, T1 IF, is asserted an d an inte rrupt will be ge n-

erated, if enabled. The T1IF bit must be cleared in

software. The respective Timer interrupt flag, T1IF, is

located in the IFS0 status register in the Interrupt

Controller.

Enabling an interrupt is accomplished via the respec-

tive time r interrupt ena ble bit, T1IE. Th e T imer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.

SOSCI

SOSCO

dsPIC30FXXXX

32.768 kHz

XTAL

C1 = C2 = 18 pF; R = 100K

dsPIC30F2010

TABLE 9-1: TIMER1 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR1 0100 Tim er 1 Registe r uuuu uuuu uuuu uuuu

PR1 0102 Period Register 1 1111 1111 1111 1111

T1CON 0104 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 —TSYNCTCS —0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

10.0 TIMER2/3 MODULE

This section describes the 32-bit general purpose

Timer module (Timer2/3) and associated operational

modes. Figure 10-1 depicts the simplified block dia-

gram of the 32-bit Timer2/3 module. Figure 10-2 and

Figure 10-3 show Timer2/3 configured as two

independent 16-bit timers; Timer2 and Timer3,

respectively.

The Timer2/3 module is a 32-bit timer, which can be

configu red as two 16-bit timers , with sele ct able oper at-

ing modes. These timers are utilized by other

peripheral modules such as:

• Input Capture

• Output Compare/Simpl e PWM

The following sections provide a detailed description,

including setup and control registers, along with asso-

ciated bl oc k dia gram s for the ope rati ona l mod es of the

timers.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and

Tim er3) with all 16 -bit operating mode s (except

Asynchronous Counter mode)

• Single 32-bit Timer operation

• Single 32-bit Synchronous Counter

Further, the following operational characteristics are

supported:

• ADC Event Trigger

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-bit Period Register Match

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit T2CON and T3CON

SFRs.

For 32-bit timer/counter operation, Timer2 is the least

signifi cant word and Tim er3 is the mos t significant wo rd

of the 32-bit timer.

16-bit Mode: In the 16-bit mode, Timer2 and Timer3

can be configured as two independent 16-bit timers.

Each time r can be set up in either 16-b it T imer mod e or

16-bit Synchronous Counter mode. See Section 9.0

“Timer1 Module” for details on these two operating

modes.

The only functional difference between Timer2 and

Timer3 is that Timer2 provides synchronization of the

clock prescal er output. This is usefu l for high frequenc y

external clock inputs.

32-bit T imer Mode: In t he 32-bi t T imer m ode, the timer

increments on every instruction cycle up to a match

value, pre loade d into the combi ned 32-bi t period regis-

ter PR3/PR2, th en rese ts to ‘0’ and continues t o count.

For synchronous 32-bit reads of the Timer2/Timer3

pair, reading the least significant word (TMR2 register)

will cause the most significant word (msw) to be read

and latched into a 16-bit holding register, termed

TMR3HLD.

For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by

a write to the TMR2 re gister, the content s of TM R3HLD

will be transferred and latched into the MSB of the

32-bit timer (TMR3).

32-bit Synchronous Counter Mode: In the 32-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal,

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in the

combined 32-bit period register PR3/PR2, then resets

to ‘0’ and continues.

When the timer is configured for the Synchronous

Counter mode of operation and the CPU goes into the

Idle mode, the timer will stop incrementing, unless the

TSIDL (T2CON<13>) bit = ‘0’. If TS IDL = ‘1’, the timer

module logic will resume the incrementing sequence

upon termination of the CPU Idle mode.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: Timer2 is a ‘ Typ e B ’ ti me r an d Timer 3 is a

‘Type C’ timer. Please refer to the appro-

priate timer type in Section 22.0 “Electri-

cal Characteristics” of this document.

Note: For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits

are used for setup and control. Timer 2

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer3 interrupt flag

(T3IF), and the interrupt is enabled with

the Timer3 interrupt enable bit (T3IE).

dsPIC30F2010

FIGU RE 10-1: 32-BI T T IM E R2 /3 B LOC K DI AG RAM

TMR3 TMR2

T3IF

Equal Comparator x 32

PR3 PR2

Reset

LSB

MSB

Event Flag

Note: Timer Configuration bit T 32, T2CON(<3>) must be set to 1 f or a 32-bit timer/counter operation. All control

bits are respective to the T2CON register.

Data Bus<15:0>

TMR3HLD

Read TMR2

Write TMR2 16

TGATE(T2CON<6>)

(T2CON<6>)

TGATE

TON TCKPS<1:0>

Prescaler

1, 8, 64, 256

TCY

TCS

1 X

0 1

TGATE

0 0

Gate

T2CK

Sync

ADC Event Trigger

Sync

dsPIC30F2010

FIGURE 10-2: 16-BIT TIMER2 BL OCK DIA GRAM (TYPE B TIMER)

FIGURE 10-3: 16-BIT TIMER3 BL OCK DIA GRAM (TYPE C TIMER)

TON

Sync

PR2

T2IF

Equal Comparator x 16

TMR2

Reset

Event Flag

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

TCS

1 X

0 1

TGATE

0 0

Gate

T2CK

Sync

TON

PR3

T3IF

Equal Comparator x 16

TMR3

Reset

Event Flag

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

TCS

1 X

0 1

TGATE

0 0

ADC Event Trigger

Sync

See

NOTE

Note: The dsPIC30F2010 does not have an external pin input to TIMER3. The following modes should not be used:

1. TCS = 1

2. TCS = 0 and TGATE = 1 (gated time accumulation)

dsPIC30F2010

10.1 Timer Gate Operation

The 32-bi t timer can be pl aced in the Ga ted Ti me Accu-

mulation mode. This mode allows the internal TCY to

increm ent the respec tive timer when the gate input si g-

nal (T2CK pin) is asserted high. Control bit TGATE

(T2CO N<6>) mus t be set to en able this mode . When in

this mode, Timer2 is the originating clock source. The

TGATE setting is ignored for T imer3 . The timer must b e

enabled (TON = 1) and the timer clock source set to

internal (TCS = 0).

The falling edge of the external signal terminates the

count ope rati on, bu t does not res et the time r. The user

must reset the timer in order to start counting from zero.

10.2 ADC Event Trigger

When a matc h occurs betwe en the 32-bit timer (TM R3/

TMR2) and the 32-bit combined period register (PR3/

PR2), a special ADC trigger event signal is generated

by Timer3.

10.3 Timer Prescaler

The in put cloc k (FOSC/4 or external clock) to the timer

has a prescale option of 1:1, 1:8, 1:64, and 1:256

selected by control bits TCKPS<1:0> (T2CON<5:4>

and T3CON<5:4>). For the 32-bit timer operation, the

origina ting clock so urce is Timer2. Th e prescale r oper-

ation for Timer3 is not applicable in this mode. The

prescaler counter is cleared when any of the following

occurs:

• a write to the TMR2/TMR3 register

• clearing either of the TON (T2CON<15> or

T3CON<15>) bits to ‘0’

• device Reset such as POR and BOR

However, if the timer is disabled (TON = 0), then the

Timer 2 prescaler cannot be reset, since the prescaler

clock is halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is

written.

10.4 Timer Operation During Sleep

Mode

During CPU Sleep mode, the timer will not operate,

because the internal clocks are disabled.

10.5 Timer Interrupt

The 32-bit timer module can generate an interrupt on

period ma tch, or on the fa lling edge of the externa l gate

signal. When the 32-bit timer count matches the

respective 32-bit period register, or the falling edge of

the external “gate” signal is detected, the T3IF bit

(IFS0<7>) is asserted and an interrupt will be gener-

ated if enabled. In this mode, the T3IF interrupt flag is

used as the source of the interrupt. The T3IF bit must

be cleared in sof tw are.

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T3IE (IEC0<7>).

dsPIC30F2010

TABLE 10-1: TIMER2/3 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu

TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) uuuu uuuu uuuu uuuu

TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu

PR2 010C Period Register 2 1111 1111 1111 1111

PR3 010E Period Register 3 1111 1111 1111 1111

T2CON 0110 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS —0000 0000 0000 0000

T3CON 0112 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS —0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

NOTES:

dsPIC30F2010

11.0 INPUT CAPTURE MODULE

This section describes the Input Capture module and

associated operational modes. The features provided

by this module are useful in applications requiring Fre-

quency (Period) and Pulse measurement. Figure 11-1

depicts a block diagram of the Input Capture module.

Input capture is useful for such modes as:

• Frequency/Period/Pulse Measurements

• Additional source s of External Interrupts

The key operational features of the Input Capture

module are:

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

These operating modes are determined by setting the

appropriate bits in the ICxCON register (where x =

1,2,...,N). The dsPIC DSC devices contain up to 8

capture channels, (i.e., the maximum value of N is 8).

FIGURE 11-1: INPUT CAPTURE MODE BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: The dsPIC30F2010 device has four

capture inputs – IC1, IC2, IC7 and IC8.

The naming of these four capture chan-

nels is intentional and preserves software

compatibility with other dsPIC DSC

devices.

ICxBUF

Prescaler

ICx

ICM<2:0>

Mode Select

Note: Where ‘ x’ i s sh ow n, re fere nce is made to t he reg is ters o r bit s as soc ia ted to the res pe cti ve i npu t

capture ch annels 1 through N.

Set Flag

ICxIF

ICTMR

T2_CNT T3_CNT

Edge

Detection

Logic

Clock

Synchronizer

1, 4, 16

From General Purpose Timer Module

16 16

FIFO

R/W

Logic

ICI<1:0>

ICBNE, ICOV

ICxCON Interrupt

Logic

Set Flag

ICxIF

Data Bus

dsPIC30F2010

11.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product

family are:

• Capture every falling edge

• Capture every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by

setting the appropriate bits ICM<2:0> (ICxCON<2:0>).

11.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings, speci-

fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the

capture c hanne l is turn ed of f, the pr escal er coun ter will

be cleared. In addition, any Reset will clear the

prescaler counter.

11.1.2 CAPTURE BUFFER OPERATION

Each capture channel has an associated FIFO buffer,

which is four 16-bit words deep. There are two status

flags, which provide status on the FIFO buffer:

• ICBNE – Input Capture Buffer Not Empty

• IC OV – Input Capture Ov erfl ow

The ICBFNE will be set on the fir st input ca ptu r e event

and remain set until all capture events have been read

from the FIF O. As each word is read fro m the FIFO, th e

remaining words are advanced by one position within

the buffer.

In the event that the FIFO is full with four capture

events and a fifth capture event occurs prior to a read

of the FIFO, an overflow condition will occur and the

ICOV bit will be s et to a logic ‘1’. The fifth capture event

is lost and is not stored in the FIFO. No additional

events will be captured until all four events have been

read from the buffer.

If a FIFO read is performed after the last read and no

new capture event has been received, the read will

yield indeterminate results.

11.1.3 TIMER2 AND TIMER3 SELECTION

MODE

The inp ut capture modu le c onsist s of up to 8 input cap-

ture chann els. Each channel can select between on e of

two timers for the time base, Timer2 or Timer3.

Selection of the timer resource is accomplished

through SFR bit ICTMR (ICxCON<7>). Timer3 is the

default timer resource available for the input capture

module.

11.1.4 HALL SENSOR MODE

When the input capture module is set for capture on

every ed ge, risi ng and fal ling, ICM <2:0> = 001, the fol-

lowing operations are performed by the input capture

logic:

• The input capture interrupt flag is set on every

edge, rising and falling.

• The interrupt on Capture mode setting bits,

ICI<1:0>, is ignored, since every capture

generates an interrupt.

• A capture overflow condition is not generated in

this mode.

dsPIC30F2010

11.2 Input Capture Operation During

Sleep and Idle Modes

An input capture event will generate a device wake-up

or interrupt, if enabled, if the device is in CPU Idle or

Sleep mode.

Independent of the timer being enabled, the input

capture module will wake-up from the CPU Sleep or

Idle mode when a capture event occurs, if ICM<2:0> =

111 and the inte rrupt enab le bit is asserte d. The same

wake-u p can gen erate an int errupt, if the conditi ons for

processing the interrupt have been satisfied. The

wake-up feature is useful as a method of adding extra

external pin interrupts.

11.2.1 INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module opera-

tion with reduced functionality. In the CPU Sleep

mode, the ICI<1:0> bits are not applicable, and the

input capture module can only function as an external

inter rupt so urc e.

The capture module must be configured for interrupt

only on the rising edge (ICM<2:0> = 111), in order for

the input capture module to be used while the device

is in Sleep m ode. Th e pre scale s etting s of 4:1 or 16: 1

are not applicable in this mode.

11.2.2 INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle m ode, the interrupt

mode selected by the ICI<1:0> bits are applicable, as

well as the 4:1 and 16:1 capture prescale settings,

which are defined by control bits ICM<2:0>. This mode

requires the selected timer to be enabled. Moreover, the

ICSIDL bit must be asserted to a logic ‘0’.

If the input capture module is defined as ICM<2:0> =

111 in CPU Idle mode, the input capture pin will serve

only as an external interrupt pin.

11.3 Input Capture Interr upts

The inpu t captur e channe ls have the a bility to generate

an interrupt, based upon the selected number of cap-

ture even ts. The s ele cti on num be r is se t by c ont rol bits

ICI<1:0> (ICxCON<6:5>).

Each chan nel provide s an interrupt flag (ICxI F) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx status register.

Enabling an interrupt is accomplished via the respec-

tive capture channel interrupt enable (ICxIE) bit. The

capture interrupt enable bit is located in the

corresponding IEC Control register.

dsPIC30F2010

TABLE 11-1: INPUT CAPTURE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bi t 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu

IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC3BUF 0148 Input 3 Capture Register uuuu uuuu uuuu uuuu

IC3CON 014A ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC4BUF 014C Input 4 Capture Register uuuu uuuu uuuu uuuu

IC4CON 014E ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC5BUF 0150 Input 5 Capture Register uuuu uuuu uuuu uuuu

IC5CON 0152 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC6BUF 0154 Input 6 Capture Register uuuu uuuu uuuu uuuu

IC6CON 0156 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu

IC7CON 015A ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu

IC8CON 015E ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

12.0 OUTPUT COMPARE MODULE

This section describes the Output Compare module

and associated operational modes. The features pro-

vided by this module are use ful in applications requiring

operational modes such as:

• Generation of Variable Width Output Pulses

• Pow er Fact or Correction

Figure 12-1 depicts a block diagram of the Output

Compare module.

The key operational features of the Output Compare

module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare during Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting

the appropriate bit s in the 16-b it OCxCO N SFR (where

x = 1 and 2).

OCxRS and OCxR in the figure represent the Dual

Compare registers. In the Dual Compare mode, the

OCxR register is used for the f irst comp are and O CxRS

is used for the second compare.

FIGU RE 12-1: OUTPUT CO MP AR E MODE BL OC K DIAGR AM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

OCxR

Comparator

Output

Logic QS

OCM<2:0>

Output Enable

OCx

Set Fla g bit

OCxIF

OCxRS

Mode Select

Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channels 1and 2.

OCFA

OCTSEL 01

T2P2_MATCH

TMR2<15:0> TMR3<15:0> T3P3_MATCH

From General Purpose

(for x = 1 and 2)

Timer Module

dsPIC30F2010

12.1 Timer 2 and Timer3 Selec tion Mode

Each output compare channel can select between one

of two 16-bit timers: Ti mer2 or Timer3.

The selection of the timers is controlled by the OCTSEL

bit (OCxCON<3> ). T im er2 is the de fault ti mer reso urce

for the Output Compare module.

12.2 Simple Output Compare Match

Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 001,

010 or 011, the selected output compare channel is

configured for one of three simple Output Compare

Match modes:

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

The OCxR reg is ter i s us ed in th es e m ode s. Th e O C xR

selected incrementing timer count. When a compare

occurs, o ne of these C ompare Match modes oc curs. If

the counter resets to zero before reaching the value in

OCxR, the state of the OCx pin remains unchanged.

12.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100

or 101, the selec ted outp ut compare chan nel is co nfig-

ured for one of two Dual Output Compare modes,

which are:

• Single Output Pulse mode

• Conti nuous Output Pulse mode

12.3.1 SINGLE PULSE MODE

For the use r to confi gure the modul e for the ge ner ation

of a single output pulse, the following steps are

required (assuming timer is off):

• Determine instruction cycle time TCY.

• Calcu la te d es ired pulse w id t h v al ue bas ed on TCY.

• Calcu late ti me to s tart pulse from ti mer st a rt valu e

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS compare registers (x denotes

channel 1, 2).

• Set timer period register to value equal to, or

greater than, value in OCxRS compare register.

• Set OCM<2:0> = 100.

• Enable timer, TON (TxCON<15>) = 1.

To initiate another single pulse, issue another write to

set OCM<2:0> = 100.

12.3.2 CONTINUOUS PULSE MODE

For the use r to confi gure the modul e for the ge neratio n

of a continuous stream of output pulses, the following

steps are required:

• Determine instruction cycle time TCY.

• Calculate desired pulse value based on TCY.

• Calcu late timer to st art pulse width from timer sta rt

value of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS (x denotes channel 1, 2) compare

registers, respectively.

• Set timer period register to value equal to, or

greater than, value in OCxRS compare register.

• Set OCM<2:0> = 101.

• Enable timer, TON (TxCON<15>) = 1.

12.4 Simple PWM Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 110

or 111, the selec ted outp ut comp are c hannel is confi g-

ured for th e PWM mode of opera tion. When co nfigured

for the PWM mode of operation, OCxR is the main latch

(read-only) and OCxRS is the secondary latch. This

enables glitchless PWM transitions.

The user must perform the following steps in order to

configure the output compare module for PWM

operation:

1. Set the PWM pe riod by writing to the appropriate

period register.

2. Set the PWM duty cy cle by writ ing to the OCxRS

3. Configure the output compare module for PWM

operation.

4. Set the TMRx prescale value and enable the

Timer, TON (TxCON<15>) = 1.

12.4.1 INPUT PIN FAULT PROTECTION

FOR PWM

When control bits OCM<2:0> (OCxCON<2:0>) = 111,

the selected output compare channel is again config-

ured for the PWM mode of operation, with the

additional feature of input fault protection. While in this

mode, if a logic ‘0’ is detected on the OCFA/B pin, the

respect ive PWM outpu t pin is plac ed in the hig h-imped-

ance input state. The OCFLT bit (OCxCON<4>)

indicates whether a Fault condition has occurred. This

state will be maintained until both of the following

events have occurred:

• The external Fault condition has been removed.

• The PWM mode has been re-enabled by writing

to the appropriate control bits.

dsPIC30F2010

12.4.2 PWM PERIO D

The PWM peri od is spe cified by writing to the PRx reg-

ister. The PWM period can be calculated using

Equation 12-1.

EQUATION 12-1: PWM PERIOD

PWM frequency is defined as 1 / [PWM period].

When the selected TMRx is equal to its respective

period register, PRx, the following four events occur on

the next increment cycle:

• TMRx is cleared.

• The OCx pin is set.

- Exception 1: If PWM duty cycle is 0x0000,

the OCx pin will remain low.

- Exception 2: If duty cy cle is greater tha n PRx,

the pin will remain high.

• The PWM duty cycle is latched from OCxRS into

OCxR.

• The corresponding timer interrupt flag is set.

See Figure 12-1 for key PWM period comparisons.

Timer3 is referred to in the figure for clarity.

12.5 Output Compare Operation During

CPU Sleep Mode

When the CPU enters the Sleep mode, all internal

clocks are stopped. Therefore, when the CPU enters

the Sleep state, the output compare channel will drive

the pin to the active state that was observed prior to

entering the CPU Sleep state.

For example, if the pin was high when the CPU

entered the Sleep state, the pin will remain high. Like-

wise, if the pin was low when the CPU entered the

Sleep state, the pin will remain low. In either case, the

output compare module will resume operation when

the device wakes up.

12.6 Output Compare Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel will operate during the

CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at

logic ’ 0’ and the sel ected time ba se (Timer2 or Timer3)

is enabled and the TSIDL bit of the selected timer is

set to logic ‘0’.

FIGURE 12-1: PWM OUTPUT TIMING

12.7 Output Compare Interrupts

The outpu t compare channels ha ve the ability to gener-

ate an interrupt on a compare match, for whichever

Match mode has been selected.

For all modes except the PWM mode, when a compare

event occurs, the respective interrupt flag (OCxIF) is

asserte d an d an in terru pt w ill b e ge nerated, if ena ble d.

The OCxIF bit is located in the corresponding IFS

status register, and must be cleared in software. The

interrupt is enabled via the respective compare inter-

rupt enable (OCxIE) bit, located in the corresponding

IEC Control registe r.

For the PWM mode, when a n event occurs, the respec-

tive timer interrupt flag (T2IF or T3IF) is asserted and

an interrupt will be generated, if enabled. The IF bit is

located in the IFS0 st atus register, and m ust be cleared

in software. The interrupt is enabled via the respective

timer interrupt enable bit (T2IE or T3IE), located in the

IEC0 Control register. The output compare interrupt

flag is never set during the PWM mode of operation.

PWM period = [(PRx) + 1] • 4 • TOSC •

(TMRx prescale value)

Period

Duty Cycle

TMR3 = Duty Cycle (OCxR) TMR3 = Duty Cycle (OCxR)

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = PR3

(Interrupt Flag)

OCxR = OCxRS

T3IF = 1

dsPIC30F2010

TABLE 12-1: OUTPUT COMPARE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

OC1RS 0180 Output Compare 1 Master Register 0000 0000 0000 0000

OC1R 0182 Output Compare 1 Slave Register 0000 0000 0000 0000

OC1CON 0184 — OCFRZ OCSIDL — — — — — — — — OCFLT1 OCTSEL1 OCM<2:0> 0000 0000 0000 0000

OC2RS 0186 Output Compare 2 Master Register 0000 0000 0000 0000

OC2R 0188 Output Compare 2 Slave Register 0000 0000 0000 0000

OC2CON 018A — OCFRZ OCSIDL — — — — — — — — OCFLT2 OCTSEL2 OCM<2:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

13.0 QUADRATURE ENCODER

INTERFACE (QEI) MODULE

This section describes the Quadrature Encoder Inter-

face (QEI) module and associated operational modes.

The QEI module provides the interface to incremental

encoders for obtaining motor positioning data. Incre-

mental encoders are very useful in motor control

applications.

The Quadrature Encoder Interface (QEI) is a key fea-

ture require ment for several motor control applic ations,

such as Switched Reluctance (SR) and AC Induction

Motor (ACIM ). The opera tio nal fe atu r es of the QEI are,

but not limited to:

• Three input channels for two phase signals and

index pulse

• 16-bit up/down position counter

• Count direction status

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Quadrature Encoder Interface interrupts

These operating modes are determined by setting the

appropriate bits QEIM<2:0> (QEICON<10:8>).

Figure 13-1 depicts the Quadrature Encoder Interface

block dia gram .

FIGU RE 13-1: QUAD RATUR E ENCOD ER IN TERF ACE BL OCK DI AGRA M

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

16-bit Up/Dow n Co unter

Comparator/

Max C ount Registe r

Quadrature

Programmable

Di gita l Filter

Q EA

Programmable

Digital Filte r

INDX

Encoder

Programmable

Digital Filte r

QE B

Interface Logic

QEIM<2:0>

Mode Select

(POSCNT)

(MAXCNT)

QEIIF

Event

Flag

Reset

Equal

TQCS TQCKPS<1:0>

1, 8, 64, 256

Prescaler

TQGATE

QEIM<2:0>

Synchronize

Det

Sleep Inp ut

UPDN_SRC

QEICON<11> Zero De te ct

dsPIC30F2010

13.1 Quadrature Encoder Interface

Logic

A typica l in cre me nt a l (a.k .a . optical) enc ode r has three

outputs: Phase A, Phase B, and an index pulse. These

signals are useful and often required in position and

speed control of ACIM and SR motors.

The two chann els, Phase A (QEA) and Phase B (QEB),

have a unique relationship. If Phase A leads Phase B,

then the direction (of the motor) is deemed positive or

forward. If Phase A lags Phase B, then the direction (of

the motor) is deemed negative or reverse.

A third channel, termed index pulse, occurs once per

revolution and is used as a reference to establish an

absolute position. The index pulse coincides with

Phase A and Phase B, both low.

13.2 16-bit Up/Down Position Counter

Mode

The 16-bit Up/Down Counter counts up or down on

ever y count pulse, w hich is generat ed by t he dif ference

of the Phase A and Phase B input signals. The counter

acts as an integrato r , wh ose cou nt value is proporti onal

to position. The direction of the count is determined by

the UPDN signal, which is generated by the

Quadrat ure Enc ode r Interfac e Log ic.

13.2.1 POSITION COUNTER ERROR

CHECKING

Position c oun t e rror checkin g i n the Q EI i s p rov ide d for

and indic ated by the CNTERR bit (QEICO N<15>). The

error checking only applies when the position counter

is configured for Reset on the Index Pulse modes

(QEIM<2:0> = ‘110’ or ‘100’). In these modes, the

contents of the POSCNT register is compared with the

values (0xFFFF or MAXCNT + 1, depen din g on direc -

tion) . If the se values are de tec ted , an e rror c ond ition is

generated by setting the CNTERR bit and a QEI count

error interrupt is generated. The QEI count error

interrupt can be disabled by setting the CEID bit

(DFLTCON<8>). The position counter continues to

count enc oder edg es after an err or has been detected.

The POSCNT register continue s to count up/do wn until

a natural rollover/underflow. No interrupt is generated

for the natural rollover/underflow event. The CNTERR

bit is a read/write bit and reset in software by the user.

13.2.2 POSITION COUNTER RESET

The Position Counter Reset Enable bit, POSRES

(QEI<2>) c ontrol s wheth er the position co unter i s reset

when the index pulse is detected. This bit is only

applicable when QEIM<2:0> = ‘100’ o r ‘110’.

If the POSRES bit is se t to ‘1’, then the posi tion count er

is reset when the index pulse is detected. If the

POSRES bit is set to ‘0’, then the position counter is not

reset when the index pulse is detected. The position

counter will continue counting up or down, and will be

reset on the rollover or underflow condition.

When selecting the INDX signal to reset the position

counter (POSCNT), the user has to specify the states

on QEA and QEB input pins. These states have to be

matched in order for a reset to occur. These states are

selected by the IMV<1:0> bit in the DFLTCON <10:9>

The IMV<1:0> (Index Match Value) bit allows the user

to specify the state of the QEA and QEB input pins

during an index pulse when the POSCNT register is to

be reset.

In 4X Quadrature Count Mode:

IMV1 = Required state of phase B input signal for

match on index pulse

IMV0 = Required state of phase A input signal for

match on index pulse

In 2X Quadrature Count Mode:

IMV1 = Selects phase input signal for index state

match (

= Phase A,

= Phase B)

IMV0 = Required state of the selected phase input

signal for mat ch on ind ex pulse

The interrupt is still generated on the detection of the

index pulse and not on the position counter overflow/

underflow.

13.2.3 COUNT DIRECTION STATUS

As mentioned in the previous section, the QEI logic

generates an UPDN signal, based upon the relation-

ship between Phase A and Phase B. In addition to the

output pin, the state of this internal UPDN signal is

supplied to a SFR bit UPDN (QEICON<11>) as a read-

only bit.

Note: QEI pins are multiplexed with analog

inputs. User must insure that all QEI asso-

ciated pins are set as digital inputs in the

ADPCFG register.

dsPIC30F2010

13.3 Position Measurement Mode

There are two Measurement modes which are sup-

ported and are termed x2 and x4. These modes are

select ed by the QEIM <2:0> mo de selec t bit s locate d in

SFR QEICON<10:8>.

When control bits QEIM<2:0> = 100 or 101, the x2

Measurement mode is selected and the QEI logic only

looks at the Phase A input for the position counter

increment rate. Every rising and falling edge of the

Phase A s ignal caus es the po sition c ounter to b e incre-

mented or decremented. The Phase B signal is still

utilized for the determination of the counter direction,

just as in the x4 mode.

Within the x2 Measurement mode, there are two

variations of how the position counter is reset:

1. Position counter reset by detection of index

pulse, QEI M<2 :0> = 100.

2. Position counter reset by match with MAXCNT,

QEIM<2:0> = 101.

When control bits QEIM<2:0> = 110 or 111, the x4

Measur ement mode i s selected and the QE I logic looks

at both edges of the Phase A and Phase B input sig-

nals. Every edge of both signals causes the position

counter to increment or decrement.

Within the x4 Measurement mode, there are two

variations of how the position counter is reset:

1. Position counter reset by detection of index

pulse, QEI M<2 :0> = 110.

2. Position counter reset by match with MAXCNT,

QEIM<2:0> = 111.

The x4 Measurement mode provides for finer resolu-

tion data (more position counts) for determining motor

position.

13.4 Programmable Digital Noise

Filters

The digital noise filter section is responsible for reject-

ing noise on the incoming capture or quadrature sig-

nals. Schmitt Trigger inputs and a three-clock cycle

delay filter combine to reject low level noise and large,

short duration nois e s pik es tha t ty pic al ly occ ur i n n ois e

prone applications, such as a motor system.

The filter ensures that the filtered output signal is not

permitted to change until a stable value has been

registered for three consecutive clock cycles.

For the QEA, QEB an d IN DX pin s, the c lock d iv ide fre-

quency for the digital filter is programmed by bits

QECK<2:0> (DFLTCON<6:4>) and are derived from

the base instruction cycle TCY.

To enable the filter output for channels QEA, QEB and

INDX, the QEOUT bit must be ‘1’ . The f ilt er netwo rk for

all channels is disabled on POR and BOR.

13.5 Alternate 16-bit Timer/Counter

When the QEI module is not configured for the QEI

mode QEIM<2:0> = 001, the modu le can be confi gured

as a sim ple 16-bit timer/c ou nte r. The setup and co ntro l

of the auxiliary timer is accomplished through the

QEICON SFR register. This timer functions identically

to T imer1. The QEA pin is used as the timer clock input.

When configured as a timer, the POSCNT register

serves as the Timer Count Register and the MAXCNT

period register match occur, the QEI interrupt flag will

be asserted.

The only exception between the general purpose tim-

ers and this timer is the added feature of external Up/

Down input select. When the UPDN pin is asserted

high, the timer will increment up. When the UPDN pin

is asserted low, the timer will be decremented .

The UPDN control/status bit (QEICON<11>) can be

used to select the co unt direction st ate of the T imer reg-

ister. When UPDN = 1, the timer will count up. When

UPDN = 0, the timer will count down.

In addition, control bit UPDN_SRC (QEICON<0>)

determines whether the timer count direction state is

based o n the l ogi c st ate, writte n into the UP DN co ntrol/

status bit (QEICON<11 >), or the QEB pin state. When

UPDN_SRC = 1, the timer coun t dire ct ion is co ntro lle d

from the QEB pin. Likewise, when UPDN_SRC = 0, the

timer count direction is controlled by the UPDN bit.

13.6 QEI Module Operation During CPU

Sleep Mode

13.6.1 QEI OPERATION DURING CPU

SLEE P MOD E

The QEI module will be halted during the CPU Sleep

mode.

13.6.2 TIMER OPERATION DURING CPU

SLEE P MOD E

During CPU Sleep mode, the timer will not operate,

because the internal clocks are disabled.

Note: Changing the Operational mode (i.e., from

QEI to Timer or vice versa), will not affect

the Timer/Position Count Register

contents.

Note: This Timer does not support the External

Asynchronous Counter mode of operation.

If using an exte rnal cloc k sourc e, the cl ock

will automatically be synchronized to the

internal instruction cycle.

dsPIC30F2010

13.7 QEI Module Operation During CPU

Idle Mode

Since the QEI module can function as a quadrature

encoder interface, or as a 16-bit timer, the following

section describes operation of the module in both

modes.

13.7.1 QEI OPERATION DURING CPU IDLE

MODE

When the CPU is placed in the Idle mode, the QEI

module will operate if the QEISIDL bit (QEICON<13>)

= 0. This bit de fau lts to a logic ‘0’ upon executing POR

and BOR. For halting the QEI module during the CPU

Idle mode, QEISIDL should be set to ‘1’.

13.7.2 TIMER OPERATION DURING CPU

IDLE MODE

When the CPU is placed in the Idle mode and the QEI

module is configured in the 16-bit Timer mode, the

16-bit timer will operate if the QEISIDL bit

(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon

execut ing POR a nd BO R. F or halting the ti me r mo dul e

during the CPU Idle mode, QEISIDL should be set

to ‘1’.

If the QEISIDL bit is cleared, the timer will function

normally, as if the CPU Idle mode had not been

entered.

13.8 Quadrature Encoder Interface

Interrupts

The quadrature encoder interface has the ability to

generate an interrupt on occurrence of the following

events:

• Inter rupt on 16-bit up/down position counter

rollover/underflow

• Detection of qualified index pulse, or if CNTERR

bit is set

• Timer period match event (overflow/underflow)

• Gate accumulation event

The QEI interrupt flag bit, QEIIF, is asserted upon

occurrence of any of the above events. The QEIIF bit

must be cleared in software. QEIIF is located in the

IFS2 status register.

Enabling an interrupt is accomplished via the respec-

tive enable bit, QEIIE. The QEIIE bit is located in the

IEC2 Control register.

dsPIC30F2010

TABLE 13-1: QEI REGISTER MAP

SFR

Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB — TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 0000 0000 0000

DFLTCON 0124 — — — — — IMV1 IMV0 CEID QEOUT QECK2 QECK1 QECK0 — — — — 0000 0000 0000 0000

POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000

MAXC NT 0128 Maxim un Coun t<15:0> 1111 1111 1111 1111

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

NOTES:

dsPIC30F2010

14.0 MOTOR CONTROL PWM

MODULE

This module simplifies the task of generating multiple,

synchronized Pulse Width Modulated (PWM) outputs.

In particular, the following power and motion control

applications are supported by the PWM module:

• Three Phase AC Inducti on Motor

• Switched Reluctance (SR) Motor

• Brushless DC (BLDC) Motor

• Uninterruptible Power Supply (UPS)

The PWM module has the following features:

• 6 PWM I/O pins with 3 duty cycle generators

• Up to 16-bit resolution

• ‘On-the-Fly’ PWM frequency changes

• Edge and Center-Aligned Output modes

• Single Pulse Generation mode

• Interrupt support for asymmetrical updates in

Center-Aligned mode

• Output override control for Electrically

Commutative Motor (ECM) operation

• ‘Special Event’ comparator for scheduling other

peripheral events

•FLTA

pins to optionally drive each of the PWM

output pins to a defined state

This module contains 3 duty cycle generators, num-

bered 1 through 3. The modul e has 6 PW M output p ins,

numbere d PWM1 H/PWM 1L throu gh PWM 3H/PWM3 L.

The six I/O pins are grouped into high/low numbered

pairs, denoted by the suffix H or L, respectively. For

complementary loads, the low PWM pins are always

the complement of the corresponding high I/O pin.

A simplified block diagram of the Motor Control PWM

modules is shown in Figure 14-1.

The PWM module allows several modes of operation

which are beneficial for specific power control

applications.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

dsPIC30F2010

FIGU RE 14-1 : PWM B LOC K DI AG R AM

PDC3

PDC3 Buffer

PWMCON1

PTPER Buffer

PWMCON2

PTPER

PTMR

Comparator

Channel 3 Dead-Time

Generator and

PTCON

SEVTCMP

Comparator Special Event Trigger

FLTACON

OVDCON

PWM Enable and Mode SFRs

FLTA Pin Control SFR

PWM Manual

Channel 2 Dead-Time

Generator and

Channe l 1 Dead - Tim e

Generator and

PWM Generat or

PWM Generator

PWM Generator #3

SEVTDIR

PTDIR

DTCON1 Dead-Time Control SFR

Special Event

Postscaler

FLTA

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

16-bit Dat a Bus

Override Logic

Control SF R

PWM Time Base

Output

Driver

Block

Note: Details of PWM Generator #1 and #2 not shown for clarity.

dsPIC30F2010

14.1 PWM Time Base

The PWM time base is provided by a 15-bit timer with

a pr escaler and postsc aler . The time base is acce ssible

via the PTMR SFR. PTMR<15> is a read-only status

bit, P TDIR, tha t indic ates th e present c ount dir ection of

the PWM time base. If PTDIR is cleared, PTMR is

counting upwards. If PTDIR is set, PTMR is counting

downwards. The PWM time base is configured via the

PTCON SFR. The time base is enabled/disabled by

setting/clearing the PTEN bit in the PTCON SFR.

PTMR is not cleared when the PTEN bit is cleared in

software.

The PTPER SFR sets the counting period for PTMR.

The user must write a 15-bit value to PTPER<14:0>.

When the value in PTMR<14:0> matches the value in

P TPER<14:0> , the time ba se will ei ther Reset to ‘0’, or

reverse the count direction on the next occurring clock

cycle. The action taken depends on the Operating

mode of the time base.

The PWM time base can be configured fo r four different

modes of opera tion:

• Free Running mode

• Single Shot mode

• Continuous Up/Down Count mode

• Continuous Up/Down Count mode with interrupts

for double updates

These four modes are selected by the PTMOD<1:0>

bits in the PT CON SFR. The Up/Down Counting modes

support center-aligned PWM generation. The Single

Shot mode allows the PWM module to support pulse

control of certain Electronically Commutative Motors

(ECMs).

The interrupt sig nal s ge nerated by the PWM t im e bas e

depend on the mode sele ction bit s (P TMOD<1:0>) and

the post sca ler bit s (P T OPS <3:0>) in the PT CON SFR.

14.1.1 FREE RUNNING MODE

In the Fre e Run nin g mo de, the PWM time b as e co unts

upwards until the value in the Time Base Period regis-

ter (P TPER) is match ed. The P TMR regi ster is reset o n

the following input clock edge and the time base will

continue to count upwards as long as the PTEN bit

remains set.

When the PWM time base is in t he Free Run ning mod e

(PTMOD<1:0> = 00), an interrupt event is generated

each tim e a m atch wi th the P TPER reg ister o ccurs an d

the PTMR register is Reset to zero. The postscaler

selectio n bi ts m ay b e us ed i n thi s mode of th e timer t o

reduce the frequency of the interrupt events.

14.1.2 SINGLE-SHOT MODE

In the Single-S hot Counti ng m ode, t he PWM tim e base

begins counting upwards when the PTEN bit is set.

When the value in the PTMR register matches the

P TPER reg is ter, the P TM R regi st er w il l be res et o n th e

following input clock edge and the PTEN bit will be

cleared by the hardware to halt the time base.

When the PWM time base is in the Single-Shot mode

(PTMOD<1:0> = 01), an interrupt event is generated

when a match with the PTPER register occurs, the

PTMR register is reset to zero on the following input

clock edge, and the P TEN bit is cleared. The postscaler

selection bits have no effect in this mode of the timer.

14.1.3 CONTINUOUS UP/DOWN

COUNTING MODES

In the Continuous Up/Down Counting modes, the PWM

time bas e count s upwar ds until th e value in the PTPER

downwards on the following input clock edge. The

PTDIR bit in the PTCON SFR is read-only and indi-

cates the counting direction The PTDIR bit is set when

the timer counts downwards.

In the Up/Down Counting mode (PTMOD<1:0> = 10),

an interrupt event is generated each time the value of

the PTMR register becomes zero and the PWM time

base begins to count upwards. The postscaler selec-

tion bit s may be used in this mode of the timer to reduce

the frequency of the interrupt events.

Note: If the period register is set to 0x0000, the

timer will stop counting, and the interrupt

and the special event trigger will not be

generated, even if the special event value

is also 0x0000. The module will not update

the period register if it is already at

0x0000; therefore, the user must disable

the module in order to update the period

dsPIC30F2010

14.1.4 DOUBLE UPDATE MODE

In the Double Update mode (PTMOD<1:0> = 11), an

inter rupt event is generated each time the PTM R regis-

ter is eq ual to zero, as well as each time a pe riod match

occur s. Th e postsc aler se lecti on bits ha ve no effect in

this mode of the timer.

The Do uble Update mo de provides two addition al func-

tions to the user. First, the control loop bandwidth is

doubled because the PWM duty cycles can be

updat ed, twi ce p er pe riod . S econd , a symme tric al c en-

ter-aligned PWM waveforms can be generated, which

are useful for minimizing output waveform distortion in

certain motor control applications.

14.1.5 PW M TIME BA SE PRES CA LER

The input clock to PTMR (FOSC/4), has prescaler

options of 1:1, 1:4, 1:16 or 1:64, s elected by con trol bits

PTCKPS<1:0> in the PTCON SFR. The prescaler

counter is cleared when any of the following occurs:

• a write to the PTMR register

• a write to the PTCON register

• any devic e Re se t

The PTMR register is not cleared when PTCON is

written.

14.1.6 PWM TIME BASE POSTSCALER

The match output of PTMR can optionally be post-

scaled through a 4-bit postscaler (which gives a 1:1 to

1:16 scaling).

The postscaler counter is cleared when any of the

following occurs:

• a write to the PTMR register

• a write to the PTCON register

• any devic e Re se t

The PTMR register is not cleared when PTCON is written.

14.2 PWM Period

PTPER is a 15-bit register and is used to set the count-

ing period for the PWM time base. PTPE R is a double-

buffered register. The PTPER buffer contents are

loaded into the PTPER register at the following

instances:

• Free Running and Single Shot modes: When the

PTMR register is reset to zero after a match with

the PTPER register.

• Up/Down Counting modes: When the PTMR

The value held in the PTPER buffer is automatically

loaded into the PTPER register when the PWM time

base is disabled (PTEN = 0).

The PWM period can be determined using

Equation 14-1:

EQUATION 14-1: PWM PERIOD

If the PWM time base is configured for one of the Up/

Down Count modes, the PWM period is found using

Equation 14-2.

EQUATION 14-2: PWM PERIOD (UP/DOWN

COUNT MODE)

The maximum resolution (in bits) for a given device

oscillator and PWM frequency can be determined using

Equation 14-3:

EQUATION 14-3: PWM RESOLUTION

Note: Programming a value of 0x0001 in the

period register could generate a continu-

ous interrupt pulse, and hence, must be

avoided.

TPWM = TCY • (PTPER + 1)

(PTMR Prescale Value)

TPWM = TCY • 2 • (PTPER + 0.75)

(PTMR Prescale Value)

Resolution = log (2 • TPWM / TCY)

log (2)

dsPIC30F2010

14.3 Edge-Aligned PWM

Edge-aligned PWM signals are produced by the module

when the PWM time base is in the Free Running or Sin-

gle Shot mode. For edge-aligned PWM outputs, the out-

put has a period specified by the value in PTPER and a

duty cycle specified by the appropriate duty cycle regis-

ter (see Figure 14-2). The PWM output is driven active

at the beginning of the period (PTMR = 0) and is driven

inactive when the value in the duty cycle register

matches PTMR.

If the value in a particular duty cycle register is zero,

then the output on the corresponding PWM pin will be

inactiv e for the en tire PWM p erio d. In add iti on, the out-

put on the PWM pin will be active for the entire PWM

period if the value in the duty cycle register is greater

than the value held in the PTPER register.

FIGURE 14-2: EDGE-ALIGNED PWM

14.4 Center-Aligned PWM

Center-a ligned PWM sign als are produc ed by the mo d-

ule when the PWM time base is configured in an Up/

Down Coun ting mode (see Figure 14-3).

The PWM compare output is driven to the active state

when the value of the duty cycle register matches the

value of PTMR and the PWM time base is counting

downwards (PTDIR = 1). The P W M compa r e o utp ut is

drive n to the inacti ve st ate w hen th e PWM ti me bas e is

counting upwards (PTDIR = 0) and the value in the

PTMR register matches the duty cycle value.

If the value in a particular duty cycle register is zero,

then the output on the corresponding PWM pin will be

inactiv e for the entire PWM period. In additi on, the out-

put on the PWM pin will be active for the entire PWM

period if the value in the duty cycle register is equal to

the value held in the PTPER register.

FIGU RE 14- 3: CENTER- ALIGN ED PWM

14.5 PWM Duty Cycle Comparison

Units

There are four 16-bit Special Function Registers

(PDC1, PDC2, PDC3 and PDC4) used to specify duty

cycl e values for the PWM module.

The value in each duty cycle register determines the

amount of time that the PWM output is in the active

state. The duty cycle registers are 16 bits wide. The

LSb of a duty cycle register determines whether the

PWM edge occurs in the beginning. Thus, the PWM

resolution is effectively doubled.

Period

Duty Cycle

PTPER

PTMR

Value

New Duty Cycle Latched

PTPER PTMR

Value

Period

Period/2

Duty

Cycle

dsPIC30F2010

14.5.1 DUTY CYCLE REGISTER BUFFERS

The four PWM duty cycle regi sters are double-buf fered

to allow glitchless updates of the PWM outputs. For

each duty cycle, there is a duty cycle register that is

acces sible by the us er and a sec ond duty cyc le register

that holds the actual comp are value used in the pre sent

PWM period.

For edge-aligned PWM output, a new duty cycle value

will b e updated whene ver a match with the PTPER reg-

ister occurs and PTMR is reset. The contents of the

duty cycle buffers are automatically loaded into the

duty cycle registers when the PWM time base is dis-

abled (PTEN = 0) and the UDIS bit is cleared in

PWMCON2.

When the PWM time base is in the Up/Down Counting

mode, new duty cycle values are updated when the

value of the PTMR register is zero and the PWM time

base b egins to c ount upwa rds. The co ntents o f the duty

cycle buffers are automatically loaded into the duty

cycle registers when the PWM time base is disabled

(PTEN = 0).

When the PWM time base is in the Up/Down Counting

mode w ith do uble updat es, new duty c ycle va lues are

updated when the value of the PTMR register is zero,

and when the value of the PTMR register matches the

value in the PTPER register. The contents of the duty

cycle buffers are automatically loaded into the duty

cycle registers when the PWM time base is disabled

(PTEN = 0).

14.6 Complementary PWM Operation

In the Complementary mode of operation, each pair of

PWM outputs is obtained by a complementary PWM

signal. A dead time may be optionally inserted during

dev ice swi tchin g, whe n bot h out puts ar e inac tiv e for a

short period (Refer to Section 14.7 “Dead-Time Gen-

erators”).

In Complementary mode, the duty cycle comparison

units are assigned to the PWM outputs as follows:

• PDC1 register controls PWM1H/PWM1L outputs

• PDC2 register controls PWM2H/PWM2L outputs

• PDC3 register controls PWM3H/PWM3L outputs

The Complementary mode is selected for each PWM

I/O pin pair by clearing the appropriate PMODx bit in the

PWMCON1 SFR. The PWM I/O pins are set to

Complementary mode by default upon a device Reset.

14.7 Dead-Time Generators

Dead-time generation may be provided when any of

the PWM I/O pin pairs are operating in the Comple-

mentary Output mode. The PWM outputs use Push-

Pull drive ci rcui ts. Due to the inabili ty of the pow e r out-

put devic es to sw it ch in stantaneously, some amount of

time must be provided between the turn off event of one

PWM output in a complementary pair and the turn on

event of the other transistor.

14.7.1 DEAD-TIME GENERATORS

Each complementary output pair for the PWM module

has a 6-bit down counter that is used to produce the

dead-time insertion. As shown in Figure 14-4, the

dead-time unit has a rising and falling edge detector

connected to the duty cycle comparison output.

14.7.2 DEAD-TIME RANGES

The amount of dead time provided by the dead-time

unit is selected by specifying the input clock prescaler

value and a 6-bit unsigned value.

Four input clock prescaler selections have been pro-

vided to allow a su itable range of dead t imes, bas ed on

the device operating frequency. The dead-time clock

prescal er value is selec ted usi ng the DTAPS<1:0> and

DTBPS<1:0> control bits in the DTCON1 SFR. One of

four clock prescaler options (TCY, 2TCY, 4TCY or 8TCY)

is selected for the dead-time value.

After the prescaler value is selected, the dead time is

adjusted by loading a 6-bit unsigned value into the

DTCON1 SFR.

The dead-ti me unit prescaler is cleared on the following

events:

• On a load of the down timer due to a duty cycle

comparison edge event.

• On a write to the DTCON1 register.

• On any device Reset.

Note: The user should not modify the DTCON1

values while th e PWM modu le is opera ting

(PTEN = 1). Unexpected results may

occur.

dsPIC30F2010

FIGURE 14-4: DEAD-TIME TIMING DIAGRAM

14.8 Independent PWM Output

An indepen dent PWM Output mode is require d for driv-

ing certain types of loads. A particular PWM output pair

is in the Independent Output mode when the corre-

sponding PMOD bit in the PWMCON1 register is set.

No dead-time control is implemented between adjacent

PWM I/O pins when the module is operating in the

Indepen dent mode and b oth I/O pin s a r e al lowe d to b e

active simultaneously.

In the Ind ependent mod e, e ach du ty c yc le gen era tor i s

connected to both of the PWM I/O pins in an output

pair. By using the associated duty cycle register and

the appropriate bits in the OVDCON register, the user

may select the following signal output options for each

PWM I/O pin operating in the Independent mode:

• I/O pin outputs PWM signal

• I/O pi n inactive

• I/O pin active

14.9 Single Pulse PWM Operation

The PWM m odule pr odu ce s si ngle pulse outputs w he n

the P TCON co ntrol bits PTMOD<1: 0> = 10. Only edge-

aligned outputs may be produced in the Single Pulse

mode. In Single Pulse mode, the PWM I/O pin(s) are

driven to the active state when the PTEN bit is set.

When a match with a duty cycle register occurs, the

PWM I/O pin is driven to the inactive state. When a

match with the PTPER register occurs, the PTMR reg-

ister is cleared, all active PWM I/O pins are driven to

the inactive state, the PTEN bit is cleared, and an

inter rupt is genera ted .

14.10 PWM Output Override

The PWM output override bits allow the user to manu-

ally drive the PWM I/O pins to specified logic states,

independent of the duty cycle comparison units.

All control bits associated with the PWM output over-

ride function are contained in the OVDCON register.

The upper half of the OVDCON register contains six

bits , POVDxH<3:1> and POVDxL<3 :1>, that de termine

which PWM I/O pins will be overridden. The lower half

of the OVDCON register contains six bits,

POUTxH<3:1> and POUTxL<3:1>, that determine the

state of the PWM I/O pins when a particular output is

overridden via the POVD bits.

14.10.1 COMPLEMENTARY OUTPUT MODE

When a PWMxL pin is driven active via the OVDCON

ment of the corresponding PWMxH pin in the pair.

Dead-time insertion is still performed when PWM

channel s are overridden manu all y.

14.10.2 OVERRIDE SYNCHRONIZATION

If the OSYNC bit in the PWMCON2 register is set, all

output overrides performed via the OVDCON register

are sync hro ni zed to the PWM tim e b ase. Sy nc hron ou s

output overrides occur at the following times:

• Edge-Aligned mode, when PTMR is zero.

• Center-Aligned modes, when PTMR is zero and

when the value of PTMR matches PTPER.

Duty Cycle Generator

PWMxH

PWMxL

dsPIC30F2010

14.11 PWM Output and Polarity Cont rol

There are three device Configuration bits associated

with the PWM module that provide PWM output pin

control:

• HPOL Configuration bit

• LPOL Configuration bit

• PWMPIN Configuration bit

These th ree b its in the F P ORBO R C on figu r ati on re gi s-

ter ( see Secti on 2 1) wo rk i n co njun cti on wi th t he t hree

PWM enable bits (PWMEN<3:1>) located in the

PWMCON1 SFR. The Configuration bits and PWM

enable b its ens ure that the PWM pins are in the correct

states after a device Reset occurs. The PWMPIN con-

figuration fuse allows the PWM module outputs to be

opti on al ly en ab l ed on a de vi ce R e set . If P WMP I N = 0,

the PWM outputs will be driven to their inactive states

at Reset. If PWMPIN = 1 (default), the PWM outputs

will be tri-st ate d. The HPOL bit speci fies the polarity for

the PWMxH outputs, whereas the LPOL bit specifies

the polarity for the PWMxL outputs.

14.11.1 OUTPUT PIN CONTROL

The PEN<3:1>H and PEN<3:1>L control bits in the

PWMCON1 SFR enable each high PWM output pin

and each low PWM output pin, respectively. If a partic-

ular PWM output pin not enabled, it is treated as a

general purpose I/O pin.

14.12 PWM FLTA Pins

There is one FL T A pin (FL T A ) associated with the PWM

module. When asserted, this pin can optionally drive

each of the PWM I/O pins to a defined state.

14.12.1 FAULT PIN ENABLE BITS

The FLTACON SFR has 4 control bits that determine

whether a particular pair of PWM I/O pins is to be con-

trolled b y the FLTA input pin. To enable a specific PW M

I/O pin pair for FLTA overrides, the corresponding bit

should be set in the FLTACON register.

If all enable bits are cleared in the FLTACON register,

then the FLT A input p in has no ef fect on the PWM mo d-

ule and the pin may be used as a general purpose

interrupt or I/O pin.

14.12.2 FAULT STATES

The FLTACON special function register has 8 bits that

determine the state of each PWM I/O pin when it is

overridden by a FLTA input. When these bits are

cleared , the PW M I/O pin is dri ven to the inact ive s tat e.

If the bit is set, the PWM I/O pin will be driven to the

active state. The active and inactive states are refer-

enced to the polarity defined for each PWM I/O pin

(HPOL and LPOL polarity control bits).

14.12.3 FAULT INPUT MODES

The FLTA input pin has two modes of operation:

•Latched Mode: When the FLTA pin is driven low,

the PWM outputs will go to the states defined in

the FLTACON register. The PWM outputs will

remain in this state until the FLTA pin is driven

high and the corresponding interrupt flag has

been cleared in software. When both of these

actions have occurred, the PWM outputs will

return to normal operation at the beginning of the

next PWM cycle or half-cycle boundary. If the

interrupt flag is cleared before the FLTA condition

ends, the PWM module will wait until the FLT A pin

is no longer as sert ed to r estore the out puts.

•Cycle-by-Cycle Mode: When the FLTA input pin

is driven low, the PWM outputs remain in the

defined FLTA s t ate s for as lo ng as the FLTA pin is

held low. After the FLTA pin is driven high, the

PWM outputs return to normal operation at the

beginning of the following PWM cycle or

half-cycle boundary.

The Operating mode for the FLTA input pin is selected

using the FLTAM control bit in the FLTACON Special

Function Regi ster.

The FLTA pin can be controlled manually in software.

14.13 PWM Update Lockout

For a comple x PWM appli ca tio n, the user ma y nee d to

write up to four duty cy cle regi sters an d the time base

period reg ister, P T PER, at a gi ven time. In som e a ppl i-

cations , it is import ant that all buf fer re gisters be writte n

before th e new duty c ycle and perio d values are loaded

for use by the module.

The PWM update lockout feature is enabled by setting

the UDIS co ntro l bi t in the PWMCON2 SFR . Th e UD IS

bit affects all duty cycle buffer registers and the PWM

time base period buffer, PTPER. No duty cycle

changes or pe riod value ch anges will hav e effect w hil e

UDIS = 1.

Note: The FLTA pin logic can operate indepen-

dent of the PWM logic. If al l the enable bit s

in the FL TACON register are cleared, then

the FLTA pin(s) could be used as general

purpose interrupt pin(s). Each FLTA pin

has an interrupt vector, interrupt flag bit

and interrupt priority bits associated with it.

dsPIC30F2010

14.14 PWM Special Event Trigger

The PWM module has a special event trigger that

allows A/D conversions to be synchronized to the PWM

time bas e. The A/D sa mplin g an d convers ion ti me ma y

be programmed to occur at any point within the PWM

period. The special event trigger allows the user to min-

imize th e delay betwee n the time whe n A/D conversio n

results are acquired, and the time when the duty cycle

value is updat ed.

The PWM special event trigger has an SFR named

SEVTCMP, and five co ntrol b its to control it s opera tion.

The PTMR value for which a special event trigger

should occur is loaded into the SEVTCMP register.

When the PWM time base is in an Up/Down Counting

mode, an addi tional c ontrol b it is r equired t o sp ecify th e

counting phase for the special event trigger. The count

phase is selected using the SEVTDIR control bit in the

SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe-

cial event trigger will occur on the upward counting

cycle of the PWM time base. If the SEVTDIR bit is set,

the special event trigger will occur on the downward

count cycle of the PWM time base. The SEVTDIR

control bit has no effect unless the PWM time base is

configured for an Up/Down Counting mode.

14.14.1 SPECIAL EVENT TRIGGER

POSTSCALER

The PWM special event trigger has a postscaler that

allows a 1:1 to 1:16 postscale ratio. The postscaler is

configured by writing the SEVOPS<3:0> control bits in

the PWMCON2 SFR.

The special event output postscaler is cleared on the

following events:

• Any write to the SEVTCMP register

• Any device Reset

14.15 PWM Operation During CPU Sleep

Mode

The FLTA A and FLTA B input pins have the ability to

wake the CPU from Sleep mode. The PWM module

generates an interrupt if either of the FLTA pins is

driven low while in Sleep.

14.16 PWM Operation During CPU Idle

Mode

The PTCON SFR contains a PTSIDL control bit. This

bit determines if the PWM module will continue to

operate or stop when the device enters Idle mode. If

PTSIDL = 0, the module will continue to operate. If

PT S IDL = 1, the module will stop operation as long as

the CPU remains in Idle mode.

dsPIC30F2010

TABLE 14-1: PWM REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

PTCON 01C0 PTEN —PTSIDL ————— PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000

PTMR 01C2 PTDIR PWM Timer Cou nt Value 0000 0000 0000 0000

PTPER 01C4 — PWM Time Base Period Register 0011 1111 1111 1111

SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000

PWMCON1 01C8 — — — — — PTMOD3 PTMOD2 PTMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L 0000 0000 0111 0111

PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — — OSYNC UDIS 0000 0000 0000 0000

DTCON1 01 CC DTBPS<1:0> DTB<5:0> DTAPS<1 :0> Dead Time A Value 0000 0000 0000 0000

FLTACON 01D0 —— FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1 0000 0000 0000 0000

OVDCON 01D4 —— POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L —— POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000

PDC1 01D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000

PDC2 01D8 PWM Duty Cycle #2 Register 0000 0000 0000 0000

PDC3 01DA PWM Duty Cycle #3 Register 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

15.0 SPI MODULE

The Serial Peripheral Interface (SPI) module is a syn-

chronou s serial inte rface. It is usefu l for commun icating

with other peripheral devices such as EEPROMs, shift

registers, display drivers and A/D converters or other

microcontrollers. It is compatible with Motorola's SPI

and SIOP interfaces.

15.1 Operating Function Description

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in

and out, and a buffer register, SPIxBUF. A control reg-

ister, SPIxCON, configures the module. Additionally, a

status register, SPIxSTAT, indicates various status

conditions.

The serial interface consists of 4 pins: SDIx (serial

data input), SDOx (serial data output), SCKx (shift

clock input or output) and SSx (active-low slave

select).

In Master mode operation, SCK is a clock output, but

in Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shifts

out bits from the SPIxSR to SDOx pin and simulta-

neously shifts in data from SDIx pin. An interrupt is

generated when the transfer is complete and the cor-

responding interrupt flag bit (SPI1IF or SPI2IF) is set.

This interrupt can be disabled through an interrupt

enable bit (SPI1IE or SPI2IE).

The receive operation is double-buffered. When a

complete byte is received, it is transferred from

SPIxSR to SPIxBUF.

If the receive buffer is full when new data is being

transferred from SPIxSR to SPIxBUF, the module will

set the SPIROV bit, indicating an overflow condition.

The transfer of the data from SPIxSR to SPIxBUF will

not be completed and the new data will be lost. The

module will not respond to SCL transitions while

SPIROV is ‘1’, effectively disabling the module until

SPIxBUF is read by user software.

Transmit writes are also double-buffered. The user

write s to SPIxBU F. When the mast er or slav e transfe r

is completed, the contents of the shift register

(SPIxSR) is moved to the receive buffer. If any trans-

mit data has been written to the buffer register, the

contents of the transmit buffer are moved to SPIxSR.

The received data is thus placed in SPIxBUF and the

transmit data in SPIxSR is ready for the next transfer.

In Master mode, the clock is generated by prescaling

the system clock. Data is transmitted as soon as a

value is written to SPIxBUF. The interrupt is generated

at the middle of the transfer of the last bit.

In Slave mode, data is transmitted and received as

external clock pulses appear on SCK. Again, the inter-

rupt is generated when the last bit is latched. If SSx

control is enabled, then transmission and reception

are enabled only when SSx = low. The SDOx output

will be disabled in SSx mode with SSx high.

The clock provided to the module is (FOSC/4). This

clock is then prescaled by the primary (PPRE<1:0>)

and the secondary (SPRE<2:0>) prescale factors. The

CKE bit determines whether transmit occurs on transi-

tion from active clock state to Idle clock state, or vice

versa. The CKP bit selects the Idle state (high or low)

for the clock.

15.1.1 WORD AND BYTE

COMMUNICATION

A control bit, MODE16 (SPIxCON<10>), allows the

module to communicate in either 16-bit or 8-bit mode.

16-bit operation is identical to 8-bit operation, except

that the number of bits transmitted is 16 instead of 8.

The user software must disable the module prior to

changing the MODE16 bit. The SPI module is reset

when the MODE16 bit is changed by the user.

A basic dif ference betwee n 8-bit and 16-bit operat ion is

that the data is transmitted out of bit 7 of the SPIxSR for

8-bit operation, and data is transmitted out of bit 15 of

the SPIxSR for 16-bit opera tion. In both mode s, dat a is

shifted into bit 0 of the SPIxSR.

15.1.2 SDOx DISABLE

A control bit , DISSDO, is provided to the SPIxCON reg-

ister to allow the SDOx output to be disabled. This will

allow the SPI module to be connected in an input only

configuration. SDO can also be used for general

purpose I/O.

15.2 Framed SPI Support

The module supports a basic framed SPI protocol in

Master or Sla ve mode. The co ntrol bit FRMEN enables

framed SPI supp ort and c auses the SSx pi n to perform

the frame synchronization pulse (FSYNC) function.

The control bit SPIFSD determines whether the SSx

pin is an input or an output (i.e., whether the module

receives or generates the frame synchronization

pulse). The frame pulse is an active-high pulse for a

single SPI clock cycle. When frame synchronization is

enabled, the data transmission starts only on the

subsequent transmit edge of the SPI clock.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

dsPIC30F2010

FIGURE 15-1: SPI BLOCK DIAGRAM

FIGURE 15-2: SPI MASTER/SLAVE C ONNECTION

Note: x = 1 or 2.

Read Write

Internal

Data Bus

SDIx

SDOx

SSx

SCKx

SPIxSR

SPIxBUF

bit 0

Shift

clock Edge

Select

FCY

Primary

1:1, 1:4,

Enable Master Clock

Prescaler

Secondary

Prescaler

1:1-1:8

SS & FSYNC

Control

Clock

Control

Transmit

SPIxBUF

Receive

1:16, 1:64

Serial Input Buffer

(SPIxBUF)

Shift Register

(SPIxSR)

MSb LSb

SDOx

SDIx

PROCESSOR 1

SCKx

SPI Master

Serial Input Buffer

(SPIyBUF)

Shift Register

(SPIySR)

LSb

MSb

SDIy

SDOy

PROCESSOR 2

SCKy

SPI Slav e

Serial Clock

Note: x = 1 or 2, y = 1 or 2.

dsPIC30F2010

15.3 Slave Select Synchronization

The SSx pin allows a Synchronous Slave mode. The

SPI must be configured in SPI Slave mode, with SSx

pin control enabled (SSEN = 1). When the SSx pin is

low, transmission and reception are enabled, and the

SDOx pin is driven. When SSx pin goes high, the SDOx

pin is no longer driven. Also, the SPI module is re-

synchronized, and all counters/control circuitry are

reset. Therefore, when the SSx pin is asserted low

again, transmission/reception will begin at the MSb,

even if SSx had been de-asserted in the middle of a

transmit/receive.

15.4 SPI Operation During CPU Sleep

Mode

During Sleep mode, the SPI module is shut down. If

the CPU enters Sleep mode while an SPI transaction

is in progress, then the transmission and reception is

aborted.

The transmitter and receiver will stop in Sleep mode.

However, register contents are not affected by

entering or exiting Sleep mode.

15.5 SPI Operation During CPU Idle

Mode

When the device enters Idle mode, all clock sources

remain functional. The SPISIDL bit (SPIxSTAT<13>)

selects if the SPI module will stop or continue on Idle.

If SPISIDL = 0, the module will continue to operate

when the CPU enters Idle mode. If SPISIDL = 1, the

module will stop when the CPU enters Idle mode.

dsPIC30F2010

TABLE 15-1: SPI1 REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000

SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000

SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

16.0 I2C MODULE

The Inter-Integrated Circuit (I2C) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard, with a 16-bit interface.

This module offers the following key features:

•I

2C interface supporting both Master and Slave

operation.

•I

2C Slave mode supports 7 and 10-bit address.

•I

2C Master mode supports 7 and 10-bit address.

•I

2C port allows bidirectional transfers between

master and slav es.

• Serial clock synchronization for I2C port can be

used as a ha ndshake mechanis m to suspen d and

resume serial transfer (SCLREL control).

•I

2C supports Multi-Master operation; detects bus

collision and will arbitrate accordingly.

16.1 Operating Function Description

The hardw are fully im plements all the maste r and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

Thus, the I2C module can operate either as a slave or

a master on an I2C bus.

16.1.1 VARIOUS I2C MODES

The following types of I2C operation are supported:

•I

2C Slave operation with 7-bit address

•I

2C Slave operation with 10-bit address

•I

2C Master operation with 7 or 10-bit address

See the I2C programmer’s model in Figure 16-1.

16.1.2 PIN CONFIGURATION IN I2C MODE

I2C has a 2- pin i nterfac e: pin SCL is clock and pin SD A

is data.

FIGURE 16 - 1: PROGRAMMER’ S MOD EL

16.1.3 I2C REGISTERS

I2CCON and I2 CSTAT are con trol a nd st at us regis ters,

respect ively . The I2CCO N register is readable an d writ-

able. The lower 6 bits of I2CSTAT are read-only. The

remaining bits of the I2CSTAT are read/write.

I2CRSR is the shift register used for shifting data,

whereas I2CRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CRCV is the receive buffer, as shown in Figure 16-1.

I2CTRN is the transmit register to which bytes are writ-

ten during a transmit operation, as s hown in Figure 16-2.

The I2CADD regis ter hol ds the s lave a ddress. A status

bit, ADD10, indicates 10-bit Address mode. The

I2CBRG acts as the Baud Rate Generator (BRG)

reload value.

In receive operations, I2CRSR and I2CRCV together

form a double-buffered receiver. When I2CRSR

receives a complete byte, it is transferred to I2CRCV

and an interrupt pulse is generated. During

transmission, the I2CTRN is not double-buffered.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

bit 7 bit 0 I2CRCV (8 bits)

bit 7 bit 0 I2CTRN (8 bits)

bit 8 bit 0 I2CBRG (9 bits)

bit 15 bit 0 I2CCON (16 bits)

bit 15 bit 0 I2CSTAT (16 bits)

bit 9 bit 0 I2CADD (10 bits)

Note: Following a Restart condition in 10-bit

mode, the user only needs to match the

first 7-bit addre ss.

dsPIC30F2010

FIGURE 16-2: I2C B LO C K DI AGR AM

I2CRSR

I2CRCV

Internal

Data Bus

SCL

SDA

Shift

Mat ch Detect

I2CADD

Start and

Stop bit Detect

Clock

Addr_Match

Clock

Stretching

I2CTRN LSB

Shift

Clock

Write

Read

BRG Down I2CBRG

Reload

Control

FCY

Start, Restart,

Stop bit Generate

Write

Read

Acknowledge

Generation

Collision

Detect

Write

Read

Write

Read

I2CCON

Write

Read

I2CSTAT

Control Logic

Read

LSB

Counter

dsPIC30F2010

16.2 I2C Module Addresses

The I2CADD register contains the Slave mode

addresses. The register is a 10-bit register.

If the A10M bit (I2CCON<10>) is ‘0’, the address is

inter prete d by the mo dul e as a 7 - bit add ress . When an

address is re ceived, i t is c ompa red to the 7 LSbs of the

I2CADD register.

If the A10M bit is ‘1’, the address is assumed to be a

10-bit address. When an address is received, it will be

compared with the binary value ‘1 1 1 1 0 A9 A8’

(where A9, A8 are two Most Significant bits of

I2CADD). If that value matches, the next address will

be compared with the Least Significant 8 bits of

I2CAD D, as speci fied in the 1 0-bit addres sing proto col.

TABLE 16-1: 7-BIT I2C™ SLAVE

ADDRESSES SUPPORTED BY

dsPIC30F

16.3 I2C 7-bit Slave Mode Operation

Once enabled (I2CEN = 1), the slave module will wait

for a S t art bit to occur (i.e., the I2C module is ‘I dle’). Fol-

lowin g t he det ection of a St art bit , 8 bi ts are s hif ted into

I2CRSR and the address is compared against

I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>

are compared against I2CRSR<7:1> and I2CRSR<0>

is the R_W bit. All incoming bits are sampled on the

rising edge of SCL.

If an address match occurs, an acknowledgement will

be sent, and the slave event interrupt flag (SI2CIF) is

set on the falling edge of the ninth (ACK) bit. The

address match does not affect the contents of the

I2CRCV buffer or the RBF bit.

16.3.1 SLAVE TRANSMISSION

If the R_W bit received is a ‘

’, then the serial port will

go into Transmit mode. It wil l send ACK on the nin th bit

and then hold SCL to ‘

’ until the CPU responds by writ-

ing to I2C TRN. SCL is rele ased by settin g the SCLREL

bit, and 8 bits of data are shifted out. Data bits are

shifted out on the fa lling edge of SCL, s uch that SDA i s

valid during SCL high (see timing diagram). The inter-

rupt pulse is sent on the falling edge of the ninth clock

pulse, regardless of the status of the ACK received

from the master.

16.3.2 SLAV E RECE PTI ON

If the R_W bit received is a ‘0’ during an address

match, then Receive mode is initiated. Incoming bits

are sa mpl ed on the risi ng ed ge of SCL . After 8 bi t s are

received, if I2CRCV is not full or I2COV is not set,

I2CRSR is transferred to I2CRCV. ACK is sent on the

ninth clock.

If the RBF flag is set, indicating that I2CRCV is still

holding data from a pre vious operati on (RBF = 1), the n

ACK is not sent; however, the interrupt pulse is gener-

ated. In the case of an overflow, the contents of the

I2CRSR are not loaded into the I2CRCV.

16.4 I2C 10-bit Slave Mode Operation

In 10-bit mode, the basic receive and transmit opera-

tions are the same as in the 7-bit mode. However, the

criteria for address match is more complex.

The I2C specification dictates that a slave must be

address ed for a write ope ration, with tw o address byte s

following a Start bit.

The A10M bit is a control bit that signifies that the

address in I2CADD is a 10-bit address rather than a

7-bit address. The address detection protocol for the

first byte of a message address is identical for 7-bit

and 10-bit messages, but the bits being compared are

different.

I2CADD holds the entire 10-bit address. Upon receiv-

ing an address following a Start bit, I2CRSR <7:3> is

compared against a literal ‘11110’ (the default 10-bit

address) and I2CRSR<2:1> are compared against

I2CADD<9:8>. If a match occurs and if R_W = 0, the

interrupt pu lse is sent. Th e ADD10 bit will be cleare d to

indicate a partial address match. If a match fails or

R_W = 1, the ADD10 bit is cleared and the module

returns to the Idle state.

The low byte of the address is then received and com-

pared with I2CADD<7:0>. If an address match occurs,

the interrupt pulse is generated and the ADD10 bit is

set, indicating a complete 10-bit address match. If an

address match did not occur, the ADD10 bit is cleared

and the module returns to the Idle state.

0x0 0 General call ad dress or Start byte

0x01-0x03 Reserved

0x04-0x07 Hs mode Maste r code s

0x08-0x77 Valid 7-bit addresses

0x78-0x7B Valid 10-bit addresses

(lower 7 bits)

0x7C-0x7F Reserved

Note: The I2CRCV will be loaded if the I2COV

bit = 1 and the RBF flag = 0. In this case,

a read of the I2CRCV was performed, but

the user did not clear the state of the

I2COV bit before the next receive

occurred. The acknowledgement is not

sent (ACK = 1) and the I2CRCV is

updated.

dsPIC30F2010

16.4.1 10-BIT MODE SLAVE

TRANSMISSION

Once a slave is addressed in this fashion, with the full

10-bit address (we will refer to this state as

"PRIOR_ADDR_MATCH"), the master can begin

sending data bytes for a slave reception operation.

16.4.2 10-BIT MODE SLAVE RECEPTION

Once ad dress ed, the ma ster ca n genera te a Rep eated

Start, reset the high byte of the address and set the

R_W bit without generating a Stop bit, thus initiating a

slave tran sm it ope ratio n.

16.5 Automatic Clock Stretch

In the Slave mo des, the module ca n synchroniz e buf fer

reads and write to the master device by clock

stretching.

16.5.1 TRANSMI T CLOCK STRETCHING

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of th e ninth c lock if th e TBF bit i s clea red, ind icat-

ing the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed, irrespective of the STREN bit.

Clock synchronization takes place following the ninth

clock of the transmit sequence. If the device samples

an ACK on the fa lling edge o f the ni nth cl ock, a nd if th e

TBF bit is still clear, then the SCLREL bit is automati-

cally cleared. The SCLREL being cleared to ‘0’ will

assert the SCL line low. The user ’s ISR must set the

SCLREL bit before transmission is allowed to con-

tinue. By ho ldi ng the SC L l ine lo w, the user has tim e to

service the ISR and load the contents of the I2CTRN

before the master device can initiate another transmit

sequence.

16.5.2 RECEIVE CLOCK STRETCHING

The STREN bit in the I2CCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCL pin will be held low at

the end of each data receive sequence.

16.5.3 CLOCK STRETCHING DURING

7-BIT ADDRESSING (STREN = 1)

When the STREN bit is set in Slave Receive mode,

the SCL line is held low when the buffer register is full.

The method for stretching the SCL output is the same

for both 7 and 10-bit Addressing modes.

Clock stretching takes place following the ninth clock of

the receive sequence. On the falling edge of the ninth

clock at the end of the ACK sequence, if the RBF bit is

set, the SCLREL bit is automatically cleared, forcing the

SCL output to be held low. The user ’s ISR must set the

SCLREL bit before reception is allowed to continue. By

holding the SCL line low, the user has time to service

the ISR and read the contents of the I2CRCV before the

master device can initiate another receive sequence.

This will prevent buffer ov erruns from occ urring.

16.5.4 CLOCK STRETCHING DURING

10-BIT ADDRESSING (STREN = 1)

Clock stretching takes place automatically during the

addressing sequence. Because this module has a

the protocol to wait for the address to be updated.

After the address phase is complete, clock stretching

will occur on each data receive or transmit sequence

as was described earlier.

Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the fallin g edge

of the n int h c lo ck , th e SC LREL bit w il l n ot

be cleared and clock stretching will not

occur.

2: The SCLREL bit can be set in software,

regardless of the state of the TBF bit.

Note 1: If the user reads the contents of the

I2CRCV, clearing the RBF bit before the

falling edge of the ninth clock, the

SCLREL bit will not be cleared and clock

stretching will not occur.

2: The SCLREL bit can be set in software,

regardles s of the state of the RBF bit. The

user should be careful to clear the RBF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

dsPIC30F2010

16.6 Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching. The logic will synchronize writes to

the SCLREL bit with the SCL clock. Clearing the

SCLREL bit will not assert the SCL output until the

module detects a falling edge on the SCL output and

SCL is sampled low. If the SCLREL bit is cleared by

the user while the SCL line has been sampled low, the

SCL output will be asserted (held low). The SCL out-

put will remain low until the SCLREL bit is set, and all

other devices on the I2C bus have de-asserted SCL.

This ensures that a write to the SCLREL bit will not

violate the mi nimum high time requirement for SCL.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

16.7 Interrupts

The I2C module generates two interrupt flags, MI2CIF

(I2C Master I nterrupt Flag) an d SI2CIF (I2C Slav e Inter-

rupt Flag). The MI2CIF interrupt flag is activated on

completion of a master message event. The SI2CIF

interrupt flag is activated on detection of a message

directed to the slave.

16.8 Slope Control

The I2C standard requires slope control on the SDA

and SCL signals for Fast Mode (400 kHz). The control

bit, DISSLW , enables the us er to disable slew rate con-

trol, if desired. It is necessary to disable the slew rate

control for 1 MHz mode.

16.9 IPMI Support

The control bit IPMIEN enables the module to support

Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module ac ce pts and ac t s upo n

all addres ses .

16.10 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in

theor y, respond with an ackno w led gem en t.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all 0s with R_W = 0.

The general call address is recognized when the Gen-

eral Call Enable (GCEN) bit is set (I2 CCON<15> = 1).

Following a Start bit detection, 8 bits are shifted into

I2CRSR and the address is compared with I2CADD,

and is also compared with the general call address

which is fixed in hardware.

If a gen eral cal l ad dres s mat ch occu rs, t he I2CRS R is

transferred to the I2CRCV after the eighth clock, the

RBF flag is set, and on the falling edge of the ninth bit

(ACK bit), the master event interrupt flag (MI2CIF) is

set.

When the i nterrupt is serv iced, the source f or the inter-

rupt can be checked by reading the contents of the

I2CRCV to determine if the address was device

specific, or a general call address.

16.11 I2C Master Support

As a Master device, six operations are supported.

• Assert a Start condition on SDA and SCL.

• Assert a Restart condition on SDA and SCL.

• Write to the I2CTRN register initiating

transmission of data/address.

• Generate a Stop condition on SDA and SCL.

• Config ure the I2C port to receive data.

• Generate an ACK condition at the end of a

received byte of data.

16.12 I2C Master Operation

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the begi nning of the next seria l transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the data direction bit. In

this ca se, the da ta direc tion bit (R_ W) is logi c ‘0’. Serial

data is transmitted 8 bits at a time. After each byte is

transmitted , an ACK bit i s received . S t art and Stop con-

ditions are output to indicat e the beginn ing and the en d

of a serial transfer.

In Master Rec eive mode, the firs t byte transmitte d con-

tains the slave address of the transmitting device (7

bits) and the data direction bit. In this case, the data

directio n bit (R_W) is lo gic ‘1’. Thus, the first byte trans -

mitted is a 7-b it slave a ddre ss , followed b y a ‘ 1’ to ind i-

cate receive bit. Serial data is received via SDA, while

SCL outputs the serial clock. Serial data is received 8

bits at a tim e. After e ach by te is rece ived, a n ACK bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

dsPIC30F2010

16.12.1 I2C MASTER TRANSMISSION

T rans mission of a data by te, a 7-bit ad dress or the sec-

ond half of a 10-bit address is accomplished by simply

writing a value to I2CTRN register. The user should

only write to I2CTRN when the module is in a Wait

state. This action will set the buffer full flag (TBF) and

allow the Baud Rate Generator to begin counting and

start the next transmission. Each bit of address/data

will be shifted out onto the SDA pin after the falling

edge of SCL is asserted. The Transmit Status Flag,

TRSTAT (I2CSTAT<14>), indicates that a master

transmit is in progress.

16.12.2 I2C MASTER RECEPTION

Master mode recepti on is enab led by progra mmin g the

receive enable (RCEN) bit (I2CCON<11>). The I2C

module must be Idle before the RCEN bit is set, other-

wise the RCEN bit will be disregarded. The Baud Rate

Generator begins counting, and on each rollover, the

stat e of the SCL pin toggles, and data is shifted in to the

I2CRSR on the rising edge of each clock.

16.12.3 BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the I2CBRG register. When the BRG is

loaded w ith th is v alu e, the BRG c ou nt s d own to ‘0’ and

stops until another reload has taken place. If clock

arbitration is taking place, for instance, the BRG is

reloaded when the SCL pin is sampled high.

As per the I2C standard, FSCK may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.

EQUATION 16-1: I2CBRG VALUE

16.12.4 CLOCK ARBITRATION

Clock arbitration occurs when the master de-asserts

the SCL pin (SCL allowed to float high) during any

receive, transmit or Restart/Stop condition. When the

SCL pin is allowed to float high, the Baud Rate

Generator is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is

sampled high, the Baud Rate Generator is reloaded

with the co ntent s o f I2C BRG an d begi ns c ountin g. Thi s

ensures that the SCL high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device.

16.12.5 MULTI-MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master operation support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA, by letting SDA float high

whil e another mas ter asse rts a ‘0’. Wh en the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA

pin = 0, then a bus collision has taken place. The

master will set the MI2CIF pulse and reset the master

portion of the I2C port to its Idle state.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is

cleared , the SDA and SCL line s are de-a sserted, and a

value can now be written to I2CTRN. When the user

services the I2C master event Interrupt Service

Routine, if the I2C bus is free (i.e., the P bit is set) the

user can resume communication by asserting a Start

condition.

If a Start, Restart, Stop or Acknowledge condition was

in progres s when the bus co lli si on o cc urre d, th e c ond i-

tion is aborted, the SDA and SCL lines are de-asserted,

and the respective control bits in the I2CCON register

are cleared to ‘0’. When t h e u s er se r vi c es the bu s c ol -

lision Interrupt Service Routine, and if the I2C bus is

free, the user can resume co mm uni ca tio n by as se rting

a St art conditi on .

The Master will continue to monitor the SDA and SCL

pins, and if a Stop condition occurs, the MI2CIF bit will

be set.

A write to the I2CTR N will start the trans mission of dat a

at the first data bit, regardless of where the transmitter

left off when bus collision occurred.

In a Multi-Maste r en vi ronm en t, th e i nte rrup t ge nera tio n

on the d etecti on of St art a nd Stop conditio ns al lows the

determination of when the bus is free. Control of t he I2C

bus can be taken when the P bit is set in the I2CSTAT

cleared.

I2CBRG Fcy

Fscl

-----------Fcy

1 111 111,,

---------------------------

–

⎝⎠

⎛⎞

1–=

dsPIC30F2010

16.13 I2C Module Operat ion During CPU

Sleep and Idle Modes

16.13.1 I2C OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’. If

Sleep occurs in the middle of a transmission, and the

state machine is partially into a transmission as the

clock s stop, the n th e trans miss ion is ab orte d. Simi larly,

if Sleep occurs in the middle of a reception, then the

reception is aborted.

16.13.2 I2C OPERATION DURING CPU IDLE

MODE

For the I2C, the I2CSIDL bit selects if the module will

stop on Idle or continue on Idle. If I2CSIDL = 0, the

module will continue operation on assertion of the Idle

mode. If I2CSIDL = 1, the module will stop on Idle.

dsPIC30F2010

TABLE 16-2: I2C™ REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000

I2CTRN 0202 — — — — — — — — Tra nsmit Register 0000 0000 1111 1111

I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000

I2CCON 0206 I2CEN —I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000

I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000

I2CADD 020A — — — — — — Address Regist er 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

17.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART) MODULE

This section describes the Universal Asynchronous

Receiver/Transmitter Communications module.

17.1 UART Module Overview

The key features of the UART module are:

• Full-duplex, 8 or 9-bit data communication

• Even, Od d or No Parity options ( for 8 -bit data)

• One or two Stop bits

• Fully integ rate d Baud R ate Ge nera tor with 16-b it

prescaler

• Baud rates range from 38 bps to 1.875 Mbps at a

30 MHz instruction rate

• 4-word deep transmit data buffer

• 4-word deep receive data buffer

• Parity, Framin g and B uff er Overrun error detec tion

• Support for Interrupt only on Address Detect

(9th bit = 1)

• Separate Transmit and Receive Interrupts

• Loopback mode for diagnostic support

FIGU RE 17- 1: UART TRANS MI T TE R BL OCK D I A GRA M

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: Since dsPIC30F2010 devices have only

one UART, all references to Ux... imply

that x = 1 only.

Write Write

UTX8 UxTXREG Low Byte

Load TSR

Transmit Control

– Control TSR

– Control Buffer

– Generate Flags

– Generate Interrupt

Control and Status bi ts

UxTXIF

Data

‘0’ (Start)

‘1’ (Stop)

Parity Parity

Generator

Transmit Shift Register (UxTSR)

16 Divider

Control

Signals

16X Baud Cl o ck

from Baud Rate

Generator

Internal Data Bus

UTXBRK

Note: x = 1 only.

UxTX

dsPIC30F2010

FIGU RE 17-2 : UART R ECEIVER B LO C K DI AGR AM

Read

URX8 UxRXREG Low Byte

Load RSR

UxMODE

Receive Buffer Control

– Generate Fl ag s

– Generate Inte rr upt

UxRXIF

UxRX

· S

tart

bit Detect

Receive Shift Register

16 Divider

Control

Signals

UxSTA

– Shift Data Characters

Read Read

Write Write

to Buffer

8-9

(UxRSR)

PERR

FERR

· Parity Check

· Stop bit Detect

· Shift Clock Generation

· Wake Logic

Internal Data Bus

LPBACK

From Ux TX

16X Baud Clock from

Baud Rate Generator

Note: x = 1 only.

dsPIC30F2010

17.2 Enabling and Setting Up UART

17.2.1 ENABLING THE UART

The UART module is enabled by setting the UARTEN

bit in the UxMODE register (where x = 1 only). Once

enabled , the UxTX and UxRX pins are configured as an

output and an input respectively, overriding the TRIS

and LATCH register bit settings for the corresponding

I/O port pins. The UxTX pin is at logic ‘1’ when no

transmission is taking place.

17.2.2 DISABLING THE UART

The UART module is disabled by clearing the

UARTEN bit in the UxMODE register. This is the

default state after any Reset. If the UART is disabled,

all I/O pins operate as port pins under the control of

the latch and TRIS bits of the corresponding port pins.

Disabling the UART module resets the buffers to

empty states. Any data characters in the buffers are

lost, and the baud rate counter is reset.

All error and status flags associated with the UART

module are reset when the module is disabled. The

URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and

UTXBF bits are cleared, whereas RIDLE and TRMT

are set. Other control bits, including ADDEN,

URXISEL<1:0>, UTXISEL, as well as the UxMODE

and UxBRG registers, are not affected.

Clearing the UARTEN bit while the UART is active will

abort all pending transmissions and receptions and

reset the module as defined above. Re-enabling the

UART will restart the UART in the same configuration.

17.2.3 ALT ERNA TE I/O

The alternate I/O function is enabled by setting the

ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX

and UxARX pins (alternate transmit and alternate

receive pins, respectively) are used by the UART mod-

ule instead of the UxTX and UxRX pins. If ALTIO = 0,

the UxTX and UxRX pins are used by the UART

module.

17.2.4 SETTING UP DATA, PARITY AND

STOP BIT SELECTIONS

Control bits PDSEL<1:0> in the UxMODE register are

used to select the data length and parity used in the

transmission. The data length may either be 8 bits with

even, odd or no parity, or 9 bits with no parity.

The STSEL bit determines whether one or two S top bit s

will be used during data transmissi on.

The defau lt (Power-on) se tting of the UAR T is 8 bit s, no

parity, 1 Stop bit (typically represented as 8, N, 1).

17.3 Transmitting Data

17.3.1 TRANSMITTING IN 8-BIT DATA

MODE

The following steps must be performed in order to

transmit 8-bit data:

1. Set up the UART:

First, the data length, parity and number of Stop

bits must be selected. Then, the Transmit and

Receive Interrupt enable and priority bits are

setup in the UxMODE and UxSTA registers.

Also, the appropriate baud rate value must be

written to the UxBRG register.

2. Enable the UART by setting the UARTEN bit

(UxMODE<15>).

3. Set the UTXEN bit (UxSTA<10>), thereby

enabling a transmission.

4. Write the byte to be t ransmitted to the lower byte

of UxTXREG. The value will be transferred to the

Transmit Shift register (UxTSR) immediately

and the serial bit stream will start shifting out

during the next rising edge of the baud clock.

Alternatively, the data byte may be written while

UTXEN = 0, following which the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

5. A Transmit interrupt will be generated depend-

ing on the value of the interrupt control bit

UTXISEL (UxSTA<15>).

17.3.2 TRANSMITTING IN 9-BIT DATA

MODE

The sequence of steps involved in the transmission of

9-bit data is similar to 8-bit transmission, except that a

16-bit data word (of which the upper 7 bits are always

clear) must be written to the UxTXREG register.

17.3.3 TRANSMIT BUFFER (UXTXB)

The transmit buffer is 9 bits wide and 4 characters

deep. Including the Transmit Shift Register (UxTSR),

the user effectively has a 5-deep FIFO (First In First

Out) buffer. The UTXBF status bit (UxSTA<9>)

indicates whether the transmit buffer is full.

If a user attempts to write to a full buffer, the new data

will not be accepted into the FIFO, and no data shift

will occur within the buffer. This enables recovery from

a buffer overrun condition.

The FIFO is reset during any device Reset, but is not

affected when the device enters or wakes up from a

Power-Saving mode.

Note: The UTXEN bit must be set after the

UARTEN bit is set to enable UART

transmissions.

dsPIC30F2010

17.3.4 TRANSMIT INTERRUPT

The transmit interrupt flag (U1TXIF or U2TXIF) is

located in the corresponding interrupt flag register.

The transmitter generates an edge to set the UxTXIF

bit. The cond itio n for gene ratin g the in terru pt depe nds

on UTXISEL control bit:

a) If UTXISEL = 0, an interrupt is generated when

a word is tra ns ferre d fro m the Transmit buf fe r to

the T ransmit Shi ft registe r (UxTSR). This means

that the transmit buffer has at least one empty

word.

b) If UTXISEL = 1, an interrupt is generated when

a word is tra ns ferre d fro m the Transmit buf fe r to

the Transmit Shift register (UxTSR) and the

Transmit buffer is empty.

Switching between the two interrupt modes during

operation is possible and sometimes offers more

flexibility.

17.3.5 TRANSMIT BREAK

Setting the UTXBRK bit (UxSTA<11>) will cause the

UxTX line to be driven to logic ‘0’. The UTXBRK bit

overrides all transmission activity. Therefore, the user

should generally wait for the transmitter to be Idle

before setting UTXBRK.

To send a break character, the UTXBRK bit must be

set by software and must remain set for a minimum of

13 baud cl oc k cy cl es . The UTX BR K b it is then cle a red

by software to generate Stop bits. The user must wait

for a duration of at least one or two baud clock cycles

in order to ensure a valid Stop bit(s) before reloading

the UxTXB or starting other transmitter activity. Trans-

mission of a break character does not generate a

transmit interrupt.

17.4 Receiving Data

17.4.1 RECEIVING IN 8-BIT OR 9-BIT DATA

MODE

The following steps must be performed while receiving

8-bit or 9-bit data:

1. Set up the UART (see Section 17.3.1 “Trans-

mitting in 8-bit data mode”).

2. Enable the UART (see Section 17.3.1 “Trans-

mitting in 8-bit data mode”).

3. A receive interrupt will be generated when one

or more data words have been received,

depending on the receive interrupt settings

specified by the URXISEL bits (UxSTA<7:6>).

4. Read the OERR bit to determine if an overrun

error has occ urred. The OERR bit must be reset

in software.

5. Read the received data from UxRXREG. The act

of reading UxRXREG will move the next word to

the top of the receive FIFO, and the PERR and

FER R values will be update d.

17.4.2 RECEIVE BUFFER (UXRXB)

The receive buffer is 4 words deep. Including the

Receive Shift register (UxRSR), the user effectively

has a 5-word deep FIFO buffer.

URXDA (UxSTA<0>) = 1 indicates that the receive

buffer has data available. URXDA = 0 implies that the

buffer is empty. If a user attempts to read an empty

buffer, the old values in the buffer will be read and no

data shift will occur within the FIFO.

The FIFO is reset during any device Reset. It is not

affected when the device enters or wakes up from a

Power-Saving mode.

17.4.3 RECEIVE INTERRUPT

The receive interrupt flag (U1RXIF) can be read from

the corresponding interrupt flag register. The interrupt

flag is set by an edge generated by the receiver. The

condition for setting the receive interrupt flag depends

on the settings specified by the URXISEL<1:0>

(UxSTA<7:6>) control bits.

a) If URXISEL<1:0> = 00 or 01, an interrupt is

generated every time a data word is transferred

from the Receive Shift Register (UxRSR) to the

Receive Buffer. There may be one or more

charact ers in the receive buffer.

b) If URXISEL<1:0> = 10, an interrupt is gene rated

when a word is transferred from the Receive

Shift Register (UxRSR) to the Receive Buffer,

which, as a result of the transfer, contains 3

characters.

c) If URXISEL<1:0> = 11, an interrupt is set when

a word is transferred from the Receive Shift

Regist er (U xRSR) to t he Re ce iv e Bu ffer, which,

as a result of the transfer, contains 4 characters

(i.e., becom es full).

Switching between the Interrupt modes during opera-

tion is possible, though generally not advisable during

normal operation.

17.5 Reception Error Handling

17.5.1 RECEIVE BUFFER OVERRUN

ERROR (OERR BIT)

The OERR bit (UxSTA<1>) is set if all of the following

conditions occur:

a) The receive buffer is full.

b) The receive shift register is full, but unable to

transfer the character to the receive buffer.

c) The Stop bit of the character in the UxRSR is

detected, indicating that the UxRSR needs to

transfer the character to the buffer.

Once OERR is se t, no furthe r dat a is s hif ted in UxRSR

(until the OERR bit is cleared in software or a Reset

occurs). The data held in UxRSR and UxRXREG

remains val id.

dsPIC30F2010

17.5.2 FRAMING ERROR (FERR)

The FERR bit (UxSTA<2>) is set if a ‘0’ is detected

instead of a Stop bit. If two Stop bits are selected, both

Stop bits must be ‘1’, otherwise FERR will be set. The

read-only FERR bit is buffered along with the received

data. It is cleared on any Reset.

17.5.3 PARITY ERROR (PERR)

The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable

only if a Parity mode (odd or even) is selected. The

read-only PERR bit is buffered along with the received

data bytes. It is cleared on any Reset.

17.5.4 IDLE STATUS

When the receiver is active (i.e., between the initial

detecti on of the Start bit and the comp letion of the Sto p

bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the

completion of the Stop bit and detection of the next

Start bit, the RIDLE bit is ‘1’, indicating that the UART

is Idle.

17.5.5 RECEIVE BRE AK

The receiver will count and expect a certain number of

bit times based on the values programmed in the

PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)

bits.

If the break is longer than 13 bit times, the reception is

considered complete after the number of bit times

specified by PDSEL and STSEL. The URXDA bit is

set, FERR is set, zeros are loaded into the receive

FIFO, interrupts are generated, if appropriate, and the

RIDLE bit is set.

When the module receiv es a lo ng b r ea k s ign al a nd th e

receiver has detected the Start bit, the data bits and

the inv ali d Stop bit (wh ic h sets the FER R), the receiv er

must wai t for a val id Sto p bit before looki ng for the next

Start bit . It cannot assu me that the br eak conditi on on

the line is the next Start bit.

Break is regarded as a character containing all ‘0’s,

with the FERR bit set. The break character is loaded

into the buffer. No further reception can occur until a

Stop bit is received. Note that RIDLE goes high when

the Stop bit has not been received yet.

17.6 Address Detect Mode

Setting the ADDEN bit (UxSTA<5>) enables this spe-

cial mode, in which a 9th bit (URX8) value of ‘1’ identi-

fies the received word as an address rather than data.

This m ode i s o nl y a pp lic ab le for 9-bit dat a commun ic a-

tion. The URXISEL control bit does not have any

impact on interrupt generation in this mode, since an

interrupt (if enabled) will be generated every time the

received word has the 9th bit set.

17.7 Loopback Mode

Setting the LPBACK bit enables this special mode in

which the UxTX pin is int ernally conne cted to the UxRX

pin. When configured for the Loopback mode, the

UxRX pin is disconnected from the internal UART

receive logic. However, the UxTX pin still functions as

in a normal operation.

To select this mode:

a) Configure UART for desired mode of operation.

b) Set LPBACK = 1 to enable Loopback mode.

c) Enable tran sm is si on as def ine d in Section 17.3

“Transmitting Data”.

17.8 Baud Rate Generator

The UART has a 16-bit Baud Rate Generator to allow

maximu m fl exib ilit y in b aud r ate ge nera tio n. Th e Baud

Rate Generator register (UxBRG) is readable and

writable. The baud rate is computed as follows:

BRG = 16-bit value held in UxBRG register

(0 through 65535)

FCY = Instruction Clock Rate (1/TCY)

The Baud Rate is given by Equati on 17-1.

EQUATION 17-1: BAUD RATE

Therefore, maxi mum baud rate possible is

FCY /16 (if BRG = 0),

and the minimum baud rate possible is

FCY / (16 * 65536).

With a full 16-bit Baud Rate Generator, at 30 MIPs

operation, the minimum baud rate achievable is

28.5 bps.

17.9 Auto Baud Support

To allow the system to determine baud rates of

received characters, the input can be optionally linked

to a selected capture input. To enable this mode, the

user must program the input capture module to detect

the falling and rising edges of the Start bit.

Baud Rate = FCY / (16 * ( BRG + 1))

dsPIC30F2010

17.10 UART Operation During CPU

Sleep and Idle Modes

17.10.1 UART OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’. If

entry into Sleep mode occurs while a transmission is

in progress, then the transmission is aborted. The

UxTX pin is driven to logic ‘1’. Similarly, if entry into

Sleep mode occurs while a reception is in progress,

then the reception is aborted. The UxSTA, UxMODE,

transmit and receive registers and buffers, and the

UxBRG register are not affected by Sleep mode.

If the W AKE bit (UxMODE<7>) is set be fore the devic e

enters Sleep mode, then a falling edge on the UxRX

pin will generate a receive interrupt. The Receive

Interrupt Select mode bit (URXISEL) has no effect for

this function. If the receive interrupt is enabled, then

this will wake-up the device from Sleep. The UARTEN

bit must be set in order to generate a wake-up

interrupt.

17.10.2 UART OPERATION DURING CPU

IDLE MODE

For the UART, the USIDL bit selects if the module will

stop operation when the device enters Idle mode, or

whethe r the m odu le wi ll co nti nue on Idl e. If U SID L = 0,

the module will continue operation during Idle mode. If

USIDL = 1, the module will stop on Idle.

dsPIC30F2010

TABLE 17-1: UART1 REGISTER MAP

SFR Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

U1MODE 020C UARTEN —USIDL——ALTIO—— WAKE LPBACK ABAUD —— PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000

U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000

U1TXREG 0210 — — — — — — — UTX8 T ransmit Register 0000 000u uuuu uuuu

U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000

U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

NOTES:

dsPIC30F2010

18.0 10-BIT HIGH-SPEED ANALOG-

TO-DIGITAL CONVERTER

(ADC) MODULE

The10-bit high-speed Analog-to-Digital Converter

(ADC) allows conversion of an analog input signal to a

10-bit digital number. This module is based on a Suc-

cessive Approximation Register (SAR) architecture,

and provides a maximum sampling rate of 500 ksps.

The ADC module has up to 16 analog inputs which are

multiplexed into four sample and hold amplifiers. The

output of the sa mp le and hold is the input in to the con-

verter, which generates the result. The analog refer-

ence voltages are software selectable to either the

devi ce sup ply vol tag e (AVDD/AVSS) or the voltage level

on the (VREF+/VREF-) pin. The ADC has a unique fea-

ture of b eing able to operate whil e the device is in Sleep

mode.

The ADC module has six 16-bit registers:

• A/D Control Register1 (ADCON1)

• A/D Control Register2 (ADCON2)

• A/D Control Register3 (ADCON3)

• A/D Input Select Register (ADCHS)

• A/D Port Configuration Register (ADPCFG)

• A/D Input Scan Selection Register (ADCSSL)

The ADCON1, ADCON2 and ADCON3 registers con-

trol the ope ration of the ADC module. Th e ADCHS reg-

ister selects the input channels to be converted. The

ADPCFG register configures the port pins as analog

inputs or as digital I/O. The ADCSSL register selects

input s for sca nni ng .

The block diagram of the ADC module is shown in

Figure 18-1.

FIGURE 18-1: 10-BIT HIGH-SPEED ADC FUNCTIONAL B LOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: The SSRC<2:0>, ASAM, SIMSAM,

SMPI<3:0>, BUFM and ALTS bits, as well

as the ADCON3 and ADCSSL registers,

must not be written to while ADON = 1.

This would lead to indeterminate results.

S/H

10-bit Result Conversion Logic

VREF+

AVSS

AVDD

ADC

Data

16-word, 10-bit

Dual Port

Buffer

Bus Interface

AN0

AN5

AN1

AN2

AN3

AN4

AN5

AN0

AN1

AN2

AN3

CH1

CH2

CH3

CH0

AN5

AN2

AN4

AN1

AN3

AN0

AN1

VREF-

Sample/Sequence

Control

Sample

CH1,CH2,

CH3,CH0

Input MUX

Control

Input

Switches

S/H

Format

dsPIC30F2010

18.1 A/D Result Buffer

The module contains a 16-word dual port read-only

buffe r, called A DCBUF0 ...ADC BUFF, to bu ffer the ADC

result s. The RAM i s 10 bits wi de, but is read into differe nt

format 16-bit words. The contents of the sixteen ADC

conversion result buffer registers, ADCBUF0 through

ADCBUFF, cannot be written by user software.

18.2 Conversion Operation

After th e ADC module has been configu red, the samp le

acquisition is started by setting the SAMP bit. Various

sources, such as a programmable bit, timer time-outs and

external events, will terminate acquisition and start a con-

version. When the A/D conversion is complete, the result

is loaded into ADCBUF0...ADCBUFF, and the A/D

interrupt flag ADIF and the DONE bit are set after the

number of samples specified by the SMPI bit.

The following steps should be followed for doing an

A/D conversion:

1. Configure the ADC module:

- Configure an alog pins, voltage re ferenc e and

digital I/O

- Select A/D input ch annels

- Select A/D conve rsi on cl ock

- Select A/D conver si on trig ger

- Turn on A/D module

2. Configure A/D interrupt (if required):

- Clear ADIF bit

- Select A/D interrupt priority

3. Start sampling.

4. Wait the required acquisition time.

5. Trigger acquisition end, start conversion

6. Wait for A/D conversion to complete, by either:

- Waiting for the A/D interrupt

- Waiting for the DONE bit to get set

7. Read A/D result buffer, clear ADIF if required.

18.3 Selecting the Conver sion

Sequence

Several groups of control bits select the sequence in

which the A/D connects inputs to the sample/hold

channe ls, convert s chann els, writes the buffe r memory,

and generates interrupts. The sequence is controlled

by the sampling clocks.

The SIMSAM bit controls the acquire/convert

sequence for multiple channels. If the SIMSAM bit is

‘0’, the two or four se lec ted chan ne ls are acqu ired and

converted sequentially, with two or four sample clocks.

If the SIMSAM bit is ‘1’, two or four selected channels

are acquired simultaneously, with one sample clock.

The channels are then converted sequentially. Obvi-

ously, if there is only 1 channel selected, the SIMSAM

bit is not applicable .

The CHPS bits selects how many channels are sam-

pled. This can vary from 1, 2 or 4 channels. If CHPS

selects 1 channel, the CH0 channel will be sampled at

the sample clock and converted. The result is stored in

the buffer. If CHPS selects 2 channels, the CH0 and

CH1 channels w ill b e s am pl ed and con ve r ted . If C HP S

selects 4 channels, the CH0, CH1, CH2 and CH3

channels will be sampled and converted.

The SMPI bits select the number of acquisition/conver-

sion sequences that would be performed before an

interrupt occurs. This can vary from 1 sample per

interrupt to 16 samples per interrupt.

The user cannot program a combination of CHPS and

SMPI bits that specifies more than 16 conversions per

interrupt, or 8 conversions per interrupt, depending on

the BUFM bit. The BUFM bit, when set, will split the

16-word results buffer (ADCBUF0...ADCBUFF) into

two 8-word groups. Writing to the 8-word buffers will be

alternate d on each in terrupt event. Use o f the BUFM bit

will depend on how much time is available for moving

data o ut of the buf fers after the inte rrupt, as determine d

by the application.

If the processor can quickly unload a full buffer within

the time it takes to acquire and convert one channel,

the BUFM bit can be ‘0’ and up to 16 conversions may

be done per interrupt. The processor will have one

sample and conversion time to move the sixteen

conversions.

If the processor cannot unload the buffer within the

acquisition and conversion time, the BUFM bit should

be ‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) =

0111, then eight conversions will be loaded into 1/2 of

the buf fer , follo wing which an in terrupt occurs. The next

eight co nversions will b e loaded into the o ther 1/2 of the

buff er. The processor wil l have the enti re time b etween

interrupts to move the eight conversions.

The ALTS bit can be used to alternate the inputs

select ed durin g the samp ling sequ ence. The i nput mul-

tiplexer has two sets of sample inputs: MUX A and

MUX B. If the ALTS bit i s ‘0’, onl y the MUX A input s are

selected for sampling. If the ALTS bit is ‘1’ and

SMPI<3:0> = 0000, on the first sample/convert

sequence, the MUX A inputs are selected, and on the

next acquire/convert sequence, the MUX B inputs are

selected.

The CSCNA bit (ADCON2<10>) will allow the CH0

channel inputs to be alternately scanned across a

select ed number of analog i nputs for the MUX A g roup.

The inputs are selected by the ADCSSL register. If a

particular bit in the ADCSSL register is ‘1’, the corre-

sponding input is selected. The inputs are always

scanne d from low er to higher numbered in puts, st arting

after each interrupt. If the number of inputs selected is

greate r than the number of s amples ta ken per int errupt,

the higher numbered inputs are unused.

dsPIC30F2010

18.4 Programming the S tart of

Conversion Trigger

The conversion trigger will terminate acquisition and

start the requested conversions.

The SSRC<2:0> bits select the source of the

conversion trigger.

The SSRC bits provide for up to 5 alternate sources of

conversion trigger.

When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit will

cause the co nve r si on trigger.

When SSRC<2:0> = 111 (Auto-Start mode), the con-

version trigger is under A/D clock control. The SAMC

bits select the number of A/D clocks between the start

of acqu isitio n and the s t art of convers ion . Th is p rov ide s

the fastest conversion rates on multiple channels.

SAMC must always be at least 1 clock cycle.

Other trigger sources can come from timer modules,

Motor Control PWM module or external interrupts.

18.5 Aborting a Conversion

Clearing the ADON bit during a conversion will abort

the cu rrent conv ersion a nd stop the sam pling s equenc-

ing. The ADCBUF will not be updated with the partially

completed A/D conversion sample. That is, the

ADCBUF will continue to contain the value of the last

completed conversion (or the last value written to the

ADCBUF register).

If the clearing of the ADON bit coincides with an auto

start, the clearing has a higher priority.

After the A/D conversion is aborted, a 2 TAD wait is

required before the next sampling may be started by

setting the SAMP bit.

If sequ ential sam pling is s pecified, th e A/D will continue

at the next sample pulse which corresponds with the

next channel converted. If simultaneous sampling is

specified, the A/D will continue with the next

multichannel group conversion sequence.

18.6 Selecting the A/D Conversi on

Clock

The A/ D conv ersion requir es 12 TAD. The source of the

A/D conversion clock is software selected using a six

bit counter. There are 64 possible options for TAD.

EQUATION 18-1: A/D CONVERSION CLOCK

The internal RC oscillator is selected by setting the

ADRC bit.

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 83.33 nsec (for VDD = 5V). Refer to the Section 22.0

"Electrical Characteristics" for minimum TAD under

other ope rati ng con di tion s.

Example 18-1 shows a sample calculation for the

ADCS<5:0> bits, assuming a device operating speed

of 30 MIPS.

EXAMPLE 18-1: A/D CONVERSION CLOCK

CALCULATION

Note: To operate the A/D at the maximum

specified conversion speed, the Auto

Conve rt Trigg er op tion should be s ele cte d

(SSRC = 111) and the Auto Sample Time

bits should be set to 1 TAD (SAMC =

00001). This confi gu ratio n w il l gi ve a tot a l

conversion period (sample + convert) of

13 TAD.

The use of any other conversion trigger

will result in additional TAD cycles to

synchronize the external event to the A/D.

TAD = T CY * (0.5 * (ADCS<5:0> + 1))

ADCS<5:0> = 2 – 1

TAD

TCY

TAD = 84 nsec

ADCS<5:0> = 2 – 1

TAD

TCY

TCY = 33 nsec (30 MIPS)

= 2 • – 1

84 nsec

33 nsec

= 4.09

Therefore,

Set ADCS<5 :0> = 5

Actual TAD = (ADCS<5:0> + 1)

TCY

= (5 + 1)

33 nse c

= 99 nsec

dsPIC30F2010

18.7 A/D Conversion Speeds

The dsPIC30F 10-bit ADC specifications permit a

maximum 1 Msps sampling rate. Table 18-1

summarizes the conversion speeds for the dsPIC30F

10-bit ADC and the required operating conditions.

TABLE 18-1: 10-BIT A/D CONVERSION RATE PARAMETERS

dsPIC30F 10-bit A/D Converter Conversion Rates

A/D Speed TAD

Minimum Sampling

Time Min RS Max VDD Temperature A/D Channels Configuration

Up to

1 Msps(1) 83.33 ns 12 TAD 500Ω4.5V to 5.5V -40°C to +85°C

Up to

750 ksps(1) 95.24 ns 2 TAD 500Ω4.5V to 5.5V -40°C to +85°C

Up to

600 ksps(1) 138.89 ns 12 TAD 500Ω3.0V to 5.5V -40°C to +125°C

Up to

500 ksps 153.85 ns 1 TAD 5.0 kΩ4.5V to 5.5V -40°C to +125°C

Up to

300 ksps 256.41 ns 1 TAD 5.0 kΩ3.0V to 5.5V -40°C to +125°C

Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure 18-2 for recommended

circuit.

REF

-V

REF

ADC

ANx S/H

S/H

CH1, CH2 or CH3

CH0

REF

-V

REF

ADC

ANx S/H CH

REF

-V

REF

ADC

ANx S/H

S/H

CH1, CH2 or CH3

CH0

REF

-V

REF

ADC

ANx S/H CH

ANx or V

REF

-V

REF

ADC

ANx S/H CH

ANx or V

REF

dsPIC30F2010

The configuration guidelines give the required setup

values for the conversion speeds above 500 ksps,

sinc e t h ey r equ i r e ex ter n a l VREF pins usage and there

are some differences in the configuration procedure.

Configuration details that are not critical to the

conversion speed have been omitted.

Figure 18-2 depicts the recommended circuit for the

conversion rates above 500 ksps.

FIGURE 18-2: ADC VOLTAGE REFERENCE SCHEMATIC

18.7.1 1 Msps CONFIGURATION

GUIDELINE

The co nfiguration f or 1 Msp s operatio n is depen dent on

whether a single input pin is to be sampled or whether

multiple pins w ill be sampled.

18.7.1.1 Single Analog Input

For conversions at 1 Msps for a single analog input, at

least two sample and hold channels must be enabled.

The analog input multiplexer must be configured so

that the same input pin is connected to both sample

and hol d chan nel s. The A/D con ver ts t he va lue he ld on

one S/H channel, while the second S/H channel

acq uires a new input sample.

18.7.1.2 Multiple Analog Inputs

The A /D conv erter c an als o be used t o sam ple m ultipl e

analog inputs usin g multiple sample and ho ld channels.

In this cas e, the tot al 1 Msp s conver sio n rate is divide d

among the different input signals. For example, four

inputs can be sampled at a rate of 250 ksps for each

signal or two inputs could be sampled at a rate of

500 ksps for each signal. Sequential sampling must be

used in this configuration to allow adequate sampling

time on each input.

18.7.1.3 1 Msps Configuration Items

The following configuration items are required to

achieve a 1 Msps conversion rate.

• Compl y with con di t ion s provided in Table 19-2

• Connect external VREF+ and V REF- pins following

the recommended circuit shown in Figure 18-2

• Set SSRC<2:0> = 111 in the ADCON1 regist er to

enable the auto-convert option

• Enable automatic sampling by setting the ASAM

control bit in the AD CON1 register

• Enable sequential sampling by clearing the

SIMSAM bit in the ADCON1 register

• Enable at least two sample and hold channels by

writin g the CHPS <1:0> control bits in the

ADCON2 register

• Write the SMPI<3:0> control bits in the ADCON2

between interrupts. At a minimum, set

SMPI<3:0> = 0001 s ince at least two s ample and

hold channels should be enabled

• Config ure the A/D clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register

• Configure the sampling time to be 2 TAD by

writing: SAMC<4:0> = 00010

• Select at least two channels per analog input pin

by writing to the ADCHS register

REF

dsPIC30F2010

0.1

FC1

0.01

12 x 1,000,000 = 83.33 ns

dsPIC30F2010

18.7.2 750 ksps CONFIGURATION

GUIDELINE

The following configuration items are required to

achiev e a 7 50 ks p s con ve rsion rate. This c onfi guration

assumes that a single analog input is to be sampled.

• Compl y with con di t ion s provided in Table 18-2

• Connect exter nal VREF+ and VREF- pins following

the recommended circuit shown in Figure 18-2

• Set SSRC<2:0> = 111 in the ADCON1 register to

enable the auto-convert opti on

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register

• Enable one sample and hold channel by setting

CHPS<1:0> = 00 in the ADCON2 register

• Write the SMPI<3 :0> con trol bit s in the ADCON2

between interrupts

• Configure t he A/ D clo c k period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register

• Configure the sampling time to be 2 TAD by

writing: SAMC<4:0> = 00010

18.7.3 600 ksps CONFIGURATION

GUIDELINE

The configuration for 600 ksps operation is dependent

on whether a single input pin is to be sampled or

whether multiple pins will be sampled.

18.7.3.1 Single Analog Input

When performing conversions at 600 ksps for a single

analog input, at least two sample and hold channels

must be enabled. The ana log input multiple xer must b e

configured so that the same input pin is connected to

both samp le an d ho ld c han nels. Th e A/D conv erts the

value held on one S/H channel, while the second S/H

channel acquires a new input sample.

18.7.3.2 Multiple Analog Input

The ADC can also be used to sample multiple analog

input s using mult iple sampl e and hold chann els. In thi s

case, the total 600 ksps conversion rate is divided

among the different input signals. For example, four

inputs can be sampled at a rate of 150 ksps for each

signal or two inputs can be sampled at a rate of 300

ksps for each signal. Sequential sampling must be

used in this configuration to allow adequate sampling

time on each input.

18.7.3.3 600 ksps Configuration Items

The following configuration items are required to

achieve a 600 ksps conversion rate.

• Comply with conditions provided in Table 18-2

• Connect external VREF+ and V REF- pins following

the recommended circuit shown in Figure 18-2

• Set SSRC<2:0> = 111 in the ADCON1 regist er to

enable the auto-convert option

• Enable automatic sampling by setting the ASAM

control bit in the AD CON1 register

• Enable sequential sampling by clearing the

SIMSAM bit in the ADCON1 register

• Enable at least two sample and hold channels by

writin g the CHPS <1:0> control bits in the

ADCON2 register

• Write the SMPI<3:0> control bits in the ADCON2

between interrupts. At a minimum, set

SMPI<3:0> = 0001 s ince at least two s ample and

hold channels should be enabled

• Config ure the A/D clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register

• Configure the sampling time to be 2 TAD by

writing: SAMC<4:0> = 00010

Select at least two channels per analog input pin by

writing to the ADCHS register.

(12 + 2) X 750,000

= 95.24 ns

12 x 600,000 = 138.89 ns

dsPIC30F2010

18.8 A/D Acquisition Requirements

The analog input model of the 10-bit ADC is shown in

Figure 18-3. The total sampling time for the A/D is a

function of the internal amplifier settling time, device

VDD and the ho lding capacitor charge time.

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the voltage level on the analog input

pin. The source impedance (RS), the interconnect

impedance (RIC), and the internal sampling switch

(RSS) impedance combine to directly affect the time

required to cha rge the capac itor CHOLD. The combined

impedance of the analog sources must therefore be

small enough to fully charge the holding capacitor

within the c hos en sam pl e tim e. To minim iz e the ef fe cts

of pin lea kage curren ts on the accuracy of th e A/D con-

verter, the maximum recommended source imped-

ance, RS, is 5 kΩ. After the analog input channel is

selected (changed), this sampling function must be

comple ted p r ior to s t art ing the co nve r si on. Th e internal

holdi ng capaci tor wi ll be i n a disc harged state pr ior to

each sample operation.

The us er mus t all ow at le ast 1 TAD pe riod o f sampl ing

time, TSAMP, between conversions to allow each sam-

ple to be ac quired . This s ample time ma y be co ntrolle d

manually in software by setting/clearing the SAMP bit,

or it may be automatically controlled by the A/D con-

verter. In an automatic configuration, the user must

allow eno ugh tim e betw e en con ve rsion triggers s o th at

the min imum samp le time c an be sa tisfied. Re fer to the

Electrical Specifications for TAD and sample time

requirements.

FIGURE 18-3: ADC ANALOG INPUT MODEL

CPIN

Rs ANx VT = 0.6V

VT = 0.6V I leakage

RIC ≤ 250ΩSampling

Switch

RSS

CHOLD

= DAC capac itance

VSS

VDD

= 4.4 pF

± 500 nA

Legend: CPIN

I leakage

RIC

RSS

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch resistance

= sample/ hol d capacitance (fro m DA C)

various junctions

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.

RSS ≤ 3 kΩ

dsPIC30F2010

18.9 Module Power-Down Modes

The module has 3 internal power modes. When the

ADON bit is ‘1’, the module is in Active mode; it is fully

powered and function al. When ADO N is ‘0’, th e module

is in Off mode. The digital and analog portions of the

circuit are disabled for maximum current savings. In

order to return to the Active mode from Off mode, the

user must wait for the ADC circuitry to stabilize.

18.10 A/D Operation During CPU Sleep

and Idle Modes

18.10.1 A /D OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the con-

version is aborted. The converte r will not c onti nue with

a partially completed conversion on exit from Sleep

mode.

entering or leaving Sleep mode.

The A/D module can operate during Sleep mode if the

A/D clock source is set to RC (ADRC = 1). When the

RC cloc k sourc e is sel ected , the A/D mo dule w ait s one

instruction cycle before starting the conversion. This

allows the SLEEP instruction to be executed, which

eliminates all digital switching noise from the conver-

sion. When the conversion is complete, the DONE bit

will be set and the result loaded into the ADCBUF

If the A/D interrupt is enabled, the device will wake-up

from Sleep. If the A/D interrupt is not enabled, the A/D

module will then be turned off, although the ADON bit

will remain set.

18.10.2 A/D OPERATION DURING CPU IDLE

MODE

The ADSIDL bit select s if the mod ule will stop on Idle or

continue on Idle. If ADSIDL = 0, the module will con-

tinue operation on assertion of Idle mode. If

ADSIDL = 1, the module will stop on Idle.

18.11 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off, and any

conversion and acquisition sequence is aborted. The

values that are in the ADCBUF registers are not modi-

fied. The A/D result register will contain unknown data

after a Power-on Reset.

18.12 Output Formats

The A/D result is 10 bits wide. The data buffer RAM is

also 10 b it s wid e. The 10 -bit data can be rea d in one of

four different formats. The FORM<1:0> bits select the

format. Each of the outpu t format s trans lates t o a 16-bit

result on the data bus.

Write data will always be in right justified (integer)

format.

FIGURE 18-4: A/D OUTPUT DATA FORMATS

RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Signed Fractional (1.15) d09 d08d07d06d05d04d03d02d01d00000000

Fractional (1.15)d09d08d07d06d05d04d03d02d01d00000000

Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

dsPIC30F2010

18.13 Configuring Analog Port Pins

The use of the ADPC FG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared (out-

put), the digital output level (VOH or VOL) will be

converted.

The A/D operation is independent of the state of the

CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.

When read ing the POR T register, all pins c onfigured a s

analog input channels will read as cleare d.

Pins configured as digital inp uts will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins), may cause the

input buffer to consume current that exceeds the

device specifications.

18.14 Connection Considerations

The anal og inp uts h ave diod es to VDD and V SS as ESD

protection. This requires that the analog input be

betwee n VDD and VSS. If the input voltage exceeds this

range by greater th an 0.3V (eit her direct ion), one o f the

diodes becomes forward b iased and it may damage the

device if the input curre nt specificati on is exce ede d.

An external RC filter is sometimes added for anti-

aliasi ng of the input signal. The R component should be

select ed to ens ure that th e sampl ing time requirem ents

are satisfied. Any external components connected (via

high-impedance) to an analog input pin (capacitor,

zener diode, etc.) should have very little leakage

current at the pin.

dsPIC30F2010

TABLE 18-2: ADC REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

ADCBUF0 0280 — — — — — — ADC Data Buffer 0 0000 00uu uuuu uuuu

ADCBUF1 0282 — — — — — — ADC Data Buffer 1 0000 00uu uuuu uuuu

ADCBUF2 0284 — — — — — — ADC Data Buffer 2 0000 00uu uuuu uuuu

ADCBUF3 0286 — — — — — — ADC Data Buffer 3 0000 00uu uuuu uuuu

ADCBUF4 0288 — — — — — — ADC Data Buffer 4 0000 00uu uuuu uuuu

ADCBUF5 028A — — — — — — ADC Data Buffer 5 0000 00uu uuuu uuuu

ADCBUF6 028C — — — — — — ADC Data Buffer 6 0000 00uu uuuu uuuu

ADCBUF7 028E — — — — — — ADC Data Buffer 7 0000 00uu uuuu uuuu

ADCBUF8 0290 — — — — — — ADC Data Buffer 8 0000 00uu uuuu uuuu

ADCBUF9 0292 — — — — — — ADC Data Buffer 9 0000 00uu uuuu uuuu

ADCBUFA 0294 — — — — — — ADC Data Buffer 10 0000 00uu uuuu uuuu

ADCBUFB 0296 — — — — — — ADC Data Buffer 11 0000 00uu uuuu uuuu

ADCBUFC 0298 — — — — — — ADC Data Buffer 12 0000 00uu uuuu uuuu

ADCBUFD 029A — — — — — — ADC Data Buffer 13 0000 00uu uuuu uuuu

ADCBUFE 029C — — — — — — ADC Data Buffer 14 0000 00uu uuuu uuuu

ADCBUFF 029E — — — — — — ADC Data Buffer 15 0000 00uu uuuu uuuu

ADCON1 02A0 ADON —ADSIDL— — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 0000 0000 0000

ADCON2 02A2 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000

ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000

ADCHS 02A6 CH123NB<1:0> CH123SB CH0NB CH0SB<3:0> CH123NA<1:0> CH123SA CH0NA CH0SA<3:0> 0000 0000 0000 0000

ADPCFG 02A8 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

ADCSSL 02AA — — — — — — — — — — CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

19.0 SYSTEM INTEGRATION

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external component s, provide Power-Saving Operating

modes and of fer code protection:

• Oscillator Selection

• Reset

- Power-on Reset (P OR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Programmable Brown-out Reset (BOR)

• Watchdog Timer (WDT)

• Power-Saving modes (Sleep and Idle)

• Code Protection

• Unit ID Locations

• In-Circuit Serial Programming (ICSP)

programming capability

dsPIC30F devices have a Watchdog Timer, which is

permanently enabled via the Configuration bits, or can

be software controlled. It runs off its own RC oscillator

for added re liability. There are two timers tha t offer ne c-

essary de la ys on p ow er-u p. On e is the O s cil la tor Star t-

up T imer (OST), intended to keep the chip in Reset unti l

the crystal oscillator is stable. The other is the Power-

up T i mer (P WR T), w hich p rovi des a delay on p ower-up

only, designed to keep the part in Reset while the

power supply stabilizes. With these two timers on-chip,

most applications need no external Reset circuitry.

Sleep mode is designed to offer a very low current

Power-down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer Wake-up or

through an inte rrupt. Several os cillator opti ons are also

made available to allow the part to fit a wide variety of

applications. In the Idle mode, the clock sources are

still active, but the CPU is shut off. The RC oscillator

option saves system cost, while the LP crystal option

saves power.

19.1 Oscillator System Overview

The dsPIC30F oscillator system has the following

modules and features:

• Various external and internal oscillator options as

clock sources

• An on-chip PLL to boost internal operating

frequency

• A clock switching mechanism between various

clock sources

• Programm abl e c loc k pos t s ca ler for system po w er

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• Clock Control Register OSCCON

• Configuration bits for main oscillator selection

Table 19-1 provides a summary of the dsPIC30F

Oscillat or Operating modes. A simplified diagram of the

oscillator system is shown in Figure 19-1.

Configuration bits determine the clock source upon

Power-on Reset (POR) and Brown-out Reset (BOR).

Thereafter, the clock source can be changed between

permissible clock sources. The OSCCON register

controls the clock switching and reflects system clock

related status bits.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F2010

TABLE 19-1: OSCILLATOR OPERATING MODES

Oscillator Mode Description

XTL 200 kHz-4 MHz crystal on OS C1:OSC2.

XT 4 MHz-10 MHz crystal on OSC1:OSC2.

XT w/ PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled.

XT w/ PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled.

XT w/ PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled(1).

LP 32 kHz crystal on SOSCO:SOSCI(2).

HS 10 MHz-25 MHz crystal.

EC External clock input (0-40 MHz).

ECIO External clock input (0-40 MHz). OSC2 pin is I/O.

EC w/ PLL 4x External clock input (0-40 MHz). OSC2 pin is I/O. 4x PLL enabled(1).

EC w/ PLL 8x External clock input (0-40 MHz). OSC2 pin is I/O. 8x PLL enabled(1).

EC w/ PLL 16x External clock input (0-40 MHz). OSC2 pin is I/O. 16x PLL enabled(1).

ERC External RC oscillator. OSC2 pin is FOSC/4 output(3).

ERCIO External RC oscillator. OSC2 pin is I/O(3).

FRC 7.37 MHz internal RC Oscillator.

LPRC 512 kHz internal RC Oscillator.

Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.

2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.

3: Requires external R and C. Frequency operation up to 4 MHz.

dsPIC30F2010

FIGURE 19-1: OSCILLATOR SYSTEM BLOCK DIAGRAM

Primary

OSC1

OSC2

SOSCO

SOSCI

Oscillator

32 kHz LP

Clock

and Control

Block

Switching

Oscillator

x4, x8, x16

PLL

Primary

Oscillator

Stability Detector

Secondary

Oscillator

Programmable

Clock Divider

Oscillator

Start-up

Timer

Fail-Safe Clock

Monitor (FSCM)

Internal Fast RC

Oscillator (FRC)

Internal Low

Power RC

Oscillator (LPRC)

PWRSAV Instruction

Wake-up Request

Oscillator Configuration bits

System

Clock

Oscillator Trap

to Timer1

LPRC

FRC

Secondary Osc

POR Done

Primary Os c

FPLL

POST<1:0>

FCKSM<1:0> 2

PLL

Lock COSC<1:0>

NOSC<1:0>

OSWEN

dsPIC30F2010

19.2 Oscillator Configurations

19.2.1 INITIAL CLOCK SOURCE

SELECTION

While coming out of Power-on Reset or Brown-out

Reset, th e device sel ects its clock source based on:

a) FOS<1:0> Configuration bits that select one of

four oscillator groups.

b) AND FPR<3:0> Configuration bits that select one

of 13 oscillator choices within the primary group.

The selection is as shown in Table 19-2.

19.2.2 OSCILLATOR START-UP TIMER

(OST)

In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an oscillator

start-up timer is included. It is a simple 10-bit counter

that counts 1024 TOSC cycles before releasing the

oscillator clock to the rest of the system. The time-out

period is designated as TOST. The TOST time is involved

every time the oscillator has to restart (i.e., on POR,

BOR and wake-up from Sleep). The oscillator start-up

timer is applied to the LP Oscillator, XT, XTL, and HS

modes (upon wake-up from Sleep, POR and BOR) for

the primary oscillator.

TABLE 19-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator

Source FOS1 FOS0 FPR3 FPR2 FPR1 FPR0 OSC2

Function

EC Primary 111011 CLKO

ECIO Primary 111100 I/O

EC w/ PLL 4x Primary 111101 I/O

EC w/ PLL 8x Primary 111110 I/O

EC w/ PLL 16x Primary 111111 I/O

ERC Primary 111001 CLKO

ERCIO Primary 111000 I/O

XT Primary 110100 OSC2

XT w/ PLL 4x Primary 110101 OSC2

XT w/ PLL 8x Primary 110110 OSC2

XT w/ PLL 16x Primary 110111 OSC2

XTL Primary 11000X OSC2

HS Primary 11001X OSC2

LP Secondary 0 0 ————(No tes 1, 2)

FRC Internal FRC 0 1 ————(Notes 1, 2)

LPRC Internal LPRC 1 0 ————(Notes 1, 2)

Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>).

2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock

source is selected at all times.

dsPIC30F2010

19.2.3 LP OSCILLATOR CONTROL

Enabling the LP oscillator is controlled with two

elements:

1. The current oscillator group bits COSC<1:0>.

2. The LPOSCEN bit (OSCCON register).

The LP oscillator is ON (even during Sleep mode) if

LPOSCEN = 1. The LP oscillator is the device clock if:

• COSC<1:0> = 00 (LP selected as main oscillator)

and

• LPOSCEN = 1

Keeping the LP oscillator ON at all times allows for a

fast swit ch to the 3 2 kHz syst em cl oc k f or lowe r powe r

operation. Returning to the faster main oscillator will

still require a start-up time

19.2.4 PHASE LOCKED LOOP (PLL)

The PLL multi plies the clock wh ic h is gen era ted by the

primary oscillator or Fast RC oscillator. The PLL is

select able t o have either ga ins of x 4, x8, and x16. Inp ut

and output frequency ranges are summarized in

Table 19-3.

TABLE 19-3: PLL FREQUENCY RANGE

The PLL fea tures a lo ck out put which is assert ed whe n

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g ., due to nois e), the lock signal will b e

rescinded. The state of this signal is reflected in the

read-only LOCK bit in the OSCCON register.

19.2.5 FAST RC OSCILLATOR (FRC)

The FRC oscillator is a fast (7.37 MHz ±2% nominal)

inter nal RC o scil lat or. This osci llator is inten ded to p ro-

vide reasonable device operating speeds without the

use of an external crystal, ceramic resonator or RC

network.

The dsPIC30F operates from the FRC oscillator when

the current oscillator selection control bits in the

OSCCON register (OSCCON<13:12>) are set to ‘01’.

The four bit field specified by TUN<3:0> (OSCCON

<15:14> and OSCCON<1 1:10>) all ows the user to tune

the internal fast RC oscillator (nominal 7.37MHz). The

user c an tune the FR C osci llator wit hin a r ange of -12%

(or -960 kHz) to +10.5% (or +840 kHz) in steps of

1.50% around the factory calibrated setting, see

Table 19-4.

TABLE 19-4: FRC TUNING

19.2.6 LOW-POWER RC OSCILLATOR

(LPRC)

The LPRC oscillator is a component of the Watchdog

Timer (WDT) and oscillates at a nominal frequency of

512 kHz. The LPRC oscillator is the clock source for

the Power-up Timer (PWRT) circuit, WDT, and clock

monitor circuits. It may also be used to provide a low

frequency clock source option for applications where

power consumption is critical and timing accuracy is

not required

The LPRC oscillator is always enabled at a Power-on

Reset because it is the clock source for the PWRT.

After the PWRT expires, the LPRC oscillator will

remain on if one of the following is true:

• The Fail-Safe Clock Monitor is enabled

• The WDT is enabled

• The LPRC oscillator is selected as the system

clock via the COSC<1:0> control bits in the

OSCCON register

If one of the above conditions is not true, the LPRC will

shut-off after the PWRT expires.

FIN PLL

Multiplier FOUT

4 MHz-10 MHz x4 16 MHz-40 MHz

4 MHz-10 MHz x8 32 MHz-80 MHz

4 MHz-7.5 MHz x16 64 MHz-120 MHz

TUN<3:0>

Bits FRC Frequency

0111 + 10.5%

0110 + 9.0%

0101 + 7.5%

0100 + 6.0%

0011 + 4.5%

0010 + 3.0%

0001 + 1.5%

0000 Center Frequency (oscillator is

running at calibrated frequency)

1111 - 1.5%

1110 - 3.0%

1101 - 4.5%

1100 - 6.0%

1011 - 7.5%

1010 - 9.0%

1001 - 10.5%

1000 - 12.0%

Note 1: OSC2 pin function is determined by the

Primary Oscillator mode selection

(FPR<3:0>).

2: OSC1 pin cannot be used as an I/O pin

even if the secondary oscillator or an

internal clock source is selected at all

times.

dsPIC30F2010

19.2.7 FAIL-SAFE CLOCK MONITOR

The Fail-Saf e Cl oc k Mo nit or (F SCM) al low s the dev ic e

to conti nue to operate even i n the e vent o f an os cilla tor

failure. The FSCM functi on i s e nab le d by ap pro pria tel y

programming the FCKSM Configuration bits (Clock

Switch and Monitor Selection bits) in the FOSC device

Configuration register. If the FSCM function is

enabled, the LPRC Internal oscillator will run at all

times (except during Sleep mode) and will not be

subject to control by the SWDTEN bit.

In the event of an oscillator failure, the FSCM will gen-

erate a clock failure trap event and will switch the sys-

tem cloc k ove r to the FRC oscil lator. The us er w ill the n

have the op tion to either att empt to restart the oscil lator

or exec ute a controlled shutdown . The user may decide

to treat th e tra p a s a warm Res et by si mp ly loading the

Reset address into the oscillator fail trap vector. In this

event, the CF (Clock Fail) status bit (OSCCON<3>) is

also set whenever a clock failure is recognized.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If the oscillator has a very slow start-up time coming

out of POR, BOR or Sleep, it is possible that the

PWRT timer will expire before the oscillator has

started. In such cases, the FSCM will be activated and

the FSCM will initiate a clock failure trap, and the

COSC<1:0> bits are loaded with FRC oscillator selec-

tion. This will effectively shut-off the original oscillator

that was trying to start.

The user may detect this situation and restart the

oscillator in the clock fail trap ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC Oscillator as follows:

1. The COSC bits (OSCCON<13:12>) are loaded

with the FRC Oscillator selection value.

2. CF bit is set (OSCCON<3>).

3. OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

1. Primary

2. Secondary

3. Internal FRC

4. Internal LPRC

The user can switch between these functional groups,

but canno t switch between opt ions within a group. If the

primary group is selected, then the choice within the

group is always determined by the FPR<3:0>

Configuration bits.

The OSC CON register holds t he control and Status bits

related to clock switching.

• COSC<1:0>: Read-only status bits always reflect

the current oscillator group in effect.

• NOSC<1:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<1:0> and

NOSC<1:0> are both l oaded with the

Configuration bit values FOS<1:0>.

• LOCK: The LOCK status bit indicates a PLL lock.

• CF: Read-only status bit indicating if a clock fail

detect has occurred.

• OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit will abort a clock

transition in progress (used for hang-up

situations).

If Configuration bits FCKSM<1:0> = 1x, then the clock

switchin g and fail -safe clock moni tor functions are

disabled. This is the default Configuration bit setting.

If clock switching is disabled, then the FOS<1:0> and

FPR<3:0> bits directly control the oscillator selection

and the COSC<1:0> bits do not control the clock

selection. However, these bits will reflect the clock

source selection.

19.2.8 PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

A write to the OSCCON regis ter is intentionally made

difficult because it controls clock switching and clock

scaling.

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

•Byte Write “0x46” to OSCCON low

•Byte Write “0x57” to OSCCON low

Byte Write i s allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

•Byte Write “0x78” to OSCCON high

•Byte Write “0x9A” to OSCCON high

Byte Write i s allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

Note: The application should not attempt to

switch to a clock of frequency lower than

100 KHz when the fail-safe clock monitor is

enabled. If such clock switching is

performed, the device may generate an

oscillator fail trap and switch to the Fast RC

oscillator.

dsPIC30F2010

19.3 Reset

The dsPIC30F2010 differentiates between various

kinds of Re set :

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) Watchdog Timer (WDT) Reset (during normal

operation)

e) Programmable Brown-out Reset (BOR)

f) RESET Inst ruction

g) Reset cause by trap lockup (TRAPR)

h) Reset caused by illegal opcode, or by using an

uninitialized W register as an Address Pointer

(IOPUWR)

Dif fer ent regi sters a re a ffe cted in dif fe rent w ays by var-

ious Reset conditions. Most registers are not affected

by a WD T wake-up, since this is viewed as the resump-

tion of normal operation. Status bits from the RCON

situations, as indicated in Table 19-5. These bits are

used in s oftwa re to dete rmi ne th e na ture of the Reset.

A block di agram of the on-ch ip Reset circuit is shown in

Figure 19-2.

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

Internall y generated Res ets do not drive MCLR pi n low .

FIGURE 19-2: RESET SYSTEM BL OCK DIA GRAM

19.3.1 POR: PO W ER-O N RESET

A power-on event will generate an internal POR pulse

when a VDD rise is detected. The Reset puls e will occur

at the POR circuit threshold voltage (VPOR), which is

nominally 1.85V. The device supply voltage character-

istics mus t meet spec ified sta rting v olt ag e and rise ra te

requirements. The POR pulse will Reset a POR timer

and place the device in the Reset state. The POR also

selects the device clock source identified by the

oscillator configuration fuses.

The POR circuit inserts a small delay, TPOR, which is

nominally 10 μs and ensures that the device bias cir-

cuits are stable. Furthermore, a user selected power-

up time-out (TPWRT) is applied. The TPWRT pa ra me te r

is based on device Configuration bits and can be 0 ms

(no delay), 4 ms, 16 ms or 64 ms. The total delay is at

device power-up TPOR + TPWRT. When these delays

have expired, SYSRST will be negated on the next

leading edge of the Q1 clock, and the PC will jump to

the Reset vector.

The timing for the SYSRST signal is shown in

Figure 19-3 through Figure 19-5.

MCLR

VDD

VDD Rise

Detect POR

SYSRST

Sleep or Idle

Brown-out

Reset BOREN

RESET

Instruction

WDT

Module

Digital

Glitch Filter

BOR

Trap Conflict

Illegal Opcode/

Uninitialized W Register

dsPIC30F2010

FIGURE 19-3: TIME-OUT SEQUENCE ON POWER -UP (MCLR TIED TO VDD)

FIGURE 19-4: TIME-OUT SEQUENCE ON POWER -UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 19-5: TIME-OUT SEQUENCE ON POWER -UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

MCLR

TPWRT

TOST

VDD

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

MCLR

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

TPWRT

TOST

dsPIC30F2010

19.3.1.1 POR with Long Crystal Start-up Time

(with FSCM Enabled)

The osci ll ator s t art-up circuit r y is not linked to the POR

circuitry. Some crystal circuits (especially low fre-

quency crystals) will have a relatively long start-up

time. Th erefore, one or more of the foll owing condit ions

is possible after the POR timer and the PWRT have

expired:

• The oscillator circuit has not begun to oscillate.

• The osc il lat or s t art -up tim er h as N OT ex pi red (if a

crystal oscillator is used).

• The PLL has not achieved a L OCK (if PLL is

used).

If th e FSCM is enabled and one of th e above c onditions

is true, then a clock failure trap will occur. The device

will automatically switch to the FRC oscillator and the

user can switch to the desired crystal oscillator in the

trap ISR.

19.3.1.2 Operating without FSCM and PWRT

If the FSCM is disabled and the Power-up Timer

(PWRT) is also disabled, then the device will exit rap-

idly from Reset on power-up. If the clock source is

FRC, LPRC, EXTRC or EC, it will be active

immediately.

If the FSCM is disabled and the system clock has not

start ed, the de vice w ill be in a frozen st ate at th e Res et

vector until the system clock starts. From the user’s

perspective, the device will appear to be in Reset until

a system clock is available.

19.3.2 BOR : PROG RA MMA BL E

BROWN-OUT RESET

The BOR mod ule is ba sed on a n interna l volt age ref er-

ence c ircuit. The m ain purpose o f the BOR modu le is to

generate a device Reset when a brown-out condition

occurs. Brown-out conditions are generally caused by

glitches on the AC mains (i.e., missing portions of the

AC cycle waveform due to bad power transmission

lines or voltage sags due to excessive current draw

when a large inductive load is turned on).

The BOR module allows selection of one of the follow-

ing voltage trip points:

•2.6V-2.71V

•4.1V-4.4V

• 4.58V-4.73V

A BOR will generate a Reset pulse whi ch will rese t the

device. The BOR will select the clock source, based on

the device Configuration bit values (FOS<1:0> and

FPR<3:0>). Furthermore, if an Oscillator mode is

selected, the BOR will activate the Oscillator Start-up

Timer (OST). The system clock is held until OST

expires. If the PLL is used, then the clock will be held

until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the POR time-out (TPOR) and the PWRT

time-out (TPWRT) will be applied before the internal

Reset is released. If TPWRT = 0 and a crystal oscillator

is being used , the n a nom in al de lay of TFSCM = 100 μs

is applied. The total delay in this case is (TPOR +

TFSCM).

The B OR status bit (RCON <1>) wi ll be set to indic ate

that a BOR has occurred. The BOR circuit, if enabled,

will continue to operate while in Sleep or Idle modes

and wi ll reset the de vice shoul d VDD fall below the BOR

threshold voltage.

FIGURE 19-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

Note: The BOR voltage trip points indicated here

are nominal values provided for design

guidance only.

Note: Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be

used as an external Power-on Reset

circuit.

Note 1: External Power-on Reset circuit is

required only if the VDD power-up slope

is too slow. The diode D help s discharge

the capacitor quickly when VDD po wers

down.

2: R should be suitably chosen so as to

make sure that the voltage drop across

R does not violate the device’s electrical

specification.

3: R1 should be suitably chosen so as to

limit an y curre nt flow ing in to MCLR from

external capacitor C, in the event of

MCLR/VPP pin breakdown due to Elec-

trostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

dsPIC30F

MCLR

dsPIC30F2010

Table 19-5 shows the Reset conditions for the RCON

ter are R/W, the information in the table implies that all

the bits are negated prior to the action specified in the

conditi on column.

TABLE 19-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1

Table 19-6 shows a second example of the bit

conditi ons for th e R CO N Re gis ter. In this cas e, it is n ot

assu med th e use r has s et/ cle ared s peci fic bits pr ior to

action specified in the condition column.

TABLE 19-6: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2

Condition Program

Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR

Power-on Reset 0x000000 000000011

Brown-out Reset 0x000000 000000001

MCLR Reset during normal

operation 0x000000 001000000

Software Reset during

normal ope rati on 0x000000 000100000

MCLR Reset during Sleep 0x000000 001000100

MCLR Reset during Idle 0x000000 001001000

WDT Time-out Reset 0x000000 000010000

WDT Wake-up PC + 2 000010100

Interrupt Wake-up from

Sleep PC + 2(1) 000000100

Clock Failure Trap 0x000004 000000000

Trap Reset 0x000000 100000000

Illegal Operation Trap 0x000000 010000000

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’

Note 1: When the wake-up is du e to an enable d inte rrupt, the PC is lo aded w ith th e corre spond ing in terrupt vec tor.

Condition Program

Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR

Power-on Reset 0x000000 000000011

Brown-out Reset 0x000000 uuuuuuu01

MCLR Reset during normal

operation 0x000000 uu10000uu

Software Reset during

normal ope rati on 0x000000 uu01000uu

MCLR Reset during Sleep 0x000000 uu1u001uu

MCLR Reset during Idle 0x000000 uu1u010uu

WDT Time-out Reset 0x000000 uu00100uu

WDT Wake-up PC + 2 uuuu1u1uu

Interrupt Wake-up from

Sleep PC + 2(1) uuuuuu1uu

Clock Failure Trap 0x000004 uuuuuuuuu

Trap Reset 0x000000 1uuuuuuuu

Illegal Operation Reset 0x000000 u1uuuuuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’

Note 1: When the wake -up is due to an en abled i nterrupt , the PC is loa ded with the co rrespon ding in terrupt v ector.

dsPIC30F2010

19.4 Watchdog Timer (WDT)

19.4.1 WATCHDOG TI MER OPERATION

The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software mal-

function. The WDT is a free running timer, which runs

off an on-chip RC oscil lator, requi ring no e xte rnal com -

ponent. Th erefore, the WDT tim er will continue to oper-

ate even if the main processor clock (e.g., the crystal

oscillator) fails.

19.4.2 ENABLING AND DISABLING THE

WDT

The Watchdog Timer can be “Enabled” or “Disabled”

only through a Configuration bit (FWDTEN) in the

Configuration register FWDT.

Setting FWDTEN = 1 enables the Watchdog Timer.

The enabling is done when programming the device.

By default, after chip-erase, FWDTEN bit = 1. Any

device programmer capable of programming

dsPIC30F devices allows programming of this and

other Configuration bits.

If enabled, the WDT will increment until it overflows or

“times out”. A WDT time-out will force a device Reset

(except during Sleep). To prevent a WDT time-out, the

user must clear the Watchdog Timer using a CLRWDT

instruction.

If a WDT times out during Sleep, the device will wake-

up. The WDT O bit in the RCO N register wil l be cleare d

to indicate a wake-up resulting from a WDT time-out.

Setting FWDTEN = 0 allows user software to enable/

disable the Watchdog Timer via the SWDTEN

(RCON<5>) control bit.

19.5 Power-Saving Modes

There are tw o powe r-saving s tate s that c an be entere d

through the execu tion of a spe ci al ins t ru cti on, PWRSAV.

These are: Sleep and Idle.

The format of the PWRSAV instruc tion is as follows:

PWRSAV <parameter>, where ‘parameter’ defines

Idle or Sleep mode.

19.5.1 SLEEP MODE

In Sleep m ode, t he clo ck to t he CPU a nd peri pheral s is

shutdown. If an on-chip oscillator is being used, it is

shutdown.

The fail-safe clock monitor is not functional during

Sleep, since there is no clock to monitor. However,

LPRC clock remains active if WDT is ope rational during

Sleep.

The Brown-out protection circuit and the Low Voltage

Detect circuit, if enabled, will remain functional during

Sleep.

The processor wakes up from Sleep if at least one of

the following conditions has occurred:

• any interrupt that is individually enabled and

meets the required priority level

• any Reset (POR, BOR and MCLR)

• WDT time-out

On waking up from Sleep mode, the processor will

restart the same clock that was active prior to entry

into Sleep mode. When clock switching is enabled,

bits COSC<1:0> will determine the oscillator source

that will be used on wake-up. If clock switch is

disabled, then there is only one sy ste m cl ock .

If the clock source is an oscillator, the clock to the

device will be held off until OST times out (indicating a

stable oscillator). If PLL is used, the system clock is

held off until LOCK = 1 (indicating that the PLL is

stab le). I n eit her c ase, TPOR, T LOCK and TPWRT delay s

are applied.

If EC, FRC, LPRC or ERC oscillators are used, then a

delay of TPOR (~ 10 μs) is applied. This is the smallest

delay possible on wake-up from Sleep.

Moreover, if LP oscillator was active during Sleep, and

LP is the oscillator used on wake-up, then the start-up

delay will be equal to TPOR. PWRT delay and OST

timer delay are not applied. In order to have the small-

est poss ible sta rt-up delay when waking up fro m Sleep,

one of these faste r wake-up optio ns shoul d be selecte d

before entering Sleep.

Any interrup t that is ind ividually en abled (usin g the cor-

responding IE bit) and meets the prevailing priority

level will be able to wake-up the processor . The proces-

sor will process the interrupt and branch to the ISR.

The Sleep status bit in RCON register is set upon

wake-up.

Note: If a POR or BOR occurred, the selection of

the oscillator is based on the FOS<1:0>

and FPR<3:0> Configuration bits.

Note: In spite of various delays applied (TPOR,

TLOCK and TPWRT), the crystal oscillator

(and PLL) may not be active at the end of

the time-out (e.g., for low-frequency crys-

tals. In such cases), if FSCM is enabled,

then the device will detect this as a clock

failure and process the clock failure trap,

the FRC osc illator w ill be enabled, and the

user will have to re-enable the crystal

oscill ator . If FSCM is n ot enable d, then th e

device will simply suspend execution of

code until the clock is stable, and will

remain in Sleep until the oscillator clock

has st a rted.

dsPIC30F2010

All Resets will wake-up the processor from Sleep

mode. Any Reset, other than POR, will set the Sleep

status bit. In a POR, the Sleep bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Sleep mode upon WDT time-out. The

Sleep and WDTO status bits are both set.

19.5.2 IDLE MODE

In Idle mode, the clock to the CPU is shutdown while

peripher als keep running. Unlike Sleep mode, the clock

sour ce rem ains active .

Several peripherals have a control bit in each module,

that allows them to operate during Idle.

LPRC fail-safe clock remains active if clock failure

detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions is true:

• on any interrupt that is individually enabled (IE bit

is ‘1’) and meets the required priority level

• on any Reset (POR, BOR, MCLR)

• on WDT time-out

Upon wake -up from Idle mode, the cloc k is reappli ed to

the CPU and inst ructio n executio n begin s imm ediate ly,

starting with the instruction following the PWRSAV

instruction.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to

wake-u p th e p roc es sor. The pro ce ssor w i ll p roc es s th e

interrupt and branch to the ISR. The Idle status bit in

RCON register is set upon wake-up.

Any Reset, other than POR, will set the Idle status bit.

On a POR, the Idle bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Idle mode upon WDT time-out. The Idle

and WDTO status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involved in wake-up from Idle.

19.6 Device Configuration Registers

The Configuration bits in each device Configuration

grammed by a device programmer, or by using the In-

Circuit Ser ial Programm ing (ICSP) prog ramming c ap a-

bility feature of the device. Each device Configuration

each register are used to hold configuration data.

There are four device Configuration registers available

to the user:

1. FOSC (0xF80000): Oscillator Configuration

2. FWDT (0xF80002): Watchdog Timer

Conf iguration Register

3. FBORPOR (0xF80004): BOR and POR

Configu ration Register

4. FGS (0xF8000A): General Code Segment

Configu ration Register

The placement of the Configuration bits is automati-

cally ha ndled when you sel ect the device in your device

programmer . The desired state of the Configuration bit s

may be sp ecified i n the source code (depen dent on the

languag e tool used ), or through th e programming inter-

face. After the device has been programmed, the appli-

cation software may read the Configuration bit values

through the table read instructions. For additional infor-

mation, plea se refer to the programm in g sp eci fic ati on s

of the device.

19.7 In-Circui t Debugger

When M PLAB® ICD2 is selected as a De bugger , the In-

Circuit Debugging functionality is enabled. This func-

tion all ows simp le de buggin g func tions whe n used w ith

MPLAB IDE. When the device has this feature e nabled,

some of the resources are not available for general

use. These resources include the first 80 bytes of data

RAM and two I/O pins.

One of fo ur pairs of debug I/O p ins m ay b e se lec ted by

the user using configuration options in MPLAB IDE.

These pin pairs are named EMUD/EMUC, EMUD1/

EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3.

In each c as e, th e se lec te d EMU D p in i s th e Em ula tio n/

Debug Data line, and the EMUC pin is the Emulation/

Debug Clock line. These pins will interface to the

MPLAB ICD 2 module available from Microchip. The

selected pair of Debug I/O pins is used by MPLAB

ICD 2 to send commands and receive responses, as

well as to send and receive data. To use the In-Circuit

Debugger function of the device, the design must

implement ICSP connections to MCLR, VDD, VSS,

PGC, PGD and the selected EMUDx/EMUCx pin pair.

This gives rise to two possibilities:

1. If EMUD/EMU C is selecte d as the Debug I/O pin

pair, then only a 5-pin interface is required, as

the EMUD and EMUC pin functions are multi-

plexed with the PGD and PGC pin functions in

all dsPIC30F devices.

2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/

EMUC3 is selected as the Debug I/O pin pair,

then a 7-pin interface is required, as the

EMUDx/EMUCx pin functions (x = 1, 2 or 3) are

not multiplexed with the PGD and PGC pin

functions.

Note: If the code protection configuration fuse

bits (FGS<GCP> and FGS<GWRP>)

have been programmed, an erase of the

entire code-protected device is only

possib le at vol tages VDD ≥ 4.5V.

dsPIC30F2010

TABLE 19-7: SYSTEM INTEGRATION REGISTER MAP

TABLE 19-8: DEVICE CONFIGURATION REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

RCON 0740 TRAPR IOPUWR BGST — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset.

OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 TUN0 NOSC<1:0> POST<1:0> LOCK —CF— LPOSCEN OSWEN Depends on Configuration bits.

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

File Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FOSC F80000 — FCKSM<1:0> — — — — FOS<1:0> ————FPR<3:0>

FWDT F80002 —FWDTEN— — — — — — — — — FWPSA<1:0> FWPSB<3:0>

FBORPOR F80004 — MCLREN — — — — PWMPIN HPOL LPOL BOREN — BORV<1:0> ——FPWRT<1:0>

FGS F8000A — — — — — — — — — — — — — — —GCPGWRP

Note: Refer to “dsPIC 30F Family Refere nce M anual” (DS70046) for descriptions of register bit fields.

dsPIC30F2010

NOTES:

dsPIC30F2010

20.0 INSTRUCTION SET SUMMARY

The dsPIC30F instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration from PIC

MCU instruction sets.

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode which specifies the instruction

type, and one or more operands which further specify

the operation of the instruction.

The instruction set is highly orthogonal and is grouped

into five bas ic ca tego ries:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• DSP operations

• Control operations

Table 20-1 shows the general symbols used in

des c ribing t he instructions.

The dsPIC30F instruction set summary in Table 20-2

lists all the instructions along with the status flags

affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand, which is typically a

• The second source operand, which is t ypically a

• The destination of the result, which is typically a

However , word or byte-ori ented file register instructions

have two operands:

• The file register specified by the value ‘f ’

• The destination, which could either be the file

‘WREG’

Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

• The W register (with or without an address modi-

fier) or file register (specified by the value of ‘Ws’

or ‘f’)

• The bit in the W register or file register

(specified by a literal value, or indirectly by the

contents of register ‘Wb’)

The litera l instruct ions that invo lve data m ovement ma y

use some of the following operands:

• A lite ral value to be lo aded i nto a W regi ster or file

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand, which is a register ‘Wb’

without any addre s s modifier

• The second source operand, which is a literal

value

• The dest ination of the result (only if not the same

as the first source operand), which is typically a

The MAC class of DSP instructions may use some of the

following operands:

• The accumulator (A or B) to be used (required

operand)

• The W regis ters t o be used as the two operands

• The X and Y address space prefetch operations

• The X and Y address space prefetch destinations

• The accumulator writ e-ba ck destination

The other DSP instructions do not involve any

multipl ic ati on, and may include:

• The accumul ator to be used (requ ired )

• The source o r destin ation ope rand (des ignated as

Wso or Wdo, respectively) with or without an

address modifier

• The amount of shift, specified by a W register

‘Wn’ or a literal value

The control instructions may use some of the following

operands:

• A program memory address

• The mode of the table read and table write

instructions

All instructions are a single word, except for certain

double word instructions, which were made double

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8MSbs are ‘0’s. If t his se co nd wo r d i s ex ec ute d as an

instruction (by itself), it will execute as a NOP.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F2010

Most single-word instructions are executed in a single

instruc tion cycle , u nle ss a co ndi tional test is tru e or the

program counter is changed as a result of the instruc-

tion. In these cases, the executio n takes tw o instructio n

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/c ompu ted bra nch), i ndirec t CALL/GOTO, al l t abl e

reads and writes and RETURN/RETFIE instructions,

which are single-word instructions, but take two or

three cycles. Certain instructions that involve skipping

over the subsequent instruction, require either two or

three cycles if the skip is performed, depending on

whether the instruction being skipped is a single-word

or two-word instruction. Moreover, double word moves

require two cycles. The double word instructions

execute in two instruction cycles.

Note: For more details on the instruction set,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description

#text Me ans literal defined by “text“

(text) Mean s “content of text“

[text] Means “the location addressed by text”

{ } Optional field or operation

<n:m> Register bit field

.b Byte mode selection

.d Double word mode selection

.S Shadow register select

.w Word mode selection (default)

Acc One of two accumulators {A, B}

AWB Accumulator write-back destination address register ∈ {W13, [W13] + = 2}

bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

C, DC, N, OV, Z MCU status bits: Carry, Digit Carry, Negative, Overflow, Zero

Expr Absolute address, label or expression (resolved by the linker)

fFile register address ∈ {0x0000...0x1FFF}

lit1 1-bit unsigned literal ∈ {0,1}

lit4 4-bit unsigned literal ∈ {0...15}

lit5 5-bit unsigned literal ∈ {0...31}

lit8 8-bit unsigned literal ∈ {0...255}

lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

lit14 14-bit unsigned literal ∈ {0...16384}

lit16 16-bit unsigned literal ∈ {0...65535}

lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be 0

None Field does not require an entry, may be blank

OA, OB, SA, SB DSP status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate

PC Program Counter

Slit10 10-bit signed literal ∈ {-512...511}

Slit16 16-bit signed literal ∈ {-32768...32767}

Slit6 6-bit signed literal ∈ {-16...16}

dsPIC30F2010

Wb Base W register ∈ {W0..W15}

Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn Dividend, Divisor working register pair (direct addressing)

Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈

{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}

Wn One of 16 working registers ∈ {W0..W15}

Wnd One of 16 destination working registers ∈ {W0..W15}

Wns One of 16 source working registers ∈ {W0..W15}

WREG W0 (working register used in file register instructions)

Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wx X data space prefetch address register for DSP instructions

∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,

[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,

[W9 + W12],none}

Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7}

Wy Y data space prefetch address register for DSP instructions

∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,

[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,

[W11 + W12], none}

Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7}

TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field Description

dsPIC30F2010

TABLE 20-2: INSTRUCTION SET OVERVIEW

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

word

# of

cycles Status Flags

Affected

1ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB

ADD f f = f + WREG 1 1 C,DC,N,OV,Z

ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z

ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z

ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB

2ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z

3AND AND f f = f .AND. WREG 1 1 N,Z

AND f,WREG WREG = f .AND. WREG 1 1 N,Z

AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z

4ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z

ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z

ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z

5BCLR BCLR f,#bit4 Bit Clear f 1 1 None

BCLR Ws,#bit4 Bit Clear Ws 1 1 None

6BRA BRA C,Expr Branch if Carry 1 1 (2) None

BRA GE,Expr Branch if greater than or equal 1 1 (2) None

BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None

BRA GT,Expr Branch if greater than 1 1 (2) None

BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None

BRA LE,Expr Branch if less than or equal 1 1 (2) None

BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None

BRA LT,Expr Branch if less than 1 1 (2) None

BRA LTU,Expr Branch if unsigned less than 1 1 (2) None

BRA N,Expr Branch if Negative 1 1 (2) None

BRA NC,Expr Branch if Not Carry 1 1 (2) None

BRA NN,Expr Branch if Not Negative 1 1 (2) None

BRA NOV,Expr Branch if Not Overflow 1 1 (2) None

BRA NZ,Expr Branch if Not Zero 1 1 (2) None

BRA OA,Expr Branch if accumulator A overflow 1 1 (2) None

BRA OB,Expr Branch if accumulator B overflow 1 1 (2) None

BRA OV,Expr Branch if Overflow 1 1 (2) None

BRA SA,Expr Branch if accumulator A saturated 1 1 (2) None

BRA SB,Expr Branch if accumulator B saturated 1 1 (2) None

BRA Expr Branch Unconditionally 1 2 None

BRA Z,Expr Branch if Zero 1 1 (2) None

BRA Wn Computed Branch 1 2 None

7BSET BSET f,#bit4 Bit Set f 1 1 None

BSET Ws,#bit4 Bit Set Ws 1 1 None

8BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

9BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None

10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1

(2 or 3) None

BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1

(2 or 3) None

dsPIC30F2010

11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1

(2 or 3) None

BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1

(2 or 3) None

12 BTST BTST f,#bit4 Bit Test f 1 1 Z

BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C

BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z

BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C

BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z

13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z

BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C

BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z

14 CALL CALL lit23 Call subr ou tine 2 2 None

CALL Wn Call indir ect subr ou ti ne 1 2 None

15 CLR CLR f f = 0x0000 1 1 None

CLR WREG WREG = 0x0000 1 1 None

CLR Ws Ws = 0x0000 1 1 None

CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB

16 CLRWDT CLRWDT Clear Watchdog T imer 1 1 WDTO,Sleep

17 COM COM f f = f 11N,Z

COM f,WREG WREG = f 11N,Z

COM Ws,Wd Wd = Ws 11N,Z

18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z

CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z

CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C,DC,N,OV,Z

19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z

CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z

20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,Ws Compare Wb with Ws, with Borrow

(Wb - Ws - C)1 1 C,DC,N,OV,Z

21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1

(2 or 3) None

22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1

(2 or 3) None

23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1

(2 or 3) None

24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠11

(2 or 3) None

25 DAW DAW Wn Wn = decimal adju st Wn 1 1 C

26 DEC DEC f f = f - 1 1 1 C,DC,N,OV,Z

DEC f,WREG WREG = f -1 1 1 C,DC,N,OV,Z

DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z

27 DEC2 DEC2 f f = f - 2 1 1 C,DC,N,OV,Z

DEC2 f,WREG WREG = f -2 1 1 C,DC,N,OV,Z

DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z

28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None

29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C, OV

DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C, OV

DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C, OV

DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C, OV

30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C, OV

31 DO DO #lit14,Expr Do code to PC+Expr, lit14 + 1 times 2 2 None

DO Wn,Expr Do code to PC+Expr, (Wn) + 1 times 2 2 None

32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,

SA,SB,SAB

33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,

SA,SB,SAB

TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

word

# of

cycles Status Flags

Affected

dsPIC30F2010

34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None

35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C

36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C

37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

38 GOTO GOTO Expr Go to address 2 2 None

GOTO Wn Go to indirect 1 2 None

39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z

INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z

INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z

INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z

41 IOR IOR f f = f .IOR. WREG 1 1 N,Z

IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z

IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z

IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z

IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z

42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

43 LNK LNK #lit14 Link frame pointer 1 1 None

44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z

LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z

LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z

LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z

LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z

45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,

AWB Multiply and Accumula te 1 1 OA,OB,OAB,

SA,SB,SAB

MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,

SA,SB,SAB

46 MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 N,Z

MOV f,WREG Move f to WREG 1 1 N,Z

MOV #lit16,Wn Move 16-bit litera l to Wn 1 1 None

MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None

MOV Wn,f Move Wn to f 1 1 None

MOV Wso,Wdo Move Ws to Wd 1 1 None

MOV WREG,f Move WREG to f 1 1 N,Z

MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None

MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None

47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None

48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None

50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,

AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None

MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) *

unsigned(Ws) 1 1 None

MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

signed(Ws) 1 1 None

MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws) 1 1 None

MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) *

unsigned(lit5) 1 1 None

MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5) 1 1 None

MUL f W3:W2 = f * WREG 1 1 None

TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

word

# of

cycles Status Flags

Affected

dsPIC30F2010

52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

NEG f f = f + 1 1 1 C,DC,N,OV,Z

NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

53 NOP NOP No Operation 1 1 None

NOPR No Operation 1 1 None

54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None

POP Wdo Pop from Top-of-S tack (TOS) to Wdo 1 1 None

POP.D Wnd Pop from Top-of-S tack (TOS) to W(nd):W(nd

+ 1) 1 2 None

POP.S Pop Shadow Registers 1 1 All

55 PUSH PUSH f Push f to Top-of-St ack (TOS) 1 1 None

PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None

PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-S tack (TOS) 1 2 None

PUSH.S Push Shadow Registers 1 1 None

56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep

57 RCALL RCALL Expr Relative Call 1 2 None

RCALL Wn Computed Call 1 2 None

58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None

REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None

59 RESET RESET Software device Reset 1 1 None

60 RETFIE RETFIE Return from interrupt 1 3 (2) None

61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None

62 RETURN RETURN Return from Subroutine 1 3 (2) None

63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z

RLC f,WREG WREG = Rotate Left through Carry f 1 1 C ,N,Z

RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z

64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z

RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z

RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z

65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z

RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z

RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z

66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z

RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z

67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None

SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None

68 SE SE Ws,Wnd Wnd = sign extended Ws 1 1 C,N,Z

69 SETM SETM f f = 0xFFFF 1 1 None

SETM WREG WREG = 0xFFFF 1 1 None

SETM Ws Ws = 0xFFFF 1 1 None

70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,

SA,SB,SAB

SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,

SA,SB,SAB

71 SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z

SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z

SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z

SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z

TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

word

# of

cycles Status Flags

Affected

dsPIC30F2010

72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,

SA,SB,SAB

SUB f f = f - WREG 1 1 C,DC,N,OV,Z

SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z

SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z

SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z

SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z

73 SUBB SUBB f f = f - WREG - (C) 1 1 C,DC,N,OV,Z

SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z

SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z

SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z

SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z

74 SUBR SUBR f f = WREG - f 1 1 C,DC,N,OV,Z

SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z

SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z

SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z

75 SUBBR SUBBR f f = WREG - f - (C) 1 1 C,DC,N,OV,Z

SUBBR f,WREG WREG = WREG - f - (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z

76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None

SWAP Wn Wn = byte swap Wn 1 1 None

77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None

79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None

80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None

81 ULNK ULNK Unlink frame pointer 1 1 None

82 XOR XOR f f = f .XOR. WREG 1 1 N,Z

XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z

XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z

XOR Wb,#lit5,Wd Wd = W b .XOR. lit5 1 1 N,Z

83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N

TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

word

# of

cycles Status Flags

Affected

dsPIC30F2010

21.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

21.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separatel y)

- In-C ircuit D ebugger (so ld separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (eithe r assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

dsPIC30F2010

21.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

21.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

21.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, de letion and extraction

21.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linke d with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

21.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and inte rnal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

dsPIC30F2010

21.7 MPLAB ICE 2000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC micro-

controllers. Software control of the MPLAB ICE 2000

In-Circuit Emulator is advanced by the MPLAB Inte-

grated Development Environment, which allows edit-

ing, building, downloading and source debugging from

a sin gle environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

21.8 MPLAB ICE 4000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 4000 In-Circuit Emu lator is intende d to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PIC MCUs and dsPIC DSCs. Software control of the

MPLAB ICE 4000 In-Circuit Emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environm ent.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

21.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

21.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is incl uded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions and

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

dsPIC30F2010

21.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

21.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer with an easy-to-use interface for pro-

gramming many of Microchip’s baseline, mid-range

and PIC1 8F families of Fl ash memory mic rocontrollers.

The PICkit 2 S tar ter Kit includes a pr ototypin g develop-

ment board, twelve sequential lessons, software and

HI-TECH’s PICC™ Lite C compiler, and is designed to

help get up to speed quickly using PIC® micro-

controllers. The kit provides everything needed to

program, evaluate and develop applications using

Microchip’s powerful, mid-range Flash memory family

of microcontroll ers.

21.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards includ e prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart® battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

dsPIC30F2010

22.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of dsPIC30F electrical character istics. Additional information will be provided in future

revisions of this document as it becomes available.

For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual”

(DS70046).

Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for

extende d peri ods may aff ec t devi ce re liabil ity. Functional o perat ion o f the devi ce at th ese o r any other co nditio ns ab ove

the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................-0.3V to (VDD + 0.3V)

Vo lt a ge on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V

Vo lt a ge on MCLR with respect to VSS (Note 1)......................................................................................... 0V to +13.25V

Total power dissipation (Note 2) ...............................................................................................................................1.0W

Maximum curr ent o ut of VSS pin ...........................................................................................................................300 mA

Maximum curr ent i nto VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin....................................................................................................25 mA

Maximum current sunk by all ports.......................................................................................................................200 mA

Maximum current sourced by all ports..................................................................................................................200 mA

Note 1: Voltage s pi kes be low V SS a t the M CLR /VPP p in, inducing curre nt s gre ate r than 80 m A, m ay c au se l atc hu p.

Thus, a se ries resisto r of 50-100Ω should be u sed w he n a ppl yi ng a “low” level to the MC L R/VPP pin, rath er

than pulling this pin directly to VSS.

2: Maximum allowable current is a function of device maximum power dissipation. See Table 22-4.

22.1 DC Characteristics

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stres s rating onl y and funct ional ope ration of the device at tho se or any other co nditio ns above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

TABLE 22-1: OPERATING MIPS VS. VOLTAGE

VDD Range Temp Range Max MIPS

dsPIC30F2010-30I dsPIC30F2010-20E

4.5-5.5V -40°C to 85°C 30 —

4.5-5.5V -40°C to 125°C — 20

3.0-3.6V -40°C to 85°C 20 —

3.0-3.6V -40°C to 125°C — 15

2.5-3.0V -40°C to 85°C 10 —

dsPIC30F2010

TABLE 22-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit

dsPIC30F2010-30I

Operating Junction Temperature Range TJ-40 +125 °C

Operating Ambient Temperature Range TA-40 +85 °C

dsPIC30F2010-20E

Operati ng Junction Temperat ure Range TJ-40 +150 °C

Operating Ambient Temperature Range TA-40 +125 °C

Power Dissipation:

Internal ch ip pow er dis sip ation:

PDPINT + PI/OW

I/O Pin power dissipation:

Maximum Allowed Power Dissipation PDMAX (TJ - TA) / θJA W

TABLE 22-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes

Package Thermal Resistance, 28-pin SOIC (SO) θJA 48.3 °C/W 1

Package Thermal Resistance, 28-pin QFN θJA 33.7 °C/W 1

Package Thermal Resistance, 28-pin SPDIP (SP) θJA 42 °C/W 1

Note 1: Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.

TABLE 22-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Operating Voltage(2)

DC10 VDD Supply Voltage 2.5 — 5.5 V Indu stri al tem pera ture

DC11 VDD Supply Volt age 3.0 — 5.5 V Extended tempe ratu r e

DC12 VDR RAM Data Retention Voltage(3) —1.5—V

DC16 VPOR VDD Start Voltage

to ensure internal

Power-on Rese t signal

—VSS —V

DC17 SVDD VDD Rise Rate

to ensure internal

Power-on Rese t signal

0.05 V/ms 0-5V in 0.1 sec

0-3V in 60 ms

Note 1: Dat a in “Typ” column is a t 5V, 25°C unless o therw ise st ate d. Parame ters are for desi gn gui dance only an d

are not t ested.

2: These parameters are characterized but not tested in manufacturing.

3: This is the limit to which VDD can be lowered without losing RAM data.

INT VDD IDD IOH

∑

–()×=

–

{}

×()

∑VOL IO

(

∑

dsPIC30F2010

TABLE 22-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical Max Units Conditions

Operating Current (IDD)(1)

DC31a 1.6 3 mA 25°C 3.3V 0.128 MIPS

LPRC (512 kHz)

DC31b 1.6 3 mA 85°C

DC31c 1.6 3 mA 125°C

DC31e 3.9 7 mA 25°C 5VDC31f 3.5 7 mA 85°C

DC31g 3.4 7 mA 125°C

DC30a 3 5 mA 25°C 3.3V (1.8 MIPS)

FRC (7.37MHz)

DC30b 3 5 mA 85°C

DC30c 3 5 mA 125°C

DC30e 6 9 mA 25°C 5VDC30f 6 9 mA 85°C

DC30g 6 9 mA 125°C

DC23a 9 14 mA 25°C 3.3V

4 MIPS EC mode, 4X PLL

DC23b 10 15 mA 85°C

DC23c 10 15 mA 125°C

DC23e 16 24 mA 25°C 5VDC23f 16 24 mA 85°C

DC23g 16 24 mA 125°C

DC24a 21 32 mA 25°C 3.3V

10 MIPS EC mode, 4X PLL

DC24b 21 32 mA 85°C

DC24c 21 32 mA 125°C

DC24e 35 53 mA 25°C 5VDC24f 36 53 mA 85°C

DC24g 36 53 mA 125°C

DC27a 39 59 mA 25°C 3.3V

20 MIPS EC mode, 8X PLL

DC27b 39 59 mA 85°C

DC27d 66 99 mA 25°C 5VDC27e 66 99 mA 85°C

DC27f 66 99 mA 125°C

DC29a 95 150 mA 25°C 5V 30 MIPS EC mode, 16X PLL

DC29b 94 150 mA 85°C

Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an imp act on the current c onsumpti on. The tes t condi tions fo r all IDD measur ement s are as follow s: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.

MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data

Memory are oper ational . N o peripheral modules are operat ing.

dsPIC30F2010

TABLE 22-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5. 5V

(unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical Max Units Conditions

Operating Current (IDD)(1)

DC51a 1.5 3.0 mA 25°C 3.3V

0.128 MIPS

LPRC (512 kHz)

DC51b 1.5 3.0 mA 85°C

DC51c 1.5 3.0 mA 125°C

DC51e 4.1 7 mA 25°C 5VDC51f 3.6 7 mA 85°C

DC51g 3.5 7 mA 125°C

DC50a 3 5 mA 25°C 3.3V

(1.8 MIPS)

FRC (7.37MHz)

DC50b 3 5 mA 85°C

DC50c 3 5 mA 125°C

DC50e 7 9 mA 25°C 5VDC50f 6 9 mA 85°C

DC50g 6 9 mA 125°C

DC43a 5 9 mA 25°C 3.3V

4 MIPS EC mode, 4X PLL

DC43b 6 9 mA 85°C

DC43c 6 9 mA 125°C

DC43e 10 15 mA 25°C 5VDC43f 10 15 mA 85°C

DC43g 10 15 mA 125°C

DC44a 11 18 mA 25°C 3.3V

10 MIPS EC mode, 4X PLL

DC44b 12 18 mA 85°C

DC44c 12 18 mA 125°C

DC44e 20 30 mA 25°C 5VDC44f 20 30 mA 85°C

DC44g 20 30 mA 125°C

DC47a 20 30 mA 25°C 3.3V

20 MIPS EC mode, 8X PLL

DC47b 21 30 mA 85°C

DC47d 35 45 mA 25°C 5VDC47e 35 45 mA 85°C

DC47f 35 45 mA 125°C

DC49a 49 65 mA 25°C 5V 30 MIPS EC mode, 16X PLL

DC49b 50 65 mA 85°C

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with core off, clock on and all modules turned off.

dsPIC30F2010

TABLE 22-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical Max Units Conditions

Power Down Current (IPD)(1)

DC60a 0.05 — μA 25°C 3.3V

Base Power Down Current(2)

DC60b 3 25 μA 85°C

DC60c 20 50 μA 125°C

DC60e 0.1 — μA 25°C 5VDC60f 6 35 μA 85°C

DC60g 40 70 μA 125°C

DC61a 30 45 μA 25°C 3.3V

Watchdog Timer Current: ΔIWDT(2)

DC61b 34 51 μA 85°C

DC61c 46 69 μA 125°C

DC61e 35 53 μA 25°C 5VDC61f 39 59 μA 85°C

DC61g 40 60 μA 125°C

DC62a 4 10 μA 25°C 3.3V

T imer 1 w/32 kHz Crystal: ΔITI32(2)

DC62b 5 10 μA 85°C

DC62c 4 10 μA 125°C

DC62e 4 15 μA 25°C 5VDC62f 6 15 μA 85°C

DC62g 5 15 μA 125°C

DC63a 4 6 μA 25°C 3.3V

BOR On: ΔIBOR(2)

DC63b 4 6 μA 85°C

DC63c 5 7.5 μA 125°C

DC63e 10 15 μA 25°C 5VDC63f 9 15 μA 85°C

DC63g 10 15 μA 125°C

Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. LVD, BOR, WDT, etc. are all switch ed off.

2: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

dsPIC30F2010

TABLE 22-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VIL Input Low Voltage(2)

DI10 I/O pi ns:

with Schmitt Trigger buffer VSS —0.2VDD V

DI15 MCLR VSS —0.2VDD V

DI16 OSC1 (in XT, HS and LP modes) VSS —0.2VDD V

DI17 OSC1 (in RC mode)(3) VSS —0.3VDD V

DI18 SDA, SCL VSS —0.3VDD V SM bus disa ble d

DI19 SDA, SCL VSS —0.2VDD V SM bus enabled

VIH Input High Voltage(2)

DI20 I/O pi ns:

with Schmitt Trigger buffer 0.8 VDD —VDD V

DI25 MCLR 0.8 VDD —VDD V

DI26 OSC1 (in XT, HS and LP modes) 0.7 V DD —VDD V

DI27 OSC1 (in RC mode)(3) 0.9 VDD —VDD V

DI28 SDA, SCL 0.7 VDD —VDD V SM bus disa bled

DI29 SDA, SCL 0.8 VDD —VDD V SM bus enab led

ICNPU CNXX Pull-up Current(2)

DI30 50 250 400 μAVDD = 5V, VPIN = VSS

IIL Input Leakage Current(2)(4)(5)

DI50 I/O po rts — 0.01 ±1 μAVSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI51 Analog input pins — 0.50 ±1.3 μAV

SS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI55 MCLR —0.05±5μAVSS ≤ VPIN ≤ VDD

DI56 OSC1 — 0.05 ±7 μAVSS ≤ VPIN ≤ VDD, XT, HS

and LP Osc mode

Note 1: Dat a in “Typ” column is a t 5V, 25°C unless o therw ise st ate d. Parame ters are for desi gn gui dance only an d

are not t ested.

2: These parameters are characterized but not tested in manufacturing.

3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that

the dsPIC30F device be driven with an external clock while in RC mode.

4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

5: Negative current is defined as current sourced by the pin.

dsPIC30F2010

FIGURE 22-1: BROWN-OUT RESET CH ARACTE RISTICS

TABLE 22-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VOL Output Low Voltage(2)

DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V

——TBDVI

OL = 2.0 mA, VDD = 3V

DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V

(RC or EC Osc mode) — — TBD V IOL = 2.0 mA, VDD = 3V

VOH Output High Voltage(2)

DO20 I/O ports VDD – 0 .7 — — V IOH = -3.0 mA, VDD = 5V

TBD — — V IOH = -2.0 mA, VDD = 3V

DO26 OSC2/CLKO VDD – 0. 7 — — V IOH = -1.3 mA, VDD = 5V

(RC or EC Osc mode) TBD — — V IOH = -2.0 mA, VDD = 3V

Capacitive Loading Specs

on Output Pins(2)

DO50 COSC2 OSC2/SO SC2 pin — — 15 pF In XTL, XT, HS and LP modes

when e xternal cloc k is used to

drive OSC1.

DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode

DO58 CBSCL, SDA — — 400 pF In I2C mode

Note 1: Data i n “Typ” col um n i s at 5V, 25°C unles s otherwise st ate d. Parameters ar e for design gu ida nc e on ly and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

BO10

Reset (due to BOR)

VDD

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

Power Up T ime-out

BO15

dsPIC30F2010

TABLE 22-10: ELECTRICAL CHARACTERISTICS: BOR

TABLE 22-11: DC CHARACTERISTICS: PROGRAM AND EEPROM

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

BO10 VBOR BOR Voltage(2) on

VDD transition high to

low

BORV = 11(3) — — — V Not in operating

range

BORV = 10 2.6 — 2.71 V

BORV = 01 4.1 — 4.4 V

BORV = 00 4.58 — 4.73 V

BO15 VBHYS —5—mV

Note 1: Data i n “Typ” col umn i s at 5V, 25°C unles s o the rw is e s t ate d. Pa ram ete rs ar e for design gu ida nc e on ly and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: 11 values not in usa bl e operating range.

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Data EEPROM Memory (2)

D120 EDByte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C

D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write Cycle Time — 2 — ms

D123 TRETD Characteris tic Retention 40 1 00 — Year Provid ed no other specifications

are violated

D124 IDEW IDD During Programming — 10 30 mA Row Erase

Program Flash Memory(2)

D130 EPCell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VEB VDD for Bulk Erase 4.5 — 5 .5 V

D133 VPEW VDD for Erase/Write 3.0 — 5.5 V

D134 TPEW Erase/Write Cycle Time — 2 — ms

D135 TRETD Characteris tic Retention 40 1 00 — Year Provid ed no other specifications

are violated

D136 TEB ICSP Block Erase Time — 4 — ms

D137 IPEW IDD During Programming — 10 30 mA Row Erase

D138 IEB IDD During Programming — 10 30 mA Bulk Erase

Note 1: D ata in “Typ” column is at 5V, 25°C unless otherwise stated.

2: These parameters are characterized but not tested in manufacturing.

dsPIC30F2010

22.2 AC Characteristi cs and Timing Parameters

The information contained in this section defines dsPIC30F AC characteristics and timing parameters.

TABLE 22-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGU RE 22-2 : LOAD CO ND IT I ONS FOR D E VI CE T I MIN G SP E CI FI CA T IO N S

FIGU RE 22-3: EXTER NA L C LOC K TIMIN G

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Operati ng voltage VDD range as described in Section 22.1 “DC Charac-

teristics”.

VDD/2

VSS

RL= 464 Ω

CL= 50 pF for all pins except OSC2

5 pF for OSC2 output

Load Condition 1 - for all pins except OSC 2 Load Condition 2 - for OSC2

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

OS20

OS25

OS30 OS30

OS40 OS41

OS31 OS31

dsPIC30F2010

TABLE 22-13: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5. 5V

(unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

OS10 FOSC External CLKI Frequency(2)

(External clocks allowed only

in EC mode)

—

7.5

MHz

EC with 4x PLL

EC with 8x PLL

EC with 16x PLL

Osci lla tor Freq uen cy(2) DC

0.4

—

7.37

512

7.5

—

MHz

kHz

MHz

kHz

XTL

XT with 4x PLL

XT with 8x PLL

XT with 16x PLL

FRC internal

LPRC internal

OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10

for FOSC value

OS25 TCY Instruction Cycle Time(2)(3) 33 — DC ns See Table 22-16

OS30 TosL,

TosH External Clock(2) in (OSC1 )

High or Low Time .45 x TOSC ——nsEC

OS31 TosR,

TosF External Clock(2) in (OSC1 )

Rise or Fall Time — — 20 ns EC

OS40 TckR CLKO Rise Time(2)(4) — 6 10 ns

OS41 TckF CLKO Fall Time(2)(4) — 6 10 ns

Note 1: Dat a in “Typ” column is at 5V, 25°C unless othe rw ise st at ed. Parameters are for desi gn gu ida nc e onl y and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: Instruct ion cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on charac teri za tion data for that part ic ular oscillator typ e unde r st andard operating con di tion s

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “Min”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“Max” cycle time limit is “DC” (no clock) for all devices.

4: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is

low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

dsPIC30F2010

TABLE 22-15: PLL JITTER

TABLE 22-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)

AC CHARACTERISTICS

Standard Operating Cond itions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OS50 FPLLI PLL Input Frequency Range(2) 4

—

7.5(3)

MHz

EC with 4x PLL

EC with 8x PLL

EC with 16x PLL

XT with 4x PLL

XT with 8x PLL

XT with 16x PLL

OS51 FSYS On-Chip PLL Output(2) 16 — 120 MHz EC, XT modes with PLL

OS52 TLOC PLL Start-up Time (Lock Time) — 20 50 μs

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” colum n i s at 5V, 25°C unles s o the rwis e s t ated. Paramete rs ar e for design gu ida nc e on ly and

are not tested.

3: Limited by device operating frequency range.

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ(1) Max Units Conditions

OS61 x4 PLL — 0.251 0.413 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V

— 0.251 0.413 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V

— 0.256 0.47 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V

— 0.256 0.47 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V

x8 PLL — 0.355 0.584 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V

— 0.355 0.584 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V

— 0.362 0.664 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V

— 0.362 0.664 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V

x16 PLL — 0.67 0.92 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V

— 0.632 0.956 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V

— 0.632 0.956 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V

Note 1: These parameters are characterized but not tested in manufacturing.

dsPIC30F2010

TABLE 22-16: INTERNAL CLOCK TIMING EXAMPLES

TABLE 22-17: AC CHARACTERISTICS: INTERNAL RC ACCURACY

TABLE 22-18: INTERNAL RC ACCURACY

Clock

Oscillator

Mode

FOSC

(MHz)(1) TCY (μsec)(2) MIPS(3)

w/o PLL MIPS(3)

w PLL x4 MIPS(3)

w PLL x8 MIPS(3)

w PLL x16

EC 0.200 20.0 0.05 — — —

4 1.0 1.0 4.0 8.0 16.0

10 0.4 2.5 10.0 20.0 —

25 0.16 6.25 — — —

XT 4 1.0 1.0 4.0 8.0 16.0

10 0.4 2.5 10.0 20.0 —

Note 1: Assumption: Oscillator Postscaler is divide by 1.

2: Instruction Execution Cycle Time: TCY = 1 / MIPS.

3: Instruction Execution Frequency: MIPS = (FOSC * PLLx) / 4 (since there are 4 Q clocks per instruction

cycle).

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Jitter @ FRC Freq. = 7.37 MHz(1)

OS62 FRC — +0.04 +0.16 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

—+0.07 +0.23 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1)

OS63 FRC — — +1.50 % -40°C ≤ TA ≤ +125°C VDD = 3.0-5.5V

Internal FRC Drift @ FRC Freq. = 7.37 MHz(1)

OS64 -0.7 — 0.5 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

-0.7 — 0.7 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V

-0.7 — 0.5 % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V

-0.7 — 0.7 % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V

Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN <3:0> bits can be used to compensate for

temperature drift.

2: Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift

percentages.

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

LPRC @ Freq. = 512 kHz(1)

OS65 -35 — +35 % —

Note 1: Change of LPRC frequency as VDD changes.

dsPIC30F2010

FIGURE 22-4: CLKO AND I/O TIMING CHARACTERISTICS

TABLE 22-19: CLKO AND I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1)(2)(3) Min Typ(4) Max Units Conditions

DO31 TIOR Port output rise time — 7 20 ns —

DO32 TIOF Port output fall time — 7 20 ns —

DI35 TINP INTx pin h igh or low time (output) 20 — — ns —

DI40 TRBP CNx high or low time (input) 2 TCY ——— —

Note 1: These parameters are asynchronous events not related to any internal clock edges

2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.

3: These parameters are characterized but not tested in manufacturing.

4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

Note: Refer to Figur e 22-2 for load conditions.

I/O Pin

(Input)

I/O Pin

(Output)

DI35

Old Value New Value

DI40

DO31

DO32

dsPIC30F2010

FIGURE 22-5: RESET, WATCHDOG T IMER, OSCILLATOR S TART-UP T I MER A ND POWER-UP

TIMER TIMING CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

SY11

SY10

SY20

SY13

I/O Pins

SY13

Note: Refer to Figure 22-2 for load conditions.

FSCM

Delay

SY35

SY30

SY12

dsPIC30F2010

TABLE 22-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY10 TmcL MCLR Puls e Width (low) 2 — — μs -40°C to +85°C

SY11 TPWRT Power-up Timer Period 3

ms -40°C t o +85° C

User programmable

SY12 TPOR Power On Reset Delay 3 10 30 μs -40°C to +85°C

SY13 TIOZ I/O high-impedance from MCLR

Low or Watchdog Timer Reset —0.81.0μs

SY20 TWDT1 Watchdog Timer Time-out Period

(No Prescaler) 1.4 2.1 2.8 ms 3.3V, -40°C to +125°C

TWDT2 1.4 2.1 2.8 ms 5.0V, -40°C to +125°C

SY25 TBOR Brown-out Reset Puls e Width(3) 100 — — μsVDD ≤ VBOR (D034)

SY30 TOST Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period

SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

3: Refer to Figure 22-1 and Table 22-10 for BOR.

dsPIC30F2010

FIGURE 22-6: BAND GAP ST ART-UP TIME CHARACTERISTICS

TABLE 22-21: BAND GAP START-UP TIME REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5. 5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY40 TBGAP Band Gap Start-up Time — 40 65 µs Defined as the time between the

instant that the band gap is enabled

and the moment that the band gap

reference voltage is stabl e.

RCON<13>Status bit

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

VBGAP

Enable Band Gap

Band Gap

(see Note)

Stable

Note: Band Gap is enabled when FBORPOR<7> is set.

SY40

dsPIC30F2010

FIGU RE 22-7: TIM ER EX TER NAL CL OCK T IM ING CHARA CTER ISTI CS

TABLE 22-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operati ng Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operati ng tem pe rature -40 °C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TA10 TTXH TxCK High Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with presca ler 10 — — ns

Asynchronous 10 — — ns

TA11 TTXL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with presca ler 10 — — ns

Asynchronous 10 — — ns

TA15 TTXP TxCK I nput Period Synchronous ,

no prescaler TCY + 10 — — ns

Synchronous,

with presca ler Greater of:

20 ns or

(TCY + 40)/N

— — — N = prescale

value

(1, 8, 64, 256)

Asynchronous 20 — — ns

OS60 Ft1 SOSC1 /T1CK oscillator input

frequency range (oscillator enabled

by setting bit TCS (T1CON, bit 1))

DC — 50 kHz

TA20 TCKEXTMRL Delay from External TxCK Clock

Edge to Ti mer Increment 0.5 TCY 1.5 TCY —

Tx11

Tx15

Tx10

Tx20

TMRX OS60

TxCK

Note: “x” refers to Timer Type A or Timer Type B.

Refer to Figure 22-2 for load conditions.

dsPIC30F2010

TABLE 22-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS

TABLE 22-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operati ng tem pe rature -40 °C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TB10 TtxH TxCK High Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TB15

Synchronous,

with prescale r 10 — — ns

TB11 TtxL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TB15

Synchronous,

with prescale r 10 — — ns

TB15 TtxP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescale r Greater of:

20 ns or

(TCY + 40)/N

TB20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY 1.5 TCY —

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC15 TtxP TxCK Inpu t Period Synchronous,

no prescaler TCY + 10 — — ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40)/N

TC20 TCKEXTMRL Delay from External TxCK Clock

Edge to Ti mer Increment 0.5 TCY 1.5 TCY —

dsPIC30F2010

FIGURE 22-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS

TABLE 22-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENT S

AC CHARACTERISTICS

Standard Operating Cond itions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ Max Units Conditions

TQ10 TtQH TQCK High Time Synchronous,

with presca ler TCY + 20 — ns Must also meet

parameter TQ15

TQ11 TtQL TQCK Low Time Synchronous,

with presca ler TCY + 20 — ns Must also meet

parameter TQ15

TQ15 TtQP TQCP Input Period Synchronous,

with presca ler 2 * TCY + 40 — ns —

TQ20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY 1.5 TCY ns —

Note 1: These parameters are characterized but not tested in manufacturing.

TQ11

TQ15

TQ10

TQ20

QEB

POSCNT

dsPIC30F2010

FIGU RE 22-9: INPUT CAPTU RE (CA Px) TI MING CHAR ACTE RIST ICS

TABLE 22-26: INPUT CAPTURE TIMING REQUIREMENTS

FIGURE 22-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

TABLE 22-27: OUTPUT COMPARE MODULE TIMING REQUIREMENT S

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Max Units Conditions

IC10 TccL ICx Input Low Ti me No Prescaler 0.5 TCY + 20 — ns

With Prescaler 10 — ns

IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 2 0 — ns

With Prescaler 10 — ns

IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale

va lue (1, 4, 16)

Note 1: These parameters are characterized but not tested in manufacturing.

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC10 TccF OCx Output Fall Time — — — ns See parameter D032

OC11 TccR OCx Output Rise Time — — — ns See parameter D031

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless ot herwi se st ated. Parameters are fo r des ign guid ance only and

are not tested.

ICX

IC10 IC11

IC15

Note: Refer to Figure 22-2 for load conditions.

OCx

OC11 OC10

(Output Compare

Note: Refer to Figure 22-2 for load conditions.

or PWM Mode)

dsPIC30F2010

FIGURE 22-11: OC/PWM MODULE TIMING CHARACTERISTICS

TABLE 22-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC15 TFD Fault Input to PWM I/O

Change ——50ns —

OC20 TFLT Fault Input Pulse Width 50 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” colum n i s at 5V, 25°C unles s o the rwis e s t ated. Paramete rs ar e for design gu ida nc e on ly and

are not tested.

OCFA/OCFB

OCx

OC20

OC15

dsPIC30F2010

FIGURE 22-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS

FIGURE 22-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS

TABLE 22-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

MP10 TFPWM PWM Output Fall Time — — — ns See pa ram e ter D032

MP11 TRPWM PWM Output Rise Time — — — ns See parameter D031

MP20 TFD Fault Input ↓ to PWM

I/O Change — — 50 ns —

MP30 TFH M inimum Pulse Width 50 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” colum n i s at 5V, 25°C unles s otherwise st ate d. Pa ram ete rs are for design guidanc e on ly and

are not tested.

FLTA/B

PWMx

MP30

MP20

PWMx

MP11 MP10

Note: Refer to Figure 22-2 for load cond iti ons .

dsPIC30F2010

FIGURE 22-14: QEA/QEB INPUT CHARACTERISTICS

TABLE 22-30: QUADRATURE DECODER TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise sta ted)

Operating temperature -40°C ≤ TA ≤ +85°C for Industri al

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Typ(2) Max Units Conditions

TQ30 TQUL Quadrature Input Low Time 6 TCY —ns —

TQ31 TQUH Quadrature Input High Time 6 TCY —ns —

TQ35 TQUIN Quadrature Input Period 12 TCY —ns —

TQ36 TQUP Quadrature Phase Period 3 TCY —ns —

TQ40 TQUFL Filter Time to Recognize Low,

with Digital Filter 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

TQ41 TQUFH Filter Time to Recognize High,

with Digital Filter 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

Note 1: These parameters are characterized but not tested in manufacturing.

2: N = Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder

Interface (QEI)” in the “dsPIC30F Family Reference Manual” (DS70046).

TQ30

TQ35

TQ31

QEA

(input)

TQ30

TQ35

TQ31

QEB

(input)

TQ36

QEB

Internal

TQ40TQ41

dsPIC30F2010

FIGU RE 22 - 15: QEI MOD UL E IN DEX PULS E TIMI NG CH AR AC T ERI ST IC S

TABLE 22-31: QEI INDEX PULSE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Max Units Conditions

TQ50 TqIL Filter Time to Recognize Low,

with Digital Filter 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

TQ51 TqiH Filter Time to Recognize High,

with Digital Filter 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

TQ55 Tqidxr Index Pulse Recognized to Position

Counter Reset (Ungated Index) 3 TCY —ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Alignment of Index Pulses to QEA and QEB is shown for Position Counter reset timing only. Shown for

forward direction only (QEA leads QEB). Same timing a ppl ie s for reverse dire ction (QEA lags QEB) but

Index Pulse recognition occurs on falling edge.

QEA

(input)

Ungated

Index

QEB

(input)

TQ55

Index Internal

Position

TQ50

TQ51

dsPIC30F2010

FIGURE 22-16: SPI MODULE MA STER MOD E (CKE = 0) TIMING CHARACTERISTICS

TABLE 22-32: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKX Output Low Time(3) TCY / 2 — — ns —

SP11 TscH SCKX Output High Time(3) TCY / 2 — — ns —

SP20 TscF SCKX Output Fall Time(4 — — — ns See parameter

D032

SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter

D031

SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter

D032

SP31 TdoR SDOX Data Output Rise Time(4) — — — ns See parameter

D031

SP35 TscH2doV,

TscL2doV SDOX Data Output Valid after

SCKX Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” colum n i s at 5V, 25°C unles s o the rwis e s t ated. Paramete rs ar e for design gu ida nc e on ly and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specificat ion.

4: Assumes 50 pF load on all SPI pins.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP11 SP10

SP40 SP41

SP21

SP20

SP35

SP20

SP21

MSb LSb

BIT14 - - - - - -1

MSb IN LSb IN

BIT14 - - - -1

SP30

SP31

Note: Refer to Figur e 22-2 for load conditio ns.

dsPIC30F2010

FIGURE 22-17: SPI MODULE MA STER MOD E (C KE = 1) TIMING CHARACTERISTICS

TABLE 22-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industri al

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKX output low time(3) TCY / 2 — — ns —

SP11 TscH SCKX output high time(3) TCY / 2 — — ns —

SP20 TscF SCKX output fall time(4) — — — ns See parameter

D032

SP21 TscR SCKX output rise time(4) — — — ns See parameter

D031

SP30 TdoF SDOX data output fall time(4) — — — ns See parameter

D032

SP31 TdoR SDOX data output rise time(4) — — — ns See parameter

D031

SP35 TscH2doV,

TscL2doV SDOX data output valid after

SCKX edge — — 30 ns —

SP36 TdoV2sc,

TdoV2scL SDOX data output setup to

first SCKX edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup time of SDIX data input

to SCKX edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold time of SDIX data input

to SCKX edge 20 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Dat a in “Typ” column is at 5V, 25°C unles s othe rwise st ate d. Par ameters are for desi gn gui dance only an d

are not t ested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SDIX

SP36

SP30,SP31

SP35

MSb

MSb IN

BIT14 - - - - - -1

LSb IN

BIT14 - - - -1

LSb

Note: Refer to Figure 22-2 for load conditions.

SP11 SP10 SP20

SP21

SP20

SP40

SP41

dsPIC30F2010

FIGU RE 22-18: SPI MO DULE SLAV E MO D E ( C KE = 0) TIMING CHARACTERISTICS

TABLE 22-34: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREM ENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKX Input Low Time 30 — — ns —

SP71 TscH SCKX Input High Time 30 — — ns —

SP72 TscF SCKX Input Fall Time(3) —1025ns —

SP73 TscR SCKX Input Rise Ti me(3) —1025ns —

SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See pa rameter

D032

SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See pa rameter

D031

SP35 TscH2doV,

TscL2doV SDOX Data Output Valid after

SCKX Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP50 TssL2scH,

TssL2scL SSX↓ to SCKX↑ or SCKX↓ Input 120 — — ns —

SP51 TssH2doZ SSX↑ to SDOX Output

High-Impedance(3) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSX after SCK Edge 1.5 TCY +40 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” colum n i s at 5V, 25°C unles s o the rwis e s t ated. Paramete rs ar e for design gu ida nc e on ly and

are not tested.

3: Assumes 50 pF load on all SPI pins.

SCK

(CKP =

)

SCK

(CKP =

)

SDO

SDI

SP50

SP40 SP41

SP30,SP31 SP51

SP35

SDI

MSb LSb

BIT14 - - - - - -1

MSb IN BIT14 - - - -1 LSb IN

SP52

SP73

SP72

SP73

SP71 SP70

Note: Refer to Figure 22-2 for load conditions.

dsPIC30F2010

FIGU RE 22-19: SPI MO DULE SLAV E MO D E ( C KE = 1) TIMING CHARACTERISTICS

SSX

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SDI

SP50

SP60

SDIX

SP30,SP31

MSb BIT14 - - - - - -1 LSb

SP51

MSb IN BIT14 - - - -1 LSb IN

SP35

SP52

SP73

SP72

SP73

SP71 SP70

SP40 SP41

Note: Refer to Figure 22- 2 for l oad conditions.

dsPIC30F2010

TABLE 22-35: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKX Input Low Time 30 — — ns —

SP71 TscH SCKX Input High Time 30 — — ns —

SP72 TscF SCKX Input Fall Time(3) —1025ns —

SP73 TscR SCKX Input Rise T ime(3) —1025ns —

SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parame ter

D032

SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parame ter

D031

SP35 TscH2doV,

TscL2doV SDOX Data Output Va li d after

SCKX Edge ——30ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP50 TssL2scH,

TssL2scL SSX↓ to SCKX↓ or SCKX↑ input 120 — — ns —

SP51 TssH2doZ SS↑ to SDOX Output

High-Impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSX↑ after SCKX Edge 1.5 TCY + 40 — — ns —

SP60 TssL2doV SDOX Data O utput Valid after

SSX Edge ——50ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” colum n i s at 5V, 25°C unles s o the rwis e s t ated. Paramete rs ar e for design gu ida nc e on ly and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specificat ion.

4: Assumes 50 pF load on all SPI pins.

dsPIC30F2010

FIGURE 22-20: I2C™ BUS ST ART/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 22-21: I2C™ BUS DATA TIMI NG CH AR AC TE RI ST IC S ( M AST ER M OD E)

IM31 IM34

SCL

SDA

Start

Condition Stop

Condition

IM30 IM33

Note: Refer to Figure 22-2 for load conditions.

IM11 IM10 IM33

IM11 IM10

IM20

IM26 IM25

IM40 IM40 IM45

IM21

SCL

SDA

Out

Note: Refer to Figure 22-2 for load conditions.

dsPIC30F2010

TABLE 22-36: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min(1) Max Units Conditions

IM10 TLO:SCL Clo ck Lo w Time 100 kHz mode TCY / 2 (BRG + 1) — µs —

400 kHz mode TCY / 2 (BRG + 1) — µs —

1 MHz mode(2) TCY / 2 (BRG + 1) — µs —

IM11 THI:SCL Clock High Time 100 kHz mode TCY / 2 (BRG + 1) — µs —

400 kHz mode TCY / 2 (BRG + 1) — µs —

1 MHz mode(2) TCY / 2 (BRG + 1) — µs —

IM20 TF:SCL SDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 100 ns

IM21 TR:SCL SDA and SCL

Rise Time 100 kHz mode — 1000 ns CB is specif ied to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 300 ns

IM25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns —

400 kHz mode 1 00 — ns

1 MHz mode(2) TBD — ns

IM26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns —

400 kHz mode 0 0.9 µs

1 MHz mode(2) TBD — ns

IM30 TSU:STA Start Conditio n

Setup Time 100 kHz mode TCY / 2 (BRG + 1) — µs Only relevant for

repeated Start

condition

400 kHz mode TCY / 2 (BRG + 1) — µs

1 MHz mode(2) TCY / 2 (BRG + 1) — µs

IM31 THD:STA Start Co nd itio n

Hold Time 100 kHz mode TCY / 2 (BRG + 1) — µs After this period the

first clock pulse is

generated

400 kHz mode TCY / 2 (BRG + 1) — µs

1 MHz mode(2) TCY / 2 (BRG + 1) — µs

IM33 TSU:STO Stop Condition

Setup Time 100 kHz mode TCY / 2 (BRG + 1) — µs —

400 kHz mode TCY / 2 (BRG + 1) — µs

1 MHz mode(2) TCY / 2 (BRG + 1) — µs

IM34 THD:STO Stop Conditi on 100 kHz mode TCY / 2 (BRG + 1) — ns —

Hold Time 400 kHz mode TCY / 2 (BRG + 1) — ns

1 MHz mode(2) TCY / 2 (BRG + 1) — ns

IM40 TAA:SCL Output Valid

From Clock 100 kHz mode — 3500 ns —

400 kHz mode — 1000 ns —

1 MHz mode(2) ——ns —

IM45 TBF:SDA Bus Fr ee Time 100 k Hz mod e 4.7 — µs Time the bus must be

free before a new

transmission can start

400 kHz mode 1.3 — µs

1 MHz mode(2) TBD — µs

IM50 CBBus Capacitive Loading — 400 pF

Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit™

(I2C)” in the “dsPIC30F Family Reference M anual” (DS70046).

2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).

dsPIC30F2010

FIGURE 22-22: I2C™ BUS ST ART/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 22-23: I2C™ B US DATA TIMING CH AR AC TE RI ST ICS (S LA V E MODE )

IS31 IS34

SCL

SDA

Start

Condition Stop

Condition

IS30 IS33

IS30 IS31 IS33

IS11

IS10

IS20

IS26 IS25

IS40 IS40 IS45

IS21

SCL

SDA

Out

dsPIC30F2010

TABLE 22-37: I2C™ BUS DATA TI MING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS

Standard Operating Cond itions: 2.5V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Max Units Conditions

IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — μs Device must operate at a

minimum of 10 MHz.

1 MHz mode(1) 0.5 — μs—

IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — μs Device must operate at a

minimum of 10 MHz

1 MHz mode(1) 0.5 — μs—

IS20 TF:SCL SDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 100 ns

IS21 TR:SCL SDA and SCL

Rise Time 100 kHz mode — 1000 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

IS25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode(1) 100 — ns

IS26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns —

400 kHz mode 0 0.9 μs

1 MHz mode(1) 00.3μs

IS30 TSU:STA Start Condition

Setup Time 100 kHz mode 4.7 — μs Only relevant for repeated

Start condition

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS31 THD:STA Start Conditi on

Hold Time 100 kHz mode 4.0 — μs After this period the first

clock pulse is generated

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS33 TSU:STO Stop Condition

Setup Time 100 kHz mode 4.7 — μs—

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.6 — μs

IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns —

Hold Time 400 kHz mode 600 — ns

1 MHz mode(1) 250 ns

IS40 TAA:SCL Output V alid From

Clock 100 kHz mode 0 3500 ns —

400 kHz mode 0 1000 ns

1 MHz mode(1) 0 350 ns

IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — μs

1 MHz mode(1) 0.5 — μs

IS50 CBBus Capacitive

Loading — 400pF —

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

dsPIC30F2010

TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 2.7V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Device Supply

AD01 AVDD Modu le VDD Supply Greate r of

VDD - 0.3

or 2.7

Lesser of

VDD + 0.3

or 5.5

V—

AD02 AVSS Modu le VSS Supply Vss - 0.3 VSS + 0.3 V —

Reference Inputs

AD05 VREFH Reference Voltage High AVss+2.7 AV DD V—

AD06 VREFL Reference Voltage Low AVss AVDD - 2.7 V —

AD07 VREF Absolute Reference Voltage AVss - 0.3 AVDD + 0.3 V —

AD08 IREF Current Drain — 200

.001 300

3μA

μAA/D operating

A/D off

Analog Input

AD10 VINH-VINL Full-Scale Inpu t Sp an V REFL VREFH V—

AD11 VIN Absolute Input Voltage AVSS - 0.3 AVDD + 0.3 V —

AD12 — Leakage Current — ±0.001 ±0.244 μAV

INL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

Source Impedance = 5 kΩ

AD13 — Leakage Current — ±0.001 ±0.244 μAV

INL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

Source Impedance = 5 kΩ

AD17 RIN Recom m end ed Impedance

Of Analog Voltage Source —5KΩ—

DC Accuracy

AD20 Nr Resol uti on 10 data bits bit s —

AD21 INL Integ ral Nonl ine ari ty(3) —±1±1LSbVINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

AD21A INL In t eg ral Nonl ine ari ty(3) —±1±1LSbVINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD22 DNL Differential Nonlinearity(3) —±1±1LSbVINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

AD22A DNL Differential Nonlinearity(3) —±1±1LSbVINL = AVSS = V REFL = 0V,

AVDD = VREFH = 3V

AD23 GERR Gain Error(3) +1±5±6LSbVINL = AVSS = V REFL = 0V,

AVDD = VREFH = 5V

AD23A GERR Gain Error(3) +1±5±6LSbVINL = AVSS = V REFL = 0V,

AVDD = VREFH = 3V

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: The A/D conversio n resul t neve r decre as es w ith an inc rea se in the inp ut vol t ag e, and has no miss in g

codes.

3: Measurements were taken with external VREF+ and VREF- used as the ADC voltage references.

dsPIC30F2010

AD24 EOFF Offset Error ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

AD24A EOFF Offset Error ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD25 — Monotonicity(2) — — — — Guaranteed

Dynamic Performance

AD30 THD Total Harmonic Distortion — -64 -67 dB —

AD31 SINAD Signal to Noise and

Distortion —5758dB —

AD32 SFDR Spurious Free Dynamic

Range —6771dB —

AD33 FNYQ Input Signal Bandwidth — — 500 kHz —

AD34 ENOB Effective Number of Bits 9.29 9.41 — bits —

TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 2.7V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: The A/D conversio n resul t neve r decre as es w ith an inc rea se in the inp ut vol t ag e, and has no miss in g

codes.

3: Measurements were taken with external VREF+ and VREF- used as the ADC voltage references.

dsPIC30F2010

FIGURE 22-24: 10-BIT HIGH-SPEED A /D C ONVERSION TIMING CHARACTERI STICS

(CHP S = 01, SIMSAM = 0, ASAM = 0, SSR C = 000)

AD55

TSAMP

CLEAR SAMPSET SAMP

AD61

ADCLK

Instruction

SAMP

ch0_dischrg

ch1_samp

AD60

DONE

ADIF

ADRES(0)

ADRES(1)

1 2 3 4 5 6 8 5 6 7

1– Software sets ADCON. SAMP to start sam p lin g.

2– Sampling starts after discharge period TSAMP is described in Section 18.7.

3– Software clears ADCON. SAM P to start conversion.

4– Sampling ends, conversion sequence starts.

5– Convert bit 9.

8– One TAD for end of conversion.

AD50

ch0_samp

ch1_dischrg

eoc

AD55

6– Convert bit 8.

7– Convert bit 0.

Execution

dsPIC30F2010

FIGURE 22-25: 10-BIT HIGH-SPEED A /D C ONVERSION TIMING CHARACTERISTIC S

(CHP S = 01, SIMSAM = 0, ASAM = 1, SSR C = 111, SAMC = 00001)

AD55

TSAMP

SET ADON

ADCLK

Instruction

SAMP

ch0_dischrg

ch1_samp

DONE

ADIF

ADRES(0)

ADRES(1)

1 2 3 4 5 6 4 5 6 8

1– Software sets ADCON. ADON to start AD operation.

2– Sampling starts after discharge period.

3– Convert bit 9.

4– Convert bit 8.

5– Convert bit 0.

AD50

ch0_samp

ch1_dischrg

eoc

7 3

AD55

6– One TAD for end of conversion.

7– Begin conversion of next channel

8– Sample for time specified by SAMC.

TSAMP TCONV

3 4

Execution

TSAMP is described in the “dsPIC30F

Family Reference Manual” (DS70046), Section 17.

TSAMP is described in Section 18.7.

dsPIC30F2010

TABLE 22-39: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Cond itions: 2.7V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Clock Parameters

AD50 TAD A/D Clock Period — 84 — ns See Table 18-1(1)

AD51 tRC A/D Internal RC Oscillator Period 700 900 1100 ns —

Conversion Rate

AD55 tCONV Conversion Time — 12 TAD —— —

AD56 FCNV Throughput Rate — 1.0 — Msps See Table 18-1(1)

AD57 TSAMP Sample Time — 1 TAD — — See Table 18-1(1)

Timing Parameters

AD60 tPCS Conversion Start from Sample

Trigger —1.0 TAD —ns —

AD61 tPSS Sample Start from Setting

Sample (SAMP) Bit 0.5 TAD — 1.5 TAD ns —

AD62 tCSS Conversion Completion to

Sample Start (ASAM = 1)—0.5 TAD —ns —

AD63 tDPU Time to Stabilize Analog Stage

from A/D Off to A/D On —20— μs—

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

dsPIC30F2010

23.0 PACKAGING INFORMATION

23.1 Package Marking Information

28-Lead SOIC (.300”)

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

dsPIC30F2010-30I/SO

0648017

28-Lead SPDIP (Skinny DIP)

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

dsPIC30F2010-30I/SP

0648017

XXXXXXXX

28-Lead QFN-S

XXXXXXXX

YYWWNNN

dsPIC30F2010

Example

-30I/MM

060700U

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Micro chip p art num ber can not be ma rked on on e line, i t will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

dsPIC30F2010

28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body [QFN-S]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

NOTE 1 BOTTOM VIEW

TOP VIEW

EXPOSED

PAD

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length §

Contact-to-Exposed Pad §

Units

Dimension Limits

0.80

0.00

3.65

0.23

0.30

0.20

0.65 BSC

0.90

0.02

0.20 REF

6.00 BSC

3.70

6.00 BSC

3.70

0.38

0.40

—

1.00

0.05

4.70

0.43

0.50

—

MIN NOM MAX

MILLIMETERS

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Package is saw singulated

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–124, Sept. 8, 2006

dsPIC30F2010

28-Lead Skinny Plasti c Dual In-line (SP) – 300 mil Body (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

1510515105

Mold D raft Angle Bottom 1510515105

Mold D raft Angle Top 10.928.898.13.430.350.320

Overall Row Spacing

0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOve ra ll Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Bas e to S eatin g Plane 3.433.303.18.135.130.125A2Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plan e 2.54.100

Pitch 2828

Num ber of Pin s MAXNOMMINMAXNOMMINDime nsion Lim its MILLIMETERSINCHES

Units

Notes:

JEDEC Equivalent: MO-095

Drawing No. C04-070

Contro ll in g P a ra met er

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

Significant Cha racteristic

dsPIC30F2010

28-Lead Plasti c Small Outline (SO) – Wide, 300 mil Body (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Foot Angle Top φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27

.050

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

§ Significant Characteristic

© 2006 Microchip Technology Inc. DS70118G-page 189
dsPIC30F2010
APPENDIX A: REVISION HISTORY
Revision F (May 2006)
Previous versions of this data sheet contained
Advance or Preliminary Information. They were 
distributed with incomplete characterization data.
This revision  reflects these updates:
• Supported I2C Slave addresses 
(see Table 16-1)
• 10-bit A/D High-speed Conversion timing require-
ments (see Section 18.0 “10-bit High-Speed 
Analog-to-Digital Converter (ADC) Module”
• Operati ng Curren t (IDD) specifications 
(see Table 22-5)
• Idle Current (IIDLE) specifications
(see Table 22-6)
• Power-down Current (IPD) specifications
(see Table 22-7)
• I/O pin Input specification s  
(see Table 22-8)
• BOR voltage limits 
(see Table 22-10)
• PLL Clock Timing specifications
(see Table 22-14)
• PLL Jitter specifications
(see Table 22-15 )
• Intern al RC Acc ura cy  spec ifi cat ion s
(see Table 22-17)
• Watchdo g Timer  time-out li mits 
(see Table 22-20)
• Additional minor corrections throughout 
document.
Revision G (December 2006)
This revision includes updates to the packaging 
diagrams.

dsPIC30F2010

NOTES:

© 2006 Microchip Technology Inc. DS70118G-page 191
dsPIC30F2010
INDEX
A
A/D....................................................................................111
1 Msps Configur a tion Guideline...................... ..........115
600 ksps Configuration Guideline.............................116
750 ksps Configuration Guideline.............................116
Conversi o n  Ra te Parameters....... ..................... ........114
Conversion Speeds........................ .... .. .... .. .. ....... .... ..114
Selec t i n g  th e  C o n ve r sion C l o ck.... .. ...... ...... ..... ...... .. .1 1 3
Voltage Reference Schematic ............................ .. ....115
AC Characteristics ............................................................157
Load Conditions...................... ....... .. .. .. .. .. .. ....... .. .. .. ..157
AC Temperature and Voltage Specifications....................157
Address Generator Units ....................................................31
Alternate 16-bit Timer/Counter............................................77
Alternate Vector Table........................................................41
Assembler
MPASM Assembler...................................................146
Automatic Clock Stretch. .....................................................98
During 10-bit Addressing (STREN = 1).......................98
During 7-bit Addressing (STREN = 1).........................98
Receive Mode.............................................................98
Transmit Mode...... ........................... ...........................98
B
Band Gap Start-up Time
Requirements............................................................164
Timing Cha racterist ics ............... .............. ............... ..164
Barrel Shifter.......................................................................17
Bit-Reversed Addre ssing................................... .................35
Example......................................................................35
Implementation ...........................................................35
Modifier Values (T a b l e ).......................... .....................36
Sequence Table (16-Entry)....................................... ..36
Block Diagram
PWM...........................................................................82
Block Diagrams
10-bit High Speed ADC Functional...........................111
16-bit Timer1 Module..................................................58
DSP Engine....... .................................. .......................14
dsPIC30F2010..............................................................6
External Power-on Reset Circuit...............................131
I2C...............................................................................96
Input Capture Mode.............. ....... .. .... .. .. .... .. ....... .. .. ....67
Oscillator System......................................................125
Output Co mpa re Mode .......................... .....................71
Quadrature Encoder Interface ....................................75
Reset System........ ........................... ..................... ....129
Shared Po rt Structure................................ .................53
SPI..............................................................................92
SPI Master/Slave Connection.....................................92
UART Receiver.........................................................104
UART Transmitter.....................................................103
BOR Characteristics .........................................................156
BOR. See Brown-out Reset
Brown-out Reset
Characteristics..........................................................155
Timing Requirements............................... .. ....... .. .. ....163
Brown-out Reset (BOR)....................................................123
C
C Compilers
MPLAB C18........ ........................... ..................... ...... 146
MPLAB C30........ ........................... ..................... ...... 146
Center-Aligned PWM.......................................................... 85
CLKO and I/O Timing
Characteristics.......................................................... 161
Requirements........................................................... 161
Code Examples
Data EEPRO M Block Erase............ ..................... ...... 50
Data EEPRO M Block Write.................... .................... 52
Data EEPRO M Read...... ..................... ..................... .. 49
Data EEP RO M Word Er a se ........................... ............ 50
Data EEPRO M Word Write ....... ........................... ...... 51
Erasing a Row of Program Memory ........................... 45
Initiating a Programming Sequence ................. .... .. .. .. 46
Loading Write Latches............. .. .. .... .. .. ..... .. .... .. .. .. .. .. .. 46
Code Protection................................................................ 123
Complementary PWM Operation........................................ 86
Config u ring Analog Port Pins................... ..................... ...... 54
Control Reg i s te rs.................. ............... ............... ................ 44
NVMADR.................................................................... 44
NVMADRU ................................................................. 44
NVMCON.................................................................... 44
NVMKEY .................................................................... 44
Core Architecture
Overview....................................................................... 9
Core Register Map.............................................................. 27
Customer Change Notification Service............................. 199
Custome r Notification Ser vice ................... ............... ........ 199
Customer Support............................ ...... .... ........... .... .... .... 199
D
Data Access from Program Memory Using 
Program Space Visibility............................................. 22
Data Accumulators and Adder................................ 15, 16, 17
Data Addre ss Space.................... ..................... .................. 23
Access RAM... ..................... ........................... ............ 27
Alignment.................................................................... 26
Alignment (Figure)...................................................... 26
MCU and DSP (MAC Class) Instructions ................... 25
Memory Map ......................................................... 23, 24
Spaces........................................................................ 26
Width .......................................................................... 26
Data EEPRO M Mem ory...... ..................... ........................... 49
Erasing ....................................................................... 50
Erasing, Block............................................................. 50
Erasing, Word............................................................. 50
Protection Agains t Sp u rious Write....... ..................... .. 52
Reading...................................................................... 49
Write Verify................................................................. 52
Writing ........................................................................ 51
Writing , Block..................... ..................... .................... 52
Writing , Wo rd........ ............... ..................... .................. 51
DC Characteristics. ........................................................... 149
BOR.......................................................................... 156
Brown-o u t Re set.......................... ..................... ........ 155
I/O Pin Input Specifications ............................ .... .. .... 153
I/O Pin Outpu t Specifications... ........ ..................... .... 155
Idle Current (IIDLE).................................................... 152
Operating Current (IDD) ............................................ 151
Power-Down Current (IPD)........................................ 153
Program and EEPROM ............................................ 156
Temperature and Voltage Specifications .................. 149

dsPIC30F2010
DS70118G-page 192 © 2006 Microchip Technology Inc.
Dead-Time Generators .......................................................86
Ranges........................................................................86
Development Support .......................................................145
Device Configuration
Register Map........................... ..................... .............135
Device Configuration Registers .........................................134
FBORPOR ................................................................134
FGS...........................................................................134
FOSC........................................................................134
FWDT........................................................................134
Device Overview...................................................................5
Divide Support................ .... ....... .... .. .. .... .. ....... .... .. .... .. ....... ..12
DSP Engine. .................................. ........................... ...........13
Multiplier......................................................................15
Dual Output Compare Match Mode ........ ............... .............72
Continuous Pulse Mode............................. .... .. .. ....... ..72
Single  Pu lse Mode. ............................ .........................72
E
Edge-Aligned PWM........ .... ....... .. .... .... .. ....... .... .... .. .... .. .......85
Electrical Characteristics...................................................149
AC.............................................................................157
DC.............................................................................149
Equations
A/D Convers i o n  Clock............... ............... .................113
Baud Rate.................................................................107
PWM Period.............................. ..................................84
PWM Period (Up/Down Count Mode)............ .... .. .......84
PWM Resolut i on.... ..................... ..................... ...........84
Serial Clock Rate ......................................................100
Errata ....................................................................................4
Exception Sequence
Trap Sources ................ ........................... ...................39
External Clock Timing Characteristics
Type A an d B Time r............ ......................................165
External Clock Timing Requirements. ...............................158
Type A Time r ..... ........................... ............................165
Type B Time r ..... ........................... ............................166
Type C Timer..... ............... ........................... .............166
External Interrupt Requests ................................................41
F
Fast Context Saving............................................................41
Firmware Instructions........................................................137
Flash Pr o g ram Memory................................ .......................43
In-Circuit Serial Programming (ICSP).........................43
Run-Time Self-Programming (RTSP) .........................43
Table Instruction Operation Summary........................43
I
I/O Pin Specifications
Input..........................................................................153
Output .......................................................................155
I/O Ports............. ........................... .................................. ....53
Paral l e l  I/O (PIO)......................... ............................ ....53
I2C.......................................................................................95
I2C 10-bit Slave Mode Operation........................................97
Reception....................................................................98
Transmission...............................................................98
I2C 7-bit Slave Mode Operation..........................................97
Reception....................................................................97
Transmission...............................................................97
I2C Master Mode
Baud Rate Generator ............................................... 100
Clock Arbitration....................................................... 100
Multi-Master Communication, Bus Collision and 
Bus Arbitration.... ........................... ................... 100
Reception ................................................................. 100
Transmission ............................................................ 100
I2C Module
Addresses................................................................... 97
Bus Data Timing Characteristics
Master Mode..................................................... 178
Slave Mode................................ ....................... 180
Bus Data Timing Requirements
Master Mode..................................................... 179
Slave Mode................................ ....................... 181
Bus Start/Stop Bits Timing Characteristics
Master Mode..................................................... 178
Slave Mode................................ ....................... 180
General Call Address Support.. .................................. 99
Interrupts .................................................................... 99
IPMI Support............................................................... 99
Master Operation........................................................ 99
Master Support........................................................... 99
Operating Function Description.................................. 95
Operation During CPU Sleep and Idle Modes.......... 101
Pin Configuration........................................................ 95
Programm er’s Model .................................................. 95
Register Map ... ............................ ..................... ........ 10 2
Registers .................................................................... 95
Slope Control.............................................................. 99
Software Controlled Clock Stretching (STREN = 1) . .. 99
Various Modes...................... .. ....... .... .. .. .... .. ....... .... .. .. 95
Idle Current (IIDLE)............................................................ 152
In-Circuit Serial Programming (ICSP)............................... 123
Independent PWM Output.................................................. 87
Initialization Condition for RCON Register Case 1 ........... 132
Initialization Condition for RCON Register Case 2 ........... 132
Initialization Condition for RCON Register, Case 1.......... 132
Input Capture (CAPx) Timing Characteristics................... 168
Input Capture Interrupts...................................................... 69
Register Map ... ............................ ..................... .......... 70
Input Capture Module......................................................... 67
In CPU Slee p Mode............ ............................ ............ 69
Simple Capture Event Mode ....................................... 68
Input Capture Timing Requirements................................. 168
Input Change Notification Module....................................... 54
Register Map (bits 15-0)............................................. 55
Input Characteristics
QEA/QEB ................................................................. 171
Instruction Addressing Modes ............................................ 31
File Register Instructions............................................ 31
Fundamental Modes Supported .................. ....... .... .. .. 31
MAC Instru ctions .. ..................... ..................... ............ 32
MCU Instru ctions................................... ..................... 32
Move and Accumulator Instructions ............................ 32
Other Ins tructio n s....... ........................... ..................... 32
Instruction Set................................................................... 137
Inter-Integrated Circuit. See I2C
Internal Clock Timing Examples....................................... 160
Inter n e t Ad d ress ................................ ........................... .... 199

© 2006 Microchip Technology Inc. DS70118G-page 193
dsPIC30F2010
Interrupt Controller
Register Map..................... ..................... .....................42
Inter rupt Priority ........................ ........................... ...............38
Traps...........................................................................39
Interrupt Sequence ......................... ........... .... .... ......... .... ....41
Inter rupt Stack Frame.......................... .......................41
Interrupts.............................................................................37
L
Load Conditions....... .. ..... .. .. .... .. .. .. .. ..... .... .. .. .. .. .. .. ....... .. .. ..157
M
Memory Organization..........................................................19
Microc h i p  In ternet Web Site......................... .....................199
Modulo Addressing .............................................................33
Applicability.................................................................35
Operation Example.....................................................34
Start and End Address................................................33
W Addres s Reg ister Selection................. ...................33
Motor Control PWM Module. ...............................................81
Fault Timing Character i stics ...... .............. .................170
Timing Cha racterist ics ............... .............. ............... ..170
Timing Requirements............................... .. ....... .. .. ....170
MPLAB ASM30 Assembler, Linker, Librarian ...................146
MPLAB ICD 2 In-Circuit Debugger ...................................147
MPLAB ICE 2000 High-Perform ance Universal 
In-Circuit Emulator....................................................147
MPLAB ICE 4000 High-Perform ance Universal 
In-Circuit Emulator....................................................147
MPLAB Integrated Development Environment Software..145
MPLAB PM3 Device Programmer ....................................147
MPLINK Object Linker/MPLIB Object Libraria n................146
O
OC/PWM Module Timing Characteristics..........................169
Operating Current (IDD).....................................................151
Operating MIPS vs Voltage
dsPIC30F2010..........................................................149
Oscillator
Configurations
Fast RC (FRC)..................................................127
Low Power RC (LPRC).....................................127
Phase Locked Loop (PLL) ................. .. ......... .. ..127
Oscillator Configurations...................................................126
Fail-Safe Clock Monitor.............................................128
Initial Clock Source Selection...................................126
LP Oscillator Control.................................................127
Start- u p  Timer (OST)................. ...............................126
Oscillator Operating Modes Table . ...................................124
Oscillator Selection ...........................................................123
Oscillator Start-up Timer
Timing Cha racterist ics ............... .............. ............... ..162
Timing Requirements............................... .. ....... .. .. ....163
Output Co mpa re Interrup ts........... ..................... .................73
Output Compare Mode
Register Map..................... ..................... .....................74
Output Compare Module.............................. .. .. .... ....... .. .... ..71
Timing Cha racterist ics ............... .............. ............... ..168
Timing Requirements............................... .. ....... .. .. ....168
Output Compare Operation During CPU Idle Mode............73
Output Compare Sleep Mode Operation ............................73
P
Packagi n g  In fo rmation............... ..................... .................. 187
Marking..................................................................... 187
PICSTART Plus Development Programmer..................... 148
Pinout Descriptions.......................... .. .... .... .. ....... .... .... .. .... .... 7
PLL Clock Timing  Sp e c ifications............... ............... ........ 159
POR. See Power-on Reset
Port Register Map............................................................... 55
Port Write/Read Example................................................... 54
PORTB
Register Map.............. ............................ .................... 55
PORTC
Register Map.............. ............................ .................... 55
PORTD
Register Map.............. ............................ .................... 55
PORTE
Register Map.............. ............................ .................... 55
PORTF
Register Map.............. ............................ .................... 55
Positio n  Mea surement Mode......... .............. ..................... .. 77
Power-Down Current (IPD)................................................ 153
Power-on Reset (POR)..................................................... 123
Oscillato r Start-up Timer (OST)......... ......... ........ ...... 123
Power-up Timer (PWRT).......................................... 123
Power-Saving Modes.................................................... .... 133
Idle............................................................................ 134
Sleep ........................................................................ 133
Power-Saving Modes (Sleep and Idle)............................. 123
Power-up Timer
Timing Ch a rac te ristics............. ............... .................. 162
Timing Re q uirements ........................ ....................... 163
Product Identification System........................................... 201
Program Address Space..................................................... 19
Construction ............................................................... 20
Data Access from Program Memory Using 
Table Ins tructio n s........ ........................... ............ 21
Data Access From, Address Generation.................... 20
Memory Map ............................................................... 19
Table Instructions
TBLRDH............................................................. 21
TBLRDL.............................................................. 21
TBLWTH............................................................. 21
TBLWTL ............................................................. 21
Program and EEPRO M Charac terist ics ............................ 156
Program Counter................................................................ 10
Program Data Table Access........ ..................... .................. 22
Program Space Visibility
Window into Program Space Operation ........... .. .. .... .. 23
Programmable.................................................................. 123
Programmable Digital Noise Filters.................................... 77
Programm er’s Model .......................................................... 10
Diagram...................................................................... 11
Programming Operations...... ..................... ..................... .... 45
Algor ith m for Program Flas h.... ........................... ........ 45
Erasing a Row of Program Memory ........................... 45
Initiating the Programming Sequence ........................ 46
Loading Write Latches............. .. .. .... .. .. ..... .. .... .. .. .. .. .. .. 46
Programming, Device Instructions.................................... 137
Protection Against Accidental Writes to OSCCON........... 128

dsPIC30F2010
DS70118G-page 194 © 2006 Microchip Technology Inc.
PWMRegister  Map...... ............... ........................... ...............90
PWM Duty Cycle Comparison Units ...................................85
Duty Cycle Register Buffer s................... .....................86
PWM FLTA Pins..................................................................88
Enable Bits..................................................................88
Fault States..................... ................................. ...........88
Modes .........................................................................88
Cycle-by-Cycle....................................................88
Latched...............................................................88
PWM Operation  During CPU Idle Mode......... .............. .......89
PWM Operation During CPU Sleep Mode..........................89
PWM Output and Polarity Control... .... .... ......... .... .. .... .........88
Output Pin  Co n trol .......... ..................... ..................... ..88
PWM Output  Override........ ............................ .....................87
Complementary Output Mode.....................................87
Synchronization ..........................................................87
PWM Period.. ............................ ........................... ...............84
PWM Special Event Trigger..................................... .. .........89
Postscaler...................................................................89
PWM Time Base.. .............. ............................ .....................83
Continuous Up/Down Counting Modes........ .. .. .. .. .......83
Double Update Mode.................... .. ....... .. .. .. .... .. .. .......84
Free Running Mode . ..................... ..................... .........83
Postscaler...................................................................84
Prescaler.....................................................................84
Single-Shot Mode .......................................................83
PWM Update Lockout.........................................................88
Q
QEA/QEB Input Characteristics........................................171
QEI Module
External Clock Timing Requirements........................167
Index Pulse Timing Characteristics.................. .. .......172
Index Pulse Timing Requirements..................... .. .....172
Operation During CPU Idle Mode...............................78
Operation During CPU Sleep Mode............................77
Register Map........................... ..................... ...............79
Timer Operation During CPU Idle Mode.....................78
Timer Operation During CPU Sleep Mode..................77
Quadrature Decoder Timing Requirements ... .... .. .... .. .......171
Quadrature Encoder Interface (QEI ) Module ......................75
Quadrature Encoder Interface Interrupts ............................78
Quadrature Encoder Interface Logic...................................76
R
Reader Response.............................................................200
Reset.........................................................................123, 129
Reset Sequence.............................. .. .... ....... .... .... .. .... .........39
Reset Sources ......... ..................... ............................ ..39
Reset Timin g  Char acteristics.. ........ ........ ............... ...........162
Reset Timing Requirements................................... .. .... .....163
Resets
BOR, Programmable.......................... .......................131
POR..........................................................................129
Operating without FSCM and PWRT................131
POR with Long Crystal Start-up Time.......................131
RTSP Operation..................................................................44
S
Sales and Support........................ ....... .... .. .... .. .... ....... .. .... 201
Serial Peripheral Interface. See SPI
Simple Capture Event Mode
Capture Bu ffer Operation................................ ............ 68
Capture Prescaler................. ..................... ................. 68
Hall Sensor Mode........... ............... ..................... ........ 68
Input Capture in CPU Idle Mode................................. 69
Timer2 and Timer3 Selection Mode...................... .... .. 68
Simple OC/PWM Mode Timing Requirements ................. 169
Simp le  Outp ut Co mp a re Ma tc h Mo d e ........ ...... ..... .......... ... 7 2
Simple PWM Mode.............................................................72
Input Pin  Fa u l t Protectio n................................. .......... 72
Period ......................................................................... 73
Single Pulse PWM Operation............................................. 87
Softwar e  Simulator (MPL AB SIM) ......... ..................... ...... 14 6
Softwar e  Stack Point e r, Frame Pointer ... ..................... ...... 10
CALL Stack Fr a me.................... ..................... ............ 27
SPI...................................................................................... 91
SPI Mode
Slave Select Synchron i zation. ............................ ........ 93
SPI1 Register Map...................................................... 94
SPI Module......................................................................... 91
Framed SPI Support................................................... 91
Operating Function Description.................................. 91
SDOx Disabl e.............................. ..................... .......... 91
Timing Characteristics
Master Mode (CKE = 0). ................................... 173
Master Mode (CKE = 1). ................................... 174
Slave Mode (CKE = 1).............................. 175, 176
Timing Requirements
Master Mode (CKE = 0). ................................... 173
Master Mode (CKE = 1). ................................... 174
Slave Mode (CKE = 0)..................... ............... .. 175
Slave Mode (CKE = 1)..................... ............... .. 177
Word and Byte Communication................................ .. 91
SPI O p e ra ti o n  D u r i n g  C PU  Id l e  M o de ........ ...... ..... ...... ...... . 93
SPI Operation During CPU Sleep Mode............................. 93
STATUS Regi ster...... ..................... ..................... ............... 10
Subtracter........................................................................... 15
Data Space Write Saturation......................................17
Overflow and Saturation................ .... .... .... .. ......... .... .. 15
Round Logic . .............................................................. 16
Write Back .................................................................. 16
Symbols used in Opcode Descriptions............................. 138
System Integration............................................................ 123
Overview................................................................... 123
Register Map ... ............................ ..................... ........ 13 5
T
Temperature and Voltage Specifications
AC............................................................................. 157
DC ............................................................................ 149
Timer1 Module.................................................................... 57
16-bit Asynchronous Counter Mode........................... 57
16-bit Synchronous Counter Mode............................. 57
16-bit Timer Mode........................ ........................... .... 57
Gate Operation........................................................... 58
Interrupt ...................................................................... 59
Operation During Sleep Mode.................................... 58
Prescaler .................................................................... 58
Real-Time Clock......................................................... 59
RTC Interru p ts............................. ..................... .. 59
RTC Oscillator Operation ................................... 59
Register Map ... ............................ ..................... .......... 60

© 2006 Microchip Technology Inc. DS70118G-page 195
dsPIC30F2010
Timer2 and Timer3 Selection Mode................... .. ......... .. ....72
Timer2/3 Module................. .... .. .. .... ....... .. .... .. .. .... ....... .. .. ....61
32-bit Synchronous Counter Mode. ............................61
32-bit Timer Mode.......................................................61
ADC Event Trigger......................................................64
Gate Operation ...........................................................64
Interrupt.......................................................................64
Operation During Sleep Mode ....................................64
Register Map..................... ..................... .....................65
Timer Prescaler...........................................................64
TimerQ (QEI Modu le) Ex terna l Clock Timi ng 
Characteristics..........................................................167
Timing Characteristics
A/D Conversion
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000)..........................184
10-bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111, SAMC = 00001) 185
Band Gap Start-up Time...........................................164
CLKO and I/O ...........................................................161
External Clock...........................................................157
I2C Bus Data
Master Mode.....................................................178
Slave Mode.......................................................180
I2C Bus Start/Stop Bits
Master Mode.....................................................178
Slave Mode.......................................................180
Input Capture (CAPx)................................. .. ......... .. ..168
Motor Control PWM Module......................................170
Motor Control PWM Module Falult............................170
OC/PWM Module. .....................................................169
Oscillator Start-up Timer...........................................162
Output Co mpa re Module.................... .......................168
Power-up  Timer ........................... ..................... ........162
QEI Module Index Pulse....................................... ....172
Reset.........................................................................162
SPI Module
Master Mode (CKE = 0)....................................173
Master Mode (CKE = 1)....................................174
Slave Mode (CKE = 0)......................................175
Slave Mode (CKE = 1)......................................176
TimerQ (QEI Module) Ex ternal Clock .. .....................167
Type A and B Timer External Clock..........................165
Watchdog Timer...................... ....... .. .. .... .. .... ..... .... .. ..162
Timing Diagrams
Center-Aligned PWM. .................................................85
Dead-Time..................................................................87
Edge-Aligned PWM................................ .... .. ....... .... .. ..85
PWM Output......... ..................... ........................... ......7 3
Time-out Sequence on Power-up (MCLR 
Not Tied to VDD), Case 1..................................130
Time-out Sequence on Power-up (MCLR 
Not Tied to VDD), Case 2..................................130
Time-out Sequence on Power-up (MCLR 
Tied to VDD)......................................................130
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy...............160
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
High-speed....................................................... 186
Band Gap Start-up Time........................................... 164
Brown-o u t Re set.......................... ..................... ........ 163
CLKO and I/O........................................................... 161
External Clock .......................................................... 158
I2C Bus Data (Master Mode) .................................... 179
I2C Bus Data (Slave Mode)...................................... 181
Input Capture............................................................ 168
Motor Control PWM Module ..................................... 170
Oscillator Start-up Timer...... ..................................... 163
Output Com p a re Module.................................. ........ 168
Power-up Timer........................................................ 163
QEI Module
External Clock.................................................. 167
Index Pulse....... ..................... ........................... 172
Quadrature Decoder.................. .... .. .... ......... .. .... .... .. 171
Reset........................................................................ 163
Simple OC/PWM Mode ............................................ 169
SPI Module
Master Mode (CKE = 0)........................ .. .... .. .. .. 173
Master Mode (CKE = 1)........................ .. .... .. .. .. 174
Slave Mode (CKE = 0)...................................... 175
Slave Mode (CKE = 1)...................................... 177
Type A Timer Ex te rnal Clock..... ............... ................ 165
Type B Timer Ex te rnal Clock..... ............... ................ 166
Type C Timer External Clock.................................... 166
Watchdog Timer ....... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. .. 163
Timing Specifications
PLL Clock ................................................................. 159
U
UART
Address Detect Mode............................................... 107
Auto Baud Support............................................. .... .. 107
Baud Rate Generator ............................................... 107
Enabling and Setting Up UART. .. .. .. .. .. ..... .... .. .. .. .. .. .. 105
Altern a te I/O ...................... ........................... .... 105
Disabling........................................................... 105
Enabling ........................................................... 105
Setting Up Data, Parity and Stop Bit 
Selections................................................. 105
Loopback Mode...... .. .... .. ....... .... .. .. .... .. ....... .. .... .. .... .. 107
Module Overview...................................................... 103
Operation During CPU Sleep and Idle Modes.......... 108
Receiving Data......................................................... 106
In 8-bit or 9-bit Data Mode................................ 106
Interrupt............................................................ 106
Receive Buffer (UxRXB)..................... .............. 106
Reception Error Handling............ ........ ............... ...... 106
Framing Error (FERR)...................................... 107
Idle Status ........................................................ 107
Parity Error (PERR).......................................... 107
Receive Bre a k............. ..................... ................ 107
Receive Buffer Overrun Error (OERR Bit)........ 106
Transmitting Data..................................................... 105
In 8-bit Da ta  Mod e............... ..................... ........ 105
In 9-bit Da ta  Mod e............... ..................... ........ 105
Interrupt............................................................ 106
Transmit Buffer (UxTXB).................................. 105
UART1 Register Map ............................................... 109
Unit ID Locations.............................................................. 123
Universal Asynchronous Receiver Transmitter. See UART.

dsPIC30F2010

Wake-up from Sleep .........................................................123

Wake-up from Sleep and Idle..............................................41

Watchdog Timer

Timing Cha racterist ic s ...... ........ ............... ............... ..162

Timing Requirements................ .... .. ..... .... .. .. .. .... .. .....163

Watchdog Timer (WDT)................................... .... .. ...123, 133

Enabling and Disabling .............................................133

Operation ..................................................................133

WWW Address..................................................................199

WWW, On-Line Support ........................................................4

dsPIC30F2010

THE MICROCHIP WEB SITE

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dsPIC30F2010

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DS70118GdsPIC30F2010

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dsPIC30F2010

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dsPIC30F2010AT-30E/SO-ES

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dsPIC30F2010AT-30E/SO = 30 MIPS, Extended temp., SOIC package, Rev. A

Trademark

Architecture

Flash

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Temperature

Device ID

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Memory Size in Bytes

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WORLDWIDE SALES AND SERVICE

10/19/06

© 2006 Microchip Technology Inc. DS70118G-page 1
0 Device Overview .......................................................................................................................................................................... 5
0 CPU Architecture Overview.......................................................................................................................................................... 9
0 Memory O rganization. ................................................................................................................................................................ 19
0 Address Generato r Units............................................................................................................................................................ 31
0 Interrupts.................................................................................................................................................................................... 37
0 Flash Pro g ram Memory............................ ............................ ........................... ........................................................................... 43
0 Data EEPR OM Mem o ry........ ..................... ..................... ............................ ........................... .................................................... 49
0 I/O Ports........... ............................ ........................... .................................. ................................................................................. 53
0 Timer1 Module ........................................................................................................................................................................... 57
0 Timer2/3 Module ................... ....... .. .. .. .. .... .. ..... .... .. .. .. .. .... ..... .. .. .... .. .. .. .. ....... .. .. .. .... .. .. ..... ............................................................ 61
0 Input Capture Module............................. .... ..... .... .. .. .... .. .. ....... .. .... .. .. .... ..... .... .. .. .... .. .. ....... .......................................................... 67
0 Output Compa re Module........................ ..................... ..................... ............................ .............................................................. 71
0 Quadrature Encoder Interface (QEI ) Module . ............................................................................................................................ 75
0 Mot or Control PWM Module....................................................................................................................................................... 81
0 SP I Module................................................................................................................................................................................. 91
0 I2C Module................................................................................................................................................................................. 95
0 U nivers al Asynchr onous Receiver  Transmi tter (UART) Module .............................................................................................. 103
0 10-bit High-Speed Analog-to-Digital Converter (ADC) Module........................... .... .. ....... .... .... .. .... ....... .. ................................. 111
0 System Inte g r a tion .... ..................... ..................... ........................... ..................... ..................................................................... 123
0 Instruction Set Summary.......................................................................................................................................................... 137
0 Development Support............................................................................................................................................................... 145
0 Electrical Characteristics.......................................................................................................................................................... 149
0 Packagin g  In fo rmation.............................. ............................ ..................... ............................................................................... 187
The Micro chip Web Site...... ........................... ........................... .................................. ....................................................................... 199
Customer Change Notification Service............................................................................... ............................................................... 199
Customer Support............................................................... .... ............. ...... ............. ...... .... ................................................................. 199
Reader Response.............................................................................................................................................................................. 200
Product Identification System ............................................................................................................................................................ 201