ICS8535AG-31T - Integrated Circuit Systems, Inc.

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

GENERAL DESCRIPTION

The ICS8535-31 is a low skew, high performance

1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V

LVPECL fanout buffer and a member of the

HiPerClockS™ family of High Performance Clock

Solutions from ICS. The ICS8535-31 has select-

able single ended clock or crystal inputs. The single ended

clock input accepts LVCMOS or LVTTL input levels and

translate them to 3.3V LVPECL levels. The output enable is

internally synchronized to eliminate runt pulses on the out-

puts during asynchronous assertion/deassertion of the clock

enable pin.

Guaranteed output and part-to-part skew characteristics

make the ICS8535-31 ideal for those applications demand-

ing well defined performance and repeatability.

FEATURES

•4 differential 3.3V LVPECL outputs

•Selectable LVCMOS/LVTTL CLK or crystal inputs

•CLK can accept the following input levels: LVCMOS, LVTTL

•Maximum output frequency: 266MHz

•Output skew: 30ps (maximum)

•Part-to-part skew: 200ps (maximum)

•Propagation delay: 1.65ns (maximum)

•Additive phase jitter, RMS: 0.057ps (typical)

•3.3V operating supply

•0°C to 70°C ambient operating temperature

•Lead-Free package fully RoHS compliant

•Industrial Temperature information available upon request

•Replaces the ICS8535-11

BLOCK DIAGRAM PIN ASSIGNMENT

ICS8535-31

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm package body

G Package

Top View

VEE

CLK_EN

CLK_SEL

CLK

XTAL_IN

XTAL_OUT

VCC

nQ0

VCC

nQ1

nQ2

VCC

nQ3

HiPerClockS™

ICS

CLK

nQ0

nQ1

nQ2

nQ3

CLK_EN

CLK_SEL

OSC

XTAL_IN

XTAL_OUT

Pullup

Pulldown

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

rebmuNemaNepyTnoitpircseD

rewoP.nipylppusevitageN

2NE_KLCtupnIpulluP

kcolcswollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS

.hgihd

ecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni

.slevelecafretniLTTVL/SOMCVL

3LES_KLCtupnInwodlluP .st

upniLATXstceles,HGIHnehW.tupnitceleskcolC

.slevelecafretniLTTVL/SOMCVL.tupniKLCstceles,WOLnehW

4KLCtupnInw

odlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolC

9,8,5cndesunU.tcennocoN

,NI_LATX

TUO_LATX tupnI .tupniehtsiNI

_LATX.ecafretnirotallicsolatsyrC

.tuptuoehtsiTUO_LATX

81,31,01V

rewoP.snipylppusevitisoP

21,113Q,3QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD

51,412Q,2QntuptuO.sl

evelecafretniLCEPVL.stuptuokcolclaitnereffiD

71,611Q,1QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnere

ffiD

02,910Q,0QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD

:ETON

pulluP

dna

nwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

TABLE 3A. CONTROL INPUT FUNCTION TABLE

TABLE 3B. CLOCK INPUT FUNCTION TABLE

stupnIstuptuO

NE_KLCLES_KLCecruoSdetceleS3Q:0Q3Qn:0Qn

00 KLCWOL;delbasiDHGIH;delbasiD

01 TUO_LATX,NI_LATXWOL;delbasiDHG

IH;delbasiD

10 KLCdelbanEdelbanE

11 TUO_LATX,NI_LATXdelbanEdelbanE

latsyrcrokcolctupnignillafdnagnisiragniwollofde

lbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA

ninwohssaegderotallicso

erugiF

.B3elbaTnidebircsedsatupniKLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI

stupnIstuptuO

KLC3Q:0Q3Qn:0Qn

0WOLHGIH

1HGIHWOL

Enabled

Disabled

CLK

CLK_EN

nQ0:nQ3

Q0:Q3

FIGURE 1. CLK_EN TIMING DIAGRAM

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI 2V

V3.0+V

egatloVwoLtupnI 3.0-8.0V

tnerruChgiHtupnI

,KLC

LES_KLC V

V564.3=051Aµ

NE_KLCV

V564.3=5Aµ

tnerruCwoLtupnI

,KLC

LES_KLC V

V,V0=

V564.3=5-Aµ

NE_KLCV

V,V0=

V564.3=051-Aµ

TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuOV

4.1-V

9.0-V

1ETON;egatloVwoLtuptuOV

-0.2V

-7.1V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V

05htiwdetanimretstuptuO:1ETON ΩVot

.V2-

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSrewoP 531.33.3564.3V

tnerruCylppuSrewoP 06Am

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θ

JA 73.2°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

TABLE 6. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO 662zHM

1ETON;yaleDnoitagaporP 54.156.1sn

tij ;SMR,rettiJesahPevitiddAreffuB

noitceSrettiJesahPevitiddAotrefer

,zHM25.551

:egnaRnoitargetnI(

)zHM02-

zHk21

750.0sp

)o(ks4,2ETON;wekStuptuO 03sp

)pp(ks4,3ETON;wekStraP-ot-traP 002sp

emiTllaF/esiRtuptuO%08ot%02003006sp

cdoelcyCytuDtuptuO 6445%

ƒtaderusaemsretemarapllA ≤.esiwrehtodetonsselnuzHM6

VehtmorfderusaeM:1ETON

.tniopgnissorctuptuolaitnereffidehtottupniehtfo2/

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastu

ptuoneewtebwekssadenifeD:2ETON

.stniopssorclaitnereffidtuptuoehttaderusaeM

daollauqehtiwdnasegatlovylpp

usemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON

.stniopssorclaitnereffidehttad

erusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnoc

.56dradnatSCEDEJhtiwecnadroccanid

enifedsiretemarapsihT:4ETON

TABLE 5. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 2104zHM

)RSE(ecnatsiseR

seireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

leveLevirD 1Wm

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

ADDITIVE PHASE JITTER

Additive Phase Jitter, RMS

@ 155.52MHz (12kHz to 20MHz)

= 0.057ps typical

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k 10k 100k 1M 10M 100M

The spectral purity in a band at a specific offset from the funda-

mental compared to the power of the fundamental is called the

dBc Phase Noise.

This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise

power present in a 1Hz band at a specified offset from the fun-

damental frequency to the power value of the fundamental. This

ratio is expressed in decibels (dBm) or a ratio of the power in

As with most timing specifications, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise floor of the equipment is higher than

the noise floor of the device. This is illustrated above. The de-

the 1Hz band to the power in the fundamental. When the re-

quired offset is specified, the phase noise is called a

dBc

value,

which simply means dBm at a specified offset from the funda-

mental. By investigating jitter in the frequency domain, we get a

better understanding of its effects on the desired application over

the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

vice meets the noise floor of what is shown, but can actually be

lower. The phase noise is dependant on the input source and

measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

PARAMETER MEASUREMENT INFORMATION

PROPAGATION DELAY

OUTPUT SKEW3.3V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

nQx

LVPECL

OUTPUT RISE/FALL TIME

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

-1.3V ± 0.165V

sk(o)

nQx

nQy

Clock

Outputs 20%

80% 80%

20%

SWING

Pulse Width

tPERIOD

PERIOD

odc =

Q0:Q3

nQ0:nQ3

CLK

Q0:Q3

nQ0:nQ3

VEE

VCC

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

APPLICATION INFORMATION

- 2V

50Ω50Ω

RTT

= 50Ω

FOUT FIN

RTT = Z

((V

+ V

) / (V

– 2)) – 2

3.3V

125Ω125Ω

84Ω84Ω

Zo = 50Ω

FOUT FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

50Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion.

Figures 2A and 2B

show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

TERMINATION FOR LVPECL OUTPUTS

FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION

Figure 3. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS8535-31 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown

Figure 3

below were determined using an 18pF parallel reso-

nant crystal and were chosen to minimize the ppm error.

These same capacitor values will tune any 18pF parallel reso-

nant crystal over the frequency range and other parameters

specified in this data sheet. The optimum C1 and C2 values

can be slightly adjusted for different board layouts.

18p

18pF Parallel Crystal

22p

XTAL_IN

XTAL_OUT

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8535-31.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8535-31 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 60mA = 207.9mW

•Power (outputs)MAX = 30mW/Loaded Output pair

If all outputs are loaded, the total power is 4 * 30mW = 120mW

Total Power_MAX (3.465V, with all outputs switching) = 207.9mW + 120mW = 327.9mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.328W * 66.6°C/W = 92°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. THERMAL RESISTANCE θθ

θθ

θJA FOR 20-PIN TSSOP, FORCED CONVECTION

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in

Figure 4.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V

- 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCC_MAX - VOH_MAX

) = 0.9V

• For logic low, VOUT = VOL_MAX = VCC_MAX

– 1.7V

(VCC_MAX - VOL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOH_MAX) = [(2V - (V

CC_MAX - VOH_MAX

))/R

] * (VCC_MAX

- VOH_MAX) =

[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOL_MAX) = [(2V - (V

CC_MAX - VOL_MAX

))/R

] * (VCC_MAX

- VOL_MAX) =

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION

VOUT

VCC

VCC - 2V

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS8535-31 is: 428

TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP

TABLE 9. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

NIMXAM

N02

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D04.606.6

ECISAB04.6

1E03.405.4

eCISAB56.0

L54.057.0

α°

0°8

aaa--01.0

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

TABLE 10. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

13-GA5358SCI13-GA5358SCIPOSSTdael02ebutC°07otC°0

T13

-GA5358SCI13-GA5358SCIPOSSTdael02leer&epat0052C°07otC°0

FL13-GA5358SCIL13GA5358SCIPOSST"eerF-daeL"dael02ebutC°

07otC°0

TFL13-GA5358SCIL13GA5358SCIPOSST"eerF-daeL"dael02leer&epat0052C°07otC°0

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

8535AG-31 www.icst.com/products/hiperclocks.html REV. B APRIL 29, 2005

Integrated

Circuit

Systems, Inc.

ICS8535-31

LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

TEEHSYROTSIHNOISIVER

veRelbaTegaPegnahCfonoitpircseDetaD

B6T

ot.xamsp001morftellubwekStraP-ot-traPdetcerro

c-noitceSserutaeF

.xamsp002

ot.xamsp001morfwekStraP-ot-traPdetcerroc-elbaTscitsiretcarahCCA

.xamsp002

50/

92/4