2014-2016 Microchip Technology Inc. DS20005322D-page 1
MCP37231/21-200
MCP37D31/21-200
Features
• Sample Rates:
- 200 Msps for single-channel mode
- 200 Msps/number of channels used
• SNR with fIN = 15 MHz and -1 dBFS:
- 74.7 dBFS (typical) at 200 Msps
• SFDR with fIN = 15 MHz and -1 dBFS:
- 90 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 490 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 436 mW at 200 Msps, Output Clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 390 mW at 200 Msps
• Power-Saving Modes:
- 144 mW during Standby
- 28 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 VP-P
• Input Channel Bandwidth: 500 MHz
• Channel-to-Channel Crosstalk in Multi-Channel
Mode (Input = 15 MHz, -1 dBFS): >95 dB
• Output Data Format:
- Parallel CMOS, DDR LVDS
- Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
• Serial Peripheral Interface (SPI)
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Fractional Delay Recovery (FDR) for time-
delay corrections in multi-channel operations
(dual-/octal-channel modes)
- Phase, Offset and Gain adjust of individual
channels
- Digital Down-Conversion (DDC) with I/Q or
fS/8 output (MCP37D31/21-200)
- Continuous wave beamforming for octal-
channel mode (MCP37D31/21-200)
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• AutoSync Mode to Synchronize Multiple Devices
to the Same Clock
• Package Options:
- VTLA-124 (9 mm x 9 mm x 0.9 mm)
- TFBGA-121 (8 mm x 8 mm x 1.08 mm)
• No External Reference Decoupling Capacitor
Required for TFBGA Package
• Industrial Temperature Range: -40°C to +85°C
Typical Applications
• Communication Instruments
• Cellular Base Stations
• Radar
• Ultrasound and Sonar Imaging
• Scanners and Low-Power Portable Instruments
• Industrial and Consumer Data Acquisition System
MCP372XX/MCP37DXX Family Comparison(1):
Part Number Sample Rate Resolution Digital
Decimation(2)Digital
Down-Conversion(3)CW
Beamforming(4)Noise-Shaping
Requantizer(2)
MCP37231-200 200 Msps 16 Yes No No No
MCP37221-200 200 Msps 14 Yes No No No
MCP37211-200 200 Msps 12 Yes No No Yes
MCP37D31-200 200 Msps 16 Yes Yes Yes No
MCP37D21-200 200 Msps 14 Yes Yes Yes No
MCP37D11-200 200 Msps 12 Yes Yes Yes Yes
Note 1: Devices in the same package type are pin-to-pin compatible.
2: Available in single- and dual-channel mode.
3: Available in single- and dual-channel mode, and octal-channel mode when CW beamforming is enabled.
4: Available in octal-channel mode.
200 Msps, 16-/14-Bit Low-Power ADC with 8-Channel MUX
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 2 2014-2016 Microchip Technology Inc.
Functional Block Diagram
Output Control:
Input Multiplexer
Reference
SENSE
VCM
AIN0+
AIN0-
CLK+
CLK-
Q
OVR
SCLK CS
SDIO
AIN7+
AIN7-
DCLK+
DCLK-
VREF+ VREF-
WCK
Pipelined
PLL
Clock
- Serialized LVDS
Output Clock Control
Internal Registers
ADC
Digital Signal Post-Processing:
- FDR, Decimation
- CMOS, DDR LVDS
REF0-
AVDD12 AVDD18 DVDD18
DVDD12
REF0+
REF1-REF1+
DLL
Duty Cycle
Correction
Selection
- Phase/Offset/Gain Adj.
GND
Generator
VBG
- DDC, CW Beamforming
(MCP37D31/21-200)
[15:0]
SYNC
SLAVE
2014-2016 Microchip Technology Inc. DS20005322D-page 3
MCP37231/21-200 AND MCP37D31/21-200
Description
The MCP37231/21-200 is Microchip's baseline 16-/14-
bit 200 Msps pipelined ADC family, featuring built-in
high-order digital decimation filters, gain and offset
adjustment per channel and fractional delay recovery.
The MCP37D31/21-200 device family features digital
down-conversion and CW beamforming capability, in
addition to the features offered by the MCP37231/21-
200.
All devices feature harmonic distortion correction and
DAC noise cancellation that enable high-performance
specifications with SNR of 74.7 dBFS (typical), and
SFDR of 90 dBc (typical).
These A/D converters exhibit industry-leading low-
power performance with only 490 mW operation while
using the LVDS interface at 200 Msps. This superior
low-power operation coupled with high dynamic
performance makes these devices ideal for various
high-performance, high-speed data acquisition
systems, including communications equipment, radar
and portable instrumentation.
The output decimation filter option improves SNR
performance up to 93.5 dBFS with the 512x decimation
setting. The digital down-conversion option, in
conjunction with the decimation and quadrature output
options, offers great flexibility in digital communication
system design, including cellular base-stations and
narrow-band communications. Gain, phase and DC
offset can be adjusted independently for each input
channel, allowing for simplified implementation of CW
beamforming and ultrasound Doppler imaging
applications.
These devices can have up to eight differential input
channels through an input MUX. The sampling rate is
up to 200 Msps when a single channel is used, or
25 Msps per channel when all eight input channels are
used.
In dual or octal-channel mode, the Fractional Delay
Recovery (FDR) feature digitally corrects the difference
in sampling instance between different channels, so
that all inputs appear to have been sampled at the
same time.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after 28
clock cycles of data latency. Latency will increase if any
of the digital signal post-processing (DSPP) options are
enabled.
AutoSync mode offers a great design flexibility when
multiple devices are used in applications. It allows
multiple devices to sample input synchronously at the
same clock.
The differential full-scale analog input range is
programmable up to 2.975 VP-P
. The ADC output data
can be coded in two's complement or offset binary
representation, with or without the data randomizer
option. The output data is available as full-rate CMOS
or Double-Data-Rate (DDR) LVDS. Additionally, a
serialized LVDS option is also available for the 16-bit
octal-channel mode.
These devices also include various features designed
to maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment
and programmable digital pattern generation. The
device’s operational modes and feature sets are
configured by setting up the user-programmable
registers.
The device is available in Pb-free VTLA-124 and
TFBGA-121 packages. The device operates over the
commercial temperature range of -40°C to +85°C.
Package Types
(a) VTLA-124 Package.
(b) TFBGA-121 Package.
Bottom View
Dimension: 9 mm x 9 mm x 0.9 mm
Bottom View
Dimension: 8 mm x 8 mm x 1.08 mm
Ball Pitch: 0.65 mm
Ball Diameter: 0.4 mm
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 4 2014-2016 Microchip Technology Inc.
NOTES:
2014-2016 Microchip Technology Inc. DS20005322D-page 5
MCP37231/21-200 AND MCP37D31/21-200
1.0 PACKAGE PIN CONFIGURATIONS
AND FUNCTION DESCRIPTIONS
FIGURE 1-1: VTLA-124 Package. See Table 1-1 for the pin descriptions and Table 1-3 for active
and inactive ADC output pins for various ADC resolution modes.
A13
A17
A14
A15
A16
AV
DD18
A
IN6+
CLK-
CLK+
RESET
DCLK+
DCLK-
VTLA-124
(9 mm x 9 mm x 0.9 mm)
A67
A
IN2+
A
IN4+
A
IN0+
A
IN1-
A
IN7-
A
IN3-
A
IN5-
SLAVE
SYNC
CAL
Q4/Q2-
Q5/Q2+
Q6/Q3-
Q7/Q3+
Q8/Q4-
Q9/Q4+
Q10/Q5-
Q11/Q5+
Q12/Q6-
Q13/Q6+
Q15/Q7+
WCK/OVR+
REF0-
REF0- REF0+
REF0+ SENSE
REF1-
REF1-
V
CM
REF1+
REF1+
SDIO
SCLK
CS
NC
V
CMIN
GND
WCK/OVR-
DV
DD18
DV
DD18
AV
DD12
EP
Note 1: Tie to GND or DVDD18. ADR1 is internally bonded to GND.
2: NC – Not connected pins. These pins can float or be tied to ground.
3: Exposed pad (EP – back pad of the package) is the common ground (GND) for analog and digital
supplies. Connect this pad to a clean ground reference on the PCB.
V
BG
A68 A65
A66 A63
A64 A61
A62 A59
A60 A57
A58 A55
A56 A53
A54 A52
A1 B55
B56 B53
B54 B51
B52 B49
B50 B47
B48 B45
B46 B43
B44 B42
A2
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
A19
A18 A21
A20 A23
A22 A25
A24 A27
A26 A30 A33
A32
B15
B14 B17
B16 B19
B18 B21
B20 B22 B24 B27 B28
A34
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A51
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
AV
DD12
ADR0
DV
DD18
AV
DD18
NC
NC
AV
DD18
AV
DD18
AV
DD12
AV
DD12
AV
DD12
A
IN6-
A
IN2-
A
IN4-
A
IN0-
AIN1+
A
IN7+
A
IN3+
A
IN5+
DV
DD12
DV
DD12
DV
DD12
DV
DD18
DV
DD18
(OVR)
(WCK)
DV
DD18
Q14/Q7-
NC GND
Top View
(Not to Scale)
(GND)
A28 A29 A31
B26
Note 3
Note 2
Note 2
Note 1
Note 2
A3
Note 2
B23 B25
DM2/DM-
DM1/DM+
Q0/Q0-
Q3/Q1+
Q1/Q0+ Q2/Q1-
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 6 2014-2016 Microchip Technology Inc.
TABLE 1-1: PIN FUNCTION TABLE FOR VTLA-124
Pin No. Name I/O Type Description
Power Supply Pins
A2, A22, A65, B1,
B52
AVDD18 Supply Supply voltage input (1.8V) for analog section
A12, A56, A60,
A63, B10, B11, B12,
B13, B15, B16,
B45, B49, B53
AVDD12 Supply voltage input (1.2V) for analog section
A25, A30, B39 DVDD12 Supply voltage input (1.2V) for digital section
A41, B24, B27,
B31, B36, B43
DVDD18 Supply voltage input (1.8V) for digital section and all digital I/O
EP GND Exposed pad: Common ground pin for digital and analog sections
ADC Analog Input Pins
A3 AIN6+ Analog
Input
Channel 6 differential analog input (+)
B2 AIN6- Channel 6 differential analog input (-)
A4 AIN2+ Channel 2 differential analog input (+)
B3 AIN2- Channel 2 differential analog input (-)
A5 AIN4+ Channel 4 differential analog input (+)
B4 AIN4- Channel 4 differential analog input (-)
A6 AIN0+ Channel 0 differential analog input (+)
B5 AIN0- Channel 0 differential analog input (-)
B6 AIN1+ Channel 1 differential analog input (+)
A8 AIN1- Channel 1 differential analog input (-)
B7 AIN7+ Channel 7 differential analog input (+)
A9 AIN7- Channel 7 differential analog input (-)
B8 AIN3+ Channel 3 differential analog input (+)
A10 AIN3- Channel 3 differential analog input (-)
B9 AIN5+ Channel 5 differential analog input (+)
A11 AIN5- Channel 5 differential analog input (-)
A21 CLK+ Differential clock input (+)
B17 CLK- Differential clock input (-)
Reference Pins(1)
A57, B46 REF1+ Analog
Output
Differential reference 1 (+) voltage
A58, B47 REF1- Differential reference 1 (-) voltage
A61, B50 REF0+ Differential reference 0 (+) voltage
A62, B51 REF0- Differential reference 0 (-) voltage
SENSE, Bandgap and Common-Mode Voltage Pins
B48 SENSE Analog
Input
Analog input full-scale range selection. See Tab l e 4- 2 for SENSE
voltage settings.
A59 VBG Analog
Output
Internal bandgap output voltage
Connect a decoupling capacitor (2.2 µF)
A7 VCMIN Analog
Input
Common-mode voltage input for auto-calibration
Connect VCM voltage(2)
A55 VCM Common-mode output voltage (900 mV) for analog input signal
Connect a decoupling capacitor (0.1 µF)(3)
2014-2016 Microchip Technology Inc. DS20005322D-page 7
MCP37231/21-200 AND MCP37D31/21-200
Digital I/O Pins
B18 ADR0 Digital Input SPI address selection pin (A0 bit). Tie to GND or DVDD18.(4)
A23 SLAVE Slave or Master selection pin in AutoSync (12).
If not used, tie to GND.
B19 SYNC Digital Input/
Output
Digital synchronization pin for AutoSync (12)
If not used, leave it floating.
B21 RESET Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(5)
A26 CAL Digital
Output
Calibration status flag digital output:
High: Calibration is complete
Low: Calibration is not complete(6)
B22 DCLK+ LVDS: Differential digital clock output (+)
CMOS: Digital clock output(7)
A27 DCLK- LVDS: Differential digital clock output (-)
CMOS: Unused (leave floating)
TABLE 1-1: PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)
Pin No. Name I/O Type Description
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 8 2014-2016 Microchip Technology Inc.
ADC Output Pins(8)
B23 DM2/DM- Digital
Output
18-bit mode: Digital data output (last two LSb bits)(9)
Other modes: Not used
A28 DM1/DM+
A29 Q0/Q0- Digital data output: CMOS = Q0
DDR LVDS = Q0- (Even bit first), Q8- (MSb byte first)
Serialized LVDS = Q- for the last selected channel (n) = 8
B25 Q1/Q0+ Digital data output: CMOS = Q1
DDR LVDS = Q0+ (Even bit first), Q8+ (MSb byte first)
Serialized LVDS = Q+ for the last selected channel (n) = 8
B26 Q2/Q1- Digital data output: CMOS = Q2
DDR LVDS = Q1- (Even bit first), Q9- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 7
A31 Q3/Q1+ Digital data output: CMOS = Q3
DDR LVDS = Q1+ (Even bit first), Q9+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 7
B30 Q4/Q2- Digital data output: CMOS = Q4
DDR LVDS = Q2- (Even bit first), Q10- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 6
A38 Q5/Q2+ Digital data output: CMOS = Q5
DDR LVDS = Q2+ (Even bit first), Q10+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 6
A39 Q6/Q3- Digital data output: CMOS = Q6
DDR LVDS = Q3- (Even bit first), Q11- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 5
B32 Q7/Q3+ Digital data output: CMOS = Q7
DDR LVDS = Q3+ (Even bit first), Q11+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 5
A40 Q8/Q4- Digital data output: CMOS = Q8
DDR LVDS = Q4- (Even bit first), Q12- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 4
B33 Q9/Q4+ Digital data output: CMOS = Q9
DDR LVDS = Q4+ (Even bit first), Q12+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 4
B34 Q10/Q5- Digital data output: CMOS = Q10
DDR LVDS = Q5- (Even bit first), Q13- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 3
TABLE 1-1: PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)
Pin No. Name I/O Type Description
2014-2016 Microchip Technology Inc. DS20005322D-page 9
MCP37231/21-200 AND MCP37D31/21-200
A42 Q11/Q5+ Digital
Output
Digital data output: CMOS = Q11
DDR LVDS = Q5+ (Even bit first), Q13+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 3
B35 Q12/Q6- Digital data output: CMOS = Q12
DDR LVDS = Q6- (Even bit first), Q14- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 2
A43 Q13/Q6+ Digital data output: CMOS = Q13
DDR LVDS = Q6+ (Even bit first), Q14+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 2
A44 Q14/Q7- Digital data output: CMOS = Q14
DDR LVDS = Q7- (Even bit first), Q15- (MSb byte first)
Serialized LVDS = Q- for the first selected channel (n) = 1
B37 Q15/Q7+ Digital data output: CMOS = Q15
DDR LVDS = Q7+ (Even bit first), Q15+ (MSb byte first)
Serialized LVDS = Q+ for the first selected channel (n) = 1
B38 WCK/OVR+
(OVR)
WCK: Word clock sync digital output
OVR: Input overrange indication digital output(11)
A45 WCK/OVR-
(WCK)
SPI Interface Pins
A53 SDIO Digital Input/
Output
SPI data input/output
A54 SCLK Digital
Input
SPI serial clock input
B44 CS SPI Chip Select input
Not Connected Pins
A1, A13 - A20, A32
- A37, A46 - A52,
A66 - A68, B14,
B28, B29, B40,
B41, B42, B55, B56
NC These pins can be tied to ground or left floating.
Pins that need to be grounded
A24, A64, B20, B54 GND These pins are not supply pins, but need to be tied to ground.
TABLE 1-1: PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)
Pin No. Name I/O Type Description
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 10 2014-2016 Microchip Technology Inc.
Notes:
1. These pins are for the internal reference voltage outputs. They should not be driven. External decoupling circuits
are required. See Section 4.5.3, "Decoupling Circuits for Internal Voltage Reference and Bandgap Output"
for details.
2. VCMIN is used for Auto-Calibration only. VCMIN+ and VCMIN- should be tied together always. There should be no
voltage difference between the two pins. Typically both VCMIN+ and VCMIN- are tied to the VCM output pin
together, but they can be tied to another common-mode voltage if external VCM is used. This pin has High Z input
in Shutdown, Standby and Reset modes.
3. When the VCM output is used for the common-mode voltage of analog inputs (i.e. by connecting to the center-
tap of a balun), the VCM pin should be decoupled with a 0.1 µF capacitor, and should be directly tied to the VCMIN+
and VCMIN- pins.
4. ADR1 (for A1 bit) is internally bonded to GND (‘0’). If ADR0 is dynamically controlled, ADR0 must be held
constant while CS is “Low”.
5. The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET, the device exits Reset
mode, initializes all internal user registers to default values, and begins power-up calibration.
6. CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a
soft reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes, this pin will maintain the
prior condition.
7. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing, PLL and/or DLL. See
also Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.
8. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The
even data bits (Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14) appear when DCLK+ is “High”. The odd data bits (Q1, Q3,
Q5, Q7, Q9, Q11, Q13, Q15) appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68
(Register 5-26) for output polarity control. See Figures 2-2 to 2-6 for LVDS output timing diagrams.
9. Available for the MCP37231-200 and MCP37D31-200 devices only.
Leave these pins floating (No Connect) if not used.
10. 18-bit mode: DM1/DM+ and DM2/DM- are the last LSb bits. DM2/DM- is the LSb. In LVDS output, DM1/DM+ and
DM2/DM- are the LSb pair. DM1/DM+ appears at the falling edge and DM2/DM- is at the rising edge of the DCLK+.
Other than 18-bit mode: DM1/DM+ and DM2/DM- are High Z in LVDS mode.
11. CMOS output mode: WCK/OVR- is WCK and WCK/OVR+ is OVR.
DDR LVDS output mode: The rising edge of DCLK+ is WCK and the falling edge is OVR.
OVR: OVR will be held “High” when analog input overrange is detected. Digital signal post-processing will cause
OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: WCK is normally “Low”. WCK is “High” while data from the first channel is sent out. In single-channel
mode, WCK stays “High” except when in I/Q output mode. In serialized LVDS (octal) output mode, the WCK out-
put is asserted “High” on the MSb bit. See Section 4.12.5 “Word Clock (WCK)” for further WCK description.
12. (a) SLAVE = “High”: The device is selected as slave and the SYNC pin becomes input pin.
(b) SLAVE = “Low”: The device is selected as master and the SYNC pin becomes output pin. In SLAVE/SYNC
operation, master and slave devices are synchronized to the same clock.
2014-2016 Microchip Technology Inc. DS20005322D-page 11
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 1-2: TFBGA-121 Package. See Table 1-2 for the pin descriptions and Table 1-3 for active
and inactive ADC output pins for various ADC resolution modes.
Top View
1 2 3 4 5 6 7 8 9 10 11
SDIO V
CM
REF1+ REF1- REF0+ REF0- A
IN4-
A
IN2+
SCLK
WCK/
Q14/Q7-
Q12/Q6-
Q8/Q4-
Q6/Q3-
Q2/Q1-
Q4/Q2-
Q10/Q5-
OVR-
CS
WCK/
Q15/Q7
+
Q13/Q6
+
Q11/Q5
+
Q7/Q3+
Q3/Q1+
Q9/Q4+
Q5/Q2+
OVR+
GND
GND
GND
GND
DV
DD18
DV
DD12
DM1/DM+
DV
DD12
DV
DD18
GND
GND
GND
GND
DV
DD18
DV
DD12
DV
DD12
DV
DD18
DCLK-
SENSE
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD18
AV
DD18
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
CAL GND SLAVE ADR0
GND
GND
GND
GND
GND
GND
GND
ADR1
A
IN4+
A
IN5+
A
IN5-
A
IN6-
A
IN6+
A
IN7-
A
IN7+
V
CMIN
+
GND
A
IN3-
A
IN3+
A
IN1+
A
IN1-
A
IN0+
A
IN0-
A
IN2-
V
CMIN
-
GND
Q0/Q0- Q1/Q0+
DM2/DM-
DCLK+ RESET SYNC GND CLK+ CLK- GND AV
DD18
GND GND
A
B
C
D
E
F
G
H
J
K
L
(Not to Scale)
Analog
Digital
All others: Supply Voltage
V
BG
(WCK) (OVR)
Notes:
• Die dimension: 8 mm x 8 mm x 1.08 mm.
• Ball dimension: (a) Ball Pitch = 0.65 mm, (b) Ball Diameter = 0.4 mm.
• Flip-chip solder ball composition: Sn with Ag 1.8%.
• Solder sphere composition: SAC-405 (Sn/Au 4%/Cu 0.5%).
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 12 2014-2016 Microchip Technology Inc.
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121
Ball No. Name I/O Type Description
A1 SDIO Digital Input/
Output
SPI data input/output
A2 VCM Analog
Output
Common-mode output voltage (900 mV) for analog input signal
Connect a decoupling capacitor (0.1 µF)(1)
A3 REF1+ Differential reference voltage 1 (+/-). Decoupling capacitors are embedded in
the TFBGA package. Leave these pins floating.
A4 REF1-
A5 VBG Internal bandgap output voltage
A decoupling capacitor (2.2 μF) is embedded in the TFBGA package. Leave
this pin floating.
A6 REF0+ Differential reference 0 (+/-) voltage. Decoupling capacitors are embedded in
the TFBGA package. Leave these pins floating.
A7 REF0-
A8 GND Supply Common ground for analog and digital sections
A9
A10 AIN4- Analog Input Channel 4 differential analog input (-)
A11 AIN2+ Channel 2 differential analog input (+)
B1 SCLK Digital Input SPI serial clock input
B2 CS SPI Chip Select input
B3 GND Supply Common ground for analog and digital sections
B4
B5 SENSE Analog
Input
Analog input range selection. See Table 4-2 for SENSE voltage settings.
B6 AVDD12 Supply Supply voltage input (1.2V) for analog section
B7
B8 AVDD18 Supply voltage input (1.8V) for analog section
B9
B10 AIN4+ Analog Input
Channel 4 differential analog input (+)
B11 AIN2- Channel 2 differential analog input (-)
C1 WCK/OVR-
(WCK)
Digital
Output
WCK: Word clock sync digital output
OVR: Input overrange indication digital output(2)
C2
WCK/OVR+
(OVR)
C3 GND Supply Common ground for analog and digital sections
C4
C5 AVDD12 Supply voltage input (1.2V) for analog section
C6
C7
C8 GND Common ground pin for analog and digital sections
C9
C10 AIN6- Analog Input
Channel 6 differential analog input (-)
C11 AIN0+ Channel 0 differential analog input (+)
D1 Q14/Q7- Digital
Output
Digital data output(3)
CMOS = Q14
DDR LVDS = Q7- (Even bit first), Q15- (MSb byte first)
Serialized LVDS = Q- for the first selected channel (n = 1)
D2 Q15/Q7+ Digital data output(3)
CMOS = Q15
DDR LVDS = Q7+ (Even bit first), Q15+ (MSb byte first)
Serialized LVDS = Q+ for the first selected channel (n = 1)
2014-2016 Microchip Technology Inc. DS20005322D-page 13
MCP37231/21-200 AND MCP37D31/21-200
D3 GND Supply Common ground for analog and digital sections
D4
D5 AVDD12 Supply Supply voltage input (1.2V) for analog section
D6
D7
D8 GND Common ground for analog and digital sections
D9
D10 AIN6+ Analog Input
Channel 6 differential analog input (+)
D11 AIN0- Channel 0 differential analog input (-)
E1 Q12/Q6- Digital
Output
Digital data output(3)
CMOS = Q12
DDR LVDS = Q6- (Even bit first), Q14- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 2
E2 Q13/Q6+ Digital data output(3)
CMOS = Q13
DDR LVDS = Q6+ (Even bit first), Q14+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 2
E3 GND Supply Common ground for analog and digital sections
E4
E5 AVDD12 Supply voltage input (1.2V) for analog section
E6
E7
E8 GND Common ground for analog and digital sections
E9
E10 AIN5+ Analog Input
Channel 5 differential analog input (+)
E11 AIN1+ Channel 1 differential analog input (+)
F1 Q10/Q5- Digital
Output
Digital data output(3)
CMOS = Q10
DDR LVDS = Q5- (Even bit first), Q13- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 3
F2 Q11/Q5+ Digital data output(3)
CMOS = Q11
DDR LVDS = Q5+ (Even bit first), Q13+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 3
F3 DVDD18 Supply Supply voltage input (1.8V) for digital section.
All digital input pins are driven by the same DVDD18 potential.
F4
F5 AVDD12 Supply voltage input (1.2V) for analog section
F6
F7
F8 GND Common ground for analog and digital sections
F9
F10 AIN5- Analog Input
Channel 5 differential analog input (-)
F11 AIN1- Channel 1 differential analog input (-)
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No. Name I/O Type Description
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 14 2014-2016 Microchip Technology Inc.
G1 Q8/Q4- Digital
Output
Digital data output(3)
CMOS = Q8
DDR LVDS = Q4- (Even bit first), Q12- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 4
G2 Q9/Q4+ Digital data output(3)
CMOS = Q9
DDR LVDS = Q4+ (Even bit first), Q12+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 4
G3 DVDD18 Supply Supply voltage input (1.8V) for digital section
All digital input pins are driven by the same DVDD18 potential
G4
G5 GND Common ground for analog and digital sections
G6
G7 AVDD12 Supply Supply voltage input (1.2V) for analog section
G8
G9 GND Common ground for analog and digital sections
G10 AIN7- Analog Input
Channel 7 differential analog input (-)
G11 AIN3+ Channel 3 differential analog input (+)
H1 Q6/Q3- Digital
Output
Digital data output(3)
CMOS = Q6
DDR LVDS = Q3- (Even bit first), Q11- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 5
H2 Q7/Q3+ Digital data output(3)
CMOS = Q7
DDR LVDS = Q3+ (Even bit first), Q11+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 5
H3 DVDD12 Supply Supply voltage input (1.2V) for digital section
H4
H5 GND Common ground for analog and digital sections
H6
H7
H8
H9
H10 AIN7+ Analog Input
Channel 7 differential analog input (+)
H11 AIN3- Channel 3 differential analog input (-)
J1 Q4/Q2- Digital
Output
Digital data output(3)
CMOS = Q4
DDR LVDS = Q2- (Even bit first), Q10- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 6
J2 Q5/Q2+ Digital data output(3)
CMOS = Q5
DDR LVDS = Q2+ (Even bit first), Q10+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 6
J3 DVDD12 Supply DC supply voltage input pin for digital section (1.2V)
J4
J5 GND Common ground for analog and digital sections
J6
J7
J8
J9
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No. Name I/O Type Description
2014-2016 Microchip Technology Inc. DS20005322D-page 15
MCP37231/21-200 AND MCP37D31/21-200
J10 VCMIN+Analog Input Common-mode voltage input for auto-calibration(4)
These two pins should be tied together and connected to VCM voltage.
J11 VCMIN-
K1 Q2/Q1- Digital
Output
Digital data output(3)
CMOS = Q2
DDR LVDS = Q1- (Even bit first), Q9- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 7
K2 Q3/Q1+ Digital data output(3)
CMOS = Q3
DDR LVDS = Q1+ (Even bit first), Q9+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 7
K3 DM1/DM+
18-bit mode:
Digital data output. DM1 and DM2 are the last two LSb bits
(5)
Other modes:
Not used
K4 DCLK- LVDS: Differential digital clock output (-)
CMOS: Not used (leave floating)
K5 CAL Digital
Output
Calibration status flag digital output(6)
High: Calibration is complete
Low: Calibration is not complete
K6 GND Supply Common ground pin for analog and digital sections
K7 SLAVE Digital Input Slave or Master selection pin in AutoSync (10). If not used, tie to GND.
K8 ADR0 SPI address selection pin (A0 bit). Tie to GND or DVDD18(7)
K9 ADR1 SPI address selection pin (A1 bit). Tie to GND or DVDD18(7)
K10 GND Supply Common ground for analog and digital sections
K11
L1 Q0/Q0- Digital
Output
Digital data output(3)
CMOS = Q0
DDR LVDS = Q0- (Even bit first), Q8- (MSb byte first)
Serialized LVDS = Q- for the last selected channel (n=8)
L2 Q1/Q0+ Digital data output(8)
CMOS = Q1
DDR LVDS = Q0+ (Even bit first), Q8+ (MSb byte first)
Serialized LVDS = Q+ for the last selected channel (n=8)
L3 DM2/DM-
18-bit mode:
Digital data output. DM1 and DM2 are the last two LSb bits
(
5
)
Other modes:
Not used
L4 DCLK+ LVDS: Differential digital clock output (+)
CMOS: Digital clock output(8)
L5 RESET Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(9)
L6 SYNC Digital Input/
Output
Digital synchronization pin for AutoSync(10)
If not used, leave it floating.
L7 GND Supply Common ground for analog and digital sections
L8 CLK+ Analog Input Differential clock input (+)
L9 CLK- Differential clock input (-)
L10 GND Supply Common ground for analog and digital sections
L11 AVDD18 Analog Input Supply voltage input (1.8V) for analog section
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No. Name I/O Type Description
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 16 2014-2016 Microchip Technology Inc.
Notes:
1. When the VCM output is used for the common-mode voltage of analog inputs (i.e. by connecting to the center-tap of a
balun), the VCM pin should be decoupled with a 0.1 µF capacitor, and should be directly tied to the VCMIN+ and VCMIN- pins.
2. CMOS output mode: WCK/OVR- is WCK and WCK/OVR+ is OVR.
DDR LVDS output mode: The rising edge of DCLK+ is WCK and the falling edge is OVR.
OVR: OVR will be held “High” when analog input overrange is detected. Digital signal post-processing will cause
OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: WCK is normally “Low”. WCK is “High” while data from the first channel is sent out. In single-channel
mode, WCK stays “High” except when in I/Q output mode. In serialized LVDS (octal) output mode, the WCK out-
put is asserted “High” on the MSb bit. See Section 4.12.5 “Word Clock (WCK)” for further WCK description.
3. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The
even data bits (Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14) appear when DCLK+ is “High”. The odd data bits (Q1, Q3,
Q5, Q7, Q9, Q11, Q13, Q15) appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68
(Register 5-26) for output polarity control. See Figures 2-2 to 2-6 for LVDS output timing diagrams.
4. VCMIN is used for Auto-Calibration only. VCMIN+ and VCMIN- should be tied together always. There should be no
voltage difference between the two pins. Typically both VCMIN+ and VCMIN- are tied to the VCM output pin
together, but they can be tied to another common-mode voltage if external VCM is used. This pin has High Z input
in Shutdown, Standby and Reset modes.
5. Available for the MCP37231-200 and MCP37D31-200 devices only.
Leave these pins floating (No Connect) if not used.
18-bit mode: DM1/DM+ and DM2/DM- are the last LSb bits. DM2/DM- is the LSb. In LVDS output, DM1/DM+ and
DM2/DM- are the LSb pair. DM1/DM+ appears at the falling edge and DM2/DM- is at the rising edge of the DCLK+.
Other than 18-bit mode: DM1/DM+ and DM2/DM- are High Z in LVDS mode.
6. CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a
soft reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes, this pin will maintain the
prior condition.
7. If the SPI address is dynamically controlled, the Address pin must be held constant while CS is “Low”.
8. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing, PLL and/or DLL. See
also Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.
9. The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET, the device exits Reset
mode, initializes all internal user registers to default values, and begins power-up calibration.
10. (a) SLAVE = “High”: The device is selected as slave and the SYNC pin becomes input pin.
(b) SLAVE = “Low”: The device is selected as master and the SYNC pin becomes output pin. In SLAVE/SYNC
operation, master and slave devices are synchronized to the same clock.
2014-2016 Microchip Technology Inc. DS20005322D-page 17
MCP37231/21-200 AND MCP37D31/21-200
TABLE 1-3: DATA OUTPUT PINS FOR EACH RESOLUTION OPTION
ADC
Resolution
Output Pin Name
Q15/
Q7+
Q14/
Q7-
Q13/
Q6+
Q12/
Q6-
Q11/
Q5+
Q10/
Q5-
Q9/
Q4+
Q8/
Q4-
Q7/
Q3+
Q6/
Q3-
Q5/
Q2+
Q4/
Q2-
Q3/
Q1+
Q2/
Q1-
Q1/
Q0+
Q0/
Q0-
DM1/
DM+
DM2
/DM-
18-bit mode Q15 pin is MSb (bit 17), and DM2 is LSb (bit 0)
16-bit mode Q15 pin is MSb, and Q0 is LSb Not used
(2)
14-bit mode(1)Q15 pin is MSb, and Q2 is LSb Not used(2)
12-bit mode Q15 pin is MSb, and Q4 is LSb Not used(2)
10-bit mode Q15 pin is MSb, and Q6 is LSb Not used(2)
Note 1: The MCP37221-200 and MCP37D21-200 devices have the 14-bit mode option only, while the MCP37231-
200 and MCP37D31-200 have all listed resolution options.
2: Output condition at “not-used” output pin:
-‘0’ in CMOS mode. Leave these pins floating.
- High Z state in LVDS mode
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 18 2014-2016 Microchip Technology Inc.
2.0 ELECTRICAL SPECIFICATIONS
2.1 Absolute Maximum Ratings†
Analog and digital supply voltage (AVDD12, DVDD12) .............. ......................................................................................... -0.3V to 1.32V
Analog and digital supply voltage (AVDD18, DVDD18) .............. ......................................................................................... -0.3V to 1.98V
All inputs and outputs with respect to GND ............................ ...........................................................................–0.3V to AVDD18 +0.3V
Differential input voltage.......................................................... ....................................................................................... |AVDD18 - GND|
Current at input pins................................................................ ...................................................................................................... ±2 mA
Current at output and supply pins .......................................... .................................................................................................. ±250 mA
Storage temperature ............................................................... ...................................................................................... -65°C to +150°C
Ambient temperature with power applied (TA) ........................ ...................................................................................... -55°C to +125°C
Maximum junction temperature (TJ)........................................ .................................................................................................... +150°C
ESD protection on all pins....................................................... ................................................................................................ 2 kV HBM
Solder reflow profile ................................................................ ................................ See Microchip Application Note AN233 (DS00233)
2.2 Electrical Specifications
Notice†: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 2-1: ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
Power Supply Requirements
Analog Supply Voltage AVDD18 1.71 1.8 1.89 V
AVDD12 1.14 1.2 1.26 V
Digital Supply Voltage DVDD18 1.71 1.8 1.89 V Note 1
DVDD12 1.14 1.2 1.26 V
Analog Supply Current
Analog Supply Current
During Conversion
IDD_A18 —2746mAat AV
DD18 pin
IDD_A12 — 185 252 mA at AVDD12 pin
Digital Supply Current
Digital Supply Current
During Conversion
IDD_D12 — 97 226 mA at DVDD12 pin
Digital I/O Current in
CMOS Output Mode
IDD_D18 —27—mAat DV
DD18 pin
DCLK = 100 MHz
Digital I/O Current in
LVDS Mode
IDD_D18 Measured at DVDD18 Pin
—
55 81 mA 3.5 mA mode
39 — mA 1.8 mA mode
69 5.4 mA mode
Supply Current during Power-Saving Modes
During Standby Mode ISTANDBY_AN — 84 — mA Address 0x00<4:3> = 1,1(2)
ISTANDBY_DIG —36—
During Shutdown Mode IDD_SHDN — 23 — mA Address 0x00<7,0> = 1,1(3)
2014-2016 Microchip Technology Inc. DS20005322D-page 19
MCP37231/21-200 AND MCP37D31/21-200
PLL Circuit
PLL Circuit Current IDD_PLL — 17 — mA PLL enabled. Included in
analog supply current
specification.
Total Power Dissipation(4)
Power Dissipation
During Conversion,
Excluding Digital I/O
PDISS_ADC — 387 — mW
Total Power Dissipation
During Conversion with
CMOS Output Mode
PDISS_CMOS — 436 — mW fS = 200 Msps,
DCLK = 100 MHz
Total Power Dissipation
During Conversion with
LVDS Output Mode
PDISS_LVDS
—
486 — mW 3.5 mA mode
457 — 1.8 mA mode
511 5.4 mA mode
During Standby Mode PDISS_STANDBY — 144 — mW Address 0x00<4:3> = 1,1(2)
During Shutdown Mode PDISS_SHDN —27.6—mW
Address 0x00<7,0> = 1,1(3)
Power-on Reset (POR) Voltage
Threshold Voltage VPOR — 800 — mV Applicable to AVDD12 only
(POR tracks AVDD12)Hysteresis VPOR_HYST —40—mV
SENSE Input(5,7)
SENSE Input Voltage VSENSE GND — AVDD12 V V
SENSE selects reference
SENSE Pin Input
Resistance
RIN_SENSE — 500 — To virtual ground at 0.55V.
400 mV < V
SENSE
<800mV
Current Sink into SENSE
Pin
ISENSE — 4.5 — µA SENSE = 1.2V
636 SENSE = 0.8V
-2 SENSE = 0V
Reference and Common-Mode Voltages
Internal Reference Voltage
(Selected by VSENSE)
VREF —0.74—VV
SENSE = GND
—1.49 — V
SENSE = AVDD12
—
1.86 x V
SENSE
—
400 mV < V
SENSE
<800mV
Common-Mode
Voltage Output
VCM — 0.9 — V Available at VCM pin
Reference Voltage
Output(7,8)
VREF1— 0.4 —VV
SENSE = GND
—0.8— V
SENSE = AVDD12
—0.4 - 0.8—
400 mV < V
SENSE
<800mV
VREF0— 0.7 —VV
SENSE = GND
—1.4— V
SENSE = AVDD12
—0.7 - 1.4—
400 mV < V
SENSE
<800mV
Bandgap Voltage Output VBG — 0.55 — V Available at VBG pin
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 20 2014-2016 Microchip Technology Inc.
Analog Inputs
Full-Scale Differential
Analog Input Range(5,7)
AFS — 1.4875 — VP-P VSENSE = GND
—2.975— V
SENSE = AVDD12
— 3.71875 x
V
SENSE
—
400 mV < V
SENSE
<800mV
Analog Input Bandwidth fIN_3dB — 500 — MHz AIN = -3 dBFS
Differential Input
Capacitance
CIN 567pF
Note 5, Note 9
Analog Input Channel
Cross-Talk
XTALK — 100 — dBc Note 10
Analog Input Leakage
Current (AIN+, AIN- pins)
ILI_AH ——+1µAV
IH = AVDD12
ILI_AL -1 — — µA VIL = GND
ADC Conversion Rate(11)
Conversion Rate fS40 — 200 Msps Tested at 200 Msps
Clock Inputs (CLK+, CLK-)(12)
Clock Input Frequency fCLK ——250MHz
Note 5
Differential Input Voltage VCLK_IN 300 — 800 mVP-P Note 5
Clock Jitter CLKJITTER — 175 — fSRMS Note 5
Clock Input Duty Cycle(5)49 50 51 % Duty cycle correction
disabled
30 50 70 % Duty cycle correction
enabled
Input Leakage Current at
CLK input pin
ILI_CLKH ——+110µAV
IH = AVDD12
ILI_CLKL -20 — — µA VIL = GND
Converter Accuracy(6)
ADC Resolution
(with no missing code)
— — 16 bits MCP37231/MCP37D31
— — 14 bits MCP37221/MCP37D21
Offset Error — ±5 ±61 LSb MCP37231/MCP37D31
— ±1.25 ±15.25 LSb MCP37221/MCP37D21
Gain Error GER —±0.5 —
% of FS
Integral Nonlinearity INL — ±2 — LSb MCP37231/MCP37D31
— ±0.5 — LSb MCP37221/MCP37D21
Differential Nonlinearity DNL — ±0.4 — LSb MCP37231/MCP37D31
— ±0.1 — LSb MCP37221/MCP37D21
Analog Input
Common-Mode
Rejection Ratio
CMRRDC — 70 — dB DC measurement
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
2014-2016 Microchip Technology Inc. DS20005322D-page 21
MCP37231/21-200 AND MCP37D31/21-200
Dynamic Accuracy(6,15)
Spurious Free Dynamic
Range
SFDR 78 90 — dBc fIN = 15 MHz
77 85 — dBc fIN = 70 MHz
Signal-to-Noise Ratio SNR
fIN = 15 MHz
73.3 74.7 — dBFS MCP37231/MCP37D31
— 74.2 — dBFS MCP37221/MCP37D21
SNR
fIN = 70 MHz
— 74.2 — dBFS MCP37231/MCP37D31
— 73.7 — dBFS MCP37221/MCP37D21
Effective Number of Bits
(ENOB)(13)
ENOB
fIN = 15 MHz
— 12.1 — bits MCP37231/MCP37D31
— 12 — bits MCP37221/MCP37D21
ENOB
fIN = 70 MHz
— 12 — bits MCP37231/MCP37D31
— 11.7 — bits MCP37221/MCP37D21
Total Harmonic Distortion
(for all resolutions, first 13
harmonics)
THD 78 89 — dBc fIN = 15 MHz
77 82 — dBc fIN = 70 MHz
Worst Second or
Third Harmonic Distortion
HD2 or HD3 — 90 — dBc fIN = 15 MHz
—83 —dBc
fIN = 70 MHz
Two-Tone Intermodulation
Distortion
fIN1 = 15 MHz,
fIN2 = 17 MHz
IMD — 90.5 — dBc AIN = -7 dBFS,
with two input frequencies
Digital Logic Input and Output (Except LVDS Output)
Schmitt Trigger High-Level
Input Voltage
VIH 0.7 DVDD18 —DVDD18 V
Schmitt Trigger Low-Level
Input Voltage
VIL GND — 0.3 DVDD18 V
Hysteresis of Schmitt
Trigger Inputs
(All digital inputs)
VHYST —
0.05 DV
DD18
—V
Low-Level Output Voltage VOL ——0.3VI
OL = -3 mA, all digital I/O pins
High-Level Output Voltage VOH
DV
DD18
–0.5
1.8 — V IOL = +3 mA, all digital I/O pins
Digital Data Output (CMOS Mode)
Maximum External Load
Capacitance
CLOAD —10 —pF From output pin to GND
Internal I/O Capacitance CINT —4—pF
Note 5
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 22 2014-2016 Microchip Technology Inc.
Notes:
1. This 1.8V digital supply voltage is used for the digital I/O circuit, including SPI, CMOS and LVDS data output drivers.
2. Standby Mode: Most of the internal circuits are turned off, except the internal reference, clock, bias circuits and
SPI interface.
3. Shutdown Mode: All circuits including reference and clock are turned off except the SPI interface.
4. Power dissipation (typical) is calculated by using the following equation:
(a) During operation:
PDISS = VDD18 x (IDD_A18 + IDD_D18) + VDD12 x (IDD_A12 + IDD_D12), where IDD_D18 is the digital I/O current for
LVDS or CMOS output. VDD18 = 1.8V and VDD12 = 1.2V are used for typical value calculation.
(b) During Standby mode:
PDISS_STANDBY = (ISTANDBY_AN + ISTANDBY_DIG) x 1.2V
(c) During Shutdown mode:
PDISS_SHDN = IDD_SHDN x 1.2V
5. This parameter is ensured by design, but not 100% tested in production.
6. This parameter is ensured by characterization, but not 100% tested in production.
7. See Table 4-2 for details.
8. Differential reference voltage output at REF1+/- and REF0+/- pins. VREF1 = VREF1+–V
REF1-.
VREF0 = VREF0+–V
REF0-. These references should not be driven.
9. Input capacitance refers to the effective capacitance between one differential input pin pair.
10. Channel cross-talk is measured when AIN = -1 dBFS at 12 MHz is applied on one channel while other channel(s)
are terminated with 50. See Figure 3-39 for details.
11. The ADC core conversion rate. In multi-channel mode, the conversion rate of an individual channel is fS/N, where
N is the number of input channels used.
12. See Figure 4-8 for the details of the clock input circuit.
13. ENOB = (SINAD - 1.76)/6.02.
14. This leakage current is due to the internal pull-up resistor.
15. Dynamic performance is characterized with CH(n)_DIG_GAIN<7:0> = 0011-1000.
Digital Data Output (LVDS Mode)(5)
LVDS High-Level
Differential Output Voltage
VH_LVDS 200 300 400 mV 100 differential termination,
LVDS bias = 3.5 mA
LVDS Low-Level
Differential Output Voltage
VL_LVDS -400 -300 -200 mV 100 differential termination,
LVDS bias = 3.5 mA
LVDS Common-Mode
Voltage
VCM_LVDS 11.151.4V
Output Capacitance CINT_LVDS — 4 — pF Internal capacitance from
output pin to GND
Differential Load
Resistance (LVDS)
RLVDS — 100 — Across LVDS output pairs
Input Leakage Current on Digital I/O Pins
Data Output Pins ILI_DH ——+1µA
VIH = DVDD18
ILI_DL -1 — — µA VIL = GND
I/O Pins except Data
Output Pins
ILI_DH ——+6µA
VIH = DVDD18
ILI_DL -35 — — µA VIL = GND(14)
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
2014-2016 Microchip Technology Inc. DS20005322D-page 23
MCP37231/21-200 AND MCP37D31/21-200
TABLE 2-2: TIMING REQUIREMENTS - LVDS AND CMOS OUTPUTS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA,
DCLK_PHDLY_DLL<2:0> = 000, +25°C is applied for typical value.
Parameter Symbol Min. Typ. Max. Units Conditions
Aperture Delay tA—1—ns
Note 1
Out-of-Range Recovery Time tOVR —1—Clocks
Note 1
Output Clock Duty Cycle — 50 — % Note 1
Pipeline Latency TLATENCY — 28 — Clocks Note 2, Note 4
System Calibration(1)
Power-Up Calibration Time TPCAL —2
27 —ClocksFirst 2
27 sample clocks after
power-up
Background Calibration Update
Rate
TBCAL —2
30 —ClocksPer 2
30 sample clocks after
TPCAL
RESET Low Time TRESET 5 — — ns See Figure 2-8 for details(1)
AutoSync (1,6)
Sync Output Time Delay TSYNC_OUT —1—Clocks
Maximum Recommended ADC
Clock Rate for AutoSync
— 200 — MHz Single-Channel mode
— 160 — Multi-Channel mode
LVDS Data Output Mode(1,5)
Input Clock to
Output Clock Propagation Delay
tCPD —5.7—ns
Output Clock to
Data Propagation Delay
tDC —0.5—ns
Input Clock to
Output Data Propagation Delay
tPD —5.8—ns
CMOS Data Output Mode(1)
Input Clock to
Output Clock Propagation Delay
tCPD —3.8—ns
Output Clock to
Data Propagation Delay
tDC —0.7—ns
Input Clock to
Output Data Propagation Delay
tPD —4.5—ns
Note 1: This parameter is ensured by design, but not 100% tested in production.
2: This parameter is ensured by characterization, but not 100% tested in production.
3: tRISE = approximately less than 10% of duty cycle.
4: Output latency is measured without using fractional delay recovery (FDR), decimation filter or digital
down-converter options.
5: The time delay can be adjusted with the DCLK_PHDLY_DLL<2:0> setting.
6: Characterized with a single slave device. The maximum ADC sample rate for AutoSync mode may be
reduced if multiple slave devices are used.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 24 2014-2016 Microchip Technology Inc.
FIGURE 2-1: Timing Diagram - CMOS Output.
FIGURE 2-2: Timing Diagram - LVDS Output with Even Bit First Option.
CLK-
CLK+
Input Clock:
DCLK
Digital Clock Output:
Q<N:0>
Output Data:
OVR
Over-Range Output:
S-L-1 S-L S-L+1 S-1 S
S-L-1 S-L S-L+1 S-1 S
S-1
SS+1 S+L
S+L-1
t
A
Latency = L Cycles
tCPD
t
DC
t
PD
Input Signal:
*S = Sample Point
Note: If the output resolution is selected for less than 16-bit, unused bits are ‘0’s.
CLK-
CLK+
Input Clock:
Digital Clock Output:
Output Data:
Word-CLK/
Over-Range Output:
S-1
S
S+1 S+L
S+L-1
tA
Latency = L Cycles
tCPD
tDC
tPD
DCLK-
DCLK+
Q-[N:0]
Q+[N:0]
WCK/OVR-
WCK/OVR+
EVEN
S-L
ODD
S-L
EVEN
S-L-1
ODD
S-L-1
EVEN
S-L+1
EVEN
S
EVEN
S-1
ODD
S-1
WCK
S-L
OVR
S-L
WCK
S-L-1
OVR
S-L-1
WCK
S-L+1
WCK
S
WCK
S-1
OVR
S-1
Input Signal:
*S = Sample Point
Note: If the output resolution is selected for less than 16-bit, unused bits are High Z.
2014-2016 Microchip Technology Inc. DS20005322D-page 25
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 2-3: Timing Diagram - LVDS Output with MSb Byte First Option. This output option is
available for 16-bit mode only.
CLK-
CLK+
S-1
S
S+1 S+L
S+L-1
tA
Latency = L Cycles
tCPD
tDC
tPD
DCLK-
DCLK+
Q-[N:0]
Q+[N:0]
WCK/OVR-
WCK/OVR+
b[15:8]
S-L
b[7:0]
S-L
b[15:8]
S-L-1
b[7:0]
S-L-1
b[15:8]
S-L+1
b[15:8]
S
b[15:8]
S-1
b[7:0]
S-1
WCK
S-L
OVR
S-L
WCK
S-L-1
OVR
S-L-1
WCK
S-L+1
WCK
S
WCK
S-1
OVR
S-1
Input Clock:
CLK Output:
Output Data:
Word-CLK/
Over-Range Output:
Input Signal:
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 26 2014-2016 Microchip Technology Inc.
FIGURE 2-4: Timing Diagram - L VDS Serial Output in Octal-Channel Mode. This output is available
for octal-channel with 16-bit mode only. Note that although the eight input channels are sampled
sequentially (auto-scan with 1 cycle separation), all channels are output simultaneously with the MSb (bit
15) synchronized with the rising edge of WCK.
CLK Output:
Input Clock:
Word-CLK/
Over-Range Output:
Ch.0
Ch.1
Ch.0
Ch.7
t
A
Latency = L Cycles
t
CPD
t
DC
t
PD
DCLK-
DCLK+
Q-[0]
Q+[0]
WCK/OVR-
WCK/OVR+
b[15]
Ch.0
b[14]
Ch.0
b[1]
Ch.0
b[0]
Ch.0
b[13]
Ch.0
b[15]
Ch.0
b[1]
Ch.0
b[0]
Ch.0
WCK
“1”OVROVR WCK
“1”
OVR
Q-[7]
Q+[7]
b[15]
Ch.7
b[14]
Ch.7
b[1]
Ch.7
b[0]
Ch.7
b[13]
Ch.7
b[15]
Ch.7
b[1]
Ch.7
b[0]
Ch.7
Q-[1]
Q+[1]
b[15]
Ch.1
b[14]
Ch.1
b[1]
Ch.1
b[0]
Ch.1
b[13]
Ch.1
b[15]
Ch.1
b[1]
Ch.1
b[0]
Ch.1
Ch.7
“0”“0”“0”
CLK-
CLK+
Output Data:
Input Signal:
Note: Q+/Q-[7] is the first channel selected data, and Q+/Q-[0] is the last channel selected data.
2014-2016 Microchip Technology Inc. DS20005322D-page 27
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 2-5: SPI Serial Input Timing Diagram.
FIGURE 2-6: SPI Serial Output Timing Diagram.
TABLE 2-3: SPI SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value. All timings are measured at 50%.
Parameters Symbol Min. Typ. Max. Units Conditions
Serial Clock frequency, fSCK = 50 MHz
CS Setup Time tCSS 10 — — ns
CS Hold Time tCSH 20 — — ns
CS Disable Time tCSD 20 — — ns
Data Setup Time tSU 2——ns
Data Hold Time tHD 4——ns
Serial Clock High Time tHI 8——ns
Serial Clock Low Time tLO 8——ns
Note 1
Serial Clock Delay Time tCLD 20 — — ns
Serial Clock Enable Time tCLE 20 — — ns
Output Valid from SCK Low tDO — — 20 ns
Output Disable Time tDIS — — 10 ns Note 1
Note 1: This parameter is ensured by design, but not 100% tested.
CS
SCLK
SDIO LSb in
MSb in
tCSS
tSU tHD
tCSD
tCSH tCLD
tCLE
tHI tLO
tSCK
(SDI)
tCSH
tDIS
tHI tLO
tSCK
CS
SCLK
SDIO MSb out LSb out
tDO
(SDO)
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 28 2014-2016 Microchip Technology Inc.
FIGURE 2-7: POR-Related Events: Register Initialization and Power-Up Calibration.
FIGURE 2-8: RESET Pin Timing Diagram.
FIGURE 2-9: Sync Timing Diagram with Power-On Reset.
AVDD12
Power-on Reset (POR)
227 cycles
(TPCAL)
Power-Up calibration complete.
• Registers are initialized
• Device is ready for correct conversion
RESET Pin
tRESET
Stop ADC conversion
and ADC recalibration
Power-Up Calibration Time
Start register initialization
(TPCAL)
Recalibration complete:
•CAL Pin: High
•ADC_CAL_STAT = 1
POR (Power-On Reset)
(~ 220 clock cycles)
SYNC Output
CAL Pin (Output)
Data Output
Clock Input
Valid Data
A. Master Device
Toggle to High at the 2nd rising edge of Clock Input
TPCAL
SYNC Input
CAL Pin (Output)
Data Output
Clock Input
B. Slave Device(s)
TPCAL
(SLAVE Pin = 1)
(SLAVE Pin = 0)
Valid Data
Invalid Data
Invalid Data
12
12
TSYNC_OUT
2014-2016 Microchip Technology Inc. DS20005322D-page 29
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 2-10: Sync Timing Diagram with RESET Pin Operation.
FIGURE 2-11: Sync Timing Diagram with SOFT_RESET Bit Setting.
RESET Pin
SYNC Output
CAL Pin (Output)
Data Output
Clock Input
A. Master Device
TPCAL
SYNC Input
CAL Pin (Output)
Data Output
Clock Input
B. Slave Device(s)
TPCAL
(SLAVE Pin = 1)
(SLAVE Pin = 0)
TSYNC_OUT
Valid Data
Valid Data
Invalid Data
Invalid Data
12
POR
(~ 2
20
clock cycles)
SYNC Output
CAL Pin (Output)
Data Output
Clock Input
Vali d Data
A. Master Device (SLAVE Pin = 0)
Toggle to High at the 2nd rising edge of Clock Input after POR
T
PCAL
SYNC Input
CAL Pin (Output)
Data Output
Clock Input
B. Slave Device(s)
T
PCAL
(SLAVE Pin = 1)
Valid Data
Invalid
SOFT_RESET = 0 SOFT_RESET = 1
Invalid Data
122
1
SPI SOFT RESET Control
Invalid Data
122
1
Toggle to High at the 2nd rising edge of Clock Input
after SOFT_RESET = 1
T
SYNC_O
UT
No Output
No Output
T
PCAL
T
PCAL
Data
Valid
Data
Invalid
Data
Vali d
Data
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 30 2014-2016 Microchip Technology Inc.
TABLE 2-4: TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges(1)
Operating Temperature Range TA-40 — +85 °C
Thermal Package Resistances(2)
121L Ball-TFBGA
(8 mm x 8 mm)
Junction-to-Ambient Thermal Resistance JA —40.2—°C/W
Junction-to-Case Thermal Resistance JC —8.4—°C/W
124L – VTLA
(9 mm x 9 mm)
Junction-to-Ambient Thermal Resistance JA —21—°C/W
Junction-to-Case (top) Thermal Resistance JC —8.7—°C/W
Note 1: Maximum allowed power-dissipation (PDMAX) = (TJMAX - TA)/JA.
2: This parameter value is achieved by package simulations.
2014-2016 Microchip Technology Inc. DS20005322D-page 31
MCP37231/21-200 AND MCP37D31/21-200
NOTES:
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 32 2014-2016 Microchip Technology Inc.
3.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DV
DD18 =1.8V, AV
DD12 =DV
DD12 =1.2V, GND=0V,
SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS, fIN =70MHz, Clock
Input = 200 MHz, fS= 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation filters are disabled.
FIGURE 3-1: FFT for 14.7 MHz Input
Signal: fS = 200 Msps/Ch., AIN = -1 dBFS.
FIGURE 3-2: FFT for 69.5 MHz Input
Signal: f S = 200 Msps/Ch., AIN = -1 dBFS.
FIGURE 3-3: FFT for 149 MHz Input
Signal: f S = 200 Msps/Ch., AIN = -1 dBFS.
FIGURE 3-4: FFT for 14.7 MHz Input
Signal: fS = 200 Msp s/Ch., AIN = -4 dBFS.
FIGURE 3-5: FFT for 69.5 MHz Input
Signal: fS = 200 Msp s/Ch., AIN = -4 dBFS.
FIGURE 3-6: FFT for 149 MHz Input
Signal: fS = 200 Msp s/Ch., AIN = -4 dBFS.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
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2014-2016 Microchip Technology Inc. DS20005322D-page 33
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 3-7: FFT for 14.7 MHz Input
Signal: f S = 100 Msps/Ch., Dual, AIN = -1 dBFS.
FIGURE 3-8: FFT for 14.7 MHz Input
Signal: f S = 50 Msps/Ch., Quad, AIN = -1 dBFS.
FIGURE 3-9: FFT for 3.8 MHz Input
Signal: f S = 25 Msps/Ch., Octal, AIN = -1 dBFS.
FIGURE 3-10: FFT for 14.7 MHz Input
Signal: fS = 100 Msps/Ch., Dual, AIN = -4 dBFS.
FIGURE 3-11: FFT for 14.7 MHz Input
Signal: fS = 50 Msps/Ch., Quad, AIN = -4 dBFS.
FIGURE 3-12: FFT for 3.8 MHz Input
Signal: fS = 25 Msps/Ch., Octal, AIN = -4 dBFS.
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MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 34 2014-2016 Microchip Technology Inc.
FIGURE 3-13: FFT for 14.7 MHz Input
Signal: f S = 25 Msps/Ch., Octal, AIN = -1 dBFS .
FIGURE 3-14: Two-Tone FFT:
fIN1 = 17.6 MHz and fIN2 =20.6MHz,
AIN = -7 dBFS per Tone, fS=200Msps.
FIGURE 3-15: FFT for 14.7 MHz Input
Signal: fS = 25 Msps/Ch., Octal, AIN = -4 dBFS.
FIGURE 3-16: SNR/SFDR vs. Input
Frequency.
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2014-2016 Microchip Technology Inc. DS20005322D-page 35
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 3-17: SNR/SFDR vs. Analog Input
Amplitud e: f S=200Msps, f
IN =70MHz.
FIGURE 3-18: SNR/SFDR vs. Sample
Rate (Msps): fIN = 70 MHz.
FIGURE 3-19: SNR/SFDR vs. SENSE Pin
Voltage: fS = 200 Msps, fIN = 68 MHz.
FIGURE 3-20: SNR/SFDR vs. Analog Input
Amplitu de: f S = 200 Msps, fIN = 15 MHz.
FIGURE 3-21: SNR/SFDR vs. Sample
Rate (Msps): fIN = 15 MHz.
FIGURE 3-22: SNR/SFDR vs. SENSE Pin
Voltage: fS = 200 Msps, fIN = 15 MHz.
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MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 36 2014-2016 Microchip Technology Inc.
FIGURE 3-23: SNR/SFDR vs. VCM Voltage
(Externally Applied): fS = 200 Msps,
fIN =15MHz.
FIGURE 3-24: SNR/SFDR vs.Temperature:
fS = 200 Msps, fIN = 15 MHz.
FIGURE 3-25: SNR/SFDR vs. Supply
Voltage: fS = 200 Msps, fIN = 15 MHz.
FIGURE 3-26: HD2/HD3 vs. Supply
Voltage: fS = 200 Msps, fIN = 15 MHz.
FIGURE 3-27: VREF0 Vs. Temperature.
FIGURE 3-28: Gain and Offset Error Drifts
Vs. Temperature Using Internal Reference, with
Respect to 25°C: fS = 200 Msps.
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2014-2016 Microchip Technology Inc. DS20005322D-page 37
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 3-29: INL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 16-bit Mode .
FIGURE 3-30: INL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 14-bit Mode .
FIGURE 3-31: INL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz,12-bit Mode.
FIGURE 3-32: DNL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 16-bit Mode.
FIGURE 3-33: DNL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 14-bit Mode.
FIGURE 3-34: DNL Error Vs. Output Code:
fS = 200 Msps, fIN = 4 MHz, 12-bit Mode.
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MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 38 2014-2016 Microchip Technology Inc.
FIGURE 3-35: Shorted Input Histogr am :
fS= 200 Msps, Resolution = 16-Bit Shorted
Input.
FIGURE 3-36: Shorted Input Histogr am :
fS= 200 Msps, Resolution = 14-Bit.
FIGURE 3-37: Shorted Input Histogram:
fS= 200 Msps, Resolution = 12-bit.
FIGURE 3-38: Input Bandwidth.
FIGURE 3-39: Input Channel Cross-Talk.
FIGURE 3-40: Power Consumption vs.
Sampling Frequency (LVDS Mode).
-20-15-10-505101520
Output Code
Occurences
160k
140k
120k
100k
80k
60k
40k
20k
0
Resolution = 16-Bit
f
S
= 200 Msps
-20-15-10-505101520
Output Code
Occurrences
500k
400k
300k
200k
100k
0
Resolution = 14-Bit
fS= 200 Msps
-20-15-10-505101520
Output Code
Occurrences
1.5M
1.0M
500k
0
Resolution = 12-Bit
fS= 200 Msps
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0
40
80
120
160
200
240
Current (mA)
Sampling Frequency (MHz)
I
DD_A12
I
DD_A18
I
DD_D12
I
DD_D18
Total Power for ADC Core
(except LVDS I/O)
AIN = -1 dBFS
050 100 150 200 250
00
250
300
350
400
450
500
Power (mW)
2014-2016 Microchip Technology Inc. DS20005322D-page 39
MCP37231/21-200 AND MCP37D31/21-200
4.0 THEORY OF OPERATION
The MCP37231/21-200 and MCP37D31/21-200
device family is a low-power, 16-/14-bit, 200 Msps
Analog-to-Digital Converter (ADC) with built-in features
including Harmonic Distortion Correction (HDC), DAC
Noise Cancellation (DNC), Dynamic Element Matching
(DEM) and flash error calibration.
Depending on the product number selection, the device
offers various built-in digital signal post-processing
features, such as FIR decimation filters, Digital Down-
Conversion (DDC), Fractional Delay Recovery (FDR),
continuous CW beamforming and digital gain and
offset correction. These built-in advanced digital signal
post-processing sub-blocks, which are individually
controlled, can be used for various special applications
such as I/Q demodulation, digital down-conversion,
and ultrasound imaging.
When the device is first powered-up, it performs inter-
nal calibrations by itself and runs with default settings.
From this point, the user can configure the device reg-
isters using the SPI command.
In multi-channel mode, the input channel selection and
MUX scan order are user-configurable, and the inputs
are sequentially multiplexed by the input MUX defined
by the scan order.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after
28 clock cycles of data latency. Latency will increase if
any of the various digital signal post-processing
(DSPP) options are enabled.
The output data can be coded in two’s complement or off-
set binary format, and randomized using the user option.
Data can be output using either the CMOS or LVDS (Low-
Voltage Differential Signaling) interface. Serialized LVDS
output is also available in 16-bit octal-channel mode. In
this mode, each input channel is output serially over a
unique LVDS pair.
4.1 ADC Core Architecture
Figure 4-1 shows the simplified block diagram of the
ADC core. The first stage consists of a 17-level flash
ADC, multi-level Digital-to-Analog Converter (DAC)
and a residue amplifier with a gain of 8. Stages 2 to 6
consist of a 9-level (3-bit) flash ADC, multi-level DAC
and a residue amplifier with a gain of 4. The last stage
is a 9-level 3-bit flash ADC. Dither is added in each of
the first three stages.The digital outputs from all seven
stages are combined in a digital error correction logic
block and digitally processed for the final output.
The first three stages include patented digital
calibration features:
• Harmonic Distortion Correction (HDC) algorithm
that digitally measures and cancels ADC errors
arising from distortions introduced by the residue
amplifiers
• DAC Noise Cancellation (DNC) algorithm that
corrects DAC’s nonlinearity errors
• Dynamic Element Matching (DEM) which
randomizes DAC errors, thereby converting
harmonic distortion to white noise
These digital correction algorithms are first applied
during the Power-on Reset sequence and then operate
in the background during normal operation of the
pipelined ADC. These algorithms automatically track
and correct any environmental changes in the ADC.
More details of the system correction algorithms are
shown in Section 4.13 “System Calibration”.
FIGURE 4-1: ADC Core Block Diagram.
Clock Generation
Pipeline
(3-bit)
Stage 1
Pipeline
(2-bit)
Stage 2
Pipeline
(2-bit)
Stage 3
Pipeline
(2-bit)
Stage 4
Pipeline
(2-bit)
Stage 5
Pipeline
Stage 6
3-bit Flash
(3-bit)
Stage 7
Digital Error Correction
MUX
Input
AIN0+
AIN0-
HDC1, DNC1 HDC2, DNC2 HDC3, DNC3
(2-bit)
AIN7+
AIN7 -
User-Programmable Options Programmable Digital Signal Post-Processing (DSPP)
Reference Generator
REF0 REF1 REF1 REF1 REF1 REF1 REF1
REF0
REF1
16-Bit Digital Output
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 40 2014-2016 Microchip Technology Inc.
4.2 Supply Voltage (DVDD, AVDD, GND)
The device operates from two sets of supplies and a
common ground:
• Digital Supplies (DVDD) for the digital section:
1.8V and 1.2V
• Analog Supplies (AVDD) for the analog section:
1.8V and 1.2V
• Ground (GND): Common ground for both digital
and analog sections.
The supply pins require an appropriate bypass
capacitor (ceramic) to attenuate the high-frequency
noise present in most application environments. The
ground pins provide the current return path. These
ground pins must connect to the ground plane of the
PCB through a low-impedance connection. A ferrite
bead can be used to separate analog and digital supply
lines if a common power supply is used for both analog
and digital sections.
The voltage regulators for each supply need to have
sufficient output current capabilities to support a stable
ADC operation.
4.3 Input Sample Rate
In single-channel mode, the device samples the input
at full speed. In multi-channel mode, the core ADC is
multiplexed between the selected channels. The result-
ing effective sample rate per channel is shown in
Equation 4-1.
For example, with 200 Msps operation, the input is
sampled at the full 200 Msps rate if a single channel is
used, or at 25 Msps per channel if all eight channels
are used.
EQUATION 4-1: SAMPLE RATE PER
CHANNEL
4.4 Analog Input Channel Selection
The analog input is auto-multiplexed sequentially as
defined by the channel-order selection bit setting. The
user can configure the input MUX using the following
registers:
• SEL_NCH<2:0> in Address 0x01 (Register 5-2):
Select the total number of input channels to be
used.
• Addresses 0x7D – 0x7F (Registers 5-37–5-39):
Select auto-scan channel order.
The user can select up to eight input channels. If all
eight input channels are to be used, SEL_NCH<2:0> is
set to 000 and the input channel sampling order is set
using Addresses 0x7D – 0x7F (Registers 5-37–5-39).
Regardless of how many channels are selected, all
eight channels must be programmed in Addresses
0x7D – 0x7F (Registers 5-37–5-39) without duplica-
tion. Program the addresses of the selected channels
in sequential order, followed by the unused channels.
The order of the unused channels has no effect. The
device samples the first N-Channels listed in
Addresses 0x7D – 0x7F (Registers 5-37–5-39)
sequentially, where N is the total number of channels to
be used, defined by the SEL_NCH<2:0>. Table 4-1
shows examples of input channel selection using
Addresses 0x7D – 0x7F (Registers 5-37–5-39).
Sample Rate/Channel Full ADC Sample Rate fs
Number of Channel Used
---------------------------------------------------------------------=
TABLE 4-1: EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
No. of
Channels
(1)
Selected
Channels
Channel
Order(2)Address 0x7F Address 0x7E Address 0x7D
b
7
b
0
b
7
b
0
b
7
b
0
8
Channel Order Bit Settings
5th Ch. 4th Ch. 6th Ch. 3rd Ch. 7th Ch. 2nd Ch. 8th Ch. 1st Ch.
[0 1 2 3 4 5 6 7] [0 1 2 3 4 5 6 7]
(Default)
100011101010110001111000
[7 6 5 4 3 2 1 0] [7 6 5 4 3 2 1 0] 011100010101001110000111
[0 2 4 6 1 3 5 7] [0 2 4 6 1 3 5 7] 001110011100101010111000
[1 3 5 7 0 2 4 6] [1 3 5 7 0 2 4 6] 000111010101100011110001
7
Channel Order Bit Settings
Unused 4th Ch. 5th Ch. 3rd Ch. 6th Ch. 2nd Ch. 7th Ch. 1st Ch.
[0 1 2 3 4 5 6] [0 1 2 3 4 5 6 7] 111011100010101001110000
[0 2 4 6 1 3 5] [0 2 4 6 1 3 5 7] 111110001100011010101000
Note 1: Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
2: Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.
2014-2016 Microchip Technology Inc. DS20005322D-page 41
MCP37231/21-200 AND MCP37D31/21-200
6
Channel Order Bit Settings
Unused Unused 4th Ch. 3rd Ch. 5th Ch. 2nd Ch. 6th Ch. 1st Ch.
[0 1 2 3 4 5] [0 1 2 3 4 5 6 7] 111110011010100001101000
[0 2 4 6 1 3] [0 2 4 6 1 3 5 7] 111101110100001010011000
5
Channel Order Bit Settings
Unused Unused Unused 3rd Ch. 4th Ch. 2nd Ch. 5th Ch. 1st Ch.
[0 1 2 3 4] [0 1 2 3 4 5 6 7] 110101111010011001100000
[0 2 4 6 1] [0 2 4 6 1 3 5 7] 101011111100110010001000
4
Channel Order Bit Settings
Unused Unused Unused Unused 3rd Ch. 2nd Ch. 4th Ch. 1st Ch.
[0 1 2 3 ] [0 1 2 3 4 5 6 7] 110101111100010001011000
[4 5 6 7] [4 5 6 7 0 1 2 3] 010001011000110101111100
[0 2 4 6] [0 2 4 6 1 3 5 7] 101011111001100010110000
[1 3 5 7] [1 3 5 7 0 2 4 6] 100010110000101011111001
3
Channel Order Bit Settings
Unused Unused Unused Unused Unused 2nd Ch. 3rd Ch. 1st Ch.
[0 1 2] [0 1 2 3 4 5 6 7] 101100110011111001010000
[0 2 4] [0 2 4 6 1 3 5 7] 011001101110111010100000
2
Channel Order Bit Settings
Unused Unused Unused Unused Unused Unused 2nd Ch. 1st Ch.
[0 1] [0 1 2 3 4 5 6 7] 101100110011111010001000
[2 3] [2 3 0 1 4 5 6 7] 101100110001111000011010
[4 5] [4 5 0 1 2 3 6 7] 011010110001101000101100
[6 7] [6 7 0 1 2 3 4 5] 011010100001101000111110
1
Channel Order Bit Settings
Unused Unused Unused Unused Unused Unused Unused 1st Ch.
[0] [0 1 2 3 4 5 6 7] 100011101010110001111000
[1] [1 0 2 3 4 5 6 7] 100011101010110000111001
[2] [2 0 1 3 4 5 6 7] 100011101001110000111010
[3] [3 0 1 2 4 5 6 7] 100010101001110000111011
[4] [4 0 1 2 3 5 6 7] 011010101001110000111100
[5] [5 0 1 2 3 4 6 7] 011010100001110000111101
[6] [6 0 1 2 3 4 5 7] 011010100001101000111110
[7] [7 0 1 2 3 4 5 6] 011010100001101000110111
TABLE 4-1: EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
No. of
Channels
(1)
Selected
Channels
Channel
Order(2)Address 0x7F Address 0x7E Address 0x7D
b
7
b
0
b
7
b
0
b
7
b
0
Note 1: Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
2: Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 42 2014-2016 Microchip Technology Inc.
4.5 Analog Input Circuit
The analog input (AIN) of all MCP37XXX devices is a
differential, CMOS switched capacitor sam-
ple-and-hold circuit. Figure 4-2 shows the equivalent
input structure of the device.
The input impedance of the device is mostly governed
by the input sampling capacitor (CS= 6 pF) and input
sampling frequency (fS). The performance of the
device can be affected by the input signal conditioning
network (see Figure 4-3). The analog input signal
source must have sufficiently low output impedance to
charge the sampling capacitors (CS= 6 pF) within one
clock cycle. A small external resistor (e.g., 5Ω) in series
with each input is recommended, as it helps reduce
transient currents and dampens ringing behavior. A
small differential shunt capacitor at the chip side of the
resistors may be used to provide dynamic charging
currents and may improve performance. The resistors
form a low-pass filter with the capacitor and their values
must be determined by application requirements and
input frequency.
The VCM pin provides a common-mode voltage
reference (0.9V), which can be used for a center-tap
voltage of an RF transformer or balun. If the VCM pin
voltage is not used, the user may create a common-
mode voltage at mid-supply level (AVDD18/2).
FIGURE 4-2: Equivalent Input Circuit.
4.5.1 ANALOG INPUT DRIVING CIRCUIT
4.5.1.1 Differential Input Configuration
The device achieves optimum performance when the
input is driven differentially, where common-mode
noise immunity and even-order harmonic rejection are
significantly improved. If the input is single-ended, it
must be converted to a differential signal in order to
properly drive the ADC input. The differential
conversion and common-mode application can be
accomplished by using an RF transformer or balun with
a center-tap. Additionally, one or more anti-aliasing
filters may be added for optimal noise performance and
should be tuned such that the corner frequency is
appropriate for the system.
Figure 4-3 shows an example of the differential input
circuit with transformer. Note that the input-driving
circuits are terminated by 50 near the ADC side
through a pair of 25 resistors from each input to the
common-mode (VCM) from the device. The RF
transformer must be carefully selected to avoid
artificially high harmonic distortion. The transformer
can be damaged if a strong RF input is applied or an RF
input is applied while the MCP37XXX is powered-off.
The transformer has to be selected to handle sufficient
RF input power.
Figure 4-4 shows an input configuration example when
a differential output amplifier is used.
FIGURE 4-3: Transformer Coupled Input
Configuration.
FIGURE 4-4: DC-Coupled Input
Configuration with Preamplifier: the external
signal conditioning circuit and associated
component values are for reference only.
Typical ly, th e amplifier manufacturer prov ides
reference circuits and component values.
AIN+
AIN-
VCM
CS=6pF
50
3pF
AVDD18
AVDD18
Sample Hold
Hold
CS=6pF
Sample
50
3pF
MCP37XXX
AIN+
AIN-
VCM
3.3 pF
50
50
5
5
0.1 µF
25
25
Analog
0.1 µF
1
1
3
6
41
6
43
MABAES0060
Input
MCP37XXX
MABAES0060
AIN+
AIN-
Analog 6.8 pF
High-Speed 100
100
VCM
50
Differential
Amplifier
0.1 µF
CM
+
-
MCP37XXX
Input
2014-2016 Microchip Technology Inc. DS20005322D-page 43
MCP37231/21-200 AND MCP37D31/21-200
4.5.1.2 Single-Ended Input Configuration
Figure 4-5 shows an example of a single-ended input
configuration. This single-ended input configuration is
not recommended for the best performance. SNR and
SFDR performance degrades significantly when the
device is operated in a single-ended configuration. The
unused negative side of the input should be
AC-coupled to ground using a capacitor.
FIGURE 4-5: Singled-Ended Input
Configuration.
4.5.2 SENSE VOLTAGE AND INPUT
FULL-SCALE RANGE
The device has a bandgap-based differential internal
reference voltage. The SENSE pin voltage is used to
select the reference voltage source and configure the
input full-scale range. A comparator detects the
SENSE pin voltage and configures the full-scale input
range into one of the three possible modes which are
summarized in Tab le 4- 2. Figure 4-6 shows an
example of how the SENSE pin should be driven.
The SENSE pin can sink or source currents as high as
500 µA across all operational conditions. Therefore, it
may require a driver circuit, unless the SENSE
reference source provides sufficient output current.
FIGURE 4-6: SENSE Pin Voltage Setup.
A
IN
+
A
IN
-
R
VCM
1kAnalog
50
10 µF
0.1 µF
0.1 µF
10 µF 0.1 µF
1k
VCM
R
C
MCP37XXX
Input
Note 1: This voltage buffer can be removed if the SENSE
reference is coming from a stable source (such as
MCP1700) which can provide a sufficient output
current to the SENSE pin.
SENSE
0.1 µF
R1
R2
MCP1700
0.1 µF
MCP37XXX
(Note 1)
TABLE 4-2: SENSE PIN VOLTAGE AND INPUT FULL-SCALE RANGE
SENSE Pin
Voltage
(VSENSE)
Selected
Reference Voltage
(VREF)
Full-Scale Input Voltage
Range (AFS)
LSb Size
(Calculated with AFS)Condition
Tied to GND 0.7V 1.4875 VP-P(1)16-bit mode: 22.7 µV Low-Reference
Mode(4)
14-bit mode: 90.8 µV
0.4V – 0.8V 0.7V – 1.4V 1.4875 VP-P to 2.975 VP-P(2)Adjustable Sense Mode(5)
Tied to AVDD12 1.4V 2.975 VP-P(3)16-bit mode: 45.4 µV High-Reference
Mode(4)
14-bit mode: 181.6 µV
Note 1: AFS = (17/16) x 1.4 VP-P =1.487V
P-P
.
2: AFS = (17/16) x 2.8 VP-P x(V
SENSE)/0.8 = 1.4875 VP-P to 2.975 VP-P
.
3: AFS = (17/16) x 2.8 VP-P =2.975V
P-P
.
4: Based on internal bandgap voltage.
5: Based on VSENSE.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 44 2014-2016 Microchip Technology Inc.
4.5.2.1 SENSE Selection Vs. SNR/SFDR
Performance
The SENSE pin is used to configure the full-scale input
range of the ADC. Depending on the application
conditions, the SNR, SFDR and dynamic range
performance are affected by the SENSE pin
configuration. Tab l e 4-3 summarizes these settings.
• High-Reference Mode
This mode is enabled by setting the SENSE pin to
AVDD12 (1.2V). This mode provides the highest input
full-scale range (2.975 VP-P) and the highest SNR
performance. Figure 3-17 and Figure 3-20 show
SNR/SFDR versus input amplitude in High-Reference
mode.
• Low-Reference Mode
This mode is enabled by setting the SENSE pin to
ground. This mode is suitable for applications which have
a smaller input full-scale range. This mode provides
improved SFDR characteristics, but SNR is reduced by
-6 dB compared to the High-Reference Mode.
• SENSE Mode
This mode is enabled by driving the SENSE pin with an
external voltage source between 0.4V and 0.8V. This
mode allows the user to adjust the input full-scale
range such that SNR and dynamic range are optimized
in a given application system environment.
TABLE 4-3: SENSE VS. SNR/SFDR PERFORMANCE
SENSE Descriptions
High-Reference Mode
(SENSE pin = AVDD12)
High-input full-scale range (2.975 VP-P) and optimized SNR
Low-Reference Mode
(SENSE pin = ground)
Low-input full-scale range (1.4875 VP-P) and reduced SNR, but optimized SFDR
Sense Mode
(SENSE pin = 0.4V to 0.8V)
Adjustable-input full-scale range (1.4875 VP-P - 2.975 VP-P). Dynamic trade-off
between High-Reference and Low-Reference modes can be used.
2014-2016 Microchip Technology Inc. DS20005322D-page 45
MCP37231/21-200 AND MCP37D31/21-200
4.5.3 DECOUPLING CIRCUITS FOR
INTERNAL VOLTAGE REFERENCE
AND BANDGAP OUTPUT
4.5.3.1 Decoupling Circuits for REF1 and
REF0 Pins
The device has two internal voltage references, and
these references are available at pins REF0 and REF1.
REF0 is the internal voltage reference for the ADC
input stage, while REF1 is for all remaining stages.
VTLA-124 Package Device: Figure 4-7 shows the
recommended circuit for the REF1 and REF0 pins for
the VTLA-124 package. Placing a 2.2 µF ceramic
capacitor with two additional optional capacitors (22 nF
and 220 nF) between the positive and negative
reference pins is recommended. The negative
reference pin is then grounded through a 220 nF
capacitor. The capacitors should be placed as close to
the ADC as possible with short and thick traces. Vias
on the PCB are not recommended for this reference pin
circuit.
TFBGA-121 Package Device: The decoupling capac-
itor is embedded in the package. Therefore, no external
circuit is required on the PCB.
4.5.3.2 Decoupling Circuit for VBG Pin
The bandgap circuit is a part of the reference circuit and
the output is available at the VBG pin.
VTLA-124 Package Device: V
BG pin needs an
external decoupling capacitor (2.2 µF) as shown in
Figure 4-7.
TFBGA-121 Package Device: The decoupling capac-
itor is embedded in the package. Therefore, no external
circuit is required on the PCB.
FIGURE 4-7: External Circuit for Voltage
Reference and VBG pins for the VTLA-124
Package. Note that this external circuit is not
required for the TFBGA-121 package.
4.6 External Clock Input
For optimum performance, the MCP37XXX requires a
low-jitter differential clock input at the CLK+ and CLK−
pins. Figure 4-8 shows the equivalent clock input
circuit.
FIGURE 4-8: Equivalent Clock Input
Circuit.
The clock input amplitude range is between 300 mVP-P
and 800 mVP-P
. When a single-ended clock source is
used, an RF transformer or balun can be used to
convert the clock into a differential signal for the best
ADC performance. Figure 4-9 shows an example clock
input circuit. The common-mode voltage is internally
generated and a center-tap is not required. The
back-to-back Schottky diodes across the transformer’s
secondary current limit the clock amplitude to
approximately 0.8 VP-P differential. This limiter helps
prevent large voltage swings of the input clock while
preserving the high slew rate that is critical for low jitter.
FIGURE 4-9: Transformer-Coupled
Differential Clock Input Configuration.
REF1+ REF1-
2.2 µF
22 nF
220 nF
220 nF
REF0+ REF0-
2.2 µF
22 nF
220nF
2.2 µF
VBG
220 nF
(optional)
CLK+
CLK-
2pF
300
AVDD12
AVDD12
300
12 k
Clock
Buffer
100 fF
100 fF
~300 fF
AVDD12
MCP37XXX
~300 fF
CLK+
CLK-
0.1 µF
Clock
50Schottky
(HSMS-2812)
61
43
WBC1-1TL
Coilcraft
MCP37XXX
Diodes
Source
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 46 2014-2016 Microchip Technology Inc.
4.6.1 CLOCK JITTER AND SNR
PERFORMANCE
In a high-speed pipelined ADC, the SNR performance
is directly limited by thermal noise and clock jitter.
Thermal noise is independent of input clock and
dominant term at low-input frequency. On the other
hand, the clock jitter becomes a dominant term as input
frequency increases. Equation 4-2 shows the SNR
jitter component, which is expressed in terms of the
input frequency (fIN) and the total amount of clock jitter
(TJitter), where TJitter is a sum of the following two
components:
• Input clock jitter (phase noise)
• Internal aperture jitter (due to noise of the clock
input buffer).
EQUATION 4-2: SNR VS.CLOCK JITTER
The clock jitter can be minimized by using a high-qual-
ity clock source and jitter cleaners as well as a band-
pass filter at the external clock input, while a faster
clock slew rate improves the ADC aperture jitter.
With a fixed amount of clock jitter, the SNR degrades
as the input frequency increases. This is illustrated in
Figure 4-10. If the input frequency increases from
10 MHz to 20 MHz, the maximum achievable SNR
degrades about 6 dB. For every decade (e.g. 10 MHz
to 100 MHz), the maximum achievable SNR due to
clock jitter is reduced by 20 dB.
FIGURE 4-10: SNR vs. Clock Jitter.
SNRJitter dBc 20 log10
–2
f
IN T
Jitter
=
where the total jitter term (Tjitter) is given by:
TJitter tJitter Clock Input,
2tAperture ADC,
2
+=
0
20
40
60
80
100
120
140
160
1 10 100 1000
SNR (dBc)
Input Frequency (fIN, MHz)
Jitter = 1
p
s
Jitter = 0.5 ps
Jitter = 0.25 ps
Jitter = 0.125 ps
Jitter = 0.0625 ps
2014-2016 Microchip Technology Inc. DS20005322D-page 47
MCP37231/21-200 AND MCP37D31/21-200
4.7 ADC Clock Selection
This section describes the ADC clock selection and
how to use the built-in Delay-Locked Loop (DLL) and
Phase-Locked Loop (PLL) blocks.
When the device is first powered-up, the external clock
input (CLK+/-) is directly used for the ADC timing as
default. After this point, the user can enable the DLL or
PLL circuit by setting the register bits. Figure 4-11
shows the clock control blocks. Tab le 4- 4 shows an
example of how to select the ADC clock depending on
the operating conditions.
TABLE 4-4: ADC CLOCK SELECTION (EXAMPLE)
Operating Conditions Control Bit Settings(1)
Features
Input Clock Duty
Cycle Correction
DCLK Output Phase
Delay Control
CLK_SOURCE = 0 (Default)(2)
• DLL output is not used
• Decimation is not used
(Default)(3)
EN_DLL = 0
EN_DLL_DCLK = 0
EN_PHDLY = 0
Not Available Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 0
Available
• DLL output is used
• Decimation is not used
EN_DLL = 1
EN_DLL_DCLK = 1
EN_PHDLY = 1
Available Available
• DLL output is not used
• Decimation is used(4)
EN_DLL = 0
EN_DLL_DCLK = X
EN_PHDLY = 1
Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 1
Available
CLK_SOURCE = 1(5)
• Decimation is not used EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 0
Not Available Available
• Decimation is used(4)EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 1
Note 1: See Addresses 0x52, 0x53, and 0x64 for bit settings.
2: The sampling frequency (fS) of the ADC core comes directly from the input clock buffer
3: Output data is synchronized with the output data clock (DCLK), which comes directly from the input clock buffer.
4: While using decimation, output clock rate and phase delay are controlled by the digital clock output control block
5: The sampling frequency (fS) is generated by the PLL circuit. The external clock input is used as the reference input
clock for the PLL block.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 48 2014-2016 Microchip Technology Inc.
FIGURE 4-11: Timing Clock Control Blocks.
VCO
Phase/Freq.
Detector (3rd Order) Output/Div
PLL_PRE<11:0>
PLL_REFDIV<9:0>
Current
PLL_OUTDIV<3:0>
PLL Block
Input Clock Buffer
EN_DUTY
C1: PLL_CAP1<4:0>
PLL_CHAGPUMP<3:0>
Loop Filter Control
C2: PLL_CAP2<4:0>
C3: PLL_CAP3<4:0>
R1: PLL_RES<4:0>
Loop Filter
(80 MHz - 250 MHz)
PLL Output Control Block
Pump
C3C2
R1
C1
Loop Filter Control Parameters:
fVCO
See Address 0x54 - 0x5D for Control Parameters
See Address 0x55 and 0x6D
÷N
÷R
if CLK_SOURCE = 1
Charge
Clock Input (fCLK): < 250 MHz
fREF
Duty Cycle Correction (DCC)
fS
EN_DLL
Phase Delay
DCLK_PHDLY_DLL<2:0>
DCLK
fS
EN_CLK
DLL Block
fQ
EN_PLL_CLK
DCLK Delay
DCLK_DLY_PLL<2:0>
for control parameters
if CLK_SOURCE = 0
Note: VCO output range is 1.075 GHz – 1.325 GHz by setting PLL_REFDIV<10:0> and PLL_PRE<11:0>, with fREF = 5 MHz - 250 MHz range.
fVCO N
R
----f
REF
1.075 1.325–GHz==
EN_PLL_REFDIV
Digital Output
Clock Phase Delay Control
Clock Rate Control
Digital Output
Digital Clock Output Control Block
DCLK
if digital decimation is used
OUT_CLKRATE<3:0>
RESET_DLL
EN_DLL_DCLK
DCLK_PHDLY_DEC<2:0>
EN_PHDLY
DCLK
See Address 0x64 and 0x02
for control parameters
See Address 0x52 and 0x64<7> for details
if digital decimation is used
See Address 0x7A, 0x7B, 0x7C, and 0x81
(5 MHz to 250 MHz)
(when decimation filter is used)
EN_PLL EN_PLL_BIAS
EN_PLL_OUT
EN_DLL = 0
EN_DLL_DCLK = 0
See Address 0x7A, 0x7B, 0x7C, and 0x81
EN_PHDLY
DLL Circuit
DCLK
2014-2016 Microchip Technology Inc. DS20005322D-page 49
MCP37231/21-200 AND MCP37D31/21-200
4.7.1 USING DLL MODE
Using the DLL block is the best option when output
clock phase control is needed while the clock multipli-
cation and digital decimation are not required. When
the DLL block is enabled, the user can control the input
clock Duty Cycle Correction (DCC) and the output
clock phase delay.
See the DLL block in Figure 4-11 for details. Table 4-5
summarizes the DLL control register bits. In addition,
see Tabl e 4-21 for the output clock phase control.
4.7.1.1 Input Clock Duty Cycle Correction
The ADC performance is sensitive to the clock duty
cycle. The ADC achieves optimum performance with
50% duty cycle, and all performance characteristics are
ensured when the duty cycle is 50% with ±1%
tolerance.
When CLK_SOURCE = 0, the external clock is used
as the sampling frequency (fS) of the ADC core. When
the external input clock is not high-quality (for example,
duty cycle is not 50%), the user can enable the internal
clock duty cycle correction circuit by setting the
EN_DUTY bit in Address 0x52 (Register 5-7). When
duty cycle correction is enabled (EN_DUTY=1), only
the falling edge of the clock signal is modified (rising
edge is unaffected).
Because the duty cycle correction process adds addi-
tional jitter noise to the clock signal, this option is rec-
ommended only when an asymmetrical input clock
source causes significant performance degradation or
when the input clock source is not stable.
4.7.1.2 DLL Block Reset Event
The DLL must be reset if the clock frequency is
changed. The DLL reset is controlled by using the
RESET_DLL bit in Address 0x52 (Register 5-7). The
DLL has an automatic reset with the following events:
• During power-up: Stay in reset until the
RESET_DLL bit is cleared.
• When a SOFT_RESET command is issued while
the DLL is enabled: the RESET_DLL bit is
automatically cleared after reset.
4.7.2 USING PLL MODE
The PLL block is mainly used when clock multiplication
is needed. When CLK_SOURCE = 1, the sampling
frequency (fS) of the ADC core is coming from the
internal PLL block.
The recommended PLL output clock range is from
80 MHz to 250 MHz. The external clock input is used
as the PLL reference frequency. The range of the clock
input frequency is from 5 MHz to 250 MHz.
4.7.2.1 PLL Output Frequency and Output
Control Parameters
The internal PLL can provide a stable timing output
ranging from 80 MHz to 250 MHz. Figure 4-11 shows the
PLL block using a charge-pump-based integer N PLL
TABLE 4-5: DLL CONTROL REGISTER BITS
Control Parameter Register Descriptions
CLK_SOURCE 0x53 CLK_SOURCE = 0: external clock input becomes input of the DLL block
EN_DUTY 0x52 Input clock duty cycle correction control bit(1)
EN_DLL 0x52 EN_DLL = 1: enable DLL block
EN_DLL_DCLK 0x52 DLL output clock enable bit
EN_PHDLY<2:0> 0x52 Phase delay control bits of digital output clock (DCLK) when DLL or
decimation filter is used(2)
RESET_DLL 0x52 Reset control bit for the DLL block
Note 1: Duty cycle correction is not recommended when a high-quality external clock is used.
2: If decimation is used, the output clock phase delay is controlled using DCLK_PHDLY_DEC<2:0> in
Address 0x64.
Note: The clock duty cycle correction is only
applicable when the DLL block is enabled
(EN_DLL = 1). It is not applicable for the PLL
output.
Note: The PLL mode is only supported for
sampling frequencies between 80 MHz
and 250 MHz.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 50 2014-2016 Microchip Technology Inc.
and the PLL output control block. The PLL block
includes various user control parameters for the desired
output frequency. Table 4-6 summarizes the PLL control
register bits and Tab le 4- 7 shows an example of register
bit settings for the PLL charge pump and loop filter.
The PLL block consists of:
• Reference Frequency Divider (R)
• Prescaler - which is a feedback divider (N)
• Phase/Frequency Detector (PFD)
• Current Charge Pump
• Loop Filter - a 3rd order RC low-pass filter
• Voltage-Controlled Oscillator (VCO)
The external clock at the CLK+ and CLK- pins is the
input frequency to the PLL. The range of input fre-
quency (fREF) is from 5 MHz to 250 MHz. This input
frequency is divided by the reference frequency
divider (R) which is controlled by the 10-bit-wide
PLL_REFDIV<9:0> setting. In the feedback loop, the
VCO frequency is divided by the prescaler (N) using
PLL_PRE<11:0>.
The ADC core sampling frequency (fS), ranging from
80 MHz to 250 MHz, is obtained after the output
frequency divider (PLL_OUTDIV<3:0>). For stable
operation, the user needs to configure the PLL with
the following limits:
The charge pump is controlled by the PFD, and forces
sink (DOWN) or source (UP) current pulses onto the
loop filter. The charge pump bias current is controlled
by the PLL_CHAGPUMP<3:0> bits, approximately
25 µA per step. The loop filter consists of a 3rd order
passive RC filter. Table 4-7 shows the recommended
settings of the charge pump and loop filter parameters,
depending on the charge pump input frequency range
(output of the reference frequency divider).
When the PLL is locked, it tracks the input frequency
(fREF) with the ratio of dividers (N/R). The PLL operat-
ing status is monitored by the PLL status indication bits:
<PLL_VCOL_STAT> and <PLL_VCOH_STAT> in
Address 0xD1 (Register 5-80).
Equation 4-3 shows the VCO output frequency (fVCO) as
a function of the two dividers and reference frequency:
EQUATION 4-3: VCO OUTPUT
FREQUENCY
See Addresses 0x54 to 0x57 (Registers 5-9 – 5-12) for
these bits settings.
The tuning range of the VCO is 1.075 GHz to
1.325 GHz. N and R values must be chosen so the
VCO is within this range. In general, lower values of the
VCO frequency (fVCO) and higher values of the charge
pump frequency (fQ) should be chosen to optimize the
clock jitter. Once the VCO output frequency is deter-
mined to be within this range, set the final ADC sam-
pling frequency (fS) with the PLL output divider using
PLL_OUTDIV<3:0>. Equation 4-4 shows how to obtain
the ADC core sampling frequency:
EQUATION 4-4: SAMPLING FREQUENCY
Tabl e 4- 8 shows an example of generating
fS= 200 MHz output using the PLL control parameters.
4.7.2.2 PLL Calibration
The PLL should be recalibrated following a change in
clock input frequency or in the PLL Configuration
register bit settings (Addresses 0x54 - 0x57;
Registers 5-9 – 5-12).
The PLL can be calibrated by toggling the PLL_-
CAL_TRIG bit in Address 0x6B (Register 5-27) or by
sending a SOFT_RESET command (See Address
0x00, Register 5-1). The PLL calibration status is
observed by the PLL_CAL_STAT bit in Address 0xD1
(Register 5-80).
4.7.2.3 Monitoring of PLL Drifts
The PLL drifts can be monitored using the status mon-
itoring bits in Address 0xD1 (Register 5-80). Under
normal operation, the PLL maintains a lock across all
temperature ranges. It is not necessary to actively
monitor the PLL unless extreme variations in the sup-
ply voltage are expected or if the input reference clock
frequency has been changed.
• Input clock frequency (fREF) = 5 MHz to 250 MHz
• Charge pump input frequency
(after PLL reference divider)
= 4 MHz to 50 MHz
• VCO output frequency = 1.075 to1.325 GHz
• PLL output frequency after
output divider
= 80 MHz to 250 MHz
fVCO N
R
----
fREF 1.075 GHz t o 1.325 G H z==
Where:
N = 1 to 4095 controlled by PLL_PRE<11:0>
R = 1 to 1023 controlled by PLL_REFDIV<9:0>
fSfVCO
PLL_OUTDIV
--------------------------------------
80 MHz to 250 MHz==
2014-2016 Microchip Technology Inc. DS20005322D-page 51
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-6: PLL CONTROL REGISTER BITS
Control Parameter Register Descriptions
PLL Global Control Bits
EN_PLL 0x59 Master enable bit for the PLL circuit
EN_PLL_OUT 0x5F Master enable bit for the PLL output
EN_PLL_BIAS 0x5F Master enable bit for the PLL bias
EN_PLL_REFDIV 0x59 Master enable bit for the PLL reference divider
PLL Block Setting Bits
PLL_REFDIV<9:0> 0x54-0x55 PLL reference divider (R) (See Tab l e 4-8)
PLL_PRE<11:0> 0x56-0x57 PLL prescaler (N) (See Tabl e 4-8 )
PLL_CHAGPUMP<3:0> 0x58 PLL charge pump bias current control: from 25 µA to 375 µA, 25 µA per step
PLL_RES<4:0> 0x5A PLL loop filter resistor value selection (See Table 4-7)
PLL_CAP3<4:0> 0x5B PLL loop filter capacitor 3 value selection (See Ta b l e 4 - 7 )
PLL_CAP2<4:0> 0x5D PLL loop filter capacitor 2 value selection (See Ta b l e 4 - 7 )
PLL_CAP1<4:0> 0x5C PLL loop filter capacitor 1 value selection (See Ta b l e 4 - 7 )
PLL Output Control Bits
PLL_OUTDIV<3:0> 0x55 PLL output divider (See Tabl e 4-8)
DCLK_DLY_PLL<2:0> 0x6D Delay DCLK output up to 15 cycles of VCO clocks
EN_PLL_CLK 0x6D EN_PLL_CLK = 1 enable PLL output clock to the ADC circuits
PLL Drift Monitoring Bits
PLL_VCOL_STAT 0xD1 PLL drift status monitoring bit
PLL_VCOH_STAT 0xD1 PLL drift status monitoring bit
PLL Block Calibration Bits
PLL_CAL_TRIG 0x6B Forcing recalibration of the PLL
SOFT_RESET 0x00 PLL is calibrated when exiting soft reset mode
PLL_CAL_STAT 0xD1 PLL auto-calibration status indication
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 52 2014-2016 Microchip Technology Inc.
TABLE 4-7: RECOMMENDED PLL CHARGE PUMP AND LOOP FILTER BIT SETTINGS
PLL Charge Pump and Loop Filter
Parameter
fQ=f
REF/PLL_REFDIV
fQ<5 MHz 5 MHz ≤fQ<25MHz f
Q ≥ 25 MHz
PLL_CHAGPUMP<3:0> 0x04 0x04 0x04
PLL_RES<4:0> 0x1F 0x1F 0x07
PLL_CAP3<4:0> 0x07 0x02 0x07
PLL_CAP2<4:0> 0x07 0x01 0x08
PLL_CAP1<4:0> 0x07 0x01 0x08
TABLE 4-8: EXAMPLE OF PLL CONTROL BIT SETTINGS FOR fS = 200 MHz WITH fREF = 100 MHz
PLL Control Parameter Value Descriptions
fREF 100 MHZfREF is coming from the external clock input
Ta r ge t fS(1)200 MHZ ADC sampling frequency
Ta r ge t fVCO(2)1.2 GHZRange of fVCO = 1.0375 GHz – 1.325 GHz
Ta r ge t fQ(3)10 MHZfQ = fREF/PLL_REFDIV (See Ta bl e 4 - 7 )
PLL Reference Divider (R) 10 PLL_REFDIV<9:0> = 0x0A
PLL Prescaler (N) 120 PLL_PRE<11:0> = 0x78
PLL Output Divider 6 PLL_OUTDIV<3:0> = 0x06
Note 1: fS=f
VCO/PLL_OUTDIV = 1.2 GHz/6 = 200 MHz
2: fVCO = (N/R) x fREF = (12) x 100 MHz = 1.2 GHz
3: fQ should be maximized for the best noise performance.
2014-2016 Microchip Technology Inc. DS20005322D-page 53
MCP37231/21-200 AND MCP37D31/21-200
4.8 Digital Signal Post-Processing
(DSPP) Options
While the device converts the analog input signals to
digital output codes, the user can enable various digital
signal post-processing (DSPP) options for special
applications. These options are individually enabled or
disabled by setting the Configuration bits. Table 4-9
summarizes the digital signal post-processing (DSPP)
options that are available for each device family.
4.8.1 FRACTIONAL DELAY RECOVERY
FOR DUAL- AND OCTAL-CHANNEL
MODES
The FDR feature is available in dual and octal-channel
modes only. When FDR is enabled, the built-in high-
order, band-limited interpolation filter compensates for
the time delay between input samples of different
channels. Due to the finite bandwidth of the
interpolation filter, the fractional delay recovery is not
guaranteed for input frequencies near the Nyquist
frequency (fS/2). For example, in dual-channel mode,
FDR can operate correctly for input frequencies in the
range from 0 to 0.45*fS (or from 0.55*fs to fS if the input
is in the 2nd Nyquist band). In octal-channel mode,
FDR can operate correctly for input frequencies in the
range from 0 to 0.38*fS. See Table 4-11 for the
summary of the input bandwidth requirement for FDR.
The FDR process takes place in the digital domain and
requires 59 clock cycles of processing time. Therefore,
the output data latency is also increased by 59 clock
periods.
Figure 4-12 shows the simplified block diagram for the
ADC output data path with FDR. The related
Configuration register bits are listed in Tabl e 4-10 .
Table 4-11 shows the input bandwidth limits of the FDR
feature for distortion less than 0.1 mdB (0.1 × 10-3 dB),
where fS is the sampling frequency per channel.
Figures 4-13 and 4-14 show the responses of the dual-
channel and octal-channel FDRs, respectively.
FIGURE 4-12: Simplified Block Diagram for
ADC Output Data Path with Fractional Delay
Recovery Option. Note that Fractional Delay
Recovery occurs prior to other DSPP features.
TABLE 4-9: DIGITAL SIGNAL POST PROCESSING (DSPP) OPTIONS
Digital Signal Post Processing Option Available Operating Mode Offering Device
Fractional Delay Recovery (FDR) Dual and octal-channel modes
MCP37231/21-200
MCP37D31/21-200
FIR Decimation Filters Single and dual-channel modes
CW octal-channel mode
DDC for I and Q data
Digital Gain and Offset correction per channel Available for all channels
Digital-Down Conversion (DDC) Single and dual-channel modes
CW octal-channel mode MCP37D31/21-200
Continuous Wave (CW) Beamforming CW octal-channel mode
Fractional Delay
Recovery
(FDR)
ADC Output for
dual- or octal-channel
FDR Control
ADC data after
sampling time delay between
channels is removed
FIR
Decimation Filters
Digital
Down-Conversion (DDC)
CW
Beamforming
(MCP37D31/21-200)
(MCP37D31/21-200)
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 54 2014-2016 Microchip Technology Inc.
FIGURE 4-13: Response of the Dual-
Channel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.
FIGURE 4-14: Response of the Octal-
Channel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.
TABLE 4-10: CONTROL PARAMETERS FOR FRACTIONAL DELAY RECOVERY (FDR)
Channel Operation Control Parameter Register Descriptions
Global control for both
dual and octal-channel
modes
EN_FDR = 10x7A Enable FDR features
FDR_BAND 0x81 Select 1st or 2nd Nyquist band
Dual-channel SEL_FDR = 00x81 Select FDR for dual-channel mode
EN_DSPP_8 = 00x81 Select digital signal post-processing feature for
dual-channel mode
EN_DSPP_2 = 10x79 Enable all digital post-processing functions for
dual-channel operation
Octal-channel SEL_FDR = 10x81 Select FDR for octal-channel mode
EN_DSPP_8 = 10x81 Select digital signal post-processing feature for
octal-channel operation
TABLE 4-11: INPUT BANDWIDTH
REQUIREMENT FOR FDR
Bandwidth
in percentage
of fS(1)
Nyquist Band (2)
Dual-Channel Mode
0–45% 1
st Nyquist Band (FDR_BAND = 0)
55 – 100% 2nd Nyquist Band (FDR_BAND = 1)
45 – 55% Avoid
Octal-Channel Mode
0–38% 1
st Nyquist Band (FDR_BAND = 0)
Note 1: fs is sampling frequency per channel.
Distortion is less than 0.1 mdB.
2: See Address 0x81 for FDR_BAND bit
setting
0f
S/2 fS
Frequency
0f
S/2 fS
Interpolation Filter Frequency Response
In-Band Ripple
0.0005
0
-0.0005
0
-30
-60
-90
-120
Amplitude (dBc)
In-Band Ripple
0f
S/2 fS2×fS3×fS4×fS
Frequency
0f
S/2 fS2×fS3×fS4×fS
Frequency
0.0005
0
-0.0005
0
-30
-60
-90
-120
Amplitude (dBc)
2014-2016 Microchip Technology Inc. DS20005322D-page 55
MCP37231/21-200 AND MCP37D31/21-200
4.8.2 DECIMATION FILTERS
The decimation feature is available in single and dual-
channel modes and CW octal-channel mode.
Figure 4-15 shows a simplified decimation filter block,
and Tabl e 4- 13 shows the register settings. The
decimation rate is controlled by FIR_A<8:0> and
FIR_B<7:0> register settings (Addresses 0x7A –
0x7C: Registers 5-34 - ). These registers are
thermometer encoded.
In single-channel mode, FIR B is disabled and only
FIR A is used. In this mode, the maximum program-
mable decimation rate is 512x using nine cascaded
decimation stages.
In dual-channel mode or when using the Digital Down-
Conversion (DDC) in I/Q mode, both FIR A and FIR B
are used (see Figure 4-15). In this case, both channels
are set to the same decimation rate. Note that stage
1A in FIR A is unused: the user must clear FIR_A<0>
in Address 0x7A (Register 5-34). In dual-channel
mode, the maximum programmable decimation rate is
up to 256x, which is half the single-channel decimation
rate (512x).
The overall SNR performance can be improved with
higher decimation rate. In theory, 3 dB improvement is
expected with each successive stage of decimation
(2x per stage), but the actual improvement is approxi-
mately 2.5 dB per stage due to finite attenuation in the
FIR filters.
When using a high decimation rate option (128x or
above) in 16-bit mode, the user may consider enabling
two additional LSb output bits using the DM1DM2 bit
setting in Address 0x68 (Register 5-26). This results in
18-bit resolution. The recommended decimation rates
for adding these two additional bits are 128x or above.
This option is available for 16-bit devices only
(MCP37231-200 and MCP37D31-200).
Table 4-12 summarizes the decimation rate versus
SNR performance in 16-bit and 18-bit output modes.
The results indicate that the SNR is marginally
improved with higher decimation rates. Therefore, the
user may benefit from the 18-bit output mode when a
high decimation rate is used. When a low decimation
rate is used, there is no benefit to SNR or SFDR per-
formance although the 18-bit output is enabled.
Table 4-13 summarizes the related control parameters
for using decimation filters.
TABLE 4-12: DECIMATION RATE VS. SNR
PERFORMANCE
Decimation
Rate
SNR (dBFS)
16-Bit Output
Mode
18-Bit Output
Mode(1)
1x 74.5 74.5
2x 76.7 76.7
4x 79.5 79.5
8x 82.3 82.3
16x 84.8 84.8
32x 87.1 87.4
64x 89.2 89.7
128x 91.0 91.8
256x 92.0 93.2
512x 92.3 93.5
Note 1: DM1DM2 bit is enabled.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 56 2014-2016 Microchip Technology Inc.
4.8.2.1 Output Data Rate and Clock Phase
Control When Decimation is Used
When decimation is used, it also reduces the output
clock rate and output bandwidth by a factor equal to
the decimation rate applied: the output clock rate is
therefore no longer equal to the ADC sampling clock.
The user needs to adjust the output clock and data
rates in Address 0x02 (Register 5-3) based on the
decimation applied. This allows the output data to be
synchronized to the output data clock.
Phase shifts in the output clock can be achieved using
DCLK_PHDLY_DEC<2:0> in Address 0x64
(Register 5-22). Only four output sampling phases are
available when a decimation rate of 2x is used, while
all eight clock phases are available for other
decimation rates. See Section 4.12.9 “Output Data
and Clock Rates” for more details.
4.8.2.2 Using Decimation with CW
Beamforming and Digital Down-
Conversion
Decimation can be used in conjunction with CW octal-
channel mode or DDC. In CW octal-channel mode
operation, the eight input channels are summed into a
single channel prior to entering the decimation filters.
When DDC is enabled, the I and Q outputs can be
decimated using the same signal path for the dual-
channel mode: I and Q data are fed into Channel A
and B, respectively.
In DDC mode, the half-band filter already includes a
2x decimation rate. Therefore, the maximum
decimation rate setting for I/Q filtering is 128x for the
FIR_A<8:1> and FIR_B<7:0>. See Section 4.8.3
“Digital Down-Conversion (MCP37D31/21-200
only)” for details.
Note: Fractional Delay Recovery, Digital
Gain/Offset adjustment and DDC for I/Q
data options occur prior to the decimation
filters if they are enabled.
2014-2016 Microchip Technology Inc. DS20005322D-page 57
MCP37231/21-200 AND MCP37D31/21-200
I
FIGURE 4-15: Simplified Block Diagram of Decimation Filters.
TABLE 4-13: REGISTER CONTROL PARAMETERS FOR USING DECIMATION FILTERS
Control Parameter Register Descriptions
Decimation Filter Settings
FIR_A<8:0> 0x7A, 0x7B Channel A FIR configuration for single- or dual-channel mode
FIR_B<7:0> 0x7C Channel B FIR configuration for single- or dual-channel mode
Output Data Rate and Clock Rate Settings(1)
OUT_DATARATE<3:0> 0x02 Output data rate: Equal to decimation rate
OUT_CLKRATE<3:0> 0x02 Output clock rate: Equal to decimation rate
Output Clock Phase Control Settings(2)
EN_PHDLY 0x64 Enable digital output phase delay when decimation filter is used
DCLK_PHDLY_DEC<2:0> 0x64 Digital output clock phase delay control
Digital Signal Post-Processing (DSPP) Function Block Settings
EN_DSPP_2 = 1 0x79 Enable dual-channel decimation
Note 1: The output data and clock rates must be updated when decimation rates are changed.
2: Output clock (DCLK) phase control is used when the output clock is divided by OUT_CLKRATE<3:0>
bit settings.
Stage 1A
FIR
Input
DeMUX
Stage 2A
FIR
Stage 2B
FIR
Stage 3A
FIR
Stage 3B
FIR
Output
D2
Single
D2
Dual
Output D4
Dual
Stage 9A
FIR
Stage 9B
FIR
Output
D128
I/Q
D4
Single
D8
Single
D512
Single
Ch. A
Ch. B
Single-channel operation
Single
2
2
22 2
2
2
(Note 1)
(Note 2)
(Note 3)
Ch.
Input
Dual
Ch.
Input
Input
DeMUX
Ch. A
Ch. B
Input for DDC
MUX MUX MUX
DDC I/Q filtering
Output
D256
Dual
MUX
Note 1: Stage 1A FIR is the first stage of the FIR A filter.
2: (a) Single-channel mode: Only Channel A is used and controlled by FIR_A<8:0>.
(b) Dual-channel mode or I/Q filtering in DDC mode: Both Channel A and Channel B are used: Channel A is used for
the first channel or I data, and Channel B is used for the second channel or Q data.
3: Maximum decimation rate:
(a) When I/Q filtering in DDC mode is not used: 512x for single-channel and 256x for dual-channel mode.
(b) I/Q filtering in DDC mode: 128x each for FIR_A<8:1> and FIR_B<7:0>.
Dual-channel operation
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 58 2014-2016 Microchip Technology Inc.
4.8.3 DIGITAL DOWN-CONVERSION
(MCP37D31/21-200 ONLY)
The Digital Down-Conversion (DDC) feature is avail-
able in single-, dual- and CW octal-channel modes in
the MCP37D31/21-200. This feature can be optionally
combined with the decimation filter and used to:
• translate the input frequency spectrum to a lower
frequency band
• remove the unwanted out-of-band portion
• output the resulting signal as either I/Q data or as
a real signal centered at 25% of the output data
rate.
Figure 4-16 and Figure 4-17 show the DDC
configuration for single- and dual-channel DDC mode,
respectively. The DDC includes a 32-bit, complex
numerically controlled oscillator (NCO), a selectable
(high/low) half-band filter, optional decimation, and two
output modes (I/Q or fS/8).
Frequency translation is accomplished with the NCO.
The NCO frequency is programmable from 0 Hz to fS.
Phase and amplitude dither can be enabled to improve
spurious performance of the NCO.
This DDC feature can be used in a variety of high-
speed signal-processing applications, including digital
radio, wireless base stations, radar, cable modems,
digital video, MRI imaging, etc.
Example:
If the ADC is sampling an input at 200 Msps, but the
user is only interested in a 5 MHz span which is
centered at 67 MHz, the digital down-conversion may
be used to mix the sampled ADC data with 67 MHz to
convert it to DC. The resulting signal can then be
decimated by 16x such that the bandwidth of the ADC
output is 6.25 MHz (200 Msps/16x decimation gives
12.5 Msps with 6.25 MHz Nyquist bandwidth). If fS/8
mode is selected, then a single 25 Msps channel is
output, where 6.25 MHz in the output data corresponds
to 67 MHz at the ADC input. If I/Q mode is selected,
then two 12.5 Msps channels are output, where DC
corresponds to 67 MHz and the channels represent in-
phase (I) and quadrature (Q) components of the down-
conversion.
4.8.3.1 Single-Channel DDC
Figure 4-16 shows the single-channel DDC
configuration. Each of these processing sub-blocks are
individually controlled. Examples of setting registers for
selected output type are shown in Tables 4-14 and 4-15.
FIGURE 4-16: Simplified DDC Block Diagram for Single-Channel Mode. See Tables 4-14 and 4-15
for Using This DDC Block.
Half-Band Filter A
LP/HP
NCO (32-bit)
CH. A
I
Q
Down-Converting and Decimation
HBFILTER_A
Decimation and Output Frequency Translation
FIR A
Decimation Filter
(Note 2)
(Note 1)(Note 1)
Real
(Note 3)
EN_DDC2
EN_DDC_FS/8
NCO (
)
EN_DDC1
f
S
/8
DER
EN_NCO
(Note 4)
(Note 5)
ADC DATA
COS SIN
FIR_A<8:1>
FIR_B<7:0>
FIR B
Decimation Filter
I or IDEC
Q or QDEC
RealDEC
or
Note 1: See Address 0x80 - 0x81 (Registers 5-40 – 5-41) for the control parameters.
2: See Figure 4-18 for details of NCO control block.
3: Half-band Filter A includes a single- stage decimation filter.
4: See Figure 4-15 for details.
5: Switches are closed if decimation filter is not used, and open if decimation filter is used.
2014-2016 Microchip Technology Inc. DS20005322D-page 59
MCP37231/21-200 AND MCP37D31/21-200
4.8.3.2 Dual-Channel DDC
Figure 4-17 shows the dual-channel DDC configura-
tion. Each channel includes the same processing ele-
ments as shown in the single-channel DDC, however
the I/Q outputs cannot be separately decimated since
the device only supports two channels of decimation
(four would be required for I/Q of Channel A and I/Q of
Channel B). The decimation option can be used if the
DDC output after the half-band filter is up-converted by
fS/8 for each channel. Otherwise, I/Q of each channel
will be output separately, similar to a four-channel input
device with the WCK output pin toggling synchronously
with the I-data of Channel A. Note that the NCO phase
can be adjusted uniquely for each of the two input
channels (see Figure 4-18). Examples of setting regis-
ters for selected output type are shown in Tables 4-16
and 4-17.
FIGURE 4-17: Simplified DDC Block Diagram for Dual-Channel Mode. See Tables 4-16 and 4-17 for
Using this DDC Block.
Half-Band Filter A
LP/HP
NCO (32-bit) NCO (fS/8)
Half-Band Filter B
LP/HP
CH. B
CH. A
IA
QA
IB
QB
RealA
RealB
QB
IB
EN_DDC1
Down-Converting and Decimation (Note 1)
HBFILTER_B
HBFILTER_A
EN_DDC2
(Note 3)
(Note 3)
EN_DDC_FS/8
Output Frequency Translation and Decimation (Note 1)
EN_NCO
(Note 2)
IA
QA
COS
ADC
Data:
SIN
COS SIN
Note 1: See Address 0x80 – 0x81 for the Control Parameters.
2: See Figure 4-18 for details of NCO control block.
3: Half-band Filter A and B include a single-stage decimation filter.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 60 2014-2016 Microchip Technology Inc.
4.8.3.3 Numerically Controlled Oscillator
(NCO)
The on-board Numerically Controlled Oscillator (NCO)
provides the frequency reference for the in-phase and
quadrature mixers in the digital down-converter (DDC).
The NCO serves as a quadrature local oscillator,
capable of producing an NCO frequency of between 0
Hz and fS with a resolution of fS/232, where fS is the
ADC core sampling frequency.
Figure 4-18 shows the control signals associated with
the NCO. In octal- or dual-channel mode, the NCO
allows the output phase to be adjusted on a
per-channel basis.
FIGURE 4-18: NCO Block Diagram.
• NCO Frequency Control:
The NCO frequency is programmed from 0 Hz to fS,
using the 32-bit-wide unsigned register variable
NCO_TUNE<31:0> in Addresses 0x82 – 0x85
(Registers 5-42 – 5-45).
The following equation is used to set the
NCO_TUNE<31:0> register:
EQUATION 4-5: NCO FREQUENCY
Mod() is a remainder function. For example,
Mod(5,2) = 1 and Mod(1.999, 2) = 1.999.
Example 1:
If fNCO is 100 MHz and fS is 200 MHz:
Example 2:
If fNCO is 199.99999994 MHz and fS is 200 MHz:
4.8.3.4 NCO Amplitude and Phase Dither
The EN_AMPDITH and EN_PHSDITH parameters in
Address 0x80 (Register 5-40) can be used for
amplitude and phase dithering, respectively. In
principle, these will dither the quantization error created
by the use of digital circuits in the mixer and local
oscillator, thus reducing spurs at the expense of noise.
In practice, the DDC circuitry has been designed with
sufficient noise and spurious performance for most
applications. In the worst-case scenario, the NCO has
an SFDR of greater than 116 dB when the amplitude
dither is enabled, and 112 dB when disabled. Although
the SNR (≈93 dB) of the DDC is not significantly
affected by the dithering option, using the NCO with
dithering options enabled is always recommended for
the best performance.
4.8.3.5 NCO for fS/8 and fS/(8xDER)
The output of the first down-conversion block (DDC1)
is a complex signal (comprising I and Q data) which can
then be optionally decimated further up to 128x to
provide both a lower output data rate and input channel
filtering. If fS/8 mode is enabled, a second mixer stage
(DDC2) will convert the I/Q signals to a real signal
centered at half of the current Nyquist frequency; i.e., if
the output data rate in I/Q mode is 25 Msps per channel
(12.5 MHz Nyquist), then in fS/8 mode the output data
rate would be 50 Msps (25 Msps each for I and Q), and
the signal would be re-centered around 12.5 MHz. In
single-channel mode, this is done at the output of the
decimation filters (if used). In dual-channel mode, this
must be done prior to the decimation.
When decimation is enabled, the I/Q outputs are up-
converted by fS/(8xDER), where DER is the additional
decimation rate added by the FIR decimation filters.
This provides a decimated output signal centered at
fS/8 or fS/(8xDER) in the frequency domain.
Note: The NCO is only used for DDC or CW octal-
channel mode. It should be disabled when
not in use.
CH(n) NCO_PHASE<15:0>
Amplitude Dither EN_AMPDITH
EN_PHSDITH
EN_LFSR
NCO_TUNE<31:0>
Phase Offset Control
NCO Tuning Sine/Cosine
Signal Generator NCO Output
EN_NCO
Phase Dither EN_LFSR
NCO_TUNE<31:0> round 232 Mod fNCO fS
fS
------------------------------------
=
Where:
fS=sampling frequency (Hz)
fNCO =desired NCO frequency (Hz)
Mod (fNCO, fS)=gives the remainder of fNCO/fS
Mod fNCO fS
Mod 100 200
100==
NCO_TUNE<31:0> round 232 Mod 100 200
200
--------------------------------------
=
0x8000 0000=
Mod fNCO fS
Mod 199.99999994 200
199.99999994==
NCO_TUNE<31:0> round 232 Mod 199.99999994 200
200
---------------------------------------------------------------
=
0xFFFF FFFF=
2014-2016 Microchip Technology Inc. DS20005322D-page 61
MCP37231/21-200 AND MCP37D31/21-200
4.8.3.6 NCO Phase Offset Control
The user can add phase offset to the NCO frequency
using the NCO phase offset control registers
(Addresses 0x86 to 0x95, Registers 5-46 – 5-61).
CH(n)_NCO_PHASE<15:0> is the 16-bit-wide NCO
phase offset control parameter for Channel n. A
0x0000 value in the register corresponds to no offset,
and a 0xFFFF corresponds to an offset of 359.995°.
The phase offset can be controlled with 0.005° per
step. The following equation is used to program the
NCO phase offset register:
EQUATION 4-6: NCO PHASE OFFSET
A decimal number is used for the binary contents of
CH(n)_NCO_PHASE<15:0>.
4.8.3.7 In-Phase and Quadrature Signals
When the first down-conversion is enabled, it produces
In-phase (I) and Quadrature (Q) components as shown
in Equation 4-7:
EQUATION 4-7: I AND Q SIGNALS
I and Q outputs are interleaved where I data is output
on the rising edge of the WCK. If I and Q outputs are
selected in dual-channel mode with DDC enabled, I
data of Channel 0 is output at the rising edge of WCK,
followed by Q data of Channel 0, then I and Q data of
Channel 1 in the same way.
4.8.3.8 Half-Band Filter
The frequency translation is followed by a half-band
digital filter, which is used to reduce the sample rate by
a factor of two while rejecting aliases that fall into the
band of interest.
The user can select high- or low-pass half-band filter
using the HBFILTER_A and HBFILTER_B bits in
Address 0x80 (Register 5-40). These filters provide
greater than 90 dB of attenuation in the attenuation
band and less than 1 mdB (10-3 dB) of ripple in the
passband region of 20% of the input sampling rate.
For example, for an ADC sample rate of 200 MSPS,
these filters provide less than 1 mdB of ripple over a
bandwidth of 40 MHz.
The filter responses shown in Figures 4-15 and 4-16
indicate a ripple of 0.5 mdB and an alias rejection of
90 dB. The output of the half-band filter is a DC-cen-
tered complex signal (I and Q). This I and Q signal is
then carried to the next down-conversion stage
(DDC2) for frequency translation (up-conversion), if
the DDC is enabled.
FIGURE 4-19: High-Pass (HP) Response
of Half-Band Filter.
FIGURE 4-20: Low-Pass (LP) Response of
Half-Band Filter.
CH(n)_NCO_PHASE<15:0> 216 Offset Value (
360
---------------------------------------
=
Where:
n = channel number
Offset Value () = desired phase offset value in
degrees
where:
(a)
(b)
IADCCOS2
fNCOt
+
=
QADCSIN2
fNCOt
+
=
(c)
360 CH(n)_NCO_PHASE<15:0>
216
-----------------------------------------------------------------------
=
0.005493164
CH(n)_NCO_PHASE<15:0>
=
where:
ADC = output of the ADC block
= NCO phase offset of selected channel, which
is defined by CH(n)_NCO_PHASE<15:0> in
Addresses 0x86 - 0x95
t = k/fS, with k =1, 2, 3,..., n
fNCO = NCO frequency
Note: The half-band filter delays the data output
by 80 clock cycles: 2 (due to decimation) x
40 cycles (due to group delay)
In-Band Ripple
0.0005
0
-0.0005
0
-30
-60
-90
-120
Amplitude (dBc)
0 0.1 0.2 0.3 0.4 0.5
Half-Band Filter Frequency Response
0 0.1 0.2 0.3 0.4 0.5
Fraction of Input Sample Rate
In-Band Ripple
0.0005
0
-0.0005
0
-30
-60
-90
-120
Amplitude (dBc)
0 0.1 0.2 0.3 0.4 0.5
Half-Band Filter Frequency Response
0 0.1 0.2 0.3 0.4 0.5
Fraction of Input Sample Rate
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 62 2014-2016 Microchip Technology Inc.
4.8.4 EXAMPLES OF REGISTER
SETTINGS FOR USING DDC AND
DECIMATION
The following tables show examples of setting registers
for using decimation and digital down-conversion
(DDC) depending on the output type selection. This
feature is available in the MCP37D31/21-200 device
only.
TABLE 4-14: REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS
FOR SINGLE-CHANNEL MODE – EXAMPLE
Decimation Rate
(by FIR A and FIR B)(1)
DDC
Mode
Addr.
0x02(2)
FIR A Filter FIR B Filter DDC1 DDC2 Dual-Channel
DSPP Control
Output
0x7A<6>
(FIR_A<0>)
0x7B
(FIR_A<8:1>)
0x7C
(FIR_B<7:0>)
0x80<5,1,0>(3)
0x81<6,3,2>(4)
0x79<7>
(EN_DSPP_2)
0 Disabled 0x00 00x00 0x00 0,0,0 0,0,0 0 ADC
8 Disabled 0x33 10x03 0x00 0,0,0 0,0,0 0 ADC with decimation
(÷8)
512 Disabled 0x99 10xFF 0x00 0,0,0 0,0,0 0 ADC with decimation
(÷512)
0 I/Q 0x00(5)00x00 0x00 1,0,1 0,0,0 0 I/Q Data
8I/Q0x3300x07 0x07 1,0,1 0,0,0 0 Decimated I/Q (÷8)
0f
S/8 0x11(6)00x00 0x00 1,1,1 0,0,0 0 Real without
additional decimation
8f
S/8 0x44 00x07 0x07 1,0,1 1,0,0 0 Real with decimation
(÷16)
Note 1: When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-I/Q option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
2: Output data and clock rate control register.
3: 0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
4: 0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
5: Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate
adjustment is not needed.
6: The Half-Band Filter A includes decimation of 2.
2014-2016 Microchip Technology Inc. DS20005322D-page 63
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-15: OUTPUT TYPE VS. CONTROL PARAMETERS FOR SINGLE-CHANNEL DDC
(EXAMPLE)
Output Type Control Parameter Register Descriptions
Complex: I and Q EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 00X80 NCO(fS/8/DER) is disabled
EN_DDC2 = 00X81 DDC2 is disabled
FIR_A<8:1>=0x00 0X7B FIR A decimation filter is disabled
FIR_B<7:0>=0x00 0X7C FIR B decimation filter is disabled
OUT_CLKRATE<3:0> 0X02 Output clock rate is not affected (no need to change)
Decimated I and
Q:IDEC, QDEC
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 00X80 NCO(fS/8/DER) is disabled
EN_DDC2 = 00X81 DDC2 is disabled
FIR_A<8:1> 0X7B Program FIR A filter for extra decimation(1)
FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(1)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the decimation rate
Real: RealA after
DDC(fS/8/DER)
without using
Decimation Filter
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 10X80 NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8(2)
EN_DDC2 = 10X81 DDC2 is enabled
FIR_A<8:1>=0x00 0X7B Decimation filter FIR A is disabled
FIR_B<7:0>=0x00 0X7C Decimation filter FIR B is disabled
OUT_CLKRATE<3:0>
=0001
0X02 Adjust the output clock rate to divided by 2(3)
Decimated Real:
RealA_DEC
after Decimation
Filter and
DDC(fS/8/DER)
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 10X80 NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8/DER(2)
EN_DDC2 = 10X81 DDC2 is enabled
FIR_A<8:1> 0X7B Program FIR B filter for extra decimation(4)
FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(4)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
Note 1: For I/Q decimation, the maximum decimation rate for the FIR A and FIR B filters is 128x each since the
input is already decimated by 2x in the Half-Band Filter. See Figure 4-15 for details.
2: DER is the decimation rate setting of the FIR A and FIR B filters.
3: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
4: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 64 2014-2016 Microchip Technology Inc.
TABLE 4-16: REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS FOR DUAL-CHANNEL
MODE EXAMPLE
Decimation Rate
(by FIR A and FIR B)(1)
DDC-Mode
Address 0x02(2)
FIR A Filter FIR B Filter DDC1 DDC2
Dual-Channel
DSPP
Control
Output
0x7A<6>
(FIR_A<0>)
0x7B
(FIR_A<8:1>)
0x7C
(FIR_B<7:0>)
0x80<5,1,0>(3)
0x81<6,3,2>(4)
0x79<7>
(EN_DSPP_2)
0 Disabled 0x00 00x00 0x00 0,0,0 0,0,0 0 ADC
8 Disabled 0x33 00x07 0x07 0,0,0 0,0,0 0 ADC with decimation (÷8)
256 Disabled 0x88 00xFF 0xFF 0,0,0 0,0,0 0 ADC with decimation (÷256)
0 I/Q 0x00(5)00x00 0x00 1,0,1 0,0,0 1 I/Q data
0f
S/8 0x11(6)00x00 0x00 1,1,1 0,0,0 1 Real without additional
decimation
8f
S/8 0x44 00x0E 0x0E(7)1,1,1 0,0,0 1 Real with decimation filter
(÷16)
Note 1: When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-fS/2 option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
2: Output data and clock rate control register.
3: 0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
4: 0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
5: Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate
adjustment is not needed.
6: The Half-Band Filter A/B includes decimation of 2.
7: 0x0E takes into account the stages 1 and 2 are bypassed. See Figure 4-15 for “dual-channel Input” for DDC.
2014-2016 Microchip Technology Inc. DS20005322D-page 65
MCP37231/21-200 AND MCP37D31/21-200
TABLE 4-17: OUTPUT TYPE VS. CONTROL PARAMETERS FOR DUAL-CHANNEL DDC EXAMPLE
Output Type Control Parameter Register Descriptions
Complex: I and Q EN_DSPP_2 = 10X79 Enable all digital post-processing functions for dual-channel
operations
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
HBFILTER_B = 10X80 Enable Half-Band Filter B, includes 2x decimation
EN_DDC_FS/8 = 00X80 NCO(fS/8/DER) is disabled
EN_DDC2 = 00X81 DDC2 is disabled
FIR_A<8:1> = 0x00 0X7B FIR A decimation filter is disabled
FIR_B<7:0> = 0x00 0X7C FIR B decimation filter is disabled
OUT_CLKRATE<3:0> 0X02 Output clock rate is not affected (no need to change)
Real: RealA for
Channel A
and RealB for
Channel B after
NCO(fS/8/DER)
Without Using
Decimation Filter
EN_DSPP_2 = 10X79 Enable all digital post-processing functions for dual-channel
operations
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
HBFILTER_B = 10X80 Enable Half-Band Filter B, includes 2x decimation
EN_DDC_FS/8 = 10X80 NCO(fS/8/DER) is enabled. This translates the input signal
from DC to fS/8(1)
EN_DDC2 = 10X81 DDC2 is enabled
FIR_A<8:1> = 0x00 0X7B Decimation filter FIR A is disabled
FIR_B<7:0> = 0x00 0X7C Decimation filter FIR B is disabled
OUT_CLKRATE<3:0>
=0001
0X02 Adjust the output clock rate to divided by 2(2)
Decimated Real:
RealA_DEC for
Channel A and
RealB_DEC for
Channel B after
NCO(fS/8/DER) and
Decimation Filter
EN_DSPP_2 = 10X79 Enable all digital signal post-processing functions for dual-
channel operation
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
HBFILTER_B = 10X80 Enable Half-Band Filter B, includes 2x decimation
EN_DDC_FS/8 = 10X80 NCO(fS/8/DER) is enabled. This translates the input signal
from DC to fS/8/DER(1)
EN_DDC2 = 10X81 DDC2 is enabled
FIR_A<8:1> 0X7B Program FIR A filter for extra decimation(3)
FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(3)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
Note 1: DER is the decimation rate setting of the FIR A and FIR B filters.
2: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
3: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 66 2014-2016 Microchip Technology Inc.
4.9 Digital Offset and Digital Gain
Settings
Figure 4-21 shows a simplified block diagram of the
digital offset and gain settings. Offset is applied prior to
the gain. Offset and gain adjustments occur prior to
DDC, Decimation or FDR when these features are
used.
4.9.1 DIGITAL OFFSET SETTINGS
The offset can be corrected using a 16-bit-wide global
offset correction register (0x66) for all channels, offset
correction registers for individual channels (0x9E-
0xA7) or by combining both global and individual offset
correction registers. The offset control for individual
channels can be used with DIG_OFFSET_WEIGHT
<1:0> in 0xA7. The corresponding registers for each
correction are shown in Figure 4-21.
Note that, except for the octal-channel mode, the offset
setting registers for individual channels, 0x9E-0xA7
(Registers 5-70 –5-78), do not sequentially
correspond to the channel order defined by
CH_ORDER<23:0>. Tabl e 4-1 8 shows the details of
the offset registers that correspond to the actual
channels, depending on the number of channels used.
4.9.2 DIGITAL GAIN SETTINGS
CH(N)_DIG_GAIN<7:0> in Addresses 0x96 – 0x9D
(Registers 5-62 – 5-69) is used to adjust the digital gain
per channel.
FIGURE 4-21: Simplified Block Diagram for Digital Offset and Gain Settings.
Note 1: Digital Offset Setting: Register mapping
(0x9E – 0xA7) to the corresponding
channel is not sequential to the channel
order defined by CH_ORDER<23:0>,
except for the octal-channel mode. See
Table 4-18 for details.
2: Gain and NCO Phase Offset: Register
mapping to the corresponding channel is
sequential to the channel order defined
by CH_ORDER<23:0>.
TABLE 4-18: REGISTER ASSIGNMENT FOR OFFSET SETTING
Number of
Channel Used
Register Address for Offset Setting
1st Channel 2nd Channel 3rd Channel 4th Channel 5th Channel 6th Channel 7th Channel 8th Channel
10x9F ─ ─ ─ ─ ─ ─ ─
2 0xA0 0x9F ─ ─ ─ ─ ─ ─
3 0xA1 0x9F 0xA0 ─ ─ ─ ─ ─
4 0xA2 0x9F 0xA0 0xA1 ─ ─ ─ ─
5 0xA3 0x9F 0xA0 0xA1 0xA2 ─ ─ ─
6 0xA4 0x9F 0xA0 0xA1 0xA2 0xA3 ─ ─
7 0xA5 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 ─
8 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5
CH(n)_DIG_GAIN<7:0>
Digital Offset Control
ADC
Digital Gain Control
Output
Corrected
ADC Output
CH(n)_DIG_OFFSET<7:0>
DIG_OFFSET_WEIGHT<1:0>
Global Digital Offset Control
DIG_OFFSET_GLOBAL<15:0>
for individual channel for individual channel
(See Address 0x66) (See Addresses 0x9E – 0xA5)
(See Address 0xA7)
(See Addresses 0x96 – 0x9D)
for all channels
2014-2016 Microchip Technology Inc. DS20005322D-page 67
MCP37231/21-200 AND MCP37D31/21-200
4.10 Continuous Wave (CW)
Beamforming and Ultrasound
Doppler Signal Processing Using
CW Octal-Channel Mode
(MCP37D31/21-200 only)
In modern ultrasound medical applications, large num-
bers of transducers are often used. The signals from
these sensors are then coherently combined for higher
transducer gain and directivity. The signals from each
sensor arrive at the detection device with a different
time delay. Also, in multi-channel scanning operations
using the MUX, there is a time delay between acquiring
input signals (see Section 4.8.1 “Fractional Delay
Recovery for Dual- and Octal-Channel Modes”).
These time delays may need to be corrected before all
input signals are combined for the signal processing.
Digital beamforming is a digital signal processing
technique that requires summing all input signals from
different channels after correcting for time delay. The
time-delay correction involves the phase alignment of
the detected signals with respect to a reference.
Along with beamforming, many modern medical
ultrasound devices support Doppler imaging, which
processes phase information in addition to the classical
magnitude detection (for brightness imaging).
Ultrasound Doppler signal processing is used to
determine movement in the body as represented by
blood flow, which can help diagnose the functioning of
a heart valve or blood vessel, etc. In a traditional
ultrasound system, all of these functions are typically
accomplished with discrete components. Figure 4-23
shows an example of an ultrasound system
implementation using various specialized components.
The MCP37D31/21-200 device has a built-in feature
that can perform some of the functions that are done
traditionally using extra components. Continuous wave
(CW) digital beamforming and Doppler signal
processing features are available, but these are offered
in octal-channel operation only.
Figure 4-22 shows a simplified block diagram for the
ultrasound CW beamforming with DDC I/Q decimation.
Note that the sub-blocks shown after the MUX are
commonly used for all input channels.
FIGURE 4-22: Example of Ultrasound System Building Block.
T/R
Switcher
Transducer
Array
HV MUX and
T/R Switches
AAF
Isolation
Clocks
Beamformer Central
Control Processor
I/Q
Processing
DAC
ADC
ADC
CW
Doppler
Processing
Amp
Amp
ADC
VGA
LNA
Image and
Motion
Processing
(B Mode)
Color
Doppler
Processing
(F Mode)
HV
Amp
Digital RX Beamformer
Video DAC/
Video Encoder
Video
Compression
Amp/
Filter
Amp
Audio
DAC
LNA-VGA-ADC Array (up to 256 Channels)
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 68 2014-2016 Microchip Technology Inc.
4.10.1 BEAMFORMING
Beamforming is achieved by scanning all inputs while
correcting the phase of each channel with respect to a
reference. This can be done using:
• Fractional Delay Recovery (FDR)
• Phase offset settings of each individual channel
• Gain setting per channel
While the CW input channel is multiplexed sequentially,
the phase offset can be added to the NCO output (each
channel individually). CH(n)_NCO_PHASE<15:0>, in
Addresses 0x86 to 0x95 (Registers 5-46 – 5-61),
corrects the time delay of the incoming signals with
respect to the reference.
The phase-compensated input signal is then down-
converted by a wide dynamic range I/Q demodulator.
The digital beamforming of the inputs is then obtained
by summing I and Q data from individual channels. The
combined I and Q data are fed to the half-band filter.
Equation 4-8 shows the I and Q data of an individual
channel with phase correction (phase offset), and the
resulting digital beamforming signal.
The processing blocks after the digital beamforming
are the same as the sub-blocks used in single-channel
operation described in Section 4.8.3.1 “Single-
Channel DDC”, except only limited decimation rates of
the FIR A and FIR B filters are used due to the
processing time requirement for summing the input
signals from all channels.
EQUATION 4-8: BEAMFORMING SIGNALS
The NCO phase offset can be controlled by
0.005493164° per step. See Section 4.8.3.6 “NCO
Phase Offset Control” for details.
4.10.2 ULTRASOUND DOPPLER SIGNAL
PROCESSING
Doppler shift measurement requires summing the input
signals from multiple transducer channels and mixing
them with a phase-controlled local oscillator frequency.
The resulting low-frequency output is then centered
near DC and can measure a Doppler shift produced by
moving objects, such as blood flow and changes in
blood pressure in arteries, etc. In traditional Doppler
measurement, many discrete analog components are
typically used along with a high-resolution ADC
(~18-bit range).
This device has unique built-in features that are
suitable for ultrasound Doppler shift measurements. By
utilizing these features, system engineers can reduce
many discrete components which are otherwise
necessary for an ultrasound Doppler measurement
system.
The following built-in digital signal post-processing
(DSPP) features in the MCP37D31/21-200 can be
effectively used for the ultrasound Doppler signal pro-
cessing applications:
•Fractional Delay Recovery (FDR): Correct the
time delay of signal sampled between channels.
See details in Section 4.8.1 “Fractional Delay
Recovery for Dual- and Octal-Channel
Modes”.
•Digital Gain and Offset adjustment for each
channel: See details in Section 4.9 “Digital
Offset and Digital Gain Settings”.
•Down-Conversion for each channel with a
unique phase of the same NCO frequency prior to
summing the eight channels as shown in
Figure 4-23.
• After down-conversion by the DDC, the resulting
signal can then be decimated to achieve very high
SNR in a narrow bandwidth.
ICH n ADC COS 2
fNCOt
n+
=
QCH n ADC SIN 2
fNCOt
n+
=
II
CH n
n0=
N
=
QQ
CH n
n0=
N
=
n 360
CH(n)_NCO_PHASE<15:0>
216
-----------------------------------------------------------------------
=
0.005493164
CH(n)_NCO_PHASE<15:0>
=
Where:
(n) = NCO phase offset of channel n
ADC = the output of the ADC block
2014-2016 Microchip Technology Inc. DS20005322D-page 69
MCP37231/21-200 AND MCP37D31/21-200
I
FIGURE 4-23: Simplified Block Diagram of CW Beamforming and I/Q Signal Processing - Available
in MCP37D31/21-200 Only.
Half-Band Filter A
LP/HP
NCO (32-bit)
CH. 0
Channel Multiplexing/Down-Converting/Digital Beamforming/Decimation (2x)
HBFILTER_A
Decimation and Output Frequency Translation
FIR A
Decimation Filter
FIR_A<8:1>
FIR_B<7:0>
EN_DDC2
EN_DDC_FS/8
NCO (
)
EN_DDC1
f
S
/8
DER
EN_NCO
NCO Phase Offset Control
NCO Amplitude Dither EN_AMPDITH
EN_PHSDITH
EN_LFSR
Sine/Cosine
Signal Generator
CH. 1
CH. 2
CH. 7
NCO_TUNE<31:0>
CH(n) NCO_PHASE<15:0>
MUX
NCO Phase Dither
ICH(n)
QCH(n)
EN_LFSR
ADC
Data:
COS SIN
FIR B
Decimation Filter Real
I or IDEC
Q or QDEC
RealDEC
or
(Note 1)
Note 1: Switches are closed if a decimation filter is not used, and open if a decimation filter is used.
2: Digital Gain and Offset adjustments are applied prior to the Digital Down-Converter and
are not shown here.
(2)
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 70 2014-2016 Microchip Technology Inc.
4.11 Output Data format
The device can output the ADC data in offset binary or
two’s complement. The data format is selected by the
DATA_FORMAT bit in Address 0x62 (Register 5-20).
Table 4-19 shows the relationship between the analog
input voltage, the digital data output bits and the
overrange bit. By default, the output data format is
two’s complement.
4.12 Digital Output
The device can operate in one of the following three
digital output modes:
• Full-Rate CMOS
• Double-Data-Rate (DDR) LVDS
• Serialized DDR LVDS: Available in octal-channel
with 16-bit mode only)
The outputs are powered by DVDD18 and GND. LVDS
mode is recommended for data rates above 80 Msps.
The digital output mode is selected by the
OUTPUT_MODE<1:0> bits in Address 0x62
(Register 5-20). Figures 2-1 – 2-6 show the timing
diagrams of the digital output.
4.12.1 FULL RATE CMOS MODE
In full-rate CMOS mode, the data outputs (Q15 to Q0,
DM1 and DM2), overrange indicator (OVR), word
clock (WCK) and the data output clock (DCLK+,
DCLK–) have CMOS output levels. The digital output
should drive minimal capacitive loads. If the load
capacitance is larger than 10 pF, a digital buffer should
be used.
4.12.2 DOUBLE DATA RATE LVDS MODE
In double-data-rate LVDS mode, the output is a
parallel data stream which changes on each edge of
the output clock. See Figure 2-2 for details.
• Even-bit first option: Available for all resolution
options including 18-bit option. See Figure 2-2 for
details.
• MSb-first option: Available for the 16-bit option
only. See Figure 2-3 for details.
In multi-channel configuration, the data is output
sequentially with the WCK that is synchronized to the
first sampled channel.
The device outputs the following LVDS output pairs:
• Output Data:
- 16-/18-bit mode: Q7+/Q7- through Q0+/Q0-
- DM+/DM- (18-bit mode only)
- 14-bit mode: Q6+/Q6- through Q0+/Q0-
•OVR/WCK
• DCLK+/DCLK-
A 100Ω differential termination resistor is required for
each LVDS output pin pair. The termination resistor
should be located as close as possible to the LVDS
receiver. By default, the outputs are standard LVDS
levels: 3.5 mA output current with a 1.15V output com-
mon-mode voltage on a 100 differential load. See
Address 0x63 (Register 5-21) for more details of the
LVDS mode control.
TABLE 4-19: ADC OUTPUT CODE VS. INPUT VOLTAGE (16-BIT MODE)
Input Range Offset Binary(1)Two’s Complement(1)Overrange (OVR)
AIN > AFS 1111-1111-1111-1111 0111-1111-1111-1111 1
AIN = AFS 1111-1111-1111-1111 0111-1111-1111-1111 0
AIN = AFS – 1 LSb 1111-1111-1111-1110 0111-1111-1111-1110 0
AIN = AFS – 2 LSb 1111-1111-1111-1100 0111-1111-1111-1100 0
•
•
AIN = AFS/2 1100-0000-0000-0000 0100-0000-0000-0000 0
AIN = 0 1000-0000-0000-0000 0000-0000-0000-0000 0
AIN = -AFS/2 0011-1111-1111-1111 1011-1111-1111-1111 0
•
•
AIN = -AFS + 2 LSb 0000-0000-0000-0010 1000-0000-0000-0010 0
AIN = -AFS + 1 LSb 0000-0000-0000-0001 1000-0000-0000-0001 0
AIN = -AFS 0000-0000-0000-0000 1000-0000-0000-0000 0
AIN < -AFS 0000-0000-0000-0000 1000-0000-0000-0000 1
Note 1: MSb is sign bit
2014-2016 Microchip Technology Inc. DS20005322D-page 71
MCP37231/21-200 AND MCP37D31/21-200
4.12.3 SERIALIZED LVDS MODE
This output mode is only available for octal-channel
operation with 16-bit data output, and uses eight output
lanes: a single LVDS pair for each channel output as
shown in Figure 2-6.
Each channel’s data is serialized by the data serializer,
and the outputs are available through eight LVDS
output lanes. Each differential LVDS output pair holds
a single input channel's data, and clocks out data with
double data rate (DDR), which is synchronized with
WCK/OVR bit:
• Q7+/Q7- pair: 1st channel selected
• Q6+/Q6- pair: 2nd channel selected
•
•
• Q0+/Q0- pair: last channel selected
4.12.4 OVERRANGE BIT (OVR)
The input overrange status bit is asserted (logic high)
when the analog input has exceeded the full-scale
range of the ADC in either the positive or negative
direction. In LVDS DDR Output mode, the OVR bit is
multiplexed with the word clock (WCK) output bit such
that OVR is output on the falling edge of the data output
clock and WCK on the rising edge.
The OVR bit has the same pipeline latency as the
ADC data bits. In multi-channel mode, the OVR is out-
put independently for each input channel and is syn-
chronized to the data. In serialized LVDS mode (for
16-bit octal channel), the MSb is asserted coincident
with the WCK rising edge. OVR will be asserted if any
of the channels are overranged, but it does not specify
which channel is overranged. See Address 0x68
(Register 5-26) for OVR and WCK control options.
If DSPP options are enabled, OVR pipeline latency will
be unaffected; however, the data will incur additional
delay. This has the effect of allowing the OVR indicator
to precede the affected data.
4.12.5 WORD CLOCK (WCK)
The word clock output bit indicates the start of a new
data set. In single-channel mode, this bit is disabled
except for I/Q output mode. In DDR output with multi-
channel mode, it is always asserted coincidentally with
the data from the first sampled channel, and
multiplexed with the OVR bit. See Address 0x07
(Register 5-5) and Address 0x68 (Register 5-26) for
OVR and WCK control options.
4.12.6 LVDS OUTPUT POLARITY
CONTROL
In LVDS mode, the output polarity can be controlled
independently for each LVDS pair. Table 4-20
summarizes the LVDS output polarity control register bits.
4.12.7 PROGRAMMABLE LVDS OUTPUT
In LVDS mode, the default output driver current is
3.5 mA. This current can be adjusted by using the
LVDS_IMODE<2:0> bit setting in Address 0x63
(Register 5-21). Available output drive currents are
1.8 mA, 3.5 mA, 5.4 mA and 7.2 mA.
4.12.8 OPTIONAL LVDS DRIVER
INTERNAL TERMINATION
In most cases, using an external 100Ω termination
resistor will give excellent LVDS signal integrity. In
addition, an optional internal 100Ω termination resistor
can be enabled by setting the LVDS_LOAD bit in
Address 0x63 (Register 5-21). The internal termination
helps absorb any reflections caused by imperfect
impedance termination at the receiver.
4.12.9 OUTPUT DATA AND CLOCK RATES
The user can reduce output data and output clock rates
using Address 0x02 (Register 5-3). When decimation
or digital down-conversion (DDC) is used, the output
data rate has to be reduced to synchronize with the
reduced output clock rate.
4.12.10 PHASE SHIFTING OF OUTPUT
CLOCK (DCLK)
In full-rate CMOS mode, the data output bit transition
occurs at the rising edge of DCLK+, so the falling edge
of DCLK+ can be used to latch the output data.
In double-data-rate LVDS mode, the data transition
occurs at both the rising and falling edges of DCLK+.
For adequate setup and hold time when latching the
data into the external host device, the user can shift the
phase of the digital clock output (DCLK+/DCLK-)
relative to the data output bits.
Note: Output Data Rate in LVDS Mode: In
octal-channel mode, the input sample rate
per channel is fS/8. Therefore, the output
data rate required to shift out all 16 bits in
DDR is still equivalent to fS. For example,
if fS = 200 Msps, each channel’s sample
rate is fS/8 = 25 Msps, and the output
clock rate (DCLK) for 16-bit DDR output is
200 MHz. TABLE 4-20: LVDS OUTPUT POLARITY
CONTROL
Control
Parameter Register Descriptions
POL_LVDS<7:0> 0x65 Control polarity of LVDS
data pairs
POL_WCK_OVR 0x68 Control polarity of WCK
and OVR bit pair
POL_DM1DM2 0x68 Control polarity of DM+
and DM- pair
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 72 2014-2016 Microchip Technology Inc.
The output phase shift (delay) is controlled by each
unique register depending on which timing source is
used or if decimation is used. Ta b l e 4 - 2 1 shows the
output clock phase control registers for each Configu-
ration mode: (a) when DLL is used, (b) when decima-
tion is used, and (c) when PLL is used.
Figure 4-24 shows an example of the output clock
phase delay control using the DCLK_PHD-
LY_DLL<2:0> when DLL is used.
FIGURE 4-24: Example of Phase Shifting of Digital Output Clock (DCLK+) When DLL is Used.
TABLE 4-21: OUTPUT CLOCK (DCLK) PHASE CONTROL PARAMETERS
Control Parameter Register Operating Condition(1)
When DLL is used:
EN_PHDLY 0x64 EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DLL<2:0> 0x52 DCLK phase delay control when DLL is used. Decimation is not used.
When decimation is used:
EN_PHDLY 0x64 EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DEC<2:0> DCLK phase delay control when decimation filter is used. The phase delay
is controlled in digital clock output control block.
When PLL is used:
DCLK_DLY_PLL<2:0> 0x6D DCLK delay control when PLL is used.
Note 1: See Figure 4-11 for details.
Output Clock
Phase Shift:
0°
45° + Default
90° + Default
135° + Default
180° + Default
225° + Default
270° + Default
315° + Default
DCLK_PHDLY_DLL<2:0>
= 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
(DCLK+)
LVDS Data Output:
Note 1: Default value may not be 0° in all operations.
(Default)(1)
2014-2016 Microchip Technology Inc. DS20005322D-page 73
MCP37231/21-200 AND MCP37D31/21-200
4.12.11 DIGITAL OUTPUT RANDOMIZER
Depending on PCB layout considerations and power
supply coupling, SFDR may be improved by decorrelat-
ing the ADC input from the ADC digital output data. The
device includes an output data randomizer option.
When this option is enabled, the digital output is ran-
domized by applying an exclusive-OR logic operation
between the LSb (D0) and all other data output bits.
To decode the randomized data, the reverse operation
is applied: an exclusive-OR operation is applied
between the LSb (D0) and all other bits. The DCLK,
OVR, WCK, DM1, DM2 and LSb (D0) outputs are not
affected. Figure 4-25 shows the block diagram of the
data randomizer and decoder logic. The output ran-
domizer is enabled by setting the EN_OUT_RANDOM
bit in Address 0x07 (Register 5-5).
FIGURE 4-25: Logic Diagram for Digital Output Randomizer and Decoder (16-Bit mode).
4.12.12 OUTPUT DISABLE
The digital output can be disabled by setting
OUTPUT_MODE<1:0> = 00 in Address 0x62
(Register 5-20). All digital outputs are disabled,
including OVR, WCK, DCLK, etc.
4.12.13 OUTPUT TEST PATTERNS
To facilitate testing of the I/O interface, the device can
produce various predefined or user-defined patterns on
the digital outputs. See TEST_PATTERNS<2:0> in
Address 0x62 (Register 5-20) for the predefined test pat-
terns. For the user-defined patterns, Addresses 0x74 –
0x77 (Registers 5-29 –5-32) can be programmed using
the SPI interface. When an output test mode is enabled,
the ADC’s analog section can still be operational, but
does not drive the digital outputs. The outputs are driven
only with the selected test pattern.
Q0
Q1
Q2
WCK
DCLK
OVR
Q1
Q2
WCK
DCLK
OVR
Q0
Data Acquisition Device
(a) Data Randomizer (b) Data Decoder
DCLK
WCK
OVR
Q0
Q0
Q2 Q0
Q1 Q0
Q0
EN_OUT_RANDOM
MCP37XXX
Q15
Q14
Q15
Q14
Q15
Q14
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 74 2014-2016 Microchip Technology Inc.
4.12.13.1 Pseudo-random Number (PN)
Sequence Output
When TEST_PATTERNS<2:0> = 111, the device out-
puts a pseudo-random number (PN) sequence which is
defined by the polynomial of degree 16, as shown in
Equation 4-9. Figure 4-26 shows the block diagram of
a 16-bit Linear Feedback Shift Register (LFSR) for the
PN sequence.
EQUATION 4-9: POLYNOMIAL FOR PN
• 16-Bit Mode:
The output PN[15:0] is directly applied to the output pins
Qn[15:0]. In addition to the output at the Qn[15:0] pins, the
two MSbs, PN[15] and PN[14], are copied to OVR and
WCK pins, respectively. The two LSbs, PN[1] and PN[0],
are also copied to DM1 and DM2 pins, respectively.
• 14-Bit Mode:
The output PN[15:2] is directly applied to the output
pins Qn[13:0]. In addition to the output at the Qn[13:0]
pins, the two MSbs, PN[15] and PN[14], are copied to
OVR and WCK pins, respectively.
In CMOS output mode, the pattern is always applied to
all CMOS I/O pins, regardless whether or not they are
enabled. In LVDS output mode, the pattern is only
applied to the LVDS pairs that are enabled.
FIGURE 4-26: Block Diagram of 16-Bit LFSR
for Pseudo-Random Number (PN) Sequence for
Output Test Pattern.
4.13 System Calibration
The built-in system calibration algorithm includes:
• Harmonic Distortion Correction (HDC)
• DAC Noise Cancellation (DNC)
• Dynamic Element Matching (DEM)
HDC and DNC correct the nonlinearity in the residue
amplifier and DAC, respectively. The system
calibration is performed by:
• Power-up calibration, which takes place during
the Power-on Reset sequence (requires 227 clock
cycles)
• Background calibration, which takes place during
normal operation (per 230 clock cycles).
Background calibration time is invisible to the user,
and primarily affects the ADC's ability to track
variations in ambient temperature.
The calibration status is monitored by the CAL pin or
the ADC_CAL_STAT bit in Address 0xC0 (Register 5-
79). See Address 0x07 (Register 5-5) and 0x1E
(Register 5-6) for time delay control of the auto-
calibration. Ta b l e 4 - 2 2 shows the calibration time for
various ADC core sample rates.
4.13.1 RESET COMMAND
Although the background calibration will track changes
in temperature or supply voltage, changes in clock
frequency or register configuration should be followed
by a recalibration of the ADC. This can be
accomplished via either the Hard or Soft Reset
command. The recalibration time is the same as the
power-up calibration time (227 clock cycles). Resetting
the device is highly recommended when exiting from
Shutdown or Standby mode after an extended amount
of time. During the reset, the device has the following
state:
• No ADC output
• No change in power-on condition of internal
reference
• Most of the internal clocks are not distributed
• Contents of internal user registers:
- Not affected by Soft Reset
- Reset to default values by Hardware Reset
• Current consumption of the digital section is
negligible, but no change in the analog section.
Px 1x
4x13 x15 x16
++++=
Z-4 Z-9 Z-2 Z-1
XOR
PN[3] PN[12] PN[14] PN[15]
TABLE 4-22: CALIBRATION TIME VS. ADC
CORE SAMPLE RATE
fS (Msps) 200 150 100 70 50
Power-Up
Calibration Time (s)
0.67 0.9 1.34 1.92 2.68
Background
Calibration Time (s)
5.37 7.16 10.73 15.34 21.48
2014-2016 Microchip Technology Inc. DS20005322D-page 75
MCP37231/21-200 AND MCP37D31/21-200
4.13.1.1 Hardware Reset
A hard reset is triggered by toggling the RESET pin. On
the rising edge, all internal calibration registers and
user registers are initialized to their default states and
recalibration of the ADC begins. The recalibration time
is the same as the power-up calibration time. See
Figure 2-8 for the timing details of the hardware
RESET pin.
4.13.1.2 Soft Reset
The user can issue a Soft Reset command for a fast
recalibration of the ADC by setting the SOFT_RESET
bit to ‘0’ in Address 0x00 (Register 5-1). During Soft
Reset, all internal calibration registers are initialized to
their initial default states. User registers are unaffected.
When exiting the Soft Reset (changing from ‘0’ to ‘1’),
an automatic device calibration takes place.
4.14 Power Dissipation and Power
Savings
The power dissipation of the ADC core is proportional
to the sample rate (fS). The digital power dissipation of
the CMOS outputs are determined primarily by the
strength of the digital drivers and the load condition on
each output pin. The maximum digital load current
(ILOAD) can be calculated as:
EQUATION 4-10: CMOS OUTPUT LOAD
CURRENT
The capacitive load presented at the output pins needs
to be minimized to minimize digital power consumption.
The output load current of the LVDS output is constant,
since it is set by LVDS_IMODE<2:0> in Address 0x63
(Register 5-21).
4.14.1 POWER-SAVING MODES
This device has two power-saving modes:
• Shutdown
• Standby
They are set by the SHUTDOWN and STANDBY bits in
Address 0x00 (Register 5-1).
In Shutdown mode, most of the internal circuitry,
including the reference and clock, are turned off with
the exception of the SPI interface. During Shutdown,
the device consumes 23 mA (typical), primarily due to
digital leakage. When exiting from Shutdown, issuing a
Soft Reset at the same time is highly recommended.
This will perform a fast recalibration of the ADC. The
contents of the internal registers are not affected by the
Soft Reset.
In Standby mode, most of the internal circuitry is
disabled except for the reference, clock and SPI
interface. If the device has been in standby for an
extended period of time, the current calibration value
may not be accurate. Therefore, when exiting from
Standby mode, executing the device Soft Reset at the
same time is highly recommended.
ILOAD DVDD1.8 fDCLK NC
LOAD
=
Where:
N = Number of bits
CLOAD = Capacitive load of output pin
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 76 2014-2016 Microchip Technology Inc.
4.15 AutoSync Mode: Synchronizing
Multiple ADCs at the same Clock
using Master and Slave
Configuration
AutoSync allows multiple devices to sample input syn-
chronously at the same clock, and output the conver-
sion data at the same time if they are using the same
digital signal post-processing. Figure 4-27 shows the
system configuration using the AutoSync feature.
Three examples with timing diagram are shown in
Figure 2-9 – Figure 2-11.
Once the devices are synchronized, each device
performs internal calibration (TPCAL) before sending out
valid data output. Any ADC data output before the
calibration is complete should be ignored.
Note that the calibration time varies slightly from
device to device, and the internal calibration status can
be monitored using the CAL pin or ADC_CAL_STAT bit
in the Register Address 0xC0.
The valid synchronized output is available when all
devices complete their own internal calibration. For
this reason, the user has two options for the
synchronized output: (a) monitor the calibration status
of individual devices and wait until all devices
complete calibrations or (b) use an external AND gate
as shown in Figure 4-26. Master and all Slave devices
are synchronized when the AND gate output toggles
to “High”.
The AutoSync feature can be used with the following
steps:
• Master device is selected by setting SLAVE pin to
“GND”: SYNC pin becomes output pin.
• Slave device is selected by setting SLAVE pin to
“High” (or tie to DVDD): SYNC pin becomes input
pin.
• Feed the Master’s SYNC pin output to Slave’s
SYNC pin.
• Use AutoSync mode using (a) Power-On Reset
(Figure 2-9), (b) RESET Pin (Figure 2-10), or (c)
SOFT RESET bit (Figure 2-11).
2014-2016 Microchip Technology Inc. DS20005322D-page 77
MCP37231/21-200 AND MCP37D31/21-200
FIGURE 4-27: Synchronizing Multiple ADCs Using AutoSync Feature.
Note: For optimum operation, it is highly recommended to use the same digital supply voltage (DVDD18,
DVDD12) (i.e., tie all DVDD12 together and tie all DVDD18 together) for Master and Slave devices.
MCP37XXX
Slave 1
SYNC Pin Output SLAVESYNC
DV
DD18
DV
DD18
Pull-up
(> 360
)
CAL
MCP37XXX
SLAVESYNC
DV
DD18
CAL
MCP37XXX
SLAVESYNC
DV
DD18
CAL
Slave 2
Slave N
Master
MCP37XXX
SYNCSLAVE
CAL
AND Gate
“High” when
complete
all devices
calibration
2014-2016 Microchip Technology Inc. DS20005322D-page 78
MCP37231/21-200 AND MCP37D31/21-200
5.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The user can configure the ADC for specific functions
or optimized performance by setting the device’s
internal registers through the serial peripheral interface
(SPI). The SPI communication uses three pins: CS,
SCLK and SDIO. Table 5-1 summarizes the SPI pin
functions. The SCLK is used as a serial timing clock
and can be used up to 50 MHz. SDIO (Serial Data
Input/Output) is a dual-purpose pin that allows data to
be sent or read from the internal registers. The Chip
Select pin (CS) enables SPI communication when
active-low. The falling edge of CS followed by a rising
edge of SCLK determines the start of the SPI
communication. When CS is tied to high, SPI
communication is disabled and the SPI pins are placed
in high-impedance mode. The internal registers are
accessible by their address.
Figures 5-1 and 5-2 show the SPI data communication
protocols for this device with MSb-first and LSb-first
options, respectively. It consists of:
• 16-bit wide instruction header + Data byte 1 +
Data byte 2 + . . . + Data Byte N
Table 5-2 summarizes the bit functions. The R/W bit of
the instruction header indicates whether the command
is a read (‘1’) or a write (‘0’):
•If the R/W
bit is ‘1’, the SDIO pin changes
direction from an input (SDI) to an output (SDO)
after the 16-bit wide instruction header.
By selecting the R/W bit, the user can write the register
or read back the register contents. The W1 and W2 bits
in the instruction header indicate the number of data
bytes to transmit or receive in the following data frame.
Bits A2 – A0 are the SPI device address bits. These
bits are used when multiple devices are used in the
same SPI bus. A2 is internally hardcoded to ‘0’. Bits A1
and A0 correspond to the logic level of the ADR1 and
ADR0 pins, respectively.
The R9 – R0 bits represent the starting address of the
Configuration register to write or read. The data bytes
following the instruction header are the register data.
All register data is eight bits wide. Data can be sent in
MSb-first mode (default) or in LSb-first mode, which is
determined by the <LSb_ FIRST> bit setting in Address
0x00 (Register 5-1). In Write mode, the data is clocked
in at the rising edge of the SCLK. In the Read mode, the
data is clocked out at the falling edge of the SCLK.
Note 1: The register address counter is incremented
by one per step. The counter does not
automatically reset to 0x00 after reaching the
last address (0x15D). Be aware that the user
registers are not sequentially allocated.
Note: In the VTLA-124 package, ADR1 is
internally bonded to ground (logic ‘0’).
TABLE 5-1: SPI PIN FUNCTIONS
Pin
Name Descriptions
CS
Chip Select pin. SPI mode is initiated at
the falling edge. It needs to maintain
active-low for the entire period of the
SPI communication. The device exits the
SPI communication at the rising edge.
SCLK
Serial clock input pin.
• Writing to the device: Data is latched
at the rising edge of SCLK
• Reading from the device: Data is
latched at the falling edge of SCLK
SDIO
Serial data input/output pin. This pin is
initially an input pin (SDI) during the first
16-bit instruction header. After the
instruction header, its I/O status can be
changed depending on the R/W bit:
•if R/W = 0: Data input pin (SDI) for
writing
•if R/W
= 1: Data output pin (SDO) for
reading
TABLE 5-2: SPI DATA PROTOCOL BIT
FUNCTIONS
Bit Name Descriptions
R/W 1= Read Mode
0= Write Mode
W1, W0
(Data
Length)
00 = Data for one register (1 byte)
01 = Data for two registers (2 bytes)
10 = Data for three registers (3 bytes)
11 = Continuous reading or writing by
clocking SCLK(1)
A2 - A0 Device SPI Address for multiple
devices in SPI bus
A2: Internally hardcoded to ‘0’
A1: Logic level of ADR1 pin
A0: Logic level of ADR0 pin
R9 - R0 Address of starting register
D7 - D0 Register data. MSb or LSb first,
depending on the LSb_FIRST bit
setting in 0x00
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 79 2014-2016 Microchip Technology Inc.
FIGURE 5-1: SPI Serial Data Communication Protocol with MSb-first. See Figures 2-5 and 2-6 for
Timing Specifications.
FIGURE 5-2: SPI Serial Data Communication Protocol - with LSb-First. See Figures 2-5 and 2-6 for
Timing Specifications.
5.1 Register Initialization
The internal Configuration registers are initialized to
their default values under two different conditions:
• After 220 clock cycles of delay from the power-on
reset (POR).
• Resetting the hardware reset pin (RESET).
Figures 2-5 and 2-6 show the timing details.
5.2 Configuration Registers
The internal registers are mapped from Addresses
0x00 – 0x15D. These user registers are not
sequentially located. Some user Configuration
registers include factory-controlled bits. The factory-
controlled bits should not be overwritten by the user.
All user Configuration registers are read/write, except
for the last four registers, which are read-only. Each
register is made of an 8-bit-wide volatile memory, and
their default values are loaded during the power-up
sequence or by using the hardware RESET pin. All
registers are accessible by the SPI command using the
register address. Table 5 -3 shows the user-register
memory map, and Registers 5-1 – 5-82 show the
details of the register bit functions.
CS
R/W W1 W0 A2 A1 A0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Register Data of
Register Data 2 Register Data N
16-Bit Instruction Header
Address of
SCLK
SDIO
Register Data
defined by R9 - R0
D7 D6 D5 D4 D3 D2 D1 D0 D0D1
D2
D7 D6 D5 D4 D3 D2 D1 D0
Device Address starting register
Starting Register
CS
R/WW1W0A2A1A0R9R8R7R6R5R4R3R2R1R0
Register Data 2 Register Data N
16-Bit Instruction Header
Address of
SCLK
SDIO
Register Data
D7D6
D5
D4
D3D2
D1
D0 D7D6
D5
D4
D3D2
D1
D0 D7
D6D5
Device Address Register Data of
defined by R9 - R0
starting register
Starting Register
Note 1: All address and bit locations that are not
included in the following register map
table should not be written or modified by
the user.
2: Some registers include factory-controlled
bits (FCB). Do not overwrite these bits.
2014-2016 Microchip Technology Inc. DS20005322D-page 80
MCP37231/21-200 AND MCP37D31/21-200
TABLE 5-3: REGISTER MAP TABLE
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
0x00 SPI Bit Ordering and ADC
Mode Selection
SHUTDOWN LSb-FIRST SOFT_RESET STANDBY STANDBY SOFT_RESET LSb-FIRST SHUTDOWN 0x24
1= Shutdown 1=LSb first
0=MSb first
0= Soft Reset 1= Standby 1= Standby 0=Soft Reset 1= LSb first
0= MSb first
1=Shutdown
0x01 No. of Channel Selection and
Independency Control of
Output Data and Clock Divider
EN_DATCLK_IND
FCB<3> = 0SEL_NCH<2:0> FCB<2:0> = 111 0x0F
0x02 Output Data and
Clock Rate Control
OUT_DATARATE<3:0> OUT_CLKRATE<3:0> 0x00
0x04 SPI SDO Timing Control SDO_TIME FCB<6:0> = 0011111 0x9F
0x07 Output Randomizer
and WCK Polarity Control
POL_WCK EN_AUTOCAL_
TIMEDLY
FCB<4:0> = 10001 EN_OUT_
RANDOM
0x62
0x1E Auto-Calibration
Time Delay Control
AUTOCAL_TIMEDLY<7:0> 0x80
0x52 DLL Control EN_DUTY DCLK_PHDLY_DLL<2:0> EN_DLL_DCLK EN_DLL EN_CLK RESET_DLL 0x0A
0x53 Clock Source Selection FCB<6:4>= 010 CLK_SOURCE FCB<3:0>= 0101 0x45
0x54 PLL Reference Divider PLL_REFDIV<7:0> 0x00
0x55 PLL Output and
Reference Divider
PLL_OUTDIV<3:0> FCB<1:0> = 10 PLL_REFDIV<9:8> 0x48
0x56 PLL Prescaler (LSb) PLL_PRE (LSB)<7:0> 0x78
0x57 PLL Prescaler (MSb) FCB<3:0> = 0100 PLL_PRE (MSB)<11:8> 0x40
0x58 PLL Charge Pump FCB<2:0> = 000 PLL_BIAS PLL_CHAGPUMP<3:0> 0x12
0x59 PLL Enable Control 1 UFCB<4:3> = 10
EN_PLL_REFDIV
FCB<2:1> = 00 EN_PLL FCB<0> = 10x41
0x5A PLL Loop Filter Resistor UFCB<1:0> = 01 PLL_RES<4:0> 0x2F
0x5B PLL Loop Filter Cap3 UFCB<1:0> = 01 PLL_CAP3<4:0> 0x27
0x5C PLL Loop Filter Cap1 UFCB<1:0> = 01 PLL_CAP1<4:0> 0x27
0x5D PLL Loop Filter Cap2 UFCB<1:0> = 01 PLL_CAP2<4:0> 0x27
0x5F PLL Enable Control 2 FCB<5:2> = 1111
EN_PLL_OUT
EN_PLL_BIAS FCB<1:0> = 01 0xF1
0x62 Output Data Format and
Output Test Pattern
U LVDS_8CH DATA_FORMAT OUTPUT_MODE<1:0> TEST_PATTERNS<2:0> 0x10
0x63 ADC Output Bits
(Resolution) and LVDS
Output Load
OUTPUT_BIT<3:0> LVDS_LOAD LVDS_IMODE<2:0> 0x01
0x64 Output Clock Phase
Control when Decimation
Filter is used
EN_PHDLY
DCLK_PHDLY_DEC<2:0> FCB<3:0> = 0011 0x03
0x65 LVDS Output Polarity Control POL_LVDS<7:0> 0x00
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
2: Read-only register. Preprogrammed at the factory for internal use.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-paage 81 2014-2016 Microchip Technology Inc.
0x66 Digital Offset
Correction - Lower Byte
DIG_OFFSET_GLOBAL<7:0> 0x00
0x67 Digital Offset
Correction - Upper Byte
DIG_OFFSET_GLOBAL<15:8> 0x00
0x68 WCK/OVR and DM1/DM2 FCB<3:0> = 0010
POL_WCK_OVR
EN_WCK_OVR DM1DM2 POL_DM1DM2 0x24
0x6B PLL Calibration FCB<6:2> = 00001 PLL_CAL_TRIG FCB<1:0> = 00 0x08
0x6D PLL Output and Output Clock
Phase
U<1:0> EN_PLL_CLK FCB<1> = 0DCLK_DLY_PLL<2:0> FCB<0> = 00x00
0x74 User-Defined Output
Pattern A - Lower Byte
PATTERN A<7:0> 0x00
0x75 User-Defined Output
Pattern A - Upper Byte
PATTERN A<15:8> 0x00
0x76 User-Defined Output
Pattern B - Lower Byte
PATTERN B<7:0> 0x00
0x77 User-Defined Output
Pattern B - Upper Byte
PATTERN B<15:8> 0x00
0x79 Dual-Channel DSPP Control
EN_DSPP_2
FCB<6:0> = 000 0000 0x00
0x7A FDR and FIR_A0 FCB<5> = 0FIR_A<0> EN_FDR FCB<4:0> = 00000 0x00
0x7B FIR A Filter FIR_A<8:1> 0x00
0x7C FIR B Filter FIR_B<7:0> 0x00
0x7D Auto-Scan Channel Order -
Lower Byte
CH_ORDER<7:0> 0x78
0x7E Auto-Scan Channel Order -
Middle Byte
CH_ORDER<15:8> 0xAC
0x7F Auto-Scan Channel Order -
Upper Byte
CH_ORDER<23:16> 0x8E
0x80 Digital Down-Converter
Control 1
HBFILTER_B HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR
EN_DDC_FS/8
EN_DDC1 0x00
0x81 Digital Down-Converter
Control 2
FDR_BAND EN_DDC2 GAIN_HBF_DDC SEL_FDR EN_DSPP_8 8CH_CW GAIN_8CH<1:0> 0x00
0x82 Numerically Controlled
Oscillator (NCO) Tuning -
Lower Byte
NCO_TUNE<7:0> 0x00
0x83 Numerically Controlled
Oscillator (NCO) Tuning -
Middle Lower Byte
NCO_TUNE<15:8> 0x00
0x84 Numerically Controlled
Oscillator (NCO) Tuning -
Middle Upper Byte
NCO_TUNE<23:16> 0x00
TABLE 5-3: REGISTER MAP TABLE (CONTINUED)
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
2: Read-only register. Preprogrammed at the factory for internal use.
2014-2016 Microchip Technology Inc. DS20005322D-page 82
MCP37231/21-200 AND MCP37D31/21-200
0x85 Numerically Controlled
Oscillator (NCO) Tuning -
Upper Byte
NCO_TUNE<31:24> 0x00
0x86 CH0 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH0_NCO_PHASE<7:0> 0x00
0x87 CH0 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH0_NCO_PHASE<15:8> 0x00
0x88 CH1 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH1_NCO_PHASE<7:0> 0x00
0x89 CH1 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH1_NCO_PHASE<15:8> 0x00
0x8A CH2 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH2_NCO_PHASE<7:0> 0x00
0x8B CH2 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH2_NCO_PHASE<15:8> 0x00
0x8C CH3 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH3_NCO_PHASE<7:0> 0x00
0x8D CH3 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH3_NCO_PHASE<15:8> 0x00
0x8E CH4 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH4_NCO_PHASE<7:0> 0x00
0x8F CH4 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH4_NCO_PHASE<15:8> 0x00
0x90 CH5 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH5_NCO_PHASE<7:0> 0x00
0x91 CH5 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH5_NCO_PHASE<15:8> 0x00
0x92 CH6 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH6_NCO_PHASE<7:0> 0x00
0x93 CH6 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH6_NCO_PHASE<15:8> 0x00
0x94 CH7 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH7_NCO_PHASE<7:0> 0x00
0x95 CH7 NCO Phase Offset in CW
or DDC Mode - Upper Byte
CH7_NCO_PHASE<15:8> 0x00
0x96 CH0 Digital Gain CH0_DIG_GAIN<7:0> 0x3C
0x97 CH1 Digital Gain CH1_DIG_GAIN<7:0> 0x3C
0x98 CH2 Digital Gain CH2_DIG_GAIN<7:0> 0x3C
0x99 CH3 Digital Gain CH3_DIG_GAIN<7:0> 0x3C
TABLE 5-3: REGISTER MAP TABLE (CONTINUED)
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
2: Read-only register. Preprogrammed at the factory for internal use.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-paage 83 2014-2016 Microchip Technology Inc.
0x9A CH4 Digital Gain CH4_DIG_GAIN<7:0> 0x3C
0x9B CH5 Digital Gain CH5_DIG_GAIN<7:0> 0x3C
0x9C CH6 Digital Gain CH6_DIG_GAIN<7:0> 0x3C
0x9D CH7 Digital Gain CH7_DIG_GAIN<7:0> 0x3C
0x9E CH0 Digital Offset CH0_DIG_OFFSET<7:0> 0x00
0x9F CH1 Digital Offset CH1_DIG_OFFSET<7:0> 0x00
0xA0 CH2 Digital Offset CH2_DIG_OFFSET<7:0> 0x00
0xA1 CH3 Digital Offset CH3_DIG_OFFSET<7:0> 0x00
0xA2 CH4 Digital Offset CH4_DIG_OFFSET<7:0> 0x00
0xA3 CH5 Digital Offset CH5_DIG_OFFSET<7:0> 0x00
0xA4 CH6 Digital Offset CH6_DIG_OFFSET<7:0> 0x00
0xA5 CH7 Digital Offset CH7_DIG_OFFSET<7:0> 0x00
0xA7 Digital Offset Weight Control FCB<5:3> = 010 DIG_OFFSET_WEIGHT<1:0> FCB<2:0> = 111 0x47
0xC0 Calibration Status
Indication (Read only)
ADC_CAL_STAT FCB<6:0> = 000-0000 ─
0xD1 PLL Calibration Status
and PLL Drift Status Indication
(Read only)
FCB<4:3> = xx PLL_CAL_STAT FCB<2:1> = xx
PLL_VCOL_STAT
PLL_VCOH_STAT
FCB<0> = x─
0x15C CHIP ID - Lower Byte(2)
(Read only) CHIP_ID<7:0> ─
0x15D CHIP ID - Upper Byte(2)
(Read only)
CHIP_ID<15:8> ─
TABLE 5-3: REGISTER MAP TABLE (CONTINUED)
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
2: Read-only register. Preprogrammed at the factory for internal use.
2014-2016 Microchip Technology Inc. DS20005322D-page 84
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-1: ADDRESS 0X00 – SPI BIT ORDERING AND ADC MODE SELECTION(1)
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
SHUTDOWN LSb_FIRST SOFT_RESET STANDBY STANDBY SOFT_RESET LSb_FIRST SHUTDOWN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SHUTDOWN: Shutdown mode setting for power-saving(2)
1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
bit 6 LSb_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 5 SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 4 STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 3 STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 2 SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 1 LSb_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 0 SHUTDOWN: Shutdown mode setting for power-saving(2)
1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
Note 1: Upper and lower nibble are mirrored, which makes the MSb- or LSb-first mode interchangeable. The lower nibble (bit <3:0>)
has a higher priority when the mirrored bits have different values.
2: During Shutdown mode, most of the internal circuits including the reference and clock are turned-off except for the SPI
interface. When exiting from Shutdown (changing from ‘1’ to ‘0’), executing the device Soft Reset simultaneously is highly
recommended for a fast recalibration of the ADC. The internal user registers are not affected.
3: This bit forces the device into Soft Reset mode, which initializes the internal calibration registers to their initial default states.
The user-registers are not affected. When exiting Soft Reset mode (changing from ‘0’ to ‘1’), the device performs an automatic
device calibration including PLL calibration if PLL is enabled. DLL is reset if enabled. During Soft Reset, the device has the
following states:
- no ADC output
- no change in power-on condition of internal reference
- most of the internal clocks are not distributed
- power consumption: (a) digital section - negligible, (b) analog section - no change
4: During Standby mode, most of the internal circuits are turned off except for the reference, clock and SPI interface. When exiting
from Standby mode (changing from ‘1’ to ‘0’) after an extended amount of time, executing Soft Reset simultaneously is highly
recommended. The internal user registers are not affected.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 85 2014-2016 Microchip Technology Inc.
REGISTER 5-2: ADDRESS 0X01 – NUMBER OF CHANNELS, INDEPENDENCY CONTROL OF OUTPUT
DATA AND CLOCK DIVIDER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
EN_DATCLK_IND FCB<3> SEL_NCH<2:0> FCB<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_DATCLK_IND: Enable data and clock divider independently(1)
1 = Enabled
0 = Disabled (Default)
bit 6 FCB<3>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
bit 5-3 SEL_NCH<2:0>: Select the total number of input channels to be used(2)
111 = 7 inputs
110 = 6 inputs
101 = 5 inputs
100 = 4 inputs
011 = 3 inputs
010 = 2 inputs
001 = 1 input (Default)
000 = 8 inputs
bit 2-0 FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1: EN_DATCLK_IND = 1 enables OUT_CLKRATE<3:0> settings in Address 0x02 (Register 5-3).
2: See Addresses 0x7D – 0x7F (Registers 5-37 – 5-39) for selecting the input channel order.
2014-2016 Microchip Technology Inc. DS20005322D-page 86
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-3: ADDRESS 0X02 – OUTPUT DATA AND CLOCK RATE CONTROL(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OUT_DATARATE<3:0> OUT_CLKRATE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 OUT_DATARATE<3:0>: Output data rate control bits
1111 = Output data is all 0’s
1110 = Output data is all 0’s
1101 = Output data is all 0’s
1100 = Internal test only(2)
1011 = Internal test only(2)
1010 = Internal test only(2)
1001 = Full speed divided by 512
1000 = Full speed divided by 256
0111 = Full speed divided by 128
0110 = Full speed divided by 64
0101 = Full speed divided by 32
0100 = Full speed divided by 16
0011 = Full speed divided by 8
0010 = Full speed divided by 4
0001 = Full speed divided by 2
0000 = Full-speed rate (Default)
bit 3-0 OUT_CLKRATE<3:0>: Output clock rate control bits(3,4)
1111 = Full-speed rate
1110 = No clock output
1101 = No clock output
1100 = No clock output
1011 = No clock output
1010 = No clock output
1001 = Full speed divided by 512
1000 = Full speed divided by 256
0111 = Full speed divided by 128
0110 = Full speed divided by 64
0101 = Full speed divided by 32
0100 = Full speed divided by 16
0011 = Full speed divided by 8
0010 = Full speed divided by 4
0001 = Full speed divided by 2
0000 = No clock output (Default)
Note 1: This register should be used to realign the output data and clock when the decimation or digital down-conversion (DDC) option
is used.
2: 1100 - 1010: Do not reprogram. These settings are used for the internal test only. If these bits are reprogrammed with differ-
ent settings, the outputs will be in an undefined state.
3: Bits <3:0> become active if EN_DATCLK_IND = 1 in Address 0x01 (Register 5-2).
4: When no clock output is selected (Bits 1110 - 1010): clock output is not available at the DCLK+/DCLK- pins.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 87 2014-2016 Microchip Technology Inc.
REGISTER 5-4: ADDRESS 0X04 – SPI SDO OUTPUT TIMING CONTROL
R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
SDO_TIME FCB<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SDO_TIME: SPI SDO output timing control bit
1 = SDO output at the falling edge of clock (Default)
0 = SDO output at the rising edge of clock
bit 6-0 FCB<6:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
REGISTER 5-5: ADDRESS 0X07 – OUTPUT RANDOMIZER AND WCK POLARITY CONTROL
R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0
POL_WCK EN_AUTOCAL_-
TIMEDLY
FCB<4:0> EN_OUT_RANDOM
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 POL_WCK: WCK polarity control bit(1)
1 = Inverted
0 = Not inverted (Default)
bit 6 EN_AUTOCAL_TIMEDLY: Auto-calibration starter time delay counter control bit(2)
1 = Enabled (Default)
0 = Disabled
bit 5-1 FCB<4:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 0 EN_OUT_RANDOM: Output randomizer control bit
1 = Enabled: ADC data output is randomized
0 = Disabled (Default)
Note 1: See Address 0x68 (Register 5-26) for WCK/OVR pair control.
2: This bit enables the AUTOCAL_TIMEDLY<7:0> settings. See Address 0x1E (Register 5-6).
2014-2016 Microchip Technology Inc. DS20005322D-page 88
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-7: ADDRESS 0X52 – DLL CONTROL
REGISTER 5-6: ADDRESS 0X1E – AUTOCAL TIME DELAY CONTROL(1)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AUTOCAL_TIMEDLY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 AUTOCAL_TIMEDLY<7:0>: Auto-calibration start time delay control bits
1111-1111 = Maximum value
• • •
1000-0000 = (Default)
• • •
0000-0000 = Minimum value
Note 1: EN_AUTOCAL_TIMEDLY in Address 0x07 (Register 5-5) enables this register setting. This register controls the time delay
before the auto-calibration starts. The value increases linearly with the bit settings, from minimum to maximum values.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0
EN_DUTY DCLK_PHDLY_DLL<2:0> EN_DLL_DCLK EN_DLL EN_CLK RESET_DLL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_DUTY: Enable DLL circuit for duty cycle correction (DCC) of input clock
1 = Correction is ON
0 = Correction is OFF (Default)
bit 6-4 DCLK_PHDLY_DLL<2:0>: Select the phase delay of the digital clock output when using DLL(1)
111 = +315° phase-shifted from default
110 = +270° phase-shifted from default
101 = +225° phase-shifted from default
100 = +180° phase-shifted from default
011 = +135 phase-shifted from default
010 = +90° phase-shifted from default
001 = +45° phase-shifted from default
000 = (Default)
bit 3 EN_DLL_DCLK: Enable DLL digital clock output
1 = Enabled (Default)
0 = Disabled: DLL digital clock is turned off. ADC output is not available when DLL is used.
bit 2 EN_DLL: Enable DLL circuitry to provide a selectable phase clock to digital output clock.
1 = Enabled
0 = Disabled. DLL block is disabled (Default)
bit 1 EN_CLK: Enable clock input buffer
1 = Enabled (Default).
0 = Disabled. No clock is available to the internal circuits, ADC output is not available.
bit 0 RESET_DLL: DLL circuit reset control(2)
1 = DLL is active
0 = DLL circuit is held in reset (Default)
Note 1: These bits have an effect only if EN_PHDLY = 1 and decimation is not used.
2: DLL reset control procedure: Set this bit to ‘0’ (reset) and then to ‘1’.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 89 2014-2016 Microchip Technology Inc.
REGISTER 5-8: ADDRESS 0X53 – CLOCK SOURCE SELECTION
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
FCB<6:4> CLK_SOURCE FCB<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 FCB<6:4>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4 CLK_SOURCE: Select internal timing source
1 = PLL output is selected as timing source
0 = External clock input is selected as timing source (Default)
bit 3-0 FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
REGISTER 5-9: ADDRESS 0X54 – PLL REFERENCE DIVIDER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLL_REFDIV<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PLL_REFDIV<7:0>: PLL Reference clock divider control bits(1)
1111-1111 = PLL reference divided by 255 (if PLL_REFDIV<9:8> = 00)
1111-1110 = PLL reference divided by 254 (if PLL_REFDIV<9:8> = 00)
• • •
0000-0011 = PLL reference divided by 3 (if PLL_REFDIV<9:8> = 00)
0000-0010 = Do not use (No effect)
0000-0001 = PLL reference divided by 1 (if PLL_REFDIV<9:8> = 00)
0000-0000 = PLL reference not divided (if PLL_REFDIV<9:8> = 00) (Default)
Note 1: PLL_REFDIV is a 10-bit wide setting. See Address 0x55 (Register 5-10) for the upper two bits and Ta b l e 5 - 4 for PLL_REF-
DIV<9:0> bit settings. This setting controls the clock division ratio of the PLL reference clock (external clock input at the CLK
pin) before the PLL phase-frequency detector circuitry. Note that the divider value of 2 is not supported. EN_PLL_REFDIV in
Address 0x59 (Register 5-14) must be set.
2014-2016 Microchip Technology Inc. DS20005322D-page 90
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-10: ADDRESS 0X55 – PLL OUTPUT AND REFERENCE DIVIDER
R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
PLL_OUTDIV<3:0> FCB<1:0> PLL_REFDIV<9:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 PLL_OUTDIV<3:0>: PLL output divider control bits(1)
1111 = PLL output divided by 15
1110 = PLL output divided by 14
• • •
0100 = PLL output divided by 4 (Default)
0011 = PLL output divided by 3
0010 = PLL output divided by 2
0001 = PLL output divided by 1
0000 = PLL output not divided
bit 3-2 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 1-0 PLL_REFDIV<9:8>: Upper two MSb bits of PLL_REFDIV<9:0>(2)
00 = see Table 5-4. (Default)
Note 1: PLL_OUTDIV<3:0> controls the PLL output clock divider: VCO output is divided by the PLL_OUTDIV<3:0> setting.
2: See Address 0x54 (Register 5-9) and Ta b l e 5 - 4 for PLL_REFDIV<9:0> settings. EN_PLL_REFDIV in Address 0x59
(Register 5-14) must be set.
TABLE 5-4: EXAMPLE – PLL REFERENCE DIVIDER BIT SETTINGS VS. PLL REFERENCE INPUT
FREQUENCY
PLL_REFDIV<9:0> PLL Reference Frequency
11-1111-1111 Reference frequency divided by 1023
11-1111-1110 Reference frequency divided by 1022
──
00-0000-0011 Reference frequency divided by 3
00-0000-0010 Do not use (not supported)
00-0000-0001 Reference frequency divided by 1
00-0000-0000 Reference frequency divided by 1
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 91 2014-2016 Microchip Technology Inc.
REGISTER 5-11: ADDRESS 0X56 – PLL PRESCALER (LSB)
R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
PLL_PRE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PLL_PRE<7:0>: PLL prescaler selection(1)
1111-1111 = VCO clock divided by 255 (if PLL_PRE<11:8> = 0000)
• • •
0111-1000 = VCO clock divided by 120 (if PLL_PRE<11:8> = 0000) (Default)
• • •
0000-0010 = VCO clock divided by 2 (if PLL_PRE<11:8> = 0000)
0000-0001 = VCO clock divided by 1 (if PLL_PRE<11:8> = 0000)
0000-0000 = VCO clock not divided (if PLL_PRE<11:8> = 0000)
Note 1: PLL_PRE is a 12-bit-wide setting. The upper four bits (PLL_PRE<11:8>) are defined in Address 0x57. See Table 5-5 for the
PLL_PRE<11:0> settings. The PLL Prescaler is used to divide down the VCO output clock in the PLL phase-frequency detector
loop circuit.
REGISTER 5-12: ADDRESS 0X57 – PLL PRESCALER (MSB)
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCB<3:0> PLL_PRE<11:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 3-0 PLL_PRE<11:8>: PLL prescaler selection(1)
1111 = 212 - 1 (max), if PLL_PRE<7:0> = 0xFF
• • •
0000 = Default)
Note 1: PLL_PRE is a 12-bit-wide setting. See the lower eight bit settings (PLL_PRE<7:0>) in Address 0x56 (Register 5-11). See
Ta b l e 5 - 5 for the PLL_PRE<11:0> settings for PLL feedback frequency.
TABLE 5-5: Example: PLL Prescaler Bit Settings and PLL Feedback Frequency
PLL_PRE<11:0> PLL Feedback Frequency
1111-1111-1111 VCO clock divided by 4095 (212 - 1)
1111-1111-1110 VCO clock divided by 4094 (212 - 2)
──
0000-0000-0011 VCO clock divided by 3
0000-0000-0010 VCO clock divided by 2
0000-0000-0001 VCO clock divided by 1
0000-0000-0000 VCO clock divided by 1
2014-2016 Microchip Technology Inc. DS20005322D-page 92
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-13: ADDRESS 0X58 – PLL CHARGE-PUMP
R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
FCB<2:0>: PLL_BIAS PLL_CHAGPUMP<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4 PLL_BIAS: PLL charge-pump bias source selection bit
1 = Self-biasing coming from AVDD (Default)
0 = Bandgap voltage from the reference generator (1.2V)
bit 3-0 PLL_CHAGPUMP<3:0>: PLL charge pump bias current control bits(1)
1111 = Maximum current
• • •
0010 = (Default)
• • •
0000 = Minimum current
Note 1: PLL_CHAGPUMP<3:0> should be set based on the phase detector comparison frequency. The bias current amplitude
increases linearly with increasing the bit setting values. The increase is from approximately 25 µA to 375 µA, 25 µA per step.
See Section 4.7.2.1, "PLL Output Frequency and Output Control Parameters" for more details of the PLL block.
REGISTER 5-14: ADDRESS 0X59 – PLL ENABLE CONTROL 1
U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
—FCB<4:3> EN_PLL_REFDIV FCB<2:1> EN_PLL FCB<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<4:3>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4 EN_PLL_REFDIV: Enable PLL Reference Divider (PLL_REFDIV<9:0>).
1 = Enabled
0 = Reference divider is bypassed (Default)
bit 3-2 FCB<2:1>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 1 EN_PLL: Enable PLL circuit.
1 = Enabled
0 = Disabled (Default)
bit 0 FCB<0>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 93 2014-2016 Microchip Technology Inc.
REGISTER 5-15: ADDRESS 0X5A – PLL LOOP FILTER RESISTOR
U-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_RES<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_RES<4:0>: Resistor value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
01111= (Default)
• • •
00000 = Minimum value
Note 1: PLL_RES<4:0> should be set based on the phase detector comparison frequency. The resistor value increases linearly with the
bit settings, from minimum to maximum values. See the PLL loop filter section in Section 4.7, "ADC Clock Selection".
REGISTER 5-16: ADDRESS 0X5B – PLL LOOP FILTER CAP3
U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_CAP3<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_CAP3<4:0>: Capacitor 3 value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
00111= (Default)
• • •
00000 = Minimum value
Note 1: This capacitor is in series with the shunt resistor, which is set by PLL_RES<4:0>. The capacitor value increases linearly with the
bit settings, from minimum to maximum values. This setting should be set based on the phase detector comparison frequency.
2014-2016 Microchip Technology Inc. DS20005322D-page 94
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-17: ADDRESS 0X5C – PLL LOOP FILTER CAP1
U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_CAP1<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_CAP1<4:0>: Capacitor 1 value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
00111= (Default)
• • •
00000 = Minimum value
Note 1: This capacitor is located between the charge pump output and ground, and in parallel with the shunt resistor which is defined by
the PLL_RES<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting
should be set based on the phase detector comparison frequency.
REGISTER 5-18: ADDRESS 0X5D – PLL LOOP FILTER CAP2
U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_CAP2<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_CAP2<4:0>: Capacitor 2 value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
00111= (Default)
• • •
00000 = Minimum value
Note 1: This capacitor is located between the charge pump output and ground, and in parallel with CAP1 which is defined by the PLL_-
CAP1<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting should
be set based on the phase detector comparison frequency.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 95 2014-2016 Microchip Technology Inc.
REGISTER 5-19: ADDRESS 0X5F – PLL ENABLE CONTROL 2(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1
FCB<5:2>
EN_PLL_OUT
EN_PLL_BIAS FCB<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 FCB<5:2>: Factory-Controlled Bits. This is not for the user. Do not change the default settings.
bit 3 EN_PLL_OUT: Enable PLL output.
1 = Enabled
0 = Disabled (Default)
bit 2 EN_PLL_BIAS: Enable PLL bias
1 = Enabled
0 = Disabled (Default)
bit 1-0 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1: To enable PLL output, EN_PLL_OUT, EN_PLL_BIAS and EN_PLL in Address 0x59 (Register 5-14) must be set.
2014-2016 Microchip Technology Inc. DS20005322D-page 96
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-20: ADDRESS 0X62 – OUTPUT DATA FORMAT AND OUTPUT TEST PATTERN
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
— LVDS_8CH DATA_FORMAT OUTPUT_MODE<1:0> TEST_PATTERNS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6 LVDS_8CH: LVDS data stream type selection for octal-channel mode(1)
1 = Serialized data stream(2)
0 = Interleaved with parallel data stream(3)(Default)
bit 5 DATA_FORMAT: Output data format selection
1 = Offset binary (unsigned)
0 = Two’s complement (Default)
bit 4-3 OUTPUT_MODE<1:0>: Output mode selection(4)
11 = DDR LVDS output mode with MSb byte first(5)
10 = DDR LVDS output mode with even bit first(6)(Default)
01 = CMOS output mode
00 = Output disabled
bit 2-0 TEST_PATTERNS<2:0>: Test output data pattern selection
111 = Output data is pseudo-random number (PN) sequence(7)
110 = Sync Pattern for LVDS output.
18-bit mode: '11111111 00000000 10'
16-bit mode: '11111111 00000000'
14-bit mode: '11111111 000000'
12-bit mode: '11111111 0000'
10-bit mode: '11111111 00'
101 = Alternating Sequence for LVDS mode
16-bit mode: ‘01010101 10101010’
14-bit mode: ‘01010101 101010’
100 = Alternating Sequence for CMOS.
Output: ‘11111111 11111111’ alternating with ‘00000000 00000000’
011 = Alternating Sequence for CMOS.
Output: ‘01010101 01010101’ alternating with ‘10101010 10101010’
010 = Ramp Pattern. Output is incremented by:
18-bit mode: 1 LSb per clock cycle
16-bit mode: 1 LSb per 4 clock cycles
14-bit mode: 1 LSb per 16 clock cycles
001 = Double Custom Patterns.
Output: Alternating custom pattern A (see Addresses 0X74 – 0X75 - Registers 5-29 – 5-30) and custom
pattern B (see Address 0X76 - 0X77 - Registers 5-31 – 5-32)(8)
000 = Normal Operation. Output: ADC data (Default)
Note 1: This bit setting is valid for the octal-channel mode only. See Addresses 0x7D-0x7F (Registers 5-37 – 5-39) for channel order selection.
2: Serialized LVDS is available in octal-channel with 16-bit mode only: Each LVDS output pair holds a single input channel's data
and outputs in a serial data stream (synchronized with WCK): Q7+/Q7- is for the first channel’s selected data, and Q0+/Q0- is for
the last channel’s selected data. This bit function is enabled only when EN_DSPP_8 = 1 in Address 0x81 (Register 5-41). See
Figure 2-4 for the timing diagram.
3: The output is in parallel data stream. The first sampled data bit is clocked out first in parallel LVDS output pins, followed by the
next sampled channel data bit. See Figures 2-2 and2-3 for the timing diagram.
4: See Figures 2-1 – 2-4 for the timing diagram.
5: Only 16-bit mode is available for this option.
Rising edge: Q15 - Q8.
Falling edge: Q7 - Q0
6: Rising edge: Q14, Q12, Q10,.... Q0.
Falling edge: Q15, Q13, Q11,... Q1.
7: Pseudo-random number (PN) code is generated by the linear feedback shift register (LFSR).
8: The alternating patterns A and B are applied to Q<15:0>. Pattern A<15:14> and Pattern B<15:14> are also applied to OVR and
WCK pins, respectively. Pattern A<1:0> and Pattern B<1:0> are also applied to DM1/DM+ and DM2/DM-.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 97 2014-2016 Microchip Technology Inc.
REGISTER 5-21: ADDRESS 0X63 – ADC OUTPUT BIT (RESOLUTION) AND LVDS LOAD
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
OUTPUT_BIT LVDS_LOAD LVDS_IMODE<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 16-Bit Device (MCP37231/D31-200):
OUTPUT_BIT<3:0>: Select number of output data bits(1)
1111 = 15
1110 = 14
1101 = 13
1100 = 12
1011 = 11
1010 = 10
1001 = 9
1000 = 8
0111 = 7
0110 = 6
0101 = 5
0100 = 4
0011 = 3
0010 = 2
0001 = 1
0000 = 16-bit (Default)
14-Bit Device (MCP37221/D21-200):
OUTPUT_BIT<3:0>: These bits have no effect(2)
bit 3 LVDS_LOAD: Internal LVDS load termination
1 = Enable internal load termination
0 = Disable internal load termination (Default)
bit 2-0 LVDS_IMODE<2:0>: LVDS driver current control bits
111 = 7.2 mA
011 = 5.4 mA
001 = 3.5 mA (Default)
000 = 1.8 mA
Do not use the following settings(3):
110, 101, 100, 010
Note 1: These bits are applicable for the 16-bit device only. See Address 0x68 (Register 5-26) for additional DM1 and DM2 bits.
2: In the 14-bit device, ADC resolution is not user selectable.
3: These settings can result in unknown output currents.
2014-2016 Microchip Technology Inc. DS20005322D-page 98
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-22: ADDRESS 0X64 – OUTPUT CLOCK PHASE CONTROL WHEN DECIMATION FILTER IS USED
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
EN_PHDLY DCLK_PHDLY_DEC<2:0> FCB<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_PHDLY: Enable digital output clock phase delay control when DLL or decimation filter is used.
1 = Enabled
0 = Disabled (Default)
bit 6-4 DCLK_PHDLY_DEC<2:0>: Digital output clock phase delay control when decimation filter is used(2)
111 = +315° phase-shifted from default(2)
110 = +270° phase-shifted from default
101 = +225° phase-shifted from default(2)
100 = +180° phase-shifted from default
011 = +135° phase-shifted from default(2)
010 = +90° phase-shifted from default
001 = +45° phase-shifted from default(2)
000 = Default(3)
bit 3-0 FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1: These bits have an effect only if EN_PHDLY = 1. See Address 0x52 (Register 5-7) for the same feature when DLL is used.
2: Only available when the decimation filter setting is greater than 2. When FIR_A/B <8:1> = 0’s (default) and FIR_A<6> = 0, only 4-
phase shifts are available (+45°, +135°, +225°, +315°) from default. See Addresses 0x7A, 0x7B and 0x7C (Registers 5-34 –5-36).
See Addresses 0x6D and 0x52 (Registers 5-28 and 5-7) for DCLK phase shift for other modes.
3: The phase delay for all other settings is referenced to this default phase.
REGISTER 5-23: ADDRESS 0X65 – LVDS OUTPUT POLARITY CONTROL
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POL_LVDS<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 POL_LVDS<7:0>: Control polarity of LVDS data pairs (Q7+/Q7- – Q0+/Q0-)(1)
1111-1111 = Invert all LVDS pairs
1111-1110 = Invert all LVDS pairs except the LSb pair
• • •
1000-0000 = Invert MSb LVDS pair
• • •
0000-0001 = Invert LSb LVDS pair
0000-0000 = No inversion of LVDS bit pairs (Default)
Note 1: (a) 14-bit mode: The LSb bit has no effect. (b) 12-bit mode: The last two LSb bits have no effect.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 99 2014-2016 Microchip Technology Inc.
REGISTER 5-24: ADDRESS 0X66 – DIGITAL OFFSET CORRECTION (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIG_OFFSET_GLOBAL<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_OFFSET_GLOBAL<7:0>: Lower byte of DIG_OFFSET_GLOBAL<15:0> for all channels(1)
0000-0000 = Default
Note 1: Offset is added to the ADC output. Setting is two’s complement using two combined registers (16-bits wide).
Setting range: (-215 to 215 - 1) x step size. Step size of each bit setting:
- 12-bit mode: 0.125 LSb
- 14-bit mode: 0.25 LSb
- 16-bit mode: 0.5 LSb
-18-bit mode: 1 LSb.
REGISTER 5-25: ADDRESS 0X67 – DIGITAL OFFSET CORRECTION (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIG_OFFSET_GLOBAL<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_OFFSET_GLOBAL<15:8>: Upper byte of DIG_OFFSET_GLOBAL<15:0> for all channels(1)
0000-0000 = Default
Note 1: See Note 1 in Address 0x66 (Register 5-24)
2014-2016 Microchip Technology Inc. DS20005322D-page 100
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-26: ADDRESS 0X68 – WCK/OVR AND DM1/DM2
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
FCB<3:0> POL_WCK_OVR EN_WCK_OVR DM1DM2 POL_DM1DM2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 3 POL_WCK_OVR: Polarity control for WCK and OVR bit pair in LVDS mode
1 = Inverted
0 = Not inverted (Default)
bit 2 EN_WCK_OVR: Enable WCK and OVR output bit pair
1 = Enabled (Default)
0 = Disabled
bit 1 DM1DM2: Add two additional LSb bits (DM1/DM+ and DM2/DM- bits) to the output(1)
1 = Added
0 = Not added (Default)
bit 0 POL_DM1DM2: Polarity control for DM1/DM+ and DM2/DM- pair in LVDS mode(1)
1 = Inverted
0 = Not inverted (Default)
Note 1: Applicable for 16-bit mode only: When this bit is set and the decimation is used, two additional LSb bits (DM1/DM+ and DM2/DM-,
DM2/DM- is the LSb) can be added and result in 18-bit resolution. See Addresses 0x7B and 0x7C (Registers 5-35 and 5-36) for the
decimation filter settings. See Address 0x63 (Register 5-21) for the output bit control.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 101 2014-2016 Microchip Technology Inc.
REGISTER 5-27: ADDRESS 0X6B – PLL CALIBRATION
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
FCB<6:2> PLL_CAL_TRIG FCB<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 FCB<6:2>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 2 PLL_CAL_TRIG: Manually force recalibration of the PLL at the state of bit transition(1)
Toggle from “1” to “0”, or “0” to “1” = Start PLL calibration
bit 1-0 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not program.
Note 1: See PLL_CAL_STAT in Address 0xD1 (Register 5-80) for calibration status indication.
REGISTER 5-28: ADDRESS 0X6D – PLL OUTPUT AND OUTPUT CLOCK PHASE(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
─EN_PLL_CLK FCB<1> DCLK_DLY_PLL<2:0> FCB<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Not used
bit 5 EN_PLL_CLK: Enable PLL output clock
1 = PLL output clock is enabled to the ADC core
0 = PLL clock output is disabled (Default)
bit 4 FCB<1>: Factory-Controlled Bit. This is not for the user. Do not change default settings.
bit 3-1 DCLK_DLY_PLL<2:0>: Output clock is delayed by the number of VCO clock cycles from the nominal PLL output(2)
111 = Delay of 15 cycles
110 = Delay of 14 cycles
• • •
001 = Delay of one cycle
000 = No delay (Default)
bit 0 FCB<0>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
Note 1: This register has effect only when the PLL clock is selected by the CLK_SOURCE bit in Address 0x53
(Register 5-8) and PLL circuit is enabled by EN_PLL bit in Address 0x59 (Register 5-14).
2: This bit setting enables the output clock phase delay. This phase delay control option is applicable when PLL is
used as the clock source and the decimation is not used.
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MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-29: ADDRESS 0X74 – USER-DEFINED OUTPUT PATTERN A (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_A<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PATTERN_A<7:0>: Lower byte of PATTERN_A<15:0>(1)
Note 1: See PATTERN_A<15:8> in Address 0x75 (Register 5-30) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20). If ADC
resolution is less than 16-bit, some LSbs are not used. Unused LSb = 16-n, where n = resolution. Leave the unused LSb bits as 0s.
REGISTER 5-30: ADDRESS 0X75 – USER-DEFINED OUTPUT PATTERN A (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_A<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PATTERN_A<15:8>: Upper byte of PATTERN_A<15:0>(1)
Note 1: See PATTERN_A<7:0> in Address 0x74 (Register 5-29) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
REGISTER 5-31: ADDRESS 0X76 – USER-DEFINED OUTPUT PATTERN B (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_B<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PATTERN_B<7:0>: Lower byte of PATTERN_B<15:0>(1)
Note 1: See PATTERN_B<15:8> in Address 0x77 (Register 5-32) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20). If ADC
resolution is less than 16-bit, some LSbs are not used. Unused LSb = 16-n, where n = resolution. Leave the unused LSb bits as 0s.
REGISTER 5-32: ADDRESS 0X77 – USER-DEFINED OUTPUT PATTERN B (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_B<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PATTERN_B<15:8>: Upper byte of PATTERN_B<15:0>(1)
Note 1: See PATTERN_B<7:0> in Address 0x76 (Register 5-31) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 103 2014-2016 Microchip Technology Inc.
REGISTER 5-33: ADDRESS 0X79 – DUAL-CHANNEL DIGITAL SIGNAL POST-PROCESSING CONTROL
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EN_DSPP_2 FCB<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_DSPP_2: Enable all digital post-processing functions for dual-channel operations
1 = Enabled
0 = Disabled (Default)
bit 6-0 FCB<6:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
REGISTER 5-34: ADDRESS 0X7A – FRACTIONAL DELAY RECOVERY AND FIR_A0(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCB<5> FIR_A<0> EN_FDR FCB<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FCB<5>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
bit 6 FIR_A<0>: Enable the first 2x decimation (Stage 1A in FIR A) in single-channel mode(2)
1 = Enabled
0 = Disabled (Default)
bit 5 EN_FDR: Enable fractional delay recovery (FDR) option
1 = Enabled (with delay of 59 clock cycles).
0 = Disabled (Default)
bit 4-0 FCB<4:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1: This register is used only for single and dual-channel modes.
2: This is the LSb for the FIR A filter settings. For the first 2x decimation, set FIR_A<0> = 1 for single-channel operation, and
FIR_A<0> = 0 for dual-channel operation. See Address 0x7B (Register 5-35) for FIR_A<8:1> settings.
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MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-35: ADDRESS 0X7B – FIR A FILTER(1,5)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FIR_A<8:1>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 FIR_A<8:1>: Decimation Filter FIR A settings for Channel A (or I)(2)
Single-Channel Mode:(3)
FIR_A<8:0> =
1-1111-1111 = Stage 1 - 9 filters (decimation rate: 512)
0-1111-1111 = Stage 1 - 8 filters
0-0111-1111 = Stage 1 - 7 filters
0-0011-1111 = Stage 1 - 6 filters
0-0001-1111 = Stage 1 - 5 filters
0-0000-1111 = Stage 1 - 4 filters
0-0000-0111 = Stage 1 - 3 filters (decimation rate = 8)
0-0000-0011 = Stage 1 - 2 filters (decimation rate = 4)
0-0000-0001 = Stage 1 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
Dual-Channel Mode:(4)
FIR_A<8:0> =
1-1111-1110 = Stage 2 - 9 filters (decimation rate: 256)
0-1111-1110 = Stage 2 - 8 filters
0-0111-1110 = Stage 2 - 7 filters
0-0011-1110 = Stage 2 - 6 filters
0-0001-1110 = Stage 2 - 5 filters
0-0000-1110 = Stage 2 - 4 filters
0-0000-0110 = Stage 2 - 3 filters
0-0000-0010 = Stage 2 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
Note 1: This register is used only for single and dual-channel modes. The register values are thermometer encoded.
2: FIR_A<0> is placed in Address 0x7A (Register 5-34).
3: In single-channel mode, the 1st stage filter is selected by FIR_A<0> = 1 in Address 0x7A (Register 5-34).
4: In dual-channel mode, the 1st stage filter is disabled by setting FIR_A<0> = 0 in Address 0x7A.
5: SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation rate for the single-channel mode is 512, and 256 for the dual-channel mode.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 105 2014-2016 Microchip Technology Inc.
REGISTER 5-36: ADDRESS 0X7C – FIR B FILTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FIR_B<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 FIR_B<7:0>:Decimation Filter FIR B settings for Channel B (or Q)(3)
1111-1111 = Stage 2 - 9 filters (decimation rate = 256)
0111-1111 = Stage 2 - 8 filters
0011-1111 = Stage 2 - 7 filters
0001-1111 = Stage 2 - 6 filters
0000-1111 = Stage 2 - 5 filters
0000-0111 = Stage 2 - 4 filters
0000-0011 = Stage 2 - 3 filters
0000-0001 = Stage 2 filter (decimation rate = 2)
0000-0000 = Disabled all FIR B Filters. (Default)
Note 1: This register is used for the dual-channel mode only. The register values are thermometer encoded.
2: EN_DSPP_2 bit in Address 0x79 (Register 5-34) must be set when using decimation in dual-channel mode.
3: SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation factor for the dual-channel mode is 256.
REGISTER 5-37: ADDRESS 0X7D – AUTO-SCAN CHANNEL ORDER (LOWER BYTE)
R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
CH_ORDER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH_ORDER<7:0>: Lower byte of CH_ORDER<31:0>(1)
0111-1000 = Default
Note 1: See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
REGISTER 5-38: ADDRESS 0X7E – AUTO-SCAN CHANNEL ORDER (MIDDLE BYTE)
R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0
CH_ORDER<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH_ORDER<15:8>: Middle byte of CH_ORDER<31:0>(1)
1010-1100 = Default
Note 1: See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
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MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-39: ADDRESS 0X7F – AUTO-SCAN CHANNEL ORDER (UPPER BYTE)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0
CH_ORDER<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH_ORDER<23:16>: Upper byte of CH_ORDER<31:0>(1)
1000-1110 = Default
Note 1: See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
REGISTER 5-40: ADDRESS 0X80 – DIGITAL DOWN-CONVETER CONTROL 1(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HBFILTER_B HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR EN_DDC_FS/8 EN_DDC1
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 HBFILTER_B: Select half-bandwidth filter at DDC output of channel B in dual-channel mode(2)
1 = Select High-Pass filter at DDC output
0 = Select Low-Pass filter at DDC output (Default)
bit 6 HBFILTER_A: Select half-bandwidth filter at DDC output of channel A(2)
1 = Select High-Pass filter at DDC output
0 = Select Low-Pass filter at DDC output (Default)
bit 5 EN_NCO: Enable NCO of DDC1
1 = Enabled
0 = Disabled (Default)
bit 4 EN_AMPDITH: Enable amplitude dithering for NCO(3, 4)
1 = Enabled
0 = Disabled (Default)
bit 3 EN_PHSDITH: Enable phase dithering for NCO(3, 4)
1 = Enabled
0 = Disabled (Default)
bit 2 EN_LFSR: Enable linear feedback shift register (LFSR) for amplitude and phase dithering for NCO
1 = Enabled
0 = Disabled (Default)
bit 1 EN_DDC_FS/8: Enable NCO for the DDC2 to center the DDC output signal to be around fS/8/DER(5)
1 = Enabled
0 = Disabled (Default)
bit 0 EN_DDC1: Enable digital down converter 1 (DDC1)
1 = Enabled(6)
0 = Disabled (Default)
Note 1: This register is used for single-, dual- and octal-channel modes when CW feature is enabled (8CH_CW = 1).
2: This filter includes a decimation of 2.
-Single-channel mode: HBFILTER_A is used.
-Dual-channel mode: Both HBFILTER_A and HBFILTER_B are used.
3: This requires the LFSR to be enabled: EN_LFSR=1
4: EN_AMPDITH = 1 and EN_PHSDITH = 1 are recommended for the best performance.
5: DER is the decimation rate defined by FIR A or FIR B filter. If up-converter is not enabled (disabled), output is I/Q data.
6: DDC and NCO are enabled. For DDC function, bits 0, 2 and 5 need to be enabled all together.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 107 2014-2016 Microchip Technology Inc.
REGISTER 5-41: ADDRESS 0X81 – DIGITAL DOWN-CONVERTER CONTROL 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FDR_BAND EN_DDC2 GAIN_HBF_DDC SEL_FDR EN_DSPP_8 8CH_CW GAIN_8CH<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FDR_BAND: Select 1st or 2nd Nyquist band
1 = 2nd Nyquist band
0 = 1st Nyquist band (Default)
bit 6 EN_DDC2: Enable DDC2 after the digital half-band filter (HBF) in DDC.
1 = Enabled
0 = Disabled (Default)
bit 5 GAIN_HBF_DDC: Gain selection for the output of the digital half-band filter (HBF) in DDC(1)
1 =x2
0 =x1 (Default)
bit 4 SEL_FDR: Select fractional delay recovery (FDR)
1 = FDR for 8-channel
0 = FDR for dual-channel (Default)
bit 3 EN_DSPP_8: Enable digital signal post-processing (DSPP) features for 8-channel operation(2)
1 = Enabled
0 = Disabled (Default)
bit 2 8CH_CW: Enable CW mode in octal-channel mode(2, 3)
1 = Enabled
0 = Disabled (Default)
bit 1-0 GAIN_8CH<1:0>: Select gain factor for CW signal in octal-channel modes.
11 = x8, 10 = x4, 01 = x2, 00 = x1 (Default)
Note 1: See Section 4.8.2, "Decimation Filters".
2: By enabling this bit, the phase offset corrections in Addresses 0x086 – 0x095 (Registers 5-46 – 5-61) are also enabled.
EN_DSPP_8 is a global setting bit to enable SEL_FDR and LVDS_8CH bits (Address 0x62 - Register 5-20).
3: When CW mode is enabled, the ADC output is the result of the summation (addition) of all eight channels’ data after each
channel’s digital phase offset, digital gain, and digital offset are controlled using the Addresses 0x86 - 0xA7 (Registers 5-46 to
5-78). The result is similar to the beamforming in the phased-array sensors.
2014-2016 Microchip Technology Inc. DS20005322D-page 108
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-42: ADDRESS 0X82 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE <7:0>: Lower byte of NCO_TUNE<31:0>(1)
0000-0000 = DC (0 Hz) when NCO_TUNE<31:0> = 0x00000000 (Default)
Note 1: See Note 1 and Note 2 in Address 0x85 (Register 5-45).
REGISTER 5-43: ADDRESS 0X83 – NUMERICALLY CONTROLLED OSCILLATOR TUNING
(MIDDLE-LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE<15:8>: Middle lower byte of NCO_TUNE<31:0>(1)
0000-0000 = Default
Note 1: See Note 1 and Note 2 in Address 0x85 (Register 5-45).
REGISTER 5-44: ADDRESS 0X84 – NUMERICALLY CONTROLLED OSCILLATOR TUNING
(MIDDLE-UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE<23:16>: Middle upper byte of NCO_TUNE<31:0>(1)
0000-0000 = Default
Note 1: See Note 1 and Note 2 in Address 0x85 (Register 5-45).
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 109 2014-2016 Microchip Technology Inc.
REGISTER 5-45: ADDRESS 0X85 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<31:24>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE<31:24>: Upper byte of NCO_TUNE<31:0>(1,2)
1111-1111 = fS if NCO_TUNE<31:0> = 0xFFFF FFFF
• • •
0000-0000 = Default
Note 1: This Register is used only when DDC is enabled: EN_DDC1 = 1 in Address 0x80 (Register 5-40). See Section 4.8.3.3,
"Numerically Controlled Oscillator (NCO)" for the details of NCO.
2: NCO frequency = (NCO_TUNE<31:0>/232) x fS, where fS is the sampling clock frequency.
REGISTER 5-46: ADDRESS 0X86 – CH0 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH0_NCO_PHASE<7:0>: Lower byte of CH0_NCO_PHASE<15:0>(1,2,3)
1111-1111 = 1.4° when CH0_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: This register is not used in the MCP37231/21. In the MCP37D31/D21, this register has an effect when the following modes are
used:
- CW with DDC mode in octal-channel mode
- Single and dual-channel mode with DDC.
2: CH0 is the 1st channel selected by CH_ORDER<23:0>.
3: CH(n)_NCO_PHASE<15:0> = 216 x Phase Offset Value/360.
2014-2016 Microchip Technology Inc. DS20005322D-page 110
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-47: ADDRESS 0X87: CH0 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH0_NCO_PHASE<15:8>: Upper byte of CH0_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH0_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46.
REGISTER 5-48: ADDRESS 0X88 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH1_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH1_NCO_PHASE<7:0>: Lower byte of CH1_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH1_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-49: ADDRESS 0X89 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH1_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH1_NCO_PHASE <15:8>: Upper byte of CH1_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH1_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 111 2014-2016 Microchip Technology Inc.
REGISTER 5-50: ADDRESS 0X8A – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH2_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH2_NCO_PHASE<7:0>: Lower byte of CH2_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH2_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH2_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-51: ADDRESS 0X8B – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH2_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH2_NCO_PHASE <15:8>: Upper byte of CH2_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH2_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH2_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-52: ADDRESS 0X8C – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH3_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH3_NCO_PHASE<7:0>: Lower byte of CH3_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH3_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH3_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
2014-2016 Microchip Technology Inc. DS20005322D-page 112
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-53: ADDRESS 0X8D – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH3_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH3_NCO_PHASE <15:8>: Upper byte of CH3_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH3_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH3_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-54: ADDRESS 0X8E – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH4_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH4_NCO_PHASE<7:0>: Lower byte of CH4_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH4_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH4_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH4 is the 5th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-55: ADDRESS 0X8F – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH4_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH4_NCO_PHASE <15:8>: Upper byte of CH4_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH4_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH4_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH4 is the 5th channel selected by CH_ORDER<23:0> bits.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 113 2014-2016 Microchip Technology Inc.
REGISTER 5-56: ADDRESS 0X90 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH5_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH5_NCO_PHASE<7:0>: Lower byte of CH5_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH5_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-57: ADDRESS 0X91 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH5_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH5_NCO_PHASE <15:8>: Upper byte of CH5_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH5_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-58: ADDRESS 0X92 – CH6 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH6_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH6_NCO_PHASE<7:0>: Lower byte of CH6_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH6_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH6_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH6 is the 7th channel selected by CH_ORDER<23:0> bits.
2014-2016 Microchip Technology Inc. DS20005322D-page 114
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-59: ADDRESS 0X93 – CH6 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH6_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH6_NCO_PHASE <15:8>: Upper byte of CH6_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH6_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH6_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH6 is the 7th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-60: ADDRESS 0X94 – CH7 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH7_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH7_NCO_PHASE<7:0>: Lower byte of CH7_NCO_PHASE<15:0>(1)
1111-1111 = 1.4° when CH7_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000 = 0° when CH7_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH7 is the 8th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-61: ADDRESS 0X95 – CH7 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH7_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH7_NCO_PHASE <15:8>: Upper byte of CH7_NCO_PHASE<15:0>(1)
1111-1111 = 359.995° when CH7_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when CH7_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH7 is the 8th channel selected by CH_ORDER<23:0> bits.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 115 2014-2016 Microchip Technology Inc.
REGISTER 5-62: ADDRESS 0X96 – CH0 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH0_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH0_DIG_GAIN<7:0>: Digital gain setting for channel 0(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH0 is the 1st channel selected by CH_ORDER<23:0>.
2: Max = 0x7F(3.96875), Min = 0x80 (-4), Step size = 0x01 (0.03125). Bits from 0x81-0xFF are two’s complementary of 0x00-
0x80. Negative gain setting inverts output. See Addresses 0x7D - 0x7F (Registers 5-37 – 5-39) for channel selection.
2014-2016 Microchip Technology Inc. DS20005322D-page 116
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-63: ADDRESS 0X97 – CH1 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH1_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH1_DIG_GAIN<7:0>: Digital gain setting for channel 1(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH1 is the 2nd channel selected by CH_ORDER<23:0>.
2: See Note 2 in Register 5-62.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 117 2014-2016 Microchip Technology Inc.
REGISTER 5-64: ADDRESS 0X98 – CH2 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH2_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH2_DIG_GAIN<7:0>: Digital gain setting for channel 2(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
2: See Note 2 in Register 5-62.
2014-2016 Microchip Technology Inc. DS20005322D-page 118
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-65: ADDRESS 0X99 – CH3 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH3_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH3_DIG_GAIN<7:0>: Digital gain setting for channel 3(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
2: See Note 2 in Register 5-62.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 119 2014-2016 Microchip Technology Inc.
REGISTER 5-66: ADDRESS 0X9A – CH4 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH4_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH4_DIG_GAIN<7:0>: Digital gain setting for channel 4(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH4 is the 5th channel selected by CH_ORDER<23:0>.
2: See Note 2 in Register 5-62.
2014-2016 Microchip Technology Inc. DS20005322D-page 120
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-67: ADDRESS 0X9B – CH5 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH5_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH5_DIG_GAIN<7:0>: Digital gain setting for channel 5(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH5 is the 6th channel selected by CH_ORDER<23:0>.
2: See Note 2 in Register 5-62.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 121 2014-2016 Microchip Technology Inc.
REGISTER 5-68: ADDRESS 0X9C – CH6 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH6_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH6_DIG_GAIN<7:0>: Digital gain setting for channel 6(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH6 is the 7th channel selected by CH_ORDER<23:0>.
2: See Note 2 in Register 5-62.
2014-2016 Microchip Technology Inc. DS20005322D-page 122
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-69: ADDRESS 0X9D – CH7 DIGITAL GAIN
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
CH7_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH7_DIG_GAIN<7:0>: Digital gain setting for channel 7(1,2)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH7 is the 8th channel selected by CH_ORDER<23:0>.
2: See Note 2 in Register 5-62.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 123 2014-2016 Microchip Technology Inc.
REGISTER 5-70: ADDRESS 0X9E – CH0 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH0_DIG_OFFSET <7:0>: Digital offset setting bits for channel 0(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Table 4-18 for the corresponding channel. Offset value is two’s complement. This value is multiplied by DIG_OFFSET_-
WEIGHT<1:0> in Address 0xA7 (Register 5-78).
REGISTER 5-71: ADDRESS 0X9F – CH1 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH1_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH1_DIG_OFFSET <7:0>: Digital offset setting bits for channel 1(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-70.
REGISTER 5-72: ADDRESS 0XA0 – CH2 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH2_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH2_DIG_OFFSET <7:0>: Digital offset setting bits for channel 2(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-70.
2014-2016 Microchip Technology Inc. DS20005322D-page 124
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-73: ADDRESS 0XA1 – CH3 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH3_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH3_DIG_OFFSET <7:0>: Digital offset setting bits for channel 3(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-70.
REGISTER 5-74: ADDRESS 0XA2 – CH4 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH4_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH4_DIG_OFFSET <7:0>: Digital offset setting bits for channel 4(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-70.
REGISTER 5-75: ADDRESS 0XA3 – CH5 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH5_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH5_DIG_OFFSET <7:0>: Digital offset setting bits for channel 5(1)
1111-1111 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-70.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 125 2014-2016 Microchip Technology Inc.
REGISTER 5-76: ADDRESS 0XA4 – CH6 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH6_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH6_DIG_OFFSET <7:0>: Digital offset setting bits for channel 6(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-70.
REGISTER 5-77: ADDRESS 0XA5 – CH7 DIGITAL OFFSET
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH7_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CH7_DIG_OFFSET <7:0>: Digital offset setting bits for channel 7(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-70.
REGISTER 5-78: ADDRESS 0XA7 – DIGITAL OFFSET WEIGHT CONTROL
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
FCB<5:3> DIG_OFFSET_WEIGHT<1:0> FCB<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 FCB<5:3>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
bit 4-3 DIG_OFFSET_WEIGHT<1:0>: Control the weight of the digital offset settings(1)
11 = 2 LSb x Digital Gain
10 = LSb x Digital Gain
01 = LSb/2 x Digital Gain
00 = LSb/4 x Digital Gain, (Default)
bit 2-0 FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1: This bit setting is used for the digital offset setting registers in Addresses 0x9E - 0xA7 (Registers 5-70 – 5-78).
2014-2016 Microchip Technology Inc. DS20005322D-page 126
MCP37231/21-200 AND MCP37D31/21-200
REGISTER 5-79: ADDRESS 0XC0 – CALIBRATION STATUS INDICATION
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
ADC_CAL_STAT FCB<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADC_CAL_STAT: Power-up auto-calibration status indication flag bit
1 = Device power-up calibration is completed
0 = Device power-up calibration is not completed
bit 6-0 FCB<6:0>: Factory-Controlled Bits. These bits are read only, and have no meaning for the user.
REGISTER 5-80: ADDRESS 0XD1 – PLL CALIBRATION STATUS AND PLL DRIFT STATUS INDICATION
R-x R-x R-x R-x R-x R-x R-x R-x
FCB<4:3> PLL_CAL_STAT FCB<2:1> PLL_VCOL_STAT PLL_VCOH_STAT FCB<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 FCB<4:3>: Factory-controlled bits. These bits are read only, and have no meaning for the user.
bit 5 PLL_CAL_STAT: PLL auto-calibration status indication flag bit(1)
1 = Complete: PLL auto-calibration is completed
0 = Incomplete: PLL auto-calibration is not completed
bit 4-3 FCB<2:1>: Factory-controlled bits. These bits are read only, and have no meaning for the user.
bit 2 PLL_VCOL_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with low VCO frequency
0 = PLL operates as normal
bit 1 PLL_VCOH_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with high VCO frequency
0 = PLL operates as normal
bit 0 FCB<0>: Factory-Controlled Bit. This bit is readable, but has no meaning for the user.
Note 1: See PLL_CAL_TRIG bit setting in Address 0x6B (Register 5-27).
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 127 2014-2016 Microchip Technology Inc.
REGISTER 5-81: ADDRESS 0X15C – CHIP ID (LOWER BYTE)
R-x R-x R-x R-x R-x R-x R-x R-x
CHIP_ID<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CHIP_ID<7:0>: Device identification number. Lower byte of the CHIP ID<15:0>(1)
Note 1: Read-only register. Preprogrammed at the factory for internal use.
Example: MCP37231-200: ‘0000 1000 0111 0000’
MCP37221-200: ‘0000 1000 0101 0000’
MCP37D31-200: ‘0000 1010 0111 0000’
MCP37D21-200: ‘0000 1010 0101 0000’
REGISTER 5-82: ADDRESS 0X15D – CHIP ID (UPPER BYTE)
R-x R-x R-x R-x R-x R-x R-x R-x
CHIP_ID<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CHIP_ID<15:8>: Device identification number. Lower byte of the CHIP ID<15:0>(1)
Note 1: See Note 1 in Register 5-81.
2014-2016 Microchip Technology Inc. DS20005322D-page 128
MCP37231/21-200 AND MCP37D31/21-200
6.0 DEVELOPMENT SUPPORT
Microchip offers a high-speed ADC evaluation platform
which can be used to evaluate Microchip’s high-speed
ADC products. The platform consists of an MCP37XXX
evaluation board, an FPGA-based data capture card
board, and PC-based Graphical User Interface (GUI)
software for ADC configuration and evaluation.
Figure 6-1 and Figure 6-2 show this evaluation tool.
This evaluation platform allows users to quickly
evaluate the ADC’s performance for their specific
application requirements. More information is available
at http://www.microchip.com.
FIGURE 6-1: MCP37XXX Evaluation Kit.
FIGURE 6-2: PC-Based Graphical User Interface Software.
(a) MCP37XXX-200 Evaluation Board (b) Data Capture Board
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 129 2014-2016 Microchip Technology Inc.
NOTES:
2014-2016 Microchip Technology Inc. DS20005322D-page 130
MCP37231/21-200 AND MCP37D31/21-200
7.0 TERMINOLOGY
Analog Input Bandwidth (Full-Power
Bandwidth)
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty
The sample-to-sample variation in aperture delay.
Aperture Delay Jitter
The variation in the aperture delay time from
conversion to conversion. This random variation will
result in noise when sampling an AC input. The
signal-to-noise ratio due to the jitter alone will be:
EQUATION 7-1:
Calibration Algorithms
This device utilizes two patented analog and digital
calibration algorithms, Harmonic Distortion Correction
(HDC) and DAC Noise Cancellation (DNC), to improve
the ADC performance. The algorithms compensate
various sources of linear impairments such as
capacitance mismatch, charge injection error and finite
gain of operational amplifiers. These algorithms
execute in both power-up sequence (foreground) and
background mode:
• Power-Up Calibration: The calibration is
conducted within the first 227 clock cycles after
power-up. The user needs to wait this Power-Up
Calibration period after the device is powered-up
for an accurate ADC performance.
• Background Calibration: This calibration is
conducted in the background while the ADC
performs conversions. The update rate is about
every 230 clock cycles.
Channel Crosstalk
This is a measure of the internal coupling of a signal
from an adjacent channel into the channel of interest in
the multi-channel mode. It is measured by applying a
full-scale input signal in the adjacent channel.
Crosstalk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest)
to the power of the signal applied at the adjacent
channel input. It is typically expressed in dBc.
Pipeline Delay (LATENCY)
LATENCY is the number of clock cycles between the
initiation of conversion and when that data is presented
to the output driver stage. Data for any given sample is
available after the pipeline delay plus the output delay
after that sample is taken. New data is available at
every clock cycle, but the data lags the conversion by
the pipeline delay plus the output delay. Latency is
increased if digital signal post-processing is used.
Clock Pulse Width and Duty Cycle
The clock duty cycle is the ratio of the time the clock
signal remains at a logic high (clock pulse width) to one
clock period. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock
results in a 50% duty cycle.
Differential Nonlinearity
(DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly
1 LSb apart. DNL is the deviation from this ideal value.
No missing codes to 16-bit resolution indicates that all
65,536 codes must be present over all the operating
conditions.
Integral Nonlinearity (INL)
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
EQUATION 7-2:
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of
the fundamental is extrapolated to the converter
full-scale range.
SNRJITTER 20 2
fIN tJITTER
log–=
SNR 10 PS
PN
-------
log=
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 131 2014-2016 Microchip Technology Inc.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
EQUATION 7-3:
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
EQUATION 7-4:
Gain Error
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range.
Gain error is usually expressed in LSb or as a
percentage of full-scale range (%FSR).
Gain-Error Drift
Gain-error drift is the variation in gain-error due to a
change in ambient temperature, typically expressed in
ppm/°C.
Offset Error
The major carry transition should occur for an analog
value of 50% LSb below AIN+=A
IN−. Offset error is
defined as the deviation of the actual transition from
that point.
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value across the TMIN to TMAX range.
Maximum Conversion Rate
The maximum clock rate at which parametric testing is
performed.
Minimum Conversion Rate
The minimum clock rate at which parametric testing is
performed.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 7-5:
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 7-6:
Two-Tone Intermodulation Distortion
(Two-Tone IMD, IMD3)
Two-tone IMD is the ratio of the power of the
fundamental (at frequencies fIN1 and fIN2) to the power
of the worst spectral component at either frequency
2fIN1 –f
IN2 or 2fIN2 –f
IN1. Two-tone IMD is a function of
the input amplitudes and frequencies (fIN1 and fIN2). It
is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of
the fundamental is extrapolated to the ADC full-scale
range.
SINAD 10 PS
PDPN
+
----------------------
log=
10–=10
SNR
10
-----------–10
THD
10
------------–
–log
ENOB SINAD 1.76–
6.02
----------------------------------=
THD 10 PS
PD
--------
log=
THD 20 V2
2V3
2V4
2
Vn
2
++++
V1
2
------------------------------------------------------------------log–=
Where:
V1= RMS amplitude of the
fundamental frequency
V1 through Vn= Amplitudes of the second
through nth harmonics
2014-2016 Microchip Technology Inc. DS20005322D-page 132
MCP37231/21-200 AND MCP37D31/21-200
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The common-mode signal can be
an AC or DC signal or a combination of the two. CMRR
is measured using the ratio of the differential signal
gain to the common-mode signal gain and expressed in
dB with the following equation:
EQUATION 7-7:
CMRR 20 ADIFF
ACM
------------------
log=
Where:
ADIFF =Output Code/Differential Voltage
ADIFF =Output Code/Common Mode Voltage
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 133 2014-2016 Microchip Technology Inc.
NOTES:
2014-2016 Microchip Technology Inc. DS20005322D-page 134
MCP37231/21-200 AND MCP37D31/21-200
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
A1
A1
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
124-Lead VTLA (9x9x0.9 mm) Example
MCP37231
200-I/TL
^^
1417256
3
e
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 135 2014-2016 Microchip Technology Inc.
2014-2016 Microchip Technology Inc. DS20005322D-page 136
MCP37231/21-200 AND MCP37D31/21-200
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 137 2014-2016 Microchip Technology Inc.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
RECOMMENDED LAND PATTERN
SILK SCREEN
Dimension Limits
Units
C1
Optional Center Pad Length
Contact Pad Spacing
Contact Pad Spacing
Optional Center Pad Chamfer (X4)
C2
W3
W2
0.10
6.60
MILLIMETERS
MIN MAX
8.50
8.50
Contact Pad Length (X124)
Contact Pad Width (X124)
X2
X1
0.30
0.30
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2193A
NOM
Optional Center Pad Width T2
Contact to Center Pad Clearance (X4) G5
Pad Clearance G4
Pad Clearance G3
Pad Clearance G2
Contact Pitch 0.50 BSCE
Pad Clearance G1
6.60
0.30
0.20
0.20
0.20
0.20
E
E/2
W2
W3
G2
G4
X1
G5
X4
C2
C1
G3
G1
X2
E
T2
124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA]
2014-2016 Microchip Technology Inc. DS20005322D-page 138
MCP37231/21-200 AND MCP37D31/21-200
B
A
0.15 C
0.15 C
C
SEATING
PLANE
2X
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.10 C
D
E
2X
NOTE 1
(DATUM A)
(DATUM B)
A
A1
A2
0.10 C
SIDE VIEW
TOP VIEW
1234567891011
E1
eE
A
B
C
D
E
F
G
H
J
K
L
DETAIL A
Microchip Technology Drawing C04-212A Sheet 1 of 2
D1
eD
A1 BALL PAD CORNER
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 139 2014-2016 Microchip Technology Inc.
Microchip Technology Drawing C04-212A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
Notes:
Terminal A1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M
0.15 C A B
0.08 C
121X Øb
Number of Terminals
Overall Height
Terminal Diameter
Overall Width
Overall Length
Overall Pitch
Overall Pitch
Cap Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E1
D1
A2
eE
E
N
0.65 BSC
0.45
.035
-
0.21
0.40
8.00 BSC
6.50 BSC
6.50 BSC
-
0.32
8.00 BSC
MILLIMETERS
MIN NOM
121
0.45
1.08
-
MAX
Pitch eD 0.65 BSC
0.40 0.50
DETAIL A
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
2014-2016 Microchip Technology Inc. DS20005322D-page 140
MCP37231/21-200 AND MCP37D31/21-200
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
SILK SCREEN
Dimension Limits
Units
C1Contact Pad Spacing
Contact Pad Spacing
Contact Pitch
C2
MILLIMETERS
0.65 BSC
MIN
E
MAX
6.50
6.50
Contact Pad Diameter (X121) B 0.35
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2212B-TE
NOM
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
E
121X ØB
C2
E
C1
System In Package
2014-2016 Microchip Technology Inc. DS20005322D-page 141
MCP37231/21-200 AND MCP37D31/21-200
APPENDIX A: REVISION HISTORY
Revision D (August 2016)
The following is the list of modifications:
• Updated availability of TFBGA package.
• Added Figure 2-7, Figure 2-8 and Figure 2-9.
• Added Section 4.15, AutoSync Mode:
Synchronizing Multiple ADCs at the Same
Clock using Master and Slave Configuration.
Revision C (July 2015)
• Updated some default settings for register bits
and input leakage current specification (ILI_CKLI).
Revision B (September 2014)
• Removed the non-availability notes related to the
14-bit option.
Revision A (July 2014)
• Original release of this document.
MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 142 2014-2016 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX-XXX
Sample PackageTemperature
Range
Device
Device: MCP37231-200: 16-Bit Low-Power ADC with 8-Channel MUX
MCP37D31-200: 16-Bit Low-Power ADC with 8-Channel MUX,
Digital Down-Converter and CW Beamforming
MCP37221-200: 14-Bit Low-Power ADC with 8-Channel MUX
MCP37D21-200: 14-Bit Low-Power ADC with 8-Channel MUX,
Digital Down-Converter and CW Beamforming
Tape and
Reel Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Sample Rate: 200 = 200 Msps
Temperature
Range:
I= -40C to +85C (Industrial)
Package: TL = Terminal Very Thin Leadless Array Package -
9x9x0.9 mm Body (VTLA), 124-Lead
TE = Ball Plastic Thin Profile Fine Pitch Ball Grid Array -
8x8x1.08 mm Body (TFBGA), 121-Lead
Note 1: Tape and Reel identifier appears only in the
catalog part number description. This identifier
is used for ordering purposes and is not printed
on the device package. Check with your
Microchip Sales Office for package availability
with the Tape and Reel option.
[X](1)
Tape and Reel
Option Rate
Examples:
a) MCP37D31-200I/TL: 124LD VTLA, 200 Msps
b) MCP37D31-200I/TE: 121LD TFBGA, 200 Msps
c) MCP37231T-200I/TL: Tape and Reel,
Industrial temperature,
124LD VTLA, 200 Msps
2014-2016 Microchip Technology Inc. DS20005322D-page 143
MCP37231/21-200 AND MCP37D31/21-200
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0864-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece ived IS O/T S-16 94 9:20 09 certificat ion for its worldwi d e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC ® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005322D-page 144 2014-2016 Microchip Technology Inc.
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