8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
1
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8535I-01 is a low skew, high performance 1-to-4
LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The
ICS8535I-01 has two single ended clock inputs. the single
ended clock input accepts LVCMOS or LVTTL input levels
and translate them to 3.3V LVPECL levels. The clock
enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535I-01 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
•Four differential 3.3V LVPECL outputs
•Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
•CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
•Maximum output frequency: 266MHz
•Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
•Output skew: 30ps (maximum)
•Part-to-part skew: 250ps (maximum)
•Propagation delay: 1.9ns (maximum)
•Jitter, RMS: < 0.09ps (typical)
•3.3V operating supply
•-40°C to 85°C ambient operating temperature
•Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8535I-01
20-Lead TSSOP
4.4mm x 6.5mm x 0.92mm body package
G Package
Top View
VEE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
nQ3
CLK0
CLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
2
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
rebmuNemaNepyTnoitpircseD
1V
EE
rewoP.nipylppusevitageN
2NE_KLCtupnIpulluP
.tupnikcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
.
hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW
.slevelecafretniLTTVL/SOMCVL
3LES_KLCtupnInwodlluP .tup
ni1KLCstceles,HGIHnehW.tupnitceleskcolC
.slevelecafretniLTTVL/SOMCVL.tupni0KLCstceles,WOLnehW
40KLCtupnInw
odlluP.tupnikcolcLTTVL/SOMCVL
61KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
9,8,7,5cndesunU.tcennocoN
81,31,01V
CC
rewoP.snipylppusevitisoP
21,113Q,3QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
51,412Q,2QntuptuO.slev
elecafretniLCEPVL.riaptuptuolaitnereffiD
71,611Q,1QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
02
,910Q,0QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
3
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
1KLCro0KLC3Q:0Q3Qn:0Qn
0WOLHGIH
1HGIHWOL
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS3Q:0Q3Qn:0Qn
00 0KLCWOL;delbasiDHGIH;delbasiD
01 1KLCWOL;delbasiDHGIH;delbasiD
10 0KLCdelbanEdelbanE
11 1KLCdelbanEdelbanE
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokc
olceht,sehctiwsNE_KLCretfA
debircsedsastupni1KLCdna0KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitc
aehtnI.1erugiFniwohssa
.B3elbaTni
FIGURE 1. CLK_EN TIMING DIAGRAM
Enabled
Disabled
CLK0, CLK1
CLK_EN
nQ0:nQ3
Q0:Q3
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
4
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP 531.33.3564.3V
I
EE
tnerruCylppuSrewoP 55Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 1KLC,0KLC2V
CC
3.0+V
LES_KLC,NE_KLC2V
CC
3.0+V
V
LI
egatloVwoLtupnI 1KLC,0KLC3.0-3.1V
LES_KLC,NE_KLC3.0-8.0V
I
HI
tnerruChgiHtupnI LES_KLC,1KLC,0KLCV
NI
V=
CC
V564.3=051Aµ
NE_KLCV
NI
V=
CC
V564.3=5Aµ
I
LI
tnerruCwoLtupnI LES_KLC,1KLC,0KLCV
NI
V,V0=
CC
V564.3=5-Aµ
NE_KLCV
NI
V,V0=
CC
V564.3=051-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
CC
4.1-9.0V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
CC
.V2-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
5
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
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XAM
ycneuqerFtuptuO 662zHM
t
DP
1ETON;yaleDnoitagaporPIJzHM6620.19.1sn
t
)o(ks4,2ETON;wekStuptuO 03sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 052sp
t
tij ;SMR,rettiJesahPevitiddAreffuB
noitcesrettiJesahPevitiddAotrefer 90.0sp
t
R
t/
F
emiTllaF/esiRtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO 840525%
.esiwrehtodetonsselnuzHM662taderusaemsretem
arapllA
.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcycehT
Vehtmor
fderusaeM:1ETON
CC
.tniopgnissorctuptuolaitnereffidehtottupniehtfo2/
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastu
ptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
daollauqehtiwdnasegatlovylpp
usemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
.stniopssorclaitnereffidehttad
erusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnoc
.56dradnatSCEDEJhtiwecnadroccanid
enifedsiretemarapsihT:4ETON
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
6
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
Additive Phase Jitter at
156.25MHz = 0.09ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the
fundamental frequency to the power value of the fundamental.
This ratio is expressed in decibels (dBm) or a ratio of the power
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
in the 1Hz band to the power in the fundamental. When the
required offset is specified, the phase noise is called a
dBc
value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired ap-
plication over the entire time record of the signal. It is math-
ematically possible to calculate an expected bit error rate given
a phase noise plot.
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source
and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
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ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
OUTPUT RISE/FALL TIME
PROPAGATION DELAY OUTPUT DUTY CYCLE/ PULSE WIDTH/PERIOD
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V ± 0.165V
tsk(o)
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWI NG
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Q0:Q3
nQ0:nQ3
t
PD
CLK0,
CLK1
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
PART-TO-PART SKEW
Q0:Q3
nQ0:nQ3
VCC
VEE
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
8
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 2A and 2B
show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION
TERMINATION FOR LVPECL OUTPUTS
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT:
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
9
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 3
shows a schematic example of the ICS8535I-01. In
this example, the CLK0 input is selected. The decoupling ca-
pacitors should be physically located near the power pin. For
ICS8535I-01, the unused clock outputs can be left floating.
FIGURE 3. ICS8535I-01 LVPECL BUFFER SCHEMATIC EXAMPLE
Zo = 50
Zo = 50
3.3V
R9
50
+
-
R1
50
R3
50
C1
0.1u
3.3V
+
-
U1
ICS8535-01
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
20
19
18
17
VEE
CLK_EN
CLK_SEL
CLK0
NC
CLK1
NC
NC
NC
VCC nQ3
Q3
VCC
nQ2
Q2
nQ1
Q0
nQ0
VCC
Q1
R2
50
Zo = 50 Ohm
Ro ~ 7 Ohm
Q1
LVCMOS
Zo = 50
R12
1K
3.3V
Zo = 50
3.3V
R7
50
C3
0.1u
R13 43
3.3V
C2
0.1u
R11
1K 3.3V
R8
50
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
10
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.6mW
•Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 x 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 120mW = 310.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.311W * 66.6°C/W = 105.7°C. This is well below the limit of 125°C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 20-PIN TSSOP, FORCED CONVECTION
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
11
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCC_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
12
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8535I-01 is: 412
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
13
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
14
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
<
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
15
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
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8535AGI-01 www.idt.com REV. F OCTOBER 4, 2010
16
ICS8535I-01
LOW SKEW, 1-TO-4
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
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