_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Stereo Audio CODEC
with FlexSound Technology
MAX9888
19-5235; Rev 1; 2/11
Simplified Block Diagram
General Description
The MAX9888 is a full-featured audio CODEC whose
high performance and low power consumption make it
ideal for portable applications.
Class D speaker amplifiers provide efficient amplification
for two speakers. Low radiated emissions enable com-
pletely filterless operation. Integrated bypass switches
optionally connect an external amplifier to the transducer
when the Class D amplifiers are disabled.
DirectDrive® headphone amplifiers provide a true
ground-referenced output, eliminating the need for
large DC-blocking capacitors. 1.8V headphone opera-
tion ensures low power consumption. The device also
includes a differential receiver amplifier.
Three differential analog microphone inputs are available
as well as support for two PDM digital microphones.
Integrated switches allow microphone signals to be
routed out to external devices. Two flexible single-ended
or differential line inputs may be connected to an FM
radio or other sources.
Integrated FlexSoundK technology improves loud-
speaker performance by optimizing the signal level and
frequency response while limiting the maximum distor-
tion and power at the output to prevent speaker damage.
Automatic gain control (AGC) and a noise gate optimize
the signal level of microphone input signals to make best
use of the ADC dynamic range.
The device is fully specified over the -40NC to +85NC
extended temperature range.
Features
S 100dB DR Stereo DAC (8kHz < fS < 96kHz)
S 91dB DR Stereo ADC (8kHz < fS < 96kHz)
S Stereo Low EMI Class D Amplifiers
950mW/Channel (8I, VSPKVDD_ = 4.2V)
S Stereo DirectDrive Headphone Amplifiers
S Differential Receiver Amplifier
S 2 Stereo Single-Ended/Mono Differential Line
Inputs
S 3 Differential Microphone Inputs
S FlexSound Technology
5-Band Parametric EQ
Automatic Level Control (ALC)
Excursion Limiter
Speaker Power Limiter
Speaker Distortion Limiter
Microphone Automatic Gain Control
and Noise Gate
S Dual I2S/PCM/TDM Digital Audio Interfaces
S Asynchronous Digital Mixing
S Supports Master Clock Frequencies from 10MHz
to 60MHz
S RF Immune Analog Inputs and Outputs
S Extensive Click-and-Pop Reduction Circuitry
S I2C Control Interface
S 63 WLP Package (3.80mm x 3.30mm, 0.4mm Pitch)
+Denotes lead(Pb)-free/RoHS-compliant package.
Ordering Information
DirectDrive is a registered trademark and FlexSound is a
trademark of Maxim Integrated Products, Inc.
PART TEMP RANGE PIN-PACKAGE
MAX9888EWY+ -40NC to +85NC63 WLP
DAC
DAC
MIX
RECEIVER AMP
SPEAKER AMP
SPEAKER AMP
HEADPHONE AMP
HEADPHONE AMP
ADC
ADC
MIX
FlexSound TECHNOLOGY
• 5-BAND PARAMETRIC EQ
• AUTOMATIC LEVEL CONTROL
• LOUDSPEAKER PROCESSING
• EXCURSION LIMITER
• THD LIMITER
• POWER LIMITER
• MICROPHONE PROCESSING
• AUTOMATIC GAIN CONTROL
• NOISE GATE
• ASYNCHRONOUS DIGITAL
MIXING
DIGITAL MICROPHONE
INPUT
+
+
I2C
CONTROL
I2S/PCM
DIGITAL
AUDIO
INTERFACE
I2S/PCM
DIGITAL
AUDIO
INTERFACE
LINEIN A1
LINEIN A2
LINEIN B1
LINEIN B2
MAX9888
Stereo Audio CODEC
with FlexSound Technology
MAX9888
2
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features ..................................................................................... 1
Simplified Block Diagram ........................................................................ 1
Ordering Information ........................................................................... 1
Functional Diagram ............................................................................ 5
Absolute Maximum Ratings ...................................................................... 6
Electrical Characteristics ........................................................................ 6
Digital Input/Output Characteristics ............................................................... 19
Input Clock Characteristics ..................................................................... 21
Audio Interface Timing Characteristics ............................................................ 22
Digital Microphone Timing Characterstics .......................................................... 23
I2C Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Consumption ........................................................................... 25
Typical Operating Characteristics ................................................................ 28
Microphone to ADC..........................................................................28
Line to ADC................................................................................32
Digital Loopback ............................................................................33
Analog Loopback ...........................................................................34
DAC to Receiver ............................................................................35
Line to Receiver ............................................................................37
DAC to Speaker.............................................................................38
Line to Speaker .............................................................................42
DAC to Headphone..........................................................................43
Line to Headphone ..........................................................................48
Speaker Bypass Switch ......................................................................49
Pin Configuration ............................................................................. 50
Pin Description ............................................................................... 51
Detailed Description........................................................................... 53
I2C Slave Address...........................................................................54
Registers ..................................................................................54
Power Management .........................................................................59
Microphone Inputs ..........................................................................60
Line Inputs.................................................................................62
ADC Input Mixers ...........................................................................63
Record Path Signal Processing.................................................................64
Microphone AGC .........................................................................64
Noise Gate ..............................................................................64
Stereo Audio CODEC
with FlexSound Technology
MAX9888
3
TABLE OF CONTENTS (continued)
ADC Record Level Control ....................................................................67
Sidetone ..................................................................................68
Digital Audio Interfaces .......................................................................69
Clock Control...............................................................................76
Passband Filtering...........................................................................78
Playback Path Signal Processing ...............................................................81
Automatic Level Control ....................................................................81
Parametric Equalizer ......................................................................82
Playback Level Control .......................................................................84
DAC Input Mixers ...........................................................................85
Preoutput Signal Path ........................................................................86
Preoutput Mixer ..........................................................................86
Preoutput PGA ...........................................................................87
Receiver Amplifier ...........................................................................87
Receiver Output Volume ...................................................................88
Receiver Output Mixer .....................................................................88
Speaker Amplifiers ..........................................................................89
Speaker Output Volume ....................................................................90
Speaker Output Mixers ....................................................................90
Speaker Amplifier Signal Processing ............................................................91
Excursion Limiter .........................................................................91
Power Limiter ............................................................................93
Distortion Limiter .........................................................................94
Headphone Amplifier ........................................................................95
Headphone Output Mixers..................................................................96
Headphone Output Volume .................................................................97
Output Bypass Switches ......................................................................98
Click-and-Pop Reduction .....................................................................99
Jack Detection.............................................................................100
Jack Insertion...........................................................................100
Accessory Button Detection ...............................................................100
Jack Removal...........................................................................101
Stereo Audio CODEC
with FlexSound Technology
MAX9888
4
TABLE OF CONTENTS (continued)
Battery Measurement .......................................................................102
Device Status .............................................................................103
Device Revision............................................................................104
I2C Serial Interface .........................................................................104
Bit Transfer .............................................................................104
START and STOP Conditions...............................................................104
Early STOP Conditions....................................................................104
Slave Address ..........................................................................105
Acknowledge ...........................................................................105
Write Data Format .......................................................................105
Read Data Format .......................................................................106
Applications Information....................................................................... 107
Typical Operating Circuits ....................................................................107
Analog Microphones and Bypass Switch .....................................................107
Digital Microphones and Receiver Amplifier ...................................................108
Filterless Class D Operation ..................................................................109
RF Susceptibility ...........................................................................109
Startup/Shutdown Sequencing ................................................................109
Component Selection .......................................................................110
Optional Ferrite Bead Filter ................................................................110
Input Capacitor..........................................................................110
Charge-Pump Capacitor Selection ..........................................................110
Charge-Pump Flying Capacitor .............................................................111
Charge-Pump Holding Capacitor ...........................................................111
Unused Pins ..............................................................................111
Recommended PCB Routing .................................................................112
Supply Bypassing, Layout, and Grounding ......................................................112
WLP Applications Information .................................................................113
Package Information...........................................................................114
Revision History ..............................................................................115
Stereo Audio CODEC
with FlexSound Technology
MAX9888
5
Functional Diagram
SDA SCL
I2C
E5F5F4 E2
MCLK
CLOCK
CONTROL
INBDIFF
MIXOUT3
MIXOUT2
PGAINB:
+20dB TO -6dB
C8 INB2
D8 INB1
D9 INA2/EXTMICN
E9 INA1/EXTMICP
G9 MIC2N
F9 MIC2P
F8
D6 JACKSNS JACK
DETECTION
JDETEN
MBEN
G8 MICBIAS REG
+
MIX
MIX
PGAINB:
+20dB TO -6dB
INADIFF
INABYP
MIC2BYP
PGAINA:
+20dB TO -6dB
PGAOUT1:
0dB TO -23dB
PGAOUT2:
0dB TO -23dB
PGAOUT3:
0dB TO -23dB
+
PGAINA:
+20dB TO -6dB
PGAM2:
+20dB TO 0dB
PGAM1:
+20dB TO 0dB
MIXOUT1
PREOUT1
MIX
MIXADR
ADREN
ADLEN
PSCLK
MIX
MIXADL
MIX
PA2EN:
0/20/30dB
EXTMIC
PA1EN:
0/20/30dB
EXTMIC
MIC1N/
DIGMICCLK
E8
MIC1P/
DIGMICDATA
ADCR
ADCL
PREOUT2
PREOUT3
+9dB
+9dB
+9dB
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
MODE1
AVFLT
DSTS
MAS1
DAI1
SEL1 SEL2
BCLK1
BCLKS1
D1 D2 E4 D4 E1 F2 F3 G1 G3 G2
LRCLK1
SDOUT1
SDIN1
SIDETONE
DVST:
0dB TO -60dB
LTEN1
LBEN2
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
AUTOMATIC
GAIN
CONTROL
EQ1EN EQ2EN
DVEQ1:
0dB TO -15dB
DV1G:
0/6/12/18dB
DV2:
0dB TO -15dB DCB2
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
DVEQ2:
0dB TO -15dB
FlexSound
TECHNOLOGY
MULTI BAND ALC
EXCURSION LIMITER
DV1:
0dB TO -15dB MODE1
DVFLT
DALEN
MIXDAR
DACL
DAREN
DACR
+
+
BIT
CLOCK
FRAME
CLOCK
DATA
OUTPUT
DATA
INPUT
MAS1 HIZOFF1 MAS2
DAI2
BCLK2
LRCLK2
SDOUT2
SDIN2
BIT
CLOCK
FRAME
CLOCK
DATA
OUTPUT
DATA
INPUT
MAS2 HIZOFF2
LRCLKS1 SDOUTS1 SDINS1 DVDDS1 BCLKS2 LRCLKS2 SDOUTS2 SDINS2 DVDDS2
G4
DVDD
G5
AVDD
MUX
LBEN1
MIXREC
BATTERY ADC
0dB
RECVOL:
+8dB TO -62dB
RECP/
RXINP A6
RECN/
RXINN
SPKLP
SPKLN
B6
RECBYP
SPKBYP
RECEN
MIXSPL
+6dB
SPVOLL:
+8dB TO -62dB A4, B4
SPKLVDD A3, B3
A5, B5
SPKLGND C4, C5
SPKRVDD C3, D3
SPKRP C1, C2
SPKRN A1, B1
SPLEN
SPREN
POWER/
DISTORTION LIMITER
MIXSPR
+6dB
SPVOLR:
+8dB TO -62dB
HPVOLL:
+3dB TO -67dB
SPKRGND A2, B2
HPL B9
HPSNS C6
HPR C9
HPLEN
MIXHPL
HPVOLR:
+3dB TO -67dB
HPVDD A7
HPGND A8
B7B8A9G7F1
HPREN
MIXHPR
HPVSSAGND
DGND C1N C1P
CHARGE
PUMP
REF F7
G6
F6
PREG
REG
BIAS
MAX9888
NOISE GATE
AUDIO/
VOICE
FILTERS
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
MIX
MIX
MIX
MIXDAL
MIX
MIX
MIX
MIX
MIX
IRQ
PORT S1 PORT S2
Stereo Audio CODEC
with FlexSound Technology
MAX9888
6
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
(Voltages with respect to AGND.)
DVDD, AVDD, HPVDD .........................................-0.3V to +2.2V
SPKLVDD, SPKRVDD, DVDDS1, DVDDS2 ..........-0.3V to +6.0V
DGND, HPGND, SPKLGND, SPKRGND ..............-0.1V to +0.1V
HPVSS ............................... (HPGND - 2.2V) to (HPGND + 0.3V)
C1N .................................... (HPVSS - 0.3V) to (HPGND + 0.3V)
C1P .....................................(HPGND - 0.3V) to (HPVDD + 0.3V)
PREG ..................................................... -0.3V to (AVDD + 0.3V)
REF, MICBIAS ................................. -0.3V to (SPKLVDD + 0.3V)
MCLK, SDINS1, SDINS2, JACKSNS,
SDA, SCL, IRQ .................................................-0.3V to +6.0V
LRCLKS1, BCLKS1, SDOUTS1 ......... -0.3V to (DVDDS1 + 0.3V)
LRCLKS2, BCLKS2, SDOUTS2 ......... -0.3V to (DVDDS2 + 0.3V)
REG, INA1, INA2, INB1, INB2, MIC1P/DIGMICDATA,
MIC1N/DIGMICCLK, MIC2P, MIC2N ...............-0.3V to +2.2V
HPSNS ............................... (HPGND - 0.3V) to (HPGND + 0.3V)
HPL, HPR ............................ (HPVSS - 0.3V) to (HPVDD + 0.3V)
RECP, RECN ..............(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKLP, SPKLN ...........(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKRP, SPKRN .........(SPKRGND - 0.3V) to (SPKRVDD + 0.3V)
Continuous Power Dissipation (TA = +70NC)
63-Bump WLP (derate 25.6mW/NC above +70NC) ........2.05W
Operating Temperature Range .......................... -40NC to +85NC
Storage Temperature Range ............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Supply Voltage Range Guaranteed by PSRR
VSPKLVDD,
VSPKRVDD 2.8 5.5
V
VDVDD, VAVDD,
VHPVDD 1.65 1.8 2.0
VDVDDS1,
VDVDDS2 1.65 3.6
Total Supply Current (Note 2) IVDD
Full-duplex 8kHz mono,
receiver output (Note 3)
Analog 6.37 10
mA
Speaker 1.98 3.5
Digital 1.49 3
DAC playback 48kHz stereo,
headphone outputs (Note 3)
Analog 2.71 4
Speaker 1.65 2.5
Digital 2.93 4.5
DAC playback 48kHz stereo,
speaker outputs (Note 3)
Analog 1.85 3
Speaker 8.22 18
Digital 2.94 5
Full-duplex 48kHz stereo,
microphone inputs,
headphone outputs (Note 3)
Analog 12.75 18
Speaker 1.7 3
Digital 3.75 5.5
Stereo line playback,
IN_DIF = 0, INA1 to HPL,
INA2 to HPR, VMCLK = 0V
Analog 5.11 7
Speaker 0.58 1
Digital 0.03 0.06
Stereo Audio CODEC
with FlexSound Technology
MAX9888
7
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Shutdown Supply Current
(Note 2) TA = +25NC
Analog 0.2 2
FA
Speaker 0.1 1
Digital 1 5
REF Voltage 2.5 V
PREG Voltage 1.6 V
REG Voltage 0.7 V
Shutdown to Full Operation SLEW = 0 30 ms
SLEW = 1 17
MICROPHONE TO ADC PATH
Dynamic Range (Note 4) DR fS = 8kHz, MODE = 0 (IIR voice),
AVMICPRE_ = 0dB 75 88 dB
Total Harmonic Distortion +
Noise THD+N
VIN = 0.1VP-P, MCLK = 12.288MHz,
fS = 8kHz, f = 1kHz -77 -65
dBAVMICPRE_ = 0dB, VIN = 1VP-P, f = 1kHz -82
AVMICPRE_ = +30dB, VIN = 32mVP-P,
f = 1kHz -71
Common-Mode Rejection Ratio CMRR VIN = 100mVP-P, f = 217Hz 65 dB
Power-Supply Rejection Ratio PSRR
VAVDD = 1.65V to 2.0V, input referred, MIC
inputs floating 60 100
dB
f = 217Hz, VRIPPLE = 100mVP-P, AVADC = 0dB,
input referred 100
f = 1kHz, VRIPPLE = 100mVP-P, AVADC = 0dB,
input referred 91
f = 10kHz, VRIPPLE = 100mVP-P, AVADC = 0dB,
input referred 70
Path Phase Delay
1kHz, 0dB input,
highpass filter
disabled measured
from analog input to
digital output
MODE = 0 (IIR voice)
8kHz 2.2
ms
MODE = 0 (IIR voice)
16kHz 1.1
MODE = 1 (FIR audio)
8kHz 4.5
MODE = 1 (FIR audio)
48kHz 0.76
Stereo Audio CODEC
with FlexSound Technology
MAX9888
8
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MICROPHONE PREAMP
Full-Scale Input AVMICPRE_ = 0dB 1.05 VP-P
Preamplifier Gain AVMICPRE_ (Note 5)
PA1EN/PA2EN = 01 0
dBPA1EN/PA2EN = 10 19.5 20 20.5
PA1EN/PA2EN = 11 29.4 30 30.5
PGA Gain AVMICPGA_ (Note 5) PGAM1/PGAM2 = 0x00 19.5 20 20.5 dB
PGAM1/PGAM2 = 0x14 0
MIC Input Resistance RIN_MIC All gain settings, measured at MIC1P/MIC1N/
MIC2P/MIC2N 30 50 kI
MICROPHONE BIAS
MICBIAS Output Voltage VMICBIAS ILOAD = 1mA 2.14 2.2 2.25 V
Load Regulation ILOAD = 1mA to 2mA 0.5 11 mV
Line Regulation VSPKLVDD = 2.8V to 5.5V 100 FV
Ripple Rejection f = 217Hz, VRIPPLE (SPKLVDD) = 100mVP-P 92 dB
f = 10kHz, VRIPPLE (SPKLVDD) = 100mVP-P 83
Noise Voltage
A-weighted, f = 20Hz to 20kHz 3.8 FVRMS
P-weighted, f = 20Hz to 4kHz 2.1
f = 1kHz 33 nV/Hz
MICROPHONE BYPASS SWITCH
On-Resistance RON IMIC1_ = 100mA, INABYP = MIC2BYP = 1,
VMIC2_ = VINA_ = (0V, VAVDD)3.5 20 I
Total Harmonic Distortion +
Noise THD+N VIN = 2VP-P, VCM = 0.9V, RL = 10kI,
f = 1kHz, INABYP = MIC2BYP = 1 -80 dB
Off-Isolation VIN = 2VP-P, VCM = 0.9V, RL = 10kI,
f = 1kHz 60 dB
Off-Leakage Current VMIC1_ = (0V, VAVDD),
VMIC2_/VINA_ = (VAVDD, 0V) -2.5 +2.5 FA
LINE INPUT TO ADC PATH
Dynamic Range (Note 4) DR fS = 48kHz, MCLK = 12.288MHz, MODE = 1
(FIR audio) 91 dB
Total Harmonic Distortion +
Noise THD+N VIN = 1VP-P, f = 1kHz -77 dB
Gain Error DC accuracy 1 5 %
Stereo Audio CODEC
with FlexSound Technology
MAX9888
9
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LINE INPUT PREAMP
Full-Scale Input VIN AVPGAIN_ = 0dB 1 VP-P
AVPGAIN_ = -6dB 1.4
Level Adjust Gain AVPGAIN_
PGAINA/PGAINB = 0x0 19 20 21
dB
PGAINA/PGAINB = 0x1 13 14 15
PGAINA/PGAINB = 0x2 (Note 5) 2 3 4
PGAINA/PGAINB = 0x3 TA = +25NC0
PGAINA/PGAINB = 0x4 -4 -3 -2
PGAINA/PGAINB = 0x5, 0x6, 0x7 -7 -6 -5
Input Resistance RIN
AVPGAIN_ = +20dB 14.6 21 27.4
kI
AVPGAIN_ = +14dB 20
AVPGAIN_ = +3dB 20
AVPGAIN_ = 0dB 7.3 10 13.7
AVPGAIN_ = -3dB 20
AVPGAIN_ = -6dB 20
Feedback Resistance RIN_FB INAEXT/INBEXT = 1 TA = +25NC18.5 20 21.5 kI
TA = TMIN to TMAX 17.5 23
ADC LEVEL CONTROL
ADC Level Adjust Range AVADCLVL AVL/AVR = 0xF to 0x0 (Note 5) -12 +3 dB
ADC Level Adjust Step Size 1 dB
ADC Gain Adjust Range AVADCGAIN AVLG/AVRG = 00 to 11 (Note 5) 0 18 dB
ADC Gain Adjust Step Size 6 dB
ADC DIGITAL FILTERS
VOICE MODE IIR LOWPASS FILTER (MODE1 = 0)
Passband Cutoff fPLP
Ripple limit cutoff 0.441
x fsHz
-3dB cutoff 0.449
x fs
Passband Ripple f < fPLP -0.1 +0.1 dB
Stopband Cutoff fSLP 0.47
x fsHz
Stopband Attenuation (Note 6) f > fSLP 74 dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
10
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0)
Passband Cutoff
(-3dB from Peak) fAHPPB
AVFLT = 0x1 (elliptical tuned for
fs = 16kHz + 217Hz notch)
0.0161
x fs
Hz
AVFLT = 0x2 (500Hz Butterworth tuned for
fs = 16kHz)
0.0319
x fs
AVFLT = 0x3 (elliptical tuned for
fs = 8kHz + 217Hz notch)
0.0321
x fs
AVFLT = 0x4 (500Hz Butterworth tuned for
fs = 8kHz)
0.0632
x fs
AVFLT = 0x5 (fs/240 Butterworth) 0.0043
x fs
Stopband Cutoff
(-30dB from Peak) fAHPSB
AVFLT = 0x1 (elliptical tuned for
fs = 16kHz + 217Hz notch)
0.0139
x fs
Hz
AVFLT = 0x2 (500Hz Butterworth tuned for
fs = 16kHz)
0.0156
x fs
AVFLT = 0x3 (elliptical tuned for
fs = 8kHz + 217Hz notch)
0.0279
x fs
AVFLT = 0x4 (500Hz Butterworth tuned for fs =
8kHz)
0.0312
x fs
AVFLT = 0x5 (fs/240 Butterworth) 0.002
x fs
DC Attenuation DCATTEN AVFLT 000 90 dB
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 0, LRCLK < 50kHz)
Passband Cutoff fPLP
Ripple limit cutoff 0.43
x fs
Hz-3dB cutoff 0.48
x fs
-6.02dB cutoff 0.5
x fs
Passband Ripple f < fPLP -0.1 +0.1 dB
Stopband Cutoff fSLP 0.58
x fsHz
Stopband Attenuation (Note 6) f < fSLP 60 dB
ADC STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 1, LRCLK > 50kHz)
Passband Cutoff fPLP
Ripple limit cutoff 0.208
x fsHz
-3dB cutoff 0.28
x fs
Stereo Audio CODEC
with FlexSound Technology
MAX9888
11
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Passband Ripple f < fPLP -0.1 +0.1 dB
Stopband Cutoff fSLP 0.417
x fsHz
Stopband Attenuation f < fSLP 60 dB
ADC STEREO AUDIO MODE DC-BLOCKING HIGHPASS FILTER (MODE1 = 1)
Passband Cutoff
(-3dB from Peak) fAHPPB AVFLT 000 0.000125
x fs Hz
DC Attenuation DCAtten AVFLT 000 90 dB
MICROPHONE AUTOMATIC GAIN CONTROL
AGC Hold Duration AGCHLD = 01 50 ms
AGCHLD = 11 400
AGC Attack Time AGCATK = 00 2 ms
AGCATK = 11 123
AGC Release Time AGCRLS = 000 0.078 s
AGCRLS = 111 10
AGC Threshold Level AGCTH = 0x0 to 0xF -3 +18 dB
AGC Threshold Step Size 1 dB
AGC Gain (Note 5) 0 20 dB
ADC NOISE GATE
NG Threshold Level ANTH = 0x3 to 0xF, referred to 0dBFS -64 -16 dB
NG Attenuation (Note 5) 0 12 dB
ADC-TO-DAC DIGITAL SIDETONE (MODE = 0)
Sidetone Gain Adjust Range AVSTGA DVST = 0x01 -0.5 dB
DVST = 0x1F -60.5
Sidetone Gain Adjust Step Size 2 dB
Sidetone Path Phase Delay 1kHz, 0dB input, highpass
filter disabled
8kHz 2.2 ms
16kHz 1.1
ADC-TO-DAC DIGITAL LOOP-THROUGH PATH
Dynamic Range (Note 4) DR fS = 48kHz, MCLK = 12.288MHz, MODE = 1
(FIR audio) 89 dB
Total Harmonic Distortion THD f = 1kHz, fS = 48kHz, MCLK = 12.288MHz,
MODE = 1 (FIR audio) -71 -66 dB
DAC LEVEL CONTROL
DAC Attenuation Range AVDACATTN DV1DV2 = 0xF to 0x0 (Note 5) -15 0 dB
DAC Attenuation Step Size 1 dB
DAC Gain Adjust Range AVDACGAIN DV1G = 00 to 11 (Note 5) 0 18 dB
DAC Gain Adjust Step Size 6 dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
12
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC DIGITAL FILTERS
VOICE MODE IIR LOWPASS FILTER (MODE1 = 0)
Passband Cutoff fPLP
Ripple limit cutoff 0.448
x fsHz
-3dB cutoff 0.451
x fs
Passband Ripple f < fPLP -0.1 +0.1 dB
Stopband Cutoff fSLP 0.476
x fsHz
Stopband Attenuation (Note 6) f > fSLP 75 dB
VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0)
Passband Cutoff
(-3dB from Peak) fDHPPB
DVFLT = 0x1 (elliptical tuned for
fs = 16kHz + 217Hz notch)
0.0161
x fs
Hz
DVFLT = 0x2 (500Hz Butterworth tuned for
fs = 16kHz)
0.0312
x fs
DVFLT = 0x3 (elliptical tuned for
fs = 8kHz + 217Hz notch)
0.0321
x fs
DVFLT = 0x4 (500Hz Butterworth tuned for
fs = 8kHz)
0.0625
x fs
DVFLT = 0x5 (fs/240 Butterworth) 0.0042
x fs
Stopband Cutoff
(-30dB from Peak) fDHPSB
DVFLT = 0x1 (elliptical tuned for
fs = 16kHz + 217Hz notch)
0.0139
x fs
Hz
DVFLT = 0x2 (500Hz Butterworth tuned for
fs = 16kHz)
0.0156
x fs
DVFLT = 0x3 (elliptical tuned for
fs = 8kHz + 217Hz notch)
0.0279
x fs
DVFLT = 0x4 (500Hz Butterworth tuned for
fs = 8kHz)
0.0312
x fs
DVFLT = 0x5 (fs/240 Butterworth) 0.002
x fs
DC Attenuation DCATTEN DVFLT 000 85 dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
13
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 0, LRCLK < 50kHz)
Passband Cutoff fPLP
Ripple limit cutoff 0.43
x fs
Hz-3dB cutoff 0.47
x fs
-6.02dB cutoff 0.5
x fs
Passband Ripple f < fPLP -0.1 +0.1 dB
Stopband Cutoff fSLP 0.58
x fsHz
Stopband Attenuation (Note 6) f > fSLP 60 dB
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 1 for LRCLK > 50kHz)
Passband Cutoff fPLP
Ripple limit cutoff 0.24
x fsHz
-3dB cutoff 0.31
x fs
Passband Ripple f < fPLP -0.1 +0.1 dB
Stopband Cutoff fSLP 0.477
x fsHz
Stopband Attenuation (Note 6) f < fSLP 60 dB
STEREO AUDIO MODE DC-BLOCKING HIGHPASS FILTER
Passband Cutoff (-3dB from
Peak) fDHPPB DVFLT 000 (DAI1), DCB2 = 1 (DAI2) 0.000104
x fsHz
DC Attenuation DCATTEN DVFLT 000 (DAI1), DCB2 = 1 (DAI2) 90 dB
AUTOMATIC LEVEL CONTROL
Dual Band Lowpass Corner
Frequency ALCMB = 1 5 kHz
Dual Band Highpass Corner
Frequency ALCMB = 1 5 kHz
Gain Range 0 12 dB
Low Signal Threshold ALCTH = 111 to 001 -48 -12 dBFS
Release Time ALCRLS = 101 0.25 s
ALCRLS = 000 8
PARAMETRIC EQUALIZER
Number of Bands 5 Bands
Per Band Gain Range -12 +12 dB
Preattenuator Gain Range (Note 5) -15 0 dB
Preattenuator Step Size 1 dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
14
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC-TO-RECEIVER AMPLIFIER PATH
Dynamic Range (Note 4) DR fS = 48kHz, MCLK = 12.288MHz, f = 1kHz 96 dB
Total Harmonic Distortion +
Noise THD+N f = 1kHz, POUT = 25mW, RREC = 32I-70 -63 dB
Click and Pop Level KCP
Peak voltage, A-weighted, 32
samples per second, AVREC
= 0dB
Into shutdown -70
dBV
Out of shutdown -73
PREOUTPUT MIXERS
Level Adjust Gain AVPGAOUT_ (Note 5)
PGAOUTA/PGAOUTB/
PGAOUTC = 0x0 0
dB
PGAOUTA/PGAOUTB/
PGAOUTC = 0xC -25 -23.4 -22
Level Adjust Step Size 2 dB
Mute Attenuation f = 1kHz 85 dB
LINE INPUT-TO-RECEIVER AMPLIFIER PATH
Dynamic Range (Note 4) DR Referenced to full-scale output level 92 dB
Total Harmonic Distortion +
Noise THD+N -70 dB
Power-Supply Rejection Ratio PSRR
VSPKLVDD = 2.8V to 5.5V 54 89
dB
f = 217Hz, VRIPPLE = 100mVP-P -63
f = 1kHz, VRIPPLE = 100mVP-P -63
f = 10kHz, VRIPPLE = 100mVP-P -65
Click-and-Pop Level KCP
Peak voltage, A-weighted, 32
samples per second, AVREC
= 0dB
Into shutdown -57
dBV
Out of shutdown -55
RECEIVER AMPLIFIER
Output Power POUT RREC = 32I, f = 1kHz, THD = 1% 100 mW
Full-Scale Output (Note 7) 1 VRMS
Volume Control AVREC (Note 5) RECVOL = 0x00 -65 -62 -58 dB
RECVOL = 0x1F +7.5 +8 +8.5
Volume Control Step Size
+8dB to +6dB 0.5
dB
+6dB to +0dB 1
0dB to -14dB 2
-14dB to -38dB 3
-38dB to -62dB 4
Mute Attenuation f = 1kHz 95 dB
Output Offset Voltage VOS AVREC = -62dB TA = +25NC±0.13 ±1mV
Capacitive Drive Capability No sustained oscillations RREC = 32I500 pF
RREC = J100
Stereo Audio CODEC
with FlexSound Technology
MAX9888
15
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC-TO-SPEAKER AMPLIFIER PATH
Total Harmonic Distortion +
Noise THD+N f = 1kHz, POUT = 250mW, ZSPK = 8I + 68FH-71 dB
Crosstalk SPKL to SPKR and SPKR to SPKL,
POUT = 640mW, f = 1kHz -75 dB
Output Noise A-weighted 43 FVRMS
Click-and-Pop Level KCP
Peak voltage, A-weighted,
32 samples per second,
AVSPK_ = 0dB
Into shutdown -65
dBV
Out of shutdown -65
LINE INPUT-TO-SPEAKER AMPLIFIER PATH
Total Harmonic Distortion +
Noise THD+N f = 1kHz, POUT = 200mW, ZSPK = 8I + 68FH-66 dB
Output Noise A-weighted 56 FVRMS
Power-Supply Rejection Ratio PSRR
VSPKLVDD = VRIPPLE = 2.8V to 5.5V 43 60
dB
f = 217Hz, VRIPPLE = 100mV 75
f = 1kHz, VRIPPLE = 100mV 73
f = 10kHz, VRIPPLE = 100mV 50
Click-and-Pop Level KCP
Peak voltage, A-weighted,
32 samples per second,
AVSPK_ = 0dB
Into shutdown -48
dBV
Out of shutdown -50
SPEAKER AMPLIFIER
Output Power POUT f = 1kHz, THD = 1%,
ZSPK = 8I + 68FH
VSPKLVDD =
VSPKRVDD = 5.0V 1370
mW
VSPKLVDD =
VSPKRVDD = 4.2V 954
VSPKLVDD =
VSPKRVDD = 3.7V 733
VSPKLVDD =
VSPKRVDD = 3.2V 544
Full-Scale Output (Note 7) 2 VRMS
Volume Control (Note 5) AVSPK_ SPVOLL/SPVOLR = 0x00 -69 -64 -59 dB
SPVOLL/SPVOLR = 0x1F +7.5 +8 +8.5
Volume Control Step Size
+8dB to +6dB 0.5
dB
+6dB to +0dB 1
0dB to -14dB 2
-14dB to -38dB 3
-38dB to -64dB 4
Stereo Audio CODEC
with FlexSound Technology
MAX9888
16
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Mute Attenuation f = 1kHz 86 dB
Output Offset Voltage VOS AVSPK_ = -64dB, TA = +25NC±0.25 ±1.25 mV
EXCURSION LIMITER
Upper-Corner Frequency Range DHPUCF = 001 to 100 400 1000 Hz
Lower-Corner Frequency DHPLCF = 01 to 10 400 Hz
Biquad Minimum Corner
Frequency
DHPUCF = 000 (fixed mode) 100
Hz
DHPUCF = 001 200
DHPUCF = 010 300
DHPUCF = 011 400
DHPUCF = 100 500
Threshold Voltage
ZSPK = 8I + 68FH,
VSPKLVDD = VSPKRVDD =
5.5V, AVSPK_ = +8dB
DHPTH = 000 0.34
VP
DHPTH = 111 4.95
Release Time ALCRLS = 101 0.25 s
ALCRLS = 000 4
POWER LIMITER
Attenuation -64 dB
Threshold
ZSPK = 8I + 68FH,
VSPKLVDD = VSPKRVDD =
5.5V, AVSPK_ = +8dB
PWRTH = 0x1 0.05
W
PWRTH = 0xF 1.80
Time Constant 1 tPWR1 PWRT1 = 0x1 0.5 s
PWRT1 = 0xF 8.7
Time Constant 2 tPWR2 PWRT2 = 0x1 to 0xF 0.5 min
PWRT2 = 0xF 8.7
Weighting Factor kPWR PWRK = 000 to 111 12.5 100 %
DISTORTION LIMITER
Distortion Limit THDCLP = 0x1 < 1 %
THDCLP = 0xF 24
Release Time Constant THDT1 = 000 0.76 s
THDT1 = 111 6.2
DAC-TO-HEADPHONE AMPLIFIER PATH
Dynamic Range (Note 4) DR fS = 48kHz, MCLK =
12.288MHz
Master or slave mode 100 dB
Slave mode 94
Total Harmonic Distortion +
Noise THD+N
fS = 48kHz, MCLK = 12.288MHz,
f = 1kHz, POUT = 20mW
RHP = 16I-71 -64
dB
RHP = 32I-75
fS = 48kHz, MCLK = 12.288MHz,
f = 1kHz, VOUT = 1VRMS, RHP = 10kI-79
Stereo Audio CODEC
with FlexSound Technology
MAX9888
17
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Crosstalk
f = 1kHz, Input = -1dBFS, RHP = 10kI-82 dB
HPL to HPR and HPR to HPL,
POUT = 5mW, f = 1kHz, RHP = 32I-82 dB
Power-Supply Rejection Ratio PSRR
VAVDD = VHPVDD = 1.65V to 2.0V 60 84
dB
f = 217Hz, VRIPPLE = 100mV, AVVOL = 0dB 92
f = 1kHz, VRIPPLE = 100mV, AVVOL = 0dB 91
f = 10kHz, VRIPPLE = 100mV, AVVOL = 0dB 57
DAC Path Phase Delay
1kHz, 0dB input,
highpass filter
disabled measured
from digital input to
analog output
MODE = 0 (voice) 8kHz 2.2
ms
MODE = 0 (voice)
16kHz 1.1
MODE = 1 (music)
8kHz 4.5
MODE = 1 (music)
48kHz 0.76
Gain Error 1 %
Channel Gain Mismatch 0.5 %
Click-and-Pop Level KCP
Peak voltage, A-weighted,
32 samples per second,
AVHP_ = 0dB
Into shutdown -66
dBV
Out of
shutdown -67
LINE INPUT-TO-HEADPHONE AMPLIFIER PATH
Total Harmonic Distortion +
Noise THD+N VIN = 1VP-P, f =1kHz, RHP = 32I-70 dB
Dynamic Range (Note 4) DR 91 dB
Power-Supply Rejection Ratio PSRR
VAVDD = VHPVDD = 1.65V to 2.0V 42 66
dB
f = 217Hz, VRIPPLE = 100mVP-P 62
f = 1kHz, VRIPPLE = 100mVP-P 57
f = 10kHz, VRIPPLE = 100mVP-P 41
Click and Pop Level KCP
Peak voltage, A-weighted,
32 samples per second,
AVHP_ = 0dB
Into shutdown -62
dBV
Out of
shutdown -60
HEADPHONE AMPLIFIER
Output Power POUT f = 1kHz, THD = 1% RHP = 32I32 mW
RHP = 16I40
Full-Scale Output (Note 7) 1 VRMS
Volume Control AVHP_ TA = +25NC (Note 5) HPVOL_ = 0x00 -71 -67 -66 dB
HPVOL_ = 0x1F 2.4 3 3.5
Stereo Audio CODEC
with FlexSound Technology
MAX9888
18
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Volume Control Step Size
+3dB to +1dB 0.5
dB
+1dB to -5dB 1
-5dB to -19dB 2
-19dB to -43dB 3
-43dB to -67dB 4
Mute Attenuation f = 1kHz 82 dB
Output Offset Voltage VOS AVHP_ = -67dB TA = +25NC±0.2 ±1mV
TA = TMIN to TMAX ±2
Capacitive Drive Capability No sustained
oscillations
RHP = 32I500 pF
RHP = J100
Charge Pump Oscillator
Frequency fCP 300 667 900 kHz
Slow mode 74
SPEAKER BYPASS SWITCH
On-Resistance RON ISPKL_ = 100mA, SPKBYP = 1,
VRXIN_ = [0V, VSPKLVDD] 2.8 4.5 I
Total Harmonic Distortion +
Noise THD+N
VIN = 2VP-P, VCM = VSPKLVDD/2,
ZSPK = 8I + 68FH, f = 1kHz,
SPKBYP = 1
RS = 10I-77
dB
RS = 0I-60
Off-Isolation VIN = 2VP-P, VCM = VSPKLVDD/2,
ZL = 8I + 68FH, f = 1kHz 96 dB
Off-Leakage Current VRXIN_ = [0V, VSPKLVDD],
VSPKL_ = [VSPKLVDD, 0V] -1 +1 FA
RECEIVER BYPASS SWITCH
On-Resistance RON IRECP = 100mA, RECBYP = 1,
VRECN = [0V, VSPKLVDD]1.2 2 I
Total Harmonic Distortion +
Noise THD+N VIN = 2VP-P, VCM = VSPKLVDD/2,
RL = 32I, f = 1kHz, RECBYP = 1 -66 %
Off-Isolation VIN = 2VP-P, VCM = VSPKLVDD/2,
RL = 32I, f = 1kHz 80 dB
Off-Leakage Current VRECP = [0V, VSPKLVDD],
VRECN = [VSPKLVDD, 0V] -15 +15 FA
Stereo Audio CODEC
with FlexSound Technology
MAX9888
19
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
DIGITAL INPUT/OUTPUT CHARACTERISTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JACK DETECTION
JACKSNS High Threshold VTH1
MICBIAS enabled 0.92 x
VMICBIAS
0.95 x
VMICBIAS
0.98 x
VMICBIAS V
MICBIAS disabled 0.92 x
VSPKLVD
D
0.95 x
VSPKLVDD
0.98 x
VSPKLVD
D
JACKSNS Low Threshold VTH2
MICBIAS enabled 0.06 x
VMICBIAS
0.10 x
VMICBIAS
0.17 x
VMICBIAS V
MICBIAS disabled 0.06 x
VSPKLVD
D
0.10 x
VSPKLVDD
0.17 x
VSPKLVD
D
JACKSNS Sense Voltage VSENSE MICBIAS disabled VSPKLVDD V
JACKSNS Sense Resistance RSENSE MICBIAS disabled, JDWK = 0 1.7 2.4 2.9 kI
JACKSNS Weak Pullup Current IWPU MICBIAS disabled, JDWK = 1 2 5 9.5 FA
JACKSNS Deglitch Period tGLITCH JDEB = 00 25 ms
JDEB = 11 200
BATTERY ADC
Input Voltage Range 2.8 5.5 V
LSB Size 0.1 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MCLK
Input High Voltage VIH 1.2 V
Input Low Voltage VIL 0.6 V
Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V, TA = +25°C -1 +1 FA
Input Capacitance 10 pF
SDINS1, BCLKS1, LRCLKS1—INPUT
Input High Voltage VIH 0.7 x
DVDDS1 V
Input Low Voltage VIL 0.29 x
DVDDS1 V
Input Hysteresis 200 mV
Input Leakage Current IIH, IIL VDVDDS1 = 3.6V, VIN = 0V, 3.6V; TA = +25°C -1 +1 FA
Input Capacitance 10 pF
Stereo Audio CODEC
with FlexSound Technology
MAX9888
20
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BCLKS1, LRCLKS1, SDOUTS1—OUTPUT
Output Low Voltage VOL VDVDDS1 = 1.65V, IOL = 3mA 0.4 V
Output High Voltage VOH VDVDDS1 = 1.65V, IOH = 3mA DVDDS1
- 0.4 V
Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25°C,
high-impedance state -1 +1 FA
SDINS2, BCLKS2, LRCLKS2—INPUT
Input High Voltage VIH 0.7 x
DVDDS2 V
Input Low Voltage VIL 0.29 x
DVDDS2 V
Input Hysteresis 200 mV
Input Leakage Current IIH, IIL VDVDDS2 = 3.6V, VIN = 0V, 3.6V; TA = +25°C -1 +1 FA
Input Capacitance 10 pF
BCLKS2, LRCLKS2, SDOUTS2—OUTPUT
Output Low Voltage VOL VDVDDS2 = 1.65V, IOL = 3mA 0.4 V
Output High Voltage VOH VDVDDS2 = 1.65V, IOH = 3mA DVDDS2
- 0.4 V
Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25NC,
high-impedance state -1 +1 FA
SDA, SCL—INPUT
Input High Voltage VIH 0.7 x
DVDD V
Input Low Voltage VIL 0.3 x
DVDD V
Input Hysteresis 210 mV
Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V, TA = +25NC -1 +1 FA
Input Capacitance 10 pF
SDA, IRQ—OUTPUT
Output High Current IOH VOUT = 5.5V, TA = +25°C 1 mA
Output Low Voltage VOL VDVDD = 1.65V, IOL = 3mA 0.2 x
DVDD V
DIGMICDATA—INPUT
Input High Voltage VIH 0.65 x
DVDD V
Input Low Voltage VIL 0.35 x
DVDD V
Input Hysteresis 125 mV
Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 2.0V; TA = +25°C -25 +25 FA
Input Capacitance 10 pF
Stereo Audio CODEC
with FlexSound Technology
MAX9888
21
INPUT CLOCK CHARACTERISTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MCLK Input Frequency fMCLK 10 60 MHz
MCLK Input Duty Cycle PSCLK = 01 40 50 60 %
PSCLK = 10 or 11 30 70
Maximum MCLK Input Jitter 100 psRMS
LRCLK Sample Rate (Note 8) DHF_ = 0 8 48 kHz
DHF_ = 1 48 96
DAI1 LRCLK Average Frequency
Error (Note 9)
FREQ1 = 0x8 to 0xF 0 0 %
FREQ1 = 0x0 -0.025 +0.025
DAI2 LRCLK Average Frequency
Error (Note 9) -0.025 +0.025 %
PLL Lock Time Rapid lock mode 2 7 ms
Nonrapid lock mode 12 25
Maximum LRCLK Jitter to Maintain
PLL Lock 100 ns
Soft-Start/Stop Time 10 ms
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGMICCLK—OUTPUT
Output Low Voltage VOL VDVDD = 1.65V, IOL = 1mA 0.4 V
Output High Voltage VOH VDVDD = 1.65V, IOH = 1mA DVDD -
0.4 V
Stereo Audio CODEC
with FlexSound Technology
MAX9888
22
AUDIO INTERFACE TIMING CHARACTERISTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V, VSPKLVDD = VSPKRVDD = 2.8V, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
Figure 1. Non-TDM Audio Interface Timing Diagrams (TDM_ = 0)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BCLK Cycle Time tBCLK Slave mode 90 ns
BCLK High Time tBCLKH Slave mode 20 ns
BCLK Low Time tBCLKL Slave mode 20 ns
BCLK or LRCLK Rise and Fall Time tR, tFMaster mode, CL = 15pF ns
SDIN to BCLK Setup Time tSETUP 20 ns
LRCLK to BCLK Setup Time tSYNCSET Slave mode 20 ns
SDIN to BCLK Hold Time tHOLD 20 ns
LRCLK to BCLK Hold Time tSYNCHOLD Slave mode 20 ns
Minimum Delay Time from LSB
BCLK Falling Edge to
High-Impedance State
tHIZOUT Master mode, TDM_ = 1 42 ns
LRCLK Rising Edge to SDOUT
MSB Delay tSYNCTX CL = 30pF, TDM_ = 1, FSW_ = 1 50 ns
BCLK to SDOUT Delay tCLKTX CL = 30pF TDM_ = 1, BCLK rising edge 50 ns
TDM_ = 0 50
Delay Time from BCLK to LRCLK tCLKSYNC Master
mode
TDM_ = 1 -15 +15
ns
TDM_ = 0 0.8 x
tBCLKL
Delay Time from LRCLK to BCLK
After LSB tENDSYNC Master
mode TDM_ = 1, FSW_ = 1 20 ns
tR
tCLKTX
tSETUP tHOLD
tBCLK
tBCLKH tBCLKL
MSBLSB
LSB
BCLK
(OUTPUT)
LRCLK
(OUTPUT)
SDOUT
(OUTPUT)
SDIN
(INPUT)
BCLK
(INPUT)
LRCLK
(INPUT)
SDOUT
(OUTPUT)
SDIN
(INPUT)
MASTER MODE
tSETUP tHOLD
MSB
MSB
LSB
LSB HI-Z
SLAVE MODE
HI-Z MSB
tCLKSYNC
tF
tHIZOUT tCLKTX
tSYNCSET
tHIZOUT
Stereo Audio CODEC
with FlexSound Technology
MAX9888
23
DIGITAL MICROPHONE TIMING CHARACTERSTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 2.0V, VSPKLVDD = VSPKRVDD = 2.8V, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
Figure 2. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 0)
Figure 3. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGMICCLK Frequency fMICCLK MICCLK = 00 MCLK/8 MHz
MICCLK = 01 MCLK/6
DIGMICDATA to DIGMICCLK
Setup Time tSU,MIC Either clock edge 20 ns
DIGMICDATA to DIGMICCLK
Hold Time tHD,MIC Either clock edge 0 ns
LRCLK (OUTPUT)
BCLK (OUTPUT)
SDOUT (OUTPUT)
SDIN (INPUT)
tCLKTX
tHIZOUT
HI-ZLSB
tHOLD
tSETUP
LSB
MSB
MSB
tCLKSYNC
tR
tF
LRCLK (INPUT)
BCLK (INPUT)
SDOUT (OUTPUT)
SDIN (INPUT)
tCLKTX
tHIZOUT
HI-ZLSB
tHOLD
tSETUP
LSB
tSYNCHOLD
MSB
MSB
tBCLKH tBCLKL
tBCLK
tSYNCSET
MASTER MODE SLAVE MODE
tCLKSYNC
tBCLKH tBCLKL
tCLKSYNC
tR
tF
LRCLK (OUTPUT)
BCLK (OUTPUT)
SDOUT (OUTPUT)
SDIN (INPUT)
MASTER MODE
HI-ZLSB MSB
tSYNCTX
tENDSYNC
LSB MSB
SLAVE MODE
HI-ZLSB
LSB
MSB
MSB
tCLKTX
tHIZOUT
tHOLD
tSETUP tHOLD
tSETUP
LRCLK (INPUT)
BCLK (INPUT)
SDOUT (OUTPUT)
SDIN (INPUT)
tBCLK
tSYNCTX tCLKTX
tHIZOUT
Stereo Audio CODEC
with FlexSound Technology
MAX9888
24
Figure 4. Digital Microphone Timing Diagram
I2C TIMING CHARACTERSTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Serial-Clock Frequency fSCL Guaranteed by SCL pulse-width low and
high 0 400 kHz
Bus Free Time Between STOP and
START Conditions tBUF 1.3 Fs
Hold Time (Repeated) START
Condition tHD,STA 0.6 Fs
SCL Pulse-Width Low tLOW 1.3 Fs
SCL Pulse-Width High tHIGH 0.6 Fs
Setup Time for a Repeated START
Condition tSU,STA 0.6 Fs
Data Hold Time tHD,DAT RPU = 475I, CB = 100pF, 400pF 0 900 ns
Data Setup Time tSU,DAT 100 ns
SDA and SCL Receiving Rise Time tR(Note 10) 20 +
0.1CB300 ns
SDA and SCL Receiving Fall Time tF(Note 10) 20 +
0.1CB300 ns
SDA Transmitting Fall Time tFRPU = 475I, CB = 100pF, 400pF (Note 10) 20 +
0.05CB250 ns
Setup Time for STOP Condition tSU,STO 0.6 Fs
Bus Capacitance CBGuaranteed by SDA transmitting fall time 400 pF
Pulse Width of Suppressed Spike tSP 0 50 ns
1/fMICCLK
tHD,MIC tSU,MIC
tHD,MIC tSU,MIC
LEFT RIGHT LEFT RIGHT
Stereo Audio CODEC
with FlexSound Technology
MAX9888
25
Note 1: The IC is 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Note 2: Analog supply current = IAVDD + IHPVDD. Speaker supply current = ISPKLVDD + ISPKRVDD. Digital supply current = IDVDD
+ IDVDDS1 + IDVDDS2.
Note 3: Clocking all zeros into the DAC. Slave mode.
Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 5: Gain measured relative to the 0dB setting.
Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000.
Note 7: 0dBFS for DAC input. 1VP-P for INA/INB inputs.
Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some full-
scale performance degradation compared to synchronous integer related MCLK/LRCLK ratios.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10: CB is in pF.
Figure 5. I2C Interface Timing Diagram
Power Consumption
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V)
MODE IAVDD
(mA)
IHPVDD
(mA)
ISPKLVDD +
ISPKRVDD
(mA)
IDVDD
(mA)
IDVDDS1 + IDVDDS2
(mA)
POWER
(mW)
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters
1.35 1.37 1.65 2.91 0.02 16.25
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, 0.1mW/channel,
RHP = 32I
1.35 4.19 1.65 3.02 0.02 21.55
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, ALC enabled
1.35 1.37 1.65 2.96 0.02 16.36
SCL
SDA
tRtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
tSP
Stereo Audio CODEC
with FlexSound Technology
MAX9888
26
Power Consumption (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V)
MODE IAVDD
(mA)
IHPVDD
(mA)
ISPKLVDD +
ISPKRVDD
(mA)
IDVDD
(mA)
IDVDDS1 + IDVDDS2
(mA)
POWER
(mW)
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, EQ enabled
1.35 1.36 1.65 3.27 0.02 16.90
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, digital mixing
1.34 1.36 1.65 2.91 0.02 16.27
DAC Playback 44.1kHz Stereo HP
DAC à HP
24-bit, music filters
1.35 1.37 1.69 2.85 0.02 16.29
DAC Playback 8kHz Stereo HP
DAC à HP
16-bit, voice filters
1.35 1.37 1.65 1.46 0.01 13.65
DAC Playback 8kHz Mono HP
DAC à HP
16-bit, voice filters
1.00 0.71 1.01 1.36 0.01 9.27
DAC Playback 48kHz Stereo SPK
DAC à SPK
24-bit, music filters
1.83 0.02 8.22 2.92 0.02 39.09
DAC Playback 48kHz Mono SPK
DAC à SPK
24-bit, music filters
1.25 0.02 4.31 2.82 0.02 23.32
Line Stereo Record 48kHz
INA à ADC
16-bit, music filters
9.91 0.02 0.39 1.62 0.11 22.48
Line Stereo Record 48kHz, Stereo HP
INA à ADC
INA à HP
16-bit, music filters
10.64 2.65 0.66 1.63 0.11 29.51
Line Stereo Record 48kHz, Stereo SPK
INA à ADC
INA à SPK
16-bit, music filters
10.97 0.03 7.15 1.63 0.12 49.50
Differential Line Record 48kHz
INA à ADCL
INB à ADCR
Differential input
10.49 0.02 0.39 1.63 0.16 23.58
Microphone Stereo Record 48kHz
MIC1/2 à ADC
16-bit, music filters
10.88 0.03 0.69 1.62 0.17 25.43
Microphone Stereo Record 8kHz
MIC1/2 à ADC
16-bit, voice filters
10.77 0.02 0.64 1.03 0.06 23.78
Stereo Audio CODEC
with FlexSound Technology
MAX9888
27
Power Consumption (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V)
MODE IAVDD
(mA)
IHPVDD
(mA)
ISPKLVDD +
ISPKRVDD
(mA)
IDVDD
(mA)
IDVDDS1 + IDVDDS2
(mA)
POWER
(mW)
Microphone Mono Record 48kHz
MIC1/2 à ADC
16-bit, music filters
6.01 0.02 0.66 1.37 0.10 15.97
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters
5.95 0.02 0.64 0.98 0.04 14.94
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters, AGC
5.95 0.02 0.64 0.98 0.04 15.00
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters, AGC, noise gate
5.96 0.02 0.64 0.98 0.04 14.98
Full-Duplex 48kHz Stereo HP
MIC1/2 à ADC
DAC à HP
24-bit, music filters
11.38 1.37 1.70 3.56 0.19 36.06
Full-Duplex 8kHz Mono RCV
MIC1 à ADC
DAC à REC
16-bit, voice filters
6.35 0.02 1.98 1.47 0.03 21.47
Full-Duplex 8kHz Mono HP
MIC1 à ADC
DAC à HP
16-bit, voice filters
6.09 0.71 1.01 1.46 0.03 18.72
Full-Duplex 8kHz Stereo HP
MIC1/2 à ADC
DAC à HP
16-bit, voice filters
10.92 1.37 1.09 1.51 0.05 28.95
Line Playback Stereo HP
INA à HP
Single-ended inputs
1.89 2.65 0.58 0.03 0.01 10.41
Line Playback Stereo SPK
INA à SPK
Single-ended inputs
2.21 0.02 7.05 0.04 0.02 30.19
Line Playback Mono SPK
INA à SPK
Single-ended inputs
1.68 0.02 3.70 0.03 0.02 16.90
Differential Line Playback Stereo HP
INA à HPL
INB à HPR
Differential input
2.46 2.65 0.58 0.03 0.01 11.42
Stereo Audio CODEC
with FlexSound Technology
MAX9888
28
Typical Operating Characteristics
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Microphone to ADC
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
MAX9888 toc01
FREQUENCY (Hz)
THD+N RATIO (dB)
1000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 10,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
VIN = 1VP-P
AVMICPRE_ = 0dB
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
MAX9888 toc02
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
10 100,000
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
VIN = 1VP-P
AVMICPRE_ = 0dB
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
MAX9888 toc03
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
VIN = 1VP-P
AVMICPRE_ = 0dB
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
MAX9888 toc04
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100,000
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
VIN = 1VP-P
AVMICPRE_ = 0dB
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
MAX9888 toc05
FREQUENCY (Hz)
THD+N RATIO (dB)
1000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 10,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
VIN = 0.1VP-P
AVMICPRE_ = +20dB
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
MAX9888 toc06
FREQUENCY (Hz)
THD+N RATIO (dB)
1000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 10,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
VIN = 0.032VP-P
AVMICPRE_ = +30dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
29
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
GAIN vs. FREQUENCY (MIC TO ADC)
MAX9888 toc07
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
1000100
-75
-65
-55
-45
-35
-25
-15
-5
5
-85
10 10,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
VIN = 1VP-P
AVMICPRE_ = 0dB
MODE = 0
MODE = 1
COMMON-MODE REJECTION
RATIO vs. FREQUENCY (MIC TO ADC)
MAX9888 toc08
FREQUENCY (Hz)
CMRR (dB)
10,0001000100
10
20
30
40
50
60
70
80
90
0
10 100,000
AVMICPRE_ = +30dB
AVMICPRE_ = +20dB
AVMICPRE_ = 0dB
VOUT, DIFF = 0dBFS
POWER-SUPPLY REJECTION
RATIO vs. FREQUENCY (MIC TO ADC)
MAX9888 toc09
FREQUENCY (Hz)
PSRR (dB)
10,0001000100
-100
-80
-60
-40
-20
0
-120
10 100,000
VRIPPLE = 200mVP-P
INPUTS AC GROUNDED
RIPPLE ON
SPKLVDD, SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
FFT, 0dBFS (MIC TO ADC)
MAX9888 toc10
FREQUENCY (Hz)
AMPLITUDE (dBV)
350030002500200015001000500
-120
-100
-80
-60
-40
-20
0
-140
0 4000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
AVMICPRE_ = 0dB
FFT, -60dBFS (MIC TO ADC)
MAX9888 toc11
FREQUENCY (Hz)
AMPLITUDE (dBV)
350030002500200015001000500
-120
-100
-80
-60
-40
-20
0
-140
0 4000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
AVMICPRE_ = 0dB
FFT, 0dBFS (MIC TO ADC)
MAX9888 toc12
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
AVMICPRE_ = 0dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
30
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
FFT, -60dBFS (MIC TO ADC)
MAX9888 toc13
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
AVMICPRE_ = 0dB
FFT, 0dBFS (MIC TO ADC)
MAX9888 toc14
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
AVMICPRE_ = 0dB
FFT, -60dBFS (MIC TO ADC)
MAX9888 toc15
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
AVMICPRE_ = 0dB
FFT, 0dBFS (MIC TO ADC)
MAX9888 toc16
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
AVMICPRE_ = 0dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
31
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
FFT, -60dBFS (MIC TO ADC)
MAX9888 toc17
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
AVMICPRE_ = 0dB
SOFTWARE TURN-ON/OFF RESPONSE
(MIC TO ADC)
MAX9888 toc19
SCL
2V/div
ADC
OUTPUT
0.5V/div
10ms/div
ADC ENABLE/DISABLE RESPONSE
(MIC TO ADC)
MAX9888 toc18
SCL
2V/div
ADC
OUTPUT
0.5V/div
10ms/div
Stereo Audio CODEC
with FlexSound Technology
MAX9888
32
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Line to ADC
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
MAX9888 toc20
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
10 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
VIN = 1.4VP-P
AVPGAIN_ = -6dB
CIN = 1µF
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
MAX9888 toc21
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
VIN = 1VP-P
CIN = 1µF
AVPGAIN_ = 0dB
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
MAX9888 toc22
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
VIN = 0.1VP-P
AVPGAIN_ = +20dB
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
MAX9888 toc23
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
VIN = 1VRMS
EXTERNAL GAIN MODE
RIN = 56kI, CIN = 1µF
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO ADC)
MAX9888 toc24
FREQUENCY (Hz)
PSRR (dB)
10,0001000100
-100
-80
-60
-40
-20
0
-120
10 100,000
VRIPPLE = 200mVP-P
INPUTS AC GROUNDED
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON
SPKLVDD, SPKRVDD
Stereo Audio CODEC
with FlexSound Technology
MAX9888
33
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Digital Loopback
FFT, 0dBFS
(SDINS1 TO SDOUTS2 DIGITAL LOOPBACK)
MAX9888 toc25
FREQUENCY (Hz)
AMPLITUDE (dBFS)
15,00010,0005000
-160
-140
-120
-100
-80
-60
-40
-20
0
-180
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
FFT, -60dBFS
(SDINS1 TO SDOUTS2 DIGITAL LOOPBACK)
MAX9888 toc26
FREQUENCY (Hz)
AMPLITUDE (dBFS)
15,00010,0005000
-160
-140
-120
-100
-80
-60
-40
-20
0
-180
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
Stereo Audio CODEC
with FlexSound Technology
MAX9888
34
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Analog Loopback
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE)
MAX9888 toc27
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
10 100,000
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
RHP = 32I, CIN = 1µF
POUT = 0.025W
POUT = 0.01W
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE )
MAX9888 toc28
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
10 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I, CIN = 1µF
POUT = 0.025W
POUT = 0.01W
FFT, 0dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
MAX9888 toc29
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
RHP = 32I
FFT, -60dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
MAX9888 toc30
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
RHP = 32I
FFT, 0dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
MAX9888 toc31
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
FFT, -60dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
MAX9888 toc32
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
Stereo Audio CODEC
with FlexSound Technology
MAX9888
35
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
DAC to Receiver
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER (DAC TO RECEIVER)
MAX9888 toc33
OUTPUT POWER (W)
THD+N RATIO (dB)
0.100.080.060.040.02
-80
-70
-60
f = 100Hz
-50
-40
-30
-20
-10
0
-90
0 0.12
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RREC = 32I
AVREC = +8dB
f = 3000Hz
f = 1000Hz
TOTAL HARMONIC DISTORTION
vs. FREQUENCY (DAC TO RECEIVER)
MAX9888 toc34
FREQUENCY (Hz)
THD+N RATIO (dB)
1000100
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
10 10,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RREC = 32I
POUT = 0.05W
POUT = 0.025W
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO RECEIVER)
MAX9888 toc35
SUPPLY VOLTAGE (V)
OUTPUT POWER PER CHANNEL (mW)
5.04.53.0 3.5 4.0
70
80
90
100
110
120
130
140
60
2.5 5.5
THD+N = 10%
THD+N = 1%
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RREC = 32I
AVREC = +8dB
GAIN vs. FREQUENCY
(DAC TO RECEIVER)
MAX9888 toc36
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
1000100
-4
-3
-2
-1
0
1
2
3
4
5
-5
10 10,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RREC = 32I
POWER CONSUMPTION vs. OUTPUT
POWER (DAC TO RECEIVER)
MAX9888 toc37
OUTPUT POWER (W)
POWER CONSUMPTION (W)
0.100.080.060.040.02
0.05
0.10
0.15
0.20
0.25
0
0 0.12
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RREC = 32I
AVREC = +8dB
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO RECEIVER)
MAX9888 toc38
FREQUENCY (Hz)
PSRR (dB)
10,0001000100
-80
-60
-40
-20
0
-100
10 100,000
VRIPPLE = 200mVP-P
ALL ZEROS AT INPUT
RIPPLE ON SPKLVDD,
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
Stereo Audio CODEC
with FlexSound Technology
MAX9888
36
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
MAX9888 toc39
RECEIVER
OUTPUT
1V/div
SCL
2V/div
10ms/div
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO RECEIVER, VSEN = 0)
MAX9888 toc40
RECEIVER
OUTPUT
1V/div
SCL
2V/div
10ms/div
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO RECEIVER, VSEN = 1) FFT, 0dBFS (DAC TO RECEIVER)
MAX9888 toc41
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RREC = 32I
FFT, -60dBFS (DAC TO RECEIVER)
MAX9888 toc42
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RREC = 32I
FREQUENCY (kHz)
AMPLITUDE (dBm)
1000100101
-100
-80
-60
-40
-20
0
-120
0 10,000
WIDEBAND FFT, 0dBFS
(DAC TO RECEIVER)
MAX9888 toc43
MCLK = 13MHz
LRCLK = 8kHz
PLL MODE
RREC = 32I
FREQUENCY (kHz)
AMPLITUDE (dBm)
1000100101
-100
-80
-60
-40
-20
0
-120
0 10,000
WIDEBAND FFT, -60dBFS
(DAC TO RECEIVER)
MAX9888 toc44
MCLK = 13MHz
LRCLK = 8kHz
PLL MODE
RREC = 32I
Stereo Audio CODEC
with FlexSound Technology
MAX9888
37
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Line to Receiver
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(LINE TO RECEIVER)
MAX9888 toc45
OUTPUT POWER (W)
THD+N RATIO (dB)
0.080.060.02 0.04
-70
-60
-50
-40
-20
-30
-10
0
-80
0 0.10
RREC = 32I
AVREC = +8dB
f = 6000Hz
f = 1000Hz
f = 100Hz
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO RECEIVER)
MAX9888 toc46
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
10 100,000
RREC = 32I
CIN = 1µF
AVREC = +8dB
POUT = 0.025W
POUT = 0.05W
GAIN vs. FREQUENCY (LINE TO RECEIVER)
MAX9888 toc47
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
10,0001000100
-4
-3
-2
-1
0
1
2
3
4
5
-5
10 100,000
RREC = 32I
CIN = 1µF
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO RECEIVER)
MAX9888 toc48
FREQUENCY (Hz)
PSRR (dB)
10,0001000100
-80
-60
-40
-20
0
-100
10 100,000
VRIPPLE = 200mVP-P
INPUT AC GROUNDED
RIPPLE ON SPKLVDD,
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
Stereo Audio CODEC
with FlexSound Technology
MAX9888
38
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
DAC to Speaker
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
MAX9888 toc49
OUTPUT POWER (W)
THD+N RATIO (dB)
1.00.80.60.40.2
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
0 1.2
VSPK_VDD = 4.2V
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
AVSPK_ = +8dB
f = 6000Hz
f = 1000Hz
f = 100Hz
THD+N RATIO (dB)
-70
-60
-50
-40
-30
-20
-10
0
-80
MAX9888 toc50
OUTPUT POWER (W)
0.80.60.40.20 1.0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
f = 100Hz
VSPK_VDD = 3.7V
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
AVSPK_ = +8dB
f = 1000Hz
f = 6000Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
MAX9888 toc51
THD+N RATIO (dB)
-70
-60
-50
-40
-20
-30
-10
-80
0
OUTPUT POWER (W)
0.50.40.30.20.10 0.6
VSPK_VDD = 3.V
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
AVSPK_ = +8dB
f = 6000Hz
f = 1000Hz
f = 100Hz
VSPK_VDD = 4.2V
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
ZSPK = 4I + 33µH
AVSPK_ = +8dB
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
MAX9888 toc52
OUTPUT POWER (W)
THD+N RATIO (dB)
2.01.51.00.50 2.5
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
f = 6000Hz
f = 1000Hz
f = 100Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
VSPK_VDD = 3.7V
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
ZSPK = 4I + 33µH
AVSPK_ = +8dB
MAX9888 toc53
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
OUTPUT POWER (W)
1.51.00.50 2.0
f = 6000Hz
f = 1000Hz
f = 100Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
MAX9888 toc54
OUTPUT POWER (W)
1.21.00.6 0.80.40.2
0 1.4
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
VSPK_VDD = 3V
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 4I + 33µH
AVSPK_ = +8dB
f = 6000Hz
f = 1000Hz
f = 100Hz
Stereo Audio CODEC
with FlexSound Technology
MAX9888
39
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc55
VSPK_VDD = 4.2V
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
AVSPK_ = +8dB
POUT = 0.25W
POUT = 0.55W
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc56
VSPK_VDD = 3.7V
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
AVSPK_ = +8dB
POUT = 0.25W
POUT = 0.55W
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc57
VSPK_VDD = 4.2V
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 4I + 33µH
POUT = 0.5W
POUT = 1.0W
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc58
VSPK_VDD = 3.7V
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 4I + 33µH
POUT = 0.5W
POUT = 1.0W
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
MAX9888 toc59
SUPPLY VOLTAGE (V)
OUTPUT POWER PER CHANNEL (mW)
5.04.54.03.53.0
600
800
1000
1200
1400
1600
1800
2000
2200
400
2.5 5.5
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
THD+N = 10%
THD+N = 10%THD+N = 10%
THD+N = 10%
THD+N = 1%
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
MAX9888 toc60
OUTPUT POWER PER CHANNEL (mW)
500
1000
1500
2000
2500
3000
3500
0
SUPPLY VOLTAGE (V)
5.04.54.03.53.02.5 5.5
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 4I + 33µH
THD+N = 10%
THD+N = 1%
Stereo Audio CODEC
with FlexSound Technology
MAX9888
40
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
GAIN vs. FREQUENCY
(DAC TO SPEAKER)
MAX9888 toc61
NORMALIZED GAIN (dB)
-4
-3
-2
-1
0
1
2
3
4
5
-5
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
FREQUENCY (Hz)
10,000100010010 100,000
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
MAX9888 toc62
OUTPUT POWER PER CHANNEL (W)
0.5 1.0 1.5 2.00 2.5
VSPK_VDD = 4.2V
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
AVSPK_ = +8dB
ZSPK = 4I + 33µH
ZSPK = 4I + 33µH
ZSPK = 8I + 68µH
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
MAX9888 toc63
OUTPUT POWER PER CHANNEL (W)
1.4
1.20.8 1.00.4 0.60.20 1.6
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VSPK_VDD = 3.7V
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
AVSPK_ = +8dB
ZSPK = 4I + 33µH
ZSPK = 8I + 68µH
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
MAX9888 toc64
SPK_VDD SUPPLY VOLTAGE (V)
SPK_VDD SUPPLY CURRENT (mA)
5.04.54.03.53.0
5
10
15
20
25
30
0
2.5 5.5
MCLK = 12.288MHz,
LRCLK = 48kHz
ZSPK = 8I + 68µH
NI MODE
AVSPK_ = +8dB
ALL ZEROS AT INPUT
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO SPEAKER)
MAX9888 toc65
PSRR (dB)
-80
-60
-40
-20
0
-100
FREQUENCY (Hz)
10,000100010010 100,000
VRIPPLE = 200mVP-P
RIPPLE ON SPKLVDD,
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE (DAC TO SPEAKER)
MAX9888 toc66
SUPPLY VOLTAGE (V)
5.0
4.54.03.53.02.5 5.5
PSRR (dB)
-80
-60
-40
-20
-100
0
RIPPLE ON SPKLVDD, SPKRVDD
VRIPPLE = 200mVP-P
f = 1kHz
Stereo Audio CODEC
with FlexSound Technology
MAX9888
41
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
FREQUENCY (Hz)
10,0001000100
10 100,000
CROSSTALK vs. FREQUENCY
(DAC TO SPEAKER)
CROSSTALK (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc67
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO SPEAKER, VSEN = 0)
MAX9888 toc68
SCL
2V/div
SPEAKER
OUTPUT
1V/div
10ms/div
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO SPEAKER, VSEN = 1)
MAX9888 toc69
SCL
2V/div
SPEAKER
OUTPUT
1V/div
10ms/div
FFT, -60dBFS (DAC TO SPEAKER)
MAX9888 toc70
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
ZSPK = 8I + 68µH
FFT, -60dBFS (DAC TO SPEAKER)
MAX9888 toc71
FREQUENCY (Hz)
AMPLITUDE (dbV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
ZSPK = 8I + 68µH
WIDEBAND FFT
(DAC TO SPEAKER)
MAX9888 toc72
FREQUENCY (MHz)
AMPLITUDE (dBm)
10
-50
-40
-30
-20
-10
0
10
20
-60
1 100
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
ZSPK = 8I + 68µH
Stereo Audio CODEC
with FlexSound Technology
MAX9888
42
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Line to Speaker
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO SPEAKER)
OUTPUT POWER (W)
0.80.60.2 0.4
0
MAX9888 toc73
THD+N RATIO (dB)
-70
-60
-50
-40
-20
-30
-10
0
-80
ZSPK = 8I + 68µH
AVSPK_ = +8dB
f = 6000Hz
f = 1000Hz f = 100Hz
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO SPEAKER)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc74
ZSPK = 8I + 68µH
CIN = 1µF
AVSPK_ = +8dB
POUT = 0.55W
POUT = 0.25W
GAIN vs. FREQUENCY
(LINE TO SPEAKER)
MAX9888 toc75
NORMALIZED GAIN (dB)
-4
-3
-2
-1
0
1
2
3
4
5
-5
FREQUENCY (Hz)
10,000100010010 100,000
ZSPK = 8I + 68µH
CIN = 1µF
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO SPEAKER)
MAX9888 toc76
PSRR (dB)
-80
-60
-40
-20
0
-100
FREQUENCY (Hz)
10,000100010010 100,000
VRIPPLE = 200mVRMS
INPUT AC GROUNDED
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON SPKLVDD,
SPKRVDD
FREQUENCY (Hz)
10,0001000100
10 100,000
CROSSTALK vs. FREQUENCY
(LINE TO SPEAKER)
CROSSTALK (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc77
ZSPK = 8I + 68µH
Stereo Audio CODEC
with FlexSound Technology
MAX9888
43
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
DAC to Headphone
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX9888 toc78
OUTPUT POWER (W)
THD+N RATIO (dB)
0.040.030.020.010 0.05
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RHP = 32I
AVHP_ = +3dB
f = 3000Hz
f = 100Hz
f = 1000Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX9888 toc79
OUTPUT POWER (W)
THD+N RATIO (dB)
0.040.030.020.010 0.05
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
RHP = 32I
AVHP_ = +3dB
f = 6000Hz
f = 100Hz
f = 1000Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX9888 toc80
OUTPUT POWER (W)
THD+N RATIO (dB)
0.040.030.020.010 0.05
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
AVHP_ = +3dB
f = 6000Hz
f = 100Hz
f = 1000Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX9888 toc81
OUTPUT POWER (W)
THD+N RATIO (dB)
0.040.030.020.010 0.05
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
RHP = 32I
AVHP_ = +3dB
f = 6000Hz
f = 100Hz
f = 1000Hz
MAX9888 toc82
OUTPUT POWER (W)
0.070.060.04 0.050.02 0.030.010 0.08
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 16I
AVHP_ = +3dB
f = 6000Hz
f = 100Hz
f = 1000Hz
FREQUENCY (Hz)
1000100
10 10,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO SPEAKER)
MAX9888 toc83
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RHP = 32I
AVHP_ = +3dB
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
POUT = 0.01W
POUT = 0.02W
Stereo Audio CODEC
with FlexSound Technology
MAX9888
44
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc84
POUT = 0.025W
POUT = 0.1W
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
RHP = 32I
AVHP_ = +3dB
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9888 toc85
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
AVHP_ = +3dB
POUT = 0.025W
POUT = 0.01W
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9888 toc86
FREQUENCY (Hz)
THD+N RATIO (dB)
10,0001000100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100,000
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
RHP = 32I
AVHP_ = +3dB
POUT = 0.025W
POUT = 0.01W
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc87
POUT = 0.01W
POUT = 0.0.25W
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 16I
GAIN vs. FREQUENCY
(DAC TO HEADPHONE)
MAX9888 toc88
NORMALIZED GAIN (dB)
-60
-50
-40
-30
-20
-10
0
10
-70
FREQUENCY (Hz)
10,000100010010 100,000
MCLK = 13MHz
LRCLK = 8kHz
NI MODE
RHP = 32I
MODE = 1
MODE = 0
HPVDD INPUT CURRENT vs. OUTPUT
POWER (DAC TO HEADPHONE)
MAX9888 toc89
OUTPUT POWER PER CHANNEL (mW)
HPVDD INPUT CURRENT (mA)
1010.1
20
40
60
80
100
120
0
0.01 100
RHP = 16I
RHP = 32I
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
Stereo Audio CODEC
with FlexSound Technology
MAX9888
45
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
MAX9888 toc90
PSRR (dB)
-80
-60
-40
-20
0
-100
FREQUENCY (Hz)
10,000100010010 100,000
VRIPPLE = 200mVP-P
INPUT ALL ZEROS
RIPPLE ON SPKLVDD,
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
CROSSTALK vs. FREQUENCY
(DAC TO HEADPHONE)
MAX9888 toc91
CROSSTALK (dB)
-90
-80
-70
-60
-50
-40
-100
FREQUENCY (Hz)
10,000100010010 100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 0)
MAX9888 toc92
SCL
2V/div
HEADPHONE
OUTPUT
0.5V/div
10ms/div
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 1)
MAX9888 toc93
SCL
2V/div
HEADPHONE
OUTPUT
0.5V/div
10ms/div
FFT, 0dBFS (DAC TO HEADPHONE)
MAX9888 toc94
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz,
LRCLK = 8kHz
FREQ MODE
RHP = 32I
FFT, -60dBFS (DAC TO HEADPHONE)
MAX9888 toc95
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-140
-120
-100
-80
-60
-40
-20
0
-160
0 20,000
MCLK = 13MHz,
LRCLK = 8kHz
FREQ MODE
RHP = 32I
Stereo Audio CODEC
with FlexSound Technology
MAX9888
46
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
FFT, -60dBFS (DAC TO HEADPHONE)
MAX9888 toc97
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-140
-120
-100
-80
-60
-40
-20
0
-160
0 20,000
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
RHP = 32I
FFT, 0dBFS (DAC TO HEADPHONE)
MAX9888 toc98
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
FFT, 0dBFS (DAC TO HEADPHONE)
MAX9888 toc96
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
RHP = 32I
Stereo Audio CODEC
with FlexSound Technology
MAX9888
47
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
FFT, 0dBFS (DAC TO HEADPHONE)
MAX9888 toc100
FREQUENCY (Hz)
AMPLITUDE (dbV)
15,00010,0005000
-120
-100
-80
-60
-40
-20
0
-140
0 20,000
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
RHP = 32I
FFT, -60dBFS (DAC TO HEADPHONE)
MAX9888 toc101
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-140
-120
-100
-80
-60
-40
-20
0
-160
0 20,000
MCLK = 2.288MHz
LRCLK = 96kHz
NI MODE
RHP = 32I
WIDEBAND FFT, 0dBFS
(DAC TO HEADPHONE)
FREQUENCY (kHz)
AMPLITUDE (dBm)
1000100101
-80
-60
-40
-20
0
20
-100
0 10,000
MAX9888 toc102
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
AVHP_ = -3dB
RHP = 32I
FFT, -60dBFS (DAC TO HEADPHONE)
MAX9888 toc99
FREQUENCY (Hz)
AMPLITUDE (dBV)
15,00010,0005000
-140
-120
-100
-80
-60
-40
-20
0
-160
0 20,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
WIDEBAND FFT, -60dBFS
(DAC TO HEADPHONE)
FREQUENCY (kHz)
AMPLITUDE (dBm)
1000100101
-80
-60
-40
-20
0
20
-100
0 10,000
MAX9888 toc103
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
AVHP_ = -3dB
RHP = 32I
Stereo Audio CODEC
with FlexSound Technology
MAX9888
48
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Line to Headphone
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO HEADPHONE)
OUTPUT POWER (W)
THD+N RATIO (dB)
0.040.030.01 0.02
-70
-60
-50
-40
-20
-30
-10
0
-80
0 0.05
MAX9888 toc104
RHP = 32I
AVHP_ = +3dB
f = 6000Hz
f = 100Hz
f = 1000Hz
FREQUENCY (Hz)
10,0001000100
10 100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO HEADPHONE)
THD+N RATIO (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc105
RHP = 32I
CIN = 1µF
POUT = 0.01W
POUT = 0.025W
GAIN vs. FREQUENCY
(LINE TO HEADPHONE)
MAX9888 toc106
NORMALIZED GAIN (dB)
-4
-3
-2
-1
0
1
2
3
4
5
-5
FREQUENCY (Hz)
10,000100010010 100,000
RHP = 32I
CIN = 1µF
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
MAX9888 toc107
PSRR (dB)
-80
-60
-40
-20
0
-100
FREQUENCY (Hz)
10,000100010010 100,000
VRIPPLE = 200mVP-P
RIPPLE ON SPKLVDD,
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
FREQUENCY (Hz)
10,0001000100
10 100,000
CROSSTALK vs. FREQUENCY
(LINE TO HEADPHONE)
CROSSTALK (dB)
-80
-70
-60
-50
-40
-30
-20
-10
-90
0
MAX9888 toc108
RHP = 32I
COMMON-MODE REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
MAX9888 toc109
CMRR (dB)
10
20
30
40
50
60
70
0
FREQUENCY (Hz)
10,000100010010 100,000
VOUT = -6dBV
CIN = 1µF
RHP = 32I
AVPGAIN_ = 20dB
AVPGAIN_ = 0dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
49
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from
HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS
= 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB,
AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
1. TA = +25NC, unless otherwise noted.)
Speaker Bypass Switch
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(SPEAKER BYPASS SWITCH)
OUTPUT POWER (W)
THD+N RATIO (dB)
0.15 0.200.100.05
-70
-60
-50
-40
-30
-20
-10
0
-80
0
MAX9888 toc110
RECEIVER AMPLIFIER DRIVING
LOUDSPEAKER
ZSPK = 8I + 68µH
f = 1000Hz
f = 100Hz
f = 6000Hz
ON RESISTANCE vs. VCOM
(SPEAKER BYPASS SWITCH)
MAX9888 toc111
VCOM (V)
RON (I)
541 2 3
0.5
1.0
1.5
2.0
2.5
3.0
3.5
ISW = 20mA
VSPK_VDD = 3.0V
VSPK_VDD = 3.7V
VSPK_VDD = 4.2V
VSPK_VDD = 5.0V
4.0
0
0 6
OFF-ISOLATION vs. FREQUENCY
(SPEAKER BYPASS SWITCH)
MAX9888 toc112
FREQUENCY (Hz)
OFF-ISOLATION (dB)
10,0001000100
-100
-80
-60
-40
-20
0
-120
10 100,000
SPEAKER AMP DRIVING LOUDSPEAKER
SPEAKER BYPASS SWITCH OPEN
MEASURED AT RXIN_
50I LOAD ON RXIN_
RECEIVER AMP DRIVING RXIN_
Stereo Audio CODEC
with FlexSound Technology
MAX9888
50
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
123456789
B
C
D
E
F
G
MAX9888
A
MCLK IRQ
SPKRVDD
SPKRVDD SDINS1
SPKLGNDSPKRP SPKLGND HPSNS
JACKSNS
SCLSDA REG
AVDDDVDD PREG
REF
AGND MICBIAS
SPKLVDD SPKLPSPKRGND SPKLN RECN/
RXINN
SPKLVDD SPKLP
SPKRGND SPKLN RECP/
RXINP HPVDD HPGND
SPKRP
DGND
SPKRN
SPKRN
HPR
HPL
HPVSS
C1P C1N
N.C. INB2
BCLKS1 LRCLKS1
N.C.
N.C.
N.C.N.C.
N.C. INB1 INA2/
EXTMICN
DVDDS1 SDOUTS1 MIC1P/
DIGMICDATA
INA1/
EXTMICP
BCLKS2 LRCLKS2 MIC1N/
DIGMICCLK MIC2P
SDOUTS2 DVDDS2 SDINS2 MIC2N
Stereo Audio CODEC
with FlexSound Technology
MAX9888
51
Pin Description
PIN NAME FUNCTION
A1, B1 SPKRN Negative Right-Channel Class D Speaker Output
A2, B2 SPKRGND Right-Speaker Ground
A3, B3 SPKLVDD Left-Speaker, REF, Receiver Amplifier Power Supply. Bypass to SPKLGND with a 1FF and a 10FF
capacitor.
A4, B4 SPKLP Positive Left-Channel Class D Speaker Output
A5, B5 SPKLN Negative Left-Channel Class D Speaker Output
A6 RECP/RXINP Positive Receiver Amplifier Output. Can be positive bypass switch input when receiver amp is shut
down.
A7 HPVDD Headphone Power Supply. Bypass to HPGND with a 1FF capacitor.
A8 HPGND Headphone Ground
A9 HPVSS Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
B6 RECN/RXINN Negative Receiver Amplifier Output. Can be negative bypass switch input when receiver amp is shut
down.
B7 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
B8 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
B9 HPL Left-Channel Headphone Output
C1, C2 SPKRP Positive Right-Channel Class D Speaker Output
C3, D3 SPKRVDD Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor.
C4, C5 SPKLGND Left-Speaker Ground
C6 HPSNS Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or connect to
ground.
C7, D5, D7,
E3, E6, E7 N.C. No Connection
C8 INB2 Single-Ended Line Input B2. Also positive differential line input B.
C9 HPR Right-Channel Headphone Output
D1 BCLKS1 S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the MAX9888 is in slave mode and
an output when in master mode. The input/output voltage is referenced to DVDDS1.
D2 LRCLKS1
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and
determines whether S1 audio data is routed to the left or right channel. In TDM mode, LRCLKS1 is a
frame sync pulse. LRCLKS1 is an input when the MAX9888 is in slave mode and an output when in
master mode. The input/output voltage is referenced to DVDDS1.
D4 SDINS1 S1 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS1.
D6 JACKSNS Jack Sense. Detects the insertion of a jack. See the Headset Detection section.
D8 INB1 Single-Ended Line Input B1. Also negative differential line input B.
D9 INA2/
EXTMICN
Single-Ended Line Input A2. Also positive differential line input A or negative differential external
microphone input.
Stereo Audio CODEC
with FlexSound Technology
MAX9888
52
Pin Description (continued)
PIN NAME FUNCTION
E1 DVDDS1 S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
E2 MCLK Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
E4 SDOUTS1 S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1.
E5 IRQ
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00
change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ
until it is cleared by reading the I2C status register 0x00. Connect a 10kI pullup resistor to DVDD for
full output swing.
E8 MIC1P/
DIGMICDATA
Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
be retasked as a digital microphone data input.
E9 INA1/
EXTMICP
Single-Ended Line Input A1. Also negative differential line input A or positive differential external
microphone input.
F1 DGND Digital Ground
F2 BCLKS2 S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode and an
output when in master mode. The input/output voltage is referenced to DVDDS2.
F3 LRCLKS2
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and
determines whether audio data on S2 is routed to the left or right channel. In TDM mode, LRCLKS2 is
a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode and an output when in master
mode. The input/output voltage is referenced to DVDDS2.
F4 SDA I2C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing.
F5 SCL I2C Serial-Clock Input
F6 REG Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
F7 REF Converter Reference. Bypass to AGND with a 2.2FF capacitor.
F8 MIC1N/
DIGMICCLK
Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
be retasked as a digital microphone clock output.
F9 MIC2P Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
G1 SDOUTS2 S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2.
G2 DVDDS2 S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
G3 SDINS2 S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2.
G4 DVDD Digital Power Supply. Supply for the digital core and I2C interface. Bypass to DGND with a 1FF
capacitor.
G5 AVDD Analog Power Supply. Bypass to AGND with a 1FF capacitor.
G6 PREG Positive Internal Regulated Supply. Bypass to AGND with a 1FF capacitor.
G7 AGND Analog Ground
G8 MICBIAS Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external resistor in the 2.2kI to 1kI
range should be used to set the microphone current.
G9 MIC2N Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
Stereo Audio CODEC
with FlexSound Technology
MAX9888
53
Detailed Description
The MAX9888 is a fully integrated stereo audio codec
with FlexSound technology and integrated amplifiers.
Two differential microphone amplifiers can accept sig-
nals from three analog inputs. One input can be retasked
to support two digital microphones. Any combination of
two microphones (analog or digital) can be recorded
simultaneously. The analog signals are amplified up
to 50dB and recorded by the stereo ADC. The digital
record path supports voice filtering with selectable
preset highpass filters and high stopband attenuation
at fS/2. An automatic gain control (AGC) circuit moni-
tors the digitized signal and automatically adjusts the
analog microphone gain to make best use of the ADC’s
dynamic range. A noise gate attenuates signals below
the user-defined threshold to minimize the noise output
by the ADC.
The IC includes two analog line inputs. One of the line
inputs can be optionally retasked as a third analog micro-
phone input. Both line inputs support either stereo single-
ended input signals or mono differential signals. The line
inputs are preamplified and then routed either to the ADC
for recording or to the output amplifiers for playback.
Integrated analog switches allow two differential micro-
phone signals to be routed out the third microphone
input to an external device. This eliminates the need
for an external analog switch in systems that have two
devices recording signals from the same microphone.
Through two digital audio interfaces, the device can
transmit one stereo audio signal and receive two stereo
audio signals in a wide range of formats including I2S,
PCM, and up to four mono slots in TDM. Each interface
can be connected to either of two audio ports (S1 and
S2) for communication with external devices. Both audio
interfaces support 8kHz to 96kHz sample rates. Each
input signal is independently equalized using 5-band
parametric equalizers. A multiband automatic level
control (ALC) boosts signals by up to 12dB. One signal
path additionally supports the same voiceband filtering
as the ADC path.
The IC includes a differential receiver amplifier, stereo
Class D speaker amplifiers, and DirectDrive true ground
stereo headphone amplifiers.
When the receiver amplifier is disabled, analog switches
allow RECP/RXINP and RECN/RXINN to be reused for
signal routing. In systems where a single transducer is
used for both the loudspeaker and receiver, an exter-
nal receiver amplifier can be routed to the left speaker
through RECP/RXINP and RECN/RXINN, bypassing the
Class D amplifier, to connect to the loudspeaker. If the
internal receiver amplifier is used, then leave RECP/
RXINP and RECN/RXINN unconnected. In systems
where an external amplifier drives both the receiver and
the MAX9888’s input, one of the differential signals can
be disconnected from the receiver when not needed
by passing it through the analog switch that connects
RECP/RXINP to RECN/RXINN.
The stereo Class D amplifier provides efficient amplifi-
cation for two speakers. The amplifier includes active
emissions limiting to minimize the radiated emissions
(EMI) traditionally associated with Class D. In most
systems, no output filtering is required to meet standard
EMI limits.
To optimize speaker sound quality, the IC includes an
excursion limiter, a distortion limiter, and a power limiter.
The excursion limiter is a dynamic highpass filter with
variable corner frequency that increases in response
to high signal levels. Low-frequency energy typically
causes more distortion than useful sound at high sig-
nal levels, so attenuating low frequencies allows the
speaker to play louder without distortion or damage. At
lower signal levels, the filter corner frequency reduces
to pass more low frequency energy when the speaker
can handle it. The distortion limiter reduces the volume
when the output signal exceeds a preset distortion level.
This ensures that regardless of input signal and battery
voltage, excessive distortion is never heard by the user.
The power limiter monitors the continuous power into the
loudspeaker and lowers the signal level if the speaker is
at risk of overheating.
The stereo DirectDrive headphone amplifier uses an
inverting charge pump to generate a ground-referenced
output signal. This eliminates the need for DC-blocking
capacitors or a midrail bias for the headphone jack
ground return. Ground sense reduces output noise
caused by ground return current.
The IC integrates jack detection allowing the detection
of insertion and removal of accessories as well as button
presses.
Stereo Audio CODEC
with FlexSound Technology
MAX9888
54
Table 1. Register Map
I2C Slave Address
Configure the MAX9888 using the I2C control bus. The
IC uses a slave address of 0x20 or 00100000 for write
operations and 0x21 or 00100001 for read operations.
See the I2C Serial Interface section for a complete inter-
face description.
Registers
Table 1 lists all of the registers, their addresses, and
power-on-reset states. Registers 0x00 to 0x03 and 0xFF
are read-only while all of the other registers are read/
write. Write zeros to all unused bits in the register table
when updating the register, unless otherwise noted.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE
STATUS
Status CLD SLD ULK JDET 0x00 R 103
Microphone
AGC/NG NG AGC 0x01 R 65
Jack Status JKSNS 0x02 R 101
Battery
Voltage VBAT 0x03 R/W 102
Interrupt
Enable ICLD ISLD IULK 0 0 0 IJDET 0 0x0F 0x00 R/W 103
MASTER CLOCK CONTROL
Master Clock 0 0 PSCLK 0 0 0 0 0x10 0x00 R/W 76
DAI1 CLOCK CONTROL
Clock Mode SR1 FREQ1 0x11 0x00 R/W 76
Any Clock
Control
PLL1 NI1[14:8] 0x12 0x00 R/W 77
NI1[7:1] NI1[0] 0x13 0x00 R/W 77
DAI1 CONFIGURATION
Format MAS1 WCI1 BCI1 DLY1 0 TDM1 FSW1 WS1 0x14 0x00 R/W 71
Clock OSR1 0 0 0 BSEL1 0x15 0x00 R/W 72
I/O
Configuration SEL1 LTEN1 LBEN1 DMONO1 HIZOFF1 SDOEN1 SDIEN1 0x16 0x00 R/W 72
Time-Division
Multiplex SLOTL1 SLOTR1 SLOTDLY1 0x17 0x00 R/W 73
Filters MODE1 AVFLT1 DHF1 DVFLT1 0x18 0x00 R/W 79
DAI2 CLOCK CONTROL
Clock Mode SR2 0 0 0 0 0x19 0x00 R/W 76
Any Clock
Control
PLL2 NI2[14:8] 0x1A 0x00 R/W 77
NI2[7:1] NI2[0] 0x1B 0x00 R/W 77
DAI2 CONFIGURATION
Format MAS2 WCI2 BCI2 DLY2 0 TDM2 FSW2 WS2 0x1C 0x00 R/W 71
Clock 0 0 0 0 0 BSEL2 0x1D 0x00 R/W 72
I/O
Configuration SEL2 0 LBEN2 DMONO2 HIZOFF2 SDOEN2 SDIEN2 0x1E 0x00 R/W 72
Stereo Audio CODEC
with FlexSound Technology
MAX9888
55
Table 1. Register Map (continued)
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE
Time-Division
Multiplex SLOTL2 SLOTR2 SLOTDLY2 0x1F 0x00 R/W 73
Filters 0 0 0 0 DHF2 0 0 DCB2 0x20 0x00 R/W 79
MIXERS
DAC Mixer MIXDAL MIXDAR 0x21 0x00 R/W 85
Left ADC
Mixer MIXADL 0x22 0x00 R/W 64
Right ADC
Mixer MIXADR 0x23 0x00 R/W 64
Preoutput 1
Mixer 0 0 0 0 MIXOUT1 0x24 0x00 R/W 86
Preoutput 2
Mixer 0 0 0 0 MIXOUT2 0x25 0x00 R/W 86
Preoutput 3
Mixer 0 0 0 0 MIXOUT3 0x26 0x00 R/W 86
Headphone
Amplifier
Mixer
MIXHPL MIXHPR 0x27 0x00 R/W 97
Receiver
Amplifier
Mixer
0 0 0 0 MIXREC 0x28 0x00 R/W 88
Speaker
Amplifier
Mixer
MIXSPL MIXSPR 0x29 0x00 R/W 90
LEVEL CONTROL
Sidetone DSTS 0 DVST 0x2A 0x00 R/W 69
DAI1
Playback
Level
DV1M 0 DV1G DV1 0x2B 0x00 R/W 84
DAI1
Playback
Level
0 0 0 EQCLP1 DVEQ1 0x2C 0x00 R/W 83
DAI2
Playback
Level
DV2M 0 0 0 DV2 0x2D 0x00 R/W 84
DAI2
Playback
Level
0 0 0 EQCLP2 DVEQ2 0x2E 0x00 R/W 83
Left ADC
Level 0 0 AVLG AVL 0x2F 0x00 R/W 68
Right ADC
Level 0 0 AVRG AVR 0x30 0x00 R/W 68
Microphone
1 Input Level 0 PA1EN PGAM1 0x31 0x00 R/W 61
Stereo Audio CODEC
with FlexSound Technology
MAX9888
56
Table 1. Register Map (continued)
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE
Microphone
2 Input Level 0 PA2EN PGAM2 0x32 0x00 R/W 61
INA Input
Level 0 INAEXT 0 0 0 PGAINA 0x33 0x00 R/W 63
INB Input
Level 0 INBEXT 0 0 0 PGAINB 0x34 0x00 R/W 63
Preoutput 1
Level 0 0 0 0 PGAOUT1 0x35 0x00 R/W 87
Preoutput 2
Level 0 0 0 0 PGAOUT2 0x36 0x00 R/W 87
Preoutput 3
Level 0 0 0 0 PGAOUT3 0x37 0x00 R/W 87
Left
Headphone
Amplifier
Volume
Control
HPLM 0 0 HPVOLL 0x38 0x00 R/W 97
Right
Headphone
Amplifier
Volume
Control
HPRM 0 0 HPVOLR 0x39 0x00 R/W 97
Receiver
Amplifier
Volume
Control
RECM 0 0 RECVOL 0x3A 0x00 R/W 88
Left Speaker
Amplifier
Volume
Control
SPLM 0 0 SPVOLL 0x3B 0x00 R/W 90
Right
Speaker
Amplifier
Volume
Control
SPRM 0 0 SPVOLR 0x3C 0x00 R/W 90
MICROPHONE AGC
Configuration AGCSRC AGCRLS AGCATK AGCHLD 0x3D 0x00 R/W 65
Threshold ANTH AGCTH 0x3E 0x00 R/W 66
SPEAKER SIGNAL PROCESSING
Excursion
Limiter Filter 0 DHPUCF 0 0 DHPLCF 0x3F 0x00 R/W 92
Excursion
Limiter
Threshold
0 0 0 0 0 DHPTH 0x40 0x00 R/W 92
ALC ALCEN ALCRLS ALCMB ALCTH 0x41 0x00 R/W 82
Stereo Audio CODEC
with FlexSound Technology
MAX9888
57
Table 1. Register Map (continued)
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE
Power Limiter PWRTH 0 PWRK 0x42 0x00 R/W 93
Power Limiter PWRT2 PWRT1 0x43 0x00 R/W 94
Distortion
Limiter THDCLP 0 THDT1 0x44 0x00 R/W 95
CONFIGURATION
Audio Input INADIFF INBDIFF 0 0 0 0 0 0 0x45 0x00 R/W 63
Microphone MICCLK DIGMICL DIGMICR 0 0 EXTMIC 0x46 0x00 R/W 61
Level Control VS2EN VSEN ZDEN 0 0 0 EQ2EN EQ1EN 0x47 0x00 R/W 99, 83
Bypass
Switches INABYP 0 0 MIC2BYP 0 0 RECBYP SPKBYP 0x48 0x00 R/W 62, 98
Jack
Detection JDETEN 0 0 0 0 0 JDEB 0x49 0x00 R/W 101
POWER MANAGEMENT
Input Enable INAEN INBEN 0 0 MBEN 0 ADLEN ADREN 0x4A 0x00 R/W 59
Output Enable HPLEN HPREN SPLEN SPREN RECEN 0 DALEN DAREN 0x4B 0x00 R/W 59
System
Enable SHDN VBATEN 0 0 0 0 JDWK 0 0x4C 0x00 R/W 59
DSP COEFFICIENTS
EQ Band 1
(DAI1/DAI2)
K_1[15:8] 0x50/0x82 0xXX R/W 82
K_1[7:0] 0x51/0x83 0xXX R/W 82
K1_1[15:8] 0x52/0x84 0xXX R/W 82
K1_1[7:0] 0x53/0x85 0xXX R/W 82
K2_1[15:8] 0x54/0x86 0xXX R/W 82
K2_1[7:0] 0x55/0x87 0xXX R/W 82
c1_1[15:8] 0x56/0x88 0xXX R/W 82
c1_1[7:0] 0x57/0x89 0xXX R/W 82
c2_1[15:8] 0x58/0x8A 0xXX R/W 82
c2_1[7:0] 0x59/0x8B 0xXX R/W 82
EQ Band 2
(DAI1/DAI2)
K_2[15:8] 0x5A/0x8C 0xXX R/W 82
K_2[7:0] 0x5B/0x8D 0xXX R/W 82
K1_2[15:8] 0x5C/0x8E 0xXX R/W 82
K1_2[7:0] 0x5D/0x8F 0xXX R/W 82
K2_2[15:8] 0x5E/0x90 0xXX R/W 82
K2_2[7:0] 0x5F/0x91 0xXX R/W 82
c1_2[15:8] 0x60/0x92 0xXX R/W 82
c1_2[7:0] 0x61/0x93 0xXX R/W 82
c2_2[15:8] 0x62/0x94 0xXX R/W 82
c2_2[7:0] 0x63/0x95 0xXX R/W 82
Stereo Audio CODEC
with FlexSound Technology
MAX9888
58
Table 1. Register Map (continued)
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE
EQ Band 3
(DAI1/DAI2)
K_3[15:8] 0x64/0x96 0xXX R/W 82
K_3[7:0] 0x65/0x97 0xXX R/W 82
K1_3[15:8] 0x66/0x98 0xXX R/W 82
K1_3[7:0] 0x67/0x99 0xXX R/W 82
K2_3[15:8] 0x68/0x9A 0xXX R/W 82
K2_3[7:0] 0x69/0x9B 0xXX R/W 82
c1_3[15:8] 0x6A/0x9C 0xXX R/W 82
c1_3[7:0] 0x6B/0x9D 0xXX R/W 82
c2_3[15:8] 0x6C/0x9E 0xXX R/W 82
c2_3[7:0] 0x6D/0x9F 0xXX R/W 82
EQ Band 4
(DAI1/DAI2)
K_4[15:8] 0x6E/0xA0 0xXX R/W 82
K_4[7:0] 0x6F/0xA1 0xXX R/W 82
K1_4[15:8] 0x70/0xA2 0xXX R/W 82
K1_4[7:0] 0x71/0xA3 0xXX R/W 82
K2_4[15:8] 0x72/0xA4 0xXX R/W 82
K2_4[7:0] 0x73/0xA5 0xXX R/W 82
c1_4[15:8] 0x74/0xA6 0xXX R/W 82
c1_4[7:0] 0x75/0xA7 0xXX R/W 82
c2_4[15:8] 0x76/0xA8 0xXX R/W 82
c2_4[7:0] 0x77/0xA9 0xXX R/W 82
EQ Band 5
(DAI1/DAI2)
K_5[15:8] 0x78/0xAA 0xXX R/W 82
K_5[7:0] 0x79/0xAB 0xXX R/W 82
K1_5[15:8] 0x7A/0xAC 0xXX R/W 82
K1_5[7:0] 0x7B/0xAD 0xXX R/W 82
K2_5[15:8] 0x7C/0xAE 0xXX R/W 82
K2_5[7:0] 0x7D/0xAF 0xXX R/W 82
c1_5[15:8] 0x7E/0xB0 0xXX R/W 82
c1_5[7:0] 0x7F/0xB1 0xXX R/W 82
c2_5[15:8] 0x80/0xB2 0xXX R/W 82
c2_5[7:0] 0x81/0xB3 0xXX R/W 82
Excursion
Limiter
Biquad
(DAI1/DAI2)
a1[15:8] 0xB4/0xBE 0xXX R/W 91
a1[7:0] 0xB5/0xBF 0xXX R/W 91
a2[15:8] 0xB6/0xC0 0xXX R/W 91
a2[7:0] 0xB7/0xC1 0xXX R/W 91
b0[15:8] 0xB8/0xC2 0xXX R/W 91
b0[7:0] 0xB9/0xC3 0xXX R/W 91
b1[15:8] 0xBA/0xC4 0xXX R/W 91
b1[7:0] 0xBB/0xC5 0xXX R/W 91
b2[15:8] 0xBC/0xC6 0xXX R/W 91
b2[7:0] 0xBD/0xC7 0xXX R/W 91
REVISION ID
Rev ID REV 0xFF 0x43 R 104
Stereo Audio CODEC
with FlexSound Technology
MAX9888
59
Power Management
The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply
current.
Table 2. Power Management Registers
REGISTER BIT NAME DESCRIPTION
0x4C
7SHDN
Global Shutdown
Disables everything except the headset detection circuitry, which is controlled
separately.
0 = Device shutdown
1 = Device enabled
6 VBATEN See the Battery Measurement section.
1 JDWK See the Headset Detection section.
0x4A
7 INAEN
Line Input A Enable
0 = Disabled
1 = Enabled
6 INBEN
Line Input B Enable
0 = Disabled
1 = Enabled
3 MBEN
Microphone Bias Enable
0 = Disabled
1 = Enabled
1 ADLEN
Left ADC Enable
0 = Disabled
1 = Enabled
0 ADREN
Right ADC Enable
0 = Disabled
1 = Enabled
0x4B
7 HPLEN
Left Headphone Enable
0 = Disabled
1 = Enabled
6 HPREN
Right Headphone Enable
0 = Disabled
1 = Enabled
5 SPLEN
Left Speaker Enable
0 = Disabled
1 = Enabled
4 SPREN
Right Speaker Enable
0 = Disabled
1 = Enabled
3 RECEN
Receiver Enable
0 = Disabled
1 = Enabled
1 DALEN
Left DAC Enable
0 = Disabled
1 = Enabled
0 DAREN
Right DAC Enable
0 = Disabled
1 = Enabled
Stereo Audio CODEC
with FlexSound Technology
MAX9888
60
Microphone Inputs
The device includes three differential microphone inputs
and a low-noise microphone bias for powering the micro-
phones (Figure 6). One microphone input can also be con-
figured as a digital microphone input accepting signals
from up to two digital microphones. Two microphones,
analog or digital, can be recorded simultaneously.
In the typical application, one microphone input is used
for the handset microphone and the other is used as an
accessory microphone. In systems using a background
noise microphone, INA can be retasked as another
microphone input.
In systems where the codec is not the only device
recording microphone signals, connect microphones to
MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N
then become outputs that route the microphone signals
to an external device as needed. Two devices can then
record microphone signals without needing external
analog switches.
Analog microphone signals are amplified by two stages
of gain and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable-gain amplifier (PGA) adjustable
from 0dB to 20dB in 1dB steps. To maximize the signal-
to-noise ratio, use the gain in the first stage whenever
possible. Zero-crossing detection is included on the PGA
to minimize zipper noise while making gain changes.
Figure 6. Microphone Input Block Diagram
MIC1P/
DIGMICDATA
MICBIAS
MBEN
MCLK
PSCLK
REG
MIC1N/
DIGMICCLK
MIC2BYP
INABYP
EXTMIC PA1EN:
0/20/30dB
PGAM1:
+20dB TO 0dB
MIX
MIX
MIXADL
MIXADR
ADCL
EXTMIC PA2EN:
0/20/30dB
PGAINA:
+20dB TO -6dB
PGAINA:
+20dB TO -6dB
MIC2P
MIC2N
INA1/EXTMICP
PGAM1:
+20dB TO 0dB
INADIFF
ADLEN
ADREN
INA2/EXTMICN
ADCR
CLOCK
CONTROL
Stereo Audio CODEC
with FlexSound Technology
MAX9888
61
Table 3. Microphone Input Registers
REGISTER BIT NAME DESCRIPTION
0x31/0x32
6
PA1EN/PA2EN
MIC1/MIC2 Preamplifier Gain
Course microphone gain adjustment.
00 = Preamplifier disabled
01 = 0dB
10 = 20dB
11 = 30dB
5
4
PGAM1/PGAM2
MIC1/MIC2 PGA
Fine microphone gain adjustment.
3
VALUE GAIN (dB) VALUE GAIN (dB)
0x00 +20 0x0B +9
0x01 +19 0x0C +8
2
0x02 +18 0x0D +7
0x03 +17 0x0E +6
0x04 +16 0x0F +5
1
0x05 +15 0x10 +4
0x06 +14 0x11 +3
0x07 +13 0x12 +2
0
0x08 +12 0x13 +1
0x09 +11 0x14 to 0x1F 0
0x0A +10
0x46
7
MICCLK
Digital Microphone Clock Frequency
Select a frequency that is within the digital microphone’s clock frequency range.
Set OSR1 = 1 when using a digital microphone.
00 = PCLK/8
01 = PCLK/6
10 = 64 x LRCLK
11 = Reserved
6
5 DIGMICL
Left Digital Microphone Enable
Set PAL1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
4 DIGMICR
Right Digital Microphone Enable
Set PAR1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
1
EXTMIC
External Microphone Connection
Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using
INA_/EXTMIC_ as a microphone input.
00 = Disabled
01 = MIC1 input
10 = MIC2 input
11 = Reserved
0
Stereo Audio CODEC
with FlexSound Technology
MAX9888
62
Line Inputs
The device includes two sets of line inputs (Figure 7).
Each set can be configured as a stereo single-ended
input or as a mono differential input. Each input includes
adjustable gain to match a wide range of input signal
levels. If a custom gain is needed, the external gain
mode provides a trimmed feedback resistor. Set the gain
by choosing the appropriate input resistor and using the
following formula:
AVPGAIN = 20 x log (20K/RIN)
The external gain mode also allows summing multiple
signals into a single input, by connecting multiple input
resistors as show in Figure 8, and inputting signals larger
than 1VP-P.
Table 3. Microphone Input Registers (continued)
Figure 7. Line Input Block Diagram Figure 8. Summing Multiple Input Signals into INA/INB
REGISTER BIT NAME DESCRIPTION
0x48
7 INABYP
INA_/EXTMIC_ to MIC1_ Bypass Switch
0 = Disabled
1 = Enabled
4 MIC2BYP
MIC1_ to MIC2_ Bypass Switch
0 = Disabled
1 = Enabled
1 RECBYP
See the Output Bypass Switches section.
0 SPKBYP
MIX
MIXOUT1
INADIFF
PGAINA:
+20dB TO -6dB
INABYP
INBDIFF
INA1/
EXTMICP
INA2/
EXTMICN
INB1
INB2
MIX
MIXOUT2
MIX
MIXOUT3
PGAINA:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
LEFT
INPUT 1
LEFT
INPUT 2 INA1/EXTMICP
VCM
INA2/EXTMICN
20kI
RIGHT
INPUT 1
RIGHT
INPUT 2
VCM
20kI
Stereo Audio CODEC
with FlexSound Technology
MAX9888
63
ADC Input Mixers
The device’s stereo ADC accepts input from the micro-
phone amplifiers and line inputs. The ADC mixer routes
any combination of the six audio inputs to the left and
right ADCs (Figure 9).
Table 4. Line Input Registers
Figure 9. ADC Input Mixer Block Diagram
REGISTER BIT NAME DESCRIPTION
0x33/0x34
6 INAEXT/INBEXT
Line Input A/B External Gain
Switches out the internal input resistor and selects a trimmed 20kI feedback resistor.
Use an external input resistor to set the gain of the line input.
0 = Disabled
1 = Enabled
2
PGAINA/PGAINB
Line Input A/B Internal Gain Settings
000 = +20dB
001 = +14dB
010 = +3dB
011 = 0dB
100 = -3dB
101 = -6dB
110 = -6dB
111 = -6dB
1
0
0x45
7 INADIFF
Line Input A Differential Enable
0 = Stereo single-ended input
1 = Mono differential input
6 INBDIFF
Line Input B Differential Enable
0 = Stereo single-ended input
1 = Mono differential input
INBDIFF
PGAINB:
+20dB TO -6dB
+
PGAINB:
+20dB TO -6dB
INADIFF
PGAINA:
+20dB TO -6dB
+
PGAINA:
+20dB TO -6dB
PGAM2:
+20dB TO 0dB
PGAM1:
+20dB TO 0dB
MIXADR
ADREN
ADLEN
MIX
MIXADL
MIX
PA2EN:
0/20/30dB
PA1EN:
0/20/30dB
ADCR
ADCL
Stereo Audio CODEC
with FlexSound Technology
MAX9888
64
Table 5. ADC Input Mixer Register
Figure 10. Record Path Signal Processing Block Diagram Figure 11. AGC and Noise Gate Input vs. Output Gain
Record Path Signal Processing
The device’s record signal path includes both automatic
gain control (AGC) for the microphone inputs and a digi-
tal noise gate at the output of the ADC (Figure 10).
Microphone AGC
The IC’s AGC monitors the signal level at the output of
the ADC and then adjusts the MIC1 and MIC2 analog
PGA settings automatically. When the signal level is
below the predefined threshold, the gain is increased up
to its maximum (20dB). If the signal exceeds the thresh-
old, the gain is reduced to prevent the output signal level
exceeding the threshold. When AGC is enabled, the
microphone PGA is not user programmable. The AGC
provides a more constant signal level and improves the
available ADC dynamic range.
Noise Gate
Since the AGC increases the levels of all signals below
a user-defined threshold, the noise floor is effectively
increased by 20dB. To counteract this, the noise gate
reduces the gain at low signal levels. Unlike typical noise
gates that completely silence the output below a defined
level, the noise gate in the IC applies downward expan-
sion. The noise gate attenuates the output at a rate of
1dB for each 2dB the signal is below the threshold.
The noise gate can be used in conjunction with the AGC
or on its own. When the AGC is enabled, the noise gate
reduces the output level only when the AGC has set the
gain to the maximum setting. Figure 11 shows the gain
response resulting from using the AGC and noise gate.
REGISTER BIT NAME DESCRIPTION
0x22/0x23
7
MIXADL/MIXADR
Left/Right ADC Input Mixer
Selects which analog inputs are recorded by the left/right ADC.
1xxxxxxx = MIC1
x1xxxxxx = MIC2
xx1xxxxx = Reserved
xxx1xxxx = Reserved
xxxx1xxx = INA1
xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1)
xxxxxx1x = INB1
xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
6
5
4
3
2
1
0
PGAM2:
+20dB TO 0dB
PGAM1:
+20dB TO -6dB
MIXADR
ADREN
ADLEN
MIX
MIXADL
MIX
PA2EN:
0/20/30dB
PA1EN:
0/20/30dB
ADCR
ADCL
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
MODE1
AVFLT
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
AUTOMATIC
GAIN
CONTROL
NOISE GATE
AUDIO/
VOICE
FILTERS
AGC AND NOISE GATE
AMPLITUDE RESPONSE
INPUT AMPLITUDE (dBFS)
AGC ONLY
AGC AND NOISE GATE
NOISE GATE ONLY
AGC AND NOISE
GATE DISABLED
OUTPUT AMPLITUDE (dBFS)
-20-40-60-80-100
-120
-100
-80
-60
-40
-20
0
-120 0
Stereo Audio CODEC
with FlexSound Technology
MAX9888
65
Table 6. Record Path Signal Processing Registers
REGISTER BIT NAME DESCRIPTION
0x01
7
NG
Noise Gate Attenuation
Reports the current noise gate attenuation.
000 = 0dB
001 = 1dB
010 = 2dB
011 = 3dB to 5dB
100 = 6dB to 7dB
101 = 8dB to 9dB
110 = 10dB to 11dB
111 = 12dB
6
5
4
AGC
AGC Gain
Reports the current AGC gain setting.
VALUE GAIN (dB) VALUE GAIN (dB)
3
0x00 +20 0x0B +9
0x01 +19 0x0C +8
0x02 +18 0x0D +7
2
0x03 +17 0x0E +6
0x04 +16 0x0F +5
0x05 +15 0x10 +4
1
0x06 +14 0x11 +3
0x07 +13 0x12 +2
0x08 +12 0x13 +1
00x09 +11 0x14 to 0x1F 0
0x0A +10
0x3D
7 AGCSRC
AGC/Noise Gate Signal Source
Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on
both channels regardless of the AGCSRC setting.
0 = Left ADC output
1 = Maximum of either the left or right ADC output
6
AGCRLS
AGC Release Time
Defined as the duration from start to finish of gain increase in the region shown in Figure
12. Release times are longer for low AGC threshold levels.
000 = 78ms
001 = 156ms
010 = 312ms
011 = 625ms
100 = 1.25s
101 = 2.5s
110 = 5s
111 = 10s
5
4
Stereo Audio CODEC
with FlexSound Technology
MAX9888
66
Table 6. Record Path Signal Processing Registers (continued)
REGISTER BIT NAME DESCRIPTION
0x3D
3
AGCATK
AGC Attack Time
Defined as the time required to reduce gain by 63% of the total gain reduction (one time
constant of the exponential response). Attack times are longer for low AGC threshold
levels. See Figure 12 for details.
00 = 2ms
01 = 7.2ms
10 = 31ms
11 = 123ms
2
1
AGCHLD
AGC Hold Time
The delay before the AGC release begins. The hold time counter starts whenever the
signal drops below the AGC threshold and is reset by any signal that exceeds the
threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details.
00 = AGC disabled
01 = 50ms
10 = 100ms
11 = 400ms
0
0x3E
7
ANTH
Noise Gate Threshold
Gain is reduced for signals below the threshold to quiet noise. The thresholds are relative
to the ADC’s full-scale output voltage.
6
VALUE THRESHOLD
(dBFS) VALUE THRESHOLD
(dBFS)
0x0 Noise gate disabled 0x8 -45
0x1 Reserved 0x9 -41
5
0x2 Reserved 0xA -38
0x3 -64 0xB -34
0x4 -62 0xC -30
4
0x5 -58 0xD -27
0x6 -53 0xE -22
0x7 -50 0xF -16
3
AGCTH
AGC Threshold
Gain is reduced when signals exceed the threshold to prevent clipping. The thresholds
are relative to the ADC’s full-scale voltage.
2
VALUE THRESHOLD
(dBFS) VALUE THRESHOLD
(dBFS)
0x0 -3 0x8 -11
0x1 -4 0x9 -12
1
0x2 -5 0xA -13
0x3 -6 0xB -14
0x4 -7 0xC -15
0
0x5 -8 0xD -16
0x6 -9 0xE -17
0x7 -10 0xF -18
Stereo Audio CODEC
with FlexSound Technology
MAX9888
67
ADC Record Level Control
The IC includes separate digital level control for the left
and right ADC outputs (Figure 13). To optimize dynamic
range, use analog gain to adjust the signal level and set
the digital level control to 0dB whenever possible. Digital
level control is primarily used when adjusting the record
level for digital microphones.
Figure 12. AGC Timing
Figure 13. ADC Record Level Control Block Diagram
ATTACK TIME HOLD TIME RELEASE TIME
AUTOMATIC
GAIN CONTROL
NOISE GATE
MODE1
AVFLT1
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
ADREN
ADLEN
AUDIO/
VOICE
FILTERS
ADCR
ADCL
Stereo Audio CODEC
with FlexSound Technology
MAX9888
68
Table 7. ADC Record Level Control Register
Figure 14. Sidetone Block Diagram
Sidetone
Enable sidetone during full-duplex operation to add a
low-level copy of the recorded audio signal to the play-
back audio signal (Figure 14). Sidetone is commonly
used in telephony to allow the speaker to hear himself
speak, providing a more natural user experience. The
IC implements sidetone digitally. Doing so helps prevent
unwanted feedback into the playback signal path and
better matches the playback audio signal.
REGISTER BIT NAME DESCRIPTION
0x2F/0x30
5
AVLG/AVRG
Left/Right ADC Gain
00 = 0dB
01 = 6dB
10 = 12dB
11 = 18dB
4
3
AVL/AVR
Left/Right ADC Level
VALUE GAIN (dB) VALUE GAIN (dB)
20x0 +3 0x8 -5
0x1 +2 0x9 -6
1
0x2 +1 0xA -7
0x3 0 0xB -8
0x4 -1 0xC -9
0
0x5 -2 0xD -10
0x6 -3 0xE -11
0x7 -4 0xF -12
ADREN
ADLEN
ADCR
ADCL
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
MODE1
AVFLT
DSTS
SIDETONE
DVST:
0dB TO -60dB
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
AUTOMATIC
GAIN
CONTROL
EQ1EN EQ2EN
DVEQ1:
0dB TO -15dB
DV1G:
0/6/12/18dB
DV2:
0dB TO -15dB DCB2
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
DVEQ2:
0dB TO -15dB
MULTIBAND ALC
EXCURSION LIMITER
DV1:
0dB TO -15dB MODE1
DVFLT
DALEN
MIXDAR
DACL
DAREN
DACR
+
NOISE GATE
MIX
MIX
MIXDAL
MIX
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
AUDIO/
VOICE
FILTERS
Stereo Audio CODEC
with FlexSound Technology
MAX9888
69
Table 8. Sidetone Register
Digital Audio Interfaces
The IC includes two separate playback signal paths and
one record signal path. Digital audio interface 1 (DAI1)
is used to transmit the recorded stereo audio signal and
receive a stereo audio signal for playback. Digital audio
interface 2 (DAI2) is used to receive a second stereo
audio signal. Use DAI1 for all full-duplex operations and
for all voice signals. Use DAI2 for music and to mix two
playback audio signals. The digital audio interfaces are
separate from the audio ports to enable either interface
to communicate with any external device connected to
the audio ports.
Each audio interface can be configured in a variety of
formats including left justified, I2S, PCM, and time divi-
sion multiplexed (TDM). TDM mode supports up to 4
mono audio slots in each frame. The IC can use up to
2 mono slots per interface, leaving the remaining two
slots available for another device. Table 9 shows how to
configure the device for common digital audio formats.
Figures 16 and 17 show examples of common audio
formats. By default, SDOUTS1 and SDOUTS2 are set
high impedance when the IC is not outputting data to
facilitate sharing the bus. Configure the interface in TDM
mode using only slot 1 to transmit and receive mono
PCM voice data.
The IC’s digital audio interfaces support both ADC to
DAC loop-through and digital loopback. Loop-through
allows the signal converted by the ADC to be routed
to the DAC for playback. The signal is routed from the
record path to the playback path in the digital audio
interface to allow the IC’s full complement of digital
signal processing to be used. Loopback allows digital
REGISTER BIT NAME DESCRIPTION
0x2A
7
DSTS
Sidetone Source
Selects which ADC output is fed back as sidetone. When mixing the left and right ADC
outputs, each is attenuated by 6dB to prevent full-scale signals from clipping.
00 = Sidetone disabled
01 = Left ADC
10 = Right ADC
11 = Left + Right ADC
6
4
DVST
Sidetone Level
Adjusts the sidetone signal level. All levels are referenced to the ADC’s full-scale output.
VALUE LEVEL (dB) VALUE LEVEL (dB)
3
0x00 Sidetone disabled 0x10 -30.5
0x01 -0.5 0x11 -32.5
0x02 -2.5 0x12 -34.5
0x03 -4.5 0x13 -36.5
2
0x04 -6.5 0x14 -38.5
0x05 -8.5 0x15 -40.5
0x06 -10.5 0x16 -42.5
0x07 -12.5 0x17 -44.5
1
0x08 -14.5 0x18 -46.5
0x09 -16.5 0x19 -48.5
0x0A -18.5 0x1A -50.5
0x0B -20.5 0x1B -52.5
0
0x0C -22.5 0x1C -54.5
0x0D -24.5 0x1D -56.6
0x0E -26.5 0x1E -58.5
0x0F -28.5 0x1F -60.5
Stereo Audio CODEC
with FlexSound Technology
MAX9888
70
Figure 15. Digital Audio Signal Routing
Table 9. Common Digital Audio Formats
X = Don’t care.
data input to either SDINS1 or SDINS2 to be routed
from one interface to the other for output on SDOUTS2
or SDOUTS1. Both interfaces must be configured for
the same sample rate, but the interface format need
not be the same. This allows the IC to route audio data
from one device to another, converting the data format
as needed. Figure 15 shows the available digital signal
routing options.
MODE WCI1/WCI2 BCI1/BCI2 DLY1/DLY2 TDM1/TDM2 SLOTL1/SLOTL2 SLOTR1/SLOTR2
Left Justified Set as desired Set as desired 0 0 X X
I2S 1 0 1 0 X X
PCM X 1 X 1 0 0
TDM X 1 X 1 Set as desired
MAS1
DAI1
DAI1
RECORD PATH
DAI1
PLAYBACK PATH
DAI2
PLAYBACK PATH
SEL1 SEL2
BCLK1
BCLKS1
LRCLK1
SDOUT1
SDIN1
LTEN1
LBEN2 +
BIT
CLOCK
FRAME
CLOCK
DATA
OUTPUT
DATA
INPUT
MAS1 HIZOFF1 MAS2
DAI2
BCLK2
LRCLK2
SDOUT2
SDIN2
BIT
CLOCK
FRAME
CLOCK
DATA
OUTPUT
DATA
INPUT
MAS2 HIZOFF2
LRCLKS1 SDOUTS1 SDINS1 DVDDS1 BCLKS2 LRCLKS2 SDOUTS2 SDINS2 DVDDS2
MUX
LBEN1
PORT S1 PORT S1
Stereo Audio CODEC
with FlexSound Technology
MAX9888
71
Table 10. Digital Audio Interface Registers
REGISTER BIT NAME DESCRIPTION
0x14/0x1C
7 MAS1/MAS2
DAI1/DAI2 Master Mode
In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2
accept LRCLK and BCLK as inputs.
0 = Slave mode
1 = Master mode
6 WCI1/WCI2
DAI1/DAI2 Word Clock Invert
TDM1/TDM2 = 0:
0 = Left-channel data is transmitted while LRCLK is low.
1 = Right-channel data is transmitted while LRCLK is low.
TDM1/TDM2 = 1:
Always set WCI = 0.
5 BCI1/BCI2
DAI1/DAI2 Bit Clock Invert
BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1.
0 = SDIN is accepted on the rising edge of BCLK.
SDOUT is valid on the rising edge of BCLK.
1 = SDIN is accepted on the falling edge of BCLK.
SDOUT is valid on the falling edge of BCLK.
Master Mode:
0 = LRCLK transitions on the falling edge of BCLK.
1 = LRCLK transitions on the rising edge of BCLK.
4 DLY1/DLY2
DAI1/DAI2 Data Delay
DLY1/DLY2 has no effect when TDM1/TDM2 = 1.
0 = The most significant data bit is clocked on the first active BCLK edge after an
LRCLK transition.
1 = The most significant data bit is clocked on the second active BCLK edge after an
LRCLK transition.
2 TDM1/TDM2
DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode)
Set TDM1/TDM2 when communicating with devices that use a frame synchronization
pulse on LRCLK instead of a square wave.
0 = Disabled
1 = Enabled (BCI1/BCI2 must be set to 1)
1 FSW1/FSW2
DAI1/DAI2 Wide Frame Sync Pulse
Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 =
1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0.
0 = Disabled
1 = Enabled
0 WS1/WS2
DAI1/DAI2 Audio Data Bit Depth
Determines the maximum bit depth of audio being transmitted and received. Data is
always 16 bit when TDM1/TMD2 = 0.
0 = 16 bits
1 = 24 bits
Stereo Audio CODEC
with FlexSound Technology
MAX9888
72
Table 10. Digital Audio Interface Registers (continued)
REGISTER BIT NAME DESCRIPTION
0x15/0x1D
7
OSR1
ADC Oversampling Ratio
Use the higher setting for maximum performance. Use the lower setting for reduced
power consumption at the expense of performance.
00 = 96x
01 = 64x
10 = Reserved
11 = Reserved
6
2
BSEL1/
BSEL2
DAI1/DAI2 BCLK Output Frequency
When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When
operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK
frequency that clocks all data input to the DAC and output by the ADC.
000 = BCLK disabled
001 = 64 x LRCLK
010 = 48 x LRCLK
011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1)
100 = PCLK/2
101 = PCLK/4
110 = PCLK/8
111 = PCLK/16
1
0
0x16/0x1E
7
SEL1/SEL2
DAI1/DAI2 Audio Port Selector
Selects which port is used by DAI1/DAI2.
00 = None
01 = Port S1
10 = Port S2
11 = Reserved
6
5 LTEN1
DAI1 Digital Loopthrough
Connects the output of the record signal path to the input of the playback path. Data
input to DAI1 from an external device is mixed with the recorded audio signal.
0 = Disabled
1 = Enabled
4LBEN1/
LBEN2
DAI1/DAI2 Digital Audio Interface Loopback
LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the
digital audio input to DAI2 back out on DAI1. Selecting LBEN2 disables the ADC
output data.
0 = Disabled
1 = Enabled
3DMONO1/
DMONO2
DAI1/DAI2 DAC Mono Mix
Mixes the left and right digital input to mono and routes the combined signal to the left
and right playback paths. The left and right input data is attenuated by 6dB prior to the
mono mix.
0 = Disabled
1 = Enabled
Stereo Audio CODEC
with FlexSound Technology
MAX9888
73
Table 10. Digital Audio Interface Registers (continued)
REGISTER BIT NAME DESCRIPTION
0x16/0x1E
2HIZOFF1/
HIZOFF2
Disable DA1/DAI2 Output High-Impedance Mode
Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to
force a level on SDOUT at all times.
0 = Disabled
1 = Enabled
1SDOEN1/
SDOEN2
DAI1/DAI2 Record Path Output Enable
DAI2 outputs data only if LBEN1 = 1.
0 = Disabled
1 = Enabled
0SDIEN1/
SDIEN2
DAI1/DAI2 Playback Path Input Enable
0 = Disabled
1 = Enabled
0x17/0x1F
7
SLOTL1/
SLOTL2
TDM Left Time Slot
Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
11 = Slot 4
6
5
SLOTR1/
SLOTR2
TDM Right Time Slot
Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
11 = Slot 4
4
3
SLOTDLY1/
SLOTDLY2
TDM Slot Delay
Adds 1 BCLK cycle delay to the data in the specified TDM slot.
1xxx = Slot 4 delayed
x1xx = Slot 3 delayed
xx1x = Slot 2 delayed
xxx1 = Slot 1 delayed
2
1
0
Stereo Audio CODEC
with FlexSound Technology
MAX9888
74
Figure 16. Non-TDM Data Format Examples
WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LRCLK LEFT
LEFT
LEFT
BCLK
SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT
RIGHT
RIGHT
SDIN
WCI_ = 1, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LRCLK
BCLK
SDOUT
SDIN
LRCLK
BCLK
SDOUT
SDIN
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
WCI_ = 0, BCI_ = 0, DLY_ = 1, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LRCLK
BCLK
SDOUT
RIGHT
LEFT
SDIN
Stereo Audio CODEC
with FlexSound Technology
MAX9888
75
Figure 17. TDM Mode Data Format Examples
LRCLK
BCLK
SDOUT
SDIN L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z
HI-Z
LRCLK
BCLK
SDOUT
SDIN
LRCLK
BCLK
SDOUT
SDIN
LRCLK
BCLK
SDOUT
SDIN
LRCLK
BCLK
SDOUT
SDIN L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 1, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 1
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 2, SLOTR_ = 3
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
32 CYCLES
L L L L L L L L R R R R R R R R
HI-Z
L L L L L L L L 1 1 1 1 R R R R
HI-Z
HI-Z
16 CYCLES 16 CYCLES 16 CYCLES 16 CYCLES
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
Stereo Audio CODEC
with FlexSound Technology
MAX9888
76
Table 11. Clock Control Registers
Clock Control
The digital signal paths in the IC require a master
clock (MCLK) between 10MHz and 60MHz to func-
tion. Internally, the MAX9888 requires a clock between
10MHz and 20MHz. A prescaler divides MCLK by 1, 2,
or 4 to create the internal clock (PCLK). PCLK is used to
clock all portions of the IC.
The MAX9888 includes two digital audio signal paths,
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, three main clocking modes are
supported:
U PLL Mode: When operating in slave mode, enable
the PLL to lock onto any LRCLK input. This mode
requires the least configuration, but provides the
lowest performance. Use this mode to simplify initial
setup or when normal mode and exact integer mode
cannot be used.
U Normal Mode: This mode uses a 15-bit clock divider
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequen-
cies and can be used in either master or slave mode.
U Exact Integer Mode (DAI1 only): In both master and
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
REGISTER BIT NAME DESCRIPTION
0x10
5
PSCLK
MCLK Prescaler
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz P MCLK P 20MHz (PCLK = MCLK)
10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2)
11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4)
4
0x11/0x19
7
SR1/SR2
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
6VALUE SAMPLE RATE
(kHz) VALUE SAMPLE RATE
(kHz)
0x0 Reserved 0x8 48
5
0x1 8 0x9 88.2
0x2 11.025 0xA 96
0x3 16 0xB Reserved
0x4 22.05 0xC Reserved
4
0x5 24 0xD Reserved
0x6 32 0xE Reserved
0x7 44.1 0xF Reserved
Stereo Audio CODEC
with FlexSound Technology
MAX9888
77
Table 11. Clock Control Registers (continued)
REGISTER BIT NAME DESCRIPTION
0x11
3
FREQ1
Exact Integer Mode
Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio.
VALUE SAMPLE RATE VALUE SAMPLE RATE
0x0 Disabled 0x8 PCLK = 12MHz,
LRCLK = 8kHz
2
0x1 Reserved 0x9 PCLK = 12MHz,
LRCLK = 16kHz
0x2 Reserved 0xA PCLK = 13MHz,
LRCLK = 8kHz
0x3 Reserved 0xB PCLK = 13MHz,
LRCLK = 16kHz
0x4 Reserved 0xC PCLK = 16MHz,
LRCLK = 8kHz
1
0x5 Reserved 0xD PCLK = 16MHz,
LRCLK = 16kHz
0x6 Reserved 0xE PCLK = 19.2MHz,
LRCLK = 8kHz
0x7 Reserved 0xF PCLK = 19.2MHz,
LRCLK = 16kHz
0x12/0x1A
7 PLL1/PLL2
PLL Mode Enable (Slave Mode Only)
PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK
frequency and automatically sets the LRCLK divider (NI1/NI2).
0 = Disabled
1 = Enabled
6
NI1/
NI2
Normal Mode LRCLK Divider
When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12
for common NI values.
5
4
3SAMPLE RATE DHF1/DHF2 NI1/NI2 FORMULA
2
18kHz P LRCLK P 48kHz 0
0
0x13/0x1B
7
48kHz < LRCLK P 96kHz 1
6
5
4
3fLRCLK = LRCLK frequency
fPCLK = Prescaled MCLK frequency (PCLK)
2
1
0 NI1[0]/NI2[0]
Rapid Lock Mode
Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1
to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically
adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is
much closer to the correct value, thus speeding up lock time. Wait one LRCLK period
after programming NI1/NI2 before setting PLL1/PLL2 = 1.
LRCLK
PCLK
65536 96 f
NI f
× ×
=
LRCLK
PCLK
65536 48 f
NI f
× ×
=
Stereo Audio CODEC
with FlexSound Technology
MAX9888
78
Table 12. Common NI1/NI2 Values
Note: Values in bold are exact integers that provide maximum full-scale performance.
Figure 18. Digital Passband Filtering Block Diagram
Passband Filtering
Each digital signal path in the IC includes options for
defining the path bandwidth (Figure 18). The playback
and record paths connected to DAI1 support both voice
and music filtering while the playback path connected to
DAI2 supports music filtering only.
The voice IIR filters provide greater than 70dB stopband
attenuation at frequencies above fS/2 to reduce aliasing.
Three selectable highpass filters eliminate unwanted
low-frequency signals.
Use music mode when processing high-fidelity audio
content. The music FIR filters reduce power consump-
tion and are linear phase to maintain stereo imaging.
An optional DC-blocking filter is available to eliminate
unwanted DC offset.
In music mode, a second set of FIR filters are available
to support sample rates greater than 50kHz. The filters
can be independently selected for DAI1 and DAI2 and
support both the playback and record audio paths.
PCLK (MHz)
LRCLK (kHz)
DHF1/2 = 0 DHF1/2 = 1
8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96
10 13A9 1B18 1D7E 2752 3631 3AFB 4EA5 6C61 75F7 4EA5 6C61 75F7
11 11E0 18A2 1ACF 23BF 3144 359F 477E 6287 6B3E 477E 6287 6B3E
11.2896 116A 1800 1A1F 22D4 3000 343F 45A9 6000 687D 45A9 6000 687D
12 1062 1694 1893 20C5 2D29 3127 4189 5A51 624E 4189 5A51 624E
12.288 1000 160D 1800 2000 2C1A 3000 4000 5833 6000 4000 5833 6000
13 0F20 14D8 16AF 1E3F 29AF 2D5F 3C7F 535F 5ABE 3C7F 535F 5ABE
16 0C4A 10EF 126F 1893 21DE 24DD 3127 43BD 49BA 3127 43BD 49BA
16.9344 0B9C 1000 116A 1738 2000 22D4 2E71 4000 45A9 2E71 4000 45A9
18.432 0AAB 0EB3 1000 1555 1D66 2000 2AAB 3ACD 4000 2AAB 3ACD 4000
20 09D5 0D8C 0EBF 13A9 1B18 1D7E 2752 3631 3AFB 2752 3631 3AFB
ADREN
ADLEN
ADCR
ADCL
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
MODE1
AVFLT
DSTS
SIDETONE
DVST:
0dB TO -60dB
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
EQ1EN EQ2EN
DVEQ1:
0dB TO -15dB
DV1G:
0/6/12/18dB
DV2:
0dB TO -15dB DCB2
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
DVEQ2:
0dB TO -15dB
MULTIBAND ALC
EXCURSION LIMITER
DV1:
0dB TO -15dB MODE1
DVFLT
DALEN
MIXDAR
DACL
DAREN
DACR
+
MIX
MIX
MIXDAL
MIX
AUTOMATIC
GAIN
CONTROL
NOISE GATE
AUDIO/
VOICE
FILTERS
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
Stereo Audio CODEC
with FlexSound Technology
MAX9888
79
Table 13. Passband Filtering Registers
REGISTER BIT NAME DESCRIPTION
0x18
7 MODE1
DAI1 Passband Filtering Mode
0 = Voice filters
1 = Music filters (recommended for fS > 24kHz)
6
AVFLT1
DAI1 ADC Highpass Filter Mode
5MODE1 AVFLT1
40 See Table 14
1 Select a nonzero value to enable the DC-blocking filter
3 DHF1
DAI1 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz P LRCLK < 96kHz
2
DVFLT1
DAI1 DAC Highpass Filter Mode
1MODE1 DVFLT1
00 See Table 14
1 Select a nonzero value to enable the DC-blocking filter
0x20
3 DHF2
DAI2 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz < LRCLK P 96kHz
0 DCB2
DAI2 DC Blocking Filter
Enables a DC-blocking filter on the DAI2 playback audio path.
0 = Disabled
1 = Enabled
Stereo Audio CODEC
with FlexSound Technology
MAX9888
80
Table 14. Voice Highpass Filters
AVFTL/DVFLT VALUE INTENDED SAMPLE RATE FILTER RESPONSE
000 N/A Disabled
001/011 16kHz/8kHz
010/100 16kHz/8kHz
101 8kHz to 48kHz
110/111 N/A Reserved
FREQUENCY (Hz)
AMPLITUDE (dB)
800600400200
-50
-40
-30
-20
-10
0
-60
0 1000
FREQUENCY (Hz)
AMPLITUDE (dB)
800600400200
-50
-40
-30
-20
-10
0
-60
0 1000
FREQUENCY (Hz)
AMPLITUDE (dB)
800600400200
-50
-40
-30
-20
-10
0
-60
0 1000
LRCLK = 48kHz
Stereo Audio CODEC
with FlexSound Technology
MAX9888
81
Figure 20. ALC Input vs. Output ExamplesFigure 19. Playback Path Signal Processing Block Diagram
Playback Path Signal Processing
The IC playback signal path includes automatic level
control (ALC) and a 5-band parametric equalizer (EQ)
(Figure 19). The DAI1 and DAI2 playback paths include
separate ALCs controlled by a single set of registers.
Two completely separate parametric EQs are included
for the DAI1 and DAI2 playback paths.
Automatic Level Control
The automatic level control (ALC) circuit ensures maxi-
mum signal amplitude without producing audible clip-
ping. This is accomplished by a variable gain stage that
works on a sample by sample basis to increase the gain
up to 12dB. A look-ahead circuit determines if the next
sample exceeds full scale and reduces the gain so that
the sample is exactly full scale.
A programmable low signal threshold determines the
minimum signal amplitude that is amplified. Select a
threshold that prevents the amplification of background
noise. When the signal level drops below the low signal
threshold, the ALC reduces the gain to 0dB until the sig-
nal increases above the threshold. Figure 20 shows an
example of ALC input vs. output curves.
The ALC can optionally be configured in dual-band
mode. In this mode, the input signal is filtered into two
bands with a 5kHz center frequency. Each band is
routed through independent ALCs and then summed
together. In multiband mode, both bands use the same
parameters.
0
OUTPUT SIGNAL
(dBFS)
OUTPUT SIGNAL
(dBFS)
OUTPUT SIGNAL
(dBFS)
INPUT
SIGNAL
(dBFS)
INPUT
SIGNAL
(dBFS)
INPUT
SIGNAL
(dBFS)
LOW-LEVEL
THRESHOLD
-12 0
LOW-LEVEL
THRESHOLD
-12 0
LOW-LEVEL
THRESHOLD
-12 0
0
0
ALC WITH ALCTH 000
ALC WITH ALCTH = 000
ALC DISABLED
EQ1EN EQ2EN
DVEQ1:
0dB TO -15dB
DV1G:
0/6/12/18dB
DV2:
0dB TO -15dB DCB2
DVEQ2:
0dB TO -15dB
MULTIBAND ALC
EXCURSION LIMITER
DV1:
0dB TO -15dB MODE1
DVFLT
DALEN
MIXDAR
DACL
DAREN
DACR
+
MIX
MIXDAL
MIX
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
Stereo Audio CODEC
with FlexSound Technology
MAX9888
82
Table 15. Automatic Level Control Registers
Parametric Equalizer
The parametric EQ contains five independent biquad
filters with programmable gain, center frequency, and
bandwidth. Each biquad filter has a gain range of Q12dB
and a center frequency range from 20Hz to 20kHz. Use a
filter Q less than that shown in Figure 21 to achieve ideal
frequency responses. Setting a higher Q results in non-
ideal frequency response. The biquad filters are series
connected, allowing a total gain of Q60dB.
Figure 21. Maximum Recommended Filter Q vs. Frequency
REGISTER BIT NAME DESCRIPTION
0x41
7 ALCEN
ALC Enable
Enables ALC on both the DAI1 and DAI2 playback paths.
0 = Disabled
1 = Enabled
6
ALCRLS
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Excursion
Limiter section for Excursion Limiter release times. ALC release time is defined as the
time required to adjust the gain from 12dB to 0dB.
VALUE ALC RELEASE TIME (s)
5
000 8
001 4
010 2
011 1
4
100 0.5
101 0.25
110 Reserved
111 Reserved
3 ALCMB
Multiband Enable
Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be
configured properly to achieve the correct center frequency for each playback path.
0 = Single-band ALC
1 = Dual-band ALC
2
ALCTH
Low Signal Threshold
Selects the minimum signal level to be boosted by the ALC.
000 = -JdB (low-signal threshold disabled)
001 = -12dB
010 = -18dB
011 = -24dB
100 = -30dB
101 = -36dB
110 = -42dB
111 = -48dB
1
0
CENTER FREQUENCY (Hz)
MAXIMUM RECOMMENDED FILTER Q
10,0001000
1
10
100
1000
0.1
100 100,000
fs = 8kHz
fs = 48kHz
fs = 96kHz
Stereo Audio CODEC
with FlexSound Technology
MAX9888
83
Table 16. EQ Registers
Use the attenuator at the EQ’s input to avoid clipping
the signal. The attenuator can be programmed for fixed
attenuation or dynamic attenuation based on signal level.
If the dynamic EQ clip detection is enabled, the signal
level from the EQ is fed back to the attenuator circuit to
determine the amount of gain reduction necessary to
avoid clipping.
The MAX9888 EV kit software includes a graphic inter-
face for generating the EQ coefficients. The coefficients
are sample rate dependent and stored in registers 0x50
through 0xB3.
REGISTER BIT NAME DESCRIPTION
0x2C/0x2E
4EQCLP1/
EQCLP2
DAI1/DAI2 EQ Clip Detection
Automatically controls the EQ attenuator to prevent clipping in the EQ.
0 = Enabled
1 = Disabled
3
DVEQ1/DVEQ2
DAI1/DAI2 EQ Attenuator
Provides attenuation to prevent clipping in the EQ when full-scale signals are boost-
ed. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2
= 1.
2
VALUE GAIN (dB) VALUE GAIN (dB)
0x0 0 0x8 -8
0x1 -1 0x9 -9
1
0x2 -2 0xA -10
0x3 -3 0xB -11
0x4 -4 0xC -12
0
0x5 -5 0xD -13
0x6 -6 0xE -14
0x7 -7 0xF -15
0x47
7VS2EN
See the Click-and-Pop Reduction section.
6VSEN
5ZDEN
1 EQ2EN
DAI2 EQ Enable
0 = Disabled
1 = Enabled
0 EQ1EN
DAI1 EQ Enable
0 = Disabled
1 = Enabled
Stereo Audio CODEC
with FlexSound Technology
MAX9888
84
Figure 22. Playback Level Control Block Diagram
Table 17. DAC Playback Level Control Register
Playback Level Control
The IC includes separate digital level control for the DAI1
and DAI2 playback audio paths. The DAI1 signal path
allows boost when MODE1 = 0 and attenuation in any
mode. The DAI2 signal path allows attenuation only.
REGISTER BIT NAME DESCRIPTION
0x2B/0x2D
7 DV1M/DV2M
DAI1/DAI2 Mute
0 = Disabled
1 = Enabled
5
DV1G
DAI1 Voice Mode Gain
DV1G only applies when MODE1 = 0.
00 = 0dB
01 = 6dB
10 = 12dB
11 = 18dB
4
3
DV1/DV2
DAI1/DAI2 Attenuation
VALUE GAIN (dB) VALUE GAIN (dB)
2
0x0 0 0x8 -8
0x1 -1 0x9 -9
0x2 -2 0xA -10
1
0x3 -3 0xB -11
0x4 -4 0xC -12
0x5 -5 0xD -13
00x6 -6 0xE -14
0x7 -7 0xF -15
EQ1EN EQ2EN
DVEQ1:
0dB TO -15dB
DV1G:
0/6/12/18dB
DV2:
0dB TO -15dB DCB2
DVEQ2:
0dB TO -15dB
MULTIBAND ALC
EXCURSION LIMITER
DV1:
0dB TO -15dB MODE1
DVFLT
DALEN
MIXDAR
DACL
DAREN
DACR
+
MIX
MIXDAL
MIX
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
Stereo Audio CODEC
with FlexSound Technology
MAX9888
85
Table 18. DAC Input Mixer Register
Figure 23. DAC Input Mixer Block Diagram
DAC Input Mixers
The IC’s stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and
right DACs (Figure 23).
REGISTER BIT NAME DESCRIPTION
0x21
7
MIXDAL
Left DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
6
5
4
3
MIXDAR
Right DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
2
1
0
EQ1EN EQ2EN
DVEQ1:
0dB TO -15dB
DV1G:
0/6/12/18dB
DV2:
0dB TO -15dB DCB2
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
DVEQ2:
0dB TO -15dB
MULTIBAND ALC
EXCURSION LIMITER
DV1:
0dB TO -15dB MODE1
DVFLT
DALEN
MIXDAR
DACL
DAREN
DACR
+
MIX
MIXDAL
MIX
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
Stereo Audio CODEC
with FlexSound Technology
MAX9888
86
Figure 24. Preoutput Signal Path Block Diagram
Table 19. Preoutput Mixer Registers
Preoutput Signal Path
The IC’s preoutput mixer stage provides mixing and level adjustment for line input signals routed to the output ampli-
fiers. Figure 24 shows a block diagram of the preoutput signal path. 9dB is added between the line input amplifiers
and the output amplifiers to boost the 1VP-P maximum line input signal level to the 1VRMS maximum DAC signal level.
Preoutput Mixer
The IC’s output amplifiers each accept input from one of the three preoutput mixers. Configure each pre-
output mixer to mix any combination of the four line input signals.
REGISTER BIT NAME DESCRIPTION
0x24/0x25/
0x26
3
MIXOUT1/
MIXOUT2/
MIXOUT3
Preoutput Mixer 1
1xxx = INA1
x1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1)
xx1x = INB1
xxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
2
1
0
INBDIFF
MIXOUT3
MIXOUT2
PGAINB:
+20dB TO -6dB
+
MIX
MIX
PGAINB:
+20dB TO -6dB
INADIFF
PGAINA:
+20dB TO -6dB
PGAOUT1:
0dB TO -23dB
PGAOUT2:
0dB TO -23dB
PGAOUT3:
0dB TO -23dB
+
PGAINA:
+20dB TO -6dB
MIXOUT1
PREOUT1
MIX
PREOUT2
PREOUT3
+9dB
+9dB
+9dB
MIXREC
0dB
RECVOL:
+8dB TO -62dB
RECP/
RXINP
RECN/
RXINN
SPKLP
SPKLN
RECBYP
SPKBYP
RECEN
MIXSPL
+6dB
SPVOLL:
+8dB TO -62dB
SPKLVDD
SPKRP
SPKRN
SPLEN
SPREN
POWER/
DISTORTION LIMITER
MIXSPR
+6dB
SPVOLR:
+8dB TO -62dB HPVOLL:
+3dB TO -67dB
SPKLGND
SPKRVDD
SPKRPGND
HPL
HPSNS
HPR
HPLEN
MIXHPL
HPVOLR:
+3dB TO -67dB
HPREN
MIXHPR
MIX
MIX
MIX
MIX
MIX
BATTERY ADC
Stereo Audio CODEC
with FlexSound Technology
MAX9888
87
Table 20. Preoutput PGA Registers
Figure 25. Receiver Amplifier Block Diagram
Preoutput PGA
The IC’s preoutput PGAs allow line input signals to be attenuated to match DAC output signal levels. Use the 0dB
setting for maximum performance.
Receiver Amplifier
The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive 32I receivers. In
cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route the receiver
amplifier output to the left speaker outputs.
REGISTER BIT NAME DESCRIPTION
0x35/0x36/
0x37
3
PGAOUT1/
PGAOUT2/
PGAOUT3
Preoutput PGA Level
VALUE GAIN (dB) VALUE GAIN (dB)
20x0 0 0x8 -15
0x1 -1 0x9 -17
1
0x2 -3 0xA -19
0x3 -5 0xB -21
0x4 -7 0xC -23
0
0x5 -9 0xD Mute
0x6 -11 0xE Mute
0x7 -13 0xF Mute
PGAOUT1:
0dB TO -23dB
PGAOUT2:
0dB TO -23dB
PREOUT1
PREOUT2
+9dB
+9dB
DALEN
DACL
DAREN
DACR
MIXREC
0dB
RECVOL:
+8dB TO -62dB
RECP/
RXINP
RECN/
RXINN
RECBYP
SPKBYP
RECEN
MIX
Stereo Audio CODEC
with FlexSound Technology
MAX9888
88
Table 21. Receiver Output Mixer Register
Table 22. Receiver Output Level Register
Receiver Output Mixer
The IC’s receiver amplifier accepts input from the stereo DAC and the line inputs. Configure the mixer to mix any combina-
tion of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals,
9.5dB for 3 signals, or 12dB for 4 signals.
Receiver Output Volume
REGISTER BIT NAME DESCRIPTION
0x28
3
MIXREC
Receiver Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Preoutput mixer 1
xxx1 = Preoutput mixer 2
2
1
0
REGISTER BIT NAME DESCRIPTION
0x3A
7 RECM
Receiver Output Mute
0 = Disabled
1 = Enabled
4
RECVOL
Receiver Output Volume Level
VALUE VOLUME (dB) VALUE VOLUME (dB)
3
0x00 -62 0x10 -10
0x01 -58 0x11 -8
0x02 -54 0x12 -6
0x03 -50 0x13 -4
2
0x04 -46 0x14 -2
0x05 -42 0x15 0
0x06 -38 0x16 +1
0x07 -35 0x17 +2
1
0x08 -32 0x18 +3
0x09 -29 0x19 +4
0x0A -26 0x1A +5
0x0B -23 0x1B +6
0
0x0C -20 0x1C +6.5
0x0D -17 0x1D +7
0x0E -14 0x1E +7.5
0x0F -12 0x1F +8
Stereo Audio CODEC
with FlexSound Technology
MAX9888
89
Speaker Amplifiers
The IC integrates a stereo filterless Class D amplifier that
offers much higher efficiency than Class AB without the
typical disadvantages.
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current
steering switches and consume negligible additional
power. Any power loss associated with the Class D out-
put stage is mostly due to the I2R loss of the MOSFET
on-resistance, and quiescent current overhead.
The theoretical best efficiency of a linear amplifier is
78%, however, that efficiency is only exhibited at peak
output power. Under normal operating levels (typical
music reproduction levels), efficiency falls below 30%,
whereas the IC’s Class D amplifier still exhibits 80% effi-
ciency under the same conditions.
Traditional Class D amplifiers require the use of exter-
nal LC filters or shielding to meet EN55022B and FCC
electromagnetic-interference (EMI) regulation standards.
Maxim’s patented active emissions limiting edge-rate
control circuitry reduces EMI emissions (Figure 26).
Figure 26. EMI with 15cm of Speaker Cable
Figure 27. Speaker Amplifier Path Block Diagram
300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
30 60 80 100 120 140 160 180 200 220 240 260 280 300
40
30
20
10
-10
0
40
30
20
10
-10
0
FREQUENCY (MHz)
AMPLITUDE (dBµV/m)
FREQUENCY (MHz)
AMPLITUDE (dBµV/m)
PGAOUT2:
0dB TO -23dB
PGAOUT3:
0dB TO -23dB
PREOUT2
PREOUT3
+9dB
+9dB
DALEN
DACL
DAREN
DACR
SPKLP
SPKLN
MIXSPL
+6dB
SPVOLL:
+8dB TO -62dB
SPKLVDD
SPKLGND
SPKRVDD
SPKRP
SPKRN
SPLEN
SPREN
POWER/DISTORTION LIMITER
MIXSPR
+6dB
SPVOLR:
+8dB TO -62dB SPKRPGND
MIX
MIX
BATTERY ADC
Stereo Audio CODEC
with FlexSound Technology
MAX9888
90
Table 23. Speaker Output Mixer Register
Table 24. Speaker Output Mixer Register
Speaker Output Mixers
The IC’s speaker amplifiers accept input from the stereo DAC and the line inputs. Configure the mixer to mix any combina-
tion of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals,
9.5dB for 3 signals, or 12dB for four signals.
Speaker Output Volume
REGISTER BIT NAME DESCRIPTION
0x29
7
MIXSPL
Left Speaker Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 3
6
5
4
3
MIXSPR
Right Speaker Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 2
2
1
0
REGISTER BIT NAME DESCRIPTION
0x3B/0x3C
7 SPLM/SPRM
Left/Right Speaker Output Mute
0 = Disabled
1 = Enabled
4
SPVOLL/SPVOLR
Left/Right Speaker Output Volume Level
VALUE VOLUME (dB) VALUE VOLUME (dB)
0x00 -64 0x10 -10
0x01 -59 0x11 -8
3
0x02 -55 0x12 -6
0x03 -50 0x13 -4
0x04 -46 0x14 -2
2
0x05 -42 0x15 0
0x06 -38 0x16 +1
0x07 -35 0x17 +2
1
0x08 -32 0x18 +3
0x09 -29 0x19 +4
0x0A -26 0x1A +5
0x0B -23 0x1B +6
0
0x0C -20 0x1C +6.5
0x0D -17 0x1D +7
0x0E -14 0x1E +7.5
0x0F -12 0x1F +8
Stereo Audio CODEC
with FlexSound Technology
MAX9888
91
Figure 28. Speaker Amplifier Signal Processing Block Diagram
Speaker Amplifier Signal Processing
The IC includes signal processing to improve the sound
quality of the speaker output and protect transducers
from damage. An excursion limiter dynamically adjusts
the highpass corner frequency, while a power limiter and
distortion limiter prevent the amplifier from outputting too
much distortion or power. The excursion limiter is located
in the DSP while the distortion limiter and power limiter
control the analog volume control (Figure 28). All three
limiters analyze the speaker amplifier’s output signal to
determine when to take action.
Excursion Limiter
The excursion limiter is a dynamic highpass filter that
monitors the speaker outputs and increases the high-
pass corner frequency when the speaker amplifier’s out-
put exceeds a predefined threshold. The filter smoothly
transitions between the high and low corner frequency to
prevent unwanted artifacts. The filter can operate in four
different modes:
U Fixed Frequency Preset Mode. The highpass corner
frequency is fixed at the upper corner frequency and
does not change with signal level.
U Fixed Frequency Programmable Mode. The high-
pass corner frequency is fixed to that specified by the
programmable biquad filter.
U Preset Dynamic Mode. The highpass filter automati-
cally slides between a preset upper and lower corner
frequency based on output signal level.
U User Programmable Dynamic Mode. The highpass
filter slides between a user-programmed biquad filter
on the low side to a predefined corner frequency on
the high side.
The transfer function for the user-programmable biquad is:
-1 -2
0 1 2
-1 -2
1 2
b b z b z
H(z)
1 a z a z
+ +
=
+ +
The coefficients b0, b1, b2, a1, and a2 are sample rate
dependent and stored in registers 0xB4 through 0xC7.
Store b0, b1, and b2 as positive numbers. Store a1 and
a2 as negated two’s complement numbers. Separate fil-
ters can be stored for the DAI1 and DAI2 playback paths.
The MAX9888 EV kit software includes a graphic interface
for generating the user-programmable biquad coefficients.
Note: Only change the excursion limiter settings when
the signal path is disabled to prevent undesired artifacts.
DALEN
DACL
DAREN
DACR
SPKLP
SPKLN
MIXSPL
+6dB
SPVOLL:
+8dB TO -62dB
SPKLVDD
SPKLGND
SPKRVDD
SPKRP
SPKRN
SPLEN
SPREN
POWER/
DISTORTION LIMITER
MIXSPR
+6dB
SPVOLR:
+8dB TO -62dB SPKRPGND
MIX
MIX
EQ1EN EQ2EN
DVEQ1:
0dB TO -15dB
DV1G:
0/6/12/18dB
DV2:
0dB TO -15dB DCB2
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
DVEQ2:
0dB TO -15dB
MULTIBAND ALC
EXCURSION LIMITER
DV1:
0dB TO -15dB MODE1
DVFLT
MIXDAR
+
MIX
MIXDAL
MIX
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
BATTERY ADC
Stereo Audio CODEC
with FlexSound Technology
MAX9888
92
Table 25. Excursion Limiter Registers
REGISTER BIT NAME DESCRIPTION
0x3F
6
DHPUCF
Excursion Limiter Corner Frequency
The excursion limiter has limited sliding range and minimum corner frequencies. Listed below
are all the valid filter combinations.
5
LOWER CORNER
FREQUENCY
UPPER CORNER
FREQUENCY
MINIMUM BIQUAD
CORNER FREQUENCY DHPUCF DHPLCF
Excursion limiter disabled 000 00
4
400Hz 001 00
600Hz 010 00
800Hz 011 00
1kHz 100 00
1
DHPLCF
Programmable using biquad 100Hz 000 11
200Hz 400Hz 001 01
400Hz 600Hz 010 10
400Hz 800Hz 011 10
Programmable
using biquad 400Hz 200Hz 001 11
0
Programmable
using biquad 600Hz 300Hz 010 11
Programmable
using biquad 800Hz 400Hz 011 11
Programmable
using biquad 1kHz 500Hz 100 11
0x41
6
ALCRLS
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level Control
section for ALC release times. Excursion limiter release time is defined as the time required to
slide from the high corner frequency to the low corner frequency.
VALUE EXCURSION LIMITER RELEASE TIME (s)
5
000 4
001 2
010 1
011 0.5
4
100 0.25
101 0.25
110 Reserved
111 Reserved
0x40
3
DHPTH
Excursion Limiter Threshold
Measured at the Class D speaker amplifier outputs. Signals above the threshold use the upper
corner frequency. Signals below the threshold use the lower corner frequency. VBAT must
correctly reflect the voltage of SPKLVDD to achieve accurate thresholds.
000 = 0.34VP
001 = 0.71VP
010 = 1.30VP
011 = 1.77VP
100 = 2.33VP
101 = 3.25VP
110 = 4.25VP
111 = 4.95VP
2
1
0
Stereo Audio CODEC
with FlexSound Technology
MAX9888
93
Power Limiter
The IC’s power limiter tracks the RMS power delivered to
the loudspeaker and briefly mutes the speaker amplifier
output if the speaker is at risk of sustaining permanent
damage.
Loudspeakers are typically damaged when the voice coil
overheats due to extended operation above the rated
power. During normal operation, heat generated in the
voice coil is transferred to the speaker’s magnet, which
transfers heat to the surrounding air. For the voice coil to
overheat, both the voice coil and the magnet must over-
heat. The result is that a loudspeaker can operate above
its rated power for a significant time before it heats suf-
ficiently to cause damage.
The IC’s power limiter includes user-programmable time
constants and power thresholds to match a wide range
of loudspeakers. Program the power limiter’s threshold to
match the loudspeaker’s rated power handling. This can
be determined through measurement or the loudspeak-
er’s specification. Program time constant 1 to match the
voice coil’s thermal time constant. Program time constant
2 to match the magnet’s thermal time constant. The time
constants can be determined by plotting the voice coil’s
resistance vs. time as power is applied to the speaker.
Table 26. Power Limiter Registers
REGISTER BIT NAME DESCRIPTION
0x42
7
PWRTH
Power Limiter Threshold
If the RMS output power from the speaker amplifiers exceeds this threshold, the out-
put is briefly muted to protect the speaker. The threshold is measured in watts assum-
ing an 8I load. VBAT must correctly reflect the voltage of SPKLVDD/SPKRVDD to
achieve accurate thresholds.
6
VALUE THRESHOLD
(W) VALUE THRESHOLD
(W)
0x0 Power limiter
disabled 0x8 0.27
5
0x1 0.05 0x9 0.35
0x2 0.06 0xA 0.48
0x3 0.09 0xB 0.72
0x4 0.11 0xC 1.00
4
0x5 0.13 0xD 1.43
0x6 0.18 0xE 1.57
0x7 0.22 0xF 1.80
2
PWRK
Power Limiter Weighting Factor
Determines the balance between time constant 1 and 2 to match the dominance of
each time constant in the loudspeaker.
1
VALUE T1 (%) T2 (%)
000 50 50
001 62.5 37.5
010 75 25
011 87.5 12.5
0
100 100 0
101 12.5 87.5
110 25 75
111 37.5 62.5
REGISTER BIT NAME DESCRIPTION
Stereo Audio CODEC
with FlexSound Technology
MAX9888
94
Distortion Limiter
The IC’s distortion limiter ensures that the speaker amplifier’s output does not exceed the programmed THD+N limit.
The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is
clipped. If the distortion exceeds the programmed threshold, the output gain is reduced.
Table 26. Power Limiter Registers (continued)
0x43
7
PWRT2
Power Limiter Time Constant 2
Select a value that matches the thermal time constant of the loudspeaker’s magnet.
6
VALUE TIME CONSTANT
(min) VALUE TIME CONSTANT
(min)
0x0 Disabled 0x8 3.75
0x1 0.50 0x9 5.00
5
0x2 0.67 0xA 6.66
0x3 0.89 0xB 8.88
0x4 1.19 0xC Reserved
4
0x5 1.58 0xD Reserved
0x6 2.11 0xE Reserved
0x7 2.81 0xF Reserved
3
PWRT1
Power Limiter Time Constant 1
Select a value that matches the thermal time constant of the loudspeaker’s voice coil.
2
VALUE TIME CONSTANT
(s) VALUE TIME CONSTANT
(s)
0x0 Disabled 0x8 3.75
0x1 0.50 0x9 5.00
1
0x2 0.67 0xA 6.66
0x3 0.89 0xB 8.88
0x4 1.19 0xC Reserved
0
0x5 1.58 0xD Reserved
0x6 2.11 0xE Reserved
0x7 2.81 0xF Reserved
Stereo Audio CODEC
with FlexSound Technology
MAX9888
95
Headphone Amplifier
The IC’s headphone amplifier integrates Maxim’s
DirectDrive architecture to eliminate the need for large
DC-blocking capacitors. Traditional single-supply head-
phone amplifiers have outputs biased at a nominal
DC voltage (typically half the supply). Large coupling
capacitors are needed to block this DC bias from the
headphone. Without these capacitors, a significant
amount of DC current flows to the headphone, resulting
in unnecessary power dissipation and possible damage
to both the headphone and headphone amplifier.
The DirectDrive architecture uses a charge pump to
create an internal negative supply voltage. This allows
the IC’s headphone outputs to be biased at GND while
operating from a single supply (Figure 29). Without a DC
component, there is no need for the large DC-blocking
capacitors. Instead of two large (220FF, typ) capaci-
tors, the IC charge pump requires two small ceramic
capacitors, conserving board space, reducing cost, and
improving the frequency response of the headphone
amplifier. There is a low DC voltage on the amplifier out-
puts due to amplifier offset. However, the offset of the IC
is typically Q0.2mV, which, when combined with a 32I
load, results in less than 6FA of DC current flow to the
headphones.
In addition to the cost and size disadvantages of
the DC-blocking capacitors required by conventional
headphone amplifiers, these capacitors limit the ampli-
fier’s low-frequency response and can distort the audio
signal. The DC-blocking capacitor not only blocks DC,
but also low-frequency audio. Improving the low-fre-
quency response of a conventional headphone amplifier
requires increasing the capacitor size, further adding
to the cost and size of the solution. Due to the voltage
coefficient of the capacitors used for DC blocking, they
introduce significant distortion near the corner frequency
of the highpass filter they create. This distortion further
degrades the low-frequency audio quality.
Table 27. Distortion Limiter Registers
REGISTER BIT NAME DESCRIPTION
0x44
7
THDCLP
Distortion Limit
Measured in % THD+N.
6VALUE THD+N LIMIT (%) VALUE THD+N LIMIT (%)
0x0 Limiter disabled 0x8 12
5
0x1 < 1 0x9 14
0x2 1 0xA 16
0x3 2 0xB 18
4
0x4 4 0xC 20
0x5 6 0xD 21
0x6 8 0xE 22
0x7 10 0xF 24
2
THDT1
Distortion Limiter Release Time Constant
Duration of time required for the speaker amplifier’s output gain to adjust back to the
nominal level after a large signal has passed.
000 = 6.2s
001 = 3.1s
010 = 1.6s
011 = 815ms
100 = 419ms
101 = 223ms
110 = 116ms
111 = 76ms
1
0
Stereo Audio CODEC
with FlexSound Technology
MAX9888
96
Alternative approaches to eliminating the output-cou-
pling capacitors involve biasing the headphone return
(sleeve) to the DC bias voltage of the headphone ampli-
fiers. This method raises some issues:
U The sleeve is typically grounded to the chassis. Using
the midrail biasing approach, the sleeve must be
isolated from system ground, complicating product
design.
U During an ESD strike, the amplifier’s ESD structures
are the only path to system ground. Thus, the ampli-
fier must be able to withstand the full energy from an
ESD strike.
U When using the headphone jack as a line out to other
equipment, the bias voltage on the sleeve may con-
flict with the ground potential from other equipment,
resulting in possible damage to the amplifiers.
The IC features a low-noise charge pump to generate
a negative supply for the headphone amplifier. The
nominal switching frequency is well beyond the audio
range, and thus does not interfere with audio signals.
The switch drivers feature a controlled switching speed
that minimizes noise generated by turn-on and turn-off
transients. By limiting the switching speed of the charge
pump, the di/dt noise caused by the parasitic trace
inductance is minimized. The charge pump is active only
in headphone modes.
To reduce audible noise at the outputs, the IC’s head-
phone amplifier includes headphone ground sensing.
Connect the sense line (HPSNS) to the ground terminal
of the device’s headphone jack. Any noise present at
the headphone ground is then added to the headphone
output. The result is elimination of this noise from the
audible output. If ground sensing is not required, con-
nect HPSNS directly to ground. Figure 30 shows a block
diagram of the headphone output section including the
headphone sense function.
Headphone Output Mixers
The IC’s headphone amplifier accepts input from the
stereo DAC and the line inputs. The output of the left and
right DAC cannot be mixed at the headphone mixer. Use
MIXDAL/MIXDAR to mix the left and right audio channels
before conversion.
Figure 29. Traditional Amplifier Output vs. DirectDrive Output Figure 30. Headphone Amplifier Block Diagram
VDD
VDD/2
GND
CONVENTIONAL AMPLIFIER BIASING SCHEME
DirectDrive AMPLIFIER BIASING SCHEME
+VDD
GND
-VDD
(VSS)
MIXHPL
MIXHPR
MIX
MIX
PGAOUT2:
0dB TO -23dB
HPVOLL:
+3dB TO -67dB
HPVOLR:
+3dB TO -67dB
PREOUT2 +9dB
PGAOUT1:
0dB TO -23dB
DAREN
HPL
HPSNS
HPLEN
HPREN
HPR
PREOUT1 +9dB
DACR
DALEN
DACL
Stereo Audio CODEC
with FlexSound Technology
MAX9888
97
Table 28. Headphone Output Mixer Register
Table 29. Headphone Output Level Register
Headphone Output Volume
REGISTER BIT NAME DESCRIPTION
0x27
7
MIXHPL
Left Headphone Output Mixer
10xx = Left DAC
01xx = Right DAC (requires DALEN = 0 for proper operation)
11xx = Left DAC
xx1x = Reserved
xxx1 = Preoutput mixer 1
6
5
4
3
MIXHPR
Right Headphone Output Mixer
10xx = Left DAC (requires DAREN = 0 for proper operation)
01xx = Right DAC
11xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 2
2
1
0
REGISTER BIT NAME DESCRIPTION
0x38/0x39
7 HPLM/HPRM
Headphone Output Mute
0 = Disabled
1 = Enabled
4
HPVOLL/HPVOLR
Left/Right Headphone Output Volume Level
VALUE VOLUME (dB) VALUE VOLUME (dB)
0x00 -67 0x10 -15
0x01 -63 0x11 -13
0x02 -59 0x12 -11
3
0x03 -55 0x13 -9
0x04 -51 0x14 -7
0x05 -47 0x15 -5
0x06 -43 0x16 -4
2
0x07 -40 0x17 -3
0x08 -37 0x18 -2
0x09 -34 0x19 -1
1
0x0A -31 0x1A 0
0x0B -28 0x1B +1
0x0C -25 0x1C +1.5
0
0x0D -22 0x1D +2
0x0E -19 0x1E +2.5
0x0F -17 0x1F +3
Stereo Audio CODEC
with FlexSound Technology
MAX9888
98
Output Bypass Switches
The IC includes two output bypass switches that solve
common applications problems. When a single trans-
ducer is used for the loudspeaker and receiver, the need
exists for two amplifiers to power the same transducer.
Bypass switches connect the IC’s receiver amplifier
output to the speaker amplifier’s output, allowing either
amplifier to power the same transducer. In systems where
an external receiver amplifier is used, route its output to
the left speaker through RECP/RXINP and RECN/RXINN,
bypassing the Class D amplifier. In systems where an
external amplifier drives both the receiver and the IC’s
line input, one of the differential signals can be discon-
nected from the receiver when not needed by passing it
through the analog switch that connects RECP/RXINP to
RECN/RXINN.
Figure 31. Output Bypass Switch Block Diagrams
Table 30. Output Bypass Switches Register
REGISTER BIT NAME DESCRIPTION
0x48
7 INABYP See the Microphone Inputs section.
4 MIC2BYP
1 RECBYP
RXINP to RXINN Bypass Switch
Shorts RXINP to RXINN allowing a signal to pass through the MAX9888. Disable the
receiver amplifier when RECBYP = 1.
0 = Disabled
1 = Enabled
0 SPKBYP
RXIN to SPKL Bypass Switch
Shorts RXINP/RXINN to SPKLP/SPKLN allowing either the internal or an external
receiver amplifier to power the left speaker. Disable the left speaker amplifier when
SPKBYP = 1.
0 = Disabled
1 = Enabled
EXTERNAL
RECEIVER
AMP
RECP/RXINP
RECEN
SPLEN
POWER/DISTORTION
LIMITER
RECBYP
SPKBYP
10I*
10I*
RECN/RXINN
SPKLVDD
SPKLP
SPKLN
0dB
SPKLGND
+6dB
*OPTIONAL 10I RESISTORS IMPROVE DISTORTION
THROUGH THE ANALOG SWITCH.
SPEAKER AMPLIFIER BYPASS USING AN
EXTERNAL RECEIVER AMPLIFIER
SPEAKER AMPLIFIER BYPASS USING THE
INTERNAL RECEIVER AMPLIFIER CONTROLLING AN EXTERNAL RECEIVE
AMPLIFIER AND SPEAKER
EXTERNAL
RECEIVER AMP
RECN/RXINN
RECEN
SPLEN
POWER/DISTORTION
LIMITER
RECBYP
SPKBYP
RECN/RXINN
SPKLVDD
SPKLP
SPKLN
0dB
SPKLGND
+6dB
RECP/RXINP
RECEN
SPLEN
POWER/DISTORTION
LIMITER
RECBYP
SPKBYP
RECN/RXINN
SPKLVDD
SPKLP
SPKLN
0dB
SPKLGND
+6dB
Stereo Audio CODEC
with FlexSound Technology
MAX9888
99
Click-and-Pop Reduction
The IC includes extensive click-and-pop reduction cir-
cuitry. The circuitry minimizes clicks and pops at turn-on,
turn-off, and during volume changes.
Zero-crossing detection is implemented on all analog
PGAs and volume controls to prevent large glitches
when volume changes are made. Instead of making a
volume change immediately, the change is made when
the audio signal crosses the midpoint. If no zero-crossing
occurs within the timeout window, the change is forced.
Volume slewing breaks up large volume changes into the
smallest available step size and the steps through each
step between the initial and final volume setting. When
enabled, volume slewing also occurs at device turn-on
and turn-off. During turn-on the volume is set to mute
before the output is enabled. Once the output is on, the
volume ramps to the desired level. At turn-off the volume
is ramped to mute before the outputs are disabled.
When there is no audio signal zero-crossing detection
can prevent volume slewing from occurring. Enable
enhanced volume slewing to prevent the volume control-
ler from requesting another volume level until the previ-
ous one has been set. Each step in the volume ramp
then occurs after a zero crossing has occurred in the
audio signal or the timeout window has expired. During
turn-off, enhance volume slewing is always disabled.
Table 31. Click-and-Pop Reduction Register
REGISTER BIT NAME DESCRIPTION
0x49
7VS2EN
Enhanced Volume Smoothing
During volume slewing, the controller waits for each step in the ramp to be applied
before sending the next step. When zero-crossing detection is enabled this prevents
large steps in the output volume when no zero crossings are detected.
0 = Enabled
1 = Disabled
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
6VSEN
Volume Adjustment Smoothing
Volume changes are smoothed by stepping through intermediate steps. Also ramps
the volume from minimum to the programmed value at turn-on and back to minimum at
turn-off.
0 = Enabled
1 = Disabled
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
5ZDEN
Zero-Crossing Detection
Holds volume changes until there is a zero crossing in the audio signal. This reduces
click and pop during volume changes (zipper noise). If no zero crossing is detected
within 100ms, the volume change is forced.
0 = Enabled
1 = Disabled
Applies to volume changes in PGAM1, PGAM2, PGAOUTA, PGAOUTB, PGAOUTC,
HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
1 EQ2EN See the 5-Band Parametric EQ section.
0 EQ1EN
Stereo Audio CODEC
with FlexSound Technology
MAX9888
100
Jack Detection
The IC features jack detection that can detect the inser-
tion and removal of a jack as well as the load type. When
a jack is detected, an interrupt on IRQ can be triggered
to alert the microcontroller of the event. Figure 32 shows
the typical configuration for jack detection.
Jack Insertion
To detect a jack insertion, the IC must have a power
supply and MICBIAS should be disabled. Set JDETEN
to enable jack detection circuitry and apply a pullup cur-
rent to JACKSNS. Set JDWK to minimize supply current.
Clear JDWK to differentiate between headsets with a
microphone and headphones without a microphone. The
voltage on JACKSNS is equal to SPKLVDD as long as no
load is applied to JACKSNS. Table 32 shows the change
in JKSNS that occurs when a jack is inserted.
Accessory Button Detection
After jack insertion, the MAX9888 can detect button
presses on accessories that include a microphone and
a switch that shorts the microphone signal to ground.
Set JDETEN to enable jack detection circuitry. A pullup
current is automatically applied to JACKSNS if MICBIAS
is disabled. Clear JDWK to allow differentiation between
the microphone load and a short to ground. Button
presses can be detected both when MICBIAS is enabled
and disabled. Table 33 shows the change in JKSNS that
occurs when the accessory button is pressed.
Figure 32. Typical Configuration for Jack Detection
Table 32. Change in JKSNS Upon Jack Insertion
Table 33. Change in JKSNS Upon Button Press
JACK TYPE JDWK = 1 JDWK = 0
JKSNS: 11 è 00 JKSNS: 11 è 00
JKSNS: 11 è 00 JKSNS: 11 è 01
JACK TYPE MICBIAS ENABLED OR DISABLED
JKSNS: 01 è 00
HPL MICBIAS
JACKSNS
MIC1P
HPR
GND GND R L
MIC GND R L
MIC GND R L
Stereo Audio CODEC
with FlexSound Technology
MAX9888
101
Jack Removal
The IC detects jack removal by monitoring JACKSNS
for transitions to the 11 state. Set JDETEN to enable
jack detection circuitry. A pullup current is automatically
applied to JACKSNS if MICBIAS is disabled. Set JDWK
to minimize supply current if button detection is not
required. Table 34 shows the change in JKSNS that
occurs when a jack is removed.
Table 34. Change in JKSNS Upon Jack Removal
Table 35. Jack Detection Registers
JACK TYPE JDWK = 1 AND MICBIAS DISABLED JDWK = 0 OR MICBIAS ENABLED
JKSNS: 00 è 11 JKSNS: 00 è 11
JKSNS: 00 è 11 JKSNS: 01 è 11
REGISTER BIT NAME DESCRIPTION
0x02
(Read Only)
7
JKSNS
JACKSNS State
Reports the status of JACKSNS when JDETEN = 1.
VALUE MODE DESCRIPTION
00 MBEN = 1 VJACKSNS < 0.1 x VMICBIAS
MBEN = 0 VJACKSNS < 0.1 x VSPKLVDD
01 MBEN = 1 0.1 x VMICBIAS < VJACKSNS < 0.95 x VMICBIAS
6
MBEN = 0 0.1 x VSPKLVDD < VJACKSNS < 0.95 x VSPKLVDD
10 MBEN = 1 Reserved
MBEN = 0 Reserved
11 MBEN = 1 0.95 x VMICBIAS < VJACKSNS
MBEN = 0 0.95 x VSPKLVDD < VJACKSNS
0x49
7 JDETEN
Jack Detection Enable
0 = Disabled
1 = Enabled
1
JDEB
Jack Detection Debounce
Configures the debounce time for setting JDET.
00 = 25ms
01 = 50ms
10 = 100ms
11 = 200ms
0
0x4C
7SHDN See the Power Management section.
6 VBATEN See the Battery Measurement section.
1 JDWK
JACKSNS Pullup
When JDWK = 1 JACKSNS is slow to increase in voltage. Set JDWK = 0 before setting
JDETEN = 1 to prevent false detection.
Valid when MBIAS = 0 or SHDN = 0.
0 = 2.4kI to SPKLVDD (allows microphone detection)
1 = 5FA to SPKLVDD (minimizes supply current)
GND GND R L
MIC GND R L
Stereo Audio CODEC
with FlexSound Technology
MAX9888
102
Battery Measurement
The IC measures the voltage applied to SPKLVDD (typi-
cally the battery voltage) and reports the value in regis-
ter 0x03. This value is also used by the speaker limiter
circuitry to set accurate thresholds. When the battery
measurement function is disabled, the battery voltage is
user programmable.
Table 36. Battery Measurement Registers
REGISTER BIT NAME DESCRIPTION
0x03
4
VBAT
Battery Voltage
Read VBAT when VBATEN = 1 to determine VSPKLVDD. Program VBAT when VBATEN
= 0 to allow proper speaker amplifier signal processing. Calculate the battery voltage
using the following formula:
VBATTERY = 2.55V + [VBAT/10]
3
2
1
0
0x4C
7SHDN See the Power Management section.
6 VBATEN
Battery Measurement Enable
Enables an internal ADC to measure VSPKLVDD.
0 = Disabled (register 0x03 readable and writeable)
1 = Enabled (register 0x03 read only)
1 JDWK See the Headset Detection section.
Stereo Audio CODEC
with FlexSound Technology
MAX9888
103
Table 37. Status and Interrupt Registers
Device Status
The IC uses register 0x00 and IRQ to report the status of
various device functions. The status register bits are set
when their respective events occur, and cleared upon
reading the register. Device status can be determined
either by poling register 0x00 or configuring the IRQ to
pull low when specific events occur. IRQ is an open-
drain output that requires a pullup resistor for proper
operation. Register 0x0F determines which bits in the
status register trigger IRQ to pull low.
REGISTER BIT NAME DESCRIPTION
0x00
(Read Only)
7 CLD
Full Scale
0 = All digital signals are less than full scale.
1 = The DAC or ADC signal path has reached or exceeded full scale. This typically
indicates clipping.
6 SLD
Volume Slew Complete
SLD reports that any of the programmable-gain arrays or volume controllers has
completed slewing from a previous setting to a new programmed setting. If multiple
gain arrays or volume controllers are changed at the same time, the SLD flag is set
after the last volume slew completes. SLD also reports when the digital audio interface
soft-start or soft-stop process has completed. MCLK is required for proper SLD
operation.
0 = No volume slewing sequences have completed since the status register was last
read.
1 = Volume slewing complete.
5 ULK
Digital Audio Interface Unlocked
0 = Both digital audio interfaces are operating normally.
1 = Either digital audio interface is configured incorrectly or receiving invalid data.
1 JDET
Jack Configuration Change
JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack
Status bits are debounced before setting JDET. The debounce period is programmable
using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first
time power is applied to the IC. Read the status register following such an event to clear
JDET and allow for proper jack detection.
0 = No change in jack configuration.
1 = Jack configuration has changed.
0x0F
7 ICLD
Full-Scale Interrupt Enable
0 = Disabled
1 = Enabled
6 ISLD
Volume Slew Complete Interrupt Enable
0 = Disabled
1 = Enabled
5 IULK
Digital Audio Interface Unlocked Interrupt Enable
0 = Disabled
1 = Enabled
1 IJDET
Jack Configuration Change Interrupt Enable
0 = Disabled
1 = Enabled
Stereo Audio CODEC
with FlexSound Technology
MAX9888
104
Table 38. Device Revision Register
Figure 33. START, STOP, and REPEATED START Conditions
I2C Serial Interface
The IC features an I2C/SMBusK-compatible, 2-wire
serial interface comprising a serial-data line (SDA) and
a serial-clock line (SCL). SDA and SCL facilitate com-
munication between the IC and the master at clock rates
up to 400kHz. Figure 5 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
IC by transmitting the proper slave address followed by
the register address and then the data word. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START or REPEATED
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically greater than 500I,
is required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500I, is required
on SCL if there are multiple masters on the bus, or if
the single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the IC from high
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals (see the START and STOP Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 33). A
START condition from the master signals the beginning
of a transmission to the IC. The master terminates trans-
mission, and frees the bus, by issuing a STOP condition.
The bus remains active if a REPEATED START condition
is generated instead of a STOP condition.
Early STOP Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the
same SCL high pulse as the START condition.
SMBus is a trademark of Intel Corp.
Device Revision
REGISTER BIT NAME DESCRIPTION
0xFF
(Read Only)
7
REV Device Revision Code
REV is always set to 0x43.
6
5
4
3
2
1
0
SCL
SDA
S Sr P
Stereo Audio CODEC
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105
Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 0010000. Setting
the read/write bit to 1 (slave address = 0x21) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x20) configures the IC for write mode. The
address is the first byte of information sent to the IC after
the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 34). The IC pulls down SDA dur-
ing the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event
of an unsuccessful data transfer, the bus master retries
communication. The master pulls down SDA during the
9th clock cycle to acknowledge receipt of data when
the IC is in read mode. An acknowledge is sent by the
master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the IC, followed by a
STOP condition.
Write Data Format
A write to the IC includes transmission of a START condi-
tion, the slave address with the R/W bit set to 0, one byte
of data to configure the internal register address pointer,
one or more bytes of data, and a STOP condition. Figure
35 illustrates the proper frame format for writing one byte
of data to the IC. Figure 35 illustrates the frame format for
writing n-bytes of data to the IC.
Figure 34. Acknowledge
Figure 35. Writing One Byte of Data to the IC
Figure 36. Writing n-Bytes of Data to the IC
1
SCL
START
CONDITION
SDA
2 8 9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9888
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888
SOAAA PSLAVE ADDRESS
R/W
REGISTER ADDRESS DATA BYTE
ACKNOWLEDGE FROM MAX9888
SLAVE ADDRESS REGISTER ADDRESS DATA BYTE 1
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
1 BYTE
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
SOAAADATA BYTE n
1 BYTE
PA
R/W
Stereo Audio CODEC
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MAX9888
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The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the IC. The IC
acknowledges receipt of the address byte during the
master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer
tells the IC where to write the next byte of data. An
acknowledge pulse is sent by the IC upon receipt of the
address pointer data.
The third byte sent to the IC contains the data that is
written to the chosen register. An acknowledge pulse
from the IC signals receipt of the data byte. The address
pointer autoincrements to the next register address after
each received data byte. This autoincrement feature
allows a master to write to sequential registers within
one continuous frame. The master signals the end of
transmission by issuing a STOP condition. Register
addresses greater than 0xC7 are reserved. Do not write
to these addresses.
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The IC acknowledges receipt of
its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read com-
mand resets the address pointer to register 0x00.
The first byte transmitted from the IC is the content of
register 0x00. Transmitted data is valid on the rising
edge of SCL. The address pointer autoincrements after
each read data byte. This autoincrement feature allows
all registers to be read sequentially within one continu-
ous frame. A STOP condition can be issued after any
number of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte to
be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the IC’s slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/W bit set to 1. The
IC then transmits the contents of the specified register.
The address pointer autoincrements after transmitting
the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowl-
edge from the master and then a STOP condition. Figure
37 illustrates the frame format for reading one byte from
the IC. Figure 38 illustrates the frame format for reading
multiple bytes from the IC.
Figure 37. Reading One Byte of Data from the IC
Figure 38. Reading n Bytes of Data from the IC
ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888 NOT ACKNOWLEDGE FROM MASTER
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
1 BYTE
P
REPEATED START
SO A ASr 1AA
SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
R/W
R/W
ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
1 BYTE
REPEATED START
SOAA Sr 1 AA
SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
R/W R/W
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Applications Information
Typical Operating Circuits
Figures 39 and 40 provide example operating circuits for
the IC. The external components shown are the minimum
required for the IC to operate. Additional components
may be required by the application.
Figure 39. Typical Application Circuit Using Analog Microphone Inputs and the Bypass Switch
Analog Microphones and Bypass Switch
2.2kI
1kI
1kI
IRQ
1.8V TO
5.5V
10kI
TO MICROCONTROLLER
10MHz TO 60MHz CLOCK INPUT
DIGITAL AUDIO
PORT 1
I2C CONTROL
PORT
MICROPHONE
OUTPUT TO
BASEBAND
JACKSNS
HEADSET
MICROPHONE 1FF
1FF
1FF 1FF 2.2FF
1FF
HANDSET
MICROPHONE 1FF
1FF
DIGITAL
AUDIO
PORT 2
JACKSNS
BYPASS
SWITCH
INPUT
LRCLKS2
BCLKS2
SDINS2
SDOUTS2
JACKSNS
RECP/RXINP
RECN/RXINN
SPKLP
SPKLN
SPKRP
SPKRN
HPR
HPL
HPSNS
REF
PREG
REG
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
SDA
SCL
MIC1P/DIGMICDATA
MIC1N/DIGMICCLK
MICBIAS
MIC2P
MIC2N
INA1/EXTMICP
INA2/EXTMICN
INB1
INB2
LINE INPUT 1FF
1FF
1FF
1FF
AGND HPGND SPKRGND SPKLGND C1NHPVSS C1PDGND
DVDDS1 DVDD HPVDD AVDD SPKLVDD SPKRVDD DVDDS2
1FF 1FF
10FF1.8V TO 3.6V
2.8V TO 5.5V
1.8V
1.8V TO 3.6V
1FF 1FF 1FF 1FF 1FF
8I
8I
MAX9888
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108
Figure 40. Typical Application Circuit Using the Digital Microphone Input and Receiver Amplifier
Digital Microphones and Receiver Amplifier
IRQ
10kI
TO MICROCONTROLLER
10MHz TO 60MHz
CLOCK INPUT
DIGITAL AUDIO
PORT 1
I2C CONTROL
PORT
1FF 1FF 2.2FF
DIGITAL
AUDIO
PORT 2
JACKSNS
LRCLKS2
BCLKS2
SDINS2
SDOUTS2
JACKSNS
RECP/RXINP
RECN/RXINN
SPKLP
SPKLN
SPKRP
SPKRN
HPR
HPL
HPSNS
REF
PREG
REG
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
SDA
SCL
MIC1P/DIGMICDATA
MIC1N/ DIGMICCLK
MICBIAS
MIC2P
MIC2N
INA1/EXTMICP
INA2/EXTMICN
INB1
INB2
2.2kI
DIGITAL
MIC 1
DIGITAL
MIC 2
JACKSNS
HEADSET
MICROPHONE 1FF
1FF
1FF
DATA
CLOCK
DATA
CLOCK
1FF
1FF
AGND HPGND SPKRGND SPKLGND C1NHPVSS
C1P
DGND
LINE INPUT 1FF
1FF
LINE INPUT 1FF
1FF
32I
DVDDS1 DVDD HPVDD AVDD SPKLVDD SPKRVDD DVDDS2
1FF 1FF
10FF1.8V TO 3.6V
1.8V
1.8V TO 3.6V
1FF 1FF 1FF 1FF 1FF
2.8V TO 5.5V
1.8V TO
5.5V
MAX9888
8I
8I
Stereo Audio CODEC
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109
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filters add cost, increase the solution size of the
amplifier, and can decrease efficiency and THD+N
performance. The traditional PWM scheme uses large
differential output swings (2 x VDD peak to peak) and
causes large ripple currents. Any parasitic resistance in
the filter components results in a loss of power, lowering
the efficiency.
The IC does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear
to recover the audio component of the square-wave out-
put. Eliminating the output filter results in a smaller, less
costly, more efficient solution.
Because the frequency of the IC output is well beyond
the bandwidth of most speakers, voice coil move-
ment due to the square-wave frequency is very small.
Although this movement is small, a speaker not designed
to handle the additional power can be damaged. For
optimum results, use a speaker with a series inductance
> 10FH. Typical 8I speakers exhibit series inductances
in the 20FH to 100FH range.
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its har-
monics that is easily demodulated by audio amplifiers.
The IC is designed specifically to reject RF signals; how-
ever, PCB layout has a large impact on the susceptibility
of the end product.
In RF applications, improvements to both layout and com-
ponent selection decrease the IC’s susceptibility to RF
noise and prevent RF signals from being demodulated into
audible noise. Trace lengths should be kept below 1/4 of
the wavelength of the RF frequency of interest. Minimizing
the trace lengths prevents them from functioning as anten-
nas and coupling RF signals into the IC. The wavelength
(l) in meters is given by: l = c/f where c = 3 x 108 m/s, and
f = the RF frequency of interest.
Route audio signals on middle layers of the PCB to allow
ground planes above and below to shield them from RF
interference. Ideally, the top and bottom layers of the
PCB should primarily be ground planes to create effec-
tive shielding.
Additional RF immunity can also be obtained by rely-
ing on the self-resonant frequency of capacitors as it
exhibits a frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capaci-
tors typically exhibit self resonance at the RF frequencies
of interest. These capacitors, when placed at the input
pins, can effectively shunt the RF noise to ground. For
these capacitors to be effective, they must have a low-
impedance, low-inductance path to the ground plane.
Avoid using microvias to connect to the ground plane
whenever possible as these vias do not conduct well at
RF frequencies.
Startup/Shutdown Sequencing
To ensure proper device initialization and minimal click-
and-pop, program the IC’s SHDN = 1 after configuring all
registers. Table 39 lists an example startup sequence for
the device. To shut down the IC, simply set SHDN = 0.
Table 39. Example Startup Sequence
SEQUENCE DESCRIPTION REGISTERS
1 Ensure SHDN = 0 0x4C
2 Configure clocks 0x10 to 0x13, 0x19 to 0x1B
3 Configure digital audio interface 0x14 to 0x17, 0x1C to 0x1F
4 Configure digital signal processing 0x18, 0x20, 0x3D to 0x44
5 Load coefficients 0x50 to 0xC7
6 Configure mixers 0x21 to 0x29
7 Configure gain and volume controls 0x2A to 0x3C
8 Configure miscellaneous functions 0x45 to 0x49
9 Enable desired functions 0x4A, 0x4B
10 Set SHDN = 1 0x4C
Stereo Audio CODEC
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110
While many configuration options in the IC can be made
while the device is operating, some registers should
only be adjusted when the corresponding audio path is
disabled. Table 40 lists the registers that are sensitive
during operation. Either disable the corresponding audio
path or set SHDN = 0 while changing these registers.
Component Selection
Optional Ferrite Bead Filter
In applications where speaker leads exceed 20mm,
additional EMI suppression can be achieved by using a
filter constructed from a ferrite bead and a capacitor to
ground (Figure 41). Use a ferrite bead with low DC resis-
tance, high-frequency (> 600MHz) impedance between
100I and 600I, and rated for at least 1A. The capacitor
value varies based on the ferrite bead chosen and the
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
Input Capacitor
An input capacitor, CIN, in conjunction with the input
impedance of the IC line inputs forms a highpass filter
that removes the DC bias from an incoming analog
signal. The AC coupling capacitor allows the amplifier
to automatically bias the signal to an optimum DC level.
Assuming zero-source impedance, the -3dB point of the
highpass filter is given by:
-3dB IN IN
1
f2 R C
=
π
Choose CIN so that f-3dB is well below the lowest fre-
quency of interest. For best audio quality use capacitors
whose dielectrics have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with high-
voltage coefficients, such as ceramics, may result in
increased distortion at low frequencies.
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mI for optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surface-
mount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
Table 40. Registers That Are Sensitive to Changes During Operation
Figure 41. Optional Class D Ferrite Bead Filter
REGISTER DESCRIPTION
0x10 to 0x13, 0x19 to 0x1B Clock Control Registers
0x14 to 0x17, 0x1C to 0x1F Digital Audio Interface Configuration
0x18, 0x20 Digital Passband Filters
0x24 to 0x29 Analog Mixers
0x50 to 0xC7 Digital Signal Processing Coefficients
MAX9888
SPK_P
SPK_N
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Charge-Pump Flying Capacitor
The value of the flying capacitor (connected between
C1N and C1P) affects the output resistance of the
charge pump. A value that is too small degrades the
device’s ability to provide sufficient current drive, which
leads to a loss of output voltage. Increasing the value
of the flying capacitor reduces the charge-pump output
resistance to an extent. Above 1FF, the on-resistance
of the internal switches and the ESR of external charge-
pump capacitors dominate.
Charge-Pump Holding Capacitor
The holding capacitor (bypassing HPVSS) value and
ESR directly affect the ripple at HPVSS. Increasing
the capacitor’s value reduces output ripple. Likewise,
decreasing the ESR reduces both ripple and output
resistance. Lower capacitance values can be used in
systems with low maximum output power levels. See the
Output Power vs. Load Resistance graph in the Typical
Operating Characteristics section for more information
Unused Pins
Table 41 shows how to connect the IC’s pins when
unused.
Table 41. Unused Pins
NAME CONNECTION NAME CONNECTION
SPKRP Unconnected INB1 Unconnected
SPKRVDD Always connected INA2/MICEXTN Unconnected
SPKLVDD Always connect LRCLKS2 Unconnected
SPKLP Unconnected MCLK Always connect
RECN/RXINN Unconnected SDINS2 AGND
HPVDD Always connect IRQ Unconnected
C1P Unconnected MIC1P/DIGMICDATA Unconnected
HPGND AGND INA1/MICEXTP Unconnected
SPKRN Unconnected DGND Always connect
SPKRGND Always connect BCLKS2 Unconnected
SPKLGND Always connect SDA Always connect
SPKLN Unconnected SCL Always connect
RECP/RXINP Unconnected REG Always connect
C1N Unconnected REF Always connect
HPL Unconnected MIC1N/DIGMICCLK Unconnected
HPVSS Unconnected MIC2P Unconnected
SDINS1 AGND SDOUTS2 Unconnected
LRCLKS1 Unconnected DVDDS2 DVDD
HPSNS AGND DVDD Always connect
INB2 Unconnected AVDD Always connect
HPR Unconnected PREG Always connect
DVDDS1 DVDD AGND Always connect
SDOUTS1 Unconnected MICBIAS Unconnected
BCLKS1 Unconnected MIC2N Unconnected
JACKSNS Unconnected
Stereo Audio CODEC
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MAX9888
112
Recommended PCB Routing
The IC uses a 63-bump WLP package. Figure 42
provides an example of how to connect to all active
bumps using 3 layers of the PCB. To ensure uninter-
rupted ground returns, use layer 2 as a connecting layer
between layer 1 and layer 2 and flood the remaining area
with ground.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the IC, parti-
tion the circuitry so that the analog sections of the IC are
separated from the digital sections. This ensures that the
analog audio traces are not routed near digital traces.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect AGND,
DGND, HPGND, SPKLGND, and SPKRGND directly to
the ground plane using the shortest trace length pos-
sible. Proper grounding improves audio performance,
minimizes crosstalk between channels, and prevents
any digital noise from coupling into the analog audio
signals.
Ground the bypass capacitors on MICBIAS, REG, PREG,
and REF directly to the ground plane with minimum
trace length. Also be sure to minimize the path length to
AGND. Bypass AVDD directly to AGND.
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD,
DVDDS1, and DVDDS2 directly to DGND.
Place the capacitor between C1P and C1N as close as
possible to the IC to minimize trace length from C1P to
C1N. Inductance and resistance added between C1P
and C1N reduce the output power of the headphone
amplifier. Bypass HPVSS with a capacitor located close
to HPVSS with a short trace length to HPGND. Close
decoupling of HPVSS minimizes supply ripple and maxi-
mizes output power from the headphone amplifier.
HPSNS senses ground noise on the headphone jack and
adds the same noise to the output audio signal, thereby
making the output (headphone output minus ground)
noise free. Connect HPSNS to the headphone jack shield
to ensure accurate pickup of headphone ground noise.
Bypass SPKLVDD and SPKRVDD to SPKLGND and
SPKRGND, respectively, with as little trace length as
possible. Connect SPKLP, SPKLN, SPKRP, and SPKRN
to the stereo speakers using the shortest traces pos-
sible. Reducing trace length minimizes radiated EMI.
Route SPKLP/SPKLN and SPKRP/SPKRN as differential
pairs on the PCB to minimize loop area, thereby the
inductance of the circuit. If filter components are used
on the speaker outputs, be sure to locate them as close
as possible to the IC to ensure maximum effectiveness.
Minimize the trace length from any ground-connected
passive components to SPKLGND and SPKRGND to
further minimize radiated EMI.
Figure 42. Suggested Routing
LAYER 1
LAYER 2
LAYER 3
Stereo Audio CODEC
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MAX9888
113
Route microphone signals from the microphone to the IC
as a differential pair, ensuring that the positive and nega-
tive signals follow the same path as closely as possible
with equal trace length. When using single-ended micro-
phones or other single-ended audio sources, ground the
negative microphone input as close as possible to the
audio source and then treat the positive and negative
traces as differential pairs.
An evaluation kit (EV kit) is available to provide an exam-
ple layout for the IC. The EV kit allows quick setup of the
IC and includes easy-to-use software allowing all internal
registers to be controlled.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profile, as well as the latest information on reliability
testing results, refer to the Application Note 1891: Wafer-
Level Packaging (WLP) and Its Applications. Figure 43
shows the dimensions of the WLP balls used on the IC. Figure 43. WLP Ball Dimensions
0.24mm
0.21mm
Stereo Audio CODEC
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114
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
63 WLP W633A3+1 21-0462 Refer to
Application Note 1891
Stereo Audio CODEC
with FlexSound Technology
MAX9888
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 115
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/10 Initial release
1 2/11 Updated DAC playback 48kHz stereo, speaker outputs, speaker maximum value 6