© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 4 1Publication Order Number:
MC74VHCT139A/D
MC74VHCT139A
Dual 2−to−4 Decoder/
Demultiplexer
The MC74VHCT139A is an advanced high speed CMOS 2−to−4
decoder/demultiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL devices while maintaining CMOS low power
dissipation.
When the device is enabled (E = low), it can be used for gating or as
a data input for demultiplexing operations. When the enable input is
held high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device output is compatible with TTL−type input thresholds
and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic
to 3.0 V CMOS logic while operating at the high−voltage power
supply
The MC74VHCT139A input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHCT139A to be used to interface 5.0 V circuits to
3.0 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage−input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
•High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V
•Low Power Dissipation: ICC = 4 mΑ (Max) at TA = 25°C
•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
•Power Down Protection Provided on Inputs and Outputs
•Balanced Propagation Delays
•Designed for 2.0 V to 5.5 V Operating Range
•Low Noise: VOLP = 0.8 V (Max)
•Pin and Function Compatible with Other Standard Logic Families
•Latchup Performance Exceeds 300 mA
•ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
•Chip Complexity: 100 FETs or 25 Equivalent Gates
•Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G= Pb−Free Package
VHCT139AG
AWLYWW
VHCT
139A
ALYWG
G
(Note: Microdot may be in either location)
1
1
16
1
1
16
1
SOEIAJ−16
M SUFFIX
CASE 966
74VHCT139
ALYWG
1
16
FUNCTION TABLE
Inputs Outputs
E A1 A0 Y0 Y1 Y2 Y3
HXXHHHH
LLLLHHH
LLHHLHH
LHLHHLH
LHHHHHL
MC74VHCT139A
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2
Figure 1. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Ea
A1a
A0a
GND
A1b
A0b
Eb
VCC
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
Figure 2. Logic Diagram
A0a
A1a
Ea
A0b
A1b
1
Eb
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
ACTIVE−LOW
OUTPUTS
ADDRESS
INPUTS
ACTIVE−LOW
OUTPUTS
3
2
ADDRESS
INPUTS 13
14
15
4
5
6
7
12
11
10
9
En
A0
A1
Y0
Y1
Y2
Y3
Figure 3. Expanded Logic Diagram
(1/2 of Device)
INPUT
Figure 4. Input Equivalent Circuit
4
Figure 5. IEC Logic Diagram
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
5
6
7
12
11
10
9
15
14
13
1
2
3
A1a
A0a
Ea
A1b
A0b
Eb
2
1
EN
X/Y
1
0
2
3
0
1
DMUX
1
0
2
3
G0
3
15
14
13
1
2
3
A1a
A0a
Ea
A1b
A0b
Eb
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
4
5
6
7
12
11
10
9
MC74VHCT139A
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3
MAXIMUM RATINGS (Note 1)
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage −0.5 to +7.0 V
VIN Digital Input Voltage −0.5 to +7.0 V
VOUT DC Output Voltage Output in 3−State
High or Low State −0.5 to +7.0
−0.5 to VCC +0.5 V
IIK Input Diode Current −20 mA
IOK Output Diode Current $20 mA
IOUT DC Output Current, per Pin $25 mA
ICC DC Supply Current, VCC and GND Pins $75 mA
PDPower Dissipation in Still Air SOIC Package
TSSOP 200
180 mW
TSTG Storage Temperature Range −65 to +150 °C
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
>2000
>200
>2000
V
ILATCHUP Latchup Performance Above VCC and Below GND at 125°C (Note 5) $300 mA
qJA Thermal Resistance, Junction−to−Ambient SOIC Package
TSSOP 143
164 °C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
VCC DC Supply Voltage 4.5 5.5 V
VIN DC Input Voltage 0 5.5 V
VOUT DC Output Voltage Output in 3−State
High or Low State 0
05.5
VCC V
TAOperating Temperature Range, all Package Types −55 125 °C
tr, tfInput Rise or Fall Time VCC = 5.0 V + 0.5 V 0 20 ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME
TO 0.1% BOND FAILURES
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
TIME, YEARS
NORMALIZED FAILURE RATE
TJ= 80 C°
TJ= 90 C°
TJ= 100 C°
TJ= 110 C°
TJ= 130 C°
TJ= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 6. Failure Rate vs. Time Junction Temperature
MC74VHCT139A
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4
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC TA = 25°C TA ≤ 85°C TA = − 55 to
125°C
Symbol Parameter Condition (V) Min Typ Max Min Max Min Max Unit
VIH Minimum High−Level Input
Voltage 4.5 to 5.5 2 2 2 V
VIL Maximum Low−Level Input
Voltage 4.5 to 5.5 0.8 0.8 0.8 V
VOH Maximum High−Level
Output Voltage VIN = VIH or VIL
IOH = −50 mA4.5 4.4 4.5 4.4 4.4 V
VIN = VIH or VIL
IOH = −8 mA 4.5 3.94 3.8 3.66
VOL Maximum Low−Level
Output Voltage VIN = VIH or VIL
IOL = 50 mA4.5 0 0.1 0.1 0.1 V
VIN = VIH or VIL
IOH = 8 mA 4.5 0.36 0.44 0.52
IIN Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent
Supply Current VIN = VCC or GND 5.5 4.0 40.0 40.0 mA
ICCT Additional Quiescent
Supply Current (per Pin) Any one input:
VIN = 3.4 V
All other inputs:
VIN = VCC or GND
5.5 1.35 1.5 1.5 mA
IOPD Output Leakage Current VOUT = 5.5 V 0 0.5 5 5 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
TA = 25°C
ÎÎÎÎÎ
Î
ÎÎÎ
Î
ÎÎÎÎÎ
TA ≤ 85°C
ÎÎÎÎ
Î
ÎÎÎ
ÎÎÎÎ
TA = − 55 to
125°C
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Test Conditions
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Typ
ÎÎÎ
ÎÎÎ
Max
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Max
ÎÎÎ
ÎÎÎ
Min
ÎÎ
ÎÎ
Max
ÎÎ
ÎÎ
Unit
ÎÎÎÎ
Î
ÎÎ
Î
Î
ÎÎ
Î
ÎÎÎÎ
tPLH,
tPHL
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Maximum Propagation
Delay, A to Y
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
7.2
9.7
ÎÎÎ
ÎÎÎ
11.0
14.5
ÎÎÎ
ÎÎÎ
1.0
1.0
ÎÎÎ
ÎÎÎ
13.0
16.5
ÎÎÎ
ÎÎÎ
1.0
1.0
ÎÎ
ÎÎ
13.0
16.5
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎ
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
5.0
6.5
ÎÎÎ
Î
Î
Î
ÎÎÎ
7.2
9.2
ÎÎÎ
Î
Î
Î
ÎÎÎ
1.0
1.0
ÎÎÎ
Î
Î
Î
ÎÎÎ
8.5
10.5
ÎÎÎ
Î
Î
Î
ÎÎÎ
1.0
1.0
ÎÎ
Î
Î
ÎÎ
8.5
10.5
ÎÎÎÎ
Î
ÎÎ
Î
Î
ÎÎ
Î
ÎÎÎÎ
tPLH,
tPHL
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Maximum Propagation
Delay, E to Y
ÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎ
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
6.4
8.9
ÎÎÎ
Î
Î
Î
ÎÎÎ
9.2
12.7
ÎÎÎ
Î
Î
Î
ÎÎÎ
1.0
1.0
ÎÎÎ
Î
Î
Î
ÎÎÎ
11.0
14.5
ÎÎÎ
Î
Î
Î
ÎÎÎ
1.0
1.0
ÎÎ
Î
Î
ÎÎ
11.0
14.5
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.4
5.9
ÎÎÎ
ÎÎÎ
6.3
8.3
ÎÎÎ
ÎÎÎ
1.0
1.0
ÎÎÎ
ÎÎÎ
7.5
9.5
ÎÎÎ
ÎÎÎ
1.0
1.0
ÎÎ
ÎÎ
7.5
9.5
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
CIN
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Maximum Input
Capacitance
ÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
4
ÎÎÎ
Î
Î
Î
ÎÎÎ
10
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
10
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎ
Î
Î
ÎÎ
10
ÎÎ
ÎÎ
ÎÎ
pF
CPD Power Dissipation Capacitance (Note 6)
Typical @ 25°C, VCC = 5.0V
pF
26
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
MC74VHCT139A
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5
Figure 7. Switching Waveform
1.5 V
tPHL
tPLH
3.0 V
GND
Y1.5 V
A3.0 V
GND
tPHL tPLH
Y
E
1.5 V
1.5 V
Figure 8. Switching Waveform
*Includes all probe and jig capacitance
Figure 9. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
VOL
VOH
VOL
VOH
ORDERING INFORMATION
Device Package Shipping†
MC74VHCT139AD SOIC−16 48 Units / Rail
MC74VHCT139ADG SOIC−16
(Pb−Free) 48 Units / Rail
MC74VHCT139ADR2 SOIC−16 2500 Tape & Reel
MC74VHCT139ADR2G SOIC−16
(Pb−Free) 2500 Tape & Reel
MC74VHCT139ADT TSSOP−16* 96 Units / Rail
MC74VHCT139ADTG TSSOP−16* 96 Units / Rail
MC74VHCT139ADTR2 TSSOP−16* 2500 Tape & Reel
MC74VHCT139ADTRG TSSOP−16* 2500 Tape & Reel
MC74VHCT139AM SOEIAJ−16 50 Units / Rail
MC74VHCT139AMG SOEIAJ−16
(Pb−Free) 50 Units / Rail
MC74VHCT139AMEL SOEIAJ−16 2000 Tape & Reel
MC74VHCT139AMELG SOEIAJ−16
(Pb−Free) 2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74VHCT139A
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6
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
MC74VHCT139A
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7
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
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