NEC Electronics Inc. CMOS-9HD 3.3-Volt, 0.35-Micron (drawn) CMOS Gate Array Preliminary Description January 1998 Figure 1. Tape BGA and Chip Size Package NEC's CMOS-9HD, density-enhanced, 0.35 m gate array family delivers a complete, low-cost answer to modern-day computer and communication system ASICs. This new family uses the high-speed capabilities of a 3.3V, 0.35 m gate array technology, combined with a unique, highdensity NXT architecture from In-Chip Systems, Inc. to provide an inexpensive, high-performance solution to demanding design implementations. CMOS-9HD offers three layers of metal and stacked vias for greater routability and gate utilization. In addition, many specialized I/Os allow this densified 0.35 m family to interface using highspeed standards such as GTL+, HSTL, pECL and 5 and 3.3V, 66 MHz PCI. CMOS-9HD also offers an advanced clock insertion methodology. This includes a progressive clock tree synthesis capability with high-accuracy single frequency and multiplying digital phase-locked loops (DPLL). The CMOS-9HD gate array family consists of 10 available masters with 76K to 1.6M raw gates. This allows 53K to 1.1M usable gates running on a 3.3V power supply. CMOS-9HD, as well as the other gate array families, are supported by NEC's OpenCAD design system; a mixture of popular third-party CAE tools, and proprietary NEC tools. NEC proprietary tools include GALET floorplanner which helps reduce layout time and improve performance, clock tree synthesis for clock skew minimization, and table lookup delay calculator for accurate timing characteristics. Applications The CMOS-9HD family is ideal for use in enterprise systems, engineering workstations, telecommunications switching, transmission and wireless systems, where extensive integration, high speeds and high density are the primary design goals. CMOS-9HD is well-suited for designs requiring very high integration (500K-800K gates, 500-700 pins), high system speeds (100-200 MHz) and high performance interface standards (GTL+, pECL). CMOS-9HD is also well-suited for low power applications where high performance is required. Table 1. CMOS-9HD Series Features and Benefits CMOS-9HD Series Features * 0.35 m (drawn) 3-level metal CMOS technology CMOS-9HD Series Benefits Delivers high 0.35 m technology speeds at 2.5 times the density * High-Density NXT Cell Architecture from In-Chip Systems, Inc. Reduces cell area by 58% resulting in a much lower die cost * Ten base arrays with 76K - 1.6M raw gate counts Allows several different masters across large range of gate counts * Narrow pad pitch with 156 - 692 available I/Os Offers large numbers of I/Os with very small die sizes * GTL, GTL+, pECL, and HSTL interface capabilities Provides signaling with high-speed memory and processor buses * Full range of 5V-protected I/O buffers Delivers 5V interface capabilities while protecting 3.3V core logic * PCI buffers including 3.3V 66 MHz Supports the PCI local bus applications * Stacked vias and tighter metal pitch for increased routability Frees up additional routing area allowing much higher utilization * Single frequency and multiplying DPLL macros Offers frequency multiplication while eliminating clock tree delay * Low power dissipation: 0.5 W/MHz/gate Provides low power consumption at high system clock rates * Extensive package offering: QFPs, BGAs, TAB BGAs, CSPs Satisfies electrical, thermal, soldering, size and cost requirements * Floorplanner and Clock Tree Synthesis Tool design automation Optimizes placement and performance while reducing design time * Popular, third-party CAE tools supported A12811EU3V0DS00 Enables a smooth flow from customer design to silicon OpenCAD is a registered trademark of NEC Electronics Inc. All non-NEC trademarks are the property of their respective owners. CMOS-9HD Figure 2. Power Rail Structure Array Architecture The CMOS-9HD gate array family is built with In-Chip's 0.35-micron (drawn) channelless array architecture and NEC's I/O and Power Rail Structure. As shown in Figure 2, the array is divided into I/O and core regions. The I/O region contains input and output buffers. The core region contains the sea-of-gates array and embedded blocks. Core Region The CMOS-9HD gate array's architecture provides extra flexibility for high performance system designs. As shown in Figure 2, the arrays contain two power rails: a 3.3V rail, and a second power rail (VDD2) for special I/O types. The VDD2 rail is used for interfaces such as HSTL where a very low I/O power supply is required (1.4 to 1.6V). All four classes of HSTL buffer are supported. The VDD2 rail may be separated into sections to allow one device to support two or more buses requiring special I/O voltages. Examples of spread I/O cells that may use this VDD rail are HSTL and 5V PCI. Each section can operate as an independent voltage zone, and sections can be linked together to form common voltage zones. 3.3V VDD Rail VDD2 P-Channel N-Channel Table 2. CMOS-9HD Base Array Line-up Device(1) Drawing not to scale Max Pads Reg. Tight Pitch Pitch Available Gates Usable Gates(2) 3LM 43 75740 53018 128 172 44 100602 70421 148 196 45 128338 89836 - 216 46 202630 141841 200 268 CMOS-9HD Memory 48 312684 218878 247 324 49 437136 305995 289 380 51 585390 351234 328 436 54 835664 501398 388 516 CMOS-9HD offers three different types of available memory. Included are fixed RAM (Random Access Memory) and ROM (Read Only Memory) blocks, and one- and two-port compiled RAMs. Each storage element is considered to be asynchronous in operation. 56 1096452 657871 445 588 58 1615646 969387 535 708 (PD659xx) 3LM Notes: (1) "3LM" represents three-layer metal. (2) Actual gate utilization varies depending on circuit implementation. Utilization is 70% for most masters. Core Region The core region consists of an array of gates. Each gate contains 2 n-channel and 2 p-channel MOS logic transistors. One core gate is equivalent to one 2-input NAND gate (L302). 2 In-Chip Systems, Inc. joins NEC in the development of CMOS-9HD's core region. By designing uniquely shaped transistors which consume a much smaller area, In-Chip is able to reduce cell size and power while maintaining advanced 0.35 m system performance. NEC's high-speed, RAM Blocks have a bit/word architecture based on basic hard macros. The BIST (Built-in-SelfTest) circuit and built-in selector are configured by soft macros. This architecture eases restrictions on placement and routing and reduces complexity when multiple RAMs are placed. Compiled RAM differs from the conventional RAM in that the customer can select the bit size in the range from 2 bits to 128 bits (however, the number of words is limited by the number of bits). Table 3 shows the ranges for the existing CMOS-9HD RAM line-up. CMOS-9HD Table 3. CMOS-9HD RAM Types Type Mode Ports Bit Range Word Range Compiled Sync. 1 2-128 bits 4-1K words 2-word incr. Sync. 2 2-128 bits 4-1K words 2-word incr. High-speed Sync. 1 4-10 bits 16-64 words High-speed Sync. 2 4-10 bits 16-64 words High-Speed Async. 1 4-10 bits 16-64 words High-Speed Async. 2 4-10 bits 16-64 words Block Packaging and Test CMOS-9HD gate arrays support automatic test generation through a scan-test methodology, which allows higher fault coverage, easier testing and quicker development time. NEC also offers optional BIST test structures for RAM testing. NEC offers advanced packaging solutions including Tape Ball Grid Arrays (TBGA), Plastic Ball Grid Arrays (PBGA), Fine Pitch Ball Grid Arrays (FPBGA), Chip Size Packages (CSP), Plastic Quad Flat Packages (PQFP), Low Profile Plastic Quad Flat Packages (LQFP), Thin Plastic Quad Flat Packages (TQFP), and Pin Grid Arrays (PGA). Please call your local NEC ASIC Design Center for a listing of available master/package combinations. three features to control clock skew: the standard Digital PLL (DPLL) working at frequencies up to 100 MHz for chipto-chip skew minimization, the multiplying digital PLL providing frequencies up to 200 MHz, and Clock Tree Synthesis (CTS). CTS -- supported by an NEC proprietary design tool -- is used for clock skew management through the automatic insertion of a balanced buffer tree. The clock tree insertion method minimizes large-capacitive trunks and is especially useful with the hierarchical, synthesized design style being used for high-integration devices. RC values for actual net lengths of the clock tree are used for back annotation after place and route operations. A skew as low as 100 ps can be achieved. Accurate Design Verification. Nonlinear timing calculation is a very important requirement of the high-density, deep sub-micron ASIC designs. NEC makes use of the increased accuracy delivered by the nonlinear table look-up delay calculation methodology and offers consistent wire load models to ensure a high accuracy of the design verification. Design Rule Check. A comprehensive design rule check (DRC) program reports design rule violations as well as chip utilization statistics for the design netlist. The generated report contains such information as net counts, total pin and gate counts, and utilization figures. Layout. During design synthesis, wire load models are used to get delay estimations in a very early state of the design flow. In general, there's no need for customers to perform the floorplanning to meet the required timing. During layout, enhanced in-place optimization (IPO) features of the layout tools and engineering change order (ECO) capabilities of the synthesis tools are used to optimize critical timing paths defined by the given timing constraints. This feature can reduce the total design time. CAD Support The CMOS-9HD family is fully supported by NEC's sophisticated OpenCAD design framework,CMOS-9HD maximizes design quality and flexibility while minimizing ASIC design time. NEC's OpenCAD system allows designers to combine the EDA industry's most popular third-party design tools with proprietary NEC tools, including those for advanced floorplanner, clock tree synthesis, automatic test pattern generation (ATPG), full-timing simulation, accelerated fault grading and advanced place and route algorithms. The latest OpenCAD system is open for sign-off using standard EDA tools. NEC offers RTL- and STA- (Static Timing Analysis) sign-off procedures to shorten the ASIC design cycle of high-complexity designs. Support of High-Speed Systems. High-speed systems require tight control of clock skew on the chip and between devices on a printed circuit board. CMOS-9HD provides Test Support The CMOS-9HD family supports automatic test generation through a scan test methodology. It includes internal scan, boundary scan (JTAG) and built-in-self-test (BIST) architecture for easy and high-performance production RAM testing. This allows higher fault coverage, easier testing and faster development time. Supplemental Publications This data sheet contains preliminary specifications and operational data for the CMOS-9HD gate array family. Additional information is available in NEC's CMOS-9HD Design Manual, Block Library, Memory Macro Design Manual and other related documents. Please call your local NEC design center for additional information; see the back of this data sheet for locations and telephone numbers. 3 CMOS-9HD Input/Output Capacitance Absolute Maximum Ratings Power supply voltage, VDD -0.5 to +4.6 V VDD = VI = 0 V; f = 1 MHz Terminal Symbol Min Max Unit Input 3V 5V CIN 2.2* 4.4* 3.3* 5.5* pF Output 3V 5V COUT 2.2* 4.4* 3.3* 5.5* pF I/O 3V 5V C I/O 2.2* 4.4* 3.3* 5.5* pF Input Voltage, VI 3V Input buffer (at VI < VDD + 0.5V) -0.5 to 4.6 V 3V Fail-safe input buffer (at VI < VDD + 0.5V) -0.5 to 4.6 V 5V Input buffer (at VI < VDD + 5.0V) -0.5 to 6.6 V Output Voltage, VO Typ 3V Output buffer (at VO < VDD + 0.5V) -0.5 to 4.6 V Notes: Values include package pin capacitance. *Estimated 5V TTL Output buffer (at VO < VDD + 3.0V) -0.5 to 6.6 V Power Consumption 5V CMOS Output buffer (at VO < VDD + 3.0V) -0.5 to 6.6 V Latch-up current, ILATCH >1 A (typ) Operating temperature, TOPT -40 to +85C Storage temperature, TSTG -65 to +150C Description Limits Unit Internal gate .65* W/MHz Input buffer (FI01) 4.03* W/MHz Output buffer (FO01 @ 15 pF) 140* W/MHz Caution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions. *Estimated Recommended Operating Conditions 3.3V Interface Block Parameter I/O Power supply voltage Symbol Min Max 5V Interface Block Min 5V PCI Level Max Min Max 3.3V PCI Level Min Max Unit V DD 3.0 3.6 3.0 3.6 3.0 3.6 3.0 3.6 V Junction temperature TJ -40 +125 -40 +125 -40 +125 -40 +125 C High-level input voltage VIH 2.0 V DD 2.0 5.5 2.0 V CC 0.5VCC V CC V Low-level input voltage VIL 0 0.8 0 0.8 0 0.8 0 0.3V CC V Positive trigger voltage VP 12 2.4 1.2 2.4 -- -- -- -- V Negative trigger voltage VN 0.6 1.8 .6 1.8 -- -- -- -- V Hysteresis voltage VH .3 1.5 .3 1.5 -- -- -- -- V Input rise/fall time tR , tF 0 1 0 1 0 1 0 1 ns Input rise/fall time, Schmitt tR, tF 0 1 0 1 -- -- -- -- ms AC Characteristics VDD = 3.3V 0.3V; Tj = -40 to +125C Parameter Symbol Toggle frequency (D-flip-flop) fTOG Delay time, 2-input NAND gate @ 5V Standard gate (F302) Power gate (F322) tPD tPD Min Typ Max Unit Conditions 670 MHz F/O = 2, 5V 94 ps F/O = 1; L = 0 mm 13.1 ps F/O = 1; L = .15 mm/pin pair 108 ps F/O = 2; L = 0 mm 107 ps F/O = 1; L = .15 mm/pin pair 94 ps F/O = 2; L = 0 mm Delay time, buffer Input buffer (FI01) tPD 229 ps F/O = 1; L = .15 mm/pin pair Input buffer (FI01) tPD 222 ps F/O = 2; L = 0 mm Output buffer (FO01) tPD 1.4 ns CL = 15 pF Output rise time (FO01) tR 2.39 ns CL = 15 pF Output fall time (FO01) tF 1.87 ns CL = 15 pF 4 CMOS-9HD DC Characteristics VDD = 3.3V 0.3V; Tj = -40 to +125C Parameter Quiescent current (PD654xx) (1) -19, -39 -17, -37, -15, -35, -13, -33, -11, -31 -10, -30, -09, -29, -08, -28 -06, -26, -07, -27 Off-state output leakage current 3V output buffer 5V-protected TTL buffer Output short circuit current (3) Input leakage current (2) Regular 50 k pull-up 5 k pull-up 50 k pull-down Resistor values 50 k pull-up (4) 5 k pull-up 50 k pull-down Low-level output current (5V Interface Block) 1 mA 2 mA 3 mA 6 mA 9 mA 12 mA High-level output current (5V Interface Block) 1 mA 2 mA 3 mA 6 mA 9 mA 12 mA Low-level output current (3.3V Interface Block) 3 mA (FO09) 6 mA (FO04) Symbol 9 mA (FO01) 12 mA (FO02) 18 mA (FO03) 24 mA (FO06) High-level output current (3.3V Interface Block) 3 mA (FO09) 6 mA (FO04) 9 mA (FO01) 12 mA (FO02) 18 mA (FO03) 24 mA (FO06) Low-level output voltage High-level output voltage IOL IOL IOL IOL Min IDDS I DDS I DDS IDDS Typ Max Unit 2.0 2.0 2.0 2.0 300 300 300 300 A A A A VI = VI = VI = VI = 10 10 -250 A A mA VO = VDD or GND VO = VDD or GND VO = GND VI = VDD or GND VI = GND VI = GND VI = VDD IOZ IOZ IOS Conditions VDD VDD VDD VDD or or or or II II II II 28 280 28 10-4 83 700 83 10 190 1900 190 A A A A Rpu Rpu Rpu 21.8 2.8 25.6 37.1 5.0 41.9 83.1 10.6 105.8 k k k IOL IOL IOL IOL IOL IOL 1 2 3 6 9 12 mA mA mA mA mA mA VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V IOH IOH IOH IOH IOH IOH -1 -1 -3 -3 -3 -3 mA mA mA mA mA mA VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V IOL IOL 3.0 TBD mA VOL = 0.4 V 6.0 9.0 12.0 18.0 24.0 TBD TBD TBD TBD TBD mA mA mA mA mA VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V mA mA mA mA mA mA V V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V IOL = 0 mA IOH = 0 mA IOH IOH IOH IOH IOH IOH VOL VOH Notes: (1) Static current consumption increases if an I/O block with on-chip pull-up/ pull-down resistor or an oscillator is used. Contact an NEC ASIC Design Center for assistance in calculation. -3 -6 -9 -12 -18 -24 0.1 VDD-0.1 GND GND GND GND (2) Leakage current is limited by tester capabilities. Specification listed represents this measurement limitation. Actual values will be significantly lower. (3) Rating is for only one output operating in this mode for less than 1 second. (4) Resistor is called 50k for backwards compatibility. 5 CMOS-9HD NEC ASIC DESIGN CENTERS WEST SOUTH CENTRAL/SOUTHEAST NORTH CENTRAL/NORTHEAST * 3033 Scott Boulevard Santa Clara, CA 95054 * Three Galleria Tower 13155 Noel Road, Suite 1100 Dallas, TX 75240 * The Meadows, 2nd Floor 161 Worcester Road Framingham, MA 01701 TEL 408-588-5008 FAX 408-588-5017 TEL 972-855-5150 FAX 972-503-3993 * One Embassy Centre 9020 S.W. Washington Square Road, Suite 400 Tigard, OR 97223 TEL 503-672-4500 FAX 503-641-7719 * Research Triangle Park 2000 Regency Parkway, Suite 455 Cary, NC 27511 TEL 919-380-6500 FAX 919-469-5926 TEL 508-935-2200 FAX 508-935-2234 * Greenspoint Tower 2800 W. Higgins Road, Suite 765 Hoffman Estates, IL 60195 TEL 708-519-3945 FAX 708-882-7564 For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782 or FAX your request to: 1-800-729-9288 NEC Electronics Inc. CORPORATE HEADQUARTERS 2880 Scott Boulevard P.O. Box 58062 Santa Clara, CA 95052 TEL 408-588-6000 6(c)1998 NEC Electronics Inc./Printed in U.S.A. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc. (NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY, WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding information set forth herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. "Standard" quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti-disaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliability requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death. If customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL's willingness to support a given application. Document No. A12811EU3V0DS00