FAN54005UCX - ON SEMICONDUCTOR

November, 2019 − Rev. 4

1Publication Order Number:

FAN54005/D

USB-Compliant Single-Cell

Li-Ion Switching Charger

with USB-OTG Boost for

200 mA to 1.45 A Systems

FAN54005

Description

The FAN54005 is a highly integrated switch−mode

charger, configurable for 200 mA to 1.45 A systems using

a single external resistor.

The charging parameters and operating modes are program−

mable through an I2C Interface that operates up to 3.4 Mbps.

The charger and boost regulator circuits switch at 3 MHz

to minimize the size of external passive components.

The FAN54005 provides battery charging in three phases:

conditioning, constant current and constant voltage.

To ensure USB compliance and minimize charging time, the

input current limit can be changed through the I2C interface

by the host processor. Charge termination is determined by

a programmable minimum current level. A safety timer with

reset control provides a safety backup for the I2C host.

Charge status is reported to the host through the I2C port.

The integrated circuit (IC) automatically restarts the charge

cycle when the battery falls below an internal threshold. If

the input source is removed, the IC enters a high−impedance

mode, preventing leakage from the battery to the input.

Charge current is reduced when the die temperature reaches

120°C, protecting the device and PCB from damage.

The FAN54005 can operate as a boost regulator on

command from the system. The boost regulator includes a

soft−start that limits inrush current from the battery and uses

the same external components used for charging the battery.

Features

•Fully Integrated, High−Efficiency Charger for

Single−Cell Li−Ion and Li−Polymer Battery Packs

•Charge Voltage Accuracy: ±0.5% at 25°C

Charge Voltage Accuracy: ±1% from 0 to 125°C

•Supports 200 mA to 1.45 A Systems

95% Efficiency for 200 mA−Hour Batteries

94% Efficiency for 500 mA−Hour Batteries

90% Efficiency for 1.0 A−Hour Batteries

•±5% Input Current Regulation Accuracy

•±5% Charge Current Regulation Accuracy

•20 V Absolute Maximum Input Voltage

•6 V Maximum Input Operating Voltage

•Charge Parameters Programmable through High−Speed

I2C Interface (3.4 Mb/s) with Fast Mode Plus

Compatibility

♦Input Current

♦Fast−Charge / Termination Current

♦Charger Voltage

♦Termination Enable

•3 MHz Synchronous Buck PWM Controller with Wide

Duty Cycle Range

•Small Footprint 1 mH External Inductor

•Safety Timer with Reset Control

•1.8 V Regulated Output from VBUS for Auxiliary Circuits

•Dynamic Input Voltage Control Automatically Reduces

Charging Current with Weak Input Sources

•Low Reverse Leakage to Prevent Battery Drain to VBUS

•5 V, 500 mA Boost Mode for USB OTG for 3.0 V to

4.5 V Battery Input

•Available in a 1.96 x 1.87 mm, 20−bump, 0.4 mm Pitch

WLCSP Package

Applications

•Wireless Speakers, Headphones

•Cell Phones, Gaming Devices

•Toys, Drones, Digital Cameras

•IoT Devices

•E−Cigs, Vapes

ORDERING INFORMATION

Part Number Temperature Range Package PN Bits: IC_INFO[4:2] Packing

†

FAN54005UCX −40°C to +85°C20−Bump, Wafer−Level Chip−Scale Package

(WLCSP), 0.4 mm Pitch, 1.96 x 1.87 mm

101 Tape and Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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WLCSP

20 BALL

CASE 567SL

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Figure 1. Typical Application

FAN54005

COUT

VBAT

+Battery

CSIN

RSNS

1mH

CBAT

SYSTEM

LOAD

0.1mF

1mF

4.7mF

SDA

SCL

OTG/USB# CREG

1mF

VREG

STAT

10 mF

DISABLE

CBUS

CMID

VBUS

PMID

Block Diagram

Figure 2. IC and System Block Diagram

PWM

MODULATOR

PMID

CMID

CSIN

1mH

4.7mF

VREF

SDA

SCL

OTG

VBUS

CBUS

1mF

STAT

I2C

INTERFACE

LOGIC

AND

CONTROL

PMID

OSC

30 mA

CHARGE

PUMP

VBUS

OVP

I_IN

CONTROL

VREG

CREG

1mF

DAC

DISABLE

1.8V / PMID REG

Q1B

Q1A

Battery

RSNS

CBAT

SYSTEM

LOAD

10 mF

COUT

0.1mF

PGND

CSYS_DISTRIBUTED

47mF

PMID Q1A

> VBAT

< VBAT

OFF

Q1B

OFF

Table 1. RECOMMENDED EXTERNAL COMPONENTS

Component Description Vendor Parameter Typ Unit

L1 1 mH ±20%, 4.0 A, 33 mW, 2016 Semco CIGT201610EH1R0M L 1.0 mH

CBAT 10 mF, 20%, 6.3 V, X5R, 0603 Murata: GRM188R60J106M

TDK: C1608X5R0J106M

C 10 mF

CMID 4.7 mF, 10%, 10 V, X5R, 0603 Murata: GRM188R61A475K

TDK: C1608X5R1A475K

C (Note 1) 4.7 mF

CBUS 1.0 mF, 10%, 25 V, X5R, 0603 Murata: GRM188R61E105K

TDK: C1608X5R1E105M

C 1.0 mF

CREG 1.0 mF, 10%, 10 V, X5R, 0402 Murata: GRM155R61A105K

TDK: C1005X5R1A105K

C 1.0 mF

COUT 0.1 mF, 10%, 16 V, X7R, 0402 Murata: GRM155R71C104K

TDK: C1005X7R1C104K

C 0.1 mF

CSYS_DISTRIBUTED (Note 2) n/a n/a C 47 mF

1. A 10 V rating is sufficient for CMID because PMID is protected from over−voltage surges on VBUS by Q3 (Figure 2).

2. A minimum 47 mF of distributed capacitance on SYS is required for proper operation of the FAN54005.

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Pin Configuration

A1 A2

Top View

D1 D3D2

E1 E3E2 E4

A3 A2

D1D3 D2

E1E3 E2E4

Bottom View

Figure 3. WLCSP−20 Pin Assignments

Table 2. PIN DEFINITIONS

Pin # Name Description

A1, A2 VBUS Charger Input Voltage and USB−OTG output voltage. Bypass with a 1 mF capacitor to PGND.

A3 NC No Connect. No external connection is made between this pin and the IC’s internal circuitry.

A4 SCL I

C Interface Serial Clock. This pin should not be left floating.

B1−B3 PMID Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and

high−voltage input switch. Bypass with a minimum of 4.7 mF, 6.3 V capacitor to PGND.

B4 SDA I

C Interface Serial Data. This pin should not be left floating.

C1−C3 SW Switching Node. Connect to output inductor.

C4 STAT Status. Open−drain output indicating charge status. The IC pulls this pin LOW when charging.

D1−D3 PGND Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom

of CMID should be as short as possible.

D4 OTG On−The−Go. On VBUS Power−On Reset (POR), this pin sets the input current limit for t15MIN charging. Also,

the OTG pin enables the boost regulator in conjunction with OTG_EN and OTG_PL bits (See Table 21)

E1 CSIN Current−Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to

sense current into the battery. Bypass this pin close to RSNS with a 0.1 mF capacitor to PGND.

E2 DISABLE Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the I

C regis-

ters. When this pin is HIGH, the 15−minute timer is reset. This pin does not affect the 32−second timer.

E3 VREG Regulator Output. Connect to a 1 mF capacitor to PGND. This pin provides regulated 1.8 V and can supply

up to 2 mA of DC load current.

E4 VBAT Battery Voltage. Connect to the positive (+) terminal of the battery pack and close to RSNS.

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Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Unit

VBUS VBUS Voltage Continuous −0.7 20.0 V

Pulsed, 100 ms Maximum Non−Repetitive −1.0

VSTAT STAT Voltage −0.3 16.0 V

VIPMID Voltage 7.0 V

SW, CSIN, VBAT, DISABLE Voltage −0.3 (Note 3) 7.0

VOVoltage on Other Pins −0.3 6.5 (Note 4) V

dVBUS / dt Maximum VBUS Slope above 5.5 V when Boost or Charger are Active 4V/ms

−dVBUS / dt Negative VBUS Slew Rate during VBUS Short Circuit,

CMID ≤ 4.7 mF (See VBUS Short While Charging)

TA ≤ 60°C 4 V/ms

TA ≥ 60°C 2

ESD Electrostatic Discharge Protection Level Human Body Model

per JESD22−A114

2000 V

Charged Device Model

per JESD22−C101

1000

TJJunction Temperature −40 +150 °C

TSTG Storage Temperature −65 +150 °C

TLLead Soldering Temperature, 10 Seconds +260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

3. SW only: Switching transients of −0.7 V, minimum, with duration <20 nsec, are acceptable.

4. Lesser of 6.5 V or VI + 0.3 V

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VBUS Supply Voltage 4 6 V

VBAT(MAX) Maximum Battery Voltage when Boost enabled 4.5 V

TAAmbient Temperature −30 +85 °C

TJJunction Temperature (See Thermal Regulation and Protection section) −30 +120 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 5. THERMAL PROPERTIES

Symbol Parameter Typical Unit

qJA Junction−to−Ambient Thermal Resistance 60 °C/W

qJB Junction−to−PCB Thermal Resistance 20 °C/W

NOTE: Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p

boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a

given ambient temperature TA. For measured data, see Thermal Regulation and Protection.

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Table 6. ELECTRICAL SPECIFICATIONS

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;

VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C.

Symbol Parameter Conditions Min Typ Max Unit

POWER SUPPLIES

IVBUS VBUS Current VBUS > VIN(MIN)1, PWM Switching 10 mA

VBUS > VIN(MIN)1; PWM Enabled,

Not Switching (Battery OVP Condition);

I_IN Setting = 100 mA

2.5 mA

0°C < TJ < 85°C, HZ_MODE = 1, 32S Mode 63 90 mA

ILKG VBAT to VBUS Leakage Current 0°C < TJ < 85°C, HZ_MODE = 1,

VBAT = 4.2 V, VBUS = 0 V

0.2 5.0 mA

IBAT Battery Discharge Current in High−

Impedance Mode

0°C < TJ < 85°C, HZ_MODE = 1,

VBAT = 4.2 V

10 mA

DISABLE = 1, 0°C < TJ < 85°C,

VBAT = 4.2 V

CHARGER VOLTAGE REGULATION

VOREG Charge Voltage Range 3.5 4.4 V

Charge Voltage Accuracy TA = 25°C−0.5% +0.5%

TJ = 0 to 125°C−1% +1%

CHARGING CURRENT REGULATION

IOCHARGE Output Charge Current Range VSHORT < VBAT < VOREG,

68 < RSNS < 180 mW

200 1450 mA

Charge Current Accuracy Across

RSNS

20 mV ≤ [VCSIN – VBAT ] ≤ 40 mV 92 97 102 %

[VCSIN – VBAT ] > 40 mV 94 97 100 %

WEAK BATTERY DETECTION

VLOWV Weak Battery Threshold Range 3.4 3.7 V

Weak Battery Threshold Accuracy −5 +5 %

Weak Battery Deglitch Time Rising Voltage 30 ms

LOGIC LEVELS: DISABLE, SDA, SCL, OTG

VIH High−Level Input Voltage 1.05 V

VIL Low−Level Input Voltage 0.4 V

IIN Input Bias Current Input Tied to GND or VBUS 0.01 1.00 mA

CHARGE TERMINATION DETECTION

ITERM Termination Current Range VBAT > VOREG – VRCH,

68 < RSNS < 180 mW

20 400 mA

Termination Current Accuracy [VCSIN – VBAT ] from 3 mV to 20 mV −25 +25 %

[VCSIN – VBAT ] from 20 mV to 40 mV −5 +5

Termination Current Deglitch Time 30 ms

1.8 V LINEAR REGULATOR

VREG 1.8 V Regulator Output IREG from 0 to 2 mA 1.7 1.8 1.9 V

INPUT POWER SOURCE DETECTION

VIN(MIN)1 VBUS Input Voltage Rising To Initiate and Pass VBUS Validation 4.29 4.42 V

VIN(MIN)2 Minimum VBUS During Charge During Charging 3.71 3.94 V

tVBUS_VALID VBUS Validation Time 30 ms

DYNAMIC INPUT VOLTAGE CONTROL (VBUS)

VSP DIVC Accuracy −3 +3 %

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Table 6. ELECTRICAL SPECIFICATIONS

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;

VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C.

Symbol UnitMaxTypMinConditionsParameter

INPUT CURRENT LIMIT

IINLIM Input Current Limit Threshold IINLIM Set to 100 mA 88 93 98 mA

IINLIM Set to 500 mA 450 475 500

BATTERY RECHARGE THRESHOLD

VRCH Recharge Threshold Below VOREG 100 120 150 mV

Deglitch Time VBAT Falling Below VRCH Threshold 130 ms

STAT OUTPUT

VSTAT(OL) STAT Output Low ISTAT = 10 mA 0.4 V

ISTAT(OH) STAT High Leakage Current VSTAT = 5 V 1mA

BATTERY DETECTION

IDETECT Battery Detection Current before

Charge Done (Sink Current) (Note 5)

Begins after Termination Detected and

VBAT ≤ VOREG –VRCH

−0.80 mA

tDETECT Battery Detection Time 262 ms

SLEEP COMPARATOR

VSLP Sleep−Mode Entry Threshold,

VBUS – VBAT

2.3 V ≤ VBAT ≤ VOREG, VBUS Falling 0 0.04 0.10 V

tSLP_EXIT Deglitch Time for VBUS Rising

Above VBAT by VSLP

Rising Voltage 30 ms

POWER SWITCHES (See Figure 2)

RDS(ON) Q3 On Resistance (VBUS to PMID) IINLIM = 500 mA 180 250 mW

Q1 On Resistance (PMID to SW) 130 225

Q2 On Resistance (SW to GND) 150 225

CHARGER PWM MODULATOR

fSW Oscillator Frequency 2.7 3.0 3.3 MHz

DMAX Maximum Duty Cycle 100 %

DMIN Minimum Duty Cycle 0 %

ISYNC Synchronous to Non−Synchronous

Current Cut−Off Threshold (Note 6)

Low−Side MOSFET (Q2) Cycle−by−Cycle

Current Limit

140 mA

BOOST MODE OPERATION (OPA_MODE = 1, HZ_MODE = 0)

VBOOST Boost Output Voltage at VBUS 2.5 V < VBAT < 4.5 V, ILOAD from 0 to 200 mA 4.80 5.07 5.17 V

3.0 V < VBAT < 4.5 V, ILOAD from 0 to 500 mA 4.77 5.07 5.17

IBAT(BOOST) Boost Mode Quiescent Current PFM Mode, VBAT = 3.6 V, IOUT = 0 140 300 mA

ILIMPK(BST) Q2 Peak Current Limit 1440 1700 1960 mA

UVLOBST Minimum Battery Voltage for Boost

Operation

While Boost Active 2.30 V

To Start Boost Regulator 2.50 2.70

VBUS LOAD RESISTANCE

RVBUS VBUS to PGND Resistance Normal Operation 1500 kW

Charger Validation 100 W

PROTECTION AND TIMERS

VBUSOVP VBUS Over−Voltage Shutdown VBUS Rising 6.09 6.29 6.49 V

Hysteresis VBUS Falling 100 mV

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Table 6. ELECTRICAL SPECIFICATIONS

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;

VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C.

Symbol UnitMaxTypMinConditionsParameter

PROTECTION AND TIMERS

ILIMPK(CHG) Q1 Cycle−by−Cycle Peak Current

Limit

Charge Mode 2.3 A

VSHORT Battery Short−Circuit Threshold VBAT Rising 1.95 2.00 2.05 V

Hysteresis VBAT Falling 100 mV

ISHORT Linear Charging Current VBAT < VSHORT 20 30 40 mA

TSHUTDWN Thermal Shutdown Threshold

(Note 7)

TJ Rising 145 °C

Hysteresis (Note 7) TJ Falling 10

TCF Thermal Regulation Threshold

(Note 7)

Charge Current Reduction Begins 120 °C

tINT Detection Interval 2.1 s

t32S 32−Second Timer (Note 8) Charger Enabled 20.5 25.2 28.0 s

Charger Disabled 18.0 25.2 34.0

t15MIN 15−Minute Timer 15−Minute Mode 12.0 13.5 15.0 min

DtLF Low−Frequency Timer Accuracy Charger Inactive −25 25 %

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Negative current is current flowing from the battery to GND (discharging the battery).

6. Q2 always turns on for 60 ns, then turns off if current is below ISYNC.

7. Guaranteed by design; not tested in production.

8. This tolerance (%) applies to all timers on the IC, including soft−start and deglitching timers.

Table 7. I

C TIMING SPECIFICATIONS Guaranteed by design, VBAT ≥ 2.5 V if valid VBUS not present.

Symbol Parameter Conditions Min Typ Max Unit

fSCL SCL Clock Frequency Standard Mode 100 kHz

Fast Mode 400

High−Speed Mode, CB ≤ 100 pF 3400

High−Speed Mode, CB ≤ 400 pF 1700

tBUF Bus−Free Time between STOP and

START Conditions

Standard Mode 4.7 ms

Fast Mode 1.3

tHD;STA START or Repeated START Hold

Time

Standard Mode 4ms

Fast Mode 600 ns

High−Speed Mode 160 ns

tLOW SCL LOW Period Standard Mode 4.7 ms

Fast Mode 1.3 ms

High−Speed Mode, CB ≤ 100 pF 160 ns

High−Speed Mode, CB ≤ 400 pF 320 ns

tHIGH SCL HIGH Period Standard Mode 4ms

Fast Mode 600 ns

High−Speed Mode, CB ≤ 100 pF 60 ns

High−Speed Mode, CB ≤ 400 pF 120 ns

tSU;STA Repeated START Setup Time Standard Mode 4.7 ms

Fast Mode 600 ns

High−Speed Mode 160 ns

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Table 7. I2C TIMING SPECIFICATIONS Guaranteed by design, VBAT ≥ 2.5 V if valid VBUS not present.

Symbol UnitMaxTypMinConditionsParameter

tSU;DAT Data Setup Time Standard Mode 250 ns

Fast Mode 100

High−Speed Mode 10

tHD;DAT Data Hold Time Standard Mode 0 3.45 ms

Fast Mode 0 900 ns

High−Speed Mode, CB ≤ 100 pF 0 70 ns

High−Speed Mode, CB ≤ 400 pF 0 150 ns

tRCL SCL Rise Time Standard Mode 20+0.1CB1000 ns

Fast Mode 20+0.1CB300

High−Speed Mode, CB ≤ 100 pF 10 80

High−Speed Mode, CB ≤ 400 pF 20 160

tFCL SCL Fall Time Standard Mode 20+0.1CB300 ns

Fast Mode 20+0.1CB300

High−Speed Mode, CB ≤ 100 pF 10 40

High−Speed Mode, CB ≤ 400 pF 20 80

tRDA

tRCL1

SDA Rise Time

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

Standard Mode 20+0.1CB1000 ns

Fast Mode 20+0.1CB300

High−Speed Mode, CB ≤ 100 pF 10 80

High−Speed Mode, CB ≤ 400 pF 20 160

tFDA SDA Fall Time Standard Mode 20+0.1CB300 ns

Fast Mode 20+0.1CB300

High−Speed Mode, CB ≤ 100 pF 10 80

High−Speed Mode, CB ≤ 400 pF 20 160

tSU;STO Stop Condition Setup Time Standard Mode 4ms

Fast Mode 600 ns

High−Speed Mode 160 ns

CBCapacitive Load for SDA, SCL 400 pF

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Timing Diagrams

ÑÑ

ÓÓ

START

ÔÔÔ

ÖÖ

ÒÒÒÒ

REPEATED

START

ÕÕÕ

SCL

SDA

tHD;STA

tLOW

tHD;DAT

tHIGH

TSU;DAT

tSU;STA

tHD;STO

tBUF

ŠŠŠ

START

ÚÚÚ

STOP

tHD;STA

Figure 4. I2C Interface Timing for Fast and Slow Modes

ÛÛ

ÜÜÜÜ

REPEATED

START

ÙÙ

SCLH

SDAH

tFDA

tLOW

tRCL1

tHD;DAT

tHIGH

tSU;STO

ŸŸŸ

REPEATED

START

tRDA

tFCL

tSU;DAT

tRCL

ŽŽŽ

STOP

¦¦

= MCS Current Source Pull−up

= RP Resistor Pull−up

note A

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

tHD;STA

tSU;STA

Figure 5. I2C Interface Timing for High−Speed Mode

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Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C.

84%

86%

88%

90%

92%

94%

2.5 3.0 3.5 4.0 4.5

Battery Voltage, VBAT (V)

4.7 VBUS

5.0 VBUS

5.5 VBUS

100

120

140

160

180

2.5 3.0 3.5 4.0 4.5

Battery Voltage, VBAT (V)

5.5 VBUS

5.0 VBUS

4.7 VBUS

300

400

500

600

700

800

900

2.5 3.0 3.5 4.0 4.5

Battery Voltage, VBAT (V)

5.5 VBUS

5.0 VBUS

4.7 VBUS

82%

85%

88%

91%

94%

97%

100 300 500 700 900 1100 1300 1500

Battery Charge Current (mA)

4.3 VBAT, 5.0 VBUS

3.8 VBAT, 5.0 VBUS

4.3 VBAT, 5.5 VBUS

3.8 VBAT, 5.5 VBUS

Figure 6. Battery Charge Current vs. VBUS with

IINLIM=100 mA, VOREG=4.35V

Figure 7. Battery Charge Current vs. VBUS with

IINLIM=500 mA, VOREG=4.35V

Figure 8. Charger Efficiency, No

IINLIM,IOCHARGE=1450 mA

Figure 9. Charger Efficiency vs. VBUS,

IINLIM=500 mA, VOREG=4.35

Figure 10. Auto−Charge Startup at VBUS Plug−in,

OTG=0, VBAT=3.4 V

Figure 11. Auto−Charge Startup at VBUS Plug−in,

OTG=1, VBAT=3.4 V

Battery Charge Current (mA)

Efficiency

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Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C.

100

150

200

250

4.0 4.5 5.0 5.5 6.0

Input Voltage, VBUS

−30C

+25C

+85C

Figure 12. Auto−Charge Startup with 300 mA

Limited Charger / Adaptor, OTG=1, VBAT=3.4 V

Figure 13. Charger Startup with HZ_MODE Bit

Reset, IINLIM=500 mA, IOCHARGE=1050 mA,

VOREG=4.2 V, VBAT=3.6 V

Figure 14. Battery Removal / Insertion During

Charging, VBAT=3.9 V, IOCHARGE=1050 mA, No

IINLIM, TE=0

Figure 15. Battery Removal / Insertion During

Charging, VBAT=3.9 V, IOCHARGE=1050 mA, No

IINLIM, TE=1

Figure 16. VBUS Current in High−Impedance Mode

with Battery Open

Figure 17. VREG 1.8 V Output Regulation

High−Z Mode Input Current (mA)

1.77

1.78

1.79

1.80

1.81

1.82

VREG (V)

1.8V Regulator Load Current (mA)

−30C, 5.0 VBUS

+25C, 5.0 VBUS

+85C, 5.0 VBUS

12345

(V)

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Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C.

2.5 3.0 3.5 4.0 4.5

Battery Voltage, VBAT (V)

VBUS open,

SDA=SCL=0V

VBUS open,

SDA=SCL=1.8V

VBUS=5.0V,

SDA=SCL=0V,

DIS or HZ=1

2.5 3.0 3.5 4.0 4.5

Battery Voltage, V

BAT (V)

−30C

+25C

+85C

Figure 18. No Battery, TE=0, VBUS Power Up Figure 19. Sleep Mode Battery Discharge Current,

SDA=SCL=0 V, VBUS Open

Figure 20. Battery Discharge Current vs. Mode

Sleep Mode Battery Current (mA)

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Boost Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VBAT = 3.6 V, and TA = 25°C.

100

150

200

250

300

2.5 3.0 3.5 4.0 4.5

Battery Voltage, VBAT (V)

+25C

+85C

4.85

4.90

4.95

5.00

5.05

5.10

5.15

0 100 200 300 400 500

VBUS Load Current (mA)

−30C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

4.85

4.90

4.95

5.00

5.05

5.10

5.15

0 100 200 300 400 500

VBUS Load Current (mA)

3.0 VBAT

3.6 VBAT

4.2 VBAT

100

0 100 200 300 400 500

VBUS Load Current (mA)

−30C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

100

0 100 200 300 400 500

VBUS Load Current (mA)

3.0 VBAT

3.6 VBAT

4.2 VBAT

Figure 21. Efficiency vs. VBAT Figure 22. Efficiency Over−Temperature

Figure 23. Output Regulation vs. VBAT Figure 24. Output Regulation Over−Temperature

Figure 25. Quiescent Current

Efficiency (%)

VBUS (V)

Quiescent Current (mA)

−30C

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Boost Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VBAT = 3.6 V, and TA = 25°C.

0 100 200 300 400 500

VBUS Load Current (mA)

−30C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

0 100 200 300 400 500

VBUS Load Current (mA)

3.0 VBAT

3.6 VBAT

4.2 VBAT

Figure 26. Boost PWM Waveform Figure 27. Boost PFM Waveform

Figure 28. Output Ripple vs. VBAT Figure 29. Output Ripple vs. Temperature

Figure 30. Startup, 3.6 VBAT

, 44 W Load, Additional

10 mF, X5R Across VBUS

Figure 31. VBUS Fault Response, 3.6 VBAT

VBUS Ripple (mVpp)

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Boost Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VBAT = 3.6 V, and TA = 25°C.

Figure 32. Load Transient, 5−155−5 mA, tR=tF=100 ns Figure 33. Load Transient, 5−255−5 mA, tR=tF=100 ns

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Circuit Description / Overview

When charging batteries with a current−limited input source,

such as USB, a switching charger’s high efficiency over a

wide range of output voltages minimizes charging time.

The FAN54005 combines a highly integrated

synchronous buck regulator for charging with a

synchronous boost regulator, which can supply 5 V to USB

On−The−Go (OTG) peripherals. The FAN54005 employs

synchronous rectification for both the charger and boost

regulators to maintain high efficiency over a wide range of

battery voltages and charge states.

The FAN54005 has three operating modes:

1. Charge Mode: Charges a single−cell Li−ion or

Li−polymer battery.

2. Boost Mode: Provides 5 V power to USB−OTG

with an integrated synchronous rectification boost

regulator using the battery as input.

3. High−Impedance Mode: Both the boost and

charging circuits are OFF in this mode. Current

flow from VBUS to the battery or from the battery

to VBUS is blocked in this mode. This mode

consumes very little current from VBUS or the

battery.

Charge Mode and Registers

Note: Default settings are denoted by bold typeface.

Charge Mode

In Charge Mode, FAN54005 employs four regulation loops:

1. Input Current: Limits the amount of current drawn

from VBUS. This current is sensed internally and

can be programmed through the I2C interface.

2. Charging Current: Limits the maximum charging

current, which is sensed using an external RSNS.

Choose RSNS to provide the desired IOCHARGE and

ITERM currents for your system, relative to the

VRSNS levels determined by the IOCHARGE and

ITERM register settings, as shown in Table 4 and

Table 5, respectively.

3. Charge Voltage: The regulator is restricted from

exceeding this voltage. As the internal battery

voltage rises, the battery’s internal impedance and

RSNS work in conjunction with the charge voltage

regulation to decrease the amount of current

flowing to the battery. Battery charging is

completed when the voltage across RSNS drops

below the threshold determined by ITERM.

4. Temperature: If the IC’s junction temperature

reaches 120°C, charge current is reduced until the

IC’s temperature stabilizes at 120°C.

5. Dynamic Input Voltage Control (DIVC) limits the

amount of drop on VBUS to a programmable

voltage (VSP) to accommodate incompatible

adapters that limit current to a lower current than

might be available from a “normal” USB adapter.

Battery Charging Curve

If the battery voltage is below VSHORT, a linear current

source pre−charges the battery until VBAT reaches VSHORT.

The PWM charging circuit is then started and the battery is

charged with a constant current if sufficient input power is

available. The current slew rate is limited to prevent

overshoot.

During the current regulation phase of charging, IINLIM or

the programmed charging current limits the amount of

current available to charge the battery and power the system.

The effect of IINLIM on IOCHARGE can be seen in Figure 35.

VOREG

ISHORT

ICHARGE

PRE−

CHARGE

CONSTANT CURRENT

(CC)

CONSTANT

VOLTAGE (CV)

VSHORT

ITERM

ISHORT

VSHORT

VOREG

Figure 34. Charge Curve, IOCHARGE Not Limited by

IINLIM

VOREG

ISHORT

PRE−

CHARGE

CURRENT REGULATION VOLTAGE

REGULATION

VSHORT

ITERM

Figure 35. Charge Curve, IINLIM Limits IOCHARGE

Assuming that VOREG is programmed to the cell’s fully

charged “float” voltage, the current that the battery accepts

with the PWM regulator limiting its output (sensed at

VBAT) to VOREG declines, and the charger enters the

voltage regulation phase of charging. When the current

declines to the programmed ITERM value, the charge cycle

is complete. Charge current termination can be disabled by

resetting the TE bit (REG 01[3]).

The charger output or “float” voltage can be programmed

by the OREG bits from 3.5 V to 4.44 V in 20 mV increments

as shown in Table 8.

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Table 8. OREG BITS (REG 02[7:2]) vs. CHARGER

VOUT (VOREG) FLOAT VOLTAGE

Decimal Hex VOREG Decimal Hex VOREG

OREG

0 00 3.50 32 20 4.14

1 01 3.52 33 21 4.16

2 02 3.54 34 22 4.18

3 03 3.56 35 23 4.20

4 04 3.58 36 24 4.22

5 05 3.60 37 25 4.24

6 06 3.62 38 26 4.26

7 07 3.64 39 27 4.28

8 08 3.66 40 28 4.30

9 09 3.68 41 29 4.32

10 0A 3.70 42 2A 4.34

11 0B 3.72 43 2B 4.36

12 0C 3.74 44 2C 4.38

13 0D 3.76 45 2D 4.40

14 0E 3.78 46 2E 4.42

15 0F 3.80 47 2F 4.44

16 10 3.82 48 30 4.44

17 11 3.84 49 31 4.44

18 12 3.86 50 32 4.44

19 13 3.88 51 33 4.44

20 14 3.90 52 34 4.44

21 15 3.92 53 35 4.44

22 16 3.94 54 36 4.44

23 17 3.96 55 37 4.44

24 18 3.98 56 38 4.44

25 19 4.00 57 39 4.44

26 1A 4.02 58 3A 4.44

27 1B 4.04 59 3B 4.44

28 1C 4.06 60 3C 4.44

29 1D 4.08 61 3D 4.44

30 1E 4.10 62 3E 4.44

31 1F 4.12 63 3F 4.44

The following charging parameters can be programmed by

the host through I2C:

Table 9. PROGRAMMABLE CHARGING PARAMETERS

Parameter Name Register

Output Voltage Regulation VOREG REG 02[7:2]

Battery Charging Current Limit IOCHARGE REG 04[6:4]

Input Current Limit IINLIM REG 01[7:6]

Charge Termination Limit ITERM REG 04[2:0]

Weak Battery Voltage VLOWV REG 01[5:4]

A new charge cycle begins when one of the following

occurs:

•The battery voltage falls below VOREG – VRCH

•VBUS Power on Reset (POR)

•CE or HZ_MODE is reset through I2C write to

CONTROL1 (REG 01) register.

Charge Current Limit (IOCHARGE)

Charge current limit is established by regulating the

voltage across RSNS (VRSNS) to the value controlled by the

IOCHARGE bits. Select RSNS in the range of 68 mW < RSNS

< 180 mW.

Charge current is further limited by the IO_LEVEL (Reg

05[5]) bit by default (IO_LEVEL=1). When IOLEVEL=1,

the voltage across RSNS is limited to 34.0 mV. When

IO_LEVEL=0 charge current is limited by the IOCHARGE

bits.

Table 10. IOCHARGE CURRENT AS FUNCTION OF

IOCHARGE (REG 04 [6:4]) BITS AND RSNS VALUE

Decimal HEX VRSNS (mV)

IOCHARGE Range (mA)

180 mW68 mW

IOCHARGE

0 00 37.4 208 550

1 01 44.2 246 650

2 02 51.0 283 750

3 03 57.8 321 850

4 04 71.4 397 1050

5 05 78.2 434 1150

6 06 91.8 510 1350

7 07 98.6 548 1450

Termination Current Limit

Current charge termination is enabled when TE (REG

01[3])=1.

Table 11. ITERM CURRENT AS FUNCTION OF ITERM

BITS (REG 04[2:0]) AND RSNS RESISTOR VALUES

Decimal HEX VRSNS (mV)

ITERM Range (mA)

180 mW68 mW

ITERM

0 00 3.3 18 49

1 01 6.6 37 97

2 02 9.9 55 146

3 03 13.2 73 194

4 04 16.5 92 243

5 05 19.8 110 291

6 06 23.1 128 340

7 07 26.4 147 388

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When the charge current falls below ITERM, PWM

charging stops and the STAT bits change to READY (00) for

about 500 ms while the IC determines whether the battery

and charging source are still connected. STAT then changes

to CHARGE DONE (10), provided the battery and charger

are still connected.

PWM Controller in Charge Mode

The IC uses a current−mode PWM controller to regulate

the output voltage and battery charge currents. The

synchronous rectifier (Q2) has a current limit that switches

off the FET when the current is more negative than ISYNC.

Charger Operation

VBUS Plug In

When the IC detects that VBUS has risen above VIN(MIN)1

(4.4 V), the IC applies a 100 W load from VBUS to GND. To

clear the VBUS Power−On−Reset (POR) and begin

charging, VBUS must remain above VIN(MIN)1 and below

VBUSOVP for tVBUS_VALID (30 ms) before the IC initiates

charging.

The VBUS validation sequence always occurs before

charging is initiated or re−initiated (for example, after a

VBUS OVP fault or a VRCH recharge initiation).

TVBUS_VALID ensures that unfiltered 50 / 60 Hz chargers

and other non−compliant chargers are rejected.

Safety Timer

Section references Figure 39.

At the beginning of charging, the IC starts a 15−minute

timer (t15MIN). When this times out, charging is terminated.

Writing to any register through I2C stops and resets the

t15MIN timer, which in turn starts a 32−second timer (t32S).

Setting the TMR_RST bit (REG 00[7]) resets the t32S timer.

If the t32S timer times out; charging is terminated, all

registers (except Safety) are set to their default values, the

FAULT bits are set to 110, STAT is pulsed HIGH and returns

LOW, and charging resumes using the default values with

the t15MIN timer running.

Normal charging is controlled by the host with the t32S

timer running to ensure that the host is alive. Charging with

the t15MIN timer running is used for charging that is

unattended by the host. If the t15MIN timer expires; the IC

turns off the charger, sets the CE bit, and indicates a timer

fault (110) on the FAULT bits (REG 00[2:0]). This sequence

prevents overcharge if the host fails to reset the t32S timer.

USB−Friendly Boot Sequence

At VBUS POR, the IC operates in accordance with its I2C

Safety, and the TMR_RST bit), typically due to an absence

of host communication, the chargers input current limit is

controlled by the OTG pin (100 mA if OTG is LOW and

500 mA if OTG is HIGH).

Once the host processor begins writing to the IC, charging

parameters are set by the host, which must continually reset

the t32S timer to continue charging using the programmed

charging parameters.

Input Current Limiting

To minimize charging time without overloading VBUS

current limitations, the IC’s input current limit can be

programmed by the IINLIM bits (REG 01[7:6]).

Table 12. INPUT CURRENT LIMIT

IINLIM REG 01[7:6] Input Current Limit

00 100 mA

01 500 mA

10 800 mA

11 No limit

The OTG pin establishes the input current limit when t15MIN

is running.

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Flow Charts

VBUS POR

VBAT > VLOWV YES

Charge

Configuration

State

T15Min Timer?

YES

Reset all registers

Start T

15MIN

YES

HZ State

YES

Charge State

YES

HZ State

YES

T32Sec

Armed?

YES

T32Sec

Armed?

DISABLE Pin

set?

DISABLE Pin

set?

DISABLE Pin

set?

HZ, CE or

Figure 36. Charger VBUS POR

HZ, CE or

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Flow Charts (Continued)

CHARGE STATE

YES

Disable Charging

Indicate

VBUS Fault

T15MIN

Timeout?

Enable I

SHORT,

Reset Safety reg

Indicate Charging

PWM Charging

Indicate Charging

YESVBUS OK?

YES

Indicate timer fault

Set CE

HIGHZ mode

Indicate Charge

Complete

VBAT < VOREG–VRCH

YES

VBUS OK?

Charge

Configuration

State

YES

Disable Charging

Indicate

VBUS Fault

YES

T15MIN

Timeout?

IOUT < ITERM

Termination enabled

VBAT > VOREG –VRCH

VBAT < V

SHORT

YES

Battery Removed

Reset charge

parameters

VBAT < VOREG –VRCH

Reset Safety reg

Delay tINT

Stop Charging

Enable IDET for TDETECT

Figure 37. Charge Mode

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Flow Charts (Continued)

Charge

Configuration

State

T32Sec

ARMED AND

CE# = 0?

Charge State

YES

VBAT < VOREG

for 262ms?

YES

START T15Min

Has T15Min

and CE# = 0

Figure 38. Charge Configuration

Charge Start

Start T15MIN

T15MIN

Active?

Reset Registers

YES

Start T32SEC

Stop T15MIN

I2C Write

received?

YES

T15MIN

Expired?

NO Continue

Charging

T32SEC

Expired?

YES

Timer Fault :

Set CE

Figure 39. Timer Flow Chart

Dynamic Input Voltage Control

The FAN54005 has functionality that limits input current

in case a current−limited incompatible adapter is supplying

VBUS. These slowly increase the charging current until

either:

•IINLIM or IOCHARGE is reached

•VBUS=VSP

If VBUS collapses to VSP when the current is ramping up, the

FAN54005 charges with an input current that keeps

VBUS=VSP

. When the VSP control loop is limiting the charge

current, the SP bit (REG 05[4]) is set.

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Table 13. VSP AS FUNCTION OF VSP BITS (REG 05[2:0])

Decimal HEX VSP

VSP

0 00 4.213

1 01 4.293

2 02 4.373

3 03 4.453

4 04 4.533

5 05 4.613

6 06 4.693

7 07 4.773

Safety Settings

FAN54005 contain a SAFETY register (REG 06) that

prevents the values in OREG (REG 02[7:2]) and

IOCHARGE (REG 04[6:4]) from exceeding the values of

the VSAFE and ISAFE values. Refer to Table 14 and

Table 15 for details.

After VBAT exceeds VSHORT, the SAFETY register is

loaded with its default value and may be written only before

any other register is written. The entire desired Safety

bits are set. After writing to any other register, the SAFETY

The ISAFE (REG 06[6:4]) and VSAFE (REG 06[3:0])

registers establish the maximum values of VRSNS and

VOREG used by the control logic. If the host attempts to write

a value higher than VSAFE or ISAFE to OREG or

IOCHARGE, respectively; the VSAFE, ISAFE value

appears as the OREG, IOCHARGE register value,

respectively.

Table 14. ISAFE (IOCHARGE Limit) AS FUNCTION OF

ISAFE BITS (REG 06[6:4])

Decimal HEX VRSNS (mV)

ISAFE Range (mA)

180 mW68 mW

ISAFE

0 00 37.4 208 550

1 01 44.2 246 650

2 02 51.0 283 750

3 03 57.8 321 850

4 04 71.4 397 1050

5 05 78.2 434 1150

6 06 91.8 510 1350

7 07 98.6 548 1450

Table 15. VSAFE (VOREG Max. Limit) AS FUNCTION

OF VSAFE BITS (REG 06[3:0])

Decimal HEX

Max. OREG

(REG 02[7:2])

VOREG

Max. (V)

VSAFE

0 00 100011 4.20

1 01 100100 4.22

2 02 100101 4.24

3 03 100110 4.26

4 04 100111 4.28

5 05 101000 4.30

6 06 101001 4.32

7 07 101010 4.34

8 08 101011 4.36

9 09 101100 4.38

10 0A 101101 4.40

11 0B 101110 4.42

12 0C 101111 4.44

13 0D 110000 4.44

14 0E 110001 4.44

15 0F 110010 4.44

Thermal Regulation and Protection

When the IC’s junction temperature reaches TCF (about

120°C), the charger reduces its output current to

37.4 mV/RSNS to prevent overheating. If the temperature

increases beyond TSHUTDOWN; charging is suspended, the

FAULT bits are set to 101, and STAT is pulsed HIGH. In

Suspend Mode, all timers stop and the state of the IC’s logic

is preserved. Charging resumes at programmed current after

the die cools to about 120°C.

Additional qJA data points, measured using the

FAN54005 evaluation board, are given in Table 16

(measured with TA=25°C). Note that as power dissipation

increases, the effective qJA decreases due to the larger

difference between the die temperature and ambient.

Table 16. EVALUATION BOARD MEASURED qJA

Dissipation (W) qJA

0.504 54°C/W

0.844 50°C/W

1.506 46°C/W

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Charge Mode Input Supply Protection

Sleep Mode

When VBUS falls below VBAT + VSLP

, and VBUS is above

VIN(MIN)1, the IC enters Sleep Mode to prevent the battery

from draining into VBUS. During Sleep Mode, reverse

current is disabled by body switching Q1.

Input Supply Low−Voltage Detection

The IC continuously monitors VBUS during charging. If

VBUS falls below VIN(MIN)2, the IC:

1. Terminates charging

2. Pulses the STAT pin, sets the STAT bits to 11, and

sets the FAULT bits to 011.

If VBUS recovers above the VIN(MIN)1 rising threshold

after time tINT (about two seconds), the charging process is

repeated. This function prevents the USB power bus from

collapsing or oscillating when the IC is connected to a

suspended USB port or a low−current−capable OTG device.

Input Over−Voltage Detection

When VBUS exceeds VBUSOVP

, the IC:

1. Turns off Q3

2. Suspends charging

3. Sets the FAULT bits to 001, sets the STAT bits to

11, and pulses the STAT pin.

When VBUS falls about 100 mV below VBUSOVP

, the fault

is cleared and charging resumes after VBUS is revalidated.

VBUS Short While Charging

If VBUS is shorted with a very low impedance while the

IC is charging with IINLIMIT =100 mA, the IC may not meet

datasheet specifications until power is removed. To trigger

this condition, VBUS must be driven from 5 V to GND with

a high slew rate. Achieving this slew rate requires a 0 W

short from GND to the USB cable that is less than 10 cm

from the connector.

Charge Mode Battery Detection & Protection

VBAT Over−Voltage Protection

The OREG voltage regulation loop prevents VBAT from

overshooting the OREG voltage by more than 50 mV when

the battery is removed. When the PWM charger runs with no

battery, the TE bit is not set, and a battery is inserted that is

charged to a voltage higher than VOREG; PWM pulses stop.

If no further pulses occur for 30 ms, the IC sets the FAULT

bits to 100, sets the STAT bits to 11, and pulses the STAT pin.

Battery Detection during Charging

The IC can detect the presence, absence, or removal of a

battery if the termination bit (TE) is set. During normal

charging, once VBAT is close to VOREG and the termination

charge current is detected, the IC terminates charging and

sets the STAT bits to 10. It then turns on a discharge current,

IDETECT, for tDETECT. If VBAT is still above VOREG – VRCH,

the battery is present and the IC sets the FAULT bits to 000.

If VBAT is below VOREG – VRCH, the battery is absent and

the IC:

1. Sets the registers to their default values.

2. Sets the FAULT bits to 111.

3. Resumes charging with default values after tINT.

Battery Short−Circuit Protection

If the battery voltage is below the short−circuit threshold

(VSHORT); a linear current source, ISHORT, supplies VBAT

until VBAT > VSHORT.

System Operation with No Battery

The FAN54005 continues charging after VBUS POR with

the default parameters, regulating the VBAT line to 3.54 V

until the host processor issues commands or the t15MIN timer

expires. In this way, the FAN54005 can start the system

without a battery.

The FAN54005 soft−start function may interfere with the

system supply when the battery is absent. The soft−start

activates whenever VOREG, IINLIM, or IOCHARGE are set

from a lower to higher value. During soft−start, the IIN limit

drops to 100 mA for about 1 ms unless IINLIM is set to 11

(no limit). This could cause the system processor to fail to

start. To avoid this behavior, use the following sequence.

1. Set the OTG pin HIGH. When VBUS is plugged

in, IINLIM is set to 500 mA until the system

processor powers up and can set parameters

through I2C.

2. Program the Safety Register.

3. Set IINLIM to 11 (no limit).

4. Set OREG to the desired value (typically 4.18).

5. Reset the IO_LEVEL bit, then set IOCHARGE.

6. Set IINLIM to 500 mA if a USB source is

connected.

During the initial system startup, while the charger IC is

being programmed, the system current is limited to 500 mA

for 1 ms during steps 4 and 5. This is the value of the

soft−start IOCHARGE current used when IINLIM is set to No

Limit.

If the system is powered up without a battery present, the

CV bit should be set. When a battery is inserted, the CV bit

is cleared.

Charger Status / Fault Status

The STAT pin indicates the operating condition of the IC

and provides a fault indicator for interrupt driven systems.

Table 17. STAT PIN FUNCTION

EN_STAT Charge State STAT Pin

0 X OPEN

XNormal Conditions OPEN

1 Charging LOW

XFault (Charging or Boost) 128 ms Pulse, then

OPEN

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The FAULT bits (REG 00[2:0]) indicate the type of fault

in Charge Mode. See Table 18 for details.

Table 18. FAULT STATUS BITS DURING CHARGE MODE

Fault Bit

Fault Description

B2 B1 B0

0 0 0 Normal (No Fault)

0 0 1 VBUS OVP

0 1 0 Sleep Mode

0 1 1 Poor Input Source

1 0 0 Battery OVP

1 0 1 Thermal Shutdown

1 1 0 Timer Fault

1 1 1 No Battery

Charge Mode Control Bits

Setting either HZ_MODE or CE through I2C disables the

charger and puts the IC into High−Impedance Mode. The

t32S timer will continue to run. If it is allowed to expire, all

registers (except SAFETY) reset, which enables t15MIN

charging. When the t15MIN expires, the IC sets the CE bit and

the IC enters High−Impedance Mode. If CE was set by

t15MIN overflow, a new charge cycle can only be initiated

through I2C or VBUS POR.

Setting the RESET bit clears all registers (except Safety).

Table 19. DISABLE PIN AND CE BIT FUNCTIONALITY

Charging DISABLE Pin CE HZ_MODE

ENABLE 0 0 0

DISABLE X 1 X

DISABLE X X 1

DISABLE 1 X X

Raising the DISABLE pin does stop the t32S from

advancing. If the DISABLE pin is raised during t15MIN

charging, the t15MIN timer is reset.

Operational Mode Control

OPA_MODE (REG 01[0]) and the HZ_MODE (REG

01[1]) bits in conjunction with the FAULT state define the

operational mode of the charger.

Table 20. OPERATION MODE CONTROL

HZ_MODE OPA_MODE FAULT Operation Mode

0 0 0 Charge

0 X 1 Charge Configure

0 1 0 Boost

1 X X High Impedance

The IC resets the OPA_MODE bit whenever the boost is

deactivated, whether due to a fault or being disabled by

setting the HZ_MODE bit.

Boost Mode

Boost Mode can be enabled if the IC is in 32−Second

Mode with the OTG pin and OPA_MODE bits as indicated

in Table 21. The OTG pin ACTIVE state is 1 if OTG_PL=1

and 0 when OTG_PL=0.

If boost is active using the OTG pin, Boost Mode is

initiated even if the HZ_MODE=1. The HZ_MODE bit

overrides the OPA_MODE bit.

Table 21. ENABLING BOOST

OTG_EN OTG Pin HZ_MODE OPA_MODE BOOST

1 ACTIVE X X Enabled

X X 0 1 Enabled

X ACTIVE X 0 Disabled

0 X 1 X Disabled

1 ACTIVE 1 1 Disabled

0 ACTIVE 0 0 Disabled

To remain in Boost Mode, the TMR_RST must be set by

the host before the t32S timer times out. If t32S times out in

Boost Mode; the IC resets all registers, pulses the STAT pin,

sets the FAULT bits to 110, and resets the BOOST bit. VBUS

POR or reading REG00 clears the fault condition.

Boost PWM Control

The IC uses a minimum on−time and computed minimum

off−time to regulate VBUS. The regulator achieves

excellent transient response by employing current−mode

modulation. This technique causes the regulator to exhibit a

load line. During PWM Mode, the output voltage drops

slightly as the input current rises. With a constant VBAT, this

appears as a constant output resistance.

The “droop” caused by the output resistance when a load

is applied allows the regulator to respond smoothly to load

transients with no undershoot from the load line. This can be

seen in Figure 32 and Figure 40.

200

225

250

275

300

325

350

2.0 2.5 3.0 3.5 4.0 4.5 5.0

Output Resistance (mΩ)

Figure 40. Output Resistance (ROUT)

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VBUS as a function of ILOAD can be computed when the

regulator is in PWM Mode (continuous conduction) as:

VBUS +5.07 *ROUT @ILOAD (eq. 1)

At VBAT=3.3 V, and ILOAD=200 mA, VBUS would drop to:

VBUS +5.07 *0.26 @0.2 +5.018 V (eq. 2)

At VBAT=2.7 V, and ILOAD=200 mA, VBUS would drop to:

VBUS +5.07 *0.327 @0.2 +5.005 V (eq. 3)

PFM Mode

If VBUS > VBOOST (nominally 5.07 V) when the

minimum off−time has ended, the regulator enters PFM

Mode. Boost pulses are inhibited until VBUS < VBOOST. The

minimum on−time is increased to enable the output to pump

up sufficiently with each PFM boost pulse. Therefore the

regulator behaves like a constant on−time regulator, with the

bottom of its output voltage ripple at 5.07 V in PFM Mode.

Table 22. BOOST PWM OPERATING STATES

Mode Description Invoked When

LIN Linear Startup VBAT > VBUS

SS Boost Soft−Start VBUS < VBOOST

BST Boost Operating Mode VBAT > UVLOBST and

SS Completed

Startup

When the boost regulator is shut down, current flow is

prevented from VBAT to VBUS, as well as reverse flow

from VBUS to VBAT.

LIN State

When the boost is enabled, if VBAT > UVLOBST, the

regulator first attempts to bring PMID within 400 mV of

VBAT using an internal 450 mA current source from VBAT

(LIN State). If PMID has not achieved VBAT – 400 mV after

560 ms, a FAULT state is initiated.

SS State

When PMID > VBAT – 400 mV, the boost regulator begins

switching with a reduced peak current limit of about 50% of

its normal current limit. The output slews up until VBUS is

within 5% of its setpoint; at which time, the regulation loop

is closed and the current limit is set to 100%.

If the output fails to achieve 95% of its setpoint (VBST)

within 128 ms, the current limit is increased to 100%. If the

output fails to achieve 95% of its setpoint after this second

384 ms period, a fault state is initiated.

BST State

This is the normal operating mode of the regulator. The

regulator uses a scheme of calculated tOFF, modulated tON

with a minimum tON. The calculated tOFF is proportional to

VIN / VOUT, which keeps the regulator’s switching

frequency reasonably constant in CCM.

To ensure VBUS does not pump significantly above the

regulation point, the boost switch remains off as long as the

actual output voltage is greater than the regulation point.

Boost Faults

If a BOOST fault occurs:

1. The STAT pin pulses.

2. OPA_MODE bit is reset.

3. The power stage is in High−Impedance Mode.

4. The FAULT bits (REG 00[2:0]) are set per

Table 23

Restart After Boost Faults

If boost was enabled with the OPA_MODE bit and

OTG_EN=0, Boost Mode can only be enabled through

subsequent I2C commands since OPA_MODE is reset on

boost faults. If OTG_EN=1 and the OTG pin is still

ACTIVE (see Table 21), the boost restarts after a 5.2 ms

delay, as shown in Figure 41. If the fault condition persists,

restart is attempted every 5 ms until the fault clears or an I2C

command disables the boost.

Table 23. FAULT BITS DURING BOOST MODE

Fault Bit

Fault Description

B2 B1 B0

0 0 0 Normal (no fault)

0 0 1 VBUS > VBUSOVP

0 1 0 VBUS fails to achieve the voltage required to

advance to the next state during soft−start or

sustained (>50 ms) current limit during the BST

state.

0 1 1 VBAT < UVLOBST

1 0 0 N/A: This code does not appear.

1 0 1 Thermal shutdown

1 1 0 Timer fault; all registers reset.

1 1 1 N/A: This code does not appear.

450mA

VBUS

BATTERY

CURRENT 0

560

BOOST

ENABLED

5200

Figure 41. Boost Response Attempting to Start into

VBUS Short Circuit (times in ms)

VREG Pin

The 1.8 V regulated output on this pin can be disabled

through I2C by setting the DIS_VREG bit (REG 05[6]).

VREG can supply up to 2 mA. This circuit, which is

powered from PMID, is enabled only when PMID > VBAT

and does not drain current from the battery. During boost,

VREG is off. It is also off when the HZ_MODE bit (REG

01[1])=1.

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Monitor Register (Reg 10h)

Additional status monitoring bits enable the host

processor to have more visibility into the status of the IC.

The monitor bits are real−time status indicators and are not

internally debounced or otherwise time qualified.

The state of the MONITOR register bits listed in

High−Impedance Mode is only valid when VBUS is valid.

I2C Interface

The FAN54005’s serial interface is compatible with

Standard, Fast, Fast Plus, and High−Speed Mode I2C−Bus

specifications. The SCL line is an input and the SDA line is

a bi−directional open−drain output; it can only pull down the

bus when active. The SDA line only pulls LOW during data

reads and signaling ACK. All data is shifted in MSB (bit 7)

first.

Slave Address

Table 24. I

C SLAVE ADDRESS BYTE

Part Type 7 6 5 4 3 2 1 0

FAN54005 1 1 0 1 0 1 0 R/W

In hex notation, the slave address assumes a 0 LSB. The

hex slave address for the FAN54005 is D4H and is D6H for

all other parts in the family.

Bus Timing

As shown in Figure 42, data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

SCL TSU

SDA

Data change allowed

Figure 42. Data Transfer Timing

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH,

as shown in Figure 43.

SCL

THD;STA

SDA Slave Address

MS Bit

Figure 43. Start Bit

A transaction ends with a STOP condition, which is

defined as SDA transitioning from 0 to 1 with SCL HIGH,

as shown in Figure 44.

SCL

SDA

Slave Releases Master Drives

ACK(0) or

NACK(1)

tHD;STO

Figure 44. Stop Bit

During a read from the FAN54005 (Figure 47), the master

issues a Repeated Start after sending the register address and

before resending the slave address. The Repeated Start is a

1−to−0 transition on SDA while SCL is HIGH, as shown in

Figure 45.

High−Speed (HS) Mode

The protocols for High−Speed (HS), Low−Speed (LS),

and Fast−Speed (FS) Modes are identical except the bus

speed for HS Mode is 3.4 MHz. HS Mode is entered when

the bus master sends the HS master code 00001XXX after

a start condition. The master code is sent in Fast or Fast Plus

Mode (less than 1 MHz clock); slaves do not ACK this

transmission.

The master then generates a repeated start condition

(Figure 45) that causes all slaves on the bus to switch to HS

Mode. The master then sends I2C packets, as described

above, using the HS Mode clock rate and timing.

The bus remains in HS Mode until a stop bit (Figure 44)

is sent by the master. While in HS Mode, packets are

separated by repeated start conditions (Figure 45).

SCL

SDA ACK(0) or

NACK(1)

Slave Releases

SLADDR

MS Bit

tHD;STA

tSU;STA

Figure 45. Repeated Start Timing

Read and Write Transactions

The figures below outline the sequences for data read and

write. Bus control is signified by the shading of the packet,

defined as

Master Drives Bus

and

Slave Drives Bus

All addresses and data are MSB first.

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Table 25. BIT DEFINITIONS FOR FIGURE 46 AND FIGURE 47

Symbol Definition

SSTART, see Figure 43

AACK. The slave drives SDA to 0 to acknowledge the preceding packet.

ANACK. The slave sends a 1 to NACK the preceding packet.

RRepeated START, see Figure 45

PSTOP, see Figure 44

SSlave Address AReg Addr A A P0

7 bits 8 bits 8 bits

Data

000

SSlave Address AReg Addr A0

7 bits 8 bits

RSlave Address

7 bits

1 A Data A

8 bits

00 01

Figure 46. Write Transaction

Figure 47. Read Transaction

The nine FAN54005 user−accessible registers are defined in Table 26.

Table 26. I

C REGISTER ADDRESS

Name REG# 7 6 5 4 3 2 1 0

CONTROL0 00 0 0 0 0 0 0 0 0

CONTROL1 01 0 0 0 0 0 0 0 1

OREG 02 0 0 0 0 0 0 1 0

IC_INFO 03 0 0 0 0 0 0 1 1

IBAT 04 0 0 0 0 0 1 0 0

SP_CHARGER 05 0 0 0 0 0 1 0 1

SAFETY 06 0 0 0 0 0 1 1 0

MONITOR 10h 0 0 0 1 0 0 0 0

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Table 27. REGISTER BIT DEFINITIONS

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit Name Value Type Description

CONTROL0 Register Address: 00 Default Value=X1XX 0XXX

7TMR_RST OTG 1WWriting a 1 resets the t32S timer; writing a 0 has no effect

RReturns the OTG pin level (1=HIGH)

6 EN_STAT 0 R/W Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate

faults

1Enables STAT pin LOW when IC is charging

5:4 STAT 00 R Ready

01 Charge in progress

10 Charge done

11 Fault

3 BOOST 0 R IC is not in Boost Mode

1IC is in Boost Mode

2:0 FAULT R Fault status bits: for Charge Mode, see Table 18

CONTROL1 Register Address: 01 Default Value=0111 0000 (70h)

7:6 IINLIM 01 R/W Input current limit, see Table 12

5:4 VLOWV 00 R/W 3.4 V Weak battery voltage threshold

01 3.5 V

10 3.6 V

11 3.7 V

3 TE 0 R/W Disable charge current termination

1Enable charge current termination

2 CE 0 R/W Charger enabled.

1Charger disabled. The T32S timer is not suspended

1 HZ_MODE 0 R/W Not High−Impedance Mode See Table 21

1High−Impedance Mode

0 OPA_MODE 0 R/W Charge Mode

1Boost Mode

OREG Register Address: 02 Default Value=0000 1010 (0Ah)

7:2 OREG 000010 R/W Charger output “float” voltage; programmable from 3.5 to 4.44 V in 20 mV increments;

defaults to 000010 (3.54 V). See Table 8

1 OTG_PL 0 R/W OTG pin active LOW

1OTG pin active HIGH

0 OTG_EN 0 R/W Disables OTG pin

1Enables OTG pin

IC_INFO Register Address: 03 Default Value=100101XX (9Xh)

7:5 Vendor Code 100 RIdentifies ON Semiconductor as the IC supplier

4:2 PN 101 RPart number bits, see the Ordering Information on page 1

1:0 REV XX R IC Revision bits

IBAT Register Address: 04 Default Value=1000 1001 (89h)

7 RESET 1WWriting a 1 resets charge parameters, except the Safety register (REG 06), to their de-

faults: writing a 0 has no effect; read returns 1

6:4 IOCHARGE 000 R/W Programs the maximum charge current when IO_LEVEL (REG 05[5]) = 0. See Table 10

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Table 27. REGISTER BIT DEFINITIONS

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit DescriptionTypeValueName

3 Reserved 1R Unused

2:0 ITERM 001 R/W Sets the current used for charging termination. See Table 11

SP_CHARGER Register Address: 05 Default Value=001X X100

7 Reserved 0R Unused

6 DIS_VREG 0R/W 1.8 V regulator is ON

11.8 V regulator is OFF

5 IO_LEVEL 0 R/W Output current is controlled by the IOCHARGE bits

1Output current control is limited to 34 mV across RSNS

4 SP 0 R DIVC is not active (VBUS is able to stay above VSP)

1DIVC has been detected and VBUS is being regulated to VSP

3 EN_LEVEL 0 R DISABLE pin is LOW

1DISABLE pin is HIGH

2:0 VSP 100 R/W DIVC input regulation voltage. See Table 13

SAFETY Register Address: 06 Default Value=0100 0000 (40h)

7 Reserved 0 R Bit disabled and always returns 0 when read back

6:4 ISAFE 100 R/W Sets the maximum IOCHARGE value used by the control circuit. See Table 14

3:0 VSAFE 0000 R/W Sets the maximum VOREG used by the control circuit. See Table 15

MONITOR Register Address: 10h (16)

7 ITERM_CMP R ITERM comparator output, 1 when VRSENSE > See Table 11

6 VBAT_CMP R Output of VBAT comparator

1 during charging indicates VBAT > VSHORT

1 during HZ_MODE indicates VBAT > VLOWV

1 during Boost Mode indicated VBAT > UVLOBST

5 LINCHG R 30 mA linear charger ON

4 T_120 R Thermal regulation comparator; when=1 and T_145=0, the charge current is limited to

22.1 mV across RSENSE

3 ICHG R 0 indicates the IOCHARGE loop is controlling the battery charge current

2 IBUS R 0 indicates the IBUS (input current) loop is controlling the battery charge current

1 VBUS_VALID R 1 indicates VBUS has passed validation and is capable of charging

0 CV R 1 indicates the constant−voltage loop (OREG) had been active at least once since the

last VBUS plug in

0 indicates the constant−voltage loop (OREG) had never been reached since the last

VBUS plug in or the part is in the Charge Done state with TE=1

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PCB Layout Recommendations

Bypass capacitors should be placed as close to the IC as

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. All power and ground pins must be

routed to their bypass capacitors, using top copper whenever

possible. Copper area connecting to the IC should be

maximized to improve thermal performance if possible.

Figure 48. PCB Layout Recommendations

The table below pertains to the MOD information on the following page.

PRODUCT−SPECIFIC DIMENSIONS

Product D E X Y

FAN54005UCX 1.960 ±0.030 mm 1.870 ±0.030 mm 0.335 mm 0.180 mm

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PACKAGE DIMENSIONS

WLCSP20 1.96x1.87x0.586

CASE 567SL

ISSUE O

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