SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 D Internal Voltage References . . . 50 PPM/C features D Controlled Baseline D D D D D D D D D D D D D D - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -55C to 125C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree High-Speed 6 MSPS ADC 4 Single-Ended or 2 Differential Inputs Simultaneous Sampling of 4 Single-Ended Signals or 2 Differential Signals or Combination of Both Differential Nonlinearity Error: 1 LSB Integral Nonlinearity Error: 1.8 LSB Signal-to-Noise and Distortion Ratio: 68 dB at fI = 2 MHz Auto-Scan Mode for 2, 3, or 4 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 216 mW Max 5-V Analog Single Supply Operation Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. description D D D D and 5% Accuracy Glueless DSP Interface Parallel C/DSP Interface Integrated FIFO Available in TSSOP Package applications D D D D D Radar Applications Communications Control Applications High-Speed DSP Front-End Selected Military Applications DA PACKAGE (TOP VIEW) D0 D1 D2 D3 D4 D5 1 32 2 31 3 30 4 29 5 28 6 27 BVDD BGND D6 D7 D8 D9 D10/RA0 D11/RA1 CONV_CLK (CONVST) DATA_AV 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 AINP AINM BINP BINM REFIN REFOUT REFP REFM AGND AVDD CS0 CS1 WR (R/W) RD DVDD DGND The THS1206 is a CMOS, low-power, 12-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS1206 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002 - 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 description (continued) An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In single conversion mode, a single and simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal (CONVST). The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS1206. The internal clock oscillator is switched off in continuous conversion mode. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING -55C to 125C TSSOP - DA Tape and reel THS1206MDAREP THS1206MEP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. functional block diagram AVDD DVDD 2.5 V 3.5 V REFP 1.225 V REF 1.5 V REFOUT REFM REFIN AINP VREFM S/H DATA_AV VREFP AINM BINP S/H S/H Single Ended and/or Differential MUX + - BVDD 12 Bit Pipeline ADC 12 FIFO 16 x 12 12 Buffers BINM CONV_CLK (CONVST) CS0 CS1 RD S/H Logic and Control Control Register BGND WR (R/W) AGND 2 POST OFFICE BOX 655303 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10/RA0 D11/RA1 * DALLAS, TEXAS 75265 DGND SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AINP 32 I Analog input, single-ended or positive input of differential channel A AINM 31 I Analog input, single-ended or negative input of differential channel A BINP 30 I Analog input, single-ended or positive input of differential channel B BINM 29 I Analog input, single-ended or negative input of differential channel B AVDD AGND 23 I Analog supply voltage 24 I Analog ground BVDD BGND 7 I Digital supply voltage for buffer 8 I Digital ground for buffer CONV_CLK (CONVST) 15 I Digital input. This input is used to apply an external conversion clock in continuous conversion mode. In single conversion mode, this input functions as the conversion start (CONVST) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs. CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. See Table 14. DGND 17 I Digital ground. Ground reference for digital circuitry. DVDD 18 I Digital supply voltage D0 - D9 1-6, 9-12 I/O/Z Digital input, output; D0 = LSB D10/RA0 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to the control register 0 and control register 1. See Table 8. D11/RA1 14 I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. REFP 26 I Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. REFM 25 I Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 A. The reference output requires a capacitor of 10 F to AGND for filtering and stability. RD 19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. See timing section. WR (R/W) 20 I This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only input WR, which is active low and used as data write select from the processor. In this case, the RD input is used as a read input from the processor. See timing section. The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, DGND to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V BGND to BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V AGND to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3 V to AVDD + 1.5 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 + AGND to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to BVDD/DVDD + 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Operating free-air temperature range,TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA 25C 25 C POWER RATING DERATING FACTOR ABOVE TA = 25C 70C TA = 70 C POWER RATING 85C TA = 85 C POWER RATING 125C TA = 125 C POWER RATING DA 1453 mW 11.62 mW/C 930 mW 756 mW 291 mW This is the inverse of the traditional junction-to-ambient thermal resistance (RJA). Thermal resistances are not production tested and are for informational purposes only. recommended operating conditions power supply Supply voltage MIN NOM MAX AVDD DVDD 4.75 5 5.25 3 3.3 5.25 BVDD 3 3.3 5.25 UNIT V analog and reference inputs MIN Analog input voltage in single-ended configuration NOM MAX V 2.5 VREFP 4 3.5 AVDD-1.2 V VREFM 1 Common-mode input voltage VCM in differential configuration External reference voltage,VREFP (optional) External reference voltage, VREFM (optional) 1.4 Input voltage difference, REFP - REFM UNIT V 1.5 V 2 V digital inputs MIN NOM MAX UNIT High-level input voltage, VIH BVDD = 3.3 V BVDD = 5.25 V Low-level input voltage, VIL BVDD = 3.3 V BVDD = 5.25 V Input CONV_CLK frequency DVDD = 3 V to 5.25 V 0.1 CONV_CLK pulse duration, clock high, tw(CONV_CLKH) DVDD = 3 V to 5.25 V 80 83 5000 ns CONV_CLK pulse duration, clock low, tw(CONV_CLKL) DVDD = 3 V to 5.25 V 80 83 5000 ns 125 C Operating free-air temperature, TA 4 2 V 2.6 V 0.6 0.6 -55 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 6 V V MHz SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 electrical characteristics over recommended operating conditions, VREF = internal (unless otherwise noted) digital specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital inputs IIH IIL High-level input current DVDD = digital inputs -50 Low-level input current Digital input = 0 V -50 Ci Input capacitance 50 A 50 A 5 pF Digital outputs VOH High-level output voltage IOH = -50 A A VOL Low-level output voltage IOZ CO High-impedance-state output current CL Load capacitance at databus D0 - D11 BVDD = 3.3 V, BVDD = 5 V BVDD-0.5 BVDD-0.5 V 0.4 0.4 CS1 = DGND, CS0 = DVDD -10 Output capacitance 10 5 V A pF 30 pF dc specifications PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 12 UNIT Bits Accuracy Integral nonlinearity, INL Differential nonlinearity, DNL After calibration in single-ended mode Offset error After calibration in differential mode Gain error 1.8 LSB 1 LSB 20 LSB -20 20 LSB -20 20 LSB Analog input Input capacitance Input leakage current 15 VAIN = VREFM to VREFP pF 10 A V Internal voltage reference Accuracy, VREFP 3.3 3.5 3.7 Accuracy, VREFM 1.3 1.5 1.7 Temperature coefficient 50 Reference noise V 100 Accuracy, REFOUT 2.3 V PPM/C 2.5 2.7 V Power supply IDDA Analog supply current AVDD = 5 V, BVDD = DVDD = 3.3 V 36 40 mA IDDD Digital supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 0.5 1 mA IDDB Buffer supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 1.5 4 mA IDD_P Supply current in power-down mode AVDD = 5 V, BVDD = DVDD = 3.3 V 10 mA Power dissipation AVDD = 5 V, DVDD = BVDD = 3.3 V 186 216 mW Power dissipation in power down AVDD = 5 V, DVDD = BVDD = 3.3 V 30 mW Not production tested. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 electrical characteristics over recommended operating conditions, VREF = internal, fs = 6 MHz, fI = 2 MHz at -1dBFS (unless otherwise noted) ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF PARAMETER TEST CONDITIONS Differential mode SINAD Signal-to-noise ratio + distortion SNR Signal-to-noise ratio MIN TYP 63 65 dB 64 dB 69 dB Single-ended mode (see Note 1) Differential mode 64 Single-ended mode (see Note 1) THD Total harmonic distortion ENOB (SNR) Effective number of bits SFDR Spurious free dynamic range 68 Differential mode -70 Single-ended mode -68 Differential mode 10.17 Single-ended mode (see Note 1) Differential mode MAX 67 UNIT dB -67 dB 11 Bits 10.4 Bits 71 dB Single-ended mode 69 dB Full-power bandwidth with a source impedance of 150 in differential configuration. FS sinewave, -3 dB 96 MHz Full-power bandwidth with a source impedance of 150 in single-ended configuration. FS sinewave, -3 dB 54 MHz Small-signal bandwidth with a source impedance of 150 in differential configuration. 100 mVpp sinewave, -3 dB 96 MHz Small-signal bandwidth with a source impedance of 150 in single-ended configuration. 100 mVpp sinewave, -3 dB 54 MHz Analog Input NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling clock. timing specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, VREF = internal, CL < 30 pF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(DATA_AV) Delay time 5 ns td(o) Delay time 5 ns tpipe Latency 5 CONV CLK 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 timing specification of the single conversion mode PARAMETER tc TEST CONDITIONS Clock cycle of the internal clock oscillator 1 analog input Pulse width, CONVST 3 analog inputs Time between consecutive start of single conversion 3 analog inputs 4 analog inputs 1 analog input, Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 0, TRIG1 = 0 TL = 1 ns 2xtc 3xtc ns 4xtc 5xtc ns ns 3xt2 +6xtc t2 +7xtc ns t2 +8xtc t2 +9xtc ns 7xt2 +6xtc 3xt2 +7xtc ns 2xt2 +8xtc 2xt2 +9xtc ns 2 analog inputs, TL = 12 13xt2 +6xtc 5xt2 +7xtc ns 3 analog inputs, TL = 12 3xt2 +8xtc ns TL = 4 2 analog inputs, TL = 4 3 analog inputs, TL = 6 1 analog input, TL = 8 2 analog inputs, TL = 8 3 analog inputs, TL = 9 4 analog inputs, TL = 12 1 analog input, Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 1, TRIG1 = 1 ns 8xtc 9xtc 3 analog inputs, TL = 3 4 analog inputs, TL = 8 Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 0, TRIG1 = 1 ns ns 2 analog inputs, TL = 2 1 analog input, Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 1, TRIG1 = 0 UNIT 6xtc 7xtc 4 analog inputs, TL = 4 td(DATA_AV) 175 1 2 analog inputs td(DATA_AV) 167 Aperture time 1 analog input t2 159 MAX 3.5xtc 4.5xtc 4 analog inputs tdA TYP 1.5xtc 2.5xtc 2 analog inputs t1 MIN TL = 14 Timing parameters are ensured by design but are not tested. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 detailed description reference voltage The THS1206 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. analog inputs The THS1206 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed. converter The THS1206 uses a 12-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages, which achieves a high sample rate with low power consumption. The THS1206 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples. conversion modes The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. sampling rate The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations. Table 1. Maximum Conversion Rate in Continuous Conversion Mode NUMBER OF CHANNELS MAXIMUM CONVERSION RATE PER CHANNEL 1 single-ended channel 1 6 MSPS 2 single-ended channels 2 3 MSPS 3 single-ended channels 3 2 MSPS 4 single-ended channels 4 1.5 MSPS 1 differential channel 1 6 MSPS 2 differential channels 2 3 MSPS 1 single-ended and 1 differential channel 2 3 MSPS 2 single-ended and 1 differential channels 3 2 MSPS CHANNEL CONFIGURATION The maximum conversion rate in the continuous conversion mode per channel, fc, is given by: fc + 6 MSPS # channels 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 sampling rate (continued) Table 2 shows the maximum conversion rate in the single conversion mode. Table 2. Maximum Conversion Rate in Single Conversion Mode NUMBER OF CHANNELS MAXIMUM CONVERSION RATE PER CHANNEL 1 single-ended channel 1 3 MSPS 2 single-ended channels 2 2 MSPS 3 single-ended channels 3 1.5 MSPS 4 single-ended channels 4 1.2 MSPS 1 differential channel 1 3 MSPS 2 differential channels 2 2 MSPS 1 single-ended and 1 differential channel 2 1.5 MSPS 2 single-ended and 1 differential channels 3 1.2 MSPS CHANNEL CONFIGURATION single conversion mode In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion mode is selected by setting bit 1 of control register 0 to 1. A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started. The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13. Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can be selected to be sampled simultaneously (see Table 2). t2 CONVST t1 t1 td(A) AIN Sample N tDATA_AV DATA_AV, Trigger Level = 1 Figure 1. Timing of Single Conversion Mode The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog input channels. The time tDATA_AV, until DATA_AV becomes active is given by: tDATA_AV = tpipe + n x tc. This equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer to the timing specifications of single conversion mode. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 continuous conversion mode The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO. Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of a trigger level set to 1 or 4. Sample N Channel 1 Sample N+1 Channel 1 Sample N+2 Channel 1 Sample N+3 Channel 1 Sample N+4 Channel 1 Sample N+5 Channel 1 Sample N+6 Channel 1 Sample N+7 Channel 1 Sample N+8 Channel 1 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) 50% CONV_CLK 50% td(O) tc Data Into FIFO Data N-5 Channel 1 Data N-4 Channel 1 Data N-3 Channel 1 Data N-2 Channel 1 Data N-1 Channel 1 Data N Channel 1 Data N+1 Channel 1 Data N+2 Channel 1 Data N+3 Channel 1 td(DATA_AV) DATA_AV, Trigger Level = 1 td(DATA_AV) DATA_AV, Trigger Level = 4 Figure 2. Timing of Continuous Conversion Mode (1-channel operation) Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 2 or 4. Sample N Channel 1,2 Sample N+1 Channel 1,2 Sample N+2 Channel 1,2 Sample N+3 Channel 1,2 Sample N+4 Channel 1,2 AIN td(A) tw(CONV_CLKH) CONV_CLK 50% td(Pipe) tw(CONV_CLKL) 50% tc Data Into FIFO Data N-3 Channel 2 td(O) Data N-2 Channel 1 Data N-2 Channel 2 Data N-1 Channel 1 Data N-1 Channel 2 Data N Channel 1 Data N Channel 2 Data N+1 Channel 1 Data N+1 Channel 2 td(DATA_AV) DATA_AV, Trigger Level = 2 td(DATA_AV) DATA_AV, Trigger Level = 4 Figure 3. Timing of Continuous Conversion Mode (2-channel operation) 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 continuous conversion mode (continued) Figure 4 shows the timing of continuous conversion mode when three analog input channels are selected. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 3. Sample N Channel 1,2,3 Sample N+1 Channel 1,2,3 Sample N+2 Channel 1,2,3 AIN td(A) td(Pipe) tw(CONV_CLKL) tw(CONV_CLKH) CONV_CLK 50% 50% tc Data Into FIFO td(O) Data N-2 Channel 2 Data N-2 Channel 3 Data N-1 Channel 2 Data N-1 Channel 2 Data N-1 Channel 3 Data N Channel 1 Data N Channel 2 Data N+1 Channel 3 td(DATA_AV) DATA_AV, Trigger Level = 3 Figure 4. Timing of Continuous Conversion Mode (3-channel operation) Figure 5 shows the timing of continuous conversion mode when four analog input channels are selected. The maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level of 4. Sample N Channel 1,2,3,4 Sample N+1 Channel 1,2,3,4 Sample N+2 Channel 1,2,3,4 AIN td(A) td(Pipe) tw(CONV_CLKL) 50% tw(CONV_CLKH) 50% CONV_CLK tc Data Into FIFO Data N-2 Channel 4 td(O) Data N-1 Channel 1 Data N-1 Channel 2 Data N-1 Channel 3 Data N-1 Channel 4 Data N Channel 1 Data N Channel 2 Data N Channel 3 Data N Channel 4 td(DATA_AV) DATA_AV, Trigger Level = 4 Figure 5. Timing of Continuous Conversion Mode (4-channel operation) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 digital output data format The digital output data format of the THS1206 can either be in binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 3. Binary Output Format for Single-Ended Configuration SINGLE-ENDED, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP FFFh AIN = (VREFP + VREFM)/2 800h AIN = VREFM 000h Table 4. Twos Complement Output Format for Single-Ended Configuration SINGLE-ENDED, TWOS COMPLEMENT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP 7FFh AIN = (VREFP + VREFM)/2 000h AIN = VREFM 800h Table 5. Binary Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP - AINM VREF = VREFP - VREFM Vin = VREF Vin = 0 FFFh Vin = -VREF 000h 800h Table 6. Twos Complement Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP - AINM VREF = VREFP - VREFM 12 Vin = VREF Vin = 0 7FFh Vin = -VREF 800h POST OFFICE BOX 655303 000h * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 FIFO description In order to facilitate an efficient connection to today's processors, the THS1206 is supplied with a FIFO. This integrated FIFO enables a problem-free processing of data with today's processors. The FIFO is provided as a flexible circular buffer. The circular buffer integrated in the THS1206 can store up to 16 conversion values. Therefore, the amount of interrupts to be served by a processor can be reduced significantly. 16 1 15 2 Read Pointer 14 3 13 4 5 12 Trigger Pointer 6 11 7 10 9 8 Data in FIFO Free Write Pointer Figure 6. Circular Buffer The converted data of the THS1206 is automatically written into the FIFO. To control the writing and reading process, a write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the location which will be read next. The write pointer indicates the location which contains the last written sample. With a selection of multiple analog input channels, the converted values are written in a predefined sequence to the circular buffer (autoscan mode). In this way, the channel information for the reading processor is continually maintained. The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific trigger level according to Table 13 in order to choose the configuration which best fits the application. The FIFO provides the signal DATA_AV, which signals the processor to read the amount of data equal to the trigger level selected in Table 13. The signal DATA_AV becomes active when the trigger condition is satisfied. The trigger condition is satisfied when as many values as selected for the trigger level where written into the FIFO. The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine call, the processor must read the amount of data equal to the trigger level from the ADC. The first data represents the first channel according to the autoscan mode, which is shown in Table 10. The channel information is therefore always maintained. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 Reading data from the FIFO The THS1206 informs the connected processor via the digital output DATA_AV (data available) that a block of conversion values are ready to be read. The block size to be read is always equal to the setting of the trigger level. The selectable trigger levels depend on the number of selected analog input channels. For example, when choosing one analog input, a trigger level of 1, 4, 8 and 14 can be selected. The following figures demonstrate the principle of reading the data. In Figure 7, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 7. Trigger Level 1 Selected In Figure 8, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 8. Trigger Level 4 Selected In Figure 9, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 9. Trigger Level 8 Selected In Figure 10, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 10. Trigger Level 14 Selected READ is always the logical combination of CS0, CS1 and RD. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 ADC Control Register The THS1206 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 7. Table 7. Bit Definitions of Control Register CR0 and CR1 BIT BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD MODE VREF CR1 RBACK OFFSET BIN/2's R/W DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST RESET Writing to control register 0 and control register 1 The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper data bits D10 and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 8 shows the addressing of each control register. Table 8. Control Register Addressing D0 - D9 D10/RA0 D11/RA1 Addressed Control Register Desired register value 0 0 Control Register 0 Desired register value 1 0 Control Register 1 Desired register value 0 1 Reserved for future Desired register value 1 1 Reserved for future POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 initialization of the THS1206 The initialization of the THS1206 should be done according to the configuration flow shown in Figure 11. Start Use Default Values? No Yes Write 0x401 to THS1206 (Set Reset Bit in CR1) Write 0x401 to THS1206 (Set Reset Bit in CR1) Clear RESET By Writing 0x400 to CR1 Clear RESET By Writing 0x400 to CR1 Write The User Configuration to CR0 Write The User Configuration to CR1 (Can Include FIFO Reset, Must Exclude RESET) Continue Figure 11. THS1206 Configuration Flow 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 ADC control registers control register 0 (see Table 8) - - BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 - - TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD MODE VREF Table 9. Control Register 0 Bit Functions BITS RESET VALUE NAME 0 0 VREF Vref select: Bit 0 = 0 The internal reference is selected Bit 0 = 1 The external reference voltage is selected 1 0 MODE Continuous conversion mode/single conversion mode Bit 1 = 0 Continuous conversion mode is selected FUNCTION An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the CONV_CLK signal a new converted value is written into the FIFO. Bit 1 = 1 Single conversion mode is selected In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the THS1206 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is satisfied. 2 0 PD Power down. Bit 2 = 0 The ADC is active Bit 2 = 1 Power down The reading and writing to and from the digital outputs is possible during power down. It is also possible to read out the FIFO. 3, 4 0,0 CHSEL0, CHSEL1 Channel select Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10. 5,6 1,0 DIFF0, DIFF1 7 0 SCAN Autoscan enable Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10. 8,9 0,0 TEST0, TEST1 Test input enable Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC operation. Number of differential channels Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10. Refer to Table 11 for selection of the three different test voltages. The control signal DATA_AV is disabled in the test mode. Test voltage readings have to be done independent from DATA_AV. To get the THS1206 back to the normal operating mode, apply the the initialization routine. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 analog input channel selection The analog input channels of the THS1206 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 10 shows the possible selections. Table 10. Analog Input Channel Configurations BIT 7 SCAN BIT 6 DIFF1 BIT 5 DIFF0 BIT 4 BIT 3 CHSEL1 CHSEL0 0 0 0 0 0 Analog input AINP (single ended) 0 0 0 0 1 Analog input AINM (single ended) 0 0 0 1 0 Analog input BINP (single ended) 0 0 0 1 1 Analog input BINM (single ended) 0 0 1 0 0 Differential channel (AINP-AINM) 0 0 1 0 1 Differential channel (BINP-BINM) 1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, ... 1 0 0 1 0 Autoscan three single ended channels: AINP, AINM, BINP, AINP, ... 1 0 0 1 1 Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, ... 1 0 1 0 1 Autoscan one differential channel and one single ended channel AINP, (BINP-BINM), AINP, (BINP-BINM), ... 1 0 1 1 0 Autoscan one differential channel and two single ended channel AINP, AINM, (BINP- BINM), AINP, ... 1 1 0 0 1 Autoscan two differential channels (AINP-AINM), (BINP-BINM), (AINP-AINM), ... 0 0 1 1 0 Reserved 0 0 1 1 1 Reserved 1 0 0 0 0 Reserved 1 0 1 0 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 1 0 Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Reserved 1 1 1 1 1 Reserved DESCRIPTION OF THE SELECTED INPUTS test mode The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11. Table 11. Test Mode BIT 9 TEST1 BIT 8 TEST0 OUTPUT RESULT 0 0 Normal mode 0 1 1 0 1 1 VREFP ((VREFM)+(VREFP))/2 VREFM Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor. 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 analog input channel selection (continued) control register 1 (see Table 8) - - BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 - - RBACK OFFSET BIN/2s R/W DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST RESET Table 12. Control Register 1 Bit Functions BITS RESET VALUE NAME 0 0 RESET FUNCTION Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. In addition the FIFO pointer and offset register is reset. After reset, it takes 5 clock cycles until the first value is converted and written into the FIFO. 1 2, 3 4 0 0,0 1 OVFL (read only) Overflow flag (read only) Bit 1 of control register 1 indicates an overflow in the FIFO. Bit 1 = 0 no overflow occurred. Bit 1 = 1 an overflow occurred. This bit is reset to 0, after this control register is read from the processor. FRST (write only) FRST: FIFO reset (write only) By writing a 1 into this bit, the FIFO is reset. TRIG0, TRIG1 FIFO trigger level DATA_T DATA_AV type Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached, the signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This indicates to the processor that the ADC values can be read. Refer to Table 13. Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g for edge or level sensitive interrupt inputs). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a pulse. Refer to Table 14. 5 1 DATA_P DATA_AV polarity Bit 5 of control register 1 controls the polarity of DATA_AV. If it is set to 1, DATA_AV is active high. If it is set to 0, DATA_AV is active low. Refer to Table 14. 6 0 R/W R/W, RD/WR selection Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR becomes a write input. 7 0 BIN/2s Complement select If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6. 8 0 OFFSET Offset cancellation mode Bit 8 = 0 normal conversion mode Bit 8 = 1 offset calibration mode If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error. 9 0 RBACK Debug mode Bit 9 = 0 normal conversion mode Bit 9 = 1 enable debug mode When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. To get the THS1206 back to the normal operating mode, apply the the initialization routine. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 FIFO trigger level Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to indicate to the processor that the ADC values can be read. Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be selected, is dependent on the number of input channels. Both, a differential or a single-ended input is considered as one channel. The processor therefore always reads the data from the FIFO in the same order and is able to distinguish between the channels. Table 13. FIFO Trigger Level BIT 3 TRIG1 BIT 2 TRIG0 TRIGGER LEVEL FOR 1 CHANNEL (ADC values) TRIGGER LEVEL FOR 2 CHANNELS (ADC values) TRIGGER LEVEL FOR 3 CHANNEL (ADC values) TRIGGER LEVEL FOR 4 CHANNELS (ADC values) 0 0 01 02 03 04 0 1 04 04 06 08 1 0 08 08 09 12 1 1 14 12 12 Reserved Timing and Signal Description of the THS1206 The reading from the THS1206 and writing to the THS1206 is performed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select inputs can be used to interface easily to a processor. Reading from the THS1206 takes place by an internal RDint signal, which is generated from the logical combination of the external signals CS0, CS1 and RD (see Figure 12). This signal is then used to strobe the words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid will make RDint active while the write input (WR) is inactive. The first of those external signals going to its inactive state will then deactivate RDint again. Writing to the THS1206 takes place by an internal WRint signal, which is generated from the logical combination of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid will make WRint active while the read input (RD) is inactive. The first of those external signals going to its inactive state will then deactivate WRint again. Read Enable CS0 CS1 RD Write Enable WR Control/Data Registers Data Bits Figure 12. Logical Combination of CS0, CS1, RD, and WR 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 DATA_AV type Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of DATA_AV. This is shown in Table 14. Table 14. DATA_AV Type BIT 5 DATA_P BIT 4 DATA_T 0 0 Active low level 0 1 Active low pulse 1 0 Active high level 1 1 Active high pulse DATA_AV TYPE The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive independent of the DATA_T selection (pulse or level). If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge of READ). The trigger condition is checked again after TL reads. If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous conversion mode and one half of a clock cycle of the internal oscillator in single conversion mode. The next DATA_AV pulse (when the trigger condition is satisfied) is sent out the earliest, when the TL values, written into the FIFO before, were read out by the processor. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 timing and signal description of the THS1206 read timing (using R/W, CS0-controlled) Figure 13 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. tw(CS) 90% CS0 10% 10% CS1 III III III R/W tsu(R/W) th(R/W) 90% III III III 90% RD ta th 90% 90% D(0-11) td(CSDAV) 90% DATA_AV Figure 13. Read Timing Diagram Using R/W (CS0-controlled) read timing parameter (CS0-controlled) PARAMETER MIN tsu(R/W) ta Setup time, R/W high to last CS valid 0 Access time, last CS valid to data valid 0 td(CSDAV) th Delay time, last CS valid to DATA_AV inactive th(R/W) tw(CS) Hold time, first external CS invalid to R/W change 22 MAX 0 Pulse duration, CS active * DALLAS, TEXAS 75265 UNIT ns 10 12 Hold time, first CS invalid to data invalid POST OFFICE BOX 655303 TYP ns ns 5 ns 5 ns 10 ns SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 timing and signal description of the THS1206 (continued) write timing (using R/W, CS0-controlled) Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. tw(CS) 90% CS0 10% 10% CS1 IIII IIII tsu(R/W) III III th(R/W) WR RD tsu th 90% 90% D(0-11) IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII DATA_AV Figure 14. Write Timing Diagram Using R/W (CS0-controlled) write timing parameter (RD-controlled) PARAMETER MIN TYP MAX UNIT tsu(R/W) tsu Setup time, R/W stable to last CS valid 0 ns Setup time, data valid to first CS invalid 5 ns th th(R/W) Hold time, first CS invalid to data invalid 2 ns Hold time, first CS invalid to R/W change 5 ns tw(CS) Pulse duration, CS active 10 ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 interfacing the THS1206 to the TMS320C30/31/33 DSP The following application circuit shows an interface of the THS1206 to the TMS320C30/31/33 DSPs. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface. THS1206 TMS320C30/31/33 DVDD STRB A23 R/W INTX TOUT DATA CS0 CS1 RD R/W DATA_AV CONV_CLK DATA interfacing the THS1206 to the TMS320C54x using I/O strobe The following application circuit shows an interface of the THS1206 to the TMS320C54x. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface. THS1206 TMS320C54x DVDD CS0 CS1 RD R/W DATA_AV CONV_CLK DATA 24 POST OFFICE BOX 655303 I/O STRB A15 R/W INTX BCLK DATA * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 timing and signal description of the THS1206 (continued) read timing (using RD, RD-controlled) Figure 15 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0, CS1, and RD which becomes valid. CS0 CS1 WR IIII IIII tsu(CS) III III th(CS) tw(RD) 10% RD 10% ta th 90% 90% D(0-11) td(CSDAV) 90% DATA_AV Figure 15. Read Timing Diagram Using RD (RD-controlled) read timing parameter (RD-controlled) PARAMETER MIN tsu(CS) ta Setup time, RD low to last CS valid 0 Access time, last CS valid to data valid 0 td(CSDAV) th Delay time, last CS valid to DATA_AV inactive th(CS) tw(RD) Hold time, RD change to first CS invalid MAX 0 Pulse duration, RD active * DALLAS, TEXAS 75265 UNIT ns 10 12 Hold time, first CS invalid to data invalid POST OFFICE BOX 655303 TYP ns ns 5 ns 5 ns 10 ns 25 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 timing and signal description of the THS1206 (continued) write timing (using WR, WR-controlled) Figure 16 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal of CS0, CS1, and WR which becomes valid. CS0 CS1 tsu(CS) th(CS) tw(WR) WR 10% 10% IIIII IIIII RD tsu IIII IIII th 90% 90% D(0-11) DATA_AV IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII Figure 16. Write Timing Diagram Using WR (WR-controlled) write timing parameter using WR (WR-controlled) PARAMETER MIN TYP MAX UNIT tsu(CS) tsu Setup time, CS stable to last WR valid 0 ns Setup time, data valid to first WR invalid 5 ns th th(CS) Hold time, WR invalid to data invalid 2 ns Hold time, WR invalid to CS change 5 ns tw(WR) Pulse duration, WR active 10 ns 26 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 interfacing the THS1206 to the TMS320C6201 DSP The following application circuit shows an interface of the THS1206 to the TMS320C6201. The read (using RD, RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface. THS1206-1 TMS320C6201 CS0 CS1 RD WR DATA_AV DATA CONV_CLK CE1 EA20 ARE AWE EXT_INT6 DATA TOUT1 TOUT2 EA21 EXT_INT7 THS1206-2 CS0 CS1 RD WR DATA_AV DATA CONV_CLK analog input configuration and reference voltage The THS1206 features four analog input channels. These can be configured for either single-ended or differential operation. Best performance is achieved in differential mode. Figure 17 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference voltage). The analog input voltage range goes from VREFM to VREFP. This means that VREFM defines the minimum voltage, which can be applied to the ADC. VREFP defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V. The resulting analog input voltage swing of 2 V can be expressed by: V REFM v AINP v V REFP (1) VREFP AINP 12-Bit ADC VREFM Figure 17. Single-Ended Input Stage POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 analog input configuration and reference voltage (continued) A differential operation is desired for many applications. Figure 18 shows a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. This configuration has a few advantages, which are discussed in the following paragraphs. VREFP AINP + VADC 12-Bit ADC - AINM VREFM Figure 18. Differential Input Stage In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the input of the ADC is the difference between the input AINP and AINM. This means that VREFM defines the minimum voltage (VADC) which can be applied to the ADC. VREFP defines the maximum voltage (VADC) which can be applied to the ADC. The voltage VADC can be calculated as follows: V ADC + ABS(AINP-AINM) (2) An advantage to single-ended operation is that the common-mode voltage V CM + AINM ) AINP 2 (3) can be rejected in the differential configuration, if the following condition for the analog input voltages is true: AGND v AINM, AINP v AV 1VvV CM DD (4) v4V (5) In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection which is common to both analog inputs. See also Figure 20. single-ended mode of operation The THS1206 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the THS1206 must be driven from an operational amplifier that does not degrade the ADC performance. Because the THS1206 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc and ac coupling. An application example is shown for dc-coupled level shifting in the following section, dc coupling. 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 dc coupling An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS1206. The analog input voltage range of the THS1206 goes from 1.5 V to 3.5 V. An op-amp specified for 5-V single supply can be used as shown in Figure 19. Figure 19 shows an application example where the analog input signal in the range from -1 V up to 1 V is shifted by an op-amp to the analog input range of the THS1206 (1.5 V to 3.5 V). The op-amp is configured as an inverting amplifier with a gain of -1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT of the THS1206 by using a resistor divider. Therefore, the op-amp output voltage is centered at 2.5 V. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors. R 3.5 V 2.5 V 1.5 V 5V 1V 0V R _ THS1206 RS AINP -1 V 1.25 V + REFIN REFOUT R R Figure 19. Level-Shift for DC-Coupled Input differential mode of operation For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in differential mode. Mini Circuits T4-1 49.9 THS1206 R AINP C 200 R AINM C REFOUT Figure 20. Transformer Coupled Input POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) 70 SINAD - Signal-to-Noise and Distortion - dB THD - Total Harmonic Distortion - dB 80 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 65 60 55 50 45 40 0 1 2 3 4 5 6 7 0 1 fs - Sampling Frequency - MHz 2 Figure 21 5 6 7 SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (SINGLE-ENDED) 70 90 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 85 65 80 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 4 Figure 22 SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (SINGLE-ENDED) 75 70 65 60 55 50 60 55 50 45 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 45 40 40 0 1 2 3 4 5 6 7 0 1 2 3 4 Figure 23 Figure 24 POST OFFICE BOX 655303 5 fs - Sampling Frequency - MHz fs - Sampling Frequency - MHz 30 3 fs - Sampling Frequency - MHz * DALLAS, TEXAS 75265 6 7 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) 85 SINAD - Signal-to-Noise and Distortion - dB 80 THD - Total Harmonic Distortion - dB 80 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 75 70 65 60 55 50 45 40 0 1 2 3 4 5 6 7 0 1 2 fs - Sampling Frequency - MHz Figure 25 4 5 6 7 Figure 26 SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (DIFFERENTIAL) SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (DIFFERENTIAL) 80 100 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 95 90 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 75 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 3 fs - Sampling Frequency - MHz 85 80 75 70 65 60 55 50 70 65 60 55 50 45 45 40 40 0 1 2 3 4 5 6 7 fs - Sampling Frequency - MHz 0 1 2 3 4 5 6 7 fs - Sampling Frequency - MHz Figure 27 Figure 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) 80 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS SINAD - Signal-to-Noise and Distortion - dB THD - Total Harmonic Distortion - dB 85 75 70 65 60 55 50 45 40 0.0 0.5 1.0 1.5 2.0 2.5 75 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 70 65 60 55 50 45 40 0.0 3.0 0.5 fi - Input Frequency - MHz 2.5 3.0 SIGNAL-TO-NOISE vs INPUT FREQUENCY (SINGLE-ENDED) 80 100 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 75 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 90 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 2.0 Figure 30 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (SINGLE-ENDED) 85 80 75 70 65 60 55 50 70 65 60 55 50 45 45 40 0.0 0.5 1.0 1.5 2.0 2.5 fi - Input Frequency - MHz 3.0 40 0.0 0.5 1.0 1.5 Figure 32 POST OFFICE BOX 655303 2.0 fi - Input Frequency - MHz Figure 31 32 1.5 fi - Input Frequency - MHz Figure 29 95 1.0 * DALLAS, TEXAS 75265 2.5 3.0 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) 80 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS SINAD - Signal-to-Noise and Distortion - dB THD - Total Harmonic Distortion - dB 90 70 60 50 40 30 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 70 60 50 40 30 20 0.0 3.5 0.5 fi - Input Frequency - MHz SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (DIFFERENTIAL) 2.0 2.5 3.0 3.5 SIGNAL-TO-NOISE vs INPUT FREQUENCY (DIFFERENTIAL) 90 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 80 70 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 1.5 Figure 34 Figure 33 70 60 50 40 60 50 40 30 30 20 0.0 1.0 fi - Input Frequency - MHz AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 0.5 1.0 1.5 2.0 2.5 3.0 3.5 20 0.0 0.5 fi - Input Frequency - MHz 1.0 1.5 2.0 2.5 3.0 3.5 fi - Input Frequency - MHz Figure 35 Figure 36 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 33 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (DIFFERENTIAL) EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (SINGLE-ENDED) 12 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS ENOB - Effective Number of Bits - Bits ENOB - Effective Number of Bits - Bits 12 11 10 9 8 7 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 11 10 9 8 7 6 6 0 1 2 3 4 5 6 0 7 1 2 6 7 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (DIFFERENTIAL) EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (SINGLE-ENDED) 12 12 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS ENOB - Effective Number of Bits - Bits ENOB - Effective Number of Bits - Bits 5 Figure 38 Figure 37 11 10 9 8 7 0.5 1.0 1.5 2.0 2.5 3.0 3.5 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 11 10 9 8 7 6 0.0 0.5 1.0 1.5 2.0 Figure 40 Figure 39 POST OFFICE BOX 655303 2.5 fi - Input Frequency - MHz fi - Input Frequency - MHz 34 4 fs - Sampling Frequency - MHz fs - Sampling Frequency - MHz 6 0.0 3 * DALLAS, TEXAS 75265 3.0 3.5 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS GAIN vs INPUT FREQUENCY (SINGLE-ENDED) 5 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 0 G - Gain - dB -5 -10 -15 -20 -25 -30 0 10 20 30 40 50 60 70 80 90 100 110 120 fi - Input Frequency - MHz Figure 41 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 35 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM (4096 POINTS) (SINGLE-ENDED) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS Magnitude - dB 0 -20 -40 -60 -80 -100 -120 -140 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 f - Frequency - Hz Figure 42 FAST FOURIER TRANSFORM (4096 POINTS) (DIFFERENTIAL) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS Magnitude - dB 0 -20 -40 -60 -80 -100 -120 -140 0 500000 1000000 1500000 2000000 2500000 f - Frequency - Hz Figure 43 36 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3000000 3500000 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. differential nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than 1 LSB ensures no missing codes. zero offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. gain error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise ratio + distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. effective number of bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N+ (SINAD * 1.76) 6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 37 SGLS126A - JULY 2002 - REVISED FEBRUARY 2003 MECHANICAL DATA DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE 38 PINS SHOWN 0,30 0,19 0,65 38 0,13 M 20 6,20 NOM 8,40 7,80 0,15 NOM Gage Plane 1 19 0,25 A 0- 8 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 30 32 38 A MAX 11,10 11,10 12,60 A MIN 10,90 10,90 12,40 DIM 4040066 / D 11/98 NOTES: A. B. C. D. 38 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS1206MDAREP ACTIVE TSSOP DA 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03609-01XE ACTIVE TSSOP DA 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF THS1206-EP : THS1206 * Catalog: * Military: THS1206M NOTE: Qualified Version Definitions: - TI's standard catalog product * Catalog * Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS1206MDAREP Package Package Pins Type Drawing TSSOP DA 32 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 11.5 1.6 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS1206MDAREP TSSOP DA 32 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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