TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
135-mΩ -Maximum (5-V Input) High-Side
MOSFET Switch
D
500 mA Continuous Current
D
Short-Circuit and Thermal Protection With
Overcurrent Logic Output
D
Operating Range . . . 2.7 V to 5.5 V
D
Logic-Level Enable Input
D
2.5-ms Typical Rise Time
D
Undervoltage Lockout
D
10 µA Maximum Standby Supply Current
D
Bidirectional Switch
D
Available in 8-pin SOIC and PDIP Packages
D
Ambient Temperature Range, –40°C to 85°C
D
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
D
UL Listed – File No. E169910
description
The TPS2041 and TPS2051 power distribution switches are intended for applications where heavy capacitive
loads and short circuits are likely to be encountered. The TPS2041 and the TPS2051 are 135-mΩ N-channel
MOSFET high-side power switches. Each switch is controlled by a logic enable compatible with 5-V and 3-V
logic. Gate drive is provided by an internal charge pump that controls the power-switch rise times and fall times
to minimize current surges during switching. The charge pump requires no external components and allows
operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS2041 and TPS2051 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch,
causing the junction temperature to rise, a thermal protection circuit shuts off the switch in overcurrent to prevent
damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal
circuitry ensures the switch remains off until valid input voltage is present.
The TPS2041 and TPS2051 are designed to limit at 0.9-A load. These power distribution switches are available
in 8-pin small-outline integrated circuit (SOIC) and 8-pin plastic dual-in-line packages (PDIP) and operate over
an ambient temperature range of –40°C to 85°C.
AVAILABLE OPTIONS
RECOMMENDED
MAXIMUM CONTINUOUS
TYPICAL SHORT-CIRCUIT PACKAGED DEVICES
TAENABLE
MAXIMUM
CONTINUOUS
LOAD CURRENT
(A)
CURRENT LIMIT AT 25°C
(A) SOIC
(D)†PDIP
(P)
–40°C to 85°CActive low 0.5 0.9 TPS2041D TPS2041P
–40°C to 85°CActive high 0.5 0.9 TPS2051D TPS2051P
†The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2041DR)
Copyright 1999, Texas Instruments Incorporated
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
TPS2041
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
TPS2051
D OR P PACKAGE
(TOP VIEW)
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2041 functional block diagram
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
†Current Sense
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME D OR P
I/O
DESCRIPTION
TPS2041 TPS2051
EN 4 – I Enable input. Logic low turns on power switch.
EN – 4 I Enable input. Logic high turns on power switch.
GND 1 1 I Ground
IN 2, 3 2, 3 IInput voltage
OC 5 5 O Over current. Logic output active low
OUT 6, 7, 8 6, 7, 8 OPower-switch output
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled. The power switch supplies a minimum of 500 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (EN or EN)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on EN (TPS2041) or a logic low is present
on EN (TPS2051). A logic zero input on EN or a logic high on EN restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(IN) (see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO(OUT) (see Note 1) –0.3 V to VI(IN) + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI(ENx) or VI(ENx) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(OUT) internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . .
Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW
P1175 mW 9.4 mW/°C752 mW 611 mW
recommended operating conditions
TPS2041 TPS2051
UNIT
MIN MAX MIN MAX
UNIT
Input voltage, VI(IN) 2.7 5.5 2.7 5.5 V
Input voltage, VI(EN) or VI(EN) 0 5.5 0 5.5 V
Continuous output current, IO(OUT) 0 500 0 500 mA
Operating virtual junction temperature, TJ–40 125 –40 125 °C
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = Hi (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS†
TPS2041 TPS2051
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX MIN TYP MAX
UNIT
St ti d i t t
VI(IN) = 5 V, TJ = 25°C 80 95 80 95
Static drain-source on-state
resistance 5
-
Vo
p
eration
VI(IN) = 5 V, TJ = 85°C 90 120 90 120
resistance
,
5
-
V
o eration
VI(IN) = 5 V, TJ = 125°C 100 135 100 135 mΩ
DS(on)
St ti d i t t
VI(IN) = 3.3 V, TJ = 25°C 85 105 85 105
Static drain-source on-state
resistance 3 3
-
Vo
p
eration
VI(IN) = 3.3 V, TJ = 85°C 100 135 100 135
resistance
,
3
.
3
-
V
o eration
VI(IN) = 3.3 V, TJ = 125°C115 150 115 150
Rise time out
p
ut
VI(IN) = 5.5 V,
CL = 1 µF, TJ = 25°C,
RL = 10 Ω2.5 2.5
ms
r
Rise
time
,
o
u
tp
u
t
VI(IN) = 2.7 V,
CL = 1 µF, TJ = 25°C,
RL = 10 Ω3 3
ms
Fall time out
p
ut
VI(IN) = 5.5 V,
CL = 1 µF, TJ = 25°C,
RL = 10 Ω4.4 4.4
ms
f
Fall
time
,
o
u
tp
u
t
VI(IN) = 2.7 V,
CL = 1 µF, TJ = 25°C,
RL = 10 Ω2.5 2.5
ms
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input EN or EN
PARAMETER
TEST CONDITIONS
TPS2041 TPS2051
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 2 V
VIL
Low level in
p
ut voltage
4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 0.8 V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
2.7 V ≤ VI(IN) ≤ 4.5 V 0.4 0.4
II
In
p
ut current
TPS2041 VI(EN) = 0 V or VI(EN) = VI(IN) –0.5 0.5
µA
I
I
Inp
u
t
c
u
rrent
TPS2051 VI(EN) = VI(IN) or VI(EN) = 0 V –0.5 0.5 µ
A
ton T urnon time CL = 100 µF, RL = 10 Ω 20 20 ms
toff Turnoff time CL = 100 µF, RL = 10 Ω40 40
current limit
PARAMETER
TEST CONDITIONS†
TPS2041 TPS2051
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX MIN TYP MAX
UNIT
IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND,
Device enabled into short circuit 0.7 0.9 1.1 0.7 0.9 1.1 A
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = Hi (unless otherwise noted) (continued)
supply current
PARAMETER
TEST CONDITIONS
TPS2041 TPS2051
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
TJ = 25°C
0.015 1
Supply current, No Load EN = VI(IN) –40°C ≤ TJ ≤ 125°C
10
µA
y,
low-level output on OUT
EN=0V
TJ = 25°C
0.015 1 µ
A
EN
=
0
V
–40°C ≤ TJ ≤ 125°C
10
EN 0V
TJ = 25°C
80 100
Supply current, No Load
EN
=
0
V
–40°C ≤ TJ ≤ 125°C
100
µA
y,
high-level output on OUT
EN=V
I(IN)
TJ = 25°C
80 100 µ
A
EN
=
V
I(IN) –40°C ≤ TJ ≤ 125°C
100
Leakage current
OUT
connected
EN = VI(IN) –40°C ≤ TJ ≤ 125°C TPS2041 100
µA
Leakage
c
u
rrent
connec
t
e
d
to ground EN= 0 V –40°C ≤ TJ ≤ 125°C TPS2051 100 µ
A
Reverse leakage IN = High VI(EN) = 0 V
TJ=25
°
C
TPS2041 0.3
µA
g
current
g
impedance VI(EN) = Hi
T
J =
25°C
TPS2051 0.3 µ
A
undervoltage lockout
PARAMETER
TEST CONDITIONS
TPS2041 TPS2051
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV
overcurrent OC
PARAMETER
TEST CONDITIONS
TPS2041 TPS2051
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Sink current†VO = 5 V 10 10 mA
Output low voltage IO = 5 V, VOL(OC)0.5 0.5 V
Off-state current†VO = 5 V, VO = 3.3 V 1 1 µA
†Specified by design, not production tested.
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL CL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
50% 50%
90%
10%
VI(EN)
VO(OUT)
ton toff
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time
with 0.1-µF Load Figure 3. Turnoff Delay and Fall Time
with 0.1-µF Load
VO(OUT)
(2 V/div)
0123456
t – Time – ms 78910
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
VI(EN)
(5 V/div)
0 1000 2000 3000
t – Time – ms 4000 5000
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4. Turnon Delay and Rise Time
with 1-µF Load Figure 5. Turnoff Delay and Fall Time
with 1-µF Load
0123456
t – Time – ms 78910
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω
0 2 4 6 8 10 12
t – Time – ms 14 16 18 20
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
Figure 6. TPS2041, Short-Circuit Current,
Device Enabled into Short
012345 6
t – Time – ms 78910
IO(OUT)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
VI(EN)
(5 V/div)
Figure 7. TPS2041, Threshold Trip Current
with Ramped Load on Enabled Device
0102030405060
t – Time – ms 70 80 90 100
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
VO(OUT)
(2 V/div)
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 8. Inrush Current with 100-µF, 220-µF
and 470-µF Load Capacitance
0 2 4 6 8 10 12
t – Time – ms 14 16 18 20
VI(IN) = 5 V
TA = 25°C
RL = 10 Ω
VI(EN)
(5 V/div)
IO(OUT)
(o.2 A/div)
470 µF
220 µF
100 µF
Figure 9. Ramped Load on Enabled Device
VO(OC)
(5 V/div)
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
Load Ramp,1A/100 ms
TA = 25°C
0 20 40 60 80 100 120
t – Time – ms 140 160 180 200
Figure 10. 4-Ω Load Connected to Enabled Device
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
0 400 800 1200 1600 2000
VO(OC)
(5 V/div)
t – Time – µs
Figure 11. 1-Ω Load Connected
to Enabled Device
IO(OUT)
(1 A/div)
VI(IN) = 5 V
TA = 25°C
0 20 40 60 80 100 120 140 160 180 200
VO(OC)
(5 V/div)
t – Time – µs
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
4.5
4
3.5
32.5 3 3.5 4 4.5
Turn-On Delay – ms
5
5.5
TURNON DELAY
vs
INPUT VOLTAGE
6
5 5.5 6
VI – Input Voltage – V
CL = 1 µF
RL = 10 Ω
TA = 25°C
Figure 13
13
12
10
32.5 3 3.5 4 4.5
Turn-Off Delay – ms
15
16
TURNOFF DELAY
vs
INPUT VOLTAGE
17
5 5.5 6
14
11
VI – Input Voltage – V
CL = 1 µF
RL = 10 Ω
TA = 25°C
Figure 14
2.7
2.6
2.50.1 0.2 0.3 0.4 0.5
– Rise Time – ms
2.8
2.9
RISE TIME
vs
LOAD CURRENT
3
0.6 0.7 0.8 0.9
rt
IL – Load Current – A
VI(IN) = 5 V
CL = 1 µF
TA = 25°C
Figure 15
2.9
2.7
2.50.1 0.2 0.3 0.4 0.5
– Fall Time – ms
3.1
3.3
FALL TIME
vs
LOAD CURRENT
3.5
0.6 0.7 0.8 0.9
ft
IL – Load Current – A
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 16
70
60
50
–50 –25 0 25 50
– Supply Current, Output Enabled –
80
90
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
100
75 100 125 150
II(IN) Aµ
TJ – Junction Temperature – °C
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
Figure 17
500
300
100
–100
–50 –25 0 25 50 75
700
900
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
1000
100 125 150
800
600
400
200
0
– Supply Current, Output Disabled – nA
II(IN)
TJ – Junction Temperature – °C
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4 V
VI(IN) = 2.7 V
Figure 18
70
60
502.5 3 3.5 4 4.5
– Supply Current, Output Enabled –
80
90
SUPPLY CURRENT, OUTPUT ENABLED
vs
INPUT VOLTAGE
100
5 5.5 6
II(IN) Aµ
VI – Input Voltage – V
TJ = –40°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
Figure 19
400
200
0
–2002.5 3 3.5 4 4.5
600
800
SUPPLY CURRENT, OUTPUT DISABLED
vs
INPUT VOLTAGE
1000
5 5.5 6
– Supply Current, Output Disabled – nA
II(IN)
VI – Input Voltage – V
TJ = –40°C
TJ = 125°C
TJ = 85°CTJ = 25°C
TJ = 0°C
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
100
75
50
–50 –25 0 25 50 75
– Static Drain-Source On-State Resistance – m
125
150
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
175
100 125 150
Ω
rDS(on)
TJ – Junction Temperature – °C
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
IO = 0.5 A
Figure 21
100
75
502.5 3 3.5 4 4.5
125
150
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
175
5 5.5 6
– Static Drain-Source On-State Resistance – mΩ
rDS(on)
VI – Input Voltage – V
TJ = –40°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
IO = 0.5 A
Figure 22
50
25
00.1 0.2 0.4
– Input-to-Output Voltage – mV
75
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
100
0.5 0.6
VI(IN) –VO(OUT)
IL – Load Current – A
TA = 25°C
VI(IN) = 5 V
VI(IN) = 2.7 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
Figure 23
0.85
0.82.5 3 3.5 4
– Short-circuit Output Current – A
0.9
SHORT-CURCUIT OUTPUT CURRENT
vs
INPUT VOLTAGE
0.95
4.5 5 65.5
IOS
VI – Input Voltage – V
TJ = –40°C
TJ = 125°C
TJ = 25°C
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 24
1.15
1.125
1.12.5 3 3.5 4
Threshold Trip Current – A
1.175
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
1.2
4.5 5 65.5
VI – Input Voltage – V
TA = 25°C
Load Ramp = 1 A/10 ms
Figure 25
0.8
–50 –25 0 25 50
0.9
SHORT CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
0.95
75 100 125
0.85
TJ – Junction Temperature – °C
– Short-circuit Output Current – A
IOS
VI(IN) = 5 V
VI(IN) = 4 V
VI(IN) = 2.7 V
Figure 26
2.2
2.1
2
–50 –25 0 25 50 75
UVLO – Undervoltage Lockout – V
2.3
2.4
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
2.5
100 125 150
TJ – Junction Temperature – °C
Start Threshold
Stop Threshold
Figure 27
250
150
100
00 2.5 5 7.5
Current Limit Response –
350
450
Peak Current – A
CURRENT LIMIT RESPONSE
vs
PEAK CURRENT
500
10 12.5
400
300
200
50
sµ
VI(IN) = 5 V
TA = 25°C
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
4
2
00 2.5 5 7.5
Response Time –
6
Peak Current – A
OVERCURRENT RESPONSE TIME (OC)
vs
PEAK CURRENT
8
10 12.5
sµ
VI(IN) = 5 V
TA = 25°C
Figure 28
APPLICATION INFORMATION
IN
OC
EN GND
0.1 µF
2,3
5
4
6,7,8
0.1 µF 22 µF
Load
1
OUT
TPS2041
Power Supply
2.7 V to 5.5 V
Figure 29. Typical Application
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS2041 and TPS2051 sense the short
and immediately switch into a constant-current output.
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS2041 and TPS2051 are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter of 500 µs (see
Figure 30) can be connected to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic
capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing
a low-impedance energy source, thereby reducing erroneous overcurrent reporting.
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS2041
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS2041
Rpullup
V+
Rfilter
Rpullup
Cfilter
To USB
Controller
V+
Figure 30. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
temperature of interest and read rDS(on) from Figure 21. Next, calculate the power dissipation using:
PD
+
rDS
(
on
)
I
2
Finally, calculate the junction temperature:
TJ
+
PD
R
q
JA
)
TA
Where: TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS2041 and TPS2051 into constant current mode, which causes
the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce
EMI and voltage overshoots.
universal serial bus (USB) applications
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D
Hosts/self-powered hubs (SPH)
D
Bus-powered hubs (BPH)
D
Low-power, bus-powered functions
D
High-power, bus-powered functions
D
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2041 and
TPS2051 can provide power-distribution solutions for many of these classes of devices.
host/self-powered and bus-powered hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of
the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have
current limit protection and must report overcurrent conditions to the USB controller . T ypical SPHs are desktop
PCs, monitors, printers, and stand-alone hubs.
IN
OC
EN
GND
0.1 µF
2, 3
5
4
7
0.1 µF 120 µFGND
OUT
TPS2041
Power Supply
D+
D–
VBUS
Downstream
USB Ports
USB
Control
3.3 V 5 V
†
†May need RC Filter (see Figure 34)
Figure 31. One-Port Solution
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on powerup, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller , the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
low-power bus-powered functions and high-power bus-powered functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at powerup and
can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of
44 Ω and 10 µF at powerup, the device must implement inrush current limiting (see Figure 32).
IN
OC
EN
GND
0.1 µF2,3
5
4
6, 7, 8
0.1 µF 10 µF
GND
1
OUT
TPS2041
Power Supply
D+
D–
VBUS
USB
Control
3.3 V
10 µFInternal
Function
Figure 32. High-Power Bus-Powered Function
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
powe- distribution features must be implemented.
D
Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
D
Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)
D
Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS2041 and TPS2051 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable
and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input
ports for bus-power functions (see Figure 33).
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 33. Hybrid Self/Bus-Powered Hub Implementation
†USB rev 1.1 requires 120 µF per hub.
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D –
5 V
GND
D +
D –
5 V
D +
D –
5 V
D +
D –
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D –
Upstream
Port
TPS2041
SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2041 EN Input
OC EN
OUT
5 V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
GND
EN
OC
IN
TPS2041
OUT
EN
OC
IN
TPS2041
OUT
EN
OC
IN
TPS2041
OUT
EN
OC
IN
TPS2041
OUT
TPS76333
0.1 µF
0.1 µF
0.1 µF
0.1 µF
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
generic hot-plug applications (see Figure 34)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS2041 and TPS2051, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS2041 and TPS2051 also ensures the switch will be off after the card has been removed, and the switch
will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every
insertion of the card or module.
Power
Supply Block of
Circuitry
TPS2041
GND
IN
IN
EN
OUT
OUT
OUT
OC
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
Figure 34. Typical Hot-Plug Implementation
By placing the TPS2041 and TPS2051 between the VCC input and the rest of the circuitry, the input power will
reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing
a slow voltage ramp at the output of the device. This implementation controls system surge currents and
provides a hot-plugging mechanism for any device.
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
TPS2041, TPS2051
POWER-DISTRIBUTION SWITCHES
SLVS172A –AUGUST 1998 – REVISED APRIL 1999
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE
4040082/B 03/95
0.310 (7,87)
0.290 (7,37)
0.010 (0,25) NOM
0.400 (10,60)
0.355 (9,02)
58
41
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54) 0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated