HD74HC160/HD74HC161/
HD74HC162/HD74HC163
Synchronous Decade Counter (Direct Clear)
Synchronous 4-bit Binary Counter (Direct Clear)
Synchronous Decade Counter (Synchronous Clear)
Synchronous 4-bit Binary Counter (Synchronous Clear)
Description
The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the
HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waveform.
These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte
rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs
is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive
edge of clock the count operation will be unaffected.
All of these counters may be cleared by utilizing the clear input. The clear function on the HD74HC162
and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive
edge of clock while the clear input is held low.
The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the
counter is cleared immediately regardless of the clock.
Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy
cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the
Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows.
This pulse is approximately equal in duration to the high level portion of the QA outputs. The Ripple Carry
output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
Features
• High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
HD74HC160/HD74HC161/HD74HC162/HD74HC163
2
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs Outputs
Clock Clear*1Load Enable P Enable T Qn
L X X X Reset-clear
H L X X Load input data
H H H H Count
H H L X No count
H H X L No count
Note: 1. 162 and 163 Only-160 and 161 are Asynchronous Clear Devices
Decade Counter Binary Counter
Asynchronous clear HD74HC160P HD74HC161P
Synchronous clear HD74HC162P HD74HC163P
Pin Arrangement
1
2
3
4
5
6
7
8
Clear
Clock
A
B
C
D
Enable P
GND
VCC
QA
QB
QC
QD
Enable T
Load
16
15
14
13
12
11
10
9
(Top view)
CK
P
A
C
D
B
Ripple
Carry Ripple
Carry Output
Outputs
Data
Inputs
QA
QB
QD
T
QC
CLR
Load
HD74HC160/HD74HC161/HD74HC162/HD74HC163
3
DC Characteristics
Ta = 25°CTa = –40 to
+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Input voltage VIH 2.0 1.5 — — 1.5 — V
4.5 3.15 — — 3.15 —
6.0 4.2 — — 4.2 —
VIL 2.0 — — 0.5 — 0.5 V
4.5 — — 1.35 — 1.35
6.0 — — 1.8 — 1.8
Output voltage VOH 2.0 1.9 2.0 — 1.9 — V Vin = VIH or VIL IOH = –20 µA
4.5 4.4 4.5 — 4.4 —
6.0 5.9 6.0 — 5.9 —
4.5 4.18 — — 4.13 — IOH = –4 mA
6.0 5.68 — — 5.63 — IOH = –5.2 mA
VOL 2.0 — 0.0 0.1 — 0.1 V Vin = VIH or VIL IOL = 20 µA
4.5 — 0.0 0.1 — 0.1
6.0 — 0.0 0.1 — 0.1
4.5 — — 0.26 — 0.33 IOL = 4 mA
6.0 — — 0.26 — 0.33 IOL = 5.2 mA
Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND
Quiescent supply
current ICC 6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA
HD74HC160/HD74HC161/HD74HC162/HD74HC163
4
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°CTa = –40 to
+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Maximum clock fmax 2.0 — — 5 — 4 MHz
frequency 4.5 — — 25 — 20
6.0 — — 29 — 23
Propagation delay tPLH 2.0 — — 160 — 200 ns Clock to Q
time tPHL 4.5 — 18 32 — 40
6.0 — — 27 — 34
2.0 — — 225 — 280 ns Clear to Q
4.5 — 23 45 — 56 (HC160, HC161 only)
6.0 — — 38 — 48
2.0 — — 150 — 190 ns Enable T to Ripple Carry output
4.5 — 15 30 — 38
6.0 — — 26 — 33
2.0 — — 200 — 250 ns Clock to Ripple carry output
4.5 — 16 40 — 50
6.0 — — 34 — 43
Setup time tsu 2.0 125 — — 156 — ns Data to Clock
4.5 25 9 — 31 —
6.0 21 — — 26 —
2.0 125 — — 156 — Load to Clock
4.5 25 15 — 31 —
6.0 21 — — 26 —
2.0 125 — — 156 — Clear to Clock
4.5 25 — — 31 — (HC162, HC163 only)
6.0 21 — — 26 —
Hold time th2.0 0 — — 0 — ns
4.5 0 –7 — 0 —
6.0 0 — — 0 —
Removal time trem 2.0 100 — — 125 — ns
4.5 20 7 — 25 —
6.0 17 — — 21 —
HD74HC160/HD74HC161/HD74HC162/HD74HC163
5
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = 25°CTa = –40 to
+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Pulse width tw2.0 80 — — 100 — ns
4.5 16 6 — 20 —
6.0 14 — — 17 —
Output rise/fall tTLH 2.0 — — 75 — 95 ns
time tTHL 4.5 — 5 15 — 19
6.0 — — 13 — 16
Input capacitance Cin — — 5 10 — 10 pF
Function Table
Count Enable/Disable
Control Inputs Result at Outputs
Load Enable P Enable T QA to QDRipple Carry Output
H H H Count High when QA to QD are maximum
L H H No count
X L H No count High when QA to QD are maximum
X H L No count L
X L L No count L
HD74HC160/HD74HC161/HD74HC162/HD74HC163
6
Timing Diagram
HD74HC160/HD74HC162
Sequence illustrated in waveforms.
1. Clear outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two and three.
4. Inhibit
(Asynchronous)Clear(HC160)
Clear(HC162)
Clock(HC160)
Ripple
Carry
Output
Clear Load Count
0987321
Inhibit
Clock(HC162)
Enable P
Enable T
Load
Data
Inputs
Count
Enables
Outputs
A
B
C
D
QA
QB
QC
QD
(Synchronous)
HD74HC160/HD74HC161/HD74HC162/HD74HC163
7
HD74HC161/HD74HC163
Sequence illustrated in waveforms.
1. Clear outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit
(Asynchronous)Clear(HC161)
Clear(HC163)
Clock(HC161)
Ripple
Carry
Output
Clear Load Count
15141312 210
Inhibit
Clock(HC163)
Enable P
Enable T
Load
Data
Inputs
Count
Enables
Outputs
A
B
C
D
QA
QB
QC
QD
(Synchronous)
HD74HC160/HD74HC161/HD74HC162/HD74HC163
8
Logic Diagram
HD74HC160
Decade Counter with Asynchronous Clear
T1QA
QA
QA
QB
QC
QD
Ripple
Carry
Output
CLR
C
Load
Load
Load
Clock
Clear
Enable T
Enable P
D
C
B
A
C
P1
CLR
C
C
Load
Load
T2QB
QB
P2
CLR
C
C
Load
Load
T3
VCC
QC
QC
P3
CLR
C
C
Load
Load
T4QD
QD
P4
CLR
C
C
Load
Load
HD74HC160/HD74HC161/HD74HC162/HD74HC163
9
HD74HC161
4-bit Binary Counter with Asynchronous Clear
T1QA
QA
QA
QB
QC
QD
Ripple
Carry
Output
CLR
C
Load
Load
Load
Clock
Clear
Enable T
Enable P
D
C
B
A
C
P1
CLR
C
C
Load
Load
T2QB
QB
P2
CLR
C
C
Load
Load
T3QC
QC
P3
CLR
C
C
Load
Load
T4QD
QD
P4
CLR
C
C
Load
Load
HD74HC160/HD74HC161/HD74HC162/HD74HC163
10
HD74HC162
Decade Counter with Synchronous Clear
CK
QA
QB
QC
QD
RCO
CK
A
B
C
D
P
T
VCC
LD
CLR
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
Q
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
Q
Q
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
Q
Q
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
Q
Q
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
HD74HC160/HD74HC161/HD74HC162/HD74HC163
11
HD74HC163
4-bit Binary Counter with Synchronous Clear
CK
QA
QB
QC
QD
RCO
CK
A
B
C
D
P
T
LD
CLR
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
Q
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
Q
Q
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
Q
Q
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
Q
Q
T
CR
CR
LD
LD
LD·CLR
LD·CLR
CLR
IN
CLR
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
DP-16
Conforms
Conforms
1.07 g
Unit: mm
6.30
19.20
16 9
81 1.3
20.00 Max
7.40 Max
7.62
0.25+ 0.13
– 0.05
2.54 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.06 Max
0° – 15°
1.11 Max
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-16DA
—
Conforms
0.24 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
*0.22 ± 0.05
*0.42 ± 0.08
0.12
0.15
M
2.20 Max 5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
– 0.30
7.80
0.70 ± 0.20
0° – 8°
0.10 ± 0.10
1.15
1.27
0.40 ± 0.06
0.20 ± 0.04
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
1.27
16 9
18
0.15
0.25 M
1.75 Max 3.95
*0.22 ± 0.03
9.9
0° – 8°
10.3 Max
+ 0.10
– 0.30
6.10
+ 0.67
– 0.20
0.60
+ 0.11
– 0.04
0.14
*0.42 ± 0.08
0.635 Max
0.40 ± 0.06
0.20 ± 0.03
1.08
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
TTP-16DA
—
—
0.05 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.50 ± 0.10
0° – 8°
*0.17 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
18
16 9
4.40
5.00
5.30 Max
0.07+0.03
–0.04
0.65 Max
1.0
0.20 ± 0.06
+ 0.08
– 0.07
*0.22
0.15 ± 0.04
Cautions
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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