M•CORE CMB21 14RG/D REV 1
MOTOROLA 3
The Patch_for_CodeWarrior_for_MCore R2.0 directory contains another directory:
CodeWarrior for MCore R2.0.
2. Copy the CodeWarrior for MCore R2.0 directory.
3. Navigate to the following location on your computer:
{CodeWarrior for M•CORE Installation directory}\Metrowerks.
4. Paste the copied CodeWarrior for MCore R2.0 directory to the {CodeWarrior for
M•CORE Installation directory}\Metrowerks direct ory. A dialog box will notify
you that the copied files will replace the original files in the {CodeWarrior for M•CORE
Installation directory}\Metrowerks\CodeWarrior for MCore R2.0
directory.
5. Click Yes to All. The required files will be replaced from or added to the CodeWarrior layout.
6 Factor y Hin ts
1. The first production lot o f CMB2114 assembli es were produced with an early mask set of
the MMC2114 which has a limitation in the clock module. Because of this limitation, the
device cannot be clocked by a crystal. The CMB’s with this c locking limitation has an
MMC21 14 marked with date code “HECC0205“ on it. For these CM B’s, the only clocking
modes that can be used are Normal PLL with Ex ternal Clock Referenc e Mode or External
Clock Mode (PLL disabled). The factory default clock mode is Normal PLL with External
Clock Reference Mode. The CMB2114 User Manual describes settings for jumpers W3, W4
and W5 to change to External Clock Mode, if desired. The device on these initial production
CMB’s will fail to start clocking if they are configured for Normal PLL with Crystal Oscillator
Reference Mode.
2. An issue exists concerning the Device Driver Library for the MMC2114. The first production
version of the library, version 1.10, has not been updated to support s ome of the features of
the MMC2114 th at has been changed from the M M C 2107 .
a. This version of the library does not have support for the low-voltage detection (LVD)
capability new to the MMC2114. LVD has the capability of generating either a reset or
an interrupt. The vector for this interrupt is shared with t he EPORT’s INT0 vector, so it
was not necessary to change any of the library f unctions for the Interrupt Controller
(ITCN) or its accompany ing driver (ITCN_B). However, t he drivers for the Res et
Controller (Reset_A) do not ac curately reflect the change in stru cture of the Reset
Status Register in that it does not include the LVD Reset bit.
b. The Reset Control Register has been expanded in the MMC2114 to support LVD, and
this control has not been incorporated into the drivers for the Reset Controller.
c. In the QADC driver module, QADC64_A, the QADC clock setup in the QADC Control
Register 0 (QACR0) has been simplified from that of the MMC2107, and the
QADC64_ A_Init function still takes parameters specific to the 2107’s QACR0.
Furthermore, this function supports the setting of PORTQA’s dat a direction, but does
not allow for th e setting of PORTQB’s data direction. This port was changed to allow
for both input or output configuration on the MMC21 14, where the MMC2107’ s
PORTQB was input only.
3. The Second Generation FLASH for M·Core (SGFM) found on the MMC2114 has a feature
that allows the FLASH to be secured from external access. Secu rity is enabled by having
the value $0000000 B programm ed in the 4-byte Security Word field (at $228-$22B) in the
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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