Ordering Information and Functional Diagram appears at
end of data sheet.
General Description
The MAX98358 is a digital pulse-density modulated
(PDM) input Class D power amplifier that provides Class
AB audio performance with Class D efficiency. This IC
offers five selectable gain settings (3dB, 6dB, 9dB, 12dB,
and 15dB) set by a single gain-select input (GAIN). The IC
can be configured to produce a left channel, right channel,
or (left/2 + right/2) output from the stereo input data.
The MAX98358 takes a stereo pulse density modulated
(SPDM) input signal directly into the DAC. Data on the
rising edge of PDM_CLK is considered left-channel data
while data on the falling PDM_CLK edge is right channel.
A mono sum feature is also implemented with SPDM data
input by summing the data from both rising and falling
clock edges.
Active emissions-limiting, edge-rate limiting, and over-
shoot control circuitry greatly reduce EMI. A filterless
spread-spectrum modulation scheme eliminates the need
for output filtering found in traditional Class D devices and
reduces the component count of the solution.
The IC is available in 9-pin WLP (1.345mm x 1.435mm
x 0.64mm) and 16-pin TQFN (3mm x 3mm x 0.75mm)
packages and is specified over the -40°C to +85°C tem-
perature range.
Applications
●Notebook and Netbook Computers
●Cellular Phones
●Tablets
●Portable Media Players
Features
●Single-Supply Operation (2.5V to 5.5V)
● 3.2W Output Power into 4Ω at 5V
●1.8mA Quiescent Current (VDD = 3.7V)
●92% Efficiency (RL = 8Ω, POUT = 1.5W)
●29µVRMS Output Noise (AV = 6dB)
●Low 0.015% THD+N at 1kHz
●Supported PDM_CLK Rates of 1.84MHz–4.32MHz
and 5.28MHz–8.64MHz
●Supports Left, Right, or Left/2 + Right/2 Outputs
●Sophisticated Edge Rate Control Enables Filterless
Class D Outputs
●77dB PSRR at 217Hz
●Low RF Susceptibility Rejects TDMA
Noise from GSM Radios
●Extensive Click-and-Pop Reduction Circuitry
●Robust Short-Circuit and Thermal Protection
●Available in Space-Saving Packages:
1.345mm x 1.435mm WLP (0.4mm Pitch)
3mm x 3mm TQFN
19-6786; Rev 5; 8/17
Simplied Block Diagram
DAC
CLASS D
OUTPUT
STAGE
DIGITAL
AUDIO
INTERFACE
PDM
INPUT
GAIN
CONTROL
SHUTDOWN
AND
CHANNEL
SELECT
MAX98358
MAX98358 PDM Input Class D Audio Power Amplifier
EVALUATION KIT AVAILABLE
TABLE OF CONTENTS
General Description ............................................................................ 1
Applications .................................................................................. 1
Features ..................................................................................... 1
Simplified Block Diagram........................................................................ 1
Absolute Maximum Ratings ...................................................................... 4
Package Thermal Characteristics ................................................................. 4
Electrical Characteristics ........................................................................ 4
Typical Operating Characteristics ................................................................. 7
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Speaker Amplifier ............................................................................8
Bump/Pin Configurations ....................................................................... 15
Bump/Pin Description.......................................................................... 15
Detailed Description........................................................................... 16
Digital Audio Interface........................................................................16
Supported PDM_CLK Rates ................................................................16
PDM_CLK Jitter Tolerance .................................................................16
PDM Timing Characteristics ................................................................17
Standby Mode ...........................................................................17
S D_M O D E Pin and Shutdown Operation .........................................................17
Class D Speaker Amplifier ....................................................................18
Ultra-Low EMI Filterless Output Stage ........................................................18
Speaker Current Limit .....................................................................18
Gain Selection ...........................................................................18
Click-and-Pop Suppression .................................................................18
Filterless Class D Operation...................................................................22
Power-Supply Input..........................................................................22
Layout and Grounding........................................................................22
WLP Applications Information..................................................................22
Functional Diagram ........................................................................... 23
Ordering Information .......................................................................... 23
Package Information .......................................................................... 24
Revision History .............................................................................. 27
MAX98358 PDM Input Class D Audio Power Amplier
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LIST OF FIGURES
LIST OF TABLES
Figure 1. PDM Audio Interface Timing Diagram ...................................................... 7
Figure 2. PDM Digital Audio Interface Timing ....................................................... 17
Figure 3. SD_MODE Resistor Connection Using Open-Drain Driver ...................................... 19
Figure 4. SD_MODE Resistor Connection Using Push-Pull Driver ....................................... 19
Figure 5. EMI with 12in of Speaker Cable and No Output Filtering....................................... 19
Figure 6. Left-Channel Operation with 6dB Gain .................................................... 20
Figure 8. Right-Channel Operation with 6dB Gain ................................................... 20
Figure 7. Left-Channel Operation with 12dB Gain .................................................... 20
Figure 9. Stereo Operation Using Two MAX98358s .................................................. 21
Figure 10. Monomix (Left/2 + Right/2) PDM Operation with 6dB Gain .................................... 22
Figure 11. MAX98358 WLP Ball Dimensions ....................................................... 22
Table 1. PDM_CLK Channel Select............................................................... 16
Table 2. PDM_CLK Rates ...................................................................... 16
Table 3. Calculated PDM_CLK Rates ............................................................. 16
Table 4. RMS Jitter Tolerance ................................................................... 16
Table 5. SD_MODE Control ..................................................................... 17
Table 6. Examples of SD_MODE Pullup Resistor Values............................................... 18
Table 7. Gain Selection ........................................................................ 18
MAX98358 PDM Input Class D Audio Power Amplier
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VDD, PDM_CLK and PDM_DATA to GND ..............-0.3V to +6V
All Other Pins to GND .............................. -0.3V to (VDD + 0.3V)
Continuous Current In/Out of VDD/GND/OUT_ ..................±1.6A
Continuous Input Current (all other pins) .........................±20mA
Duration of OUT_ Short Circuit to GND or VDD….. ...Continuous
Duration of OUTP Short to OUTN .............................Continuous
Continuous Power Dissipation ..............................(TA = +70°C)
WLP (derate 13.7mW/°C above +70°C)....................1096mW
TQFN (derate 20.8mW/°C above +70°C)..................1666mW
Junction Temperature .....................................................+150°C
Operating Temperature Range .......................... -40°C to +85°C
Storage Temperature Range ............................ -65°C to +150°C
Soldering Temperature (reflow) ......................................+260°C
Lead Temperature (soldering, 10s, TQFN) .....................+300°C
WLP
Junction-to-Ambient Thermal Resistance (θJA) ..........73°C/W
Junction-to-Case Thermal Resistance (θJC) ...............50°C/W
TQFN
Junction-to-Ambient Thermal Resistance (θJA) ..........48°C/W
Junction-to-Case Thermal Resistance (θJC) .................7°C/W
(Note 1)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage Range VDD Guaranteed by PSSR test 2.5 5.5 V
Undervoltage Lockout UVLO 1.4 1.8 2.3 V
Quiescent Current IDD
TA = +25°C 2.2 2.7 mA
TA = +25°C, VDD = 3.7V 1.8 2.2
Shutdown Current ISHDN SD_MODE = 0V, TA = +25°C 0.6 2 µA
Standby Current ISTNDBY SD_MODE = 1.8V, no PDM_CLK,
TA = +25°C 340 400 µA
Turn-On Time tON Time from receipt of rst clock cycle to full
operation 0.6 0.7 ms
Output O󰀨set Voltage VOS TA = +25°C, gain = 15dB ±0.3 ±2.5 mV
Click-and-Pop Level KCP
Peak voltage, TA =
+25°C, A-weighted,
32 samples per
second (Note 3)
Into shutdown -72
dBV
Out of shutdown -66
Power-Supply Rejection Ratio PSRR
VDD = 2.5V to 5.5V, TA = +25°C 60 75
dB
TA = +25°C
(Notes 3, 4)
f = 217Hz,
200mVP-P ripple 77
f = 10kHz,
200mVP-P ripple 60
MAX98358 PDM Input Class D Audio Power Amplier
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(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Power (Note 3) POUT
THD+N 10%
ZSPK = 4Ω + 33µH 3.2
W
ZSPK = 8Ω + 68µH 1.8
ZSPK = 8Ω + 68µH,
VDD = 3.7V 0.93
THD+N = 1%
ZSPK = 4Ω + 33µH 2.5
ZSPK = 8Ω + 68µH 1.4
ZSPK = 8Ω + 68µH,
VDD = 3.7V 0.77
Total Harmonic Distortion +
Noise THD+N
f = 1kHz, POUT = 1W, TA = +25°C,
ZSPK = 4Ω + 33µH (WLP) 0.02 0.06
%
f = 1kHz, POUT = 1W, TA = +25°C,
ZSPK = 4Ω + 33µH (TQFN) 0.02
f = 1kHz, POUT = 0.5W, TA = +25µC,
ZSPK = 8Ω + 68FH 0.013
Dynamic Range DR A-weighted, PDM_CLK = 6.144MHz,
VRMS = 2.54V 99 dB
Output Noise VNA-weighted (Note 4) 29 µVRMS
Gain (Relative to a 2.1dBV
Reference Level) AV
GAIN = GND through 100kΩ 14.4 15 15.6
dB
GAIN = GND 11.4 12 12.6
GAIN = unconnected 8.4 9 9.6
GAIN = VDD 5.4 6 6.6
GAIN = VDD through 100kΩ 2.4 3 3.6
Current Limit ILIM 2.8 A
E󰀩ciency hZSPK = 8Ω + 68µH, THD+N = 10%,
f = 1kHz, gain = 12dB 92 %
DAC Gain Error 1 %
Frequency Response ±0.5 dB
Class D Oscillator Frequency fOSC 330 kHz
Spread-Spectrum Bandwidth ±20 kHz
DIGITAL AUDIO INTERFACE
PDM_CLK High Frequency
Range fCLKH 5.28 8.64 MHz
PDM_CLK Low Frequency
Range fCLKL 1.84 4.32 MHz
PDM_CLK High Time tPDM_CLKH 40 ns
PDM_CLK Low Time tPDM_CLKL 40 ns
Maximum Low-Frequency
PDM_CLK Jitter RMS jitter below 40kHz 0.5 ns
Maximum Low-Frequency
PDM_CLK Jitter RMS jitter above 40kHz 12 ns
MAX98358 PDM Input Class D Audio Power Amplier
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(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Note 2: 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design.
Note 3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For
RL = 8Ω, LL = 68µH. For RL = 4Ω, LL = 33µH.
Note 4: Digital silence used for input signal.
Note 5: Dynamic range is measured using the EIJA method. -60dbFS 1kHz output signal. A-weighted and normalized to 0dBFS.
f = 20Hz to 20kHz.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH Digital audio inputs 1.3 V
Input Low Voltage VIL Digital audio inputs 0.6 V
Input Leakage Current IIH, IIL VIN = 0V, VDD = 5.5V, TA = +25°C -1 +1 µA
Input Capacitance CIN 3 pF
PDM Ones Density Maximum 75 %
Minimum 25
PDM_DATA to PDM_CLK
Setup Time tSETUP 10
ns
PDM_DATA to PDM_CLK
Hold Time tHOLD 10
SD_MODE COMPARATOR TRIP POINTS
B0
See SD_MODE and shutdown operation
for details
0.08 0.16 0.355
VB1 0.65 0.77 0.825
B2 1.245 1.4 1.5
SD_MODE Pulldown Resistor RPD 92 100 108 kΩ
GAIN COMPARATOR TRIP POINTS
VGAIN
AV = 3dB gain 0.65 x
VDD
0.85 x
VDD
V
AV = 6dB gain 0.9 x
VDD
VDD
AV = 9dB gain 0.4 x
VDD
0.6 x
VDD
AV = 12dB gain 0 0.1 x
VDD
AV = 15dB gain 0.15 x
VDD
0.35 x
VDD
Electrical Characteristics (continued)
MAX98358 PDM Input Class D Audio Power Amplier
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(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Figure 1. PDM Audio Interface Timing Diagram
Typical Operating Characteristics
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 110
THDN (dB)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
6kHz
1kHz
100Hz
VDD = 3.7V
ZSPK = 8Ω + 68μH
toc03
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 110
THDN (dB)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
6kHz
1kHz 100Hz
VDD = 4.2V
ZSPK = 8Ω + 68μH
toc04
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 110
THDN (dB)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
6kHz
1kHz 100Hz
VDD = 5V
ZSPK = 8Ω + 68μH
toc05
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SHUTDOWN CURRENT (µA)
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
VDDIO = 1.8V
toc02
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
QUIECENT CURRENT (mA)
SUPPLY VOLTAGE (V)
QUIECENT CURRENT
vs. SUPPLY VOLTAGE
VDDIO = 1.8V
toc01
tPDM_CLK
PDM_CLK
PDM_DATA
tPDM_CLKH
tSETUP tSETUP
tHOLD tHOLD
tPDM_CLKL
LEFT RIGHT LEFT RIGHT
MAX98358 PDM Input Class D Audio Power Amplier
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(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 110
THDN (dB)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
6kHz
1kHz 100Hz
VDD = 4.2V
ZSPK = 4Ω + 33μH
toc07
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
THD+N RATIO(dB)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT FREQUENCY
POUT = 500mW
P
OUT
= 100mW
VDD = 4.2V
ZSPK = 8Ω + 68μH
toc10
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 110
THDN (dB)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
6kHz
1kHz 100Hz
VDD = 5V
ZSPK = 4Ω + 33μH
toc08
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
THD+N RATIO(dB)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT FREQUENCY
POUT = 850mW
POUT = 150mW
VDD = 5V
ZSPK = 8Ω + 68μH
toc11
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 110
THDN (dB)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
6kHz
1kHz 100Hz
VDD = 3.7V
ZSPK = 4Ω + 33μH
toc06
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
THD+N RATIO(dB)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT FREQUENCY
POUT = 350mW
POUT = 75mW
VDD = 3.7V
ZSPK = 8Ω + 68μH
toc09
MAX98358 PDM Input Class D Audio Power Amplier
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(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
THD+N RATIO(dB)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT FREQUENCY
POUT = 850mW
POUT = 250mW
VDD = 4.2V
ZSPK = 4Ω + 33μH
toc13
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
110 100
OUTPUT POWER (W)
LOAD RESISTANCE
OUTPUT POWER vs.
LOAD RESISTANCE
VDD = 4.2V
1% THD+N
10% THD+N
toc16
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
THD+N RATIO(dB)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT FREQUENCY
POUT = 1.5W
P
OUT
= 350mW
VDD = 5V
ZSPK = 4Ω + 33μH
toc14
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
110 100
OUTPUT POWER (W)
LOAD RESISTANCE
OUTPUT POWER
vs. LOAD RESISTANCE
VDD = 5V
1% THD+N
10% THD+N
toc18
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
THD+N RATIO(dB)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT FREQUENCY
POUT = 600mW
P
OUT
= 150mW
VDD = 3.7V
ZSPK = 4Ω + 33μH
toc12
0.0
0.5
1.0
1.5
2.0
2.5
110 100
OUTPUT POWER (W)
LOAD RESISTANCE
OUTPUT POWER vs.
LOAD RESISTANCE
VDD = 3.7V
1% THD+N
10% THD+N
toc15
MAX98358 PDM Input Class D Audio Power Amplier
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(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
OUTPUT POWER
vs. SUPPLY VOLTAGE
THD+N = 1%
THD+N = 10%
ZSPK = 4Ω + 33µH
toc19
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT POWER (W)
EFFICIENCY vs. OUTPUT POWER
V
DD
= 5V
V
= 4.2V
V
DD
= 3.7V
ZSPK = 8Ω + 68μH
toc22
-3
-2
-1
0
1
2
3
10 100 1000 10000 100000
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
NORMALIZED GAIN
vs. FREQUENCY
NORMALIZED TO 1kHz
toc20
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.001 0.01 0.1 110
POWER DISSIPATION (W)
OUTPUT POWER (W)
POWER DISSIPATION
vs. OUTPUT POWER
V
DD
= 5V
V
DD
= 4.2V
VDD = 3.7V
Z
SPK
= 8Ω + 68μH
toc23
0.0
0.5
1.0
1.5
2.0
2.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
OUTPUT POWER
vs. SUPPLY VOLTAGE
THD+N = 1%
THD+N = 10%
ZSPK = 8Ω + 68µH
toc18
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0
EFFICIENCY (%)
OUTPUT POWER (W)
EFFICIENCY
vs. OUTPUT POWER
V
DD
= 5V
V
DD
= 4.2V
VDD = 3.7V
ZSPK = 8Ω + 68μH
toc21
MAX98358 PDM Input Class D Audio Power Amplier
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(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT POWER (W)
EFFICIENCY vs. OUTPUT POWER
V
DD
= 5V
V
DD
= 4.2V
V
DD
= 3.7V
Z
SPK
= 4Ω + 33μH
toc25
0
10
20
30
40
50
60
70
80
90
100
2.50 3.00 3.50 4.00 4.50 5.00 5.50
PSRR (dB)
SUPPLY VOLTAGE (V)
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE
ZSPK = 8Ω + 68µH
toc28
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.001 0.01 0.1 110
POWER DISSIPATION (W)
OUTPUT POWER (W)
POWER DISSIPATION
vs. OUTPUT POWER
V
DD
= 5V
V
DD
= 4.2V
V
DD
= 3.7V
ZSPK = 4Ω + 33μH
toc26
TURN-ON RESPONSE
OUTPUT
1V/div
SD_MODE
1V/div
toc29
2ms/div
0
10
20
30
40
50
60
70
80
90
100
0123
EFFICIENCY (%)
OUTPUT POWER (W)
EFFICIENCY vs. OUTPUT POWER
V
DD
= 5V
VDD = 4.2V
VDD = 3.7V
ZSPK = 4Ω + 33μH
toc24
0
10
20
30
40
50
60
70
80
90
100
10 100 1000 10000 100000
PSRR (dB)
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
ZSPK = 8Ω + 68µH
toc27
MAX98358 PDM Input Class D Audio Power Amplier
Maxim Integrated
│
11
www.maximintegrated.com
(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 6.144MHz
ZSPK = 8Ω + 68μH
toc31
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 5.6448MHz
ZSPK = 8Ω + 68μH
toc34
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 6.144MHz
ZSPK = 8Ω + 68μH
toc32
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 5.6448MHz
ZSPK = 8Ω + 68μH
toc35
TURN-OFF RESPONSE
OUTPUT
1V/div
SD_MODE
1V/div
toc30
1ms/div
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 6.144MHz
ZSPK = 8Ω + 68μH
toc33
MAX98358 PDM Input Class D Audio Power Amplier
Maxim Integrated
│
12
www.maximintegrated.com
(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 3.072MHz
ZSPK = 8Ω + 68μH
toc37
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 2.8224MHz
ZSPK = 8Ω + 68μH
toc40
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 3.072MHz
ZSPK = 8Ω + 68μH
toc38
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 2.8224MHz
ZSPK = 8Ω + 68μH
toc41
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 5.6448MHz
ZSPK = 8Ω + 68μH
toc36
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 3.072MHz
ZSPK = 8Ω + 68μH
toc39
MAX98358 PDM Input Class D Audio Power Amplier
Maxim Integrated
│
13
www.maximintegrated.com
(VDD = 5V, VGND = 0V, GAIN = GND (12dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 2.048MHz
ZSPK = 8Ω + 68μH
toc43
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 2.048MHz
ZSPK = 8Ω + 68μH
toc44
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 2.8224MHz
ZSPK = 8Ω + 68μH
toc42
-140
-120
-100
-80
-60
-40
-20
0
20
05000 10000 15000 20000
AMPLITUDE (dBV)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
fPDMCLK = 2.048MHz
ZSPK = 8Ω + 68μH
toc45
MAX98358 PDM Input Class D Audio Power Amplier
Maxim Integrated
│
14
www.maximintegrated.com
WLP
TOP VIEW
BUMP SIDE DOWN
GNDPDM_CLK GND
GAINPDM_DATA OUTN
VDD
SD_MODE OUTP
MAX98358
+
A1
B1
C1 C2 C3
B2 B3
A3A2
15
16
14
13
5
6
7
GND
SD_MODE
8
PDM_DATA
OUTN
OUTP
N.C.
1 3
GND
4
12 10 9
GND
PDM_CLK
VDD
VDD
N.C.
N.C.
GAIN GND
2
11
N.C.
TQFN
MAX98358
TOP VIEW
+
Bump/Pin Description
Bump/Pin Congurations
BUMP PIN NAME FUNCTION
WLP TQFN
A1 4 SD_MODE Shutdown and Channel Select. Determines left, right, or (left/2 + right/2) mix and also used for
shutdown. See Table 5.
A2 7, 8 VDD Power-Supply Input
A3 9 OUTP Positive Speaker Amplier Output
B1 1 PDM_DATA Digital Input Signal
B2 2 GAIN
Amplier Gain
Gain Connections Gain (dB)
GND through 100kΩ resistor 15
GND 12
Unconnected 9
VDD 6
VDD through 100kΩ resistor 3
B3 10 OUTN Negative Speaker Amplier Output
C1 16 PDM_CLK PDM Bit Clock Input Signal. Supports frequency ranges: 1.84MHz–4.32MHz and 5.28 MHz–
8.64MHz.
C2, C3 3, 11,
14, 15 GND Ground
—5, 6,
12, 13 N.C. No Connection
— — EP Exposed Pad. The exposed pad is not internally connected. Connect the exposed pad to a solid
ground plane for thermal dissipation.
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
15
Detailed Description
The MAX98358 is a digital PDM input Class D power
amplifier. The PDM modulation scheme uses the relative
density of digital pulses to represent the amplitude of an
analog signal. The IC accepts stereo PDM data through
PDM_DATA and PDM_CLK.
SD_MODE selects which audio channel is output by the
amplifier and is used to put the IC into shutdown. The
GAIN pin offers five gain settings and allows the output of
the amplifier to be tuned to the appropriate level.
The output stage features low-quiescent current, com-
prehensive click-and-pop suppression, and excellent RF
immunity. The IC offers Class AB audio performance with
Class D efficiency in a minimal board-space solution. The
Class D amplifier features spread-spectrum modulation
with edge-rate and overshoot control circuitry that offers
significant improvements in switch-mode amplifier radi-
ated emissions. The amplifier features click-and-pop sup-
pression that reduces audible transients on startup and
shutdown. The amplifier includes thermal-overload and
short-circuit protection.
Digital Audio Interface
The IC takes a stereo PDM input signal directly into the
DAC. Data read on the rising edge of PDM_CLK is left-
channel data while data read on the falling PDM_CLK
edge is right channel (Table 1).
Supported PDM_CLK Rates
Table 2 indicates the range of PDM_CLK rates that are
supported by the IC. Table 3 indicates the specific clock
rates to use based on the baseband rate and the overs-
ample rate of the incoming PDM signal.
PDM_CLK Jitter Tolerance
The IC features a very high PDM_CLK jitter tolerance of
0.5ns for RMS jitter below 40kHz and 12ns for wideband
RMS jitter while maintaining a dynamic range greater than
98dB (Table 4).
*The mono left/2 + right/2 feature is not supported at PDM_CLK rates of 5.28MHz and above.
Table 1. PDM_CLK Channel Select
Table 2. PDM_CLK Rates
Table 4. RMS Jitter Tolerance
Table 3. Calculated PDM_CLK Rates
PDM_CLK EDGE
DIRECTION CHANNEL
Rising edge Left
Falling edge Right
SUPPORTED CLOCK RATES (MHz)
1.84–4.32
5.28–8.64
FREQUENCY RMS JITTER TOLERANCE (ns)
< 40kHz 0.5
40kHz–PDM_CLK 12
BASEBAND SAMPLE
RATE (kHz)
INPUT CLOCK RATES (MHz)
32x OVERSAMPLED
PDM
64x OVERSAMPLED
PDM
128x OVERSAMPLED
PDM
256x OVERSAMPLED
PDM
8 — — — 2.048
16 — — 2.048 4.096
32 — 2.048 4.096 —
44.1 — 2.8224 5.6448* —
48 — 3.072 6.144* —
88.2 2.8224 5.6448* — —
96 3.072 6.144* — —
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
16
PDM Timing Characteristics
Figure 2 shows the PDM operation of the IC. The bit-
depth is one bit and each bit alternates between left-
channel and right-channel data.
If the PDM generator produces data that is stuck at logic-
high or logic-low, then the output of the IC is railed, forc-
ing DC at the load. Therefore, it is recommended that the
PDM generator includes protection to detect this invalid
condition. If such a condition is detected, then the IC
should either be put into shutdown or PDM_CLK should
be stopped.
Standby Mode
The MAX98358 automatically enters standby mode when
PDM_CLK is removed. In standby mode, the Class D
speaker amplifier is turned off and the outputs go into
a high-impedance state, ensuring that the unwanted
current is not transferred to the load during this condi-
tion. Standby mode should not be used in place of the
shutdown mode because the shutdown mode provides
the lowest power consumption and the best power-on/off
click-and-pop performance.
SD_MODE Pin and Shutdown Operation
The IC features a low-power shutdown mode, drawing
less than 0.6µA (typ) of supply current. During shutdown,
all internal blocks are turned off, including setting the
output stage to a high-impedance state. Drive SD_MODE
low to put the IC into shutdown.
The state of SD_MODE determines the audio channel
that is sent to the amplifier output (Table 5).
Drive SD_MODE high to select the left channel of the
stereo input data. Drive SD_MODE high through a suf-
ficiently small resistor to select the right channel of
the stereo input data. Drive SD_MODE high through a
sufficiently large resistor to select monomix mode where
both the left and right words of the stereo input data are
summed (left/2 + right/2). The monomix (left/2 + right/2)
mode is not supported for PDM_CLK rates 5.28MHz.
and above. RLARGE and RSMALL are determined by
the VDDIO voltage (logic voltage from control interface)
that is driving SD_MODE according to the following two
equations:
RSMALL (kΩ) = 94.0 x VDDIO - 100
RLARGE (kΩ) = 222.2 x VDDIO - 100
Figure 2. PDM Digital Audio Interface Timing
Table 5. SD_MODE Control
L R L R L R L R L R L R
RIGHT CHANNEL IGNORED
L R L R L R L R L R L R L R L R L R L R L R
SD_MODE = LOGIC-HIGH
PDM_CLK
PDM_DATA
L R L R L R L R L R L R
LEFT CHANNEL IGNORED
L R L R L R L R L R L R L R L R L R L R L R
SD_MODE = PULLUP THROUGH RSMALL
PDM_CLK
PDM_DATA
L R L R L R L R L R L R
LEFT AND RIGHT CHANNELS AVERAGED
L R L R L R L R L R L R L R L R L R L R L R
SD_MODE = PULLUP THROUGH RLARGE
PDM_CLK
PDM_DATA
SD_MODE STATUS SELECTED CHANNEL
High VSD_MODE > B2 trip point Left
Pullup through RSMALL
B2 trip point (1.4V typ) > VSD_MODE >
B1 trip point Right
Pullup through RLARGE*B1 trip point (0.77V typ) > VSD_MODE >
B0 trip point (Left/2 + right/2)
Low B0 trip point (0.16V typ) > VSD_MODE Shutdown
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
17
Figure 3 and Figure 4 show how to connect an external
resistor to SD_MODE when using an open-drain driver or
a pullup/down driver.
When the device is configured in left channel mode
(SD_MODE is directly driven to logic-high by the con-
trol interface) care must be taken to avoid violating
the Absolute Maximum Ratings limits for SD_MODE.
Ensuring that VDD is always greater than VDDIO is one
way to prevent SD_MODE from violating the Absolute
Maximum Ratings limits. If this is not possible in the
application (e.g., if VDD < 3.0V and VDDIO = 3.3V), then
it is necessary to add a small resistance (~2kΩ) in series
with SD_MODE to limit the current into the SD_MODE
pin. This is not a concern when using the right channel or
monomix modes.
Class D Speaker Amplier
The filterless Class D amplifier offers much higher effi-
ciency than Class AB amplifiers. The high efficiency of
a Class D amplifier is due to the switching operation of
the output stage transistors. Any power loss associated
with the Class D output stage is mostly due to the I2R
loss of the MOSFET on-resistance and quiescent current
overhead.
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet EN55022B electromagnet-
ic-interference (EMI) regulation standards. Maxim’s active
emissions-limiting edge-rate control circuitry and spread-
spectrum modulation reduces EMI emissions while main-
taining up to 92% efficiency.
Maxim’s spread-spectrum modulation mode flattens wide-
band spectral components while proprietary techniques
ensure that the cycle-to-cycle variation of the switching
period does not degrade audio reproduction or efficiency.
The ICs’ spread-spectrum modulator randomly varies the
switching frequency by ±20kHz around the center fre-
quency (330kHz). Above 10MHz, the wideband spectrum
looks like noise for EMI purposes (Figure 5).
Speaker Current Limit
If the output current of the speaker amplifier exceeds the
current limit (2.8A typ), the IC disables the outputs for
approximately 100µs. At the end of the 100µs, the outputs
are re-enabled. If the fault condition still exists, the IC con-
tinues to disable and re-enable the outputs until the fault
condition is removed.
Gain Selection
The IC offers five programmable gain selections through
a singel gain input (GAIN). Gain is referenced to the
full-scale output of the DAC, which is 2.1dBV (Table 7).
Assuming that the desired output swing is not limited by
the supply voltage rail, the IC’s output level can be calcu-
lated based on the PDM input ones’s density and selected
amplifier gain according to the following equation:
Output signal level (dBV) = 20 x log[abs(PDM one’s
density(%) - 50) /25] (dBFS) + 2.1dB + selected
speaker amplifier gain (dB)
where the one’s density of the PDM input ranges from
75% (maximum positive magnitude) to 25% (maximum
negative magnitude). 0dFBS is referenced to 0dBV.
Click-and-Pop Suppression
The IC speaker amplifier features Maxim’s compre-
hensive click-and-pop suppression. During startup, the
click-and-pop suppression circuitry reduces audible tran-
sient sources internal to the device. To achieve optimal
click-and-pop reduction at startup, it is recommended
that idle data be sent to the digital audio interface for the
first 0.5ms of turn-on time. When entering shutdown, the
differential speaker outputs simultaneously drop to GND.
Table 6. Examples of SD_MODE Pullup
Resistor Values
Table 7. Gain Selection
LOGIC VOLTAGE
LEVEL (VDDIO) (V) RSMALL (kΩ) RLARGE (kΩ)
1.8 69.8 300
3.3 210 634
GAIN GAIN (dB)
Connect to GND through
100kΩ ±5% resistor 15
Connect to GND 12
Unconnected 9
Connect to VDD 6
Connect to VDD through
100kΩ ±5% resistor 3
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
18
Figure 3. SD_MODE Resistor Connection Using Open-Drain Driver
Figure 4. SD_MODE Resistor Connection Using Push-Pull Driver
Figure 5. EMI with 12in of Speaker Cable and No Output Filtering
GPIO
PROCESSOR VDDIO
R
100kΩ
±8%
LEFT MODE
RIGHT MODE
LEFT/2 + RIGHT/2 MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
VSD_MODE
MAX98358
GPIO
PROCESSOR
VDDIO
R
100kΩ
±8%
LEFT MODE
RIGHT MODE
LEFT/2 + RIGHT/2 MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
VSD_MODE
MAX98358
FREQUENCY (MHz)
EMISSION LEVEL (dBµV/m)
900800600 700200 300 400 500100
10
30
50
70
90
-10
0 1000
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
19
Figure 6. Left-Channel Operation with 6dB Gain
Figure 8. Right-Channel Operation with 6dB Gain
Figure 7. Left-Channel Operation with 12dB Gain
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
SD_MODE
PDM_CLK
PDM_DATA
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98358 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98358
B2 A2
A1
C1
B1 C2, C3
B3
A3 OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
SD_MODE
PDM_CLK
PDM_DATA
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98358 IS SHUTDOWN WHEN GPIO IS LOW.
GND
B2 A2
A1
C1
B1 C2, C3
B3
A3
MAX98358
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
PDM_CLK
RSMALL
(69.8kΩ)**
PDM_DATA
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**69.8kΩ ASSUMES VGPIO = 1.8V.
THE MAX98358 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98358
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
B2 A2
A1
C1
B1
C2, C3
B3
A3
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
20
Figure 9. Stereo Operation Using Two MAX98358s
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
SD_MODE
PDM_CLK
RSMALL
(69.8kΩ)**
PDM_DATA
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**69.8kΩ ASSUMES VGPIO = 1.8V.
THE MAX98358 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98358
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
PDM_CLK
PDM_DATA
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98358 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98358
B2 A2
A1
C1
B1 C2, C3
B3
A3
B2 A2
A1
C1
B1 C2
B3
A3
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
21
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filter adds cost, size, and decreases efficiency and
THD+N performance. The MAX98358’s filterless modula-
tion scheme does not require an output filter. The device
relies on the inherent inductance of the speaker coil and
the natural filtering of both the speaker and the human ear
to recover the audio component of the square-wave output.
Because the switching frequency of the IC is well beyond
the bandwidth of most speakers, voice coil movement due
to the switching frequency is very small. Use a speaker
with a series inductance > 10FH. Typical 8I speakers
exhibit series inductances in the 20FH to 100FH range.
Power-Supply Input
VDD, which ranges from 2.5V to 5.5V, powers the IC,
including the speaker amplifier. Bypass VDD with a 0.1FF
and 10FF capacitor to GND. Some applications might
require only the 10FF bypass capacitor, making it pos-
sible to operate with a single external component. Apply
additional bulk capacitance at the IC if long input traces
between VDD and the power source are used.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Good grounding improves audio perfor-
mance and prevents switching noise from coupling into
the audio signal.
Use wide, low-resistance output traces. As load imped-
ance decreases, the current drawn from the device
outputs increases. At higher current, the resistance of
the output traces decreases the power delivered to the
load. For example, if 2W is delivered from the speaker
output to a 4I load through 100mI of total speaker
trace, 1.904W is being delivered to the speaker. If power
is delivered through 10mI of total speaker trace, 1.951W
is being delivered to the speaker. Wide output, supply,
and ground traces also improve the power dissipation of
the IC. Parasitic capacitance on the output causes higher
quiescent current by VDD x 330kHz x CPARASITIC.
For example, at VDD and a total parasitic capacitance of
100pF (50pF on each output trace), the increase in quies-
cent current is: 5 x 330kHz x 100pF = 165µA.
The IC is inherently designed for excellent RF immunity.
For best performance, add ground fills around all signal
traces on top or bottom PCB planes.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability testing
results, refer to the Application Note 1891: Wafer-Level
Packaging (WLP) and Its Applications. Figure 11 shows
the dimensions of the WLP balls used on the IC.
Figure 10. Monomix (Left/2 + Right/2) PDM Operation with 6dB
Gain
Figure 11. MAX98358 WLP Ball Dimensions
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
PDM_CLK
RLARGE
(300kΩ)**
PDM_DATA
GND
*LEFT AND RIGHT ARE SUMMED WHEN GPIO IS HIGH.
**300kΩ ASSUMES VGPIO = 1.8V.
THE MAX98358 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98358
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
B2 A2
A1
C1
B1 C2, C3
B3
A3
0.21mm
0.24mm
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
│
22
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Ordering Information
Functional Diagram
2.5V TO 5.5V
0.1µF10µF
PDM_CLK
PDM_DATA
SD_MODE
DAC
CLASS D
OUTPUT
STAGE
OUTP
GAIN
VDD
OUTN
DIGITAL
AUDIO
INTERFACE
() APPLIES TO TQFN PACKAGE
MAX98358
GND
B1
C1
A1
C2, C3
A2 B2
A3
B3
(7, 8) (2)
(9)
(10)
(3, 11, 14, 15)
(16)
(1)
(3)
PART TEMP RANGE PIN-PACKAGE
MAX98358EWL+T -40°C to +85°C 9 WLP
MAX98358ETE+ -40°C to +85°C 16 TQFN
MAX98358 PDM Input Class D Audio Power Amplier
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Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
TM
integrated
maxim
0.05 AB
0.05 S
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
9 WLP W91F1+1 21-0896 Refer to Application Note 1891
16 TQFN T1633+4 21-0136 90-0031
MAX98358 PDM Input Class D Audio Power Amplier
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Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
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Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
MAX98358 PDM Input Class D Audio Power Amplier
www.maximintegrated.com Maxim Integrated
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Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/13 Initial release —
1 11/13 Removed future product reference 21
2 8/14 Added THD+N TQFN typical only spec to Electrical Characteristics table 3
3 1/15 Added Table of Contents, updated SSM spec, replaced all typical operating
characteristics, and corrected typos 5–12, 16–18
4 8/15 Corrected package outline for WLP package 24
5 8/17 Updated soldering temperature and added lead temperature in the Absolute Maximum
Ratings section 4
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX98358 PDM Input Class D Audio Power Amplier
© 2017 Maxim Integrated Products, Inc.
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.