AM79C973BKCW - AMD - Datasheet.Live

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to h elp you evaluate t his product. AMD re serves the right to chan ge or discontinu e work on this proposed

product without notice.

Publication# 21510 Rev: EAmendment/0

Issue Date: August 2000

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Am79C973/Am79C975

PCnet™-FAST III

Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY

DISTINCTIVE CHARACTERISTIC S

■Single-chip PCI-to-Wire Fast Ethernet controller

—32-bit gluele ss PCI hos t interf ace

—Supports PCI c lock frequenc y from DC to

33 MHz independent of ne twork clock

—Supports network operation with PCI clock

from 15 MHz to 33 MHz

—High performance bus mastering

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

—PCI specification revision 2.2 compliant

—Supports PCI Subsystem/Subvendor ID/

V endor ID pro gramming through the

EEPROM interface

—Supports both PCI 5.0 V and 3.3 V signaling

environments

—Plug and Play compatible

—Big endian and little endian byte alignments

supported

■Fully Integrated 10/100 Mbps Physical Layer

Interface (PHY)

—Conforms to IEEE 802.3 standard for

10BASE-T, 100BASE-TX, and 100BASE-FX

interfaces

—Integrated 10BASE-T transceiver with on-

chip filtering

—Fully integrated MLT-3 encoder/decode r for

100BASE-TX

—Provides a PECL interface for 100BASE-FX

fiber implementations

—Full-duplex capability for 10BASE-T and

100BASE-TX

—IEEE 802.3u Auto-Negotiation between 10

Mbps and 100 Mbps, half- and full-duplex op-

eration

■Dual-speed CSMA/CD (10 Mbps and 1 00 Mbps)

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 and Blue Book Ethernet

standards

■Supports PC98/PC99 and Wired for

Management baseline specifications

—Full OnNow support including pattern

matching and link status wak e-up events

—Implements AMD’s patented Magic Packet™

technology for remote wake-up & power-on

—Magic Packet mode and the physical address

loaded from EEPROM at power up without

requiring PCI clock

—Supports PCI Bus Power Management

Interface Specification Revision 1.1

—Supports Adva nced Configuration and

P ower Interface (A CPI) Specification V ersion

1.0

—Supports Network Device Class Power

Management Specification Version 1.0a

■Serial Management I nterface enables remo te

alerting of system management events

—Inter-IC (I2C) compliant electrical interface

—System Management Bus (SMBus)

compliant signaling interface and register

access protocol

—Optional interrupt pin simplifies software

interface

■Large independent internal TX and RX FIFOs

—Pr ogrammable FIFO wate rmarks fo r both TX

and RX operations

—RX frame queuing for high lat ency PCI bus

host operation

—Programmable allocation of buffer space

between RX and TX queues

■EEPROM interface supports jumperless design

and provides through-chip programming

—Supports extensive programmability of

devi ce operation through EEPROM mapping

■Supports up to 1 megabyte (Mbyte) optional

Boot PROM and Flash for diskl ess node

application

■Extensive programmable internal/external

loopback capabilities

■Extensive programmable LED status support

2 Am79C973/Am79C975

PRELIMINARY

■Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead

by allowing protocol analysis to begin before

the end of a receive frame

■Includes Programmable Inte r Packet Gap (IPG)

to address less network aggressive MAC

controllers

■Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

■IEEE 1149.1-c ompliant JTAG Boundary Scan

test access port interface and NAND tree test

mode f or board-level production connectivity

test

■Compatible with the existing PCnet Family

driver/diagnostic software

■Software compatible with AMD PCnet Family

and LANCE™/C-LANCE™ register and

descriptor architecture

■Available in 160-pin PQFP and 176-pin TQFP

packages

■Adv anced +3.3 V CMOS proce ss technology f or

low power operation

GENERAL DESCRIPTION

The Am79C973 and Am79C975 controllers are single-

chip 32-bit full- duplex, 10/100-Megabit per second

(Mbps) fully integrated PCI-to-W ire Fast Eth ernet sys-

tem solution, designed to address high-performance

system application requirements. They are flexible bus

mastering device that can be used in any application,

including network-ready PCs and bridge/router de-

signs. The bus master arc hitecture provides high data

throughput and low CPU and system bus utilization.

The Am79C973 and Am79C975 controllers are fabri-

cated with advanced low-power 3.3-V CMOS process

to provide low operating current for power sensitive ap-

plications.

The third generation Am79C973 and Am79C975 Fast

Ether net controllers also have several enhancements

over their predecessors, the Am79C971 and

Am79C972 devices. Besides integrating the complete

10/100 Physical Layer (PHY) inter face, they furth er re-

duce system implementation cost by integrating the

SRAM buffers on chip.

The Am79C973 and Am79C975 controllers contain 12-

kilobyte (Kbyte) buffers, the largest of their class in 10/

100 Mbps Ethernet controllers. The large internal buff-

ers are fully programmable between the RX and TX

queues for optimal performance.

The Am79C973 and Am79C975 controllers are also

compliant with PC98/PC99 and Wired f or Management

specifications. They fully support Microsoft’s OnNow

and ACPI specifications, which are backward compati-

ble with Magic Packet technology and compliant with

the PCI Bus Power Management Interface Specifica-

tion by suppor ting the four power management states

(D0, D1, D2, and D3), the optional PME pin, and the

necessary configuration and data registers.

The Am79C973 and Am79C975 controllers are com-

plete Ether n et nodes integrated in to a single VLS I de-

vice. It contains a bus interface unit, a Direct Memor y

Access (DMA) Buffer Management Unit, an ISO/IEC

8802-3 (IEEE 802.3)- compliant Media Access Control-

ler (MAC), a large Transmit F IFO and a large Re ceive

FIFO, and an IEEE 802.3-compliant 10/100 Mbps PHY.

The integrated 10/100 PHY unit of the Am79C973 and

Am79C975 controllers implemen t the complete physi-

cal layer for 10BASE-T and the Physical Coding Sub-

layer (PCS), Physical Medium Attachment (PMA), and

Physical Medium Dependent (PMD) functionality for

100BASE-TX, including MLT-3 encoding/decoding. It

also supports 100BASE-FX operation by providing a

Pseudo-ECL (PECL) interface for direct connectio n to

a fiber optic transceiver module. The internal 10/100

PHY implements Auto-Negotiation for twisted-pair

(10T/100T X ) opera tio n by using a mod ifi ed 1 0B ASE- T

link integrity test pulse sequence as defined in the

IEEE 802 .3u sp ecifi catio n. The Auto-Negotiat ion fun c-

tion automatically configures the controller to operate

at the maximum performance level supported across

the network link.

The Am79C975 controller also implements a Serial

Management Interface in addition to the advanced

management features offered with the Am79C973 con-

troller. The Serial Management Interface is based on

the industry standard Inter-IC (I2C) and System Man-

agement Bus (SMBus) specifications and enables a

system to communicate with another network station

for remote monitoring and alerting of local system man-

agement param ete rs and events. This si mpl e yet pow-

erful Serial Management Interface is capable of

communicating within the system and over the network

during normal operation or in low-pow er modes, e ven if

the device is not initialized or set up for transmit or re-

ceive operation by the network software driver.

The 32-bit multiplexed bus interface unit provides a di-

rect interface to the PCI local bus, simplifying the

design of an Ethernet node in a PC system. The

Am79C973 and Am79C975 controllers provide the

complete inter face to an Ex pansion ROM or Flas h de-

vice allowing add-on card designs with only a single

load per PCI bus interface pin. With their built-in sup-

port for both little and big endian byte alignment, the

Am79C973/Am79C975 3

PRELIMINARY

controllers also address non-PC applications. The

Am79C973 and Am79C975 controllers’ advanced

CMOS design allows the bus interface to be connected

to either a +5-V or a +3.3-V signaling environment. A

compliant IEEE 1149.1 JTAG test interface for board-

level testing is also provided, as well as a NAND tree

test structure for those systems that cannot support the

JTAG interface.

The Am79C973 and Am79C975 controllers support

auto-co nfiguration in the PCI confi guration space. Ad -

ditional Am79C97 3 and Am79 C975 con troll er config u-

ration parameters, including the unique IEEE physical

address, can be read from an external non-volatile

memor y (EEPROM) immediately following system re-

set.

In addition , the Am 79C973 and Am7 9C97 5 co ntr ol lers

provide programmable on-chip LED drivers for trans-

mit, receive, collision, link integrity, Magic Packet sta-

tus, activity, link active, address match, full-duplex, 10

Mbps or 100 Mbps, or jabber status.

The Am79C973 and Am79C975 controllers are regis-

ter compatible with the LANCE™ (Am7990) Ethernet

controller, the C-LANCE™ (Am79C90) Ethernet con-

troller, and all Ethernet controllers in the PCnet™ Fam-

ily, except ILACC™ (Am79C900), including the PCnet-

ISA™ (Am79C960), PCnet-ISA+™ (Am79C961),

PCnet-ISA II™ (Am79C961A), PCnet-32™

(Am79C965), PCnet-PCI™ (Am79C970),

PCnet-PCI II™ (Am79C970A), PCnet-FAST™

(Am79C971), and PCnet-FAST+™ (Am79C972). The

Buffer Management Unit supports the LANCE and

PCnet descriptor software models.

The Am79 C973 and Am 79C975 cont ro ll ers ar e id eal ly

suited for LAN on the motherboard, network adapter

card, and embedded designs. It is available in a 160-

pin Plastic Quad Flat P ack (PQFP) package and also in

a 176-pin Thin Quad Flat Pack (TQFP) package for

form factor sensitive designs.

4 Am79C973/Am79C975

PRELIMINARY

BLOCK DIAGRAM

CLK

RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT

PERR

SERR

INTA

PCI Bus

Interface

Unit

Expansion Bus

Interface

Bus

Rcv

FIFO

Bus

Xmt

FIFO

Control Network

Port

Manager

MAC

Rcv

FIFO

12K

SRAM

MAC

Xmt

FIFO

JTAG

Port

Control

OnNow

Power

Management

Unit

802.3

MAC

Core

93C46

EEPROM

Interface

LED

Control

Buffer

Management

Unit

PME

RWU

WUMI PG

TCK

TMS

TDI

TDO

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EROMCS

AS_EBOE

EBWE

EBCLK

Transmit

Block

MII

Interface

MII

Management

MDC

MDIO

Receive

Block

PHY Control

Link

Monitor Auto

Negotiation

10/100 PHY Core

MLT3

(100 BASE-TX)

PECL

(100 BASE-FX)

10 BASE-T

TX±

SDI±

RX±

XTAL1 XTAL2

LED0

LED1

LED2

LED3

EECS

EESK

EEDI

EEDO

Clock

Reference

MII

EADI

Serial

Management

Interface Unit

MCLOCK

MDATA

MIRQ

RXD[3:0],TXD[3:0]

MDIO

MDC

SFBD

EAR

MIIRXFRTGE

MIIRXFRTGD

VAUXDET

21510D-1

Am79C973/Am79C975 5

PRELIMINARY

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CONNECTION DIAGRAM (PQR160) - AM79C973 . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CONNECTION DIAGRAM (PQL176) AM79C973 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CONNECTION DIAGRAM (PQR160) - AM79C975 . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CONNECTION DIAGRAM (PQL176) - AM79C975 . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PIN DESIGNATIONS (PQR160) (Am79C973/Am79C975) . . . . . . . . . . . . . . . . . . . . 22

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PIN DESIGNATIONS (PQL176) (Am79C973/Am79C975) . . . . . . . . . . . . . . . . . . . . . 23

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PIN DESIGNATIONS (PQR160, PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Serial Management Interface (SMI) (Am79C975 only) . . . . . . . . . . . . . . . . . . . . . . 37

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

System Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Serial Management Interface (Am79C975) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Slave Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

TABLE OF CONTENTS

6 Am79C973/Am79C975

PRELIMINARY

Bus Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Master Initiated Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Master Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Re-Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Descriptor Rings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Transmit Descriptor Table Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Receive Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Receive Frame Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10/100 Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Transmit and Receive Message Data Encapsulation. . . . . . . . . . . . . . . . . . . . . 70

Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Media Access Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Transmit Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Receive Function Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Address Matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Automatic Pad Stripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Miscellaneous Loopback Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Full-Duplex Link Status LED Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10/100 PHY Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

100BASE-TX Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

100BASE-FX (Fiber Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10BASE-T Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Internal PHY Loopback Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Am79C973/Am79C975 7

PRELIMINARY

Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Link Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Far End Fault Generation and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

MLT-3 and Adaptive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Serializer/Deserializer and Clock Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Medium Dependent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10BASE-T Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Twisted Pair Receive Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Reverse Polarity Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Soft Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

External Address Detection Interface: MII Snoop Mode . . . . . . . . . . . . . . . . . . 89

External Address Detection Interface: Receive Frame Tagging . . . . . . . . . . . . 89

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Expansion ROM - Boot Device Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Direct Flash Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

AMD Flash Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Direct SRAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Automatic EEPROM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

TAP Finite State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

H_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

S_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

8 Am79C973/Am79C975

PRELIMINARY

PCI Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

PCI Programming Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

PCI Sub-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Base-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Memory Mapped I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . 118

PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Capabilities Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Interrupt Line Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI MIN_GNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Capability Identifier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Power Management Capabilities Register (PMC). . . . . . . . . . . . . . . . . . . 1 21

PCI Power Management Control/Status Register (PMCSR) . . . . . . . . . . . . . . 121

PCI PMCSR Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . 122

PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

RAP: Register Address Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

CSR0: Am79C973/Am79C975 Controller Status and Control Register. . . . . . 123

CSR1: Initialization Block Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

CSR2: Initialization Block Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . 126

CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

CSR5: Extended Control and Interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

CSR6: RX/TX Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CSR7: Extended Control and Interrupt 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR12: Physical Address Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR13: Physical Address Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR14: Physical Address Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR15: Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

CSR18: Current Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . 140

CSR19: Current Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . 140

CSR20: Current Transmit Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . 140

CSR21: Current Transmit Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . 140

CSR22: Next Receive Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . 140

CSR23: Next Receive Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . 140

Am79C973/Am79C975 9

PRELIMINARY

CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . 141

CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . 141

CSR26: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . 141

CSR27: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . 141

CSR28: Current Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . 141

CSR29: Current Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . 141

CSR30: Base Address of Transmit Ring Lower. . . . . . . . . . . . . . . . . . . . . . . . 141

CSR31: Base Address of Transmit Ring Upper. . . . . . . . . . . . . . . . . . . . . . . . 142

CSR32: Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . 142

CSR33: Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . 142

CSR34: Current Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . 142

CSR35: Current Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . 142

CSR36: Next Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . 142

CSR37: Next Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . 142

CSR38: Next Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . 143

CSR39: Next Next Transmit Descriptor Address Uper. . . . . . . . . . . . . . . . . . . 143

CSR40: Current Receive Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR41: Current Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR42: Current Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR43: Current Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR44: Next Receive Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR45: Next Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

CSR46: Transmit Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

CSR47: Transmit Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

CSR48: Receive Poll Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

CSR49: Receive Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

CSR58: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

CSR60: Previous Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . 147

CSR61: Previous Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . 148

CSR62: Previous Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR63: Previous Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR64: Next Transmit Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR65: Next Transmit Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR66: Next Transmit Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR67: Next Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR72: Receive Ring Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . 150

CSR82: Transmit Descriptor Address Pointer Lower. . . . . . . . . . . . . . . . . . . . 152

CSR84: DMA Address Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR85: DMA Address Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR88: Chip ID Register Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR89: Chip ID Register Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

CSR92: Ring Length Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

CSR100: Bus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

10 Am79C973/Am79C975

PRELIMINARY

CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

CSR122: Advanced Feature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

CSR124: Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

CSR125: MAC Enhanced Configuration Control . . . . . . . . . . . . . . . . . . . . . . . 156

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

BCR1: Master Mode Write Active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

BCR2: Miscellaneous Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

BCR4: LED 0 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

BCR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

BCR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

BCR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

BCR9: Full-Duplex Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

BCR16: I/O Base Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

BCR17: I/O Base Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

BCR19: EEPROM Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

BCR20: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

BCR22: PCI Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

BCR23: PCI Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 180

BCR24: PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

BCR25: SRAM Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

BCR26: SRAM Boundary Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

BCR27: SRAM Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

BCR28: Expansion Bus Port Address Lower

(Used for Flash/EPROM and SRAM Accesses) . . . . . . . . . . . . . . . . . . . . . 183

BCR29: Expansion Port Address Upper

(Used for Flash/EPROM Accesses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

BCR30: Expansion Bus Data Port Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 184

BCR31: Software Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

BCR32: PHY Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

BCR33: PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

BCR34: PHY Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

BCR36: PCI Power Ma nagement Capabilities (PM C) Alias Register . . . . . . . 188

BCR37: PCI DATA Register Zero (DATA0) Alias Register . . . . . . . . . . . . . . . 188

BCR38: PCI DATA Register One (DATA1) Alias Register. . . . . . . . . . . . . . . . 188

BCR39: PCI DATA Register Two (DATA2) Alias Register. . . . . . . . . . . . . . . . 189

BCR40: PCI DATA Register Three (DATA3) Alias Register . . . . . . . . . . . . . . 189

BCR41: PCI DATA Register Four (DATA4) Alias Register . . . . . . . . . . . . . . . 189

BCR42: PCI DATA Register Five (DATA5) Alias Register. . . . . . . . . . . . . . . . 190

BCR43: PCI DATA Register Six (DATA6) Alias Register. . . . . . . . . . . . . . . . . 190

BCR44: PCI DATA Register Seven (DATA7) Alias Register . . . . . . . . . . . . . . 191

BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 191

BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 191

BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . 192

BCR48-BCR55: Reserved Locations for Am79C975. . . . . . . . . . . . . . . . . . . . 192

PHY Management Registers (ANRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Am79C973/Am79C975 11

PRELIMINARY

ANR1: Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

ANR2 and ANR3: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . 196

ANR4: Auto-Negotiation Advertisement Register (Register 4). . . . . . . . . . . . . 197

ANR5: Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . 198

ANR6: Auto-Negotiation Expansion Register (Register 6). . . . . . . . . . . . . . . . 199

ANR7: Auto-Negotiation Next Page Register (Register 7). . . . . . . . . . . . . . . . 199

Reserved Registers (Registers 8-15, 20-23, and 25-31) . . . . . . . . . . . . . . . . . 199

ANR16: INTERRUPT Status and Enable Register (Register 16). . . . . . . . . . . 200

ANR17: PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . . . 200

ANR18: Descrambler Resynchronization Timer Register (Register 18) . . . . . 202

ANR19: PHY Management Extension Register (Register 19) . . . . . . . . . . . . . 202

ANR24: Summary Status Register (Register 24). . . . . . . . . . . . . . . . . . . . . . . 202

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

PHY Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

PROGRAMMABLE REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Am79C973/Am79C975 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . 220

Am79C973/Am79C975 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . 222

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . 227

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS

DETECTION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

EXTERNAL CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 35

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . 236

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE . . . . . . . . . . . . . . . . 240

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

APPENDIX A: PCnet™-FAST III Recommended Magnetics . . . . . . . . . . . . . . . . 244

APPENDIX B: SERIAL MANAGEMENT INTERFACE UNIT

(AM79C975 ONLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Am79C975 PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Am79C975 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Detailed Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

User Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

12 Am79C973/Am79C975

PRELIMINARY

Node ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Device Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Am79C975 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Am79C975 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

APPENDIX C: MEDIA INDEPENDENT INTERFACE (MII) . . . . . . . . . . . . . . . . . . . . 268

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

MII management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . 276

Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . . . . . . . 277

Switching Characteristics: Media Independent Interface . . . . . . . . . . . . . . . . . . . 278

Switching Waveforms: Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . 279

Switching Waveforms: External Address Detection Interface . . . . . . . . . . . . . . . . 281

Switching Waveforms: Receive Frame Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

APPENDIX D: ALTERNATIVE METHOD FOR INITIALIZATION . . . . . . . . . . . . . . . 283

APPENDIX E: LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT . . . . . 284

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Outline of LAPP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

LAPP Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . 289

Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

An Alternative LAPP Flow: Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . 291

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Am79C973/Am79C975 13

PRELIMINARY

Figure 1. Slave Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 2. Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 3. Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 4. Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 5. Expansion ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 6. Disconnect Of Slave Cycle When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 7. Disconnect Of Slave Burst Transfer - No Host Wait States . . . . . . . . . . . . . 44

Figure 8. Disconnect Of Slave Burst Transfer - Host Inserts Wait States . . . . . . . . . . 45

Figure 9. Address Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 10. Slave Cycle Data Parity Error Response 46

Figure 11. Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12. Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0) . . . . . . . . . . . . . . . . . . 48

Figure 14. Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15. Burst Write Transfer (EXTREQ = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 16. Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 18. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19. Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 20. Preemption During Burst Transaction 54

Figure 21. Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 22. Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 23. Initialization Block Read In Non-Burst Mode 57

Figure 24. Initialization Block Read In Burst Mode 57

Figure 25. Descriptor Ring Read In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 26. Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 27. Descriptor Ring Write In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 28. Descriptor Ring Write In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 29. FIFO Burst Write At Start Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 30. FIFO Burst Write At End Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 31. 16-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 32. 32-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 34. IEEE 802.3 Frame And Length Field Transmission Order . . . . . . . . . . . . . . 77

Figure 35. 100BASE-X Transmit and Receive Data Paths of the Internal PHY . . . . . . 81

Figure 36. MLT-3 Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 37. TX± and RX± Termina tion 86

Figure 38. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 39. Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 40. Flash Configuration for the Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 41. EPROM Only Configuration for the Expansion Bus (64K EPROM) . . . . . . . 92

Figure 42. EPROM Only Configuration for the Expa nsion Bus (64K EPROM) 93

Figure 43. Expansion ROM Bus Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 44. Flash Read from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 45. Flash Write from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 46. Block Diagram No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 47. Block Diagram Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . 97

Figure 48. LED Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

LIST OF FIGURES

14 Am79C973/Am79C975

PRELIMINARY

Figure 49. OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 50. Pattern Match RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 51. Address Match Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 52. External Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 53. PMD Interface Timing (PECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 54. PMD Interface Timing (MLT-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 55. 10 Mbps Transmit (TX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 56. 10 Mbps Receive (RX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 57. Normal and Tri-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 58. CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 59. CLK Waveform for 3.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 60. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 61. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 62. Output Tri-state Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 63. EEPROM Read Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 64. Automatic PREAD EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 65. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling . . . . . . . . . . . . . . . 238

Figure 66. JTAG (IEEE 1149.1) Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 67. EBCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 68. Expansion Bus Read Timing 240

Figure 69. Expansion Bus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 70. Standard Data Transfer on the Serial Management Interface . . . . . . . . . . 247

Figure 71. Data Transfer with Change in Direction (with wait state) . . . . . . . . . . . . . . 247

Figure 72. Write Byte Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 73. Read Byte Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 74. Block Write Command 249

Figure 75. Block Read Command 250

Figure 76. System Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 77. Media Independent Interface 268

Figure 78. Frame Format at the MII Interface Connection . . . . . . . . . . . . . . . . . . . . . 270

Figure 79. MII Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 73

Figure 80. Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 81. Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 82. MDC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 83. Management Data Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 84. Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . 280

Figure 85. Reject Timing - External PHY MII @ 25 MHz . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 86. Reject Timing - External PHY MII @ 2.5 MHz 281

Figure 87. Receive Frame Tag Timing with Media Independent Interface . . . . . . . . . 282

Figure 88. LAPP Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 89. LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 90. LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Figure 91. LAPP 3 Buffer Grouping for Two-interrupt Method . . . . . . . . . . . . . . . . . . 293

Am79C973/Am79C975 15

PRELIMINARY

Table 1. Interrupt Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 2. SDI± Settings for Transceiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 3. Slave Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 4. Master Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 5. Descriptor Read Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 6. Descriptor Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 7. Receive Address Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 8. Encoder Code-Group Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 9. Decoder Code-Group Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 10. Auto-Negotiation Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 11. EADI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 12. Am29Fxxx Flash Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 13. Am79C973 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 14. Am79C975 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 15. LED Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 16. IEEE 1149.1 Supported Instruction Summary . . . . . . . . . . . . . . . . . . . . . . 106

Table 17. BSR Mode Of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 18. Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 19. PCI Configuration Space Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 20. I/O Map In Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 21. Legal I/O Accesses in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . 111

Table 22. I/O Map In DWord I/O Mode (DWIO =1). . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 23. Legal I/O Accesses in Double Word I/O Mode (DWIO =1). . . . . . . . . . . . . 111

Table 24. Loopback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 25. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 26. Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 27. Transmit Start Point Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 28. Transmit Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 29. BCR Registers (Am79C973) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 30. BCR Registers (Am79C975) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 31. ROMTNG Programming Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 32. Interface Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 33. Software Styles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 34. SRAM_BND Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 35. EBCS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 36. CLK_FAC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 37. FMDC Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 38. APDW Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 39. Am79C973/Am79C975 Internal PHY Management Register Set . . . . . . . 193

Table 40. ANR0: PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 41. ANR1: PHY Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 42. ANR2: PHY Identifier (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 43. ANR3: PHY Identifier (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 44. ANR4: Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . 197

Table 45. ANR5: Auto-Negotiation Link Partner Ability Register (Register 5)

- Base Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 46. ANR5: Auto-Negotiation Link Partner Ability Register (Register 5)

- Next Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

LIST OF TABLES

16 Am79C973/Am79C975

PRELIMINARY

Table 47. ANR6: Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . 199

Table 48. ANR7: Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . 199

Table 49. ANR16: INTERRUPT Status and Enable Register (Register 16) . . . . . . . . 200

Table 50. ANR17: PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . 201

Table 51. ANR18: Descrambler Resynchronization Timer (Register 18) . . . . . . . . . . 202

Table 52. ANR19: PHY Management Extension Register (Register 19) . . . . . . . . . . . 202

Table 53. ANR24: Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . . 203

Table 54. Initialization Block (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 55. Initialization Block (SSIZE32 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 56. R/TLEN Decoding (SSIZE32 = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 57. R/TLEN Decoding (SSIZE32 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 58. Receive Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 05

Table 59. Receive Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 06

Table 60. Receive Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 06

Table 61. Transmit Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 62. Transmit Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 63. Transmit Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 64. Clock (XTAL1, XCLK = 1) Switching Characteristics . . . . . . . . . . . . . . . . . 231

Table 65. Crystal (XTAL1, XTAL2, XCLK = 0) Requirements . . . . . . . . . . . . . . . . . . 231

Table 66. Crystal (XTAL1, XTAL2, XCLK = 0) Requirements . . . . . . . . . . . . . . . . . . 231

Table 67. Recommended Magnetics Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Table 68. Auto-Negotiation Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 69. EADI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Table 70. MII Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Table 71. MII Management Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . 274

Table 72. MII Management Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . 275

Table 73. Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . 276

Table 74. Technology Ability Field Bit Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 75. Auto-Neg otiation Link Partner Ability Register (Regi s ter 5)

- Base Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 76. Registers for Alternative Initialization Method (Note 1) . . . . . . . . . . . . . . . . 283

Am79C973/Am79C975 17

PRELIMINARY

RELATED AMD PRODUCTS

Part No. Description

Controllers

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE™)

Integrated Controllers

Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller

Am79C940 Media Access Controller for Ethernet (MACE™)

Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus

Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses

Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus

Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

Am79C972 PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

Manchester Encoder/Decoder

Am7992B Serial Interface Adapter (SIA)

Physical Layer Devices (Single-Port)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver

Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD)

Am79C98 Twisted Pa ir Ether n et Transceiver (TPEX)

Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Physical Layer Devices (Multi-Port)

Am79C871 Quad Fast Ether n et Transceiver for 100BASE-X Repeaters (QFEXr™)

Am79C988A Quad Integrat ed Et hernet Transceiver (QuIET™)

Am79C989 Quad Ethernet Switching Transceiver (QuEST™)

Integrated Repeater/Hub Devices

Am79C 981 Integrated Multiport Repeater Plus (IMR+)

Am79C982 Basic Integrated Multiport Repeater (bIMR)

Am79C983 Integrat ed Multip ort Repeater 2 (IMR2™)

Am79C984A Enhanced Integrated Multipor t Repeater (eIMR™)

Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™)

Am79C987 Hardware Implemented Management Information Base (HIMIB™)

18 Am79C973/Am79C975

PRELIMINARY

CONNECTION DIAGRAM (PQR160) - Am79C973

Pin 1 is marked for orientation.

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS

AD14

AD13

VSSB

AD12

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

EROMCS

EBWE

AS_EBOE

EBCLK

EBUA_EBA0

VSSB

EBUA_EBA1

VDD

VDDB

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5/MDC

EBUA_EBA6/PHY_RST

EBUA_EBA7/TX_ER

VSS

EBDA8/TXD0

VSSB

EBDA9/TXD1

EBDA10/TXD2

VDDB

EBDA11/TXD3

EBDA12/TX_EN

EBDA13/MDIO

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTA

VDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

PME

VSS

EAR

EECS

VSSB

EESK/LED1/SFBD

LED2/MIIRXFRTGE

VDDB

XCLK/XTAL

VSSB

EED1/LED0

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

EEDO/LED3/MIIRXFRTGD

DVSSP

DVDDP

RX-

DVDDRX

RX+

SDI-

DVSSX

SDI+

TX-

DVDDTX

TX+

DVDDD

IREF

DVSSD

DVDDA

DVDDCO

XTAL1

XTAL2

VDDB

VSSB

VDD

VSSB

VAUXDET

EBD0/RXD0

EBD1/RXD1

EBD2/RXD2

VSS

EBD3/RXD3

VDDB

EBD4/RX_DV

EBD5/RX_CLK

EBD6/RX_ER

VSSB

EBD7/TX_CLK

EBDA15/COL

EBDA14/CRS

Am79C973

PQR160

21510D-2

Am79C973/Am79C975 19

PRELIMINARY

CONNECTION DIAGRAM (PQL176) Am79C973

Pin 1 is marked for orientation.

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS

AD14

AD13

VSSB

AD12

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

EROMCS

EBWE

AS_EBOE

EBCLK

EBUA_EBA0

VSSB

EBUA_EBA1

VDD

VDDB

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5/MDC

EBUA_EBA6/PHY_RST

EBUA_EBA7/TX_ER

VSS

EBDA8/TXD0

VSSB

EBDA9/TXD1

EBDA10/TXD2

VDDB

EBDA11/TXD3

EBDA12/TX_EN

EBDA13/MDIO

EEDO/LED3/MIIRXFRTGD

DVSSP

DVDDP

RX-

DVDDRX

RX+

SDI-

DVSSX

SDI+

TX-

DVDDTX

TX+

DVDDD

IREF

DVSSD

DVDDA

DVDDCO

XTAL1

XTAL2

VDDB

VSSB

VDD

VSSB

VAUXDET

EBD0/RXD0

EBD1/RXD1

EBD2/RXD2

VSS

EBD3/RXD3

VDDB

EBD4/RX_DV

EBD5/RX_CLK

EBD6/RX_ER

VSSB

EBD7/TX_CLK

EBDA15/COL

EBDA14/CRS

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTA

VDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

PME

VSS

EAR

EECS

VSSB

EESK/LED1/SFBD

LED2/MIIRXFRTGE

VDDB

XCLK/XTAL

VSSB

EED1/LED0

Am79C973

PQL176

21510D-3

20 Am79C973/Am79C975

PRELIMINARY

CONNECTION DIAGRAM (PQR160) - Am79C975

Pin 1 is marked for orientation.

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS

AD14

AD13

VSSB

AD12

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

EROMCS

EBWE

AS_EBOE

EBCLK

EBUA_EBA0

VSSB

EBUA_EBA1

VDD

VDDB

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5/MDC

EBUA_EBA6/PHY_RST

EBUA_EBA7/TX_ER

VSS

EBDA8/TXD0

VSSB

EBDA9/TXD1

EBDA10/TXD2

VDDB

EBDA11/TXD3

EBDA12/TX_EN

EBDA13/MDIO

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTA

VDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

PME

VSS

EAR

EECS

VSSB

EESK/LED1/SFBD

LED2/MIIRXFRTGE

VDDB

XCLK/XTAL

VSSB

EED1/LED0

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

EEDO/LED3/MIIRXFRTGD

DVSSP

DVDDP

RX-

DVDDRX

RX+

SDI-

DVSSX

SDI+

TX-

DVDDTX

TX+

DVDDD

IREF

DVSSD

DVDDA

DVDDCO

XTAL1

XTAL2

VDDB

MCLOCK

VSSB

MDATA

VDD

MIRQ

VSSB

VAUXDET

EBD0/RXD0

EBD1/RXD1

EBD2/RXD2

VSS

EBD3/RXD3

VDDB

EBD4/RX_DV

EBD5/RX_CLK

EBD6/RX_ER

VSSB

EBD7/TX_CLK

EBDA15/COL

EBDA14/CRS

Am79C975

PQR160

21510D-4

Am79C973/Am79C975 21

PRELIMINARY

CONNECTION DIAGRAM (PQL176) - Am79C975

Pin 1 is marked for orientation.

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21

AD20

VDD

AD19

AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR

SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS

AD14

AD13

VSSB

AD12

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

EROMCS

EBWE

AS_EBOE

EBCLK

EBUA_EBA0

VSSB

EBUA_EBA1

VDD

VDDB

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5/MDC

EBUA_EBA6/PHY_RST

EBUA_EBA7/TX_ER

VSS

EBDA8/TXD0

VSSB

EBDA9/TXD1

EBDA10/TXD2

VDDB

EBDA11/TXD3

EBDA12/TX_EN

EBDA13/MDIO

EEDO/LED3/MIIRXFRTGD

DVSSP

DVDDP

RX-

DVDDRX

RX+

SDI-

DVSSX

SDI+

TX-

DVDDTX

TX+

DVDDD

IREF

DVSSD

DVDDA

DVDDCO

XTAL1

XTAL2

VDDB

MCLOCK

VSSB

MDATA

VDD

MIRQ

VSSB

VAUXDET

EBD0/RXD0

EBD1/RXD1

EBD2/RXD2

VSS

EBD3/RXD3

VDDB

EBD4/RX_DV

EBD5/RX_CLK

EBD6/RX_ER

VSSB

EBD7/TX_CLK

EBDA15/COL

EBDA14/CRS

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTA

VDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

PME

VSS

EAR

EECS

VSSB

EESK/LED1/SFBD

LED2/MIIRXFRTGE

VDDB

XCLK/XTAL

VSSB

EED1/LED0

Am79C975

PQL176

21510D-5

22 Am79C973/Am79C975

PRELIMINARY

PIN DESIGNATIONS (PQR160) (Am79C973/Am79C975)

Listed By Pin Number

Note: For the Am79C973 controller, pins 96, 98, and 100 are no connects (NC).

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin No. Pin

Name

1 IDSEL 41 AD8 81 EBDA14/CRS 121 EEDI/LED0

2 AD23 42 C/BE0 82 EBDA15/COL 122 VSSB

3 VSSB 43 VSSB 83 EBD7/TX_CLK 123 XCLK/XTAL

4 AD22 44 AD7 84 VSSB 124 VDDB

5 VDD_PCI 45 VDD_PCI 85 EBD6/RX_ER 125 LED2/MIIRXFRTGE

6 AD21 46 AD6 86 EBD5/RX_CLK 126 EESK/LED1/SFDB

7 AD20 47 AD5 87 EBD4/RX_DV 127 VSSB

8 VDD 48 VDD 88 VDDB 128 EECS

9 AD19 49 AD4 89 EBD3/RXD3 129 EAR

10 AD18 50 AD3 90 VSS 130 VSS

11 VSSB 51 VSSB 91 EBD2/RXD2 131 PME

12 AD17 52 AD2 92 EBD1/RXD1 132 WUMI

13 VDD_PCI 53 VDD_PCI 93 EBD0/RXD0 133 RWU

14 AD16 54 AD1 94 VAUXDET 134 TCK

15 C/BE2 55 AD0 95 VSSB 135 TMS

16 VSS 56 VSS 96 MIRQ (see Note) 136 VDDB

17 FRAME 57 EROMCS 97 VDD 137 TDO

18 IRDY 58 EBWE 98 MDATA (see Note) 138 VSSB

19 VSSB 59 AS_EBOE 99 VSSB 139 TDI

20 TRDY 6 0 EBCLK 100 MCLOCK (see Note) 140 VDD

21 VDD_PCI 61 EBUA_EBA0 101 VDDB 141 PG

22 DEVSEL 62 VSSB 102 XTAL2 142 INTA

23 STOP 63 EBUA_EBA1 103 XTAL1 143 RST

24 VDD 64 VDD 104 DVDDCO 144 CLK

25 PERR 65 VDDB 105 DVDDA 145 GNT

26 SERR 66 EBUA_EBA2 106 DVSSD 146 REQ

27 VSSB 67 EBUA_EBA3 107 IREF 147 VDD_PCI

28 PAR 68 EBUA_EBA4 108 DVDDD 148 AD31

29 VDD_PCI 69 EBUA_EBA5/MDC 109 TX+ 149 VSSB

30 C/BE1 70 EBUA_EBA6/

PHY_RST 110 DVDDTX 150 VSS

31 AD15 71 EBUA_EBA7/TX_ER 111 TX- 151 AD30

32 VSS 72 VSS 112 SDI+ 152 AD29

33 AD14 73 EBDA8/TXD0 113 DVSSX 153 AD28

34 AD13 74 VSSB 114 SDI- 154 AD27

35 VSSB 75 EBDA9/TXD1 115 RX+ 155 VDD_PCI

36 AD12 76 EBDA10/TXD2 116 DVDDRX 156 AD26

37 AD11 77 VDDB 117 RX- 157 VSSB

38 VDD_PCI 78 EBDA11/TXD3 118 DVDDP 158 AD25

39 AD10 79 EBDA12/TX_EN 119 DVSSP 159 AD24

40 AD9 80 EBDA13/MDIO 120 EEDO/LED3/

MIIRXFRTGD 160 C/BE3

Am79C973/Am79C975 23

PRELIMINARY

PIN DESIGNATIONS (PQL176) (Am79C973/Am79C975)

Listed By Pin Number

Note: For the Am79C973 controller, pins 106, 108, and 110 are no connects (NC).

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin No. Pin

Name

1NC 45NC 89NC 133 NC

2NC 46NC 90NC 134 NC

3 IDSEL 47 AD8 91 EBDA14/CRS 135 EEDI/LED0

4 AD23 48 C/BE0 92 EBDA15/COL 136 VSSB

5 VSSB 49 VSSB 93 EBD7/TX_CLK 137 XCLK/XTAL

6 AD22 50 AD7 94 VSSB 138 VDDB

7 VDD_PCI 51 VDD_PCI 95 EBD6/RX_ER 139 LED2/MIIRXFRTGE

8 AD21 52 AD6 96 EBD5/RX_CLK 140 EESK/LED1/SFDB

9 AD20 53 AD5 97 EBD4/RX_DV 141 VSSB

10 VDD 54 VDD 98 VDDB 142 EECS

11 AD19 55 AD4 99 EBD3/RXD3 143 EAR

12 AD18 56 AD3 100 VSS 144 VSS

13 VSSB 57 VSSB 101 EBD2/RXD2 145 PME

14 AD17 58 AD2 102 EBD1/RXD1 146 WUMI

15 VDD_PCI 59 VDD_PCI 103 EBD0/RXD0 147 RWU

16 AD16 60 AD1 104 VAUXDET 148 TCK

17 C/BE2 61 AD0 105 VSSB 149 TMS

18 VSS 62 VSS 106 MIRQ (see Note) 150 VDDB

19 FRAME 63 EROMCS 107 VDD 151 TDO

20 IRDY 64 EBWE 108 MDATA (see Note) 152 VSSB

21 VSSB 65 AS_EBOE 109 VSSB 153 TDI

22 TRDY 6 6 EBCLK 110 MCLOCK (see Note) 154 VDD

23 VDD_PCI 67 EBUA_EBA0 111 VDDB 155 PG

24 DEVSEL 68 VSSB 112 XTAL2 156 INTA

25 STOP 69 EBUA_EBA1 113 XTAL1 157 RST

26 VDD 70 VDD 114 DVDDCO 158 CLK

27 PERR 71 VDDB 115 DVDDA 159 GNT

28 SERR 72 EBUA_EBA2 116 DVSSD 160 REQ

29 VSSB 73 EBUA_EBA3 117 IREF 161 VDD_PCI

30 PAR 74 EBUA_EBA4 118 DVDDD 162 AD31

31 VDD_PCI 75 EBUA_EBA5/MDC 119 TX+ 163 VSSB

32 C/BE1 76 EBUA_EBA6/

PHY_RST 120 DVDDTX 164 VSS

33 AD15 77 EBUA_EBA7/TX_ER 121 TX- 165 AD30

34 VSS 78 VSS 122 SDI+ 166 AD29

35 AD14 79 EBDA8/TXD0 123 DVSSX 167 AD28

36 AD13 80 VSSB 124 SDI- 168 AD27

37 VSSB 81 EBDA9/TXD1 125 RX+ 169 VDD_PCI

38 AD12 82 EBDA10/TXD2 126 DVDDRX 170 AD26

39 AD11 83 VDDB 127 RX- 171 VSSB

40 VDD_PCI 84 EBDA11/TXD3 128 DVDDP 172 AD25

41 AD10 85 EBDA12/TX_EN 129 DVSSP 173 AD24

42 AD9 86 EBDA13/MDIO 130 EEDO/LED3/

MIIRXFRTGD 174 C/BE3

43 NC 87 NC 131 NC 175 NC

44 NC 88 NC 132 NC 176 NC

24 Am79C973/Am79C975

PRELIMINARY

PIN DESIGNATIONS (PQR160, PQL176)

Listed By Group

1. Not including test featu res

Pin Name Pin Function Type1Driver No. of Pins

PCI Bus Interface

AD[31:0] Address/Data Bus IO TS3 32

C/BE[3:0] Bus Command/Byte Enable IO TS3 4

CLK Bus Clock INA 1

DEVSEL Device Select IO STS6 1

FRAME Cycle Frame IO STS6 1

GNT Bus Grant INA 1

IDSEL Initiali zation Device Select INA 1

INTA Interrupt OOD6 1

IRDY Initiator Ready IO STS6 1

PAR Parity IO TS3 1

PERR Parity Error IO STS6 1

REQ Bus Request OTS3 1

RST Reset INA 1

SERR System Error OOD6 1

STOP Stop IO STS6 1

TRDY Target Ready IO STS6 1

Board Interface

LED0 LED0 OLED 1

LED1 LED1 OLED 1

LED2 LED2 OLED 1

LED3 LED3 OLED 1

XCLK External Clock Source Select INA 1

XTAL Crystal Select INA 1

XTAL1 Crystal Input -25 MHz Clock Reference INA 1

XTAL2 Crystal Output OXTAL 1

EEPROM Interface

EECS Serial EEPROM Chip Select OO6 1

EEDI Serial EEPROM Data In OLED 1

EEDO Serial EEPROM Data Out INA 1

EESK Serial EEPROM Clock IO LED 1

Expansion ROM Interface

AS_EBOE Address Strobe/Expansion Bus Output Enable OO6 1

EBCLK Expansion Bus Clock INA 1

EBD[7:0] Expansion Bus Data [7:0] IO TS6 8

EBDA[15:8] Expansion Bus Data/Address [15:8] IO TS6 8

EBUA_EBA[7:0] Expansion Bus Upper Address /Expansion Bus Address

[7:0] OO6 8

EBWE Expansion Bus Write Enable OO6 1

EROMCS Expansion Bus ROM Chip Select OO6 1

Am79C973/Am79C975 25

PRELIMINARY

PIN DESIGNAT IONS

Listed By Group

Note:

1. Not including test features.

Pin Name Pin Function Type1Driver No. of Pins

Physical Layer Interface (PHY)

IREF Internal Current Reference INA 1

RX± Serial Receive Data INA 2

TX± Seri al Trans m it Da ta ONA 2

SDI± Signal Detect Inpu t INA 2

Pow e r Mana gement Interface

RWU Remote W ak e Up OO6 1

PME Power Management Event OOD6 1

WUMI Wake-Up Mode Indication OOD6 1

PG Power Goo d INA 1

VAUXDET Auxiliary Power Det ect INA 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock INA 1

TDI Test Data In INA 1

TDO Test Data Out OTS6 1

TMS Test Mode Select INA 1

External Address Detection Interface (EADI)

EAR External Address Reject Lo w INA 1

SFBD Start Frame Byte Delimiter OLED 1

MIIRXFRTGD MII Receive Frame Tag Data INA 1

MIIRXFRTGE MII Receive Frame Tag Enable INA 1

Media Independent Interface (MII)

COL Collision INA 1

CRS Carrier Sense INA 1

MDC Managem ent D ata Clock OOMII2 1

MDIO Managem ent Data I/O I/O TSMII 1

RX_CLK Receive Clock INA 1

RXD[3:0] Receive Data INA 4

RX_DV Receive Data Valid INA 1

RX_ER Receive Error INA 1

TX_CLK Transmit Clock INA 1

TXD[3:0] Transmit Data OOMII1 4

TX_EN Transmit Data Enable OOMII1 1

TX_ER Transmit Error OOMII1 1

Serial Management Interface (SMI) - Am79C975 only

MCLOCK SMI Clock I/O OD6 1

MDATA SMI Data I/O OD6 1

MIRQ SMI Interrupt OOD6 1

26 Am79C973/Am79C975

PRELIMINARY

PIN DESIGNAT IONS

Listed by Group (Concluded)

Notes:

1. Not including test features.

2. PHY power and ground pins require careful decoupling to ensure proper device performance.

Pin Name Pin Function Type1Driver No. of Pins

Power Supplies (MAC, PCI, Buffer, ROM)

VDD Digital Power PNA 6

VSS Digital Ground PNA 7

VDDB I/O Buffer Power PNA 6

VSSB I/O Buffer Ground PNA 17

VDD_PCI PCI I/O Buffer Power PNA 9

Pow e r Supplies (PHY)2

DVDDA Analog PLL Power PNA 1

DVDDD, DVDDP Physical Data Transceiver (PDX) Power, IREF PNA 2

DVSSD, DVSSP Physical Data Transceiver (PDX) Ground PNA 2

DVDDTX, DVDDRX PHY I/O Buffer Power PNA 2

DVSSX PHY Ground PNA 1

DVDDCO Crystal Oscillator Power PNA 1

Am79C973/Am79C975 27

PRELIMINARY

PIN DESIGNAT IONS

Listed By Driver Type

The following table des cri bes th e various ty pes of out-

put drivers used in the Am79C973/Am79C975 control-

ler . All IOL and IOH values shown in the table apply to 3.3

V signaling.

A sustained tri-state signal is a low active signal that is

driv en high for one clock period before it is left floating.

TX is a differential output driver. Its characteristics and

thos e of X TAL2 output are des cribed in the DC Charac-

teristics secti on.

Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 -0.4 50

OMII1 Totem Pole 4 -4 50

OMII2 Totem Pole 4 -4 390

O6 Totem Pole 6 -0.4 50

OD6 Open Drain 6 NA 50

STS6 Sust ain ed Tri-State 6 -2 50

TS3 Tri-State 3 -2 50

TS6 Tri-State 6 -2 50

TSMII Tri-State 4 -4 470

28 Am79C973/Am79C975

PRELIMINARY

ORDERING INFORMATION

Standard Products

AMD stan dard products are availab le in se veral pac kages and operating ranges . The order number (Valid Combination) is f ormed

by a combination of the elements below.

AM79C973

AM79C975

TEMPERATURE RANGE

C = Commercial (0° C to +70° C)

SPEED OPTION

PACKAGE TYPE

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Not applicable

K = Plastic Quad Flat Pack (PQR160)

V = Thin Quad Fl at Pack (PQL176)

Am79C973/Am79C975

Single- Chip 10/10 0 Mb ps PCI Ethernet Cont roll er

with Integr ate d PHY

Valid Combinatio ns

AM79C973,

AM79C975 KC\W,

VC\W

ALTERNATE PACKAGING OPTION

\W = Tr immed and formed in a tray

K\V

Am79C973/Am79C975 29

PRELIMINARY

PIN DESCRIPTIONS

PCI Interface

AD[31:0]

A dd re s s a n d D a ta In p u t/Ou tp u t

Add ress and data are m ultiplexe d on the sam e b us inter-

face pins. During the first clock of a transaction, AD [31:0]

cont ain a physic al addres s ( 32 bi ts) . Dur ing t he subse-

quent clocks, AD [31:0] contain data. Byte ordering is little

endian by default. A D[7:0] are defined as the least signifi-

cant byt e (LSB) and AD[31: 24] are defined as the most

signif icant byte (MSB). For FIFO data transfers, the

Am79C973/Am 79C 975 controller can be program m ed for

big endian byte or dering. See CSR3, bit 2 ( BSWP) f o r

m ore details.

During the address phase of t he t ransact ion, when the

Am79C973/ Am79C975 cont rol l er i s a bus mast er,

AD[31:2] will addr ess the active Doubl e Word (DWord).

The Am79C973/ Am79C975 cont rol ler al ways dr i ves

AD[1 :0 ] to ’00’ during the address phase indicating linear

burst order. W hen the Am 79C973/Am 79C975 controller is

not a bus mast er, t he AD[ 31:0] li nes ar e conti nuous l y

monit or ed to det ermine i f an addr ess mat ch exis t s for

sla ve transfers.

During the data phase of t he tr ans action, AD[31:0] ar e

driven by the Am 79C973/Am 79C 975 controller when per-

form ing bus m aster write and slave read operations. Data

on AD[31:0] is latched by the Am 79C973/Am 79C975 con-

troller when per forming bus mast e r read and s lave write

operations.

When R ST is ac tive, AD[31:0] are inpu ts f or NAND tree

testing.

C/BE[3:0]

B us Co mma n d a n d Byt e E n a ble s

Input/Output

Bus command and byte enabl es are multiplexed on t he

sam e bus interface pins. D uring the address phase of the

t ransaction, C/ BE[ 3:0] define the bus command. During

the data phase, C/BE[3:0] are used as byte enables. The

byte enables define which physical byte lanes carry mean-

ingful data. C/B E0 applies to byte 0 (A D [7:0]) and C/BE3

applies to byte 3 (AD[31:24]). The function of the byte en-

ables is independ ent of the byte ordering mode (BSWP,

CSR3, bit 2).

When RST is active, C/BE[3:0] are inputs for NAND tree

testing.

CLK

C loc k Input

This clock is used to drive the system bus interfac e and

th e internal buf fe r management un it. All bus s igna ls are

sampled on the rising edge of CLK and all parameters are

def i ned wi t h respect t o t hi s edge. The Am79C973/

Am 79C 975 controller norm ally operates over a frequency

range of 10 to 33 MHz on the PC I bus due to netw orking

demands. See the Frequency Demands for Network Op-

eration s ect ion for det ail s. The Am79C973/ Am79C975

controller will support a clock frequency of 0 MHz after

certain precautions are taken to ensure data integrity . This

clock or a derivation is not used to drive any network func-

tions.

When RST is active, CLK is an input for N A ND tree test-

ing.

DEVSEL

De vice Select Inpu t/

Output

The Am79C973/ Am79C975 cont r ol ler dr ives DEVSEL

w hen it detects a transaction that selects the device as a

target. The device samples DE VSEL to detect if a target

claim s a transaction that the Am 79C 973/Am 79C975 con-

troller has initiated.

When RST is active, DEVSEL is an input for NAND tree

testing.

FRAME

C y cle F ra me In p u t /O utp u t

FRAME is driven by the Am 79C973/Am79C975 controller

when it is the bus master to indicate the beginning and du-

r ation of a tr ans ac tion. FRAME is asse rted to indicate a

bus t ransacti on is beginning. FRAME is asserted whi le

data transfers continue. FRA M E is deasserted before the

final data phase of a trans ac tion. When the Am79C973/

Am 79C975 controller is in slave mode, it samples FRAME

to determ ine the address phase of a transaction.

When RST is active, FRAME is a n in p ut fo r NAND tre e

testing.

GNT

B us Gra n t In p u t

This signal indicates that the access to the bus has been

granted to the A m79C 973/Am 79C 975 controller.

The A m 79C973/Am 79C 975 controller supports bus park-

ing. When the PCI b us is idle and the system arbiter as-

sert s GNT without an act ive REQ from the Am79C973/

Am79C975 cont roller, the device will drive the AD[31:0],

C/BE[3:0] and PAR lines.

When R S T is active , GNT is an input for N A N D tree test-

ing.

IDSEL

In itia liz a tio n D e v ic e Se le c t In p u t

Thi s signal is used as a chip select f or t he Am79C973/

Am79C975 controller during configuration read and w rite

transactions.

When RST i s act ive, IDSEL i s an input f or NAND tree

testing.

30 Am79C973/Am79C975

PRELIMINARY

INTA

Interrupt Request Output

An attention signal which indicates that one or more of

the follo wing status flags is set: EXDINT, IDON, MERR,

MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,

TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE-

INT, and S TINT. Each sta tus fla g has e ither a mask or

an enable bit wh ic h a llows for suppressi on of IN TA as-

sertion. Table 1 shows the flag descriptions. By default

INTA is an open-drain output. For applications that

need a high-active edge-sensiti ve interr upt signal, the

INTA pin can be configured for this mode by setting IN-

TLEVEL (BCR2, bit 7) to 1.

When RST is active, INTA is the output for NAND tree

testing.

IRDY

Initiator Ready Input/Output

IRDY indicate s the abi li ty of the initiator of the transac-

tion to compl ete the current data phase. IRDY is used

in conj un ctio n w i t h T RDY. W ait states are inserted until

both IRDY and TRDY are asserted simultaneously. A

data phase is completed on any clock when both IRDY

and TRDY are asserted.

When the Am79C973/Am79C975 controller is a bus

master, it asserts IRDY duri ng al l wr ite d ata pha ses t o

indicate that valid da ta is present o n AD[31:0]. Dur ing

all read data phase s, the device asser ts IRDY to ind i-

cate that it is ready to accept the data.

When the Am79 C973/Am79C975 controller is the tar-

get of a transaction, it checks IRDY during al l write d ata

phases to determine if valid data is present on

AD[31:0]. During all read data phases, the device

checks IRDY to determine if the initiator is ready to ac-

cept the data.

When RST is active, IRDY is an input for NAND tree

testing.

PAR

Parity Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0].

When the Am79C973/Am79C975 controller is a bus

master , it generates parity during the address and write

data phases. It checks parity during read data phases.

When the Am79C973/Am79C975 controller operates

in slave mode, it checks parity during every address

phase. When it is the target of a cyc le, it checks parity

during write data phases and it generates parity during

read data phase s.

When RST is active, PAR is an input for NAND tree

testing.

PERR

P arity Error Input/Output

During any slave write transaction and any master read

transaction, the Am79C973/Am79C975 controller as-

ser ts PERR when it detects a data parity error and re-

porting of the error is enabled by setting PERREN (PCI

Command register, bit 6) to 1. During any master write

transaction, the Am79C973/Am79C975 controller

monitors PERR to see if the target reports a data parity

error.

When RST is active, PERR is an in put for NAND tree

testing.

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

EXDINT Excessive

Deferral CSR5, bit 6 CSR5, bit 7

IDON Initialization

Done CSR3, bit 8 CSR0, bit 8

MERR Memory Error CSR3, bit 11 CSR0, bit 11

MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO Missed Frame

Count Over-

flow CSR4, bit 8 CSR4, bit 9

MPINT Magi c Packet

Interrupt CSR5, bit 3 CSR5, bit 4

RCVCCO Receive

Collision Count

Overflow CSR4, bit 4 CSR4, bit 5

RINT Receive

Interrupt CSR3, bit 10 CSR0, bit 10

SINT System E rror CSR 5, bit 10 CSR5, bit 11

TINT Transmit

Interrupt CSR3, bit 9 CSR0, bit 9

TXSTRT Tr ansmit Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCINT

MII

Management

Command

Complete

Interrupt

CSR7, bit 4 CSR7, bit 5

MPDTINT MII PHY Detect

Transition

Interrupt CSR7, bit 0 CSR7, bit 1

MAPINT MII Auto-Poll

Interrupt CSR7, bit 6 CSR7, bit 7

MREINT

MII

Management

Frame Read

Error Interrupt

CSR7, bit 8 CSR7, bit 9

STINT Software Timer

Interrupt CSR7, bit 10 CSR7, bit 11

Am79C973/Am79C975 31

PRELIMINARY

REQ

Bus Request Input/Output

The Am79C973/Am79C975 controller asserts REQ pin

as a signal that it wishes to become a b us master . REQ

is driven high when the Am79C973/Am79C975 control-

ler does not request the bus. In Power Management

mode, the REQ pin will not be driven.

When RST is active, REQ is an input for NAND tree

testing.

RST

Reset Input

When RST is asser ted LOW and the PG pin is H IGH,

then the Am79C973/Am79C975 controller performs an

internal system reset of the type H_RESET

(HARDWARE_RESET, see section on RESET). RST

must be held for a minimum of 30 clock periods. While

in the H_RESET state, the Am79C973/Am79C975

controller will disable or deassert all outputs. RST may

be asynchronous to clock when asserted or deas-

serted.

When the PG pin is LOW, R ST disables all of the P CI

pins except the PME pin.

When RST is LOW and PG is HIGH, NAND tree testing

is enabled.

SERR

System Error Output

During any slave transaction, the Am79C973/

Am79C975 controller asserts SERR when it detects an

address parity error, and repor ting of the error is en-

abled by setting PERREN (PCI Command r egister, bit

6) and SERREN (PCI Command register, bit 8) to 1.

By default SERR is an open-d rain out put. For compo-

nent test, it can be programmed to be an active-high

totem-pole output.

When RST is acti ve, SERR is an input for NAND tree

testing.

STOP

Stop Input/Output

In slave mode, the Am79C973/Am79C975 controller

driv es the STOP signal to inform the bus master to stop

the current transaction. In bus master mode, the

Am79C973/ Am79C9 75 controlle r checks STO P to de-

termine if the target wants to disconnect the current

transaction.

When RST is active, STOP is an input for NAND tree

testing.

TRDY

Target Ready Input/Output

TRDY indicate s the ability of the target of the tran sac-

tion to complete the current data phase. W ait states are

inserted until both IRDY and TRDY are asserted simul-

taneously. A data phase is completed on any clock

when both IRDY and TRDY are asserted.

When the Am79C973/Am79C975 controller is a bus

maste r, i t ch ecks TRDY du r ing all read data ph ases to

determine if valid data is present on AD[31:0]. During

all write data phases, the device checks TRD Y to deter-

mine if the target is ready to accept the data.

When the Am79C973/A m79C975 cont roller is the tar-

get of a transaction, it asserts TRDY during all read

data phases to indicate that valid data is present on

AD[31:0]. During all write data pha ses, the device as-

serts TRDY to indicate that it is ready to accept the

data.

When RST is active, TRDY is an input for NAND tree

testing.

PME

Power Management Event Output, Open Drain

PME is an output that can be used to indicate that a

power management ev ent (a Magic Pac k et, an OnNow

patter n match , or a change in li nk state) has bee n de-

tected. The PME pin is asserted when either

1. PME_STATUS and PME_EN are both 1, or

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1.

The PME signal is asynchronous with respect to the

PCI clock.

VAUXDET

Auxiliary Power Detect Input

VAUXDET is used to sense the pres ence of the auxi l-

iary power and correctly report the capability of assert-

ing PME signal in D3 cold. The VAUXDET pin should

be connected to the auxiliary power supply or to ground

through a resistor. If PCI power is used to power the de-

vice, a pull-dow n resi stor is r equir ed. For system s that

provide auxiliary power, the VAUXDET pin should be

tied to auxiliary power through a pull-up resistor.

Board Interface

Note: Before programming the LED pins, see the

description of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED. By de-

fault, LED0 indicates an active link connection. This pin

can also be programmed to indicate other network sta-

32 Am79C973/Am79C975

PRELIMINARY

tus (see BCR 4). The LED0 pin pola rity is programma-

ble , b ut b y default it is active LOW. When the LED0 pin

polarity is programmed to active LOW, the output is an

open drain driver. When the LED0 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Note: The LED0 pin is multiplexed with the EEDI pin.

LED1

LED1 Output

This output is designed to directly drive an LED. By de-

fault, LED1 indicates receive activity on the network.

This pin can also be programmed to indicate other net-

work status (see BC R5). The LE D1 p in pola r ity is pro-

grammable, but by default, it is ac tive LOW. W hen the

LED1 pin polarity is programmed to active LOW, the

output is a n o pen drain dr i ver. When the LE D1 pi n po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Note: The LED1 pin is multiplex ed with the EESK and

SFBD pins.

The LED1 pin is also used during EEPROM Auto-

Detection to deter mine whe ther or not a n EEPROM is

present at the Am79C973/Am79C975 controller inter-

face. At the last rising edge of CLK while RST is active

LOW, LED1 is sampled to determine the value of the

EEDET bit in BCR19. It is impor tant to maintain ade-

quate hold time around the rising edge of the CLK at

this time to ensure a correctly sa mpled value. A sam-

pled HIGH value means that an EEPROM is present,

and EEDET will be set to 1. A sampled LOW value

means that an EEPROM is not present, and EEDET

will be set to 0. See the EEPROM Auto-Detection sec-

tion for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead in

order to resolve the EEDET setting.

WARNING: The input signal level of LED1 mus t be

insured for correct EEPROM detection before the

deassertion of RST.

LED2

LED2 Output

This output is designed to directly drive an LED. This

pin can be programmed to indicate various network

status ( see BCR6) . The L ED2 pin pol arity is program-

mable, but by default it is active LOW. When the LED 2

pin polarity is programmed to active LO W, the output is

an open drain driver . When the LED2 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Note: The LED2 pin is multiplexed with the

MIIRXFRTGE pin.

LED3

LED3 Output

This output is designed to directly drive an LED. By de-

fau lt, LED3 indicates transmit activity on the network.

This pin can also be programmed to indicate other net-

work statu s (see BC R7). The LE D3 p in pola r ity is pro-

grammable, but by default it is active LOW. When the

LED3 pin polarity is programmed to active LOW, the

output is an ope n drain dri ver. When the LED3 pin po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Special attention must be given to the external circuitry

attached to this pin. When this pin is used to drive an

LED while an EEPROM is used in the system, then

buffering maybe required between the LED3 pin and

the LED circuit. If an LED circuit were directly attached

to this pin , it may create an IOL requi r eme nt th at coul d

not be met by the serial EEPROM attached to this pin.

If no EEP ROM is i nc lud ed i n t he s yst em d es ign or l ow

current LEDs are used, then the LED3 signal may be

directly connected to an LED without buffering. For

more details regarding LED connection, see the sec-

tion on LED Support.

Note: The LED3 pin is multiplex ed with the EEDO and

MIIRXFRTGD pins.

Power Good Input

The PG pin has two functions: (1) it puts the device into

Magic Packet™ mode, and (2) it blocks any resets

when the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is

set to 1, the device enters the Magic Packet mode.

When PG is LOW, a LOW assertion of the PCI RST pin

will only caus e the PCI inte r face pins (except for PME)

to be put in the high impedance state. The internal logic

will ignore the assertion of RST.

When PG is HIGH, assertion of the PCI RST pin

causes the controller logic to be reset and the configu-

ration information to be loaded from the EEPROM.

PG input should be kept high during the NAND tree

testing.

RWU

Remote Wake Up Output

R WU is an output that is asserted either when the con-

troller is in the Magic Pac k et mode and a Magic Pac ket

frame has been detected, or the controller is in the Link

Change Detect mode and a Link Change has been de-

tected.

This pin can drive the external system management

logic that causes the CPU to get out of a low power

Am79C973/Am79C975 33

PRELIMINARY

mode of operation. This pin is implemented f or designs

that do not support the PME function.

Three bits that are loaded from the EEPROM into

CSR116 can program the characteristics of this pin:

1. R WU_POL determines the polarity of the RWU sig-

nal.

2. If RWU_GATE bi t is set, RWU is forced to t he high

impedance state when PG input is LOW.

3. RWU_DRIVER determines whether the output is

open drain or totem pole.

The internal power-on-reset signal forces this output

into the high impedance state until after the polarity and

drive type have been determined.

WUMI

Wake-Up Mode Indicator Output

This ou tput, which is capable of dri ving an LED, i s as-

serted when the device is in Magic Pac ket mode. It can

be used to drive external logic that switches the device

power source fro m the main p ower supply to an aux il-

iary power supply.

EEPROM Interface

EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EE-

PROM that uses the 93C46 EEPROM interface proto-

col. EECS is connected to the EEPROM’s chip select

pin. It is controlled by either the Am79C973/Am79C975

controller during command portions of a read of the en-

tire EE PROM, or i ndirec tly by th e host s yste m by wri t-

ing to BCR19, bit 2.

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. E EDI is connecte d to the EEPROM’s data inpu t

pin. It is controlled by either the Am79C973/Am79C975

controller during command portions of a read of the en-

tire EEPROM, or indirectly by the host system

by writing to BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0 pin.

EEDO

EEPROM Data Out Input

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EED O is connecte d to the EEPROM’s data out-

put pin. It is controlled by either the Am79C973/

Am79C975Am79C973/Am79C975Am79C973/

Am79C975 controller during command portions of a

read of the entire EEPROM, or indirectly by the host

system b y reading from BCR19, bit 0.

Note: The EEDO pin is multiplex ed with the LED3 and

MIIRXFRTGD pins.

EESK

EEPROM Se rial Clock Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EESK is connected to the EEPROM’s cl ock pin.

It is controlled by either the Am79C973/Am79C975

controller directly during a read of the entire EEPROM,

or indirectly by the host system by writing to BCR19, bit

Note: The EESK pin is multiplex ed with the LED1 and

SFBD pins.

The EESK pin is also used during EEPROM Auto-

Detect ion to deter min e whether or not an EEPROM is

present at the Am79C973/Am79C975 controller inter-

face. At the rising edge of the last CLK edge while RST

is asserted, EESK is sampled to determine the v alue of

the EEDET bit in BCR19. A sampled HIGH value

means that an EEPROM is present, and EEDET will be

set to 1. A sampled LOW value means that an EE-

PROM is not present, and EEDET will be set to 0. See

the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead to re-

solve the EEDET setting.

WARNING: The input signal level of EESK must be

valid for correct EEPROM detection before the

deassertion of RST.

Expansion Bus Interface

EBUA_EBA[7:0]

Expansion Bus Upper Address/

Expansion Bus Address [7:0] Output

The EBUA_EBA[7:0] pins provide the least and most

significant bytes of address on the Expansion Bus. The

most significant address byte (address bits [19:16] dur-

ing boo t device access es) is valid on these pins at the

beginning of a boot device access, at the rising edge of

AS_EBOE. This upper address byte must be stored ex-

ter nally in a D flip- flop. D uring subs equent cycles of a

boot device access, address bits [7:0] are present on

these pins.

All EBUA_EBA[7:0] outputs are forced to a constant

lev el to conserve power while no access on the Expan-

sion Bus is being performed.

Note: EBUA_EBA[7:5] pins are multiplexed with the

TX_ER, PHY_RST, and MDC pins.

34 Am79C973/Am79C975

PRELIMINARY

EBDA[15:8]

Expansion Bus Data/Address [15:8] Input/

Output

When EROMCS is asserted low, EBDA[15:8] contain

address bits [15:8] for boot device accesses.

The EBDA[15:8] signals are driven to a constant level

to conserve power while no access on the Expansion

Bus is being performed.

Note: EBDA[15:8] pins are multiplexed with the

TXD[3:0], TX_EN, MDIO, CRS, and COL pins.

EBD[7:0]

Expansion Bus Data [7:0] Input/Output

The EBD[7:0] pins provide data bits [7:0] for EPROM/

FLASH accesses. The EBD[7:0] signals are internally

forced to a constant level to conser ve power while no

access on the Expansion Bus is being performed.

Note: EBD[7:0] pins are multiplexed with the

RXD[3:0], RX_DV, RX_CLK, RX_ER, and TX_CLK

pins.

EROMCS

Expansion ROM Chip Select Output

EROMCS serves as the chip select f or the boot device.

It is asserted low during the data phases of boot device

accesses.

AS_EBOE

Address Strobe/Expansion Bus

Output Enable Output

AS_EBOE functions as the address strobe for the

upper address bits on the EBU A_EBA[7:0] pins and as

the output enable for the Expansion Bus.

As an address strobe, a rising edge on AS_EBOE is

supplied at the beginning of boot device accesses. This

rising edge provides a clock edge for a ‘374 D-type

edge-triggered flip-flop which must store the upper ad-

dress byte during Expansion Bus accesses for

EPROM/Flash.

AS_EBOE is asser ted active LOW during boot device

read operations on the expansion bus and is deas-

serted during boot device write operations.

EBWE

Expansion Bus Write Enable Output

EBWE p rovides the wr ite e nable fo r writ e accesse s to

the Flash device.

EBCLK

Expansion Bus Clock Input

EBCLK may be used as the fundamental clock to drive

the Expan sion Bus and inte rn al SRAM a ccess cycles.

The actual internal clock used to drive the Expansion

Bus cycles depends on the values of the EBCS and

CLK_FAC settings in BCR27. Refer to the SRAM Inter-

face Bandwidth Requirements section for details on de-

termining the required EBCLK frequency. If a clock

source other than the EBCLK pin is programmed

(BCR27, bits 5:3) to be used to run the Expansion Bus

interface, this input should be tied to VDD through a 4.7

kW resistor.

EBCLK is not used to drive the bus interface, internal

buffer management unit, or the network functions.

Media Independent Interface (MII)

TX_CLK

Transmit Clock Input

TX_CLK is a continuous clock input that provides the

timing reference for the transfer of the TX_EN,

TXD[3:0], and TX_ER signals out of the Am79C973/

Am79C975 device. TX_CLK must provide a nibble rate

clock (25% of the network data rate). Hence, an MII

transceiver operating at 10 Mbps must provide a

TX_CLK frequency of 2.5 MHz and an MII transceiver

operating at 100 Mbps must provide a TX_CLK fre-

quency of 25 MHz.

Note: The TX_CLK pin is multiplexed with the EBD7

pin.

TXD[3:0]

Transmit Data Output

TXD[3:0] is the nibble-wide MII transmit data bus. Valid

data is generated on TXD[3:0] on every TX_CLK rising

edge while TX_EN is asserted. While TX_EN is de-

asser ted, TXD[3:0] values are dr iven to a 0. TXD[3:0]

transitions synchronous to TX_CLK rising edges.

Note: The TXD[3:0] pins are multiplexed with the

EBDA[11:8] pins.

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C973/Am79C975 de-

vice is presenting valid transmit nibbles on the MII.

While TX_EN is asser ted, the Am79C973/Am79C975

device generates TXD[3:0] and TX_ER on TX_CLK ris-

ing edges. TX_EN is asserted with the first nibble of

preamble and remains asserted throughout the dura-

tion of a packet until it is deasserted prior to the first

TX_CLK following the final nibble of the frame. TX_EN

transitions synchronous to TX_CLK rising edges.

Note: The TX_EN pin is multiplexed with the EBDA 12

pin.

TX_ER

Transmit Error Output

TX_E R is an outpu t tha t, if asserted while TX_EN i s as-

ser ted, ins tructs the MII PHY device connecte d to the

Am79C973/Am79C975 device to transmit a code

Am79C973/Am79C975 35

PRELIMINARY

group error. TX_ER is unused and is reserved for future

use and will always be driven to a logical zero.

Note: The TX_ER pin is multiplexed with the

EBUA_EBA7 pin.

COL

Collision Input

COL is an input that indicates that a collision has been

detected on the network medium.

Note: The COL pin is multiplexed with the EBDA15

pin.

CRS

Carrier Sense Input

CRS is an input tha t indicates that a non -idle med ium,

due eithe r to transmit or recei ve activi ty, has been d e-

tected.

Note: The CRS pin is multiplexed with the EBDA14

pin.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII trans-

ceiver device has detected a coding error in the receive

frame currently being transferred on the RXD[3:0] pins.

When RX_E R is asser t ed while RX_DV is asser t ed, a

CRC error will be indicated in the receiv e descriptor for

the incoming receive frame. RX_ER is ignored while

RX_DV is d eas se rted. Speci al code group s gen erate d

on RXD while RX_DV is deasserted are ig nored (e.g.,

Bad SSD in TX and IDLE in T4). RX_ER transitions are

synchronous to RX_CLK rising edges.

Note: The RX_ER pin is multiplexed with the EBD6

pin.

MDC

Management Data Clock Output

MDC is a non-c ontinuous clock output t hat provides a

timing reference for bits on the MDIO pin. Dur ing MII

managemen t port operations, MDC r uns at a nominal

frequency of 2.5 MHz. When no management opera-

tions are in progress, MDC is driven LOW. The MDC is

derived from the Time Base Clock.

If the MII port is not sel ected, the MDC pin can be left

floating.

Note: The MDC pin is multiplexed with the

EBUA_EBD5 pin.

MDIO

Management Data I/O Input/Output

MDIO is the bidirectional MII management port data

pin. MDIO is an output during the header portion of the

managemen t frame transfers and dur ing the data por -

tions of write transfers. MDIO is an input during the

data portions of read data transfers. When an operation

is not in progress on the management port, MDIO is not

driven. MDIO transitions from the Am79C973/

Am79C975 controller are synchrono us to MDC falling

edges.

If the PHY is attached through an MII physical connec-

tor , then the MDIO pin should be externally pulled down

to VSS with a 10-kΩ ±5% resistor. If the PHY is on

board, then the MDIO pin should be externally pulled

up to VCC with a 10-kΩ ±5% resistor.

Note: The MDIO pin is multiplexed with the EBDA13

pin.

PHY_RST

Physical Layer Reset Output

PHY_R ST is an output pin that is used to reset an ex-

ternal PHY. This output eliminates the need for a fan

out buffer for the PCI RST si gnal, provides polar ity for

the specific external PHY used, and prev ents the reset-

ting of the external PHY when the PG input is LOW.

The output polarity is determined by RST_POL bit

(CSR 116, bit 0).

Note: The PHY_RST pin is multiplexed with the

EBUA_EBA6 pin.

RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing refer-

ence for the transfer of the RX_DV, RXD[3:0], and

RX_ER signals into the Am79C973/Am79C975 device.

RX_CLK mus t provide a nibble rate clo ck (25% o f the

network data rate). Hence, when the Am79C973/

Am79C 975 device is opera tin g a t 10 Mbps, it provides

an RX_CLK fr eq uen cy o f 2. 5 M Hz, and at 10 0 M bps i t

provides an RX_CLK frequency of 25 MHz.

Note: The RX_CLK pin is multiplexed with the EBD5

pin.

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII-compatible receive

data bus. Data on RXD[3:0] is sampled on every rising

edge of RX_CLK while RX_D V is asserted. RXD[3:0] is

ignored while RX_DV is de-asserted.

Note: The RXD[3:0] pin is multiplexed with the

EBD[3:0] pins.

RX_DV

Receive Data Valid Input

RX_DV is an input used to in dicate tha t valid received

data is being presented on the RXD[3:0] pins and

RX_CLK is synchronous to the receive data. In order

for a frame to be fully received by the Am79C973/

Am79C975 device, RX_DV must be asserted prior to

the RX_CLK rising edge, when the first nibble of the

36 Am79C973/Am79C975

PRELIMINARY

Start of Frame Delimiter is driven on RXD[3:0], and

must remain asserted until after the rising edge of

RX_CLK, wh en t he l ast n ibble of the CRC is driven on

RXD[3:0]. RX_DV must then be deasserted prior to the

RX_CLK rising edge which follows this final nibble.

RX_DV transiti ons are synchrono us to RX_CLK r ising

edges.

Note: The RX_DV pin is multiplexed with the

EBD4 pin.

External Address Detection Interface

EAR

External Address Reject Low Input

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the re-

sult of this check will be OR’d with the value on the EAR

pin. The EAR pin is defined as REJECT. The pin value

is OR’d with the internal address detection result to de-

ter mine if the curr ent frame sho uld be ac cepted or re-

jected.

The EAR pin must not be left unco nnected, it should

be tied to VDD through a 10-kΩ ±5% re si stor.

When RST is active, EAR is an input for NAND tree

testing.

SFBD

Start Frame-Byte Delimiter Output

An initial rising edge on the SFBD signal indicates that

a start of valid data is present on the RXD[3:0] pins.

SFBD will go high for one ni bb le ti me (4 00 ns wh en op-

erating at 10 Mbps and 40 ns when operating at 100

Mbps) one R X_C LK pe riod a fter RX_ DV h as b een as -

ser ted and RX_ER is deass er ted a nd the detec tion of

the SFD (Start of F rame Delimiter) of a received frame.

Data on the RXD[3:0] will be the start of the destination

address field. SFBD will subsequently toggle ev ery nib-

ble time (1.25 MHz frequency when operating at 10

Mbps and 12.5 M Hz fr equency when o perating at 10 0

Mbps) indicating the first nibble of each subsequent

byte of the received nibble stream. The RX_CLK

should be used in conjunction with the SFBD to latch

the correct data for exter nal address matching. SFB D

will be active only during frame reception.

Note: The SFBD pin is multiplex ed with the EESK and

LED1 pins.

MIIRXFRTGD

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII Snoop mode is selected, the MIIRX-

FRTGD pin becomes a data input pin for the Receive

F rame Tag. See the Receiv e F r ame Tagging section f or

details.

Note: The MIIRXFRTGD pin is multiplexed with the

EEDO and LED3 pin s.

MIIRXFRTGE

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the

Receive Frame Tagging is enabled (RXFRTG, CSR7,

bit 14), and the MII Snoop mode is selected, the MIIRX-

FRTGE pin becomes a data input enable pin for the Re-

ceive Frame Tag. See the Receive Frame Tagging

section for details.

Note: The MIIRXFRTGE pin is multiplexed with the

LED2 pin.

IEEE 1149.1 (1990) Test Access Port

Interface

TCK

T est Clock Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull up resistor.

TDI

T est Data In Input

TDI is the test data input path to the Am79C973/

Am79C975 controller. The pin has an internal pull up

resistor.

TDO

Test Data Out Output

TDO is the test data ou tput path fr om the Am79 C973/

Am79C975 controller. The pin is tri-stated when the

JTAG port is inactive.

TMS

Test Mode Select Input

A ser ial inpu t bit stream on the TMS pin is used to de-

fine the specific boundary scan test to be executed.

The pin has an internal pull up resistor.

Network Interfaces

TX+, TX-

Serial Transmit Data

MLT-3/PECL Output

These p ins are the 10BA SE-T/100BA SE-X differential

driv ers. F or 100BASE-FX, these transmit outputs carry

differenti al P ECL -level NRZ I d ata for direct c onn ec tio n

to an external fiber optic transceiver. They can be

forced to logical 0 (TX+ low, TX- high) by programming

the TX_DISABLE bit (bit 3 of the internal PHY Control/

Status Register, Register 17). For 100BASE-TX, these

pins carry ML T-3 data and are connected to the primary

side of the magnetics module. For 10BASE-T, these

Am79C973/Am79C975 37

PRELIMINARY

pins ca rr y the trans mit output data and are connecte d

to the transmit side of the magnetics module.

RX+, RX-

Serial Receive Data

MLT-3/PECL Input

These pins are the 10BAS E-T/100BASE-X po r t differ-

ential rec eiver pairs. They receive MLT- 3 data and are

connected to the receive side of the magnetics module

in 100BASE-TX operation. They receive PECL NRZI

data from an external fiber optic transceiver in

100BASE-FX application. For 10BASE-T, these pins

accept the receive input data from the magnetics mod-

ule.

SDI+, SDI-

Signal Detect Input

These pins control the selection between PECL and

MLT-3 data for the TX± and RX± pins. For 100BASE-

TX or 10BASE-T, both of these pins may be tied to

ground or left floating. This enables transmission and

reception of MLT-3 or 10BASE-T signals at the TX± and

RX± pins. For 100BASE-FX, these pins are biased at

PECL levels. They are connected to the SDI pin from

the optica l transceiver module to in dicate whether th e

received si gnal is above the requir ed threshol d. If sig-

nal detec t is no t available, these pins shoul d b e ti ed t o

a PECL logical 1 (SDI+ = PECL 1, SDI- = PECL 0). See

Table 2.

Table 2. SDI± Settings for Transceiver Operation

IREF

Internal Current Reference Input

This pin serves as a current reference for the integrated

10/100 PHY. It must be connected to ground via a

12 kΩ resistor (1%).

Clock Interface

XTAL1

Crystal Input Input

The in ter nal clock generat or uses a 25-MHz ( 50 ppm-

100 ppm) crystal that is attached to the XTAL1 and

XTAL2 pins. XTAL1 may alternatively be driven using

an external 25 MHz (50 ppm - 100 ppm) CMOS-level

clock signal when XTAL2 is left floating. The XTAL1 pin

is not 5 V to lerant and must o nly be driven by a 3.3 V

clock source.

XTAL2

Crystal Output Output

The inte r n al clock gene rator uses a 2 5 MHz (50 p pm -

100 ppm) crystal that is attached to the pins XTAL1 and

XTAL2. XTAL1 may alternatively be driven using an ex-

ternal 25 MH z (50 ppm - 100 ppm) CMOS-level clock

signal when XTAL2 is left floating.

XCLK/XTAL

External Clock/Crystal Select Input

When HIG H, a n E xt ernal Cl ock Sour ce i s sel ec ted by-

passing the Crystal circuit. When LOW, a Crystal is

used instead. The f ollowing table illustrates how this pin

works.

Serial Management Interface (SMI)

(Am79C975 only)

MCLOCK

SMI Clock Input/Output

MCLOCK is the clock pin of the serial management in-

terface. MCLOCK is typically driv en by an external I2C/

SMBus master. The Am79C975 controller will drive the

clock line low in order to insert wait states before it

starts se ndi ng out d ata i n res po ns e to a read. T h e fr e-

quency of the clock signal can vary between 10 kHz

and 100 kHz, and it can change from cycle to cycle.

Note: MCLOCK is also capable of running at a fre-

quency as high as 2.5 MHz to allow f or shorter produc-

tion test time.

MDATA

SMI Data Input/Output

MDATA is the da ta pin of the s er i al man age ment inter-

face. MDATA can b e driven by an exter nal I2C/SMBus

master or by the Am79C975 controller. The interface

protocol defines exactly at what time the Am79C975

controller has to listen to the MDATA pin and at what

time the controller must drive the pin.

MIRQ

SMI Interrupt Output

MIRQ is an asynchronous attention signal that the

Am79C975 controller provides to indicat e that a man-

agement frame has been transm itted or rec eived. The

assertion of the MIRQ signal can be controlled by a glo-

bal mask bit (MIRQEN) or individual mask bits

SDI+ SDI- Port Mode

TTL LOW

(<0 .8 V) TTL LOW

(<0.8 V) MLT-3/10BASE-T

Mode

TTL HIGH

(>2 .0 V) TTL HIGH

(>2.0 V) PECL Mode

Input Pin Output

Pin XCLK/XTAL Clock Source

XATL1 XTAL2 0 Crystal

XTAL1 Don’t Care 1 Oscillator/

External CLK

Source

38 Am79C973/Am79C975

PRELIMINARY

(MRX_DONEM, MTX_DONEM) located in the Com-

mand registe r.

Note: The SM I inte rru pt acknowledge d oes n ot follow

the SMBus al ert pr otocol, but simply requires clear ing

the interrupt bit.

Power Supply

VDDB

I/O Buffer Power (6 Pins) +3.3 V Power

There are sev en power supply pins that are used by the

input/output buffer drivers. All VDDB pins must be con-

nected to a +3.3 V supply.

VDD_PCI

PCI I/O Buffer Power (9 Pins) +3.3 V Power

There ar e n ine power suppl y pi ns tha t are used by the

PCI input/out put buffer drivers (except PME driver). All

VDD_PCI pins must be connected to a +3.3 V supply.

VSSB

I/O Buffer Ground (17 Pins)

Ground

There are 17 ground pins that are used by the input/

output buffer drivers.

VDD

Digital Power (6 Pins) +3.3 V Power

There are six power supply pins that are used by the in-

ter na l dig ita l cir cuitry. All VDD pins must be con nec te d

to a +3.3 V supply.

VSS

Digital Ground (8 Pins) Ground

There are ei ght ground pin s tha t are use d by the inter-

nal digital circuitry.

DVDDD, DVDDP

PDX Block Power +3.3 V Power

These pins supply power to the 100 Mbps Physical

Data Transceiver (PDX) block. They must be con-

nected to a +3.3 V ±5% source. These pins require

careful decoupling to ensure proper device perfor-

mance.

DVDDRX, DV DDTX

I/O Buffer Power +3.3 V Power

These pins supply power to the MLT-3/PECL/10BASE-

T input/ou tput buffers. They also supply the MLT-3 cir-

cuits (equalizer , etc.) of the network port. They must be

connected to a +3.3 V ±5% source. These pins require

careful decoupling to ensure proper device perfor-

mance.

DVDDA

Analog PLL Power +3.3 V Power

This pin s upplies power to the IRE F current reference

circuit and the 10BASE-T analog PLL. They must be

connected to a +3.3 V ±5% source. These pins require

careful decoupling to ensure proper device perfor-

mance.

DVSSX

All Blocks Ground

These pins are th e ground conn ection for all blocks of

the d e vice e xce pt th e PDX b loc k. Th ey m ust be direct ly

connected to the common external ground plane.

DVSSD, DVSSP

PDX Ground Ground

These pins are the ground co nnection for the Physical

Data Transceiver (PDX) block. They must be directly

connected to the common external ground plane.

DVDDCO

Crystal +3.3 V Power

This pin supplies the power to the Crystal circuit.

Am79C973/Am79C975 39

PRELIMINARY

BASIC FUNCTIONS

System Bus Interface

The Am79C973/Am79C975 controllers are designed

to operate as a bus mast er during no rmal operations.

Some slave I/O accesses to the Am79C973/

Am79C975 controllers are required in normal opera-

tions as well. Initialization of the Am79C973/

Am79C975 controllers are achieved through a combi-

nation of PCI Configuration Space accesses, bus slave

access es, bus master acc esses, and an o ptional r ead

of a serial EEPROM that is performed by the

Am79C973/Am79C975 controllers. The EEPROM

read operation is performed through the 93C46 EE-

PROM interface. The ISO 8802-3 (IEEE/ANSI 802.3)

Ethernet Address may reside within the serial EE-

PROM. Some Am79C973/Am79C975 controller con-

figuration registers may also be programmed by the

EEPROM read operation.

The Address PROM, on-chip board-configuration reg-

isters, and the Ether net control ler registers occupy 32

bytes of address space. I/O and memor y mapped I/O

accesses are supported. Base Address registers in the

PCI configuration space allow locating the address

space on a wide variety of starting addresses.

For disk less stations, the A m79C973/Am79 C975 con-

trollers support a ROM or Flash-based (both referred to

as the Expansion ROM throughout this specification)

boot device of up to 1 Mbyte in size. The host can map

the boot device to any memory address that aligns to a

1-Mbyte boundary by modifying the Expansion ROM

Base Address register in the PCI configuration space.

Software Interface

The software interface to the Am79C973/Am79C975

control le rs are di v ide d in to three parts. One part is the

PCI configuration registers used to identify the

Am79C973/Am79C975 controllers and to setup the

configuration of the device. The setup information in-

cludes the I/O or memory mapped I/O base address,

mapping of the Expansion ROM, and the routing of the

Am79C973/Am79C975 controller interrupt channel.

This allows for a jumperless implementation.

The secon d por tion of the software interface is the d i-

rect access to the I/O resources of the Am79C973/

Am79C975 controllers. The Am79C973/Am79C975

controllers occupy 32 bytes of address space that must

begin on a 32-byte block boundary. The address space

can be mapped into I/O or memory space (memory

mapped I/O). The I/O Base Address Register in the

PCI Con figuration Space controls the s tar t address o f

the address space if it is mapped to I/O space. The

Memory Mapped I/O Base Address Register controls

the star t address of the address space if it is mappe d

to memory space. The 32-byte address space is used

by the so f t w are to pr ogram th e Am 79 C 973 / Am 79 C9 75

controller operating mode, to enable and disable vari-

ous features, to monitor operating status, and to re-

quest particular functions to be executed by the

Am79C973/Am79C975 controllers.

The third por tion of the software interface is the de-

scriptor and buffer areas that are shared between the

software and the Am79C973/Am79C975 controllers

during normal network operations. The descriptor area

bounda r ie s a re set by the soft ware an d do not ch ange

during normal network operations. There is one de-

scriptor area for receive activity and there is a separate

area for transmit activity. The descriptor space contains

relocatable pointers to the network frame data, and it is

used to transfer frame status from the Am79C973/

Am79C975 controllers to the software. The buffer

areas are locations that hold frame data for transmis-

sion or that accept frame data that has been received.

Network Interfaces

The Am79C973/Am79C975 controllers provide all of

the PHY layer functions for 10 Mbps (10BASE-T) or

100 Mbps (100BASE-TX). It also provides a Pseudo

ECL (PECL) interface for 100BASE-FX fiber networks.

The Am79C973/Am79C975 controllers support both

half-dup lex and ful l-duplex operation on ne twork inter -

faces.

Serial Management Interface

(Am79C975)

The Am79C975 controller provides a 3-pin interface

based on the I2C and SMBus standards that enables a

system to monitor the status of the system hardware

and report the results to the management station or

system administrator. Monitored information may in-

clude critical system parameters, such as voltage, tem-

perature, and fan speed, as well as system

management ev ents, such as chassis intrusion, operat-

ing system errors and power-on failures.

MII Interface

The Am79C973/Am79C975 supports an MII interface

mode that makes the device operate like a

PCnet-F AST+ device. The MII pins are multiplex ed with

the expansion bus pins, which means the device will

only support either an EPROM/Flash or an external

PHY but no t bo th. To enter this m ode, set PHYSE LEN

(BCR2, bit 13) = 1 and PHYSEL (BCR18, bit 4 and

bit 3) = 10. This mode isolates the internal PHY to allow

interface with an external PHY. For a more detailed de-

scri ption of the M II inte rface inc luding timing diagrams

see Appendix C. Refer to the connection diagram to

see how the pins are multiplexed.

40 Am79C973/Am79C975

PRELIMINARY

DETAILED FUNC TIONS

Slave Bus Interface Unit

The slave b us interface unit (BIU) controls all accesses

to the PCI configura tion space, the Cont rol and Status

Registers (CSR), the Bus Configuration Registers

(BCR), the Address PROM (APROM) locations, and

the Expansion ROM. Table 3 shows the response of

the Am79C973/Am79C975 controllers to each of the

PCI commands in slave mode.

Table 3. Slave Commands

Slave Configuration Transfers

The host can access the Am79C973/Am79C975 PCI

configuration space with a configuration read or wr ite

command. The Am79C973/Am79C975 controllers will

assert DEVSEL during the address phase when IDSEL

is asser ted, AD[1:0] are both 0, and the access is a

configura tion cycle. AD[7:2] sele ct the DWord loca tion

in the configuration space. The Am79C973/Am79C975

controllers ignore AD[10:8], because it is a single func-

tion device. AD[31:11] are don’t care .

The active bytes within a DW ord are determined by the

byte enable sig nals. Eight-bit, 16-bit, a nd 32-bit tran s-

fers are suppor ted . DEVSEL is assert ed two clock cy-

cles after the host has asserted FRAME. All

configuration cycles are of fixed length. The

Am79C973/Am79C975 controllers will assert TRDY on

the third clock of the data phase.

The Am7 9C973/A m79C975 contr ollers do not su pport

bu rst tr ansf ers f or acc ess to co nfigur ation sp ace. Wh en

the host keeps FRAME asserted for a second data

phase, the Am79C973/Am79C975 controllers will dis-

connect the transfer.

When the host tries to access the PCI configuration

space while the automatic read of the EEPROM after

H_RESET (see section on RESET) is on-going, the

Am79C973/Am79C975 controllers will terminate the

access on the PCI bus with a disconnect/retry re-

sponse.

The Am79C973/Am79C975 controllers support fast

back-to-back transactions to different targets. This is in-

dicated by the F ast Back-To-Back Capable bit (PCI Sta-

tus register, bit 7), which is hardwired to 1. The

Am79C973/Am79C975 controllers are capable of de-

tecting a configuration cycle even when its address

phase immediately follows the data phase of a transac-

tion to a different target without any idle state in-be-

tween. There will be no contention on the DEVSEL,

TRDY, and STOP signals, since the Am79C973/

Am79C 975 controller s asser t DEVSE L on the second

clock afte r FRAME is asserted (medium timing).

Slave I/O Transfers

After the Am79C973/Am79C975 controllers are config-

ured as an I/O device by setti ng IOEN (for regula r I/O

mode) or MEMEN (for memory mapped I/O mode) in

the PCI Command register, it starts monitoring the PCI

bus for acce ss to i ts CSR, B CR, or AP ROM locati ons.

If configured for regular I/O mode, the Am79C973/

Am79C975 controllers will look for an address that falls

within its 32 bytes of I/O addres s space (star ting f rom

the I/O base address). The Am79C973/Am79C975

controllers assert DEVSEL if it detects an address

match and the acces s is an I /O cy cle. If conf igure d for

memory mapped I/O mode, the Am79C973/

Am79C975 controllers will look for an address that falls

within its 32 bytes of me mory ad dress spa ce (star ting

from the memory mapped I/O base address). The

C[3:0] Command Use

0000 Interrupt

Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Read of CSR, BCR, APROM,

and Reset registers

0011 I/O Write Write to CSR, BCR, and

APROM

0100 Reserved

0101 Reserved

0110 Memory Read

Memory mapped I/O read of

CSR, BCR, APROM, and

Reset registers

Read of the Expansion Bus

0111 Memory Write Memory mapped I/O write of

CSR, BCR, and APROM

1000 Reserved

1001 Reserved

1010 Configuration

Read Read of the Configuration

Space

1011 Configuration

Write Write to the Configuration

Space

1100 Memory Read

Multiple Aliased to Memory Read

1101 Dual Address

Cycle Not used

1110 Memory Read

Line Aliased to Memory Read

1111 Memory Write

Invalidate Aliase d to Memory Write

AD31

AD11 AD10

AD8 AD7

AD2 AD1 AD0

Don’t care Don’t care DWord

index 00

Am79C973/Am79C975 41

PRELIMINARY

Am79C973/Am79C975 controllers assert DEVSEL if it

detects an address match and the access is a memory

cycle. DEVSEL is asserted two clock cycles after the

host has asserted FRAME. See Figure 1 and Figure 2.

Figure 1. Slave Configuration Read

The Am79C973/Am79C975 controllers will not assert

DEVSEL if it detects an address match and the PCI

command is not of the correct type. In memory mapped

I/O mode, the Am79C973/Am79C975 controller aliases

all accesses to the I/O resources of the command types

Memory Read Multiple and Memo ry Read Line to the

basic Memory Read command. All accesses of the type

Memory Write and Invalidate are aliased to the basic

Memory Write command. Eight-bit, 16-bit, and 32-bit

non-burst transactions are supported. The Am79C973/

Am79C975 controllers decode all 32 address lines to

determine which I/O resource is accessed.

The typica l numb er of wait states added to a slave I/O

or memory mapped I/O read or write access on the part

of the Am79C973/Am79C975 controllers are six to sev-

en clock cycles, depending upon the relative phases of

the internal Buffer Management Unit clock and the CLK

signal, since the internal Buffer Management Unit clock

is a divide-by-two version of the CLK signal.

The Am7 9C973/A m79C975 contr ollers do not su pport

burst transfers for access to its I/O resources. When the

host keeps FRAME asserted for a second data phase,

the Am79C973/Am79C975 controllers will disconnect

the transfer.

Figure 2. Slave Configuration Write

The Am79C973/Am79C975 controllers support fast

back-to-back transactions to different targets. This is

indicated by the Fast Back-To-Back Capable bit (PCI

Status register, bit 7), which is hardwired to 1. The

Am79C973/Am79C975 controllers are capable of de-

tecting an I/O or a memory-mapped I/O cycle even when

its address phase immediately fol lows the data phase

of a transaction to a different target, without any idle

state in-between. There will be no contention on the

DEVSEL, TRDY, and STOP signals, since the

Am79C 973/Am79C9 75 contr ollers a sser t DE VSEL on

the second clock after FRAME is asserted (medium tim-

ing) See Figure 3 and Figure 4.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1010

PAR PAR PAR

DEVSEL is sampled

DATA

ADDR

21510D-6

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1011

PAR PAR PAR

DATA

ADDR

21510D-7

42 Am79C973/Am79C975

PRELIMINARY

Figure 3. Slave Read Using I/O Command

Figure 4. Slave Write Using Memory Command

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0010

PAR

1 2345678 109 11

DATA

PAR

21510D21510D-8

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0111

PAR

1 2345678 109 11

DATA

PAR

21510D-9

Am79C973/Am79C975 43

PRELIMINARY

Expansion ROM Transfers

The host mus t initiali ze the Expansi on ROM Base Ad-

dress register at offset 30H in the PCI configuration

space wi th a valid add ress b efore enabling the ac ce ss

to the device. The Am79C973/Am79C975 controllers

will not react to any access to the Expansion ROM until

both MEMEN (PCI Command register, bit 1) and

ROMEN (PCI Ex pansion ROM B ase Ad dres s reg ister,

bit 0) are set to 1. After the Expansion ROM is enabled,

the Am79C973/Am79C975 controllers will assert

DEVSEL on all memory read accesses with an address

between ROMBASE and ROMBASE + 1M - 4. The

Am79C9 73/Am79C975 controller a liases all accesses

to the Expansion ROM of the command types Memory

Read Multiple and Memory Read Line to the basic

Memory Read command. Eight-bit, 16-bit, and 32-bit

read transfers are supported.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given

the PCI Memor y Mapped I/O Base Address register

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base

Address register to a value that prevents the

Am79C973/Am79C975 controllers from claiming any

memory cycles not intended for it.

The Am79C973/Am79C975 controllers will always

read four b ytes for e very host Expansion ROM read ac-

cess. T RDY will not be asser ted until all four bytes are

loaded into an internal scratch register. The cycle

TRDY is as se rted depend s o n th e programming o f th e

Expansion ROM interface timing. The following figure

(Figure 5) assumes that ROMTMG (BCR18, bits 15-

12) is at its default value.

Note: The Expansion ROM should be read only during

PCI configuration time for the PCI system.

When the host tries to write to the Expansion ROM, the

Am79C973/Am79C975 co ntrollers will claim the cycle

by asserting DEVSEL. TRD Y will be asserted one clock

cycle later. The write operation will have no effect.

Writes to the Expansion ROM are done through the

BCR30 Expansion Bus Data Por t. See the section o n

the Ex pans i on Bu s In ter face for more detai ls. See Fig-

ure 5.

Figure 5. Expansion ROM Read

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

CMD

PAR

1 2345 484950

DATA

PAR

DEVSEL is sampled 21510D-10

44 Am79C973/Am79C975

PRELIMINARY

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55H (byte 0) and AAH (byte 1).

Slave Cycle Termination

There are three scen arios besides nor mal comple tion

of a transaction where the Am79C973/Am79C975 con-

trollers are the tar get of a slave cycle and it will ter mi-

nate the access.

Disconnect When Busy

The Am79C9 73/Am7 9C975 con troll ers cann ot service

any slave access while it is reading the contents of the

EEPROM. Simultaneous access is not allowed in order

to avoid conflicts, si nce the E EP ROM is used to init ia l-

ize some of the PCI con figuration s pace l ocations and

most of the BCRs and CSR116. The EEPROM read

operation will always happen automatically after the

deassertion of the RST pin. In addition, the host can

start the read operation by setting the PREAD bit

(BCR19, bi t 14). Wh il e the EEP ROM read is on-go ing ,

the Am79C973/Am79C975 controllers will disconnect

any slave access where it is the target by asserting

STOP together with DEVSEL, while driving TRD Y hig h.

STOP will stay asserted until the end of the cycle.

Note t hat I/O and m emory slave acce sses wil l only be

disconnected if they are enabled by setting the IOEN or

MEMEN bi t in the P CI Comma nd re gister. Without th e

enable bit set, the cycles will not be claimed at all.

Since H_R ES ET c lears the IOEN an d ME MEN bits for

the automati c EEPROM read after H_RESET, the dis-

conne ct onl y applies to configu rati on cycl es.

A second situation where the Am79C973/Am79C975

controllers will generate a PCI disconnect/retry cycle is

when the h os t tr i es to acce ss a ny of the I/O res ou rces

right after having read the Reset register . Since the ac-

cess generates an internal reset pulse of about 1 ms in

length , all fur ther slave access es will be deferred until

the i nternal rese t opera tion is co mpleted . See Figu re 6.

Disconnect Of Burst Transfer

The Am79 C973/A m79C975 contr ollers do not su pport

burst access to the configuration space, the I/O re-

sources, or to the Expansion Bus. The host indicates a

burst transaction by keeping FRAME asserted during

the data phase. When the Am79C973/Am79C975 con-

trollers see FRAME and IRDY asserted in the clock

cycle before it wants to assert TRDY, it also asserts

STOP at the same time. The transfer of the first data

phase is still successful, since IRDY and TRDY are

both asserted. See Figure 7.

Figure 6. Disconnect Of Slave Cycl e When Busy

Figure 7. Disconnect Of Slave Burst Transfer - No

Host Wait States

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

CMD

PAR PAR PAR

DATA

ADDR

21510D-11

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

PAR PAR PAR

DATA

1st DATA

21510D-12

Am79C973/Am79C975 45

PRELIMINARY

If the host is not yet ready when the Am79C973/

Am79C975 controller asserts TRDY, the device will

wait f or the host to assert IRDY. When the host asserts

IRDY and FRAME is still asserted, the Am79C973/

Am79C975 c ontroller will fi nish the first data phas e by

deasserting T RDY one c lock la ter. At the same tim e, it

will assert STOP to signal a disconnect to the host.

STOP will stay asserted until the host removes

FRAME. See Figure 8.

Figure 8. Disconnect Of Slave Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am79C973/Am79C975 controller is not the

current bus master , it samples the AD[31:0], C/BE[3:0],

and the PAR lines during the address phase of any PCI

command f or a parity error. When it detects an address

pari ty error, the controller sets PERR (PCI Status reg-

ister, bit 15) to 1. When reporting of that error is en-

abled by setting SERREN (PCI Command r egister, bit

8) and PERREN (PCI Command register, bit 6) to 1, the

Am79C973/Am79C975 controller also drives the

SERR signal low for one clock cycle and sets SERR

(PCI Status register, bit 14) to 1. The assertion of

SERR follows the address phase by two clock cycles.

The Am79C973/Am79C975 controller will not assert

DEVSEL for a PCI transaction that has an address par-

ity error when PERREN and SERREN are set to 1. See

Figure 9.

Figure 9. Address Parity Error Response

During the data phase of an I/O write, memory-mapped

I/O write, or configuration write command that se lects

the Am79C973/Am79C975 controller as target, the de-

vice sampl es the A D[31 :0] a nd C/B E[3:0] lines for par-

ity on the clock edge, and data is transferred as

indicated by the assertion of IRDY and TRDY. PAR is

sampled in the following clo ck cycle. If a par ity er ror is

detected a nd repor ting of tha t error is en abled by set-

ting PERREN (PCI Command register, bit 6) to 1,

PERR i s asserted one clock later. T he par ity error will

alwa ys set PERR (PCI Status register, bit 15) to 1 even

when PERREN is cleared to 0. The Am79C973/

Am79C975 controller will finish a transaction that has a

data par i ty er r or in th e no r m al way by assert ing T RDY.

The co rr u pted dat a wi ll be written to the a ddr ess ed l o-

cation.

Figure 10 shows a transaction that suffered a parity

error at the time data was transferred (clock 7, IRDY

and TRDY are bo th asse r ted). P ERR is driven high at

the beginning of the data phase and then drops low due

to the parity error on clock 9, two clock cycles after the

data was transferred. After PERR is driven low, the

Am79C973/Am79C975 controller drives PERR high for

one clock cycle, since PERR is a sustained tri-state sig-

nal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 23456

PAR

PAR PAR

DATA

1st DATA

21510D-13

FRAME

CLK

SERR

C/BE

DEVSEL

1 2345

PAR PAR

ADDR 1st DATA

CMD

PAR

21510D-14

46 Am79C973/Am79C975

PRELIMINARY

Figure 10. Slave Cycle Data Parity Error Response

Master Bus Interface Unit

The master Bus Interf ace Unit (BIU) controls the acqui-

sition of th e PCI bus an d all accesse s to the initializ a-

tion block, descriptor rings, and the receive and

transmit buffer memory. Table 4 shows the usage of

PCI commands by the Am79C973/Am79C975 control-

ler in master mode.

Bus Acquisition

The Am79C973/Am79C975 microcode will determine

when a DMA transfer should be initiated. The first step

in any Am79C973/Am79C975 bus master transfer is to

acquire ownership of t he bus. This task is handled by

synchronous logic within the BIU. Bus ownership is re-

quested with the REQ signal and ownership is granted

by the arbiter through the GNT signal.

Figure 11 shows the Am79 C973 /Am 79C975 con tr oll er

bus acquisition. REQ is asserted and the arbiter re-

turns GNT while another bus master is transferring

data. The A m79C973/A m79C975 controller waits until

the b us i s idle (FRAME and IRDY deasserted) before it

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

1 2345678 109

DATA

PAR

PERR

21510D-15

Table 4. Master Commands

C[3:0] Command Use

0000 Interrupt

Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Not used

0011 I/O Write Not used

0100 Reserved

0101 Reserved

0110 Memory Read

Read of the initialization

bloc k and desc ripto r

rings

Read of the transmit

buffer in non-bur st mo de

0111 Memory Write Write to the descriptor

rings and to the receive

buffer

1000 Reserved

C[3:0] Command Use

1001 Reserved

1010 Configuration Read Not used

1011 Configuration Write Not used

1100 Memory Read

Multiple Read of the transmit

buffer in burst mo de

1101 Du al Address Cycle Not used

1110 Memory Read Line Read of the transmit

buffer in burst mo de

1111 Memory Write

Invalidate Not used

Table 4. Master Commands (Co ntinued)

Am79C973/Am79C975 47

PRELIMINARY

starts driving AD[31:0] and C/BE[3:0] on clock 5.

FRAME is asserted at clock 5 indicating a valid ad-

dress and command on AD[31:0] and C/BE[3:0].

Figure 11. Bus Acquisition

In burst mode, the deassertion of REQ depends on the

setting of EXTREQ (BCR18, bit 8). If EXTREQ is

cleared to 0, REQ is deasser ted at the same time as

FRAME is asserted. (The Am79C973/Am79C975 con-

troller never performs more than one burst transaction

within a single bus mastership period.) If EXTREQ is

set to 1, the Am79C973/Am79C975 controller does not

deasser t REQ until it star ts the l ast data ph ase of the

transaction. Once asserted, REQ remains active until

GNT has become active and independent of subse-

quent se tting o f STO P (CSR 0, bit 2) or SPND ( CSR5,

bit 0). The asser tion of H_RESET or S_RESET, how-

ever, will cause REQ to go inactive immediately.

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

Am79C973/Am79C975 controller uses non-burst as

well as burst cycles for read and write access to the

main memory.

Basic Non-Burst Read Transfer

By default, the Am79C973/Am79C975 controller uses

non-burst cycles in all bus master re ad operations. All

Am79C973/Am79C975 controller non-burst read ac-

cesses are of the PCI command type Memory Read

(type 6). Note that during a non-burst read operation,

all byte lanes will always be active. The Am79C973/

Am79C975 controller will internally discard unneeded

bytes.

The Am79C973/Am79C975 controller typically per-

forms more than one non-burst read transaction within

a single bus mastership period. FRAME is dropped be-

tween consecutive non-burst read cycles. REQ how-

ev er stays asserted until FRAME is asserted for the last

transaction. The Am79C973/Am79C975 controller

supports zero wait state read cycles. It asserts IRDY

immedia tely after the address phase and at the same

time starts sampling DEVSEL. Figure 12 shows two

non-burst read transactions. The first transaction has

zero wait states. In the second transaction, the target

extends the cycle by asserting TRDY one clock later.

Basic Burst Read Transfer

The Am79C973/Am79C975 controller suppor ts burst

mode for all bus master read operations. The burst

mode must be enabled by setting BREADE (BCR18, bit

6). To allow burst transfers in descriptor read opera-

tions, the Am79C973/Am79C975 controller must also

be programmed to use SWSTYLE 3 (BCR20, bits 7-0).

All burst read accesses to the initialization block and

descriptor ring are of the PCI command type Memor y

Read (type 6). Burst read accesses to the transmit

buffer typically are longer than two data phases. When

MEMCMD (BCR18, bit 9) is cleared to 0, all burst read

accesses to the transmit buffer are of the PCI com-

mand type Mem or y Read Line (ty pe 14). When MEM-

CMD (BCR18, bit 9) is set to1, all burst read accesses

to the transmit buffer are of the PCI command type

Memory Read Multiple (type 12). AD[1:0] will both be 0

during the address phase indicating a linear burst or-

der. Note that during a burst read operation, all byte

lanes will always be active. The Am79C973/

Am79C975 controller will internally discard unneeded

bytes.

The Am79C973/Am7 9C975 controller will always per-

form only a si ngle burst read tran saction pe r bus mas-

tership period, where transaction is defined as one

address phase and one or multiple data phases. The

Am79C973/Am79C975 controller supports zero wait

state read cycles. It asserts IRDY immedi ately afte r the

address phase and at the same time starts sampling

DEVSEL. FRAME is d easser ted when the n ext to l ast

data phase is completed.

Figure 13 shows a typical burst read access. The

Am79C973/Am79C975 controller arbitrates for the bus,

is granted access, reads three 32-bit words (DWord)

from the system memory, and then releases the bus. In

the example, the memory system extends the data

phase of each access by one wait state. The example

assumes that EXTR EQ ( BCR18, bit 8) is clea red t o 0,

therefore, REQ is deasserted in the same cycle as

FRAME is asse rted.

FRAME

CLK

IRDY

C/BE

REQ

GNT

1 2345

CMD

ADDR

21510D-16

48 Am79C973/Am79C975

PRELIMINARY

Figure 12. Non-Burst Read Transfer

Figure 13. Bu rst Read Transfer (EXTREQ = 0, MEMCMD = 0)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0110

PAR

1 2345678 109 11

DATA

ADDR

DATA

PAR PAR PAR

0000 0110 0000

21510D-17

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

00001110

PAR

1 2345678 109 11

DATA

PAR PAR PAR

21510D-18

Am79C973/Am79C975 49

PRELIMINARY

Basic Non-Burst Write Transfer

By default, the Am79C973/Am79C975 controller uses

non-burst cyc les in all bus ma ster writ e op erations. All

Am79C973/Am79C975 controller non-burst write ac-

cesses are of the PCI command type Memory Write

(type 7). The byte enable signals indicate the byte

lanes that have v alid data. The Am79C973/Am79C975

controller typically performs more than one non-burst

write transaction within a single bus mastership period.

FRAME is dropped between consecutive non-burst

write cycles. REQ, however, stays asserted until

FRAME is asserted for the last transaction. The

Am79C973/Am79C975 suppor ts zero wait state write

cycles except w ith descript or write transfers. (See the

section Descriptor DMA Transfers for the only excep-

tion.) It asserts IRDY immediately after the address

phase.

Figure 14 sh ows two non-burst wr i te transac ti ons. The

first transacti on has two wait stat es. The target i nserts

one w ait stat e by as serting DEV SEL one clock late and

another wait state by also asser ting TRDY one clock

late. The second transaction shows a zero wait state

write cycle. The target asser ts DEVSEL and TRDY in

the same cycl e as the Am79C973/A m79C975 cont rol-

ler asserts IRDY.

Basic Burst Write Transfer

The Am79C973/Am79C975 controller suppor ts burst

mode for all bus master write operations. The burst

mode must be enabled by setting BWRITE (BCR18, bit

5). To allow burst transfers in descriptor write opera-

tions, the Am79C973/Am79C975 controller must also

be programmed to use SWSTYLE 3 (BCR20, bits 7-0).

All Am79 C973/Am79C975 controller burst wr ite trans-

fers are of the PCI command type Memory Write (type

7). AD[1: 0] wi ll bo th b e 0 during the add re ss phase in-

dicating a linear burst order. The byte enable signals in-

dicate the byte lanes that have valid data.

The Am79C973/Am7 9C975 controller will always per-

form a single burst write transaction per bus mastership

period, where transaction is defined as one address

phase and one or multiple data phases. The

Am79C973/Am79C975 controller supports zero wait

state write cycles except with the case of descriptor

write transfers. (See the section Descriptor DMA Trans-

fers for the only exception.) The device asserts IRDY

immedia tely after the address phase and at the same

time starts sampling DEVSEL. FRAME is deasser ted

when the next to last data phase is completed.

Figure 14. Non-Burst Write Transfer

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 2345678 109

DATA

ADDR

DATA

PAR PAR PAR

BE 0111 BE

50 Am79C973/Am79C975

PRELIMINARY

Figure 15 shows a typical burst write access. The

Am79C973/Am79C975 controller arbitrates for the bus,

is granted access, and writes four 32-bit words

(D W ords) to the system memory and then releases the

bus. In this example, the memor y system extends the

data phase of the first access by one wait state. The fol-

lowing three data phases take one clock cycle each,

which is determined by the timing of TRDY. The exam-

ple assume s that EXTREQ (BCR18, bit 8) is set to 1 ,

therefore, REQ is not deasser ted until the next to last

data phase is finished.

Target Initiated Termination

When the Am79C973/Am79C975 controller is a bus

master, the cycles it produces on the PCI bus may be

ter mi na ted by the targe t in one of three different ways:

disconnect with data transfer, discon nect without data

transfer, and target abort.

Disconnect With Data Transfer

Figure 16 shows a disconnection in which one last data

transfer occurs after the target asser ted STOP. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C973/

Am79C975 controller terminates the current transfer

with the deassertion of FRAME on clock 5 and of IRDY

one clock later. It finally releases the bus on clock 7.

The Am79C973/Am79C975 controller will again re-

quest the bus after two clock cycles, if it wants to trans-

fer more data. The starting address of the new transfer

will be the address of the next non-transferred data.

Figure 15. Burst Write Transfer (EXTREQ = 1)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

12345678

ADDR DATA DATA DATA

0111

PAR PAR PAR PAR PAR

DATA

PAR

DEVSEL is sampled

21510D-20

Am79C973/Am79C975 51

PRELIMINARY

Figure 16. Disconnect With Data Transfer

Disconnect Without Data Transfer

Figure 17 shows a ta rget disc onnect se quence du rin g

which no data is transferred. STOP is asserted on clock

4 without TRDY being asserted at the s ame t ime. The

Am79C973/Am79C975 controller terminates the ac-

cess with the dea ss ertion of FRAM E on clock 5 and of

IRDY one clock cycle later . It finally releases the bus on

clock 7. The Am79C973/Am79C975 controller will

again request the bus after two clock cycles to retry the

last transfer. The star ting address of the new transfer

will be the address of the last non-transferred data.

Target Abort

Figure 18 shows a target abor t sequ ence. The target

asserts DEVSEL for one clock. It then deasserts

DEVSEL and asser ts STOP on clock 4. A target can

use the target abo r t sequence to indicate that it can-

not service the data transfer and that it does not want

the transaction to be retried. Additionally, the

Am79C973/Am79C975 controller cannot make any

assumption about the success of the previous data

transfers in the current transaction. The Am79C973/

Am79C975 controller terminates the current transfer

with the deassertion of FRAME on clock 5 and of

IRDY one clock cycle later. It finally releases the bus

on clock 6.

Since data integrity is not guaranteed, the Am79C973/

Am79C975 controller cannot recover from a target

abort event. The Am 79C973/A m79C97 5 control ler will

reset all CSR lo cations to their STOP_RESE T values.

The BCR and PCI configuration registers will not be

cleared. Any on-going network transmission is termi-

nated in an orderly sequence. If less than 512 bits have

been transmitted onto the network, the transmission

will be terminated immediately, generating a runt

packet. If 512 bi ts or more have been transm itted, the

message will have the current FCS inverted and ap-

pended at the next byte boundary to guarantee an FCS

error is detected at the receiving station.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDRi

00000111

PAR

0111

23456789 11

PAR

DATA

STOP

ADDRi+8

DATA

21510D-21

52 Am79C973/Am79C975

PRELIMINARY

Figure 17. Disconnect Without Data Transfer

RTABORT (PCI Status register, bit 12) will be set to

indicate t hat the Am7 9C97 3/A m79 C 97 5 con t roll er has

received a target abort. In addition, SINT (CSR5, bit 11)

will be set to 1. When SINT is set, INTA is asser ted if

the enable bit SINTE (CSR5, bit 10) is set to 1. This

mechanism can be used to inform the driver of the sys-

tem error. The host can read the PCI Status register to

determine the exact cause of the interrupt.

Master Initiated Termination

There are three scen arios besides nor mal comple tion

of a transaction where the Am79C973/Am79C975 con-

troller w ill ter minate the cycles it produces on the PCI

bus.

Preemption During Non-Burst Transaction

When the Am79C973/Am79C975 controller performs

multiple non-burst transactions, it keeps REQ asserted

until the assertion of FRAME for the last transaction.

When GNT is removed, the Am79C973/Am79C975

controller will finish the current transaction and then re-

lease the bus. If it is not the las t transacti on, REQ will

remain asserted to regain bus ownership as soon as

possible. See Figure 19.

Preemption During Burst Transaction

When the Am79C973/Am79C975 controller operates

in burst mode, it only performs a single transaction per

bus mastership period, where transaction is defined as

one address phase and one or multiple data phases.

The central arbiter can remov e GNT at any ti me du ring

the transaction. The Am79C973/Am79C975 controller

will ignore the deassertion of GNT and continue with

data transfers, as long as the PCI Latency Timer is not

expired. When the Latency Timer is 0 and GNT is deas-

serted, the Am79C973/Am79C975 controller will finish

the current data phase, deassert FRAME, finish the

last data phase, and release the bus. If EXTREQ

(BCR18, bit 8) is cleared to 0, it will immediately assert

REQ to regain bus ownership as soon as possible. If

EXTREQ is set to 1, REQ will stay asserted.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

STOP

ADDRi

00000111

PAR

0111

23456789 11

ADDRi

DATA

PAR

21510D-22

Am79C973/Am79C975 53

PRELIMINARY

Figure 18. Target Abort

When the preemption occurs after the counter has

counted down to 0, the Am79C973/Am79C975 control-

ler will finish the current data phase, deassert FRAME,

finish the last data phase, and release the bus. Note

that it is important for the host to program the PCI La-

tency Timer according to the bus bandwidth require-

ment of the Am79C973/Am79C975 controller. The host

can determine this bus bandwidth requirement by read-

ing the PCI MAX_LAT and MIN_GNT registers.

Figure 20 assumes that the PCI Latency Timer has

counted down to 0 on clock 7.

Master Abort

The Am79C973/Am79C975 controller will terminate its

cycle with a Master Abor t sequence if DEVSEL is not

asserted within 4 clocks after FRAME is asserted.

Master Abort is treated as a fatal error by the

Am79C973/Am79C975 controller. The Am79C973/

Am79C975 controller will reset all CSR locations to

their STOP_RESET values. Th e BCR and PCI c onfig-

uration regi sters wil l not be clea red. Any on-goin g net-

work transmission is terminated in an orderly

sequenc e. If less than 512 bits have been transmitted

onto the network, the transmission will be terminated

immediately, generating a runt packet. If 512 bits or

more have been transmitted, the message will hav e the

current FCS inverted and appended at the next byte

boundary to guarantee an FCS error is detected at the

receiving station.

RMABORT (in the PCI Status register, bit 13) will be set

to indicate that the Am79C973/Am79C975 controller

has terminated its transaction with a master abor t. In

addition, SINT (CSR5, bit 11) will be set to 1. When

SINT is set, INTA is asser ted if the enable bit SINTE

(CSR5, bit 10) is set to 1. This mechanism can be used

to inform the driver of the system error. The host can

read the PCI Status register to determine the exact

cause of the interrupt. See Figure 21.

Parity Error Response

During every data phase of a DMA read operation,

when the target indicates that the data is valid by as-

serting TRDY, the Am79C973/Am79C975 controller

samples the AD[31:0], C/BE[3:0] and the PAR lines for

a data par ity error. When it detects a data par ity error,

the cont ro ller s et PE RR (P CI Sta tus regi s ter, bit 15) to

1. When reporting of that error is enabled by setting

PERREN (PCI Command register, bit 6) to 1, the

Am79C973/Am79C975 controller also drives the

PERR signal low and sets DATAPERR (PCI Status reg-

ister , bit 8) to 1. The assertion of PERR follows the cor-

rupt ed data /byte en ables by two c lo ck cyc les a nd PAR

by one clock cycle.

Figure 22 shows a transaction that has a parity error in

the data p hase. The Am79 C973/A m79C975 con troller

asserts PERR on cloc k 8, two clock cycles after data is

valid. The data on clock 5 is not checked for parity,

since on a read access PAR is only required to be valid

one clock after the target has asserted TRDY. The

Am79C973/Am79C975 controller then drives PERR

high for one clock cycle, since PERR is a sustained tri-

state signa l.

During e v ery data phase of a DMA write operation, the

Am79C973/Am79C975 controller checks the PERR

input t o see if the targe t repo rts a par ity error. When i t

sees the PERR input asserted, the controller sets

PERR (PCI Status register, bit 15) to 1. When PER-

REN (PCI Command register, bit 6) is set to 1, the

Am79C973/Am79C975 controller also sets

DATAPERR (PCI Status register, bit 8) to 1.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

234567

ADDR

0000

0111

PAR PAR

DATA

STOP

21510D-23

54 Am79C973/Am79C975

PRELIMINARY

Figure 19. Preemption During Non-Bu rst Trans act ion

Figure 20. Preemption During Burst Transaction

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

BE0111

PAR PAR

DEVSEL is sampled

PAR

DATA

ADDR

21510D-24

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

BE0111

PAR

1 23456789

DATA

PAR

REQ

DATA

PAR PAR PAR PAR

GNT

21510D-25

Am79C973/Am79C975 55

PRELIMINARY

Figure 21. Master Abort

Figure 22. Master Cycle Data Parity Error Response

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

REQ

GNT

0000

21510D-26

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

PERR

21510D-27

56 Am79C973/Am79C975

PRELIMINARY

Whenever the Am79C973/A m79C975 c ontroller i s the

current b us master and a data parity error occurs, SINT

(CSR5, bit 11) will be set to 1. When SINT is set, INTA

is asserted if the enable bit SINTE (CSR5, bit 10) is set

to 1. This mechan ism ca n be used to in form the dr iver

of the sy stem error. The ho st can r ead the PCI Status

The setting of SINT due to a data parity error is not

dependent on the set ting of PE RREN (PCI Com mand

registe r, bit 6).

By default, a data par ity er ror does not affect the stat e

of the MAC engine. The Am79C973/Am79C975 con-

troller treats the data in all bus master transfers that have

a parity error as if nothing has happened. All network

activity continues.

Advanced Parity Error Handling

For all DMA cycles, the Am79C973/Am79C975 control-

ler provides a second, more advanced level of parity

error handling. This mode is enabled by setting APER-

REN (BCR20, bit 10) to 1. When APERREN is set to 1,

the BPE bits (RMD1 and TMD1, bit 23) are used to

indicate parity error in data transf ers to the receive and

transmit buffers. Note that since the advanced parity

error handling uses an additional bit in the descriptor,

SWSTYLE (BCR20, bits 7-0) must be set to 2 or 3 to

program the Am79C973/Am79C975 controller to use

32- bi t so f t w a re st ruct ur es. The Am 79 C9 73 / Am 79C 9 75

controller will react in the following way when a data

parity error occurs:

■Initialization block read: STOP (CSR0, bit 2) is set to

1 and causes a STOP_RESET of t he device.

■Descriptor ring read: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bi t 2) is set to 1 to cause a STOP_RE SET

of the device.

■Descriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bi t 2) is set to 1 to cause a STOP_RE SET

of the device.

■Transmit buffer read: BPE (TMD1, bit 23) is set in

the current transmit descriptor. Any on-going net-

work transmission is terminated in an orderly se-

quence.

■Receive buffer write: BPE (RMD1, bit 23) is set in

the last receive descriptor associated with the frame.

Terminating on-going network transmission in an or-

derly sequence means that if less than 512 bits have

been transmitted onto the network, the transmission

will be terminated immediately, generating a runt

packet.

If 512 bits or more have been transmitted, the message

will have the current FCS inverted and appended at the

next byte boundary to guarantee an FCS error is de-

tected at the receiving station.

APERREN does not affect the reporting of address

parity errors or data parity errors that occur when the

Am79C973/Am79C975 controller is the target of the

transfer.

Initialization Block DMA Transfers

During execution of the Am79C973/Am79C975 con-

troller bus master initialization procedure, the

Am79C973/Am79C975 microcode will repeatedly re-

quest DMA transfers from the BIU. During each of

these initialization block DMA transfers, the BIU will

perform two data transfer cycles reading one DWord

per transfer and then it will relinquish the bus. When

SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the initialization

block is organi zed as 32-bi t so ftware st ruct ures ), there

are sev en DW ords to transfer during the bus master ini-

tialization procedure, so four bus master-ship periods

are needed in order to complete the initialization se-

quence. Note that the last DWord transfer of the last

bus mastership period of the initialization sequence ac-

cesses an unneeded location. Data from this transf er is

discarded internally. When SSIZE32 is cleared to 0

(i.e., the ini tialization block is or ganized as 16-bi t soft-

ware structures), then three bus mastership periods

are needed to complete the initialization sequence.

The Am79C973/Am79C975 supports two transfer

modes for reading the initialization block: non-burst and

burst mode, with burst mode being the preferred mode

when the Am 79C973/ Am79C975 contro ller is used in a

PCI bus application. See Figure 23 and Figure 24.

When BREADE is cleared to 0 (BCR18, bit 6), all initial-

ization block read transfers will be executed in non-

burst mode. There is a new address phase for every

data phase. FRAME will be dropped between the two

transfers. The two phases within a bus mastership pe-

riod will have addresses of ascending contiguous or-

der.

When BR EADE is se t to 1 (BCR18, bit 6) , all i niti al iza-

tion block read transfers will be executed in burst mode.

AD[1:0] will be 0 during the address phase indicating a

linear burst order.

Am79C973/Am79C975 57

PRELIMINARY

Figure 23. Initialization Block Read In Non-Burst Mode

Figure 24. Initialization Block Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

IADDi

00000110

PAR PAR

DATA DATA

IADDi+4

0000

0110

PAR PAR

1 2345678 109

21510D-28

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000110

PAR PAR PAR PAR

DEVSEL is sampled

DATA DATA

IADDi

21510D-29

58 Am79C973/Am79C975

PRELIMINARY

Descriptor DMA Transfers

Am79C973/Am79C975 microcode will determine when

a descriptor access is required. A descriptor DMA read

will consist of two data transfers. A descriptor DMA

writ e will co nsist of one or two data transfers. The de-

scriptor DMA transfers within a single bus mastership

peri od will always be of the same type ( either all rea d

or all write).

During descr iptor read accesses, the byte enable sig-

nals will indicate that all byte lanes are active. Should

some of the bytes not be needed, then the Am79C973/

Am79C975 controller will internally discard the extra-

neous information that was gathered during such a

read.

The settings of SWSTYLE (BCR20, bits 7-0) and

BREADE (BCR18, bit 6) affect the wa y the Am79C973/

Am79C975 controller performs descr iptor read opera-

tions.

When SWSTYLE is set to 0 or 2, all descriptor read op-

erations are per forme d i n no n- burst mode. T he se t tin g

of BREADE has no effect in this configuration. See Fig-

ure 25.

When SW STY LE is s et to 3 , the desc riptor en trie s a r e

ordered to allow burst transfers. The Am79C973/

Am79C975 controller will perform all descriptor read

operations in burst mode, if BREADE is set to 1. See

Figure 26.

Table 5 shows the descriptor read sequence.

During descriptor write accesses, only the byte lanes

which need to be written are enab led.

If buffer chaining is used, a ccesses to the descriptors

of all intermediate buffers consist of only one data

transfer to return ownership of the buff er to the system.

When SWST YLE (BCR2 0, bits 7- 0) is cle ared to 0 (i .e.,

the desc r iptor en tr ies a re organized as 16-bi t s oft ware

structures), the descriptor access will write a single

byte. When SW STYLE (BCR 20, bits 7-0) is set to 2 or

3 (i.e., the descriptor entries are organized as 32-bit

software str uctures), the descr iptor acces s will write a

single word. On all single buffer transmit or receive de-

scriptors, as well as on the last buff er in chain, writes to

the descriptor consist of two data transfers.

The first data transfer writes a DW ord containing status

information. The second data transfer writes a byte

(SWSTYLE cleared to 0), or otherwise a word contain-

ing additional status and the ownership bit (i.e.,

MD1[31]).

The settings of SWSTYLE (BCR20, bits 7-0) and

BWRITE (BCR18, bit 5) aff ect the wa y the Am79C973/

Am79C9 75 controlle r perfor ms descr iptor wr ite opera-

tions.

When SWSTYLE is set to 0 or 2, all descriptor write op-

erations a re performed i n n on- burst mod e. The se ttin g

of BWRITE has no effect in this configuration.

When SWST Y LE is s et to 3 , the descriptor en trie s are

ordered to allow burst transfers. The Am79C973/

Am79C975 controller will perform all descriptor write

operations in burst mode, if BWRITE is set to 1. See

Table 6 for the descriptor write sequence.

A wri te transaction to the descripto r ring entri es is the

only cas e wher e th e Am7 9C973/Am79 C97 5 contr oller

inse rts a wait s tate when being the bus master. Every

data phase in non-burst and burst mode is e xtended b y

one clock cycle, during which IRDY is deasserted.

Note that Figure 26 assumes that the Am79C973/

Am79C975 controller is programmed to use 32-bit soft-

ware stru ct ur es (SWS TYLE = 2 or 3). The byte enable

signals for the second data t rans fer would be 011 1b, if

the device was programmed to use 16-bit software

structures (SWSTYLE = 0).

Table 5. Descriptor Read Sequence

SWSTYLE

BCR20[7:0] BREADE

BCR18[6] AD Bus Sequence

Address = XXXX XX00h

Turn around cycle

Data = MD1[31:24],

MD0[23:0]

Idle

Address = XXXX XX04h

Turn around cycle

Data = MD2[15:0], MD1[15:0]

Address = XXXX XX04h

Turn around cycle

Data = MD1[31:0]

Idle

Address = XXXX XX00h

Turn around cycle

Data = MD0[31:0]

Address = XXXX XX04h

Turn around cycle

Data = MD1[31:0]

Idle

Address = XXXX XX08h

Turn around cycle

Data = MD0[31:0]

Address = XXXX XX04h

Turn around cycle

Data = MD1[31:0]

Data = MD0[31:0]

Am79C973/Am79C975 59

PRELIMINARY

Figure 25. Descriptor Ring Read In Non-Burst Mode

Figure 26. Descriptor Ring Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD1

00000110

PAR PAR

DATA DATA

MD0

00000110

PAR PAR

1 2345678 109

21510D-30

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

MD1

00000110

PAR PAR PAR

DATA DATA

PAR

DEVSEL is sampled B21510D-31

60 Am79C973/Am79C975

PRELIMINARY

Table 6. Descriptor Write Sequence

FIFO DMA Transfers

Am79C973/Am79C975 microcode will determine when

a FIFO DMA transfer is required. This transfer mode

will be used for transfers of data to and from the

Am79C973/Am79C975 FIFOs. Once the Am79C973/

Am79C975 BIU has been granted bus mastership, it

will perform a ser ie s of cons ec uti ve transfer cycles be-

fore reli nqu is hi ng t he bus. All trans fers within the mas -

ter cycle will be either read or write cycles, and all

transfers will be to contiguous, ascending addresses.

Both non-burst and burst cycles are used, with burst

mode being the preferred mode when the device is

used in a PCI bus application.

Non-Burst FIFO DM A Transfers

In the default mode, the Am79C973/Am79C975 con-

troller uses non-burst transfers to read and write data

when accessing the FIFOs. Each non-burst transfer will

be performed sequentially with the issue of an address

and the trans fer of the correspond ing da ta with a ppro-

pri ate output signals to ind icate selection of the active

data bytes duri ng the transfer.

FRAME wil l b e d eas s erted after every address ph ase.

Several factors will a ffect the le ngth of the bus mas ter-

ship period. The possibilities are as follows:

Bus cycles will continue until the transmit FIFO is filled

to its high threshold (read transfers) or the receive FIFO

is emptied to its low threshold (write transfers). The

ex act number of total transfer cycles in the bus master-

ship period is dependent on all of the following vari-

ables: the settings of the FIFO watermarks, the

conditi ons of the FI FOs, the laten cy of the sy stem bus

to the A m79 C97 3/A m79 C 975 controller ’s bus requ est,

the speed of bus operation and bus preemption ev ents.

The TRDY response time of the memory device will

also affect the number of transfers, since th e spee d of

the accesses will affect the state of the FIFO. During

accesses, the FIFO may be filling or emptying on the

network end. For example, on a receive operation, a

slower TRDY response wil l allow ad dit ion al d ata to ac-

cumulate inside of the FIFO. If the accesses are slow

enough , a com ple te DWor d may become available be-

fore the end of the bus mastership period and, thereby,

increase the number of transfers in that period. The

general rule is that the longer the Bus Grant latency,

the slower the bus transfer operations; the slower the

clock speed, the hi gher the trans mit water mar k; or th e

higher th e re ce ive water m ar k, the longer the bus mas-

tership period will be.

Note: The PCI La tency Time r is not s ignific ant dur ing

non-burst transfers.

SWSTYLE

BCR20[7:0] BWRITE

BCR18[5] AD Bus Sequence

Address = XXXX XX04h

Data = MD2[15:0],

MD1[15:0]

Idle

Address = XXXX XX00h

Data = MD1[31:24]

Address = XXXX XX08h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Data = MD1[31:16]

Am79C973/Am79C975 61

PRELIMINARY

Figure 27. Descriptor Ring Write In Non-Burs t Mode

Figure 28. Descriptor Ring Write In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD2

00000111

PAR

MD1

00110111

PAR

1 2345678 109

DATA

PAR

DATA

21510D-32

GNT

REQ

DEVSEL

TRDY

PAR

C/BE

FRAME

CLK 35

PAR

IRDY

DEVSEL is sampled

DATA

1 2 4 6 7 8

0110 0000 0011

MD2

PAR

DATA

PAR

21510D-33

62 Am79C973/Am79C975

PRELIMINARY

Burst FIFO DMA Transfers

Bursting is only performed by the Am79C973/

Am79C975 controller if the BREADE and/or BWRITE

bits of BCR18 are set. These bits individually enable/

disable the ability of the Am79C973/Am79C975 con-

troller to perform burst accesses during master read

operations and master write operations, respectively.

A burst transaction will start with an address phase, f ol-

lowed by one or more data phases. AD[1:0] will always

be 0 during the address phase indicating a linear burst

order.

During FIFO DMA read operations, all byte lanes will

always be active. The Am79C973/Am79C975 cont rol-

ler will inte r nal ly disc ard unused bytes. Duri ng the firs t

and the last data phases of a FIFO DMA burst write op-

eration, one or more of the byte enable signals ma y be

inactive. All other data phases will always write a com-

plete DWord.

Figure 29 shows the beginning of a FIFO DMA write

with the beginning of the buffer not aligned to a DWord

boundary. The Am79C973/Am79C975 controller starts

off by writing only three bytes during the first data

phase. This operation aligns the address for all other

data transfers to a 32-bit boundary so that the

Am79C973/Am79C975 controller can continue burst-

ing full DWords.

If a receive buffer does not end on a DWord boundary,

the Am79C973/Am79C975 controller will perform a

non-DWord wr ite o n the l ast transfer to the buffer. Fig-

ure 30 shows the final three FIFO DMA transfers to a

receive buffer. Since there were only nine bytes of

space left in the receive buffer, the Am79C973/

Am79C975 controller bursts three data phases. The

first two data phases write a full DWord, the last one

only writes a single byte.

Note that th e Am79C973/Am79C97 5 controller wi ll al-

way s perform a DWord transfer as lon g as it owns the

buffer space, even when there are less than four bytes

to write. F or example, if there is only one byte left for the

current receive frame, the Am79C973/Am79C975 con-

troller will write a full D Word, containing the last byte of

the receive frame in the least significant byte position

(BSWP is cleared to 0, CSR3, bit 2). The content of the

other three bytes is undefined. The message byte

count in the receive descriptor always reflects the e xact

length of the received frame.

Figure 29. FIFO Burst Write At Start Of Unaligned

Buffer

The Am79C973/Am79C975 controller will continue

transferring FIFO data until the transmit FIFO is filled to

its high threshold (read transfers) or the receive FIFO

is emptied to its low threshold (write transfers), or the

Am79C973/Am79C975 controller is preempted, and

the PCI Latency Timer is expired. The host should use

the values in the PCI MIN_GNT and MAX_LAT regis-

ters to determine the value for the PCI Latency Timer.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 23456

00000111

PAR PAR PAR

DEVSEL is sampled

0001

PAR

DATA DATA

DATA

ADD

21510D-34

Am79C973/Am79C975 63

PRELIMINARY

Figure 30. FIFO Burst Write At End Of Unaligned

Buffer

The exact number of total transfer cycles in the bus

mastership per iod is dependent on all of the following

variables: the settings of the FIFO watermarks, the

conditio ns of the FIFOs, the l atency of th e sys tem bus

to the A m79 C973 /Am79C975 c ont ro ll er’s bus requ est,

and the speed of bus operation. The TRDY response

time of the memor y device wi ll also a ffect the numb er

of transfers, since the speed of the accesses will affect

the state of the FIF O. Dur ing a ccesses, th e FIF O may

be filling or emptying on the network end. For e xample,

on a receive operation, a slower TRDY response will

allow additional data to accumulate inside of the FIFO.

If the accesses are slow enough, a complete DWord

may become available before the end of the bus mas-

tership period and, thereby, increase the number of

transfers in that period. The general rule is that the

longer the Bus Grant latency, the slower the bus trans-

fer operations; the slower the clock speed, the higher

the transmit watermark; or the lower the receive water-

mark, the longer the total burst length will be.

When a FIFO DMA burst operation is preempted, the

Am79C973/Am79C975 controller will not relinquish

bus ownership until the PCI Latency Timer expires.

Buffer Management Unit

The Buffer Management Unit (BMU) is a microcoded

state machine which implements th e initialization pro-

cedure and manage s the descr iptors and buffers. The

buffer management unit operates at half the speed of

the CLK input.

Initialization

Am79C 973/ Am 79C9 75 i nit ial iz ation inc lu des the read-

ing of the initialization block in memory to obtain the op-

erating parameters. The initialization block can be

organized i n two ways. When SSI ZE32 (BCR20, bi t 8)

is at its d efault value of 0, all i nit ial iz ati on block ent r ies

are logically 16-bits wide to be backwards compatible

with the Am79C90 C-LANCE and Am79C96x PCnet-

ISA family. When SSIZE32 (BCR20, bit 8) is set to 1, all

initialization block entries are logically 32-bits wide.

Note that the Am79C973/Am79C975 controller always

performs 32-bit bus transfers to read the initialization

block entries. The initialization block is read when the

INIT bit in CSR0 i s set. The INIT bi t should be s et be-

fore or concurrent with the STRT bit to insure correct

operation. Onc e the initializ ation block has been c om-

pletely read in and internal registers have been up-

dated, IDON will be set in CSR0, generating an

interrupt (if IENA is set).

The Am79C973/Am79C975 controller obtains the start

address of the initialization block from the contents of

CSR1 (least significant 16 bits of address) and CSR2

(most significant 16 bits of address). The host must

writ e CSR1 and CSR2 before setting the INIT bit. The

initialization block contains the user defined conditions

for Am79C973/Am79C975 operation, together with the

base addr esses and le ngth inform ation o f the trans mit

and receive descriptor rings.

There is an alternate method to initialize the

Am79C973/Am79C975 controller. Instead of initializa-

tion vi a the init ialization block in memor y, data can be

written directly into the appropriate registers. Either

method or a combination of the two may be used at the

discretion of the programmer . Please refer to Appendix

A, Alternative Method for Initialization for details on this

alternate method.

Re-Initialization

The transmitter and receiver sections of the

Am79C973/Am79C975 controller can be turned on via

the initialization block (DTX, DRX, CSR15, bits 1-0).

The states of the transmitter and receiver are moni-

tored by the host through CSR0 (RXON, TXON bits).

The Am79C973/Am79C975 controller should be re-ini-

tialized if the transmitter and/or the receiver were not

turned on during the original initialization, and it was

subsequently required to activate them or if either sec-

tion was shut off due to the detection of an error condi-

tion (MERR, UFLO, TX BUFF error).

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000111

PAR PAR PAR PAR

DEVSEL is sampled

1110

PAR

DATA DATA

DATA

ADD

21510D-35

64 Am79C973/Am79C975

PRELIMINARY

Re-initialization may be done via the initialization bloc k

or by setting the STOP bit in CSR0, followed by writing

to CSR15, and then setting the START bit in CSR0.

Note that thi s form of r e sta rt will not perfor m th e s am e

in the Am79C973/Am79C975 controller as in the C-

LANCE device. In particular, upon restart, the

Am79C973/Am79C975 controller reloads the transmit

and receive descriptor pointers with their respective

base addresses. This means that the software must

clear the descriptor OWN bits and reset its descriptor

ring pointers before restarting the Am79C973/

Am79C975 controller. The reload of descriptor base

addresses is performed in the C-LANCE device only

after initialization, so that a restart of the C-LANCE

without initialization leaves the C-LANCE pointing at

the same descriptor locations as before the restart.

Suspend

The Am79C973/Am79C975 controller offers two sus-

pend modes that allow easy updatin g of the CSR reg-

isters without going through a full re-initialization of the

device. The suspend modes also allow stopping the

device with orderly termination of all network activity.

The host requ ests the Am79 C973/Am79 C975 control-

ler to enter the suspend mode by setting SPND (CSR5,

bit 0) to 1. The host must poll SPND until it reads back

1 to determine that the Am79C973/Am79C975 control-

ler has entered the suspend mode. When the host sets

SPND to 1, the procedure taken by the Am79C973/

Am79C975 controller to enter the suspend mode de-

pends on the setting of the fast suspend enable bit

(FASTSPND, CSR7, bit 15).

When a fa st suspen d is reques ted (FAST SPND is se t

to 1), the Am79C973/Am79C975 controller performs a

quick entry into the suspend mode. At the time the

SPND bit is set, the Am79C973/Am79C975 controller

will continue the DMA process of any transmit and/or

receive packets that have already be gun DMA activ ity

until the networ k activ ity has be en compl eted. In add i-

tion, any transm it packet that had started transmis s io n

will be fully transmitted and any receive pack et that had

begun reception will be fully received. Howe ver, no ad-

ditional packets will be transmitt ed or recei ve d and no

additional transmit or receive DMA activity will begin

after network activity has ceased. Hence, the

Am79C973/Am79C975 controller may enter the sus-

pend mod e wit h transmi t and /or receive packets still i n

the FIFOs or the SRAM. This offers a wo rst case sus-

pend time of a max imum l eng th packet ove r th e poss i-

bility of com pletel y emptying the SRA M. Care must be

exercised in this mode, because the entire memory

subsystem of the Am79C973/Am79C975 controller is

susp end ed. A ny ch ang es to ei the r t he de sc riptor rings

or the SRAM can cause the Am79C973/Am79C975

controller to start up in an unknown condition and could

cause data corruption.

When FASTSPNDE is 0 and the SPND bit is set, the

Am79C973/Am79C975 controller may take longer be-

fore entering the suspend mode. At the time the SPND

bit is set, the Am79C973/Am79C975 controller will

compl ete the D MA proces s of a tr ansmit pac k et if it h ad

already begun and the Am79C973/Am79C975 control-

ler wi ll comple tely rec eive a receive packet if it had al-

ready begun. The Am79C973/Am79C975 controller

will not receive any new pac kets after the completion of

the curr ent recept ion. Addit ionally, all tra nsmit packets

stored in the transmit FIFOs and the transmit buffer

area in the SRAM (if one is present) will be transmitted,

and all receive pack ets stored in the receive FIFOs and

the receive b uffer area in the SRAM (if selected) will be

transferred into system memory. Since the FIFO and

the SRAM contents are flushed, it may take much

longer bef ore the Am79C973/Am79C975 controller en-

ters the suspend mode. The amount of time that it

takes depends on many factors including the size of the

SRAM, bus latency, and network traffic level.

Upon completion of the described operations, the

Am79C973/Am79C975 controller sets the read-version

of SPND to 1 and enters the suspend mode. In sus-

pend mode, all of the CSR and B CR registers ar e ac-

cessible. As long as the Am79C973/Am79C975

controller is not reset while in suspend mode (by

H_RESET, S_RESET, or by setting the STOP bit), no

re-initialization of the device is required after the device

comes o ut of suspe nd mod e. When SPND is set to 0,

the Am79C973/Am79C975 controller will leave the

suspend mode and will continue at the transmit and re-

ceive descriptor ring locations where it was when it en-

tered the suspend mode.

See th e section on Magic Packet™ tech nology fo r de-

tails on how that affects suspension of the Am79C973/

Am79C 975 co ntr ol ler.

Buffer Management

Buffer management is accomplished through message

descriptor entries organized as ring structures in mem-

ory . There are two descriptor rings, one for transmit and

one for receive. Each descriptor describes a single

buff er . A frame may occup y one or more buffers. If mul-

tiple buff ers are used, this is referred to as buff er chain-

ing.

Descriptor Rings

Each descriptor ring must occupy a contiguous area of

memory. During initialization, the user-defined base

address for the transmit and receive descriptor rings,

as well as the number of entries contained in the de-

scri ptor rings a re set u p. The programmin g o f the s oft-

ware style (SWSTYLE, BCR20, bits 7-0) affects the

wa y the descriptor rings and their entries are arranged.

When SWSTYLE is at its default value of 0, the de-

scriptor rings are backwards compatible with the

Am79C90 C-LANCE and the Am79C96x PCnet-ISA

Am79C973/Am79C975 65

PRELIMINARY

family. The descriptor ring base addresses must be

aligned to an 8-byte boundar y and a maximum o f 128

ring entries is allowed when the ring length is set

through th e TLEN and RLE N fields of the i nitializa tion

block. Each ring entry contains a subset of the three

32-bit transmit or receive message descriptors (TMD,

RMD) that are organized as four 16-bit structures

(SSIZE32 (BCR20, bit 8) is set to 0). Note that even

though the Am79C973/Am79C975 controller treats the

descriptor entries as 16-bit structures, it will always

perform 32-bit bus transfers to access the descriptor

entries. The value of CSR2, bits 15-8, is used as the

upper 8-bits f or all memory addresses during bus mas-

ter transfers.

When SWSTYLE is set to 2 or 3, the descriptor ring

base addresses must be aligned to a 16-byte bound-

ary , and a maximum of 512 ring entries is allowed when

the ring length is set through the TLEN and RLEN fields

of the initiali zation block. Each ring entr y is organized

as three 32-bit message descriptors (SSIZE32

(BCR20, bit 8) is set to 1). The fourth DWord is re-

served. When SWSTYLE is set to 3, the order of the

message descriptors is optimized to allow read and

write access in burst mode .

For any software styl e, the ri ng len gths can be set b e-

yond this range (up to 65535) by writing the transmit

and receive ring leng th registers (CSR76, CSR78) di-

rectly.

Each ring entry contains the following information:

■The address of the actual message data buffer in

user or host memory

■The length of the message buffer

■Status information indicating the condition of the

buffer

To permit the queuing and de-queuing of message

buffers, owners hip of each buffer is allocate d to either

the Am79C973/Am79C975 controller or the host. The

O WN bit within the descriptor status information, either

TMD or RMD, is used for this purpose.

When OWN is set to 1, it signifies that the Am79C973/

Am79C975 controller currently has ownership of this

ring descriptor and its associated buffer. Only the

owner is permitted to relinquish ownership or to write to

any field in the descriptor entry. A de vice that is not the

current owner of a descriptor entry cannot assume

ownership or change any field in the entry. A device

may, however, read from a descriptor that it does not

curren tly own. Software sh ould always read descr ip tor

entries in sequential order. When software finds that

the current descriptor is owned by the Am79C973/

Am79C 975 con t roll er, then the software must not read

ahead to the next desc riptor. The software shoul d wait

at a descriptor it does not own until the Am79C973/

Am79C975 controller sets OWN to 0 to release owner-

ship to the software. (When LAPPEN (CSR3, bit 5) is

set to 1, this rule is modified. See the LAPPEN descrip-

tion. At initialization, the Am79C973/Am79C975 con-

troller reads the base address of both the transmit and

receive descriptor rings into CSRs for use by the

Am79C973/Am79C975 controller during subsequent

operations.

Figure 31 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is cleared to 0.

66 Am79C973/Am79C975

PRELIMINARY

Figure 31. 16-Bit Software Model

Note: The value of CSR2, bits 15-8, is used as the

upper 8-bits f or all memory addresses during bus mas-

ter transfers.

Figure 32 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is set to 1.

Polling

If there is no network channel activity and there is no

pre- or post-receive or pre- or post-transmit activity

being performed by the Am79C973/Am79C975 con-

troller, then the Am79C973/Am79C975 controller will

periodically poll the current receive and transmit de-

scr iptor entries in order t o a sc ertain the ir ownersh ip. If

the DPOLL bit in CSR4 is set, then the transmit polling

function is disa bled.

A typica l polli ng operation c onsists of the following se-

quence. The Am79C973/Am79C975 controller will use

the current receive descriptor address stored internally

to vector to the appropriate Receive Descriptor Table

Entr y (RDTE). It will then u se the current transmit de-

scri ptor address (stored int er nally) to vector to the ap-

propriate Transmit Descriptor Table Entry (TDTE). The

accesses will be made in the following order: RMD1,

then RMD0 of the current RDTE during one bus arbitra-

tion, and after that, TMD1, then TMD0 of the current

TDTE during a second bus arbitration. All information

collec ted during pol li ng activ ity wil l be stor e d int ernal ly

in the appropriate CSRs, if the OWN bit is set (i.e.,

CSR18, CSR19, CSR20, CSR21, CSR40, CSR42,

CSR50, CSR52).

A typical receiv e poll is the product of the following con-

ditions:

1. Am79C973/Am79C975 controller does not own the

current RDTE and the poll time has elapsed and

RXON = 1 (CSR0, bi t 5), or

2. Am79C973/Am79C975 controller does not own the

next RDT E and ther e is more than one receive de-

scriptor in the ring and the poll time has elapsed and

RXON = 1.

Initialization

Block

IADR[15:0]IADR[31:16]

CSR1

CSR2

TDRA[15:0]

MOD

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLE RES RDRA[23:16]

TLE RES TDRA[23:16]

Rcv

Buffers

RMD RMD RMD RMD

Rcv Descriptor

Ring

NNNN•••

1st desc.

start 2nd

desc.

RMD0

Xmt

Buffers

TMD TMD TMD TMD

Xmt Descriptor

Ring

MMMM•••

1st desc.

start 2nd

desc.

TMD

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

21510B21510D-36

Am79C973/Am79C975 67

PRELIMINARY

Figure 32. 32-Bit Software Model

If RXON is cleared to 0, the Am79C973/Am79C975

controller will never poll RDTE locations.

In order to avoid missing frames, the system should

have at least one RDTE available. To minimize poll ac-

tivity, two RDTEs s hould be available. In this case, the

poll operation will only consist of the check of the status

of the current TDTE.

A typical transmit poll is the product of the following

conditions:

1. Am79C973/Am79C975 controller does not own the

current TDTE and TXDPOLL = 0 (CSR4, bit 12) and

TXON = 1 (CSR0, bit 4) and

the poll time has elapsed, or

2. Am79C973/Am79C975 controller does not own the

current TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been received, or

3. Am79C973/Am79C975 controller does not own the

current TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode

controller to exit the poll counting code and immedi-

ately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE

poll will be performed ahead of the TDTE poll. If the mi-

crocode is not executing the poll counting code when

the TDMD bit is set, then the demanded poll of the

TDTE will be delay ed until the microcode returns to the

poll counti ng co de.

The us er may chang e the poll time value from the de-

fault of 65,536 clock per iods by modifyi ng the value i n

the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) ac-

cess, the Am79C973/Am79C975 controller finds that

the OWN bit of that TDTE is not set, the Am79C973/

Am79C 975 con troller resu mes the pol l time c ount an d

re-examines the same TDTE at the next expiration of

the poll time count.

If the OWN bit of the TDTE is set, but the Start of

Packet (STP) bit is not set, the Am79C973/Am79C975

controller will immediately request the bus in order to

clear the OWN bit of this descriptor. (This condition

would normally be found following a late collision

(LCOL) or r etr y ( RTRY ) error t hat occur red in th e mid-

dle of a transmit frame chain of buff ers .) After resetting

Initialization

Block

CSR1CSR2

RMD RMD RMD RMD

Rcv Descriptor

Ring

NNNN•••

1st

desc.

start

2nd

desc.

start

RMD

TMD0 TMD1 TMD2 TMD3

Xmt Descriptor

Ring

MMMM•••

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16] IADR[15:0]

TLE

RES

RLE

RES

MODE

PADR[47:32]

RES LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

21510D-37

68 Am79C973/Am79C975

PRELIMINARY

the OWN bit of this descriptor, the Am79C973/

Am79C975 controller will again immediately request

the bus in order to access the ne xt TDTE location in the

ring.

If the OWN bit is set and the buffer length is 0, the OWN

bit will be cleared. In the C-LANCE device, the buffer

length of 0 is int er pret ed as a 409 6-byte buffer. A zero

length buffer is acceptable as long as it is not the last

buffer in a chain (STP = 0 and ENP = 1).

If the O WN bit and STP are set, then microcode control

proceeds to a routine that will enable transmit data

transfers to the FIFO. The Am79C973/Am79C975 con-

troller will look ahead to the next transmit descriptor

after it has per formed at least one transmit da ta trans-

fer from the first buffer.

If the Am79C973/Am79C975 controller does not own

the next TDTE (i.e., the second TDTE f or this frame), it

will complete transmission of the current buffer and up-

date the status of the current (first) TDTE with the

BUFF and UFLO bits being set. If DXSUFLO (CSR3,

bit 6) is cleared to 0, the underflow error will cause the

transmitter to be disabled (CSR0, TXON = 0). The

Am79C973/Am79C975 controller will hav e to be re-ini-

tialized to res tore the trans mit fun cti on . Set tin g DXS U-

FLO to 1 enables the Am79C973/Am79C975 controller

to gracefully recover from an underflow error. The de-

vice will scan the transmit descriptor ring until it finds ei-

ther the start of a new frame or a TDTE it does not own.

To avoid an underflow situation in a chained buffer

transmission, the system should always set the trans-

mit chain descriptor own bits in reverse order.

If the Am79C973/Am79C975 controller does own the

second TDTE in a chain, it will gradually empty the con-

tents of the fir s t buffer (as the bytes are nee ded by the

transmit operation), perform a single-cycle DMA trans-

fer to update the status of the first descriptor (clear the

OWN bit in TMD1), and then it may perform one data

DMA access on the second buffer in the chain before

executing another lookahead operation. (i.e., a looka-

head to the third descriptor.)

It is imperative that the host system never reads the

TDTE OWN bits out of order. The Am79C973/

Am79C975 controller normally clears OWN bits in strict

FIFO order. However, the Am79C973/Am79C975 con-

troller can queue up to two frames in the transmit FIFO.

When the second frame uses buffer chaining, the

Am79C973/Am79C975 controller might return owner-

ship out of normal FIFO order. The OWN bit for last

(and maybe only) buffer of the first frame is not cleared

until transmission is completed. During the transmis-

sion the Am79C973/Am79C975 controller will read in

buffers for the next frame and clear their OWN bits for

all but the last one. The first and all intermediate buffers

of the second frame can have their OWN bits cleared

before the Am79C973/Am79C975 controller returns

ownership for the last buffer of the first frame.

If an error occurs in the transmission before all of the

bytes of the current buff er hav e been transf erred, trans-

mit sta tus of th e current buffer will be immediat ely up-

dated. If the buffer does not c on tai n th e en d of packet,

the Am79C973/ Am 79C9 75 c on troll er wi ll s ki p over the

rest of the frame which experienced the error. This is

done by retur ning to the polling microcode where the

Am79C973/Am79C975 controller will clear the OWN

bit for all descriptors with OWN = 1 and STP = 0 and

continue in like manner until a descriptor with OWN = 0

(no more transm it frames in the ri ng) or OWN = 1 and

STP = 1 (the first buffer of a new frame) is reached.

At the end of any transmit operation, whether success-

ful or with err ors, imme dia tel y following the com ple tio n

of the descriptor updates, the Am79C973/Am79C975

controller will always perf orm another polling operation.

As described earlier, this polling operation will begin

with a check of the current RDTE, unless the

Am79C973/Am79C975 controller already owns that

descr iptor. Then the Am79C973 /Am79C975 controll er

will pol l the next TDTE. I f the transmi t de sc riptor OWN

bit has a 0 value, the Am79C973/Am79C975 controller

will resume incrementing the poll time counter. If the

transmit descriptor OWN bit has a value of 1, the

Am79C973/Am79C975 controller will begin filling the

FIFO with transmit data and initiate a transmission.

This end- of-operation poll c oupled with the TDTE loo-

kahead operation allows the Am79C973/Am79C975

controller to avoid inserting poll time counts between

successive tr ansmit frames.

By default, whenever the Am79C973/Am7 9C975 con-

troller completes a transmit frame (either with or with-

out error) and writes the status information to the

current desc riptor, the n the TINT bit of CSR0 is set t o

indicat e the c omp letion of a transmi ss i on. Thi s c auses

an interrupt signal if the IENA bit of CSR0 has been set

and the TINTM bit of CSR3 is cleared. The Am79C973/

Am79C975 controller provides two modes to reduce

the number of transmit interrupts. The interrupt of a

successfully transmitted frame can be suppressed by

setting TINTOKD (CSR5, bit 15) to 1. Another mode,

which is enabled by setting LTINTEN (CSR5, bit 14) to

1, allows suppression of interrupts for successful trans-

missions for all but the last frame in a sequence.

Receive Descriptor Table E ntry

If the Am79C973/Am79C975 controller does not own

both the current and the next Receive Descriptor Table

Entry (RDTE), then the Am79C973/Am79C975 con-

troller will continue to poll according to the polling se-

quence de scr ibed above. If the receive descr iptor r ing

length is one, then there is no next descriptor to be

polled.

Am79C973/Am79C975 69

PRELIMINARY

If a poll operation has rev ealed that the current and the

next RDTE belong to t he Am79C973/A m79C975 con-

troller, then additional poll accesses are not necessary.

Future poll ope rations will not include RDT E acce sses

as long as the Am79C973/Am79C975 controller re-

tains ownership of the current and the next RDTE.

When receive activity is present on the channel, the

Am79C973/Am79C975 controller waits for the com-

plete address of the message to arrive. It then decides

whether to accept or reject th e frame based on all ac-

tive addressing s chemes. If the frame is accepted, th e

Am79C973/Am79C975 controller checks the current

receive buffe r status registe r CRST (CSR41) to deter-

mine the ownership of the current buffer.

If ownership is lacking, the Am79C973/Am79C975

controller will immediately perform a final poll of the

current RDTE. If ownership is still denied, the

Am79C973/Am79C975 controller has no buffer in

which to store the incoming message. The MISS bit will

be set in CSR0 and the Missed Frame Counter

(CSR112) wil l be in crem ente d. Another po ll of the cur-

rent RDTE will not occur until the frame has finished.

If the Am79C973/Am79C975 controller sees that the

last poll (either a normal poll, or the final effort de-

scribed in the above paragraph) of the current RDTE

shows valid ownership , it proceeds to a poll of the next

RDTE. Following this poll, and regardless of the out-

come of this poll, transfers of receive data from the

FIFO may begin.

Regardless of ownership of the second receive de-

scriptor, the Am79C973/Am79C975 controller will con-

tinue to perform receive data DMA transfers to the first

buff er . If the frame length e xceeds the length of the first

buffer, and the Am79C973 /Am79C975 controller does

not own the second buff er , ownership of the current de-

scr iptor wi ll be pa ssed back to the sys tem by writi ng a

0 to the OWN bit of RMD1. Status will be written indi-

catin g buffer (BUFF = 1) an d possi bly overflow (OFLO

= 1) errors.

If the frame length exceeds the le ngth of the first (cur -

rent) buffer, and the Am79C973/Am79C975 controller

does own the second (next) buffer, ownership will be

passed b ack to the sy stem by writin g a 0 to the OWN

bit of RMD1 when the first buffer is full. The OWN bit is

the only bit modified in the descriptor. Receive data

transfers to the second buffer may occur before the

Am79C973/Am79C975 controller proceeds to look

ahead to the ownership of the thir d buffer. Such ac tio n

will depend upo n the state of the FIFO when the OWN

bit has been updated in the first descriptor. In any case,

lookahea d wi ll be pe rform ed to the t h ird buffer and the

informati on gat her ed wi ll b e st ored i n the c hip, regard-

less of the state of the ownership bit.

This activity continues until the Am79C973/Am79C975

controller recogn izes the comp letion of the frame (the

last byte of this receive message has been removed

from the FIFO). The Am79C973/Am79C975 controller

will subseq uent ly upda te the c urre nt RDTE s tatu s wit h

the end of frame (ENP) indication set, write the mes-

sage byte count (MCNT) for the entire frame into

RMD2, and overwrite the “current” entries in the CSRs

with the “next” entri es.

Receive Frame Queuing

The Am79C973/Am79C975 controller supports the

lack of RDTEs when SRAM (SRAM SIZE in BCR 25,

bits 7- 0) is en abled throu gh the R ece ive Frame Q ueu-

ing mechanism. When the SRAM SIZE = 0, then the

Am79C973/Am79C975 controller rever ts back to the

PCnet PCI II mode of operation. This operation is auto-

matic and does not require any programming by the

host. When SRAM is enabled, the Receive Frame

Queuing mechanism allows a slow protocol to manage

more frames wit hou t the high frame lo ss rate no r mally

attributed to FIFO based network controllers.

The Am79C9 73/Am 79C975 co ntrol ler will sto re the in-

coming frames in the extended FIFOs until polling

takes place; if en abled, it discovers it owns an RDTE.

The stored frames are not altered in any way until writ-

ten out into system buffers. When the receive FIFO

overflows, further incoming receive frames will be

missed during that time. As soon as the network re-

ceive FIFO is empty, incoming frames are processed

as normal. Status on a per frame basis is not kept dur-

ing the overflow process. Statistic counters are main-

tained and accurate during that time.

During the time that the Receive F rame Queuing mech-

anism is in operation, the A m79C973 /Am79C9 75 con-

troller relies on the Receive Poll Time Counter (CSR

48) to control the worst case access to the RDTE. The

Receive Poll Time Counter is programmed through the

Receive Polling Interval (CSR49) register. The Re-

ceived Poll ing Inter val defaults to approximately 2 ms.

The Am79C973/Am79C975 controller will also try to

access the RDTE during normal descriptor accesses

whether they are transmit or receive accesses. The

host can force the Am79C973/Am79C975 controller to

immediately access the RDTE by setting the RDMD

(CSR 7, bit 13) to 1. Its operation is similar to the trans-

mit on e. The pol ling proces s can be d isab led b y s etting

the RXDPOLL (CSR7, bit 12) bit. This will stop the au-

tomatic polling process and the host must set the

RDMD bit to initiate the receiv e process into host mem-

ory. Receive frames are still stored even when the re-

ceive polling process is disabled.

Software Interrupt Timer

The Am79C973/Am79C975 controller is equipped with

a software programmable free-running interrupt timer.

The timer is constantly running and will generate an in-

terrup t STINT (CSR 7, bit 1 1) when STINITE (CSR 7,

bit 10) is set to 1. After generating the interrupt, the

70 Am79C973/Am79C975

PRELIMINARY

software timer will load the value stored in STVA L and

restart. The timer value STV AL (BCR31, bits 15-0) is in-

terpreted as an unsigned number with a resolution of

256 Time Base Clock periods. For instance, a value of

122 ms would be programmed with a value of 9531

(253Bh), if the T ime Base Clo ck is runni ng at 20 MHz.

The default value of STVAL is FFFFh which yields the

approximate ma ximum 838 ms ti mer duration. A write

to STVAL restarts the timer with the new contents of

STVAL.

10/100 Media Access Control

The Medi a Ac ce ss Con tr ol ( MAC) engin e in co rporates

the essen tial pro toc ol requi re men ts for operation of a n

Etherne t/IE EE 80 2.3-c om pli ant no de and provides th e

interface between the FIFO subsystem and the internal

PHY.

This section describes operation of the MAC engine

when operating in half-duplex mode. When operating in

half-duple x mode, the MAC engine is fully compliant to

Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard

1990 Second Edition) and ANSI/IEEE 802.3 (1985).

When operating in full-duplex mode, the MAC engine

behavior changes as described in the section Full-

Duplex Operation .

The MAC engine provides programmable enhanced

features designed to minimize host supervision, bus

utilization, and pre- or post-message processing.

These features include the ability to disable retries after

a collision, dynamic FCS generation on a frame-by-

frame basis, autom ati c p ad fi el d ins ertion and de le tio n

to enforce minimum frame size attributes, automatic re-

transmission without reloading the FIFO, and auto-

matic deletion of collision fragments.

The two primary attributes of the MAC engine are:

■Transmit and receive message data encapsulation

—Framing (frame boundary delimitation, frame

synchronization)

—Addressing (source and destination address

handling)

—Error detection (physical medium transmission

errors)

■Media access management

—Medium allocation (collision avoidance, except

in full-duplex operation)

—Contention resolution (collision handling, except

in full-duplex operation)

T ransmit and Receive Message Data Encapsulation

The MAC engine provides minimum frame size en-

forcement for transmit and receive frames. When

APAD_XMT (CSR, bit 11) is set to 1, transmit mes-

sages will be padded with sufficient bytes (containing

00h) to ensure that the receiving station will observe an

informati on fie ld (desti nati on add r ess, sou rce add re ss,

length/type, data, and FCS) of 64 bytes. When

ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will

automatically strip pad bytes from the received mes-

sage by obser ving the value in the length fiel d and by

stripping excess bytes if this value is below the mini-

mum data size (46 bytes). Both features can be inde-

pendently over-ridden to allow illegally short (less than

64 bytes of frame data) messages to be transmitted

and/or received. The use of this feature reduces bus

utilization because the pad bytes are not transferred

into or out of main memory.

Framing

The MAC engine will autonomously handle the con-

struction of the transmit frame. Once the transmit FIFO

has been fi lled to the predet ermi ned threshold (se t by

XMTSP in CSR80) and access to the channel is cur-

rently permitted, the MAC engine will commence the 7-

byte preamble sequence (10101010b, where first bit

transmitte d is a 1) . The MAC engine will subs equen tly

append the Start Frame Delimiter (SFD) byte

(10101011b) followed by the serialized data from the

transmit FIFO . Once the data has been completed, the

MAC engine will append the FCS (most significant bit

first) which was computed on the entire data portion of

the frame. The data portion of the frame consists of

destination address, source address, length/type, and

frame data. Th e user is respo nsible for the correct or -

dering and content in each of these fields in the frame.

The MAC does not use the content in the length/type

field unless APAD_XMT (CSR4, bit 11) is set and the

data portion of the frame is shorter than 60 bytes.

The MAC engine will detect the incoming preamb le se-

quence wh en the RX_DV s ignal is ac tivated by the in-

ternal PHY. The MAC will discard the preamble and

begin searching for the SFD. Once the SFD is de-

tected, all subsequent nibbles are treated as part of the

frame. The MAC engine will inspect the length field t o

ensure minimum frame size, strip unnecessary pad

characters (if enabled), and pass the remaining bytes

through the receive FIFO to the host. If pad stripping is

performed, the MAC engine wil l als o strip the r ec eived

FCS bytes, although normal FCS computation and

checking will occur. Note that apart from pad stripping,

the frame will be p assed unm odified to th e host. If the

len gth f iel d ha s a value o f 4 6 or gr eat er, all fr am e b yt es

including FCS will be passed unmodified to the receive

buffer, regardless of the actual frame length.

If the frame ter mina tes or suffers a colli sion before 64

bytes of information (after SFD) have been received,

the MAC engine will automatically delete the frame

from the receive FIFO, without host intervention. The

Am79C 973/Am79C9 75 controll er has the ability to ac-

cept runt packets for diagnostic purposes and propri-

etary networks.

Am79C973/Am79C975 71

PRELIMINARY

Destination Address Handling

The firs t 6 bytes of infor mation afte r SFD wi ll be i nter-

preted as the destination address field. The MAC en-

gine provides facilities for physical (unicast), logical

(multicast), and broadcast address reception.

Error Detection

The MAC engine provides several facilities which re-

port and recover from errors on the medium. In addi-

tion, it protects the network from gross errors due to

inabili ty of t he hos t to keep pac e with the MAC engin e

activity.

On completion of transmission, the following transmit

status is av ailable in the appropriate Transmit Message

Descriptor (TMD) and Control and Status Register

(CSR) areas:

■The number of transmission retry attempts (ONE,

MORE, RT RY, and TRC).

■Whether the MAC engine had to Def er (DEF) due to

chann el activ it y.

■Excessive deferral (EXDEF), indicating that the

transmitter experienced Excessive Deferral on this

transmit frame, where Excessive Deferral is defined

in the ISO 8802-3 (IEEE/ANSI 802.3) standard.

■Loss of Carrier (LCAR), indicating that there was an

interruption in the ability of the MAC engine to mon-

itor its ow n tran smissi on. Rep eated LC AR erro rs in-

dicate a potentially faulty transceiver or network

connection.

■Late Collision (LCOL) indicates that the transmis-

sion suffered a collision after the slot time. This is in-

dicative of a badly configured network. Late

collisions should not occur in a normal operating

network.

■Collision Error (CERR) indicates that the trans-

ceiver did not respond with an SQE Test message

within the first 4 ms after a transmission was com-

pleted. T his may be due to a failed transce iver, dis -

connected or faulty transceiver drop cable, or

because the transceiver does not suppor t this fea-

ture (or it is disabled). SQE Test is only valid for 10-

Mbps network s.

In addition to the reporting of network errors, the MAC

engine will also atte mpt to prevent the cr eation of any

network error due to the inabi lity o f the hos t to se r vic e

the MAC engine. During transmission, if the host fails

to keep the transmi t F IFO f illed s uffi ci en tly, c aus in g a n

underflow , the MAC engine will guarantee the message

is either sent as a runt packet (which will be deleted by

the receiving station) or as an invalid FCS (which will

also cause the receiver to reject the message).

The statu s of eac h re ce ive message is available in the

appropriate Receive Message Descriptor (RMD) and

CSR areas. All received frames are passed to the host

regardless of any error . The FRAM error will only be re-

por ted if an FCS erro r is detected and there is a non-

integral number of bytes in the message.

During the reception, the FCS is generated on every

nibble (including the dribbling bits) coming from the ca-

ble, although the internally saved FCS value is only up-

dated on the eighth bit (on each byte boundary). The

MAC engine will ignore up to 7 additional bits at the end

of a message (dribbling bits), which can occur under

normal network operating conditions. The framing error

is reported to the user as follows:

■If the number of dribbling bits are 1 to 7 and there is

no FCS error , then there is no F raming error (FRAM

= 0).

■If the number of dribbling bits are 1 to 7 and there is

a FCS error, then there is also a Framing error

(FRAM = 1).

■If the number of dr ibbling bi ts is 0, the n there is n o

Fram ing error. There may or may not be a FCS er-

ror.

■If the number of dribbling bits is EIG HT, then th ere

is no Framin g error. FCS error wil l be rep orted and

the receive message count will indicate one extra

byte.

Counters are provided to report the Receive Collision

Count and Runt Packet Count, for network statistics

and utilization calculations.

Media Access Management

The basic requirement f or all stations on the network is

to provide fairness of channel allocation. The IEEE

802.3/Ethernet protocols define a media access mech-

anism which permits all stations to access the channel

with equ ality. Any node can atte mpt to conten d for the

channel by waiting for a predetermined time (Inter

Packet Gap) after the last activity, before transmitting

on the media. T he channel is a multidrop com munica-

tions media (with various topological configurations

permitted), which allows a single station to transmit and

all other stations to receive. If two nodes simulta-

neously contend for the channel, their signals will inter-

act causing loss of data, defined as a collision. It is the

responsibility of the MAC to attempt to avoid and

recover from a coll isio n, to guaran tee data i ntegr ity for

the end-to-end transmission to the receiving station.

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)

requires that the CSMA /CD MAC mo nitor the medium

for traffic b y watching for carrier activity. When carrier is

detected, the media i s considere d busy, and th e MAC

should defer to the e xisting message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard also al-

lows optiona lly a two -p art deferral after a rec ei ve mes-

sage.

72 Am79C973/Am79C975

PRELIMINARY

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: It is possible f or the PLS carrier sense indication

to fail to be assert ed dur in g a col lis ion on the media. If

the deference process simply times the inter-Frame

gap based on this indication, it is possible for a shor t

interFrame gap t o be generat ed, le ading to a po tential

reception failure of a subsequent frame. To enhance

system robustness, the following optional measures,

as specified in 4.2.8, are recommended when Inter-

Frame-SpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the in-

terrupted gap, as soon as transmitting and carrier

sense are both false.

2. When timing an inter-frame gap following reception,

reset the inter-frame gap timing if carrier sense be-

comes true during the first 2/3 of the inter-frame gap

timing interval. During the final 1/3 of the interval,

the timer shal l not be re set to ens ure fair acc ess to

the medium. An initial period shorter than 2/3 of the

interval is permissible including 0.

The MAC engine impleme nts the optional receive two

part deferral algorithm, with an InterFrameSpacing-

Part1 time of 6.0 ms. The InterFrameSpacingPart 2 in-

terval is, therefore, 3.4 ms.

The Am79C973/Am79C975 controller will perform the

two-part def erral algorithm as specified in Section 4.2.8

(Process Def erence). The Inter P ac ket Gap (IPG) timer

will start timing the 9.6 ms InterFrameSpacing after the

receive carrier is deasser ted. During the first par t de-

ferral (InterFrameSpacingPart1 - IFS1), the

Am79C973/Am79C975 controller will defer any pend-

ing transmit frame and respond to the receive mes-

sage. The IPG counter will be cleared to 0 continuously

until the carrier deasserts, at which point the IPG

counter will resume the 9.6 ms count once again. Once

the IFS1 period of 6.0 ms has elapsed, the Am79C973/

Am79C9 75 cont ro ll er will beg in timing th e se co nd pa rt

deferral (InterFrameSpacingPart2 - IFS2) of 3.4 ms.

Once I FS1 has co mplete d and IFS2 has commenc ed,

the Am79C973/Am79C975 controller will not defer to a

receive frame if a transmit frame is pending. This

means that the Am79C973/Am79C975 controller will

not attempt to receive the receive frame, since it will

start to transmit and generate a collision at 9.6 ms. The

Am79C973/Am79C975 controller will complete the

preamble (64-bit) and jam (32-bit) sequence before

ceasing transmission and invoking the random backoff

algorithm.

The Am79C973/Am79C975 controller allows the user

to program the IPG and the first part deferral (Inter-

Frame-SpacingPart1 - IFS1) through CSR125. By

changing the IPG default value of 96 bit times (60h), the

user can adjust the fairness or aggressiveness of the

Am79C973/Am79C975 MAC on the network. By pro-

gramming a lower number of bit times than the ISO/IEC

8802-3 standard requires, the Am79C973/Am79C975

MAC engin e will become more aggressi ve on the net-

work. This aggressive nature will give rise to the

Am79C973/Am79C975 controller possibly capturing

the network at times by forcing other less aggressive

compliant nodes to defer. By programming a larger

number of bit times, the Am79C973/Am79C975 MAC

will become less aggressive on the network and may

defer more often than normal. The perform ance of the

Am79C973/Am79C975 controller may decrease as the

IPG value is increased from the default value, but the

resulting behavior may improve network performance

by reducing collisions. The Am79C973/Am79C975

controller uses the same IPG for back-to-back trans-

mits and rece ive-to-tran sm it acc esse s. Changi ng IFS 1

will alter the period for which the Am79C973/

Am79C 975 MAC engine will defer to incoming rece ive

frames.

CAUTION: Care must be exercised when altering

these parameters. Adverse network activity could

result!

This transmit two-part deferral algorithm is imple-

mented as an option which can be disabled using the

DXMT2PD bit in CSR3. The IFS1 programming will

have no eff ect when DXMT2PD is set to 1, but the IPG

programming value is stil l valid. Two par t d eferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver should

generate the SQE Test message within 0.6 to 1.6 ms

after the transmission ceases. During the time period in

which the SQE Test message is expected, the

Am79C973/Am79C975 controller will not respond to

receive carrier sense .

See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):

“At the co nclusion o f the output fu nction, the DTE

opens a time window during which it expects to see

the signal_quality_error signal asserted on the

Control In circuit. The time window begins when

the CARRIER_STATUS becomes

CARRIER_OFF. If execution of the output function

does not cause CARRIER_ON to occur, no SQE

test occurs in the DTE. The duration of the window

shall be at least 4.0 ms but no more than 8.0 ms.

During the time window the Carrier Sense Function

is inhibited.”

The Am79C973/Am79C975 controller implements a

carrier sense “blinding” period of 4 .0 ms l eng th starting

from the deasser tion of carrier sense after transmis-

sion. This effectively means that when transmit two part

deferral is enabled (DXMT2PD is cleared), the IFS1

time is from 4 ms to 6 ms after a transmission. How-

Am79C973/Am79C975 73

PRELIMINARY

ever , since IPG shrinkage below 4 ms will rarely be en-

countered on a correctly configured network, and since

the fragment size will be larger than the 4 ms blinding

window, the IPG counter will be reset by a worst case

IPG shr inkage/frag ment scenar io an d the Am79C973 /

Am79C9 75 cont roller will defer its transm ission. If car-

rier is detect ed with in the 4.0 to 6. 0 ms IF S1 period, the

Am79C973/Am79C975 controller will not restart the

“blinding” period, but only restart IFS1.

Collision Handling

Collision detection is performed and reported to the

MAC engine via the COL input pin.

If a collision is detected before the complete preamble/

SFD seq uen ce has bee n transmitted, t he MAC engine

will comple te the pream ble/SFD before appen ding the

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits

being transmitted, the MA C engine will abort the trans-

mission and append the jam sequence immediately.

The jam sequence is a 32-bit all zeros pattern.

The MAC engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to nor-

mal coll isions (those wit hin the s lot time) . Detecti on of

collis io n wil l c aus e the trans mi ssio n to be r es ch edu le d

to a time determ ine d by the random ba ckoff algori thm .

If a single retry w as required, the 1 bit will be set in the

transmit frame status. If more than one retry was re-

quired, the MORE bit w ill be set. If all 16 attempts ex-

perienced collisions, the RTRY bit will be set (1 and

MORE will be cl ear) , and the transmi t mes sage wi ll be

flushed from the FIFO. If retries have been disabled by

setting the DRTY bit in CSR15, the MAC engine will

abandon tra ns mis sion of the fram e on de tec tio n o f th e

first collision. In this case, only the RTRY bit will be set

and the transmit message will be flushed from the

FIFO.

If a collision is detected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MAC engine will abor t the transmission, append the

jam se quence, and se t the LCOL bit. No r etr y attemp t

will be scheduled on detection of a late collision, and

the transmit message will be flushed from the FIFO.

The ISO 8802- 3 ( IEE E/ ANS I 802 .3) Stan dar d r equ ires

use of a “truncated binary exponential backoff” algo-

rithm, which provides a controlled pseudo random

mechanism to enforce the collision backoff interval,

before retransmission is attempte d.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), the

CSMA /CD su blayer delays before attemp ting to re-

transmit the frame. The delay is an integer multiple

of slot time. The number of slo t times to delay be-

fore the nth retransmission attempt is chosen as a

uniformly distributed random integer r in the range:

0 ≤ r < 2k where k = min (n,10).”

The Am79C973/Am79C975 controller provides an al-

ternative algorithm, which suspends the counting of the

slot time/IPG during the time that receive carrier sense

is detected. This aids in networks where large numbers

of nodes are present, and numerous nodes can be in

collision. It effectively accelerates the increase in the

back off time in busy networks and allows nodes not in-

volved in the col lisi on to ac ce ss t he ch annel, whi le th e

colliding nodes await a reduction in channel activity.

Once channel activity is reduced, the nodes resolving

the collision time-out their slot time counters as normal.

This modified backoff algorithm is enabled when EMBA

(CSR3, bit 3) is set to 1.

Transmit Operation

The transmit operation and f eatures of the Am79C973/

Am79C975 controller are controlled by programmable

options. The Am79C973/Am79C975 controller offers a

large transmit FIFO to provide frame buffering for in-

crease d sy st em l at en cy, auto ma tic re t r an smission w i th

no FIFO reloa d, and autom atic trans mit paddi ng.

Transmit Function Programming

Automatic transmit features such as retr y on collision,

FCS generation/transmission, and pad field insertion

can all be programme d to pr ovide flexibility in the (r e-)

transmis si on of mes sa ges.

Disable retry on collision (DRTY) is controlled by the

DRTY bit of the Mode register (CSR15) in the initializa-

tion block.

Automatic pad field insertion is controlled by the

APAD_XMT bit in CSR4.

The disable FCS generation/transmission feature can

be programmed as a static feature or dynamically on a

frame-by-frame basis.

Transmit FIFO W atermark (XMTFW) in CSR80 sets the

point at which the BMU requests more data from the

transmit buffers for the FIFO. A minimum of XMTFW

empty spaces must be available in the transmit FIFO

before the BMU will request the system bus in order to

transfer transmit frame data into the transmit FIFO.

Trans mit S tart Point (XM T SP ) in CS R80 s ets th e p oin t

when the transmitter actually attempts to transmit a

frame onto the media. A minimum of XMTSP bytes

must be written to the transmit FIFO for the current

frame before transmis si on of th e c urr ent frame wil l be-

gin. (When automatically padded packets are being

sent, it is conceivable that the XMTSP is not reached

when all of th e data has been tra nsferred to the F IFO.

In this case, the transmission will begin when all of the

frame data has been placed into the transmit FIFO.)

The default v alue of XMTSP is 01b, meaning there has

74 Am79C973/Am79C975

PRELIMINARY

to be 64 bytes in the transmit FIFO to start a transmis -

sion.

Automatic Pad Generation

Transmit frames can be automatically padded to extend

them to 64 data bytes (excluding preamble). This al-

lows the min imum frame s ize of 64 bytes (5 12 bits) for

IEEE 802.3/Ethernet to be guaranteed with no software

inter vention from the host/controlling process. Setting

the APAD_XMT bit in CSR4 enables the automatic

padding feature. The pad is placed between the LLC

data field and FCS field in th e IEEE 802.3 frame. FCS

is always added if the frame is padded, regardless of

the state of DXMTFCS (CSR15, bit 3) or ADD_FCS

(TMD1, bit 29). The transmit frame will be padded by

bytes with the value of 00H. The default value of

APAD_XMT is 0, which will disable automatic pad gen-

eration after H_RESET.

It is the responsibility of upper layer software to cor-

rectly define the actual length field contained in the

message to correspond to the total number of LLC

Data bytes encapsulated in the frame (length field as

defined in the ISO 8802-3 (IEEE/ANSI 802.3) stan-

dard). The length value contained in the message is not

used by the Am7 9C973/Am79C975 c ontroller to com-

pute the actual number of pad bytes to be inserted. The

Am79C973/Am79C975 controller will append pad

bytes dependent on the actual number of bits transmit-

ted onto the network. Once the last data byte of the

frame has co mplete d, pri or to append in g the FCS, the

Am79C973/Am79C975 controller will check to ensure

that 544 bits have been transmitted. If not, pad bytes

are added to extend the frame size to this value, and

the FCS is then added. See Figure 33.

Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble/SFD,

including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bits

At the point that FCS is to be appended, the transmitted

frame should contain:

Preamble/SFD + (Min Frame Size - FCS)

64 + (512-32) = 544 bits

A minimum length transmit frame from the Am79C973/

Am79C975 controller, therefore, will be 576 bits, after

the FCS is appended.

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS

(CSR15, bit 3). If DXMTFCS is cleared to 0, the trans-

mitter will generate and appe nd the FCS to the trans-

mitted frame. If the automatic padding feature is

invoked (APAD_XMT is set in CSR4), the FCS will be

appended to frames shorter than 64 bytes by the

Am79C973/Am79C975 controller regardless of the

state of DXMTF CS or ADD_FC S (TMD 1, bit 29). Not e

that the ca lculated FC S is transmitted most signifi cant

bit first. The default value of DXMTFCS is 0 after

H_RESET.

ADD_FCS (TMD1, b it 29) allows the au tomatic gener-

ation and transmission of FCS on a frame-by-frame

basis. DXMTFCS should be set to 1 in this mode. To

generate FCS for a frame, ADD_FCS must be set in all

descriptors of a frame (STP is set to 1). Note that bit 29

of TMD1 has the function of ADD_FCS if SWSTYLE

(BCR20, bits 7-0) is programmed to 0, 2, or 3.

Transmit Exception Conditions

Exception conditions for frame transmission fall into

two distinct categories: those conditions which are the

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal ev ents which may occur and which are handled

auto nomo usly b y t he Am 79C973 /Am7 9C975 contro ller

include collisions within the slot time with automatic re-

try. The Am79C973/Am79C975 controller will ensure

that collisions which occur within 512 bit times from the

Preamble

1010....1010 SFD

10101011 Destination

Address Source

Address Length LLC

Data Pad FCS

Bytes

46 – 1500

Bytes

Bits

21510D-38

Am79C973/Am79C975 75

PRELIMINARY

start of transm is sion (inclu ding prea mble) wil l b e au to-

matically retried with no host interv ention. The transmit

FIFO ensures this by guaranteeing that data contained

within the FIFO will not be overwritten un til at least 6 4

bytes (512 b its) of preamble plus a ddres s, length , and

data fields have been transmitted onto the network

without encountering a collision. Note that if DRTY

(CSR15, bit 5) is set to 1 or if the network interface is

operating in full-duplex mode, no collision handling is

required, and any byte of frame data in the FIFO can be

overwritten as soon as it is transmitted.

If 16 total attempts (initial attempt p lus 15 retries) fail,

the Am79C973/Am79C975 controller sets the RTR Y bit

in the cur rent transmit TD TE in host memo ry (TMD2),

gives up ownership (resets the OWN bit to 0) for this

frame, and processes the next frame in the transmit

ring for transmission.

Abnormal network conditions include:

■Loss of carrier

■Late collision

■SQE Test Error (Does not apply to 100-Mbps net-

works.)

These conditio ns should not occ ur on a correctl y con-

figured IEEE 802.3 network operating in half-duplex

mode. If they do, they will be repor ted. None of these

conditions will occur on a network operating in full-

duplex mode. (See the section Full-Duplex Operation

for more detail.)

When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in the

current descriptor. The OWN bit(s) in the subsequent

descriptor(s) will be cleared until the STP (the next

frame) is found.

Loss of Carrier

LCAR will be reported f or ev ery frame transmitted if the

cont roller detects a loss of carrier.

Late Collision

A late collision will be reported if a collision condition

occurs after one slot time (512 bit times) after the trans-

mit process was initiated (first bit of preamble com-

menced). The Am79C973/Am79C975 controller will

abandon the transmit process for that frame, set Late

Collision (LCOL) in the associated TMD2, and process

the next transmit fram e in the ring. Frames experi enc-

ing a late collision will not be retried. Recovery from this

condition must be performed by upper lay er software.

SQE Test Error

CERR will be asser ted in the 10BASE-T mode after

transmit, if the network port is in Link Fail state. CERR

will never cause INTA to b e activated. It wil l, however,

set the ERR bit CSR0.

Receive Operation

The receive operation an d fe atures of the Am79C973/

Am79C975 controller are controlled by programmable

options. The Am79C973/Am79C975 controller offers a

large receive FIFO to provide frame buffering for in-

creased system latency, automatic flushing of collision

fragments (runt packets), automatic receive pad strip-

ping, and a variety of address match options.

Receive Function Programming

Automat ic pad fie ld strip ping is e nabled by sett ing the

ASTRP_RCV bit in CSR4. This can provide fle xibility in

the reception of messages using the IEEE 802.3 frame

format.

All receive frames can be accepted by setting the

PROM bit in CSR15. Acceptance of unicast and broad-

cast frames can be individually turned off by setting the

DRCVPA or DRCVBC bits in CSR15. The Physical Ad-

dress register (CSR12 to CSR14) stores the address

that the Am79C973/Am79C975 controller compares to

the destination address of the incoming frame f or a uni-

cast address match. The Logical Address Filter register

(CSR8 to CS R11) ser ves as a hash fi lter for multicast

address match.

The point at which the BMU will start to transfer data

from the receive FIFO to buffer memory is controlled by

the RCVFW bits in CSR80. The default established

during H_RESET is 01b , which sets the watermark flag

at 64 bytes filled.

For test p ur p oses, the Am 79C973 /Am79C9 75 con trol-

ler c an be p rogrammed to a ccept r unt packets by set-

ting RPA in CSR124.

Address Matching

The Am79C973/Am79C975 controller supports three

types of address matching: unicast, multicast, and

broadcast. The normal address matching procedure

can be modi fied by programming three bit s in CSR15,

the mode register (PROM, DRCVPA, and DRCVBC).

If the first bit received after the SFD (the least signifi-

cant bit of the first byte of the destination address field)

is 0, the frame is unicast, which indicates that the frame

is meant to b e r ec ei ved by a single nod e. If the firs t bi t

received is 1, the frame is multicast, which indicates

that the frame is meant to be received by a group of

nodes. If the destination address field contains all 1s,

the frame is broadcast, which is a special type of multi-

cast. Frames with the broadcast address in the destina-

tion address field are meant to be received by all nodes

on the local area networ k .

When a unicast frame arrives at the Am79C973/

Am79C975 controller, the controller will accept the

frame if the destination address field of the incoming

frame exactly matches the 6-byte station address

stored in the Physical Address registers (PADR,

76 Am79C973/Am79C975

PRELIMINARY

CSR12 to CSR14). The byte order ing is such tha t the

first byte received from the network (after the SFD)

must match the least significant byte of CSR12

(PADR[7:0]), and the sixth byte received must match

the most significant byte of CSR14 (PADR[47:40]).

When DRCVPA (CSR15, bit 13) is set to 1, the

Am79C973/Am79C975 controller will not accept uni-

cast frames.

If the incoming frame is multicast, the Am79C973/

Am79C975 controller performs a calculation on the

contents of the destination address field to deter mine

whether o r not to a ccept the fram e. This calc ulation is

explained in the sec tio n th at d es cr i bes th e Lo gi ca l A d-

dress Filt er (LAD RF).

When all bits of the LADRF registers are 0, no multicast

frames are accepted, except for broadcast frames.

Although broadcast frames are classified as special

multicast frames, they are treated differently by the

Am79C973/Am79C975 controller hardware. Broadcast

frames are always accepted, except when DRCVBC

(CSR15, bi t 14) is s et and ther e is no Log ical Address

match.

None of the address filtering described above applies

when the Am79C973/Am79C975 controller is operat-

ing in the promiscuous mode. In the promiscuous

mode, all properly formed packets are received, re-

gardless of the contents of their destination address

fields. The promiscuous mode overrides the Disable

Receive Broadcast bit (DRCVBC bit l4 in the MODE

(DRCVPA, CSR15, bit 13).

The Am79 C973 /A m79 C975 con troll er op erates i n pro-

miscuous mode when PROM (CSR15, bit 15) is set.

In addition, the Am79C973/Am79C975 controller pro-

vides t he Ex ter na l Addre ss Detec tion In terface (EADI)

to allow exter nal a ddress filte ring . See the se ct ion Ex-

ternal Address Detection Interface for further detail.

The recei ve descr ipt or entry RMD1 contain s t hree bits

that indicate which method of address matching

caused the Am79C973/Am79C975 controller to accept

the frame. Note that these indicator bits are only avail-

able when the Am79C973/Am79C975 controller is pro-

grammed to use 32-bit structures for the descriptor

entries (BCR20, bit 7-0, SWSTYLE is set to 2 or 3).

PAM (RMD1, bit 22) is set by the Am79C973/

Am79C975 controller when it accepted the received

frame due to a match of the frame’s destination ad-

dress with the content of the physical address register.

LAFM (RMD1, bit 21) is set by the Am79C973/

Am79C975 controller when it accepted the received

frame based on the value in the logical address filter

BAM (RMD1, bit 20) is set by the Am79C973/

Am79C975 controller when it accepted the received

frame because the frame’s destination address is of the

type ’Broadcast’.

If DRCVBC (CSR15 , b it 14) i s c lea red t o 0 , on ly B AM,

but not LAFM will be set when a Broadcast frame is re-

ceived, even if the Logical Address Filter is pro-

grammed in s uch a way that a Broadca st fram e would

pass the hash filter . If DRCVBC is set to 1 and the Log-

ical Address Filter is programmed in such a way that a

Broadc ast frame would pas s the hash fi lter, L AFM will

be set on the reception of a Broadcast frame.

When the Am79C973/Am79C975 controller operates

in promiscuous mode and none of the three match bits

is set, it is an indication that the Am79C973/Am79C975

controller only accepted the frame because it was in

promiscuous mode.

When the Am7 9C973/Am79 C975 contr oll er is not pr o-

grammed to be in promiscuous mode, but the EADI in-

terface is enabled, th en when no ne of the thr ee m atc h

bits is set, it is an indication that the Am79C973/

Am79C975 controller only accepted the frame because

it was not rejec ted by drivi ng the EAR pin LOW within

64 bytes after SFD.

See Table 7 for receiv e address matches.

Table 7. Receive Address Match

Automatic Pad Stripping

During reception of an IEEE 802.3 frame, the pad field

can be stripped automatically. Setting ASTRP_RCV

(CSR4, bi t 0) to 1 enables the automa tic pa d str ippin g

feature. The p ad fi eld wi ll be stripp ed b efore the frame

is pas se d to th e FIF O, thus pres ervi ng FI FO sp ac e for

addition al frames. The FCS field will also be str ipped,

since it is computed at the transmitting station based on

the data and pad field characters, and will be invalid for

a receive frame that has had the pad characters

stripped.

PAM LAF

MBAM

DRC

VBC Comment

000X

Frame accepted due to

PROM = 1 or no EADI

reject

1 0 0 X Physical address match

0100

Logical address filter

match;

frame is not of type

broadcast

0101

Logical address filter

match;

frame can be of type

broadcast

0010Broadcast frame

Am79C973/Am79C975 77

PRELIMINARY

The number o f bytes to be str ipped is c alculated from

the embedded length field (as defined in the ISO 8802-

3 (IEEE/ANSI 802.3) definition) contained in the frame.

The length indicates the actual number of LLC data

bytes contained in the message. Any received frame

which contains a length field less than 46 bytes will have

the pad fi eld s tri pped ( if AST RP_RCV i s se t). Re ceive

frames which have a length field of 46 bytes or greater

will be passed to the host unmodified.

Figure 34 shows the byte/bit ordering of the received

length field for an IEEE 802.3-compatible frame format.

Figure 34. IEEE 802.3 Frame And Length Field Transmission Order

Since any valid Ethernet Type field value will always be

greater than a normal IEEE 802.3 Length field (Š46),

the Am79C973/Am79C975 controller will not attempt to

strip valid Ethernet frames. Note that f or some network

protocols, the value passed in the Ethernet Type and/

or IEEE 802.3 Len gth field is not comp liant with eith er

standard and may cause problems if pad stripping is

enabled.

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the Am79C973/Am79C975

controller. Note that if the Automatic P ad Stripping fea-

ture is enabled, the FCS for padded frames will be ver-

ified against the value computed for the incoming bit

stream including pad characters, but the FCS value for

a padded frame will not be passed to the host. If an

FCS error is det ected in a n y fr a me , t he erro r wi ll be re -

ported in the CRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinc t categor ies, i .e., thos e co ndi tio ns whi ch a re th e

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal ev ents which may occur and which are handled

auto nomo usly b y t he Am 79C973 /Am7 9C975 contro ller

are basically collisions within the slot time and auto-

matic runt packet rejection. The Am79C973/

Am79C975 controller will ensure that collisions that

occur within 512 bit times from the start of reception

(e xcluding preamble) will be automatically deleted from

the receive FIFO with no host intervention. The receive

FIFO will delete any frame that is composed of fewer

than 64 bytes provided that the Runt Packet Accept

(RPA bit in CSR124) feature has not been enabled and

the networ k i nte rface is operating in ha lf- du plex mode,

or the full-duple x Runt P ack et Accept Disable bit (FDR-

PAD, BCR9, bit 2) is set. This criterion will be met re-

gardless of whethe r the rec eive frame was the first (or

only) frame in the FIFO or if the receive frame was

queued behind a previously received message.

Abnormal network conditions include:

Preamble

1010....1010 SFD

10101011 Destination

Address Source

Address Length LLC

Data Pad FCS

Bytes

46 – 1500

Bytes

Bits

Start of Frame

at Time = 0

Increasing T ime

Bit

0Bit

7Bit

0Bit

Most

Significant

Byte

Least

Significant

Byte

1 – 1500

Bytes 45 – 0

Bytes

21510D-39

78 Am79C973/Am79C975

PRELIMINARY

■FCS er rors

■Late collision

Host related receive exception conditions include

MISS, BUFF, and OFLO. These are described in the

section, Buffer Management Unit.

Loopback Operation

Loopback is a mode of operation intended for system

diagnost ics. In this mode, the tra nsmitter and re ceiver

are both operating at the same time so that the control-

ler receives its own transmissions. The controller pro-

vides two basic types of loopback. In internal loopback

mode, the transmitted data is looped back to the re-

ceiver inside the controller without actually transmitting

any data to the external network. The receiver will

move the received data to the next receive buffer,

where it can be examined by software. Alter n ati vely, in

external loopback mode, data can be transmitted to

and received from the external network.

Refer to Table 21 for various bit settings required for

Loopback modes.

The external loopback requires a two-step operation.

The internal PHY must be placed into a loopback mode

by writing to the PHY Control Register (BCR33,

BCR34). Then, the Am79C973/Am79C975 controller

must be placed into an e xternal loopback mode b y set-

ting the Loop bits.

Miscellaneous Loopba ck Features

All transmit and receiv e function programming, such as

automa tic transmit paddi ng and receive pad str ipping ,

operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is in-

voked. This is to be backwards compatible to the C-

LANCE (Am7 9C90 ) software.

Since the Am79C973/Am79C975 controller has two

FCS generators, there are no more restrictions on FCS

generation or checking, or on testing multicast address

detect ion as they exist in the half-duplex PCnet family

devices and in the C-LANCE. On receive, the

Am79C973/Am79C975 controller now provides true

FCS status. The descriptor for a frame with an FCS

error will hav e the FCS bit (RMD1, bit 27) set to 1. The

FCS generator on the transmit side can still be disabled

by setting DXMTFCS (CSR15, bit 3) to 1.

In internal loopback operation, the Am79C973/

Am79C975 controller provides a special mode to test

the collision logic. When FCOLL (CSR15, bit 4) is set

to 1, a collision is fo rced dur ing ever y transmission at-

tempt. This will result in a Retry error.

Full-Duplex Operation

The Am79C973/Am79C975 controller supports full-du-

plex operation on both network interfaces. Full-duplex

operation allows simultaneous transmit and receive ac-

tivity. Fu ll -dupl ex operatio n is enabled by the FD E N bi t

located in BCR9. Full-duplex operation is also enabled

through Auto-Negotiation when D ANAS (BCR 32, bit 7)

is not enabled and the ASEL bit is set, and its link partner

is capable of Auto-Negotiation and full-duplex opera-

tion.

When operating in full-duplex mode, the following

changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

■The first 64 bytes of every transmit frame are not

pres erved in the Transmi t FIFO durin g tran smissi on

of the first 512 bits as described in the Transmit Ex-

ception Conditions section. Instead, when full-du-

plex mode is active and a frame is being transmitted,

the XMTFW bits (CSR80, bits 9-8) always govern

when transmit DMA is requested.

■Successful reception of the first 64 bytes of every

receive frame is not a requirement for Receive DMA

to begin as described in the Receive Exception Con-

ditions section. Instead, receive DMA will be re-

quested as soon as either the RCVFW threshold

(CSR80, b its 12-13 ) is re ached or a comp lete valid

receive frame is detected, regardless of length. This

Receive FIFO operation is identical to when the RP A

bit (CSR124, bit 3) is set during half-duplex mode

operation.

The MAC engine cha nges for full-dupl ex operation are

as follows:

■Changes to the Transmit Deferral mechanism:

—Transmission is not deferred while receive is

active.

—The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits

is started when transmit activity for the first

packet ends, instead of when transmit and car-

rie r act ivity ends.

■The 4.0 µs carrier sense blinding period after a

transmission during which the SQE test normally

occurs is disabled.

■The collision indication input to the MAC engine is

ignored.

The internal PHY changes for full-duple x operation are

as follows:

■The collision detect (COL) pin is disabled.

■The SQE test function is disabled (10 Mbps).

■Loss of Carrier (LCAR) reporting is disabled.

Am79C973/Am79C975 79

PRELIMINARY

■PHY Control Register (ANR0) bit 8 is set to 1 if Auto-

Negoti ation is disabled.

Full-Duplex Link Status LED Support

The Am79C973/Am79C975 controller provides bits in

each of the LED Status registers (BCR4, BCR5, BCR6,

BCR7) to display the Full-Duplex Link Status. If the

FDLSE bi t (bit 8) i s set, a value of 1 wil l be sent to the

associated LEDOUT bit when in Full-Duplex.

10/100 PHY Unit Overview

The 10/100 PHY unit implements the complete physi-

cal layer for 10BASE-T and the Physical Coding Sub-

layer (PCS), Physical Medium Attachment (PMA), and

Physical Medium Dependent (PMD) functionality for

100BASE-TX. The 10/100 PHY implements Auto-

Negotiation allowing two devices connected across a

link segment to take maximum advantage of their capa-

bilities. A uto-Negotiation is performed using a modified

10BASE-T link integrity test pulse sequence as defined

in the IEEE 802.3u spe cif icat ion .

The internal 10/100 PHY consists of the following

functional blocks:

■100BASE-X Block including:

—Transmit and Receive State Machines

—4B/5B Encoder and Decoder

—Stream Cipher Scrambler and Descrambler

—Link Monitor State Machine

—Far End Fault Indication (FEFI) State Machine

—MLT-3 Encoder

—MLT-3 Decoder with adaptive equalization

■10BASE-T Block including:

—Manchester Encoder/Decoder

—Collision Detection

—Jabber

—Receive Polarity Det ect

—Waveshaping and Filtering

■Auto-Negotiation

■Physical Data Transceiver (PDX)

■PHY Control and Management

100BASE-TX Physical Layer

The func tions perform ed by the device include e ncod-

ing of 4-bit data (4B/5B), decoding of received code

groups ( 5B/4B), gen erating car r ier s ense a nd co llis ion

detect indications, serialization of code groups for

transmission, de-serialization of serial data from recep-

tion, mapping of transmit, receive, carrier sense, and

collision at the PHY/MAC interface, and recovery of

clock from the incoming data stream. It offers stream ci-

pher scrambling and descrambling capability for

100BASE-TX applications.

In the transmit data path for 100 Mbps, the 10/100 PHY

receives 4-bit (nibb le) wide data across the internal MII

at 25 millio n nibbles per secon d. For 100BASE - TX ap-

plications, it encodes and scrambles the data, serial-

izes it, and transmits an MLT-3 data stream to the

media via an isolation transformer.

The 10/100 PHY receives an MLT-3 data stream from

the network for 100BASE-TX. It then recovers the clock

from the data stream, de-serializes the data stream,

and descrambles/decodes the data stream (5B/4B) be-

fore presenting it to the internal MII interface.

100BASE-FX (Fiber Interface)

The Am79C973/Am79C975 device supports a

Pseudo-ECL (PECL) interface for Fiber applications.

The mode is enabled when BCR2 bit 14

(DISSCR_SFEX) is set to 1 and the Signal Detect pins

SDI± are connected to the optical transceiver.

For 100BASE-FX receive operation, the PHY unit re-

ceives a PECL data stream from the optical transceiver

and decodes the data stream. For transmit operation,

the PHY unit encodes and serializes the data and

transmits a pseu do-ECL data stream to the fiber optic

transceiver. See Figure 35.

The Fiber Interface (100BASE-FX) does not support

Auto-Negotiation, 10 BASE-FL, and data scrambling.

When the device is set to operate in PECL mode, the

100BASE-TX operation will be disabled.

10BASE-T Physical Layer

The 10/100 PHY incorporates 10BASE-T physical

lay er functions, including both clock recov ery (ENDEC)

and transceiver functions. Data transmission over the

10BASE-T medium requires an integrated 10BASE-T

MAU. The transceiver will meet the electrical require-

ments for 10BA SE-T as spec ified in IE EE 802.3i. Th e

transmit signal is filtered on the transceiver to reduce

harmonic content per IEEE 802.3i. Since filtering is

performe d in silicon , exter nal fil tering modules are not

needed. T he 10 /100 PHY re ce ives 10-Mb ps data f rom

the MAC across the inter nal MII at 2.5 million nibbles

per second f or 10BASE-T. It then Manchester encodes

the data before transmission to the network.

The RX+ pins are differential twisted-pair receivers.

When pr operly termi nat ed, e ach r ec ei ver will meet th e

electrical requirements for 10BASE-T as specified in

IEEE 802.3i. Each receiver has internal filtering and

does not require external filter modules. The 10/100

PHY receives a Manchester coded 10BASE-T data

stream from the medium. It then recovers the clock and

decodes the data.

80 Am79C973/Am79C975

PRELIMINARY

PHY/MAC Interface

The internal MII-compatible interface provides the data

path conn ection be tween the 10/1 00 PHY an d 10/100

Medi a Acce ss Con tro l (MA C) . The inter f ac e is compat -

ible with Clause 22 of the IEEE 802.3 standard specifi-

cation.

Transmit Process

The transmit process generates code-groups based on

TXD[3:0], TX_EN, TX_ER signals on the internal MII.

These co de-groups are transmit ted by the PDX block.

This process is also responsible for frame encapsula-

tion into a Physical Layer Stream, generating the colli-

sion signal based on whether a carrier is received

simultaneously with transmission and generating the

Carrier Sense (CRS) and Collision (COL) signals at the

internal MII. The transmit process is implemented in

complia nce with the transmi t state diagram as defined

in Clause 24 of the IEEE 802.3u specification. Figure

38 shows the transmit process.

Receive Process

The receive process passes to the internal MII a se-

quence of data nibbles derived from the incoming

code-groups. Each code-group is comprised of five

code-bits. This process detects channel activity and

then aligns the incoming code bits in code-group

boundaries f or subsequent data decoding. The receive

process is responsible for code-group alignment and

also generates the Carrier Sense (CRS) signal at the

internal MII. The receive process is implemented in

compliance with the receive state diagram as defined in

Clause 24 of th e IE EE 802 .3u spe ci fi ca tion . The False

Carrier Indication as specified in the standard is also

generated by this block, and communicated to the Rec-

onciliation layer. Figure 38 shows the receive process.

Internal PHY Loopback Path

As shown in Figure 35, the 10/100 PHY provides an

internal loopback path for system testing purposes.

The loopback option utilizes the serial loopback path

from the PDX ser i al outpu t to the P DX s er ia l in put an d

can be programmed via the LBK[1:0] bits in the PHY

Control/Status Register (ANR17).

F or the corresponding LBK setting, refer to the descrip-

tion for the PHY Control/Status Register.

Am79C973/Am79C975 81

PRELIMINARY

Figure 35. 100BASE-X Transmit and Receive Data Paths of the Internal PHY

Serial O/P

Symbol O/P

Loopback Paths

4B/5B Encoder

/J/K/ Insertion

/T/R/ Insertion

1 0

DISALIGN

PDX

1 0

Scrambler

Serializer

TX_EN

DISSCR

Deserializer

Clock Recovery RSCLK

PDX

SDI±1 0

1 0

5B/4B Decoder

Code Align

Descrambler

DISALIGN

LBK[1:0]=10

LBK[1:0]=11

DISSCR

1 0

RXD[3:0] & RX_ER

RX_DV

TXD[3:0] & TX_ER

PECL

Conversion MLT-3 Conversion with

Adaptive Equalization

and Baseline Restoration

RX±

PECL

Conversion MLT-3

Conversion

TX±

SDI±

Note: The 5-bit mode bypasses Encoder/Decoder and Scrambler/Descrambler logic.

Internal MII-Compatib le Interface

Internal MII-Compatible Interface

21510D-40

82 Am79C973/Am79C975

PRELIMINARY

Encoder

The encode r converts the 4-b it nibble from the MII into

five-bit code-groups, using a 4B/5B block coding

scheme. The encoder operates on the 4-bit data nibble

independent of the code-group boundary. The

100BASE-X physical protocol data unit is called a

stream. The encoding method used provides the fol-

lowing:

■Adequate codes (32) to provide for all data code-

groups (16) plus necessary control code-groups.

■Appropriate coding efficiency (4 data bits per 5

code-bits ; 80%) to imple ment a 100-M bps physical

layer interface on a 125-Mbps physical channel.

■Suffi ci ent transiti on d ens i t y to facilit ate cl ock r ecov-

ery (when not scrambled).

The code-group mapping is defined in Tab le 8.

Table 8. Encoder Code-Gr oup Mapping

TXD[3:0] Name PCS Code-Group Interpretation

0 0 0 0 0 1 1 1 1 0 Data 0

0 0 0 1 1 0 1 0 0 1 Data 1

0 0 1 0 2 1 0 1 0 0 Data 2

0 0 1 1 3 1 0 1 0 1 Data 3

0 1 0 0 4 0 1 0 1 0 Data 4

0 1 0 1 5 0 1 0 1 1 Data 5

0 1 10 6 0 1 1 1 0 Data 6

0 1 1 1 7 0 1 1 1 1 Data 7

1 0 0 0 8 1 0 0 1 0 Data 8

1 0 0 1 9 1 0 0 1 1 Data 9

1 0 1 0 A 1 0 1 1 0 Data A

1 0 1 1 B 1 0 1 1 1 Data B

1 1 0 0 C 1 1 0 1 0 Dat a C

1 1 0 1 D 1 1 0 1 1 Dat a D

1 1 1 0 E 1 1 1 0 0 Data E

1 1 1 1 F 1 1 1 0 1 Data F

Undefined I 1 1 1 1 1 IDLE; used as inter-Stream fill code

0 1 0 1 J 1 1 0 0 0 Start-of-Stream Deli mi ter, Pa rt 1 of 2; alw ays used

in pairs with K

0 1 0 1 K 1 0 0 0 1 Start-of-Stream D eli mi ter, Pa rt 2 of 2; alw ays used

in pairs with J

Undefined T 0 1 1 0 1 End-of-Stream Delimiter, Part 1 of 2; always used in

pairs with R

Undefined R 0 0 1 1 1 End-of-Stream Delimiter , Part 2 of 2; always used in

pairs with T

Undefined H 0 0 1 0 0 Transmit Error; used to force signaling errors

Undefined V 0 0 0 0 0 Invalid Code

Undefined V 0 0 0 0 1 Invalid Code

Undefined V 0 0 0 1 0 Invalid Code

Undefined V 0 0 0 1 1 Invalid Code

Undefined V 0 0 1 0 1 Invalid Code

Undefined V 0 0 1 1 0 Invalid Code

Undefined V 0 1 0 0 0 Invalid Code

Undefined V 0 1 1 0 0 Invalid Code

Undefined V 1 0 0 0 0 Invalid Code

Undefined V 1 1 0 0 1 Invalid Code

Am79C973/Am79C975 83

PRELIMINARY

Decoder

The decoder performs the 5B/4B decoding of the re-

ceived code- groups. The five bits of data are d ecode d

into four bits of nibble data. The decoded nibble is then

forwarded to the PCS Control block to be sent across

the internal MII to the MAC unit. The code-group de-

coding is shown in Table 9.

Table 9. Decoder Code-Group Mapping

PCS Code-Group Name RXD[3:0] Interpretation

1 1 1 1 0 0 0 0 0 0 Data 0

0 1 0 0 1 1 0 0 0 1 Data 1

1 0 1 0 0 2 0 0 1 0 Data 2

1 0 1 0 1 3 0 0 1 1 Data 3

0 1 0 1 0 4 0 1 0 0 Data 4

0 1 0 1 1 5 0 1 0 1 Data 5

0 1 1 1 0 6 0 1 10 Data 6

0 1 1 1 1 7 0 1 1 1 Data 7

1 0 0 1 0 8 1 0 0 0 Data 8

1 0 0 1 1 9 1 0 0 1 Data 9

1 0 1 1 0 A 1 0 1 0 Data A

1 0 1 1 1 B 1 0 1 1 Data B

1 1 0 1 0 C 1 1 0 0 Data C

1 1 0 1 1 D 1 1 0 1 Data D

1 1 1 0 0 E 1 1 1 0 Data E

1 1 1 0 1 F 1 1 1 1 Data F

1 1 1 1 1 I Undefined IDLE; used as Inter-Stream fill code

1 1 0 0 0 J 0 1 0 1 Start-of-Stream Delimiter, Part 1 of 2;

always used in pairs with K

1 0 0 0 1 K 0 1 0 1 Start-of-Stream Delimiter, Part 2 of 2;

always used in pairs with J

0 1 1 0 1 T Undefined End-of-St ream Delimiter , P art 1 of 2; al way s

us ed in pairs with R

0 0 1 1 1 R Undefined End- of-Stream Delimite r , P art 2 of 2; alw ay s

used in pairs with T

0 0 1 0 0 H Undefined Transmit Error; used to force signaling errors

0 0 0 0 0 V Undefined Invalid Code

0 0 0 0 1 V Undefined Invalid Code

0 0 0 1 0 V Undefined Invalid Code

0 0 0 1 1 V Undefined Invalid Code

0 0 1 0 1 V Undefined Invalid Code

0 0 1 1 0 V Undefined Invalid Code

0 1 0 0 0 V Undefined Invalid Code

0 1 1 0 0 V Undefined Invalid Code

1 0 0 0 0 V Undefined Invalid Code

1 1 0 0 1 V Undefined Invalid Code

84 Am79C973/Am79C975

PRELIMINARY

Scrambler/Descrambler

The 4B/5B encoded data has repetitive patterns which

result in peaks in the RF spectrum large enough to

keep the system from meeting the standards set by

regulatory agencies such as the FCC. The peaks in the

radiated si gna l ar e r edu ce d si gni fic an tly by scram bling

the transmitte d signal. S cramblers add the ou tput of a

random generator to the data signal. The resulting sig-

nal has fewer repetitive data patterns.

After reset, the scrambler seed will be set to the PHY

address value to help improve the EMI performance of

the device.

The scrambled data str eam is descrambled, at the re-

ceiver, by adding it to the output of another random

generator. The receiver’s random generator has the

same functi on as the transmi tter’s random generator.

Link Monitor

The Link Monitor process is responsible for determin-

ing whether the underlying receiv e channel is providing

reliable data. This process takes advantage of the con-

tinuous indi catio n of sig nal detect by the PM D (PDX &

MLT-3). The process sets the link_status to FAIL when-

ever signal_status is OFF. The link is reliable whenev er

the signal_status has been continuously ON for 330 -

1000 ms. The implementation is in compliance with

Clause 24 of the IEEE 802.3u specification.

The 10BASE-T Link Monitor monitors the line for link

pulses, while the 100BASE-T Link Monitor ex pects 100

Mbps idle signal s. When the Link Moni tor detects bot h

10 Mbps a nd 100 Mbps si gna ls, a s tate c al led Parallel

Fault is entered, where the Link Monitor simply halts

and fails to repor t a link. This condition can be caused

by spurious noise on the network line. Consult the IEEE

802.3u spe cific ation for more informa tio n. The Parallel

Fault Detect condition is displayed in Register 6, bit 4.

The current link status of this port is displayed In the

PHY Management Status Register (Register 1, bit 2).

Far End Fault Generation and Detection

Far End Fault Generation and Detection is imple-

mented in th e 10/10 0 PH Y for 100BAS E-TX over ST P

and 100BASE-FX. This block generates a sp ecial Far

End Fault indi cation to its far end peer. This indica tion

is generated only when an error condition is detected

on the receive channel. When Far End Fault Indication

is detect ed from the far end peer, this block will ca use

the link monitor to transition the link_status to FAIL.

This action in-turn will cause IDLE code-group bits to

be automatically transmitted. This is necessar y to re-

establish communication when the link is repaired. The

impleme ntation is i n com pliance wit h the Cl ause 24 o f

IEEE 802.3u specification.

Far End Fault Indication can be initialized using the

PHY Control/Status Register (ANR17, bit 10).

MLT-3 and Adaptive Equalization

This block is responsi bl e for conver ting the NRZI dat a

stream from the PDX block to a currently sourced

MLT-3 encoded data stream. The effect of MLT-3 is the

reduction of energ y on the media (TX cable) in the crit-

ical frequency range of 20 MHz to 100 MHz. The re-

ceive section of thi s block is respons ible for equal izin g

and amplifying the received data stream and link detec-

tion. The adaptive equalizer compensates for the am-

plitude and phase distortion due to the cable.

MLT-3 is a tri-level signal. All transitions are between

0 V and +1 V or 0 V and -1 V. A transition has a logical

valu e of 1 a nd a lack of a transiti on has a lo gi ca l value

of 0. The benefit of MLT-3 is that it reduces the maxi-

mum frequency over the data line. The bit rate of TX

data is 125 Mbps. The maximum frequency (using

NRZI) is half of 62.5 MHz. MLT-3 reduces the maxim um

frequency to 31.25 MHz.

The impleme ntation of this block is in comp liance wit h

ANSI X3 712 TP-PMD/ 312, Revision 2.1 that defi nes a

125-Mbps, full-duple x signalling for twisted pair wiring.

A data signal stream follo wing MLT-3 rules is illustrated

in Figure 36. The data stream is 1010101.

The TX± drivers convert the NRZI serial output to

MLT-3 form at. Th e RX± rec eivers conver t the recei ved

MLT-3 signals to NRZI. When the TX port of the 10/100

PHY is connected as in Figure 37, the transmit and re-

ceive signals will be co mpliant with IEE E 802.3u Se c-

tion 25. T he required si gnals (MLT-3) are describe d in

detail in ANSI X3.263:1995 TP-PMD Revision 2.2

(1995).

The 10/100 PHY provides on-chip filtering. External fil-

ters are not required for either the transmit or receive

signals.

Am79C973/Am79C975 85

PRELIMINARY

Figure 36. MLT-3 Waveform

Serializer/Deserializer and Clock Recovery

The Physical Data Transceiver (PDX) is a CMOS all

digital c ore that is used in the 10/100 PH Y. It employs

new circuit techniques to achieve clock and data recov-

ery.

Tradi tio nal ly, Ph as e- Locked-Loops (PLL s) ar e u se d for

the purpose of clock recovery in data communication

areas. There are both analog and digital v ersions of the

PLL components such as phase detector, filter, and

charge pu mp. A traditional PL L always contains a volt-

age-controlled oscillator (VCO) to regenerate a clock

which is synchronized in frequency to and aligned in

phase with the received data.

The PDX e mpl oys techniqu es that ar e significa ntl y dif-

ferent from traditional PLLs. Not only are the control

functions completely digital, the VCO function is also

replaced by a proprietary delay time ruler technique.

The result is a highly integratible core which can be

manufactured in a standard digital CMOS process.

To transmit, the PDX accepts 4B/5B encoded data

symbols from the scrambler. The 5-bit symbol is

clocked into the PDX by the rising edge of the 25-MHz

clock, serialized and converted to NRZI format. The

NRZI data is delivered to the PECL transceiver or MLT3

transceiver . The output of either of the two transceiv ers

goes to the TX± pair.

The PDX uses a 25-MHz clock as the frequency and

phase reference to generate the serial link data rate.

The external clock source must be continuous. All of

the inter nal logi c of the PDX r uns on an inter nal clock

that is derived from the external reference source. The

PDX’s clock multiplier is referenced to the rising edges

of the 25-MHz clock only.

In order to gen erate the ser ial output wave fo rm s con-

forming to the specifications, the external reference

clock must meet 100BASE-X frequency and stability

requir ements. U nder nor mal cond ition s, the freq uency

of the 25-M Hz clo ck multiplie d by 5 must be withi n the

100BASE-X specified 100 ppm of the received data for

the PDX to operate optimally.

Note: The 100 ppm is the tolerance of the crystal-con-

trolled source.

The TX± serial output typically contains less than

0.4 ns peak-to-peak jitter at 125 Mbaud.

Receiving fr om th e physical med ium t hr oug h t he PM D

device, the PDX accepts encoded PECL NRZI signal

levels at the RX± inputs. The receiver circuit recovers

data from the input stream by regenerating clocking in-

formation embedded in the serial stream. The recov-

ered clock is called RSCLK (an internal signal). The

PDX then clocks the unframed symbol (5 bits) to the

descrambler interface on the falling edge of RSCLK.

The PDX receiver uses advanced circuit techniques to

extract encoded clo ck inform atio n fr om the s erial input

stream an d recove rs the data. Its op erating freq uency

is established by the reference clock at 25 MHz. The

PDX is capable of recovering data correctly within

±1000 ppm of the 25-MHz clock signal (which e xceeds

the frequency range defined by the 100BASE-X speci-

fication). The 100BASE-X 4B/5B encoding scheme en-

sures run-length limitation and adequate transition

density of the encoded data stream, while TP-PMD

achiev es this on a statistical basis through data scram-

bling. The PDX clock recovery circuit is designed to tol-

erate a worst-case run-length of 60-bits in order to

function correc tly with bo th fiber- optic and twi sted-pa ir

PMDs.

The PDX receiver has input jitter tolerance characteris-

tics that meet or exceed the recommendations of Phys-

ical Layer Medium Dependent (PMD) 100BASE-X

document. Typically, at 125 Mbaud (8 ns/bit), the peak-

to-peak Duty-Cycle Distortion (DCD) tolerance is

1.4 ns, the peak -to-peak Data Dependent Jitter (DDJ)

tolerance i s 2.2 ns, and the pe ak-to- peak Random Jit-

ter (RJ) tolerance is 2.27 ns. The total combined peak-

to-peak jitter tolerance i s typically 5 ns with a bit er ror

rate (BER) better than 2.5 x 10-10.

Medium Dependent Interface

The Am79C973/Am79C975 device connects directly to

low cost magnetics modules for interface to twisted pair

media (U TP an d/or STP) . The TX± and RX± pins pro-

vide the interface for both 10BASE-T and 100BASE-TX

allowing the use of a 1:1.41 (transmit) and 1:1 (receive)

transformer with single primary and secondary wind-

ings. No filtering is required in the magnetics module.

Refer to Figure 37 for recommended termination.

21510D-41

MLT-3

1010101

8 ns

86 Am79C973/Am79C975

PRELIMINARY

Figure 37. TX± and RX± Termination

10BASE-T Block

The 10BASE-T block consists of the following sub-

blocks:

—Transmit Process

—Receive Process

—Interface Status

—Collision Detect Function

—Jabber Function

—Reverse Polarity Detect

Refer to Figure 38 for the 10BASE-T block diagram.

Twisted Pair Transmit Function

Data transmission over the 10BASE-T medium re-

quires us e o f the integrated 10 BA SE -T MAU and us es

the differential driver circuitry on the TX± pins.

TX± is a differenti al twisted -pair dr iver. When proper ly

ter minated, TX± will me et the trans mitter elec trical re-

quirements for 10BASE-T transmitters as specified in

IEEE 802.3, Section 14.3.1.2. The load is a twisted pair

cable that meets IEEE 802.3, Section 14.4.

The TX± signal is filtered on the chip to reduce har-

monic content per Section 14.3.2.1 (10BASE-T). Since

filter ing is performed in s ilic on, TX ± c an be conne cte d

directly to a standard transformer. External filtering

modules are not needed.

Twisted Pair Receive Function

The RX+ port is a differential twisted-pair receiver.

When pro perly ter minated, th e RX+ port will meet the

electrical requirements for 10BASE-T receivers as

specified in IEEE 802.3, Section 14.3.1.3. The receiver

has internal filtering and does not require e xternal filter

modules or common mode chokes.

Signals appearing at the RX± differential input pair are

routed to the internal decoder. The receiver function

meets the propagation delays and jitter requirements

specified by the 10BASE-T Standard. The receiver

squelc h leve l drop s to half i ts thre shold value after un-

squelch to allow reception of minimum amplitude sig-

RX+

RX–

SDI+

SDI–

TX+

TX–3.3 V

RX+ (3)

TX+ (1)

RX– (6)

TX– (2)

RJ45

Connector

Isolation

Transformer with

common-mode

chokes

50 Ω

2 K Ω

1 K Ω

.01 µF

0.001 µF

2KV

75 Ω75 Ω75 Ω

75 Ω

* 1:1.414 *

* 1:1 *

(8)

(7)

(5)

(4)

(chassis ground)

21510D-42

Notes:

1. The isolation transformers include common-mode chokes.

2. Consult magnetics vendors for appropriate termination schemes.

49.9 Ω, 1%

0.1 µF

49.9 Ω, 1%

Am79C973/Am79C975 87

PRELIMINARY

nals and to mitigate carrier fade in the event of worst

case signal attenuation and crosstalk noise conditions.

Figure 38. 10BASE-T Transmit and Receive Data

Paths

Twisted Pair Interface Status

The Am79C973/Am79C975 device will power up in the

Link Fail state. The Auto-Negotiation algorithm will

apply to allow it to enter the Link Pass state.

In the Link P ass state, receive activity which passes the

pulse width /am pli tud e req uire men ts of the RX ± in puts,

will cause the PCS Control block to assert Carrier

Sense ( CRS) signal at t he inter nal MII interface. Colli-

sion would cause the PCS Control block to assert Car-

rier Sense (CRS) and Collision (COL) signal at the

internal MII. In the Link Fail state, this block would

cause the PCS Control block to de-assert Carrier

Sense (CRS) and Colli sion (COL) .

In jabber detect mode, this block would cause the PCS

Control block to assert the COL pin at the MII, and

allow the PCS Cont rol block to assert or de-ass er t th e

CRS pin to indicate the current state of the RX± pair. If

there is no receive activity on RX±, this block would

cause the PCS Control block to assert only the COL pin

at the internal MII. If there is RX± activity, this block

would cause the PCS Control block to assert both COL

and CRS at the internal MII.

Collision Detect Function

Simultaneous activity (presence of valid data signals)

from both the internal encoder transmit function and

the twisted pair RX± pins constitutes a collision,

thereby causing the PCS Control block to assert the

COL pin at the internal MII.

Jabber Function

The Jabber function inhibits the 10BASE-T twisted pair

transmit f unction o f the Am79 C973/Am79C 975 device

if the TX± circuits are active for an excessive period

(20-150 ms). This prevents one port from disrupting the

network due to a stuck-on or faulty transmitter condi-

tion. If the maximum transmit time is exceeded, the

data path through the 10BASE-T transmitter circuitry is

disabled (al though Link Test pulses will continue to be

sent). The PCS Control bloc k also asserts the COL pin

at the internal MII and sets the Jabber Detect bit in

the MENDE C stops, an unjab ti me of 250-750 ms will

elapse before this block causes the PCS Con trol block

to de-assert the COL indication and re-enable the

transmit circuitry.

When jabber is detected, this block will cause the PCS

control block to assert the CO L p in an d a llow the PCS

Control block to asse rt or de-assert the CRS pi n to in-

dicate the current state of the RX± pair. If there is no re-

ceive activity on RX±, this block causes the PCS

Control block to assert only the COL pin at the internal

MII. If there is RX± activity, this block will cause the

PCS Control block to assert both CO L and CRS at the

internal MII.

Reverse Polarity Detect

The polarity f or 10BASE-T signals is set by reception of

Normal Link Pulses (NLP) or packets. Polarity is

locked, however, by incoming packets only. The first

NLP received when trying to bring the link up will be ig-

nored, but it will set the polarity to the correct state. The

reception of two consecutive packets will cause the po-

larity to be locked, based on the polarity of the ETD. In

order to change the polarity once it has been locked,

the link must be brought down and back up again.

Auto-Negotiation

The obje ct o f the Auto-Nego tia tio n func ti on i s to deter-

mine the abilities of the devices sharing a link. After ex -

changing abilities, the Am79C973/Am79C975 device

and remote link partner device acknowledge each

other and make a choice of which advertised abilities to

suppor t. The Auto-Negotiation function facilitates an

ordered resolution between exchanged abilities. This

exchange allows both devices at eit her end of the link

to take maximum advantage of their respective shared

abilities.

Clock Data

Manchester

Encoder

Clock Data

Manchester

Decoder

Squelch

Circuit

RX Driver

RX±TX±

TX Driver

21510D-43

88 Am79C973/Am79C975

PRELIMINARY

The Am79C973/Am79C975 device implements the

transmit and receive A uto-Negotiation algorithm as de-

fined in IEEE 802.3u, Section 28. The Auto-Negotiation

algorithm uses a burst of link pulses called Fast Link

Pul se s ( FL Ps ) . Th e bur st of li nk pul se s are spaced be-

tween 55 a nd 140 µs s o as to be ignored by the stan-

dard 10BASE-T algorithm. The FLP burst conveys

information about the abilities of the sending device.

The receiver can accept and decode an FLP burst to

learn the abilities of the sending device. The link pulses

transmitted conform to the standard 10BASE-T tem-

plate. The device can perform auto-negotiation with re-

verse polarity link pulses.

The Am79C973/Am79C975 device uses the Auto-Ne-

gotiation algor ithm to select the type connection to b e

established according to the following priority:

100BASE-TX full duplex, 100BASE-T4, 100BASE-TX

half-dup lex, 10BASE- T ful l dup lex, 10BAS E-T h alf-du-

ple x. The Am79C973/Am79C975 de vice does not sup-

port 100BASE-T4 connections.

The Auto-Negotiation algorithm is initiated when one or

the following events occurs: Auto-Negotiation enable

bit is set, or rese t, or soft reset, or transit ion to link fail

state (when Auto-Negotiation enable bit is set), or Auto-

Negotiation restart bit is set. The result of the Auto-Ne-

gotiation process can b e read from the s tatus register

(Summary Status Register, ANR24).

The Am79C973/Am79C975 device supports Parallel

Detection for remote legacy devices which do not sup-

por t the Auto-Neg otiation algor it hm. In the case that a

100BASE-TX only device is connected to the remote

end, the Am79C973/Am79C975 device will see scram-

bled idle symbols and establish a 100BASE-TX only

connection. If NLPs are seen, the Am79C973/

Am79C975 device will establish a 10BASE -T connec-

tion.

By default, the link partner must be at least 10BASE-T

half-duplex capable. The Am79C973/Am79C975 con-

troller can automatically negotiate with the network and

yield the highest performance possible without soft-

ware support. See the section on Network Port Man-

ager for more details.

A uto-Negotiation goes further by providing a message-

based communication scheme called, Ne xt P ages, be-

fore connecting to the Link Partner. This feature is not

supported in the Am79C973/Am79C975 device unless

the DANAS (BCR32, bit 10) is selected.

Soft Reset Function

The PHY Control Register (ANR0) incorporates the

soft reset function (bit 15). It is a read/write register and

is sel f-clear ing. Wr iti ng a 1 to thi s bit causes a so ft re-

set. When read, the register returns a 1 if the soft reset

is still being performed; otherwise, it is cleared to 0.

Note that the register can be polled to verify that the

soft reset has terminated. Under normal operating con-

ditions, soft reset will be finished in 150 clock cycles.

Soft rese t only rese ts the 10 /100 PHY un it registe rs to

default value s (som e register bits retain their pr evi ous

v alues). Refer to the individual registers for v alues after

a soft reset. Soft reset does not reset the PDX block nor

the management interface.

Soft reset is required when changing the value of the

SDISSCR (scrambling/descrambling) bit. After soft

reset, the register will retain the prev ious value written.

External Address Detection Interface

The EADI is provided to allow external address filtering

and to provide a Receive Frame Tag word for propri-

etary routing information. It is selected by setting the

EADISEL bit in BCR2 to 1. This feature is typically uti-

lized by terminal servers, bridges and/or router prod-

ucts. The EADI interface can be used in conjunction

with external logic to capture the packet destination ad-

dress as it arrives at the Am79C973/Am79C975 con-

troller , to compare the captured address with a table of

stored ad dresses or id entifiers, and then to dete rmine

whether or not the Am79C973/Am79C975 controller

should accept the packet.

If an address match is detected by comparison with ei-

ther the Physical Address or Logical Address Filter reg-

isters contained within the Am79C973/Am79C975

controller or the frame is of the type 'Broadcast', then

the frame wil l be accepted r egardless o f the conditio n

of EAR. When the EADISEL bit of BCR2 is set to 1 and

the Am79C973/Am79C975 controller is programmed

to promiscuous mode (PROM bit of the Mode Register

is set to 1) , then all inc oming frames wil l be acce pted,

regardless of any activity on the EAR pin.

Internal address match is disabled when PROM

(CSR15, bit 15) is cleared to 0, DRCVBC (CSR 15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the

Logical Address Filt er registers (C SR8 to CSR11) are

programmed to all zeros.

When the EADISEL bit of BCR2 is set to 1 and internal

address match is disabled, then all incoming frames

will be accepted by the Am79C973/Am79C975 control-

Table 10. Auto-Negotiation Capabilities

Network Speed Physical Network Type

200 Mbps 100BASE-X, Full Duplex

100 Mbps 100BASE-T4, Half Duplex

100 Mbps 100BASE-X, Half Duplex

20 Mbps 10BASE-T, Full Duplex

10 Mbps 10BASE-T, Half Duplex

Am79C973/Am79C975 89

PRELIMINARY

ler, unless the EAR pin becomes active during the first

64 bytes of the frame (excluding preamble and SFD).

This allows external address lookup logic approxi-

mately 5 8 byte time s after the last d es tin ati on add re ss

bit is available to generate the EAR signal, assuming

that the Am79C973/Am79C975 controller is not config-

ured to ac ce pt runt p a ckets. The EAD I l ogi c onl y sa m-

ples E AR from 2 bi t times afte r SF D unti l 512 bi t ti mes

(64 bytes) after SFD . The frame will be accepted if EAR

has not bee n asserted dur ing th is win dow. In order for

the EAR pin to be function al in full-du pl ex mode, FDR-

PAD bit (BCR9, bit 2) needs to be set. If Runt Packet

Accept (CSR124, bit 3) is enabled, then the EAR signal

must be generated prior to the 8 bytes received, if

frame rejecti on is to be guaranteed . Runt p acket sizes

could be as shor t as 12 by te times (assum ing 6 bytes

for source address, 2 bytes for length, no data, 4 bytes

for FCS) after the last bit of the desti nation address is

available. EAR must have a pulse width of at least 110

ns.

The EADI outp uts continue to pr ovide data throug hout

the reception of a frame. This allows the ex ter na l logic

to captur e fram e head er infor mation to determine pro-

tocol type, interne twor king infor matio n, and oth er use-

ful data.

The EADI interface will operate as long as the STRT bit

in CSR0 is set, even if the receiver and/or transmitter

are disabled by software (DTX and DRX bits in CSR15

are set). This conf iguration is useful as a semi-p ower-

down mode in that the Am79C973/Am79C975 co ntrol-

ler will not perfor m any power-consumin g DMA op era-

tions. However, external circuitry can still respond to

control frames on the network to facilitate remote node

control. Table 11 summarizes the operation of the EADI

interface.

External Address Detection Interface: MII Snoop

Mode

The MII S noop mode provides al l neces sar y data an d

clock signals needed for the EADI interface. Data for

the EADI is the RXD[3:0] receive data provided to the

internal MII. The us er will recei ve the data as 4 bit nib-

bles. RX_CLK is provided to allow clocking of the

RXD[3:0] receive nibble stream into the external ad-

dress detection logic. The RXD[3:0] data is synchro-

nous to the rising edge of the RX_CLK. The data

arrives in nibbles and can be at a rate of 25 MHz or 2.5

MHz.

The assertion of SFBD is a signal to the external ad-

dress dete ction logic that the SFD has been detected

and that the first valid data nibble is on the RXD[3:0]

data bus. The SFBD signal is delayed one RX_CLK

cycle from the above definition and actually signals the

start of valid data. In order to reduce the amount of

logic external to the Am79C973/Am79C975 controller

for multiple addr ess dec oding sys tems, the SF BD sig-

nal will go HIGH at eac h new byte boundary wit hin the

packet, subsequent to the SFD. This eliminates the

need for externally supplying byte framing logic.

The EAR pin should be driven LOW by the e xternal ad-

dress comparison logic to reject a frame.

External Address Detection Interface: Receive

Frame Tagging

The Am79C973/Am79C975 controller supports re-

ceive frame tagging in MII Snoop mode. The receive

frame taggi ng implementatio n is a two-wire c hip inter-

face in addition to the existing EADI.

The Am79C973/Am79C975 controller supports up to

15 bits of receive frame tagging per frame in the receive

frame status (RFRTAG). The RFRTAG bits are in the

receive frame status field in RMD2 (bits 30-16) in 32-bit

software mode. The receive frame taggin g is not sup-

por ted in the 16-bi t software mode. The RFRTAG field

are all zeros when either the EADISEL (BCR2, bit3) or

the RXFRTAG (CSR7, bit 14) are set to 0. When

EADISEL (BCR2, bit 3) and RXFRTAG (CSR7, bit 14)

are set to 1, then the RFRTAG reflects the tag word

shifted in during that receive frame.

In the MII Sn oop mode, the two -wire interface will use

the MIIRXFRTGD and MIIRXFRTGE pins from the

EADI interface. These pins will provide the data input

and data input enable f or the receive frame tagging, re-

spectively. These pins are normally not used during the

MII operation.

The receive frame tag register is a shift register that

shifts data in MSB first, so that less than the 15 bits al-

loca ted m ay be utilized by the user. The upp er bit s no t

utilized will return zeros. The receive fr ame tag register

is set to 0 in between reception of frames. After receiv-

ing SFBD indication on the EADI, the user can start

shifting data i nto the rece ive tag regis ter u ntil o ne net-

work clock period before the Am79C973/Am79C975

controller receives the end of the current receive frame.

In the MII Snoop mode, the user must see the RX_CLK

to dri ve the synchrono us receive frame tag d ata inter-

face. After receiving the SFBD indication, sampled by

the rising edge of the RX_CLK, the user will drive the

data inp ut and the da ta inp ut en able syn chro nou s wit h

the rising edge of the RX_CLK. The user has until one

network clock period before the deassertion of the

Table 11. EADI Operations

PROM EAR Required

Timing Received

Frames

1 X No timing

requirements All rece ived frames

0 1 No timing

requirements All received frames

0 0 Low for two bit

times plus 10 ns

Fr ame rejected if in

address match

mode

90 Am79C973/Am79C975

PRELIMINARY

RX_D V to input the data into the receive frame tag reg-

ister. At the deassertion of the RX_DV, the receive

frame tag register will no longer accept data from the

two-wire interface. If the user is still driving the data

input e nable pin, erro neous or cor rupted data may r e-

side in the receive frame tag register. See Figure 39.

Figure 39. Receive Frame Tagging

Expansion Bus Interface

The Am79C 973/Am79C9 75 controlle r contains an Ex -

pansion Bus Interf ace that supports Flash and EPROM

devices as boot devices, as well as provides read/write

access to Flash or EPROM.

The signal AS_EBOE is provided to strobe the upper 8

bits of the address into an external ‘374 (D flip- flop) ad-

dress latch. AS_EBOE is asserted LOW during

EPROM/Flash read o peratio ns to c ontrol the OE inpu t

of the EPROM/Flash.

The Expansion Bus Address is split into two different

buses, EBUA_EBA[7:0] and EBDA[15:8]. The

EBU A_EBA[7:0] provides the least and the most signif-

icant address byte. When accessing EPROM/Flash,

the EBUA_EBA[7:0] is strobed into an external ‘374 (D

flip-flop) address latch. This constitutes the most signif-

icant portion of the Expansion Bus Address. For

EPROM/Flash accesses, EBUA_EBA[7:0] constitutes

the remaining least significant address byte. For byte

oriented EPROM/Flash accesses, EBDA[15:8] consti-

tutes the upper or middle address byte. EBADDRU

(BCR29, bits 3-0) should be set to 0 when not used,

since EBADDRU constitutes the EBUA por tion of the

EBU A_EBA address byte and is strobed into the e xter-

nal ’374 addre ss latch.

The signal EROMCS is conn ected to the CS/CE input

of the EPROM/Flash. The signal EBWE is connected

to the WE of the Flash device.

The Expansion Data Bus is configured f or 8-bit byte ac-

cess during EPROM/Flash accesses. During EPROM/

Flash acces ses, EBD[7:0 ] provides th e data byte. See

Figure 40, Figure 41, and Figure 42.

Expansion ROM - Boot Device Access

The Am79C973/Am79C975 controller supports

EPROM or Flash as an Expansion ROM boot device.

Both are configured using the same methods and op-

erate the same. See the previous section on Expansion

ROM transfers to get the PCI timing and functional de-

scription of the transfer method. The Am79C973/

Am79C975 controller is functionally equivalent to the

PCnet-P CI II c ontrol le r with E xp ansio n ROM. See Fi g-

ure 41 and Figure 42.

The Am79C 973/Am 79C975 co ntrol ler will al way s read

four b ytes f or e v ery host Expansion ROM read access.

The in terface to the Exp ansion Bus run s synchr onous

to the PCI bus interface clock. The Am79C973/

Am79C975 controller will start the read operation to the

Expans ion ROM by dr iving the upper 8 bits of th e Ex-

pansion ROM address on EBUA_EBA[7:0]. One-half

clock later, AS_EBOE goes high to allow registering of

the upper add re ss bit s exter nal ly. The uppe r po rtion of

the Expansion ROM address will be the same for all four

byte read cyc le s. AS_EB OE is driven high for one-hal f

clock, EBUA_EBA[ 7:0] are driven with the uppe r 8 bits

of the Expansion ROM address for one more clock cycle

after AS_EBOE goes low. Next, the Am79C973/

Am79C975 controller star ts dr iving the lower 8 bits of

the Expansion ROM address on EBUA_EBA[7:0].

The time that the Am79C973/Am79C975 controller

waits for data to be valid is programmable. ROMTMG

(BCR18, bits 15-12) defines the time from when the

Am79C973/Am79C975 controller drives

EBUA_EBA[ 7:0] with th e lower 8 bits of the E xp ansio n

ROM address to when the Am79C973/Am79C975 con-

troller latches in the data on the EBD[7:0] inputs. The

cles. When ROMTMG is set to nine (the default value),

EBD[7:0] is sampled with the next rising edge of CLK

ten clock cy cles a fter EBUA_EBA [7:0] was dr iven with

a new address value. The clock edge that is used to

sample th e data is also th e clock edge that generates

the next Expansion ROM address. All four bytes of Ex-

RX_CLK

RX_DV

MIIRXFRTGE

MIIRXFRTGD

SF/BD

21510D-44

Am79C973/Am79C975 91

PRELIMINARY

pansion ROM data are stored in holding registers. One

clock cycle after the last data byte is available, the

Am79C973/Am79C975 controller asserts TRDY.

The access time for the Expansion ROM or the EB-

DATA (BCR30) device (tACC) during read operations

can be calculated by subtracting the clock to output

delay for the EBUA_EBA[7:0 ] outputs (tv_A_D) and by

subtracting the input to clock setup time for the

EBD[7:0] inputs (ts_D) from the time defined by

ROMTMG:

tACC = ROMTMG * CLK period *CLK_FAC - (tv_A_D) -

(ts_D)

Figure 40. Flash Configuration for the Expansion Bus

The access time for the Expansion ROM or for the EB-

DATA (BCR30) device (tACC) during write operations

can be calculated by subtracting the clock to output

delay for the EBUA EBA[7:0] outputs (tv_A_D) and by

adding the input to clock setup time f or Flash/EPRO in-

puts (ts_D) from the time defined by ROMTMG:

tACC = ROMTMG * CLK period * CLK_FAC - (tv_A_D) -

(ts_D)

The timing diagram in Figure 43 assumes the default

programming of ROMTMG (1001b = 9 CLK). After

reading the first byte, the A m79C973/Am 79C975 c on-

troller reads in three more bytes by incrementing the

lower portion of the ROM address. After the last byte is

strobed in, TRDY will be asser ted on clock 50. When

the host tries to pe rform a burst read of the Exp ansio n

ROM, the Am79C973/Am79C975 controller will dis-

connect the access at the second data phase.

The hos t must pr ogram th e Expansion ROM Base A d-

dress register in the PCI configuration space before the

first access to the Expansion ROM. The Am79C973/

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

AS_/EBOE

A[15:8]

A[7:0]

DQ[7:0]

Am79C973

'374

D-FF

FLASH

EROMCS

A[23:16]

21510D-45

92 Am79C973/Am79C975

PRELIMINARY

Am79C975 controller will not react to any access to the

Expansion ROM until both MEMEN (PCI Command reg-

ister, bit 1) and ROMEN (PCI Expansion ROM Base

Address register , bit 0) are set to 1. After the Expansion

ROM is enabled, the Am79C973/Am79C975 controller

will claim all memory read accesses with an address

between ROMBASE and ROMBASE + 1M - 4 (ROM-

BASE, PCI Expansion ROM Base Address register , bits

31-20). The address output to the Expansion ROM is

the offset from the address on the PCI bus to ROM-

BASE. The Am79C973/Am79C975 controller aliases all

accesses to the Expansion ROM of the command types

Memor y Read Multiple and Memory Read Line to the

basic Memory Read command.

Figure 41. EPROM Only Configuration for the Expansion Bus (64K EPROM)

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

EROMCS

A[15:8]

A[7:0]

DQ[7:0]

Am79C973

EPROM

AS_EBOE 21510D-46

Am79C973/Am79C975 93

PRELIMINARY

Figure 42. EPROM Only Configuration for the Expansion Bus (>64K EPROM)

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given to

the PCI Memory Mapped I/O Base Address register,

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress regi ster to a value that preven ts the Am79C973 /

Am79C975 controller from claiming any memory cy-

cles not intended for it.

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55h (byte 0) and AAh (byte 1).

Direct Flash Access

Am79C973/Am79C975 controller supports Flash as an

Expansion ROM device, as well as providing a read/

write data path to the Flash. The Am79C973/

Am79C975 controller will support up to 1 Mbyte of

Flash on the Expansion Bus. The Flash is accessed by

a read or write to the Expansion Bus Data port

(BCR30). The user must load the upper address

EPADDRU (BCR 29, bits 3-0) and then set the FLASH

(BCR29, bit 15) bit to a 1. The Flash read/write utilizes

the PCI clock instead of the EBCLK during all ac-

cesses. EPADDRU is not needed if the Flash size is

64K or less, but still must be programmed. The user will

then load the low er 16 bits of address, EPADDRL (BCR

28, bits 15-0).

Flash/EPROM Read

A read to the Expansion Bus Data Port (BCR30) will

start a read cycle on the Expansion Bus Interface . The

Am79C973/Am79C975 controller will drive

EBU A_EBA[7:0] with the most significant address byte

at the same time the Am79C973/Am79C975 controller

will drive AS_EBOE high to strobe the address in the

ext er na l ‘374 (D flip-flop). On the next clock, the

Am79C973/Am79C975 controller will drive EBDA[15:8]

and EBUA_EBA[7:0] wit h the middle and least signifi-

cant address bytes.

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

EROMCS

A[15:8]

A[7:0]

DQ[7:0]

Am79C973

EPROM

AS_EBOE

'374

D-FF A[23:16]

21510D-47

94 Am79C973/Am79C975

PRELIMINARY

Figure 43. Expansion ROM Bus Read Sequence

Figure 44. Flash Read from Expansion Bus Data Port

The EROMCS is driven low for the val ue ROMTMG +

1. Figure 44 assumes that ROMTMG is set to nine.

EBD[7:0] is sampled with the next rising edge of CLK

ten clock cy cles af ter E BUA _EBA [7:0] was d r iven with

a new address value. This PCI slave access to the

Flash/EP ROM will res ult in a retry for the ver y fi rst ac-

cess. Subsequent accesses may give a retry or not, de-

pending on whether or not the data is present and valid.

The access time is dependent on the ROMTMG bits

(BCR18, bits 15-12) and the Flash/EPROM. This ac-

cess mechanism differs from the Expansion ROM ac-

cess mechanism since only one byte is read in this

manner, instead of the 4 bytes in an Expansion ROM

access. T he PCI bus will no t be held dur ing access es

through the Expansion Bus Data Port. If the LAAINC

(BCR29, bit 15) is set, the EBADDRL address will be

incremented and a continuous series of reads from the

Expansion Data Port (EBDATA, BCR30) is possible.

The add ress i ncremen tor wi ll rol l over without war nin g

and without incrementing the upper address EBAD-

DRU.

The Flash write is almost the same procedure as the

read access, except that the Am79C973/Am79C975

controller will not drive AS_EBOE low. The EROMCS

and EBWE are driven low for the value ROMTMG

again. The write to the FLASH port is a posted write

and will not resu lt in a r etr y t o the PCI unless the host

tries to write a new value before the previous write is

complete, then the host will experience a retry . See Fig-

ure 45.

CLK

EBUA_EBA [7:0]

Latched Address

EBDA [15:8]

EBD

AS_EBO

EROMCS

FRAME

IRDY

TRDY

DEVSEL

510 15 20 25 30 35 40 45 50 55 60 66

A[7:2], 0, 1A[7:2], 0, 0

A[19:16]

A[7:2], 1, 0 A[7:2], 1, 1

21510D-48

21510D-49

EBUA_EBA[7:0]

EBD[7:0]

AS_EBOE

EROMCS

EBUA[19:16]

EBDA[15:8]

EBA[7:0]

CLK

1 2 345678910 11 12 13

Am79C973/Am79C975 95

PRELIMINARY

Figure 45. Flash Write from Expansion Bus Data Port

AMD Flash Programming

AMD’s Flash products are programmed on a byte-by-

byte basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed

by the program set-up command and data write cycles.

Addresses are latched on the falling edge of EBWE

and the data is latched on the rising edge of EBWE.

The rising edge of EBWE begins programming.

Upon executing the AMD Flash Embedded Program

Algorithm command sequence, the Am79C973/

Am79C975 c ontrolle r is not req uired to provide fur th er

control s or tim in g. T he AM D F la sh produ ct will compli-

ment EBD[7] during a read of the programmed location

until the programming is complete. The host software

should poll the programmed address until EBD[7]

matches the programmed value.

AMD Flash byte programming is allowed in any se-

quence and across sector boundaries. Note that a data

0 cannot be programmed back to a 1. Only erase oper-

ations can convert zeros to ones. AMD Flash chip

erase is a six-bus cycle operation. There are two unlock

write cycles, followed by writing the set-up command.

Two more unlock cycles are then followed by the chip

erase command. Chip erase does not require the user

to program the device prior to erasure. Upon ex ecuting

the AMD Flash Embedded Erase Algor ithm com mand

sequence, the Flash device will program and verify the

entire memory for an all zero data pattern prior to elec-

trical erase. The Am79C973/Am79C975 controller is

not required to provide any controls or timings during

these operations. The automatic erase begins on the

rising edge of the last EBWE pulse in the command se-

quence and ter minates when th e data on EBD[7 ] is 1,

at which time the Flash device returns to the read

mode. Polling by the Am79C973/Am79C9 75 c on t roll er

is not requ ired dur in g the erase sequ ence. The follow-

ing FLASH programming-table excerpt (Table 12)

shows the command sequence for byte programming

and sector/chip erasure on an AMD Flash device. In

the following table, PA and PD stand for programmed

address and programmed data, and SA stands for sec-

tor address.

The Am79C973/Am79C975 controller will support only

a single sector erase per command and not concurrent

sector erasures. The Am79C973/Am79C975 controller

will support most FLASH de vices as long as there is no

timing requirement between the completion of com-

mands. The FLASH access time cannot be guaranteed

with the Am79C973/Am79C975 controller access

mechanism. The Am79C973/Am79C975 controller will

also support only Flash devices that do not require data

hold times after write operations. See Table 12.

EBUA_EBA[7:0]

EBD[7:0]

AS_EBOE

EROMCS

EBUA[19:16]

EBDA[15:8]

EBA[7:0]

CLK

1 2 345678910 11 12 13

EBWE 21510D-50

Table 12. Am29Fxxx Flash Command

Command

Sequence

Bus

Write

Cycles

Req’dFirst Bus

Write Cycle Second Bus

Write Cycle Third Bus

Write Cycle Fourth Bus

Write Cycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Byte Progr am 45555h AAh 2AAAh 55H 5555h A0h PA PD

Chip Erase 65555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h 5555h 10h

Sector Erase 65555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h SA 3h

96 Am79C973/Am79C975

PRELIMINARY

SRAM Configuration

The Am79C973/Am79C975 controller supports inter-

nal SRAM as a FIFO extensio n as well as providing a

read/write data path to the SRAM. The Am79C973/

Am79C975 controller contains 12 Kbytes of SRAM.

Internal SRAM Configuration

The SRAM _SIZE (B CR25, bi ts 7-0) programs the size

of the SRAM. SRAM_SIZE can be programmed to a

smaller value than 12 Kbytes.

The SRAM should be programmed on a 512-byte

boundary. However, there should be no accesses to the

RAM space while the Am79C973/Am79C975 control-

ler is running. The Am79C973/Am79C975 controller

assumes that it com pletely owns the SRAM while it is

in operation. To specify how much of the SRAM is allo-

cated to transmit and how much is allocated to receive,

the user should program SRAM_BND (BCR26, bits 7-

0) with the page boundary where the receive buff er be-

gins. The SRAM_BND al so sh oul d be programme d on

a 512-byte bound ary. The tran smit buffer space star ts

at 0000h. It is up to the user or the software driver to

split up the memory for transmit or receive; there is no

defaulted value. The minimum SRAM size required is

four 512-byte pages for each transmit and receive

queue, which limits the SRAM size to be at least 4

Kbytes.

The SRAM_BND upon H_RESET will be reset to

0000h. The Am79C973/Am79C975 controller will not

have any transmit buffer space unless SRAM_BND is

programmed. The las t configuration para meter neces-

sar y is the clock source us ed to contr ol the Expa nsio n

Bus inte rfac e. This is programmed through t he SRAM

Interface Control register . The e xternally driven Expan-

sion Bus Clock (EBCLK) can be used by specifying a

value of 010h in EBCS (BCR27, bits 5-3). This allows

the user to utilize any clock that may be available.

There are two standard clocks that can be chosen as

well, the PCI clock or the externally provided time base

clock. When the PCI or time base clock is used, the

EBCLK do es no t have to be dri ven, but it must be tied

to VDD through a resistor. The user must specify an

SRAM clock (BCR27, bits 5-3) that will not stop unless

the Am79C 973/Am79C975 controller is stopped. Oth-

erwise, the Am79C973/Am79C975 controller will re-

port buff er ov erflows, underflows, corrupt data, and will

hang eventually.

The user can decide to use a f ast clock and then divide

down the frequency to get a better duty-cycle if re-

quired. The choices are a divide by 2 or 4 and is pro-

grammed by the CLK_F A C bits (BCR27, bits 2-0). Note

that the Am79C973/Am79C975 controller does not

support an SRAM frequency above 33 MHz regardless

of the clock and clock factor used.

No SRAM Configuration

If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the

SRAM size register, the Am79C973/Am79C975 con-

troller wi ll assume that there is no SR AM present an d

will reco nfigur e the four inter nal FIFOs into two FIFOs,

one for transmit and one f or receive. The FIFOs will op-

erate the same as in the PCnet-PCI II controller. When

the SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM

BND (BCR26, bits 7-0) are ignored by the Am79C973/

Am79C 975 co ntrol ler. See Figure 46.

Low Latency Receive Configuration

If the LOLATRX (BCR27, bit 4) bit is set to 1, then the

Am79C973/Am79C975 controller will configure itself

for a low latency receive configuration. In this mode,

SRAM is required at all times. If the SRAM_SIZE

(BCR25, bits 7-0) value is 0, the Am79C973/

Am79C 975 control ler will no t configure for low laten cy

receive mode. The Am79C973/Am79C975 controller

will provide a fast path on the receive side bypassing

the SRAM. All transmit traffic will go to the SRAM, so

SRAM_ BND (BCR 26, bi ts 7- 0) has no m eaning in low

latency receive mode. When the Am79C973/

Am79C975 controller has received 16 bytes from the

network , it will start a DMA req uest to the P CI Bus In-

terface Unit. The Am79C973/Am79C975 controller will

not wait for the f irst 64 bytes to pas s to ch eck for colli-

sions in L ow Latency Re ceive mode. The Am79C973 /

Am79C 975 controller must b e in STOP before switch-

ing to this mode. See Figure 47.

CA UTION: T o provide data integrity when switching

into and out of the low latency mode, DO NOT SET

the FASTSPNDE bit when sett ing the SPND bit. Re-

ceive frames WILL be overwritten and the

Am79C973/Am79C975 controller may give erratic

behavior when it is enabled again.

Direct SRAM Access

The SRAM can be accessed through the Expansion

Bus Data port (BCR30). To access this data port, the

user must load the upper address EPADDRU (BCR29,

bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the

user will load the lower 16 bits of address EPADDRL

(BCR28, bits 15-0). To initiate a read, the user reads

the Exp ansion Bus Data Por t (BCR 30). This slave ac-

cess fro m the P CI wil l result i n a r etr y for the very first

access. Su bs equ ent a cc es s es m ay give a retr y or no t,

depending on whether or not the data is present and

v alid. The direct SRAM access uses the same FLASH/

EPROM access except for accessing the SRAM in

word format instead of byte format. This access is

meant to be a diagno stic access onl y. The SRA M can

only be accessed while the Am79C973/Am79C975

controller is in STOP or SPND (FASTSPNDE is set to

0) mode.

Am79C973/Am79C975 97

PRELIMINARY

Figure 46. Block Diagram No SRAM Configuration

Figure 47. Block Diagram Low Latency Receive Configuration

PCI Bus

Interface

Unit

802.3

MAC

Core

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

21510D-51

PCI Bus

Interface

Unit 802.3

MAC

Core

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

SRAM

21510D-52

98 Am79C973/Am79C975

PRELIMINARY

EEPROM Interface

The Am7 9C97 3/A m79 C975 co ntr ol le r con tai ns a built-

in capability f or reading and writing to an external serial

93C46 EEPROM. This built-in capability consists of an

interface for direct connection to a 93C46 compatible

EEPROM, an automa tic EE PROM read feature, and a

user-programmable register that allows direct access

to the interf ace pins.

Automatic EEPROM Read Operation

Shortly after the deassertion of the RST pin, the

Am79C973/Am79C975 controller will read the con-

tents of the EEPROM that is attached to the inter face.

Because of this automatic-read capability of the

Am79C973/Am79C975 controller, an EEPROM can be

used to program many of the features of the

Am79C973/Am79C975 controller at power-up, allow-

ing system-dependent configuration information to be

stored in the hardware, instead of inside the device

driver.

If an EEPROM exists on the interface, the Am79C973/

Am79C975 controller will read the EEPROM contents

at the end of the H_RESET operation. The EEPROM

contents will be s eri ally s hifted into a temp orar y regis-

ter and then sent to various register locations on board

the Am79C973/Am79C975 controller. Access to the

Am79C973/Am79C975 configuration space, the Ex-

pansion ROM or any I/O resource is not possible during

the EEPROM read operation. The Am79C973/

Am79C975 controller will terminate any access at-

tempt with the assertion of DEVSEL and STOP while

TRDY is not asserted, signaling to the initiator to dis-

connect and retry the access at a later time.

A checksum verification is performed on the data that

is read from the EEPROM. If the checksum verification

passes, PVALID (BC R19, bit 1 5) will be se t to 1. If th e

checksum verification of the EEPROM data fails,

PVALID will be cleared to 0, and the Am79C973/

Am79C9 75 controller will force all EE PROM-pr ogram-

mable BCR registers back to their H_RESET default

valu es. How ev er, the co nt en t of th e A d dr ess PROM lo-

cations (offsets 0h - Fh from the I/O or memory

mapped I/O base addre ss) will not b e cleared. The 8-

bit checksum for the entire 68 bytes of the EEPROM

should be FFh.

If no EEP ROM is p resent at the ti me of the aut omatic

read operation, the Am79C973/Am79C975 controller

will recognize this condition and will abort the auto-

matic read operation and clear both the PREAD and

PVALID bits in BCR19. All EEPROM-programmable

BCR registers will be assigned their default values after

H_RESET. The content of the Address PROM loca-

tions (offsets 0h - Fh from the I/O or memory mapped

I/O base address) will be undefined.

EEPROM Auto-Detection

The Am79 C973 /Am 79C 975 c ont ro ll er use s th e EE SK /

LED1/SFBD pin to determine if an EEPROM is present

in the system. At the rising edge of CLK during the last

clock during which RST is asserted, the Am79C973/

Am79C975 controller will sample the value of the

EESK/LED1/SFBD pin. If the sampled value is a 1,

then the Am79C973/Am79C975 controller assumes

that an EEPROM is present, and the EEPROM read

operation begins shortly after the RST pin is deas-

serted . If the sampl ed value of EE SK /LE D1/S FB D is a

0, the Am79C973/Am79C975 controller assumes that

an external pulldown device is holding the EESK/LED1/

SFBD pin low, indicating that there is no EEPROM in

the system. Note tha t if the desi gner crea tes a syste m

that contains an LED circuit on the EESK/LED1/SFBD

pin, but has no EEPROM present, then the EEPROM

auto-detection function will incorrectly conclude that an

EEPROM is present in the system. However, this will

not pose a problem for the Am79C973/Am79C975 con-

troller, since the checksum verification will f ail.

Direct Access to the Interface

The user may directly access the port through the

EEPROM register, BCR19. This register contains bits

that can be used to control the interface pins. By per-

forming an appropriate sequence of accesses to

BCR19, the user can effectively write to and read from

the EEPROM. This feature may be used by a system

configurat ion utility to program hardware c onfiguration

information into the EEPROM.

EEPROM-Programma ble Registers

The following registers contain configuration informa-

tion that will be programmed automatically during the

EEPROM read operation:

■I/O offsets 0h-Fh Address PROM locations

■BCR2 Miscellaneous Configuration

■BCR4 LED0 Status

■BCR5 LED1 Status

■BCR6 LED2 Status

■BCR7 LED3 Status

■BCR9 Full-Duplex Control

■BCR18 Burst and Bus Control

■BCR22 PCI Latency

■BCR23 PCI Subsystem Vendor ID

■BCR24 PCI Subsystem ID

■BCR25 SRAM Size

■BCR26 SRAM Boundary

■BCR27 SRAM Interface Control

■BCR32 PHY Control and Status

■BCR33 PHY Address

Am79C973/Am79C975 99

PRELIMINARY

■BCR35 PCI Vendor ID

■BCR36 PCI Power Management

Capabilities (PMC) Alias Regis-

ter

■BCR37 PCI D ATA Register Zero (DATA0)

Alias Register

■BCR38 PCI DATA Register One (DATA1)

Alias Register

■BCR39 PC I DATA Register Two (DATA2)

Alias Register

■BCR40 PCI DATA Register Three

(DATA3) Alias Register

■BC R41 PCI DATA Re gis te r Four ( DATA4)

Alias Register

■BCR42 PC I DATA Regi ster Five (DATA5)

Alias Register

■BCR43 PCI DATA Register Six (DATA6)

Alias Register

■BCR44 PCI DATA Register Seven

(DATA7) Alias Register

■BCR45 OnNow Pattern Matching

■BCR46 OnNow Pattern Matching

■BCR47 OnNow Pattern Matching

■CSR12 Physical Address Register 0

■CSR13 Physical Address Register 1

■CSR14 Physical Address Register 2

■CSR116 OnNow Miscellaneous

If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)

are cleared to 0, then the EEPROM read has experi-

enced a failure and the content s of the EEPROM pro-

grammable BCR register will be set to default

H_RESET values. The conten t of the Address PROM

locations, however, will not be cleared.

EEPROM MAP

The automatic EEPROM read operation will access 41

words (i.e., 82 bytes) of the EEPROM. The format of

the EEPROM contents is shown in Table 13 (next

page), begi nning with the byte that resides at the low-

est EEPROM address.

Note: The first bit out of any word locati on in the EE-

PROM is treated as the MSB of the register being pro-

grammed. For example, the first bit out of EEPROM

word location 0 9h wi ll be written into BCR4 , bit 15; th e

second bit out of EEPROM word location 09h will be

written into BCR4, bit 14, etc.

There are two checksum locations within the EE-

PROM. The first checksum will be used by AMD driver

software to verify that the ISO 8802-3 (IEEE/ANSI

802.3) station address has not been corrupted. The

valu e of bytes 0Ch a nd 0Dh should match the sum of

bytes 00h thr ough 0B h and 0Eh and 0Fh. The sec ond

checksum locati on (byte 51h) is not a checksu m total,

but is, instead, a checksum adjustment. The value of

this byte should be such that the total checksum for the

entire 82 bytes of EEPROM data equals the v alue FFh.

The checksum adjust byte is needed by the

Am79C973/Am79C975 controller in order to verify that

the EEPROM content has not been corrupted.

LED Support

The Am79C973/Am79C975 controller can suppor t up

to four LEDs. LED outputs LED0, LED1, and LED2

allow f or direct connection of an LED and its supporting

pullup device.

In applications that want to use the pin to drive an LED

and also have an EEPROM, it might be necessar y to

buffer the LE D3 circuit fr om the EEPROM conn ection.

When an LED circuit is directly connected to the

EEDO/LED3/SRD pin, then it is not possible for most

EEPROM devices to sink enough IOL to maintain a valid

low level on the EEDO input to the Am79C973/

Am79C 975 c on tro ller. Use of buffering ca n be avoided

if a low power LED is used.

Each LED can be programmed through a BCR register

to indicate one or more of the following networ k status

or activities: Collision Status, Full-Duplex Link Status,

Half-Dupl ex Link Status, R eceive Match, Recei ve Sta-

tus, Magic Packet, Disable Transceiver, and Transmit

Status.

100 Am79C973/Am79C975

PRELIMINARY

Table 13. Am79C973 EEPROM Map

Note: *Lowest EEPROM address.

Word

Address Byte

Addr. Most Significant Byte Byte

Addr. Least Significant Byte

00h* 01h 2nd byte of the ISO 8802-3 (IEEE/ANSI

802.3) station physical address for this node 00h

First byte of the IS0 8802-3 (IEEE/ANSI 802.3)

station physical address for this node, where

“first byte” refers to the first byte to appear on

the 802.3 medium

01h 03h 4th byte of the node address 02h 3rd byte of the node address

02h 05h 6th byte of the node address 04h 5th byte of the node address

03h 07h CSR116[15:8] (OnNow Misc. Config). 06h CSR116[7:0] (OnNow Misc. Config.)

04h 09h Hardware ID: must be 11h if compatibility to

AMD drivers is desired 08h Reserved location: must be 00h

05h 0Bh User programmable space 0Ah User programmable space

06h 0Dh MSB of tw o-byte chec ksum, which is the sum

of bytes 00h-0Bh and bytes 0Eh and 0Fh 0Ch LSB of two-byte checksum, which is the sum

of bytes 00h-0Bh and bytes 0Eh and 0Fh

07h 0Fh Must be ASCII “W” (57h) if compatibility to

AMD driver sof tware is desired 0Eh Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired

08h 11h BCR2[15:8] (Miscellaneous Configuration) 10h BCR2[7:0] (Miscellaneous Configuration)

09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED)

0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status)

0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status)

0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status)

0Dh 1Bh BCR9[15:8] (Full-Duplex control) 1Ah BCR9[7:0] (Full-Duplex Control)

0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control)

0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Latency)

10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BCR23[7:0] (PCI Subsystem Vendor ID)

11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR24[7:0] (PCI Subsystem ID)

12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size)

13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary)

14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control)

15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status)

16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address)

17h 2Fh BCR35[15:8] (PCI Vendor ID) 2 Eh BCR35[7:0] (PCI Vendor ID)

18h 31h BCR36[15:8] (Conf. Space. byte 43h alias) 30h BCR36[7:0] (Conf. Space byte 42h alias)

19h 33h BCR37[15:8] (DATA_SCALE alias 0) 32h BCR37[7:0] (Conf. Space byte 47h0alias)

1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Space byte 47h1alias)

1Bh 37h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Space byte 47h2alias)

1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Space byte 47h3alias)

1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Space byte 47h4alias)

1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 0) 3Ch BCR42[7:0] (Conf. Space byte 47h5alias)

1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 0) 3Eh BCR43[7:0] (Conf. Space byte 47h6alias)

20h 41h BCR44[15:8] (DATA_SCALE alias 0) 40h BCR44[7:0] (Conf. Space byte 47h7alias)

21h 43h BCR48[15:8]Reserved location:must be 00h 42h BCR48[7:0]Reserved location: must be 00h

22h 45h BCR49[15:8]Reserved location:must be 00h 44h BCR49[7:0]Reserved location: must be 00h

23h 47h BCR50[15:8]Reserved location:must be 00h 46h BCR50[7:0]Reserved location: must be 00h

24h 49h BCR51[15:8]Reserved location:must be 00h 48h BCR51[7:0]Reserved location: must be 00h

25h 4Bh BCR52[15:8]Reserved location:must be 00h 4Ah BCR52[7:0]Reserved location: must be 00h

26h 4Dh BCR53[15:8]Reserved location:must be 00h 4Ch BCR53[7:0]Reserved location: must be 00h

27h 4Fh BCR54[15:8]Reserved location:must be 00h 4Eh BCR54[7:0]Reserved location: must be 00h

28h 51h Chec ksu m adjus t b yte f or the 82 bytes of the

EEPROM contents, checksum of the 82 bytes

of the EEPROM should total to FFh 50h BCR55[7:0]Reserved location: must be 00h

Empty lo cations – Ignored by device

3Eh 7Dh Reserved for Boot ROM usage 7Ch Reserved for Boot ROM usage

3Fh 7Fh Reserved for Boot ROM usage 7Eh Reserved for Boot ROM usage

Am79C973/Am79C975 101

PRELIMINARY

Table 14. Am79C975 EEPROM Map

Note: * Lowest EEPROM address.

Word

Addr. Byte

Addr. Most Significant Byte Byte

Addr. Least Significant Byte

00h* 01h 2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3)

station physical address for this node 00h

First b yte of the ISO 8802 -3 (IEEE/ANSI 802.3)

station physical address for this node, where

“first byte” refers to the first byte to appear on

the 802.3 medium

01h 03h 4th byte of the node address 02h 3rd byte of the node address

02h 05h 6th byte of the node address 04h 5th byte of the node address

03h 07h CSR116[ 15:8] (On Now Mis c . Config). 06h CSR116[7:0] (OnNow Misc. Config.)

04h 09h Hardware ID: must be 11h if compatibility to

AMD drivers is desired 08h Reserved location: must be 00h

05h 0Bh User programmable space 0Ah User programmable space

06h 0Dh MSB of tw o-byte check sum, which is the sum of

bytes 00h-0Bh and bytes 0Eh and 0Fh 0Ch LSB of two -b yte ch ec ksum , whic h is th e sum of

bytes 00h-0Bh and bytes 0Eh and 0Fh

07h 0Fh Must be ASCII “W” (57 h) if compatibi lity to AMD

driver sof tware is desired 0Eh Must be ASCII “W” (57h ) if compat ibility to AM D

driver sof tware is desired

08h 11h BCR2[15:8] (Miscellaneous Configuration) 10h BCR2[7:0] (Miscellaneous Configuration)

09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED)

0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status)

0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status)

0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status)

0Dh 1Bh BCR9[15:8] (Full-Duplex Control) 1Ah BCR9[7:0] (Full-Duplex Control)

0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control)

0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Latency)

10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BCR23[7:0] (PCI Subsystem Vendor ID)

11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR22[7:0] (PCI Subsystem ID)

12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size)

13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary)

14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control)

15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status)

16h 2Dh BCR33[15:8 ] (MI I Address) 2Ch BCR33[7:0] (MII Address)

17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID)

18h 31h BCR36[15:8] (Conf. Sp. byte 43h alias) 30h BCR36[7:0] (Conf. Sp. byte 42h alias)

19h 33h BCR37[15:8] (DATA_SCALE alias0) 32h BCR37[7:0] (Conf. Sp. byte 47h0 alias)

1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Sp. byte 47h1 alias)

1Bh 37h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Sp. byte 47h2 alias)

1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Sp. byte 47h3 alias)

1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Sp. byte 47h4 alias)

1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 5) 3Ch BCR42[7:0] (Conf. Sp. byte 47h5 alias)

1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 6) 3Eh BCR43[7:0] (Conf. Sp. byte 47h6 alias)

20h 41h BCR44[15:8] (DATA_SCALE alias 7) 40h BCR44[7:0] (Conf. Sp. byte 47h7 alias)

21h 43h BCR48[15 :8] N_IP_ADR[15:8 ] 42h BCR48[7: 0] N_ IP_ADR[ 7 :0]

22h 45h BCR49[15 :8] N_IP_A DR[ 31:2 4] 44h BCR49[7: 0] N_IP_AD R[2 3:16 ]

23h 47h BCR50[15:8] M_IEEE_ADR[1 5:8] 46h BCR50[7:0] M_IEEE_ADR[7:0]

24h 49h BCR51[15:8] M_IEEE_ADR[3 1:24] 48h BCR51[7:0] M_IEEE_ADR[23 :16 ]

25h 4Bh BCR52[15:8] M_IEEE_ADR[4 7:4 0] 4Ah BCR52[7:0] M_IEEE_ADR[39 :32 ]

26h 4Dh BCR53[15:8] M_IP_ADR[15:8] 4Ch BCR53[7:0] M_IP_ADR[7:0]

27h 4Fh BCR54[15:8] M_IP_ADR[31:24] 4Eh BCR54[7:0] M_IP_ADR[23:16]

28h 51h Checksum adjust byte for the 82 bytes of the

EEPROM contents, checksum of the 82 bytes of

the EEPROM should total to FFh 50h BCR55[7:0] SMIU Slave Address

3Eh 7Dh Reserved for Boot R OM us age 7Ch Reserv ed for Boot ROM usage

3Fh 7Fh Reserv ed for Boot ROM usage 7Eh Reserv ed for Boot ROM usage

102 Am79C973/Am79C975

PRELIMINARY

The LED pins can be configured to operate in either

open-drain mode (active low) or in totem-pole mode

(active high ). The output can b e str etche d to a llow the

human eye to recognize even short events that last only

several microseconds. After H_RESET, the four LED

outputs are configured as shown in Table 15.

Table 15. LED Default Configuration

For each LED register, each of the status signals is

AND’d with its enable signa l, and thes e signa ls are all

OR’d togethe r to for m a combine d status signal. Each

LED pin combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

each shi ft register is norma lly at logic 0. The OR gate

output for each LED register asynchronously sets all

three bits of its shift register when the output becomes

asser ted. The inverted output of each shift register is

used to control an LED pin. Thus, the pulse stretcher

provides 2 to 3 clocks of stretched LED output, or 52

ms to 78 ms. See Figure 48.

Power Savings Mode

Power Management Support

The Am7 9C973/Am79C975 controller sup por ts power

management as defined in the PCI Bus Power Man-

agement Interface Specification V1.1 and Network De-

vice Class Power Management Reference

Specification V1.0.These specifications def ine the net-

work device power states, PCI power manage ment in-

terface including the Capabilities Data Structure and

power management registers block definitions, power

management events, and OnNow network Wake-up

ev ents. In addition, the Am79C973/Am79C975 control-

ler supports legacy power management schemes,

such as Remote Wake-Up (RWU) mode. When the

system is in RWU mode, PCI bus power is on, the PCI

clock may be slowed down or stopped , and the wake-

up output pin may drive the CPU's System Manage-

ment Interrupt (SMI) line.

Auxiliary Power

The Am79C973/Am79C975 uses the AUXDET pin to

detect whether it is powered by an auxiliary power sup-

ply that is always on or by the PCI power supply that

goes down during power saving modes.

If bit 15 of PMC is zero, indicating that PME asse r tion

in D3cold is not supported, the PME_Status and

PME_En bits of the PMCS R reg ister will be reset by a

PCI bus reset (assertion of RST pin). This reset will ac-

tually occur after the EEPROM read f ollowing the reset

is complete to allow the controller to be configured.

To fully satisfy the requirements of the PCI power man-

agement specification in an adapter card configuration,

the AUXDET pin should be connected directly to the

auxiliary power supply and also to ground through a re-

sistor. This will sense the presence of the auxiliary

power and correctly report the capability of asserting

PME in D3c old .

For hardwired configurations where auxiliary power is

know to be always available or never available, the

AUXDET input may be disabled by connecting it di-

rectly or through a resistor to VDD. This will allow

BCR36 bit 15 to directly control PMC bit 15.

Figure 48. LED Control Logic

The general scheme for the Am79C973/Am79C975

po w e r m a na g em e nt i s t h at w h en a PC I Wake- u p ev e nt

is detected, a signal is generated to cause hardware

external to the Am79C973/Am79C975 device to put

the computer into the working (S0) mode.

The Am79C973/Am79C975 device supports three

types of wake-up events:

1. Magic Packet Detect

2. OnNow Pattern Match Detect

3. Link State Change

Figure 49 shows the relationship between these Wak e-

up events and the various outputs used to signal to the

external hardware.

LED

Output Indication Driver Mode Pulse Stretch

LED0 Link Status Open Drain -

Active Low Enabled

LED1 Receive

Status Open Drain -

Active Low Enabled

LED2 -- Open Drain -

Active Low Enabled

LED3 Transmit

Status Open Drain -

Active Low Enabled

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

Pulse

Stretcher

MR_SPEED_SEL

100E

MPS

MPSE

21510D-53

Am79C973/Am79C975 103

PRELIMINARY

Figure 49. OnNow Functional Diagram

OnNow Wake-Up Sequence

The system software enables the PME pin by setting

the PME_EN bit in the PMCSR register (PCI configura-

tion reg isters, offse t 44h, bit 8) to 1. W hen a Wake-up

event is detected, the Am79C973/Am79C975 control-

ler sets the PME_STATUS bit in the PMCSR register

(PCI configuration registers, offset 44h, bit 15). Setting

this bit causes the PME signal t o be asser ted. Asser-

tion of the PME signal causes external hardware to

wak e up the CPU . The system software then reads the

PMCSR register of every PCI device in the system to

determine which device asserted the PME signal.

When the software determines that the signal came

from the Am79C973/Am79C975 controller, it writes to

the device’s PMCSR to put the device into power state

D0. The soft ware the n writes a 0 to the PME _S TATUS

bit to clear the bit and turn off the PME signal, and it

calls the device’s software driver to tell it that the device

is now in stat e D0. The s ystem software ca n clear th e

PME_STATUS bit either before, after, or at the same

time that it puts the device back into the D0 state.

Link Change Detect

Link change detect is one of Wake-up events defined

by the OnNow specification and is supported by the

R WU mode. Link Change Detect mode is set when the

LCMODE bit (CSR116, bit 8) is set either by software

or loaded through the EEPROM.

When thi s bit is set, any chan ge in th e Link status will

cause the LCDET bit (CSR116, bit 9) to be set. Whe n

MPDETECT

MPPEN

MPMODE

MPEN

MPINT

LED

WUMI

Magic Packet

Link Change

LCMODE

Link Change

MPMAT

LCDET

DET

CLR

BCR47 BCR46 BCR45

SET

CLR

SET

CLR

SET

CLR

PMAT

Pattern Match

Input

Pattern

PME_STATUS

Pattern Match RAM (PMR)

PME Status

PME_EN

MPMAT

PME_EN_OVR

LCEVENT

PME

RWU

SET

CLR

POR

H_RESET

POR

21510D-54

104 Am79C973/Am79C975

PRELIMINARY

the LCDET bit is set, the RWU pin will be asserted and

the PME_S TATUS bit (PMCS R register, bit 15) wil l be

set. If either the PME_EN bit (PMCSR, bit 8) or the

PME_EN_OVR bit (CSR116, bit 10) are set, then the

PME will also be asserted.

OnNow Pattern Match Mode

In the OnNow Pattern Match Mode, the Am79C973/

Am79C975 device compares the incoming packets

with up to eight patterns stored in the Pattern Match

RAM (PMR). The stored patterns can be compared

with par t or all of in coming packets, depending on th e

pattern length and the way the PMR is programmed.

When a pat ter n m atch ha s been detecte d, then P MAT

bit (CSR116, bit 7) is set. The setting of the PM AT bit

causes the PME_STATUS bit (PMCSR, bit 15) to be

set, which in turn will assert the PME pin if the

PME_EN bit (PMCSR, bit 8) is set.

Pattern Match RAM (PMR)

PMR is organized as an arra y of 64 words by 40 bits as

shown in Figure 50. The PMR is programmed indirectly

through the BC Rs 45, 46 , and 47 . Wh en the BC R45 is

writ ten and the PMAT_MODE bit (BC R45, bit 7) is set

to 1, Patter n Match logic is enabled. No bus access es

into the P MR are possi bl e when the P MAT_MODE bit

is set, and BCR46, BCR47, and all other bits in BCR45

are ignored. When PMAT_MODE is set, a read of

BCR45 returns all bits undefined except for

PMAT_MODE. In order to access the contents of the

PMR, PMAT_MODE bit should be programmed to 0.

When BCR45 is wri tten to set th e PMAT _MODE b it to

0, the Patter n Mat ch logi c is d is abled and a cc ess es to

the PMR are possible. Bits 6:0 of BCR45 specify the

address of the PMR word to be accessed. Writing to

BCR45 does not immediately affect the contents of the

PMR. Following the write to BCR45, the PMR word ad-

dressed by the bits 6:0 of the BCR45 may be read by

reading BCR45, BCR46, and BCR47 in any order. To

write to the PMR word, the write to BCR45 must be

followed by a write to BCR46 and a wr ite to BCR 47 in

that order to complete the operation. The PMR will not

actually be written until the write to BCR47 is complete.

The first two 40-bit words in this RAM serv e as pointers

and contain enable bits for the eight possible match

patterns. The remainder of the RAM contains the

match patterns and associated match pattern control

bits. The byte 0 of the first word contains the Patter n

Enable bits. Any bit position set in this byte enables the

corresponding match pattern in the PMR, as an exam-

ple if the bit 3 is set, then the Pattern 3 is enabled for

matching . Bytes 1 t o 4 in the fi rst word are poin ters to

the beginning of the patterns 0 to 3, and bytes 1 to 4 in

the second word are pointers to the beginning of the

patterns 4 to 7, respectively. Byte 0 of the second word

has no function associated with it. The byte 0 of the

words 2 to 63 i s the Control F ield of the PM R. Bit 7 of

this field is the End of Pac ket (EOP) bit. When this bit is

set, it indicates the end of a pattern in the PMR. Bits 6-

4 of the Control Field byte are the SKIP bits. The value

of the SKIP field indicates the number of the Dwords to

be skipped bef ore the pattern in this PMR word is com-

pared wi th data from t he incom ing frame. A maxi mum

of seven Dwords may be skipp ed. Bits 3- 0 of the Con-

trol Field byte are the MASK bits. These bits corre-

spond to the pattern match bytes 3-0 of the same PMR

word (PMR bytes 4-1). If bit n of this field is 0, then byte

n of the corresponding patter n word is ignored. If this

field is programmed to 3, then bytes 0 and 1 of the pat-

tern match field (bytes 2 and 1 of the word) are used

and bytes 3 an d 2 ar e ign ored in t he patte r n ma tchin g

operation.

The contents of the PMR are not affected by

H_RESET, S_RESET, or STOP. The contents are un-

defined after a power up reset (POR) .

Magic Packet Mode

In Magic Packet mode, the Am79C973/Am79C975

controller remains fully powered up (all VDD and VDDB

pins must remain at their supply levels). The device will

not generate any bus master transfers . No transmit op-

er atio ns will be initia ted on the net work. The de vic e will

continue to receive frames from the network, but all

frames will be automatically flushed from the receive

FIFO. Slave accesses to the Am79C973/Am79C975

control ler are still possible. A Magic Packet is a fram e

that is addressed to the Am79C973/Am79C975 con-

troller and contains a data sequence anywhere in its

data fie ld made up of 16 conse cu tive copies of the de-

vice’s physical address (PADR[47:0]). The Am79C973/

Am79C975 controller will search incoming frames until

it finds a Magic Packet frame. It starts scanning for the

sequence after processing the length field of the frame.

The data sequence can begin anywhere in the data

field of the frame, but must be detected before the

Am79C973/Am79C975 controller reaches the frame’s

FCS field. Any deviation of the incoming frame’s data

sequence from the required physical address se-

quence, even by a single bit, wi ll prevent the de tectio n

of that frame as a Magic Packet frame.

The Am79C973/Am79C975 controller supports two dif-

ferent modes of address detection for a Magic Packet

frame. If MPPLBA (CSR5, bit 5) or EMPPLBA

(CSR116, bit 6) are at their default value of 0, the

Am79C973/Am79C975 controller will only detect a

Magic Packet frame if the destination address of the

packet matches the content of the physical address

the destination address of the Magic Packet frame can

be unicast, multicast, or broadcast.

Am79C973/Am79C975 105

PRELIMINARY

Figure 50. Pattern Match RAM

Note: The setting of MPPLBA or EMPPLBA only ef-

fects the address detection of the Magic Packet frame.

The Magic Packet’s data sequence must be made up

of 16 consecutive copies of the device’s physical ad-

dress (PADR[47:0]), regardless of what kind of destina-

tion address it has.

There are two general methods to place the

Am79C973/Am79C975 controller into the Magic

Packet mode. The first is the software method. In this

method, either the BIOS or other software, sets the

MPMODE bit (CSR5, bit 1). Then Am79C973/

Am79C975 controller must be put into suspend mode

(see description of CSR5, bit 0), allowing any current

network activity to finish. Finally, either PG must be

deasserted (ha rdware control ) or MPEN ( CSR5, bit 2)

must be set to 1 (software control).

Note: FASTSPNDE (CSR7, bit 15) has no meaning in

Magic Packet mode.

The second method is the hardware method. In this

method, the MPPEN bit (CSR116, bit 4) is set at power

up by the loading of the EEPROM. This bit can also be

set by software. The Am79C973/Am79C975 controller

will be placed in the Magic Packet Mode when either

the PG input is deasserted or the MPEN bit is set.

WUMI output will be asserted when the Am79C973/

Am79C975 controller is in the Magic Packet mode.

Magic Packet mode can be disabled at any time by as-

serting PG or clearing MPEN bit.

BCR 47 BCR 46 BCR 45

BCR Bit Number 15 8 7 0 15 8 7 0 15 8

PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0

Pattern Match

RAM Address Pattern Match RAM Bit Number

39 32 31 24 23 16 15 8 7 0 Comments

0P3 pointer P2 pointer P1 pointer P0 pointer Pattern Enable

bits First Address

1P7 pointer P6 pointer P5 pointer P4 pointer X Second

Address

2Data Byte 3 Data Byte 2 Data Byte1 Data Byte 0 Pattern Control Start Patte rn

2+n Data Byte 4n+3 Date Byte 4n+2 Data Byte 4n+1 Data Byte 4n+0 Pattern Control End Pattern P1

JData Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Pattern Control Start Patte rn

J+m Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern Pk

63 Last Address

7 6 5 4 3 2 1 0

EOP SKIP MASK

21510D-55

106 Am79C973/Am79C975

PRELIMINARY

When the Am79C973/Am79C975 controller detects a

Magic Packet frame, it sets the MPMAT bit (CSR116,

bit 5), the MPINT bit (CSR5, bit 4), and the

PME_STATUS bit (PMCSR, b it 15). The setti ng of the

MPMAT bit will also cause the RWU pin to be asserted

and if th e P ME _E N or the P ME _EN _OVR bits are se t,

then the PM E wil l be as s erted as well. If IE NA (C SR0 ,

bit 6) and MPINTE (CSR5, bit 3) are set to 1, INTA will

be asserted. Any one of th e four LED pins c an b e pro-

grammed to indicate that a Magic Packet frame has

been received. MPSE (BCR4-7, bit 9) must be set to 1

to enable that function.

Note: The polarity of the LED pin can be programmed

to be active HIGH by setting LEDPOL (BCR4-7, bit 14)

to 1.

Once a Magic Packet frame is detected, the

Am79C973/Am79C975 controller will discard the frame

internally, but will not resume normal transmit and re-

ceive operations until PG is asserted or MPEN is

cleare d. On ce both of thes e events has oc cu rre d, ind i-

cating th at the syste m has detected the Magic Packet

and is awake, the controller will continue polling receive

and transmit descriptor rings where it left off. It is not

necessary to re-initialize the device. If the part is re-ini-

tialized, th en the de scrip tor locati ons will b e reset an d

the Am79C973/Am79C975 controller will not start

where it left off.

If magic packet mode is disabled by the assertion of

PG, then in order to immediately re-enable Magic

Packet mode, the PG pin must remain deasser ted for

at least 200 ns before it is reasserted. If Magi c Packet

mode is di sa bled by clearing M PE N bi t, the n it may be

immediately re-enabled by setting MPEN back to 1.

The PCI bus interface clock (CLK) is not required to be

running while the device is operating in Magic Packet

mode. Either of the INTA, the LED pins, RWU or the

PME signal may be used to indicate the receipt of a

Magic Packet frame when the CLK is stopped. If the

system wishes to stop the CLK, it will do so after en-

abling the Magic Packet mode.

CAUTION: To prevent unwanted inte rrupts from oth er

active parts of the Am79C973/Am79C975 controller,

care must be taken to mask all likely interruptible

events during Magic Packet mode. An examp le would

be the interrupts from the Media Independent Interface,

which could occur while the device is in Magic Packet

mode.

IEEE 1149.1 (1990) Test Access Port

Interface

An IEEE 1149.1-compatible boundary scan Test Ac-

cess Port is provided for board-lev el continuity test and

diagnostics. All digital input, output, and input/output

pins are tested. The following paragraphs summarize

the IEEE 1149.1-compatible test functions imple-

mented in the Am79C973/Am79C975 controller.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK,

TMS, TDI, and TDO), defined as the Test Access Po r t

(TAP). It includes a finite state machine (FSM), an in-

struction register , a data register arra y, and a power-on

reset circuit. Internal pull-up resistors are provided for

the TDI, TCK, and TMS pins.

TAP Finite State Machine

The TAP engine is a 16-state finite state machine

(FSM), driven by the Test Clock (TCK), and the Test

Mode Select (TMS) pins. An independent power-on

reset circuit is provided to ensure that the FSM is in the

TEST_LOGIC_RESET state at power-up. Therefore,

the TRST is not provided. The FSM is also reset when

TMS and TDI are high for five TCK periods.

Supported Instructions

In addition to the min imum IEEE 1149.1 requir ements

(BYPASS, EXTEST, and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP, and SET-

BYP) are provided to fur ther ease board-level testing.

All unused instruction codes are reserved. See Table

16 for a summary of supported instructions.

Instruction Register and Decoding Logic

After th e TAP FSM is reset, the IDC ODE ins tr uction is

always invoked. The decoding logic gives signals to con-

trol the data flow in the Data registers according to the

current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the Parallel Output Stage, respectively.

Table 16. IEEE 1149.1 Supported Instruction

Summary

Instruction

Name Instruction

Code Description Mode

Selected

Data

EXTEST 0000 External Test Test BSR

IDCODE 0001 ID Code

Inspection Normal ID REG

SAMPLE 0010 Sample

Boundary Normal BSR

TRIBYP 0011 Force Float Normal Bypass

SETBYP 0100 Control

Boundary To

1/0 Test Bypass

BYPASS 1111 Bypass Scan Normal Bypass

Am79C973/Am79C975 107

PRELIMINARY

There are four possible operation modes in the BSR

cell shown in Table 17.

Other Data Registers

Other data registers are the following:

1. Bypass Register (1 bit)

2. Device ID register (32 bits) (Table 18).

Note: The content of the Device ID register is the

same as the conten t of CSR88.

Reset

There are four different types of RESET operations that

may be performed on the Am79C973/Am79C975 de-

vice, H_RESET, S_RESET, STOP, and POR. The fol-

lowing is a description of each type of RESET

operation.

H_RESET

Hardware Reset (H_RESET) is an Am79C973/

Am79C975 reset operation that has been created by

the proper assertion of the RST pin of the A m79 C973 /

Am79C975 device while the PG pin is HIGH. When the

minimum pulse width timing as specified in the RST pin

description has been satisfied, then an internal reset

operation will be performed.

H_RESET will program most of the CSR and BCR reg-

isters to thei r default value. Note that ther e are several

CSR and BCR registers that are undefined after

H_RESET. See the sections on the individual registers

for details.

H_RESET will clear most of the registers in the PCI

configuration space. H_RESET will cause the micro-

code program to jump to its reset state. Following the

end of the H_RESET operation, the Am79C973/

Am79C975 controller will attempt to read the EEPROM

device through the EEPROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the

Am79C973/Am79C975 controller will be in 16-bit I/O

mode after the reset operation. A DWord write opera-

tion to the RDP (I/O offset 10h) must be performed to

set the device into 32-bit I/O mode.

S_RESET

Software Reset (S_RESET) is an Am79C973/

Am79C975 reset operation that has been created by a

read access to the Reset register, which is located at

offset 14h i n Word I/O m ode or o ffs et 1 8h in DWord

I/O mode from the Am79C973/Am79C975 I/O or mem-

ory mapped I/O base address.

S_RESET will reset all of or some portions of CSR0, 3,

4, 15, 80, 100, and 124 to default values. For the iden-

tity of individual CSRs and bit locations that are af-

fected by S_RESET, see the individual CSR register

descriptions. S_RESET will not affect any PCI configu-

ration space location. S_RESET will not affect any of

the BCR register values. S_RESET will cause the mi-

crocode program to jump to its reset state. Following

the end of the S_RESET operation, the Am79C973/

Am79C975 controller will not attempt to read the EE-

PROM device. After S _RESET, the host must per fo r m

a full re-initialization of the Am79C973/Am79C975 con-

troller before star ting network activity. S_RESET will

cause REQ to deassert immediately. STOP (CSR0, bit

2) or SPND ( CSR5, b it 0) can be us ed to t erminate a ny

pending bus mastership request in an orderly se-

quence.

S_RESE T term in ates all network activi ty abrup tly. The

host can use the suspend mode (SPND, CSR5, bit 0)

to terminate all network activity in an orderly sequence

before issuing an S_RESET.

STOP

A STOP reset is generated by the assertion of the

STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,

when the stop bit currently has a value of 0, will initiate

a STOP reset. If the STOP bit is already a 1, then writ-

ing a 1 to the STOP bit will not generate a ST OP reset.

ST OP will reset all or some portions of CSR0, 3, and 4

to default values. For the identity of individual CSRs

and bit locations that are affected by ST OP, see the in-

dividual CSR register descriptions. STOP will not affect

any of the BCR and PCI configuration space locations.

STOP will c ause t he micr ocode p rogram to jum p to its

reset state. Following the end of the STOP operation,

the Am79C973/Am79C975 controller will not attempt to

read the EEPROM device.

Note: STOP will n ot cause a de asser tion of the REQ

signal, if it happens to be active at the time of the write

to CSR0. The Am79C973/Am79C975 controller will

wait until it gains bus ownership and it will first finish all

scheduled bus master accesses before the ST OP reset

is executed.

Table 17. BSR Mode Of Operation

1Capture

2Shift

3 Update

4System Function

Table 18. Device ID Register

Bits 31-28 Version

Bits 27-12 Part Number (0010 0110 0010 0101)

Bits 11-1 Manuf act urer ID. The 11 bit man uf acturer ID

cod f or AMD is 000000 00001 in acc ordance

with JEDEC publication 106-A.

Bit 0 Always a logic 1

108 Am79C973/Am79C975

PRELIMINARY

ST OP terminates all network activity abruptly. The host

can use the suspend mode (SPND, CSR5, bit 0) to ter-

minate all network activity in an orderly sequence be-

fore setting the STOP bit.

Power on Reset

Power on Reset (POR) is generated when the

Am79C973/ Am79C9 75 controlle r is powered up. POR

generates a hardware reset (H_RESET). In addition, it

clears some bits that H_RESET does not affect.

Software Access

PCI Configuration Registers

The Am79C973/Am79C975 controller implements the

256-byte configuration space as defined by the PCI

specification revision 2.1. The 64-byte header includes

all registers required to identify the Am79C973/

Am79C975 controller and its function. Additionally, PCI

Power Management Interface registers are imple-

mented at location 40h - 47h. The layout of the

Am79C973/Am79C975 PCI configuration space is

shown in Table 19.

The PCI c onfiguratio n regi sters ar e acces sible only by

configuration cycles. All multi-byte numeric fields f ollow

little endian byte ordering. All write accesses to Re-

served locations have no eff ect; reads from these loca-

tions will return a data value of 0.

Table 19. PCI Configuration Space Layou t

31 24 23 16 15 8 7 0 Offset

Device ID Vendor ID 00h

Status Command 04h

Base-Class Sub-Class Programming IF Revision ID 08h

Reserved Header Type Latency Timer Reserved 0Ch

I/O Base Address 10h

Memory Mapped I/O Base Address 14h

Reserved 18h

Reserved 1Ch

Reserved 20h

Reserved 24h

Cardbus CIS Pointer 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved CAP-PTR 34h

Reserved 38h

MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch

PMC NXT_ITM_PTR CAP_ID 40h

DATA_REG PMCSR_BSE PMCSR 44H

Reserved .

Reserved FCh

Am79C973/Am79C975 109

PRELIMINARY

I/O Resources

The Am79C973/Am79C975 controller requires 32

bytes of address space for access to all the various

internal registers as well as to some setup information

stored in an external serial EEPROM. A software reset

port is available, too.

The Am79C973/Am79C975 controller supports map-

ping the address space to both I/O and memory space.

The value in the PCI I/O Base Address register deter-

mines th e s tart address o f the I/O a ddr ess s pace. Th e

registe r is typi cally p rogrammed by the P CI config ura-

tion utility after system power-up . The PCI configura-

tion utility must also set the IOEN bit in the PCI

Command register to enable I/O accesses to the

Am79C973/Am79C975 controller. For memory mapped

I/O access, the PCI Memory Mapped I/O Base Address

The MEMEN bit in the PCI Command register must also

be set to enable the mode. Both base address registers

can be active at the same time.

The Am79C973/Am79C975 controller supports two

modes for accessing the I/O resources. F or backwards

compatibility with AMD’s 16-bit Ethernet controllers,

Word I/O is the default mode after power up. The device

can be configured to DWord I/O mode by software.

I/O Registers

The A m79 C973 /Am 79C9 75 c ontro ll er reg is ter s a re d i-

vided into two groups. The Control and Status Regis-

ters (CSR) are used to configure the Ethernet MAC

engine and to obtain status information. The Bus Con-

trol Regi sters (BCR) a re used to con figure the bus i n-

terface unit and the LEDs. Both sets of registers are

accessed using indirect addressing.

The CSR and BCR share a common Register Address

Port (RAP). There are, however, separate data por ts.

The Register Data Port (RDP) is used to access a

CSR. The BCR Data Por t (BDP) is used to access a

BCR.

In order to acc ess a par ticular CSR location, th e RAP

should first be written with the appropriate CSR ad-

dress. The RDP will then point to the selected CS R. A

read of the RDP will yield the selected CSR data. A

write to the RDP will write to the selected CSR. In order

to access a particular BCR location, the RAP should

first be writ ten with the appr opr iate B CR addres s. The

BDP will th en p oi nt to the sele ct ed B CR. A r ea d o f th e

BDP will yield the selected BCR data. A write to the

BDP will write to the selected BCR.

Once t he RAP has b een wr i tten wi th a value, the RAP

value r emains u nchanged until another RAP wr ite oc-

curs, or until an H_RESET or S_RESET occurs. RAP

is cleared to all 0s when an H_RESET or S_RESET oc-

curs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The Am79C973/Am79C975 controller allows for con-

nection of a serial EEPROM. The first 16 bytes of the

EEPR OM w ill be autom atica lly loa ded in to th e Addr ess

PROM (APROM) space after H_RESET. Additionally,

the first six bytes of the EEPROM will be loaded into

CSR12 to CSR14. The Address PROM space is a con-

venient pla ce to st or e th e value of th e 4 8-bi t IE EE s ta-

tion address. It can be overwritten by the host computer

and its content has no effect on the operation of the

controlle r. The so ftware mu st co py the station add re ss

from the Address PROM space to the initialization

block in order for the receiver to accept unicast frames

directed to this station.

The six bytes of the IEEE station address occupy the

first six locations of the Address PROM space. The

next six bytes are reserved. Bytes 12 and 13 should

match the value of the checksum of bytes 1 through 11

and 14 and 15. Bytes 14 and 15 should each be ASCII

“W” (57h). The above requirements must be met in

order to be compatible with AMD driver software.

APROMWE bit (BCR2, bit 8) must be set to 1 to enable

write access to the Address PROM space.

Reset Register

A read of the Reset register creates an internal soft-

ware reset (S_RESET) pulse in the Am79C973/

Am79C975 controller. The internal S_RESET pulse

that is generated by this access is different from both

the a ssertion of the har dware RST pin (H_RESET) and

from the assertion of the software STOP bit. Specifi-

cally, S_RESET is the equivalent of the assertion of the

RST pi n ( H_ RES ET ) except that S _RE SE T ha s no ef-

fect on the BCR or PCI Configuration space locations.

The NE2100 LANCE-based family of Ethernet cards

requires that a write access to the Reset register fol-

lows each read access to the Reset register. The

Am79C973/Am79C975 controller does not have a sim-

ilar req uiremen t. The wri te access i s not requ ired and

does not have any effect.

Note: The Am79C973/Am79C975 controller cannot

service any slav e accesses for a very short time after a

read access of the Reset register , because the internal

S_RESET operation takes about 1 ms to finish. The

Am79C973/Am79C975 controller will terminate all

slave accesses with the assertion of DEVSEL and

STOP while TRDY i s not asse rted, sign al ing to the in i-

tiator to disconnect and retry the access at a later time.

Word I/O Mode

After H_ RESET, the Am79C973/A m79C975 con troller

is programmed to operate in Word I/O mode. DWIO

(BCR18, bit 7) will be cleared to 0. Table 20 shows how

the 32 bytes of address space are used in Word I/O

mode.

110 Am79C973/Am79C975

PRELIMINARY

All I/O resou rces must be acce ssed in word quan tities

and on word addresses. The Address PROM locations

can also be read in byte quantities. The only allowed

DWord operation is a write access to the RDP, which

s witches the device to D Word I/O mode. A read access

other than l isted in th e table below will yield un define d

data, a write operation may cause unexpected repro-

gramming of the A m79C973/A m79C975 co ntrol regis -

ters. Table 21 shows legal I/O accesses in Word I/O

mode.

Double Word I/O Mode

The Am79C973/Am79C975 controller can be config-

ured to operate in DWord (32-bit) I/O mode. The soft-

ware can invoke the DWIO mode by performing a

DWord write access to the I/O location at offset 10h

(RDP). The data of the write access must be such that

it does not affect the intended operation of the

Am79C973/Am79C975 controller. Setting the device

into 32-bit I/O mode is usually the first operation after

H_RESET or S_RESET. The RAP register will point to

CSR0 at that time. Writing a value of 0 to CSR0 is a

saf e operation. DWIO (BCR18, bit 7) will be set to 1 as

an indication that the Am79C973/Am79C975 controller

operates in 32-bit I/O mode.

Note: Even though the I/O resource mapping changes

when th e I/O mo de settin g cha nges, the RDP loca tio n

offset is the same for both modes. O nce the DWIO bit

has been set to 1, only H_RESET can clear it to 0. The

DWIO mode settin g is unaffected by S_RESET or set-

ting of the S TOP bit. Table 22 shows how the 32 bytes

of address space are used in DWord I/O mode.

All I/O resources must be accessed in DWord quanti-

ties and on DWord addresses. A read access other

than listed in Table 23 will yield undefined data, a write

operation may cause unexpected reprogramming of

the Am79C973/Am79C975 control registers.

Table 20. I/O Map In Word I/O Mode (DWIO = 0)

Offset No. of

Bytes Register

00h - 0Fh 16 APROM

10h 2RDP

12h 2RAP (shared by RDP and BDP)

14h 2Reset Register

16h 2BDP

18h - 1Fh 8Reserved

Am79C973/Am79C975 111

PRELIMINARY

Table 23. Legal I/O Accesses in Double Word I/O

Mode (DWIO =1)

Table 21. Legal I/O Accesses in Word I/O Mode (DWIO = 0)

AD[4:0] BE[3:0] Type Comment

0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h or Ch

0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h or Dh

0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah or Eh

0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh or Fh

0XX00 1100 RD Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or

Ch and Dh

0XX10 0011 RD Word rea d o f APR O M lo cat ion s 3 h (MSB) a nd 2 h (L SB), 7h an d 6 h, Bh and Ah o r

Fh and Eh

10000 1100 RD Word read of RDP

10010 0011 RD Word read of RAP

10100 1100 RD Word read of Reset Register

10110 0011 RD Word read of BDP

0XX00 1100 WR Word write to APR OM lo cat ion s 1h (MSB) an d 0h (LSB), 5h and 4h, 8h and 9h or

Ch and Dh

0XX10 0011 WR W ord write to APR OM locat ions 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or

Fh and Eh

10000 1100 WR Word write to RDP

10010 0011 WR Word write to RAP

10100 1100 WR Word write to Reset Register

10110 0011 WR Word write to BDP

10000 0000 WR DWord write to RDP,

switches device to DWord I/O mode

Table 22. I/O Map In DWord I/O Mode (DWIO =1)

Offset No. of Bytes Register

00h - 0Fh 16 APROM

10h 4RDP

14h 4RAP (shared by RDP and

BDP)

18h 4Reset Register

1Ch 4BDP

AD[4:0] BE[3:0] Type Comment

0XX00 0000 RD

DWord read of APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h or Fh to

10000 0000 RD DWord read of RDP

10100 0000 RD DWord read of RAP

11000 0000 RD DWord read of Reset

0XX00 0000 WR

DWord write to APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h or Fh to

10000 0000 WR DWord write to RDP

10100 0000 WR DWord write to RAP

11000 0000 WR DWord write to Reset

112 Am79C973/Am79C975

PRELIMINARY

USER ACCESSIBLE REGISTERS

The Am79C973/Am79C975 controller has four types of

user registers: the PCI configuration registers, the Con-

trol and Sta tus regis ters (CSR), the Bus Control regis -

ters (BCR), and the PHY Management registers

(ANR).

The Am79C973/Am79C975 controller implements all

PCnet-ISA (Am79C960) registers, all C-LANCE

(Am79C9 0) regi sters, plus a number of ad dition al reg-

isters. The Am 79 C97 3/A m79 C975 CSRs are com pati-

ble upon power up with both the PCnet-ISA CSRs and

all of the C-LANCE CSRs.

The PCI configuration registers can be accessed in any

data width. All other registers must be accessed ac-

cording to the I/O mode that is currently selected.

When WIO mode is selected, all other register loca-

tions are defined to be 16 bits in width. When DWIO

mode is selected, all these register locations are de-

fined to be 32 bits in width, with the upper 16 bits of

most register locations marked as reserved locations

with u ndefin ed values. When per for min g re gister wr ite

operations in D WIO mode, the upper 16 bits should al-

ways be written as zeros. When performing register

read operations in DWIO mode, the upper 16 bits of

I/O resources should always be regarded as ha ving un-

defined values, except for CSR88.

The Am79C973/Am79C975 registers can be divided

into four groups: PCI Configuration, Setup, Running,

and Te st. Registers no t included in any of these cate-

gories can be assumed to be intended for diagnostic

purposes.

■PCI Configuration Registers

These registers are intended to be initialized by the

system initialization procedure (e.g., BIOS device ini-

tialization routine) to program the operation of the

Am79C973/Am79C975 controller PCI bus interface.

The following is a list of the registers that would typi-

cally need to be programmed once during the initializa-

tion of the Am79C973/Am79C975 controller within a

system:

—PCI I/O Base Address or Memory Mapped I/O

Base Address register

—PCI Expansion ROM Base Address register

—PCI Interrupt Line register

—PCI Latency T ime r regis te r

—PCI Status register

—PCI Command register

—OnNow register

■Setup Registers

These registers are intended to be initialized by the de-

vice driver to program the operation of various

Am79C973/Am79C975 controller features.

The following is a list of the registers that would typi-

cally ne ed to be pr ogrammed onc e during the setu p of

the Am79 C973/Am79C975 controller within a system .

The control bits in each of these registers typ ically do

not need to b e modified once they have been written.

However, there are no restrictions as to how many

times these registers may actually be accessed. Note

that if th e default power up value s of any of thes e reg-

isters is acceptable to the application, then such regis-

ters need never be accessed at all.

Note: Registers marked with “^” may be programma-

ble through the EEPROM read operation and, there-

fore, do not necessarily need to be written to by the

system initialization procedure or by the driver soft-

wa re. R egiste rs mark ed with “*” will be initialized by the

initialization block read operation.

CSR1 Initialization Bloc k Address[15:0]

CSR2* Initialization Block Address[31:16]

CSR3 Interrupt Masks and Deferr al Control

CSR4 Test and Features Control

CSR5 Extended Contr ol and Inte rr u pt

CSR7 Extended Contr ol and Inte rr u pt2

CSR8* Logical Address Filter[15:0]

CSR9* Logical Address Filter[31:16]

CSR10* Logical Address Filter[47:32]

CSR11* Logical Address Filter[63:48]

CSR12* Physical Add ress [1 5:0]

CSR13*^ Physical Address[31:16]

CSR14*^ Physical Address[47:32]

CSR15* Mode

CSR24* Base Address of Receive Ring Lower

CSR25* Base Address of Receive Ring Upper

CSR30* Base Address of Transmit Ring Lower

CSR31* Base Address of Transmit Ring Upper

CSR47* Transmit Polling Interval

CSR49* Receive Polling Interval

CSR76* Receive Ring Length

CSR78* Transmit Ring Length

CSR80 DMA Transfer Counter and FIFO Thresh-

old Control

Am79C973/Am79C975 113

PRELIMINARY

CSR82 Bus Activity Timer

CSR100 Memory Error Timeout

CSR116^ OnNow Miscellaneous

CSR122 Receiver Packet Alignment Control

CSR125^ MAC Enhanced Configuration Control

BCR2^ Miscella neou s Conf igu ratio n

BCR4^ LED0 Status

BCR5^ LED 1 Sta tus

BCR6^ LED 2 Sta tus

BCR7^ LED 3 Sta tus

BCR9^ Full-Duplex Control

BCR18^ Bus and Burst Control

BCR19 EEPROM Control and Status

BCR20 Software Style

BCR22^ PCI Latency

BCR23^ PCI Subsystem Vendor ID

BCR24^ PCI Subsystem ID

BCR25^ SRAM Size

BCR26^ SRAM Boundary

BCR27^ SRAM Interface Control

BCR32^ Internal PHY Control and Status

BCR33^ Internal PHY Address

BCR35^ PCI Vendor ID

BCR36 PCI Power Management Capabilities

(PMC) Alias Register

BCR37 PCI DATA Register Zero (DATA0) Alias

BCR38 PCI DATA Register One (DATA1) Alias

BCR39 PCI DATA Register Two (DATA2) Alias

BCR40 PCI DATA Register Three (DATA3) Alias

BCR41 PCI DATA Register Four (DATA4) Alias

BCR42 PCI DATA Register Five (DATA5) Alias

BCR43 PCI DATA Register Six (DATA6) Alias Reg-

ister

BCR44 PCI DATA Register Seven (DATA7) Alias

BCR45 OnNow Pa ttern Matchi ng Regi s ter 1

BCR46 OnNow Pattern Matching Register 2

BCR47 OnNow Pattern Matching Register 3

■Running Registers

These reg isters are in tended to be use d by the device

driver software after the Am79C973/Am79C975 con-

troller is running to access status information and to

pass control information.

The following is a list of the registers that would typi-

cally ne ed to be peri odically read and perhaps wr itten

during the normal running operation of the Am79C973/

Am79C975 controller within a system. Each of these

registers contains control bits, or status bits, or both.

RAP Register Address Port

CSR0 Am79C973/Am79C975 Controller Status

CSR3 Interrupt Masks and Deferral Control

CSR4 Test and Features Control

CSR5 Extended Control and Interrupt

CSR7 Extended Control and Interrupt2

CSR112 Missed Frame Count

CSR114 Receive Collision Count

BCR32 Internal PHY Control and Status

BCR33 Internal PHY Address

BCR34 Internal PHY Management Data

■Test Registers

These registers are intended to be used only f or testing

and diagnos ti c purp o ses. Those r egi ste r s not in cl ude d

in any of the above lists can be assumed to be intended

for diagnostic purposes.

PCI Configuration Registers

PCI Vendor ID Register

Offset 00h

The PCI V endor ID register is a 16-bit register that iden-

tifies the manufacturer of the Am79C973/Am79C975

controller. AMD’s Vendor ID is 1022h. Note that this

vendor ID is not the same as the Manufacturer ID in

CSR88 and CS R89. Th e vendor ID is assi gned by the

PCI Special Interest Group.

The PCI Vendor ID register is located at offset 00h in

the PCI C onfiguration Space. It is read only.

This register is the same as BCR35 and can be written

by the EEPROM.

PCI Device ID Register

Offset 02h

The PCI Device ID register is a 16-bit register that

uniquely identifies t he Am79C973/A m79C975 con trol-

114 Am79C973/Am79C975

PRELIMINARY

ler within AMD’s product line. The Am79C973/

Am79C975 Device ID is 2000h. Note that this Device

ID is not the same as the Par t number in CSR88 and

CSR89. The Device ID is assigned by AMD. The De-

vice ID is the same as the PCnet-PCI II (Am79C970A)

and PCnet-FAST (Am79C971) devices.

The PCI Device ID register is located at offset 02h in

the PCI Configuration Space. It is read only.

PCI Command Register

Offset 04h

The PCI Command register is a 16-bit register used to

control the gross functionality of the Am79C973/

Am79C975 controller. It controls the Am79C973/

Am79C975 controller’s ability to generate and respond

to PCI bus cycles. To logically disconnect the

Am79C9 73/Am7 9C975 d evice from a ll PCI bus cycles

ex cept configuration cycles, a value of 0 should be writ-

ten to this register.

The PCI Command register is located at offset 04h in

the PC I Configuration Sp ace. It is read a nd writt en by

the host.

Bit Name Description

15-10 RES Rese rved locations. Rea d as ze-

ros; write operations have no ef-

fect.

9 FBTBEN Fast Back-to-Back Enable. Read

as zero; write operations have no

effect. The Am79C973/

Am79C975 controller will not

generate Fast Back-to-Back cy-

cles.

8 SERREN SERR Enable. Controls the as-

ser tio n of t he S ERR pin. SERR is

disabled when SERREN is

cleared. SERR will be asserted

on detecti on of an addre ss p arity

error and if both SERREN and

PERREN (bit 6 of this register)

are set.

SERREN is cleared by

H_RESET and is not effecte d by

S_RESET or by setting the STOP

bit.

7 RES Reserved location. Read as ze-

ros; write operations have no ef-

fect.

6 PERREN Parity Error Response Enable.

Enables the parity error response

functions. When PERREN is 0

and the Am79C973/Am79C975

controller detects a parity error, it

only sets the Detect ed Parity Er-

ror bit in the PCI Status register.

When PERREN is 1, the

Am79C973/Am79C975 controller

asserts PERR on the detection of

a data parity error. It also sets the

DATAPERR bit (PCI Status reg-

ister, bit 8), when the data parity

error occurred during a master

cycle. PERREN also enables re-

porting address parity errors

through the SERR pin and the

SERR bit in the PCI Status regis-

ter.

PERREN is cleared by

H_RESET and is not affecte d by

S_RESET or by setting the STOP

bit.

5 VGASNOOP VGA Palette Snoop. Read as ze-

ro; write operations have no ef-

fect.

4 MWIE N Memo ry Wr it e and Inv ali da te Cy-

cle Enable. Read as zero; write

operations have no effect. The

Am79C973/Am79C975 controller

only generates Memory Write cy-

cles.

3 SCYCEN Special Cycle Enable. Read as

zero; write operations have no ef-

fect. The Am79C973/Am79C975

controller ignores all Special Cy-

cle operations.

2 BMEN Bus Master Enable. Setting

BMEN enables the Am79C973/

Am79C975 controller to become

a bus master on the PCI bus. The

host must set BMEN before set-

ting the INIT or STRT bit in CSR0

of the Am79C973/Am79C975

controller.

BMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

1 MEMEN Memory Space Access Enable.

The Am79C973/Am79C975 con-

troller will ignore all memory ac-

cesses when MEMEN is cleared.

The host must set MEMEN be-

fore the first memory access to

the device.

Am79C973/Am79C975 115

PRELIMINARY

For memory mapped I/O, the

host must program the PCI Mem-

ory Mapped I/O Base Address

dress before setting MEMEN.

For accesses to the Expansion

ROM, the host must pr ogram the

PCI Expansion ROM Base Ad-

dress register at offset 30h with a

valid memory address before set-

ting MEMEN. The Am79C973/

Am79C975 controller will only re-

spond to acce sses to the Expa n-

sion ROM when both ROMEN

(PCI Expansion ROM Base Ad-

dress register, bit 0) and MEMEN

are set to 1. Since MEMEN also

enables the memo ry mapped ac-

cess to the Am79C973/

Am79C975 I/O resources, the

PCI Memory Mapped I/O Base

Address register must be pro-

grammed with an address so that

the device does not claim cycles

not intended for it.

MEMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

0 IOEN I/O Space Access Enable. The

Am79C973/Am79C975 controller

will igno re all I/O accesses when

IOEN is cleared. The host must

set IOEN before the first I/O ac-

cess to the device. The PCI I/O

Base Address register must be

programmed with a valid I/O ad-

dress before setting IOEN.

IOEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

PCI Status Register

Offset 06h

The PCI Status register is a 16-bit register that contains

status information for the PCI bus related events. It is

located at offset 06h in the PCI Configuration Space.

Bit Name Description

15 PERR Parity Error. PERR is set when

the Am79C973/Am79C975 con-

troller detects a parity error.

The Am79C973/Am79C975 con-

troller samples the AD[31:0], C/

BE[3:0], and the PAR lines for a

parity error at the following times:

• In slave mode, during the ad-

dress phase of any PCI bus com-

mand.

• In slave mode , for al l I/O, m em-

ory and configuration write com-

mands that select the

Am79C973/Am79C975 controller

when data is transferred (TRDY

and IRDY are asserted).

• In master mode, during the data

phase of all memory read com-

mands.

In master mode, during the data

phase of the memory write com-

mand, the Am79C973/

Am79C975 controller sets the

PERR bit if the target reports a

data pari ty error by ass erting the

PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (PCI Command register,

bit 6).

PERR is set by the Am79C973/

Am79C975 controller and

cleared by writing a 1. Writing a 0

has no effect. PERR is cleared by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

14 SERR Signaled SERR. SERR is set

when the Am79C973/Am79C975

controller detects an address par-

ity error and both SERREN and

PERREN (PCI Command regis-

ter, bits 8 and 6) are set.

SERR is set by the Am79C973/

Am79C975 controller and

cleared by writing a 1. Writing a 0

has no effect. SERR is cleared by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

13 RMABORT Received Master Abort. RM-

ABORT is set when the

Am79C973/Am79C975 controller

terminates a master cycle with a

master abort sequence.

116 Am79C973/Am79C975

PRELIMINARY

RMABORT is set by the

Am79C973/Am79C975 controller

and cleared by writing a 1. Writ-

ing a 0 has no effect. RMABORT

is cleared by H_RESET and is

not affected by S_RESET or by

setting the STOP bit.

12 RTABORT Received Target Abort. RT-

ABORT is set when a target ter-

minates an Am79C973/

Am79C975 master cycle with a

target abort sequence.

RTABORT is set by the

Am79C973/Am79C975 controller

and cleared by writing a 1. Writ-

ing a 0 has no effect. RTABORT

is cleared by H_RESET and is

not affected by S_RESET or by

setting the STOP bit.

11 STABORT Send Target Abort. Read as ze-

ro; write operations have no ef-

fect. The Am79C973/Am79C975

controller will never terminate a

slave access with a target abort

sequence.

STABORT is read only.

10-9 DEVSEL Device Select Timing. DEVSEL

is set to 01b (medium), which

means that the Am79C973/

Am79C975 controller will assert

DEVSEL two clock periods after

FRAME is asse rted.

DEVSEL is read only.

8 DATAPERR Data Parity Error Detected.

DATAPERR is set when the

Am79C973/Am79C975 controller

is the current bus master and it

detects a data parity error and the

Parity E rror Response en able bit

(PCI Command register, bit 6) is

set.

During the data phase of all

memory read commands, the

Am79C973/Am79C975 controller

checks for parity error by sam-

pling the A D[31:0] and C /BE[3:0]

and the PAR lines. During the

data phase of all memory write

commands, the Am79C973/

Am79C975 controller che cks the

PERR input to detect whether the

target has reported a parity error.

DATAPERR is set by the

Am79C973/Am79C975 controller

and cleared by writing a 1. Writ-

ing a 0 has no effect. DATAPERR

is cleared by H_RESET and is

not affected by S_RESET or by

setting the STOP bit.

7 FBTBC Fast Back-To-Back Capable.

Read as one; write operations

have no effect. The Am79C973/

Am79C975 controller is capable

of accepting fast back-to-back

transactions with the first transac-

tion addressing a different target.

6-5 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

4 NEW_CAP New Capabilities. This bit indi-

cates whether this function imple-

ments a list of extended

capabilities such as PCI power

management. When set, this bit

indicates the presence of New

Capabilities. A value of 0 means

that this fu nction does n ot imple-

ment New Capabilities.

Read as one; write operations

have no effect. The Am79C973/

Am79C975 controller supports

the Linked Additional Capabilities

List.

3-0 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

PCI Revision ID Register

Offset 08h

The PCI Revision ID register is an 8-bit register that

specifies the Am79C973/Am79C975 controller re vision

number . The value of this register is 4Xh with the lower

four bits being silicon-revision dependent.

The PCI Revision ID register is located at offset 08h in

the PCI C onfiguration Space. It is read only.

PCI Programming Interface Register

Offset 09h

The PCI Programming Interface register is an 8-bit reg-

ister that identifies the programming interface of

Am79C 973/ Am 79C9 75 c ontrol le r. PCI does not de fin e

Am79C973/Am79C975 117

PRELIMINARY

any specific register-level programming interfaces for

network devices. The value of this register is 00h.

The PCI Programming Interface register is located at

offset 09h in the PCI Configuration Space. It is read only .

PCI Sub-Class Register

Offset 0Ah

The PCI Sub-Class register is an 8-bit register that iden-

tifies specifically the function of the Am79C973/

Am79C9 75 co ntrolle r. The value of th is reg ister i s 00 h

which identifies the Am79C973/Am79C975 device as

an Ethernet co ntrol ler.

The PCI Sub- Class regist er is loca ted at offset 0Ah in

the PCI Configuration Space. It is read only.

PCI Base-Class Register

Offset 0Bh

The PCI Base-Class register is an 8-bit register that

broadly classifies the function of the Am79C973/

Am79C9 75 co ntrolle r. The value of th is reg ister i s 02 h

which classifies the Am79C973/Am79C975 device as

a network controller.

The PCI Base-Class register is located at offset 0Bh in

the PCI Configuration Space. It is read only.

PCI Latency Timer Register

Offset 0Dh

The PCI Latency Timer register is an 8-bit register that

specifies the minimum guaranteed time the Am79C973/

Am79C975 c ontrol ler will contr ol the bus once it starts

its bus mastership period. The time is measured in clock

cycle s. Ever y ti me the Am 79C973 /Am 79C975 cont rol-

ler asserts FRAME at the beginning of a bus mastership

peri od, it will copy the value of the PCI L atency Timer

counter will freeze at 0. When the system arbiter re-

moves GNT while the counter is non-zero, the

Am79C973/ Am79C975 controller will continue with its

data transfers. It will only release the bus when the

counter has reached 0.

The PCI Latency Timer is only significant in b urst trans-

actions, where FRAME stays asserted until the last data

phase. In a non-burst transaction, FRAME is only as-

ser ted dur ing the addres s phase. The inter nal laten cy

counter will be cleared and suspended while FRAME is

deasserted.

All eight bits of the PCI Latency Timer register are pro-

grammable. The host should read the Am79C973/

Am79C975 PCI MIN_GNT and PCI MAX_LA T registers

to determine the latency requirements for the device

and then initialize the Latency Timer register with an

appropriate value.

The PCI Latency Timer register is located at offset 0Dh

in the PCI Configuration Space. It is read and written by

the host. T h e PC I L aten cy T imer r egis ter is c le ared by

H_RESET and is not effected by S_RESET or by setting

the STOP bit.

PCI Header Type Register

Offset 0Eh

The PCI Header Type register is an 8-bit register that

describes the format of the PCI Configuration Space

loca tions 10 h t o 3Ch and th at identi fies a device to b e

single o r multi-functi on. The PCI H eader Ty pe register

is located at address 0Eh in the PCI Configuration

Space. It is read only.

Bit Name Description

7 FUNCT Sin gle-func tion/m ul ti-fun ct ion de-

vice. Read as zero; write opera-

tions have no effect. The

Am79C973/Am79C975 controller

is a single function device.

6-0 LAYOUT PCI configuration space layout.

Read as zeros; write operations

have no effect. The layout of th e

PCI configuration space loca-

tions 10h to 3Ch is as shown in

the table at the beginning of this

section.

PCI I/O Base Address Register

Offset 10h

The PCI I/O Base Address register is a 32-bit register

that determines the location of the Am79C973/

Am79C975 I/O resources in all of I/O space. It is located

at offset 10h in the PCI Configuration Space.

Bit Name Description

31-5 IOBASE I/O base address most significant

27 bits. These bit s are written by

the host to s pe cify the l ocati on o f

the Am79C973/Am79C975 I/O

reso urces in a ll of I/O space. IO-

BASE must be written with a valid

address before the Am79C973/

Am79C975 controller slave I/O

mode is turned on by setting the

IOEN bit (PCI Command register,

bit 0).

When the Am79C973/

Am79C975 controller is enabled

for I/O mode (IOEN is set), it

monitors the PCI bus for a valid I/

O command. If the value on

AD[31:5] during the address

phase of the cycles matches the

value of IOBASE, the

Am79C973/Am79C975 controller

118 Am79C973/Am79C975

PRELIMINARY

will drive DEVSEL indicating it

will respond to the a ccess.

IOBASE is read and written by

the host. IOBASE is cleared by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

4-2 IOSIZE I/O size requirements. Read as

zeros; write operations have no

effect.

IOSIZE indicates the size of the

I/O space the Am79C973/

Am79C975 controller requires.

When the host writes a value of

FFFF FFFFh to the I/O Base Ad-

dress reg ister, it will read back a

value of 0 in bits 4-2. That indi-

cates an Am79C973/Am79C975

I/O space requirement of 32

bytes.

1 RES Reserved location. Read as zero;

write operatio ns hav e no effec t.

0 IOSPACE I/O space indicator. Read as one;

write operations have no effect.

Indicating that this base address

address.

PCI Memory Mapped I/O Base Address Register

Offset 14h

The PCI Memory Mapped I/O Base Address register is

a 32-bit register that determines the location of the

Am79C973/Am79C9 75 I/O r esources in al l of mem ory

space. It is located at offset 14h in the PCI Configuration

Space.

Bit Name Description

31-5 MEMBASE Memory mapped I/O base ad-

dress most significant 27 bits.

These bits are written by the host

to specify the location of the

Am79C973/Am79C975 I/O re-

sources in all of memory space.

MEMBASE must be written with a

valid address before the

Am79C973/Am79C975 controller

slave mem ory mapped I/O mode

is turned on by setting the ME-

MEN bit (PCI Command register,

bit 1).

When the Am79C973/

Am79C975 controller is enabled

for memory mapped I/O mode

(MEMEN is set), it monitors the

PCI bus fo r a val id me mory c om-

mand. If the value on AD[31:5]

during the address phase of the

cycles matches the value of

MEMBASE, the Am79C973/

Am79C975 controller will drive

DEVSEL indicating it will respond

to the access.

MEMBASE is read and written by

the host. MEMBASE is cleared

by H_RES ET and is not affe cted

by S_RESET or by setting the

STOP bit.

4 MEMSIZE Memory mapped I/O size re-

quirements. Read as zeros; write

operations have no effect.

MEMSIZE indicates the size of

the memory space the

Am79C973/Am79C975 controller

requires. When the host writes a

value of FFFF FFFFh to the

Memory Mapped I/O Base Ad-

dress reg ister, it will read back a

value of 0 in bit 4. That indicates

a Am79C973/Am79C975 memo-

ry space requirement of 32 bytes.

3 PREFETCH Prefetchable. Read as zero; write

operations have no effect. Indi-

cates that memory space con-

trolled by this base address

registe r is not prefetch able. Data

in the memory mapped I/O space

cannot be prefetched. Because

one of the I/O resources in this

address space is a Reset regis-

ter, the order of the read access-

es is important.

2-1 TYPE Memory type indicator. Read as

zeros; write operations have no

effect. Indicates that this base ad-

dress reg is ter is 3 2 bi ts wid e an d

mapping can be done anywhere

in the 32-bit memory space.

0 MEMSPACE Memory space indicator. Read

as zero; write operations have no

effect. Indicates that this base ad-

dress register describes a memo-

ry base address.

Am79C973/Am79C975 119

PRELIMINARY

PCI Subsystem Vendor ID Register

Offset 2Ch

The PCI Sub sys tem Vendor ID r eg ister is a 1 6- bit re g-

ister that together with the PCI Subsystem ID uniquely

identifies the add-in card or subsystem the Am79C973/

Am79C975 controller is used in. Subsystem Vendor

IDs can be obtained from the PCI SIG. A value of 0 (the

default) indica tes th at th e A m79 C973/Am79 C975 con-

troller does not suppor t subsystem identification. The

PCI Subsystem Vendor ID is an alias of BCR23, bits

15-0. It is programmable through the EEPROM.

The PCI Subsystem V endor ID register is located at off-

set 2 C h i n t h e P CI C o nf i gu r a t ion Sp ac e. It is re ad on l y.

PCI Sub system ID Register

Offset 2Eh

The PCI Subsy ste m ID regis ter is a 16-b it regi ste r tha t

together with the PCI Subsystem Vendor ID uniquely

identifies the add-in card or subsystem the Am79C973/

Am79C975 controller is used in. The value of the Sub-

system ID is up to the system vendor . A value of 0 (the

default) indica tes th at th e A m79 C973/Am79 C975 con-

troller does not suppor t subsystem identification. The

PCI Subsystem ID is an alias of BCR24, bits 15-0. It is

programmable through the EEPROM.

The PCI Subsystem ID register is located at offset 2Eh

in the PCI Configuration Space. It is read only.

PCI Expansion ROM Base Address Register

Offset 30h

The PCI Expansion ROM Base Address register is a

32-bit regis ter that defi nes the base addre ss, size and

address alig nment of an Expa nsion ROM. It is locate d

at offset 30h in the PCI Configuration Space.

Bit Name Description

31-20 ROMBASE Expansion ROM base address

most significant 12 bits. These

bits are written by the host to

specify the location of the Expan-

sion ROM i n all of memory space.

ROMBASE must be written with a

valid address before the

Am79C973/Am79C975 Expan-

sion ROM access is enabled by

setting ROMEN (PCI Expansion

ROM Base Address register, bit

0) and MEMEN (PCI Command

registe r, bit 1).

Since the 12 mos t signific ant bits

of the base address are program-

mable, th e host c an map the Ex-

pansion ROM on any 1M

boundary.

When the Am79C973/

Am79C975 controller is enabled

for Expansion ROM access

(ROMEN and MEMEN a re set to

1), it monitors the PCI bus for a

valid memory command. If the

value on AD[31:2] du ring the ad-

dress phas e of th e c ycl e fa ll s be-

tween ROMBASE and

ROMBASE + 1M - 4, the

Am79C973/Am79C975 controller

will drive DEVSEL indicating it

will respond to the access.

ROMBASE is read and written by

the host. ROMBASE is cleared

by H_RES ET and is not affe cted

by S_RESET or by setting the

STOP bit.

19-1 ROMSIZE ROM size. Read as zeros; write

operation have no effect. ROM-

SIZE indicates the maximum size

of the Expansion ROM the

Am79C973/Am79C975 controller

can supp ort. The hos t can deter-

mine the Expansion ROM size by

writing FFFF FFFFh to the Ex-

pansion ROM Base Address reg-

ister. It will read back a value of 0

in bit 19-1, indicating an Expan-

sion ROM size of 1M.

Note that ROMSIZE only speci-

fies the maximum size of E xpan-

sion ROM the Am79C973/

Am79C975 controller supports. A

smaller ROM can be used, too.

The actual size of the code in the

Expansi on ROM is al ways deter-

mined by reading the Expansion

ROM header.

0 ROMEN Expansion ROM Enable. Written

by the host to enable access to

the Expansion ROM. The

Am79C973/Am79C975 controller

will only respond to accesses to

the Expansion ROM when both

ROMEN and MEMEN (PCI Com-

mand register, bit 1) are set to 1.

ROMEN is read and written by

the host. ROMEN is cleared by

H_RESET an d is not effected by

S_RESET or by setting the STOP

bit.

120 Am79C973/Am79C975

PRELIMINARY

PCI Capabilities Pointer Register

Offset 34h

Bit Name Description

7-0 CAP_PTR The PCI Capabilities pointer

points to a linked list of capabili-

ties implemented on this device.

This register has a default value

of 40h.

The PCI Capabilities register is

located at offset 34h in the PCI

Configuration Space. It is read

only.

PCI Interrupt Line Register

Offset 3Ch

The PCI Inter rupt Line registe r is an 8-bit register tha t

is used to communicate the routing of the interrupt.

This reg ister is wr itten by the POST software as it ini-

tializes the Am79C973/Am79C975 controller in the

system. The register is read by the network driver to

deter mine the interrupt channel which the POST so ft-

ware has a ss igned to the Am79C973/Am79C9 75 con-

troller. The PCI Interrupt Line register is not modified by

the Am79C973/Am79C975 controller. It has no effect

on the operation of the device.

The PCI Inte rr u pt Li ne r eg ister is lo ca ted a t offs et 3C h

in the PCI Configuration Space. It is read and written by

the host. It i s clea re d by H_RESE T a nd i s no t affected

by S_RESET or by setting the STOP bit.

PCI Interrupt Pin Register

Offset 3Dh

This PCI Interrupt Pin register is an 8-bit register that

indicates the interrupt pin that the Am79C973/

Am79C975 controller is using. The value for the

Am79C973/Am79C975 Interrupt Pin register is 01h,

which corresponds to INTA.

The PCI Interrupt Pin register is locate d at offset 3Dh

in the PCI Configuration Space. It is read only.

PCI MIN_GNT Register

Offset 3Eh

The PCI MIN_GNT register is an 8-bit register that

specifies the minimum length of a burst period that the

Am79C973/Am79C975 device needs to keep up with

the network activity. The length of the burst period is

calculated assuming a clock rate of 33 MHz. The regis-

ter value speci fie s t he ti me in units of 1 /4 m s. The P C I

MIN_GNT register is an alias of BCR22, bits 7-0. It is

recommended that the BCR22 be programmed to a

value of 1818h.

The host s hould use the value in thi s register to deter-

mine the setting of the PCI Latenc y Timer regis ter.

The PCI MIN_GNT register is loca ted at offset 3Eh in

the PCI C onfiguration Space. It is read only.

PCI MAX_LAT Register

Offset 3Fh

The PCI MAX_LA T register is an 8-bit register that spec-

ifies the maximum arbitration latency the Am79C973/

Am79C975 controller can sustain without causing prob-

lems to the network activity . The register value specifies

the time in units of 1/4 µs. The MAX_LAT register is an

alias of BCR22, bits 15-8. It is recommended that

BCR22 be programmed to a value of 1818h.

The host s hould use the value in thi s register to deter-

mine the setting of the PCI Latenc y Timer regis ter.

The PCI MAX_LAT register is located at offset 3Fh in

the PCI C onfiguration Space. It is read only

PCI Capability Identifier Register

Offset 40h

Bit Name Description

7-0 CAP_ID This register, when set to 1, iden-

tifies th e linked list item as b eing

the PCI Power Management reg-

isters. T his regis ter has a de fault

value of 1h.

The PCI Capabilities Identifier

the PCI Configuration Space. It is

read only.

PCI Next Item Pointer Register

Offset 41h

Bit Name Description

7-0 NXT_ITM_PTR

The Next Item Pointer Register

points to the starting address of

the next capability. The pointer at

this offset is a null pointer, indi-

cating that this is the last capabil-

ity in the linked list of the

capabilities. This register has a

default value of 0h.

The P CI Next P ointe r Regist er is

located at offset 41h in the PCI

Configuration Space. It is read

only.

Am79C973/Am79C975 121

PRELIMINARY

PCI Power Management Capabilities Register

(PMC)

Offset 42h

Note: All bits of this register are loaded from

EEPROM. The r egi st er is al ias ed to B CR36 for testin g

purposes.

Bit Name Description

15-11 PME_SPT PME Support. This 5-bit field indi-

cates the power states in which

the function may assert PME. A

value of 0b for any bit indicates

that the function is not capable of

ass er t ing t h e PM E signal while in

that power state.

Bit(11) XXXX1b - PME can be

asserted from D0.

Bit(12) XXX1Xb - PME can be

asserted from D1.

Bit(13) XX1XXb - PME can be

asserted from D2.

Bit(14) X1XXXb - PME can be

asserted from D3hot.

Bit(15) 1XXXXb - PME can be

asserted from D3cold.

Read only.

Bit 15 of the PMC register indi-

cates that the controller is capa-

ble of generating PME from the

D3 cold state. This capability de-

pends on the presence of auxilia-

ry power, as indicated by the

AUXDET input. The capability

can be disabled by loading a zero

in to bit 15 of BCR3 6 from th e EE-

PROM. (This register is aliased to

the PMC registe r. )

10 D2_SPT D2 Support. If this bit is a 1, this

function supports the D2 Power

Management State.

Read only.

9 D1_SPT D1 Sup port. If this bit is a 1, this

function supports the D1 Power

Management State.

Read only.

8-6 RES Reserved locations. Written as

zeros and read as undefined.

5 DSI Device Specific Initialization.

When this bit is 1, it indicates that

special initialization of the func-

tion is requir ed (b eyo nd the st an-

dard PCI configuration header)

before the generic class device

driver is able to use it.

Read onl y.

4 RES Reserved locations. Written as

zeros and read as undefined.

3 PME_ CLK PME Cloc k. When this bit is a 1 ,

it indicates that the function relies

on the presence of the PCI clock

for PME operation . When this bi t

is a 0 it indicates that no PCI

clock is required for the function

to generate PME.

Functions that do not support

PME generation in any state

must return 0 for this field.

Read onl y.

2-0 PMIS_VER Power Management Interface

Specification Version. A value of

001b indicates that this function

complies with the revision 1.1 of

the PCI Power Management In-

terface Specification.

PCI Power Management Control/Status Register

(PMCSR)

Offset 44h

Bit Name Description

15 PME_STATUS PME Status. This bit is set when

the function would normally as-

sert the PME s ignal independen t

of the state of the PME_EN bit.

Writing a 1 to this bit will clear it

and cause the function to stop as-

serting a PME (if enabled). Writ-

in g a 0 has no effect.

If the function supports PME from

D3cold then this bit is sticky and

must be explicitly cleared by the

operating system each time the

operating system is initially load-

ed.

122 Am79C973/Am79C975

PRELIMINARY

Read/write accessible always.

Sticky bit. This bit is reset by

POR. H_RESET, S_RESET, or

setting the STOP bit has no ef-

fect.

14-13 DATA_SCALE

Data Scale. This two bit read-

only field indicates the scaling

factor to b e used when inter pret-

ing the value of the Data register.

The value and meaning of this

field will vary depending on the

DATA_SCALE field.

Read only.

12-9 DATA_SEL Data Select. This optional four-bit

field is used to select which data

is repo rted thro ugh the Data reg-

ister and DATA_SCALE field.

Read/write accessible always.

Sticky bit. This bit is reset by

POR. H_RESET, S_RESET, or

setting the STOP bit has no ef-

fect.

8 PME_EN PME Enable. When a 1,

PME_EN en ables the functi on to

assert PM E. When a 0, PME as-

sertion is disabled.

This bit defaults to “0” if the func-

tion does not support PME gener-

ation from D3cold.

If the function supports PME from

D3cold, the n this bi t is stic ky and

must be explicitly cleared by the

operating system each time the

operating system is initially loa d-

ed.

Read/write accessible always.

Sticky bit. This bit is reset by

POR. H_RESET, S_RESET, or

setting the STOP bit has no ef-

fect.

7-2 RES Reserved locations. Read only.

1-0 PWR_STATE Power State. This 2-bit field is

used both to determine the cur-

rent power state of a function and

to set the function into a new

power sta te. The de fin ition of th e

field values is given below.

00b - D0.

01b - D1.

10b - D2.

11b - D3.

These bits can be written and

read, but their contents have no

effect on th e operat ion o f the de-

vice.

Read/ write ac ces s ib le alwa ys .

PCI PMCSR Bridge Support Extensions Register

Offset 46h

Bit Name Description

7-0 PM CSR_BSE The P CI PM CSR Bridge S upport

Extensions Register is an 8-bit

Extensions are not supported.

This register has a default value

of 00h.

The P CI PM CSR B ri dge S upp ort

Extensions register is located at

offset 46h in the PCI Configura-

tion Space. It is read only.

PCI Data Register

Offset 47h

Note: All bits of this register are loaded from EE-

PROM. The register is aliased to lower bytes of the

BCR37-44 for testing purposes.

Bit Name Description

7-0 DATA_REG The PCI Data Register is an 8-bit

Power Management Interface

Specification” version 1.1 for a

more detailed description of this

The PCI DATA register is located

at offset 47h in the PCI Configu-

ration Space. It is read only.

RAP Register

The RAP (Register Address P ointer) register is used to

gain access to CSR and BCR registers on board the

Am79C973/Am79C975 controller. The RAP contains

the address of a CSR or BCR.

As an example of R AP use, con si der a r ead ac ces s t o

CSR4. In order to access this register, it is necessar y

to first load the value 0004h into the RAP by performing

a wri te ac cess t o the RAP o ffset of 12h ( 12h wh en WI O

mode has been selected, 14h when DWIO mode has

Am79C973/Am79C975 123

PRELIMINARY

been selected). Then a second access is performed,

this time to the RDP offset of 10h (for either WIO or

DWIO mode). The RDP access i s a read acce ss, and

since RAP has just been loaded with the value of 0004h,

the RDP read will yield the contents of CSR4. A read of

the BDP at this time (offset of 16h when WIO mode has

been selected, 1Ch when DWIO mode has been select-

ed) will yield the contents of BCR4, since the RAP is

used as the pointer into both BDP and RDP space.

RAP: Register Address Port

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 RES Reserved locations. Read and

written as zeros.

7-0 RAP Register Address Port. The value

of these 8 bits determines which

CSR or BCR will be accessed

when an I/O access to the RDP

or BDP po rt, respectiv ely, is per-

formed.

A write acces s to undefi ned CSR

or BCR lo cations may cause un-

expected reprogramming of the

Am79C973/Am79C975 control

registers. A read access will yield

undefin ed va lue s.

Read/Write accessible always.

RAP is cleared by H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

Control and Status Registers

The CSR spac e is accessible by performing ac cesses

to the RDP (Register Data Port). The particular CSR

that is read or written during an RDP access will depend

upon the current setting of the RAP. RAP ser ves as a

pointer into the CSR space.

CSR0: Am79C973/Am79C975 Controller Status and

Contr ol Register

Certain bits in CSR0 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR0 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 ERR Error is set by the OR of CERR,

MISS, and MERR. ERR remains

set as long as any of the error

flags are true.

Read accessible always. ERR is

read only. Write operations are

ignored.

14 RES Reserved locations. Read/Write

accessible always. Read returns

zero.

13 CERR Collision Error is set by the

Am79C973/Am79C975 controller

when the device operates in half-

duplex m ode and the c oll is i on in -

puts (10 Mbps) failed to activate

within 20 network bit times after

the chip terminated transmission

(SQE Test). This feature is a

10BASE-T PHY test feature.

CERR reporting is disabled when

the Am79C973/Am79C975 con-

troller operates in full-duplex

mode.

When the MII port is selected,

CERR is only reported when the

external PHY is operating as a

half-duplex 10BASE-T PHY.

CERR assertion will not result in

an interrupt being generated.

CERR as ser tion w ill s et the E RR

bit.

Read/Write accessible always.

CERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. CERR is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

12 MISS Missed Frame is set by the

Am79C973/Am79C975 controller

when it has lost an incoming re-

ceive frame resulting from a Re-

ceive Descriptor not being

available. This bit is the only im-

mediate indication that receive

data has been lost since there is

no current receive descriptor.

The Missed Frame Counter

(CSR112) also increments each

time a receive frame is missed.

When MISS is set, INTA is as-

serted if IENA is 1 and the mask

124 Am79C973/Am79C975

PRELIMINARY

bit MISSM (CSR3, bit 12) is 0.

MISS assertion will set the ERR

bit, regardless of the settings of

IENA and MISSM.

Read/Write accessible always.

MISS is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MISS is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

11 MERR Memory Error is set by the

Am79C973/Am79C975 controller

when it requests the use of the

system interface bus by asserting

REQ and has not received GNT

assertion after a programmable

length of ti me. Th e l eng th of tim e

in micro seconds before MERR is

asserted will depend upon the

setting of the Bus Timeout Regis-

ter (CSR100). The default setting

of CSR100 will give a MERR after

153.6 ms of bus latency.

When MERR is set, INTA is as-

serted i f IENA is 1 and the ma sk

bit MERRM (CSR3, bit 11) is 0.

MERR assertion wil l set the E RR

bit, regardless of the settings of

IENA and MERRM.

Read/Write accessible always.

MERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MERR is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

10 RINT Receive Interrupt is set by the

Am79C973/Am79C975 controller

after the last descriptor of a re-

ceive frame has been updated by

writing a 0 to the O WNership bit.

RINT may also be set when the

first de scr ipt or of a recei ve fr am e

has been updated by writing a 0

to the OWNership bit if the LAP-

PEN bit of CS R3 ha s b een set to

a 1.

When RINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

RINTM (CSR3, bit 10) is 0.

Read/Write accessible always.

RINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. RINT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

9 TINT Transmit Interrupt is set by the

Am79C973/Am79C975 controller

after the OWN bit in the last de-

scriptor of a transmit frame has

been cleared to indicate the

frame has been sent or an error

occurred in the transmission.

When TINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

TINTM (CSR3, bit 9) is 0.

TINT will not be set if TINTOKD

(CSR5, bit 15) is set to 1 and the

transmission was successful.

Read/Write accessible always.

TINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. TINT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

8 IDON Initialization Done is set by the

Am79C973/Am79C975 controller

after the initialization sequence

has completed. When IDON is

set, the Am79C973/Am79C975

controller has read the initializa-

tion block from memory.

When IDON is set, INTA is as-

serted if IENA is 1 and the mask

bit IDONM (CSR3, bit 8) is 0.

Read/Write accessible always.

IDON is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. IDON is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

7 INTR Interrupt Flag indicates that one

or more following interrupt caus-

ing conditions has occurred:

EXDINT, IDON, MERR, MISS,

MFCO, RCVCCO, RINT, SINT,

TINT, TXSTRT, UINT, STINT,

MREINT, MCCINT, MIIPDTINT,

MAPINT and the associated

mask or enable bit is pro-

grammed to allow the event to

cause an interrupt. If IE NA is set

to 1 and INTR is set, INTA will be

active. When INTR is set by SINT

Am79C973/Am79C975 125

PRELIMINARY

or SLPINT, INTA will be active in-

dependent of the state of INEA.

Read access ible al ways. INT R is

read only. INTR is cleared by

clearing all of the active individual

interrupt bits that have not been

masked out.

6 IENA Interrupt Enable allows INTA to

be active if the Interrupt Flag is

set. If IENA = 0, then INTA will be

disabled regardless of the state

of INTR.

Read/Write accessible always.

IENA is set by writing a 1 and

cleared by writing a 0. IENA is

cleared by H_RESET or

S_RESET and set ting the STOP

bit.

5 RXO N Receive On indicates that the re-

ceive fun ction is enabled. RXON

is set if DRX (CSR15, bit 0) is set

to 0 after the START bit is set. If

INIT and START are set together,

RXON will not be set until after

the initialization block has been

read in.

Read accessible always. RXON

is read on ly. RXON is c leared by

H_RESET or S_RESET and s et-

ting the STOP bit.

4 TXON Transmit On indicates that the

transmit function is enabled.

TXON is set if DTX (CSR15, bit 1)

is set to 0 after the START bit is

set. If INIT and START are set to-

gether, TXON will not be set until

after the initialization block has

been read in.

This bit will reset if the DXSUFLO

bit (CSR3, bit 6) is reset and there

is an underflow condition encoun-

tered.

Read accessible always. TXON

is read only. TXO N is cleared by

H_RESET or S_RESET and s et-

ting the STOP bit.

3 TDMD Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit De-

scriptor Ring without waiting for

the poll- time cou nter t o elapse. If

TXON is not enabled, TDMD bit

will be reset and no Transmit De-

scripto r Ring access will occur.

TDMD is re quired to be set i f the

TXDPOLL bit in CSR4 is set. Set-

ting TDMD while TXDPOLL = 0

merely hastens the Am79C973/

Am79C975 controller’s response

to a Transmit Descriptor Ring En-

try.

Read/Write accessible always.

TDMD is set by writi ng a 1. Writ-

ing a 0 has no effect. TDMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a

Transmit Descriptor. TDMD is

cleared by H_RESET or

S_RESET and setting the STOP

bit.

2 STOP STOP assertion disables the chip

from all DMA activity. The chip re-

mains inactive until either STRT

or INIT are set. If STOP, STRT

and INIT are all set together,

STOP will override STRT and

INIT.

Read/Write accessible always.

STOP is set by writing a 1, by

H_RESET or S_RESET. Writing

a 0 has no effect. STOP is

cleared by setting either STRT or

INIT.

1 STRT STRT assertion enables

Am79C973/Am79C975 controller

to send and receive frames, and

perform buffer management op-

erations. Setting STRT clears the

STOP bit. If STRT and INIT are

set together, the Am79C973/

Am79C975 controller initializa-

tion will be performed first.

Read/Write accessible always.

STRT is set by writing a 1. Writing

a 0 has no effect. STRT is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

0 INIT INIT assertion enables the

Am79C973/Am79C975 controller

to begin the initialization proce-

dure whic h reads in th e initial iza-

tion block from memory. Setting

126 Am79C973/Am79C975

PRELIMINARY

INIT clears the STOP bit. If STRT

and INIT are set together, the

Am79C973/Am79C975 controller

initialization will be performed

first. INIT is not cleared when the

initialization sequence has com-

pleted.

Read/Write accessible always.

INIT is se t by wr iting a 1. Wri ting

a 0 has no e ffect. INIT is cleare d

by H_RESET, S_RESET, or by

setting the STOP bit.

CSR1: Initialization Block Address 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADR[15:0] Lower 16 bits of the address of

the Initialization Block. Bit loca-

tions 1 and 0 must both be 0 to

align the initialization block to a

DWord boundary.

This register is aliased with

CSR16.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. Unaffected by H_RESET

or S_RESET, or by setting the

STOP bit.

CSR2: Initialization Block Address 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 IADR[31:24] If S SIZE32 is s et (BCR20, b it 8),

then the IADR[31:24] bits will be

used strictly as the upper 8 bits of

the initialization block address.

However, if SSIZE32 is reset

(BCR20, bit 8), then the

IADR[31:24] bits will be used to

generate the upper 8 bits of all

bus mastering addresses, as re-

quired for a 32-bit address bus.

Note that the 16-bit software

structures specified by the

SSIZE32 = 0 setting will yield

only 24 bits of address for the

Am79C973/Am79C975 bus mas-

ter accesses, while the 32-bit

hardware for which the

Am79C973/Am79C975 controller

is intended will require 32 bits of

address. Therefore, whenever

SSIZE32 = 0, the IADR[31:24]

bits will be appended to the 24-bit

initiali zation add ress , to eac h 24-

bit descriptor base address and

to each beginning 24-bit buffer

address in order to form complete

32-bit addresses. The upper 8

bits that exist in the descriptor ad-

dress registers and the buffer ad-

dress registers which are stored

on board the Am79C973/

Am79C975 controller will be

overwritten with the IADR[31:24]

value, so that CSR accesses to

these registers will show the 32-

bit address that includes the ap-

pended field.

If SSIZE32 = 1, then software will

provide 32-bit pointer values for

all of the shared software struc-

tures - i.e., descriptor bases and

buffer addresses, and therefore,

IADR[31: 24] will not be written to

the upper 8 bits of any of these

resources, but it will be used as

the upper 8 bits of the initializa-

tion address.

This register is aliased with

CSR17.

Read/Write accessible only when

either the STO P or the SPND bit

is set. Unaffected by H_RESET,

S_RESET, or by setting the

STOP bit.

7-0 IADR[23:16] Bits 23 through 16 of the address

of the Initialization Block. When-

ever this register is written,

CSR17 is updated with CSR2’s

contents.

Read/Write accessible only when

either the STO P or the SPND bit

is set. Unaffected by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR3: Interrupt Masks and Deferral Control

Am79C973/Am79C975 127

PRELIMINARY

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-13 RES Reserved locations. Read and

written as zero.

12 MISSM Missed Frame Mask. If MISSM is

set, the MISS bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

MISSM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

11 MERRM Memory Error Mask. If MERRM

is set, the MERR bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

MERRM is clea red by H_RESE T

or S_RESET and is not affected

by STOP.

10 RINTM Receive Interrupt Mask. If RINTM

is set, the RINT bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

RINTM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

9 TINTM Transmit Interrupt Mask. If

TINTM is set , th e TINT b it wi ll b e

masked and unable to set the

INTR bit.

Read/Write accessible always.

TINTM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

8 IDONM Initialization Done Mask. If

IDONM is set, the IDON bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

IDONM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

7 RES Reserved location. Read and

written as zeros.

6 DXSUFLO Disable Transmit Stop on Under-

flow error.

When DXSUFLO (CSR3, bit 6) is

set to 0, the transmitter i s turned

off when an UFLO error occurs

(CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C973/Am79C975 controller

gracefully recovers from an

UFLO error. It scans the transmit

descriptor ring until it finds the

start of a new fram e and starts a

new transmission.

Read/Write accessible always.

DXSUFLO is cleared by

H_RESET or S_RESET and is

not affected by STOP.

5 LAPPEN Look Ahead Packet Processing

Enable. When set to a 1, the

LAPPEN bit will cause the

Am79C973/Am79C975 controller

to generate an in terrupt fol lowin g

the descriptor write operation to

the first buffer of a receive frame.

This interrupt will be generated in

addition to the interrupt that is

generated following the descrip-

tor write operation to the last buff-

er of a receive packet. The

interrupt will be signaled through

the RINT bit of CSR0.

Setting LAPPEN to a 1 also en-

ables the Am7 9C9 73/A m7 9C97 5

controller to read the STP bit of

receive descriptors. The

Am79C973/Am79C975 controller

will use the STP information to

determine where it should begin

writing a receive packet’s data.

Note that while in this mode, the

Am79C973/Am79C975 controller

can write intermediate packet

data to buffers whose descriptors

do not contain STP bits set to 1 .

Following the write to the last de-

scriptor used by a packet, the

Am79C973/Am79C975 controller

will scan through the next de-

scrip tor entries to loca te the nex t

STP bit that is set to a 1. The

Am79C973/Am79C975 controller

will begin writing the next packets

data to the buffer pointed to by

that descriptor.

Note that because several de-

scrip tors may be alloc at ed by the

128 Am79C973/Am79C975

PRELIMINARY

host for each packet, and not all

messages may need all of the de-

scriptors that are allocated be-

tween descriptors that contain

STP = 1, then some descriptors/

buffers may be skipped in the

ring. While performing the search

for the n ext STP bit that is set t o

1, the Am79C973/Am79C975

controller will advance through

the receive descriptor ring re-

gardless of the state of ownership

bits. If a ny of the en tries th at are

examined during this search indi-

cate Am79C973/Am79C975 con-

tr oller o wners hip o f the de scri ptor

but also indicate STP = 0, then

the Am79C973/Am79C975 con-

troller will res et the OWN bit to 0

in these en tries . If a sc anned en-

try indicates host ownership with

STP = 0, then the Am79C973/

Am79C975 controller will not al-

ter the entry, but will advance to

the next entry.

When the STP bit is found to be

true, but the descriptor that con-

tains this setting i s not own ed by

the Am79C973/Am79C975 con-

troller, then the Am79C973/

Am79C975 controller will stop

advancing through the ring en-

tries and begin periodic polling of

this entry. When the STP bit is

found to be true, and the descrip-

tor that contains this setting is

owned by the Am79C973/

Am79C975 controller, then the

Am79C973/Am79C975 controller

will stop advancing through the

ring entries, store the descriptor

information that it has just read,

and wait for the next receive to ar-

rive.

This behavior allows the host

software to pre-assign buffer

space in such a manner that the

header portion of a receive pac k-

et will a lways b e wri tten to a par-

ticular memory area, and the data

portion of a receive packet will al-

ways be written to a separate

memory area. The interrupt is

generated when the header bytes

have been written to the header

memory area.

Read/Write accessible always.

The LAPPEN bit will be reset to 0

by H_RESET or S_RESET and

will be unaffected by STOP.

See Appendix E for more infor-

mation on the Lo ok Ah ead P ack-

et Processing concept.

4 DXMT2PD Disable Transmit Two Part Defer-

ral (see Medium Allocation sec-

tion in the Media Access

Management section for more

details). If DXMT2PD is set,

Transmit Two Part Deferral will

be disabled.

Read/Write accessible always.

DXMT2PD is cleared by

H_RESET or S_RESET and is

not affected by STOP.

3 EMBA Enable Modified Back-off Algo-

rithm (see Contenti on Res olutio n

section in Media Access Man-

agement section for more de-

tails). If EMBA is set, a modified

back-off algorithm is implement-

ed.

Read/Write accessible always.

EMBA is cleared by H_RESET or

S_RESET a nd is not affected by

STOP.

2 BSWP Byte Swap. This bit is used to

choose between big and little En-

dian modes of operation. When

BSWP is set to a 1, big Endian

mode is sele cted. Wh en BSWP i s

set to 0, lit tle En dian m ode is se-

lected.

When big End ian mode is se lec t-

ed, the Am79C973/Am79C975

controller will swap the order of

bytes on the AD bus during a data

phase on accesses to the FIFOs

only. Specifically, AD[31:24] be-

comes Byte 0, AD[23:16] be-

comes Byte 1, AD[15:8] becomes

Byte 2, and AD[7:0] becomes

Byte 3 when big Endian mode is

selected. When little Endian

mode is selected, the order of

bytes on the AD bus during a data

phase is: AD[31:24] is Byte 3,

AD[23:16] is Byte 2, AD[15:8] is

Byte 1, and AD[7:0] is Byte 0.

Am79C973/Am79C975 129

PRELIMINARY

Byte swap only affects data

transfers that involve the FIFOs.

Initialization block transfers are

not affected by the setting of the

BSWP bit. Descriptor transfers

are not affected by th e setting of

the BSWP bit. RDP, RAP, BDP

and PCI configuration space ac-

cesses are not affected by the

setting o f the B SWP bi t. Add ress

PROM transfers are not affected

by the setting of the BSWP bit.

Expansion ROM accesses are

not affected by the setting of the

BSWP bit.

Note that the byte ordering of the

PCI bus is de fined to be little En-

dian. BSWP should not be set to

1 when the Am79C973/

Am79C975 controller is used in a

PCI bus applicati on.

Read/Write accessible always.

BSWP is cleared by H_RESET or

S_RESET a nd is not affected by

STOP.

1-0 RES Reserved location. The default

value of this b it is a 0. Writing a 1

to this bit has no eff ec t on de vic e

function. If a 1 is written to this bit,

then a 1 will be read back . Exist-

ing drivers may write a 1 to this bit

for compatibility, but new drivers

should write a 0 to this bit and

should treat the read value as un-

defined.

CSR4: Test and Features Control

Certain bits in CSR4 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR4 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 RES Reserved location. It is OK for

legacy software to write a 1 to this

location. This bit must be set

back to 0 before setting INIT or

STRT bits.

Read/Write accessible always.

This bit is cleared by H_RESET

or S_RESET and is unaffected by

the STOP bit .

14 DMAPLUS Writing and reading from this bit

has no effect. DMAPLUS is al-

ways set to 1.

13 RES Reserved Location. Written as

zero and read as undefined.

12 TXDPO LL Dis able Tra nsmit Polling. If T XD-

POLL is set, the Buffer Manage-

ment Unit will disable transmit

polling. Likewise, if TXDPOLL is

cleared, automatic transmit poll-

ing is enabled. If TXDPOLL is set,

TDMD bit in CSR0 must be set in

order to initiate a manual poll of a

transmit descriptor. Transmit de-

scriptor polling will not take place

if TXON is reset. Transmit polling

will take place following Receive

activities.

Read/Write accessible always.

TXDPOLL is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

11 APAD_XMT Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to extend

them to 64 bytes including FCS.

The FCS is calculated for the en-

tire frame, including pad, and ap-

pended after the pad field.

APAD_XMT will override the pro-

gramming of the DXMTFCS bit

(CSR15, bit 3) and of the

ADD_FCS bit (TMD1, bit 29) for

frames shorter than 64 bytes.

Read/Write accessible always.

APAD_XMT is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

10 ASTRP_RCV Auto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

Read/Write accessible always.

ASTRP_RCV is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

130 Am79C973/Am79C975

PRELIMINARY

9 MFCO M issed Frame Cou nter Overflow

is set by the Am79C973/

Am79C975 controller when the

Missed Fr ame Co unter (CS R112

and CSR113) has wrapped

around.

When MFCO is set, INTA is as-

serted i f IENA is 1 and the ma sk

bit MFCOM is 0.

Read/Write accessible always.

MFCO is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MFCO is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

8 MFCOM Missed Frame Counter Overflow

Mask. If MFCOM is set, the

MFCO bit will be masked and un-

able to set the INTR bit.

Read/Write accessible always.

MFCOM is set to 1 b y H_RE SET

or S_RESET and is not affected

by the STOP bit.

7 UINTCMD User Interrupt Command.

UINTCMD can be used by the

host to generate an interrupt un-

related to any network activity.

When UINTCMD is set, INTA is

asserted if IENA is set to 1.

UINTCMD will be cleared inter-

nally after the Am79C973/

Am79C975 controller has set

UINT to 1.

Read/Write accessible always.

UINTCMD is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

6 UINT User Interrupt. UINT is set by the

Am79C973/Am79C975 controller

after the host has issued a user

interrupt command by setting

UINTCMD (CSR4, bit 7) to 1.

Read/Write accessible always.

UINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. UINT is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

5 RCVCCO Receive Collision Counter Over-

flow is set by the Am79C973/

Am79C975 controller when the

Receive Collision Counter

(CSR114 and CSR115) has

wrapped around.

When RCVCCO is set, INTA is

asserted if IENA is 1 and the

mask bit RCVCCOM is 0.

Read/Write accessible always.

RCVCCO is cleared by the host

by writing a 1. W r iting a 0 has n o

effect. RCVCCO is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

4 RCVCCOM Receive Collision Counter Over-

flow Mask. If RCVCCOM is set,

the RCVCCO bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

RCVCCOM is set to 1 by

H_RESET or S_RESET and is

not affected by the STOP bit.

3 TXST RT Trans mit S tart stat us is set b y the

Am79C973/Am79C975 controller

whenever it begins transmission

of a frame.

When TXSTRT is set, INTA is as-

serted if IENA is 1 and the mask

bit TXSTRTM is 0.

Read/Write accessible always.

TXSTRT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. TXSTRT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

2 TXSTRTM Transmit Start Mask. If TX-

STRTM is set, the TXSTRT bit

will be mas ked and una ble to set

the INTR bit.

Read/Write accessible always.

TXSTRTM is set to 1 by

H_RESET or S_RESET and is

not affected by the STOP bit.

1-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR5: Extended Control and Interrupt 1

Certain bits in CSR5 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

Am79C973/Am79C975 131

PRELIMINARY

means that the software can read CSR5 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 TOKINTD Transmit OK Interrupt Disable. If

TOKINTD is set to 1, the TINT bit

in CSR0 will not be set when a

transmission was successful.

Only a transmit error will set the

TINT bit.

TOKINTD has no effect when

LTINTEN (CSR5 , bit 14) is set to

1. A transmit descriptor with

LTINT set to 1 will always cause

TINT to be set to 1, independent

of the success of the transmis-

sion.

Read/Write accessible always.

TOKINTD is cleared by

H_RESET or S_RESET and is

unaffected by STOP.

14 LTINTEN Last Transmit Interrupt Enable.

When set to 1, the LTINTEN bit

will cause the Am79C973/

Am79C975 controller to read bit

28 of TMD1 as LTINT. The set-

ting LTINT will determine if TINT

will be set at the end of the trans-

mission.

Read/Write accessible always.

LTINTEN is cleared by

H_RESET or S_RESET and is

unaffected by STOP.

13-12 RES Reserved locations. Written as

zeros and read as undefined.

11 SINT System Interrupt is set by the

Am79C973/Am79C975 controller

when it detects a system error

during a bus master transfer on

the PCI bus. System errors are

data parity error, master abort, or

a target abort. The setting of

SINT due to data parity error is

not dependent on the setting of

PERREN (PCI Command regis-

ter, bit 6).

When SINT is set, INTA is assert-

ed if the enable bit SINTE is 1.

Note that the assertion of an in-

terrupt due to S INT is not dep en-

dent on th e state of the INEA bit,

since INEA is cleared by the

STOP reset generated by the

system er ro r.

Read/Write accessible always.

SINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. The state of SINT is not af-

fected b y clea ring a ny o f the PCI

Status register bits that get set

when a data parity error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13), or target

abort (RTABORT, bit 12) occurs.

SINT is cleared by H_RESET or

S_RESET a nd is not affected by

setting the STOP bit.

10 SINTE System Interrupt Enable. If SIN-

TE is set, the SINT bit will be able

to set the INTR bit.

Read/Write accessible always.

SINTE is set to 0 by H_RESET or

S_RESET a nd is not affected by

setting the STOP bit.

9-8 RES Reserved locations. Written as

zeros and read as undefined.

7 EXDINT Excessive Deferral Interrupt is

set by the Am79C973/

Am79C975 controller when the

transmitter has experienced Ex-

cessive Deferral on a transmit

frame, where Excessive Deferral

is defined in the ISO 8802-3

(IEEE/ANSI 802.3) standard.

When EXDINT is set, INTA is as-

serted i f the enab le bit E XDINTE

is 1.

Read/Write accessible always.

EXDINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. EXDINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 EXDINTE Excessive Deferral Interrupt En-

able. If EXDINTE is set, the

EXDINT bit will be able to set the

INTR bit.

132 Am79C973/Am79C975

PRELIMINARY

Read/Write accessible always.

EXDINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

5 MPPLBA Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

at its default value of 0, the

Am79C973/Am79C975 controller

will only detect a Magic Packet

frame if the destination address

of the packet matches the con-

tent of the physical address regis-

ter (PADR). If MPPLBA is set to

1, the destination address of the

Magic Packet frame can be uni-

cast, multicast, or broadcast.

Note that t he setting of MPPL BA

only affects the address detection

of the Magic Packet frame. The

Magic Packet frame’s data se-

quence must be made up of 16

consecutive physical addresses

(PADR[47:0]) regardless of what

kind of destination address it has.

This bi t is OR’ed with EMPPLBA

bit (CSR116, bit 6) .

Read/Write accessible always.

MPPLBA is set to 0 by H_RESET

or S_RESET and is not affected

by setting the STOP bit.

4 MPINT Magic Packet Interrupt. Magic

Packet Interrupt is set by the

Am79C973/Am79C975 controller

when the device is in the Magic

Packet mode and the

Am79C973/Am79C975 controller

receives a Magic Packet frame.

When MPINT i s set to 1, INTA is

asserted if IENA (CSR0, bit 6)

and the enable bit MPINTE are

set to 1.

Read/Write accessible always.

MPINT is cleared by the host by

writing a 1. Writing a 0 has no af-

fect. MPINT is cleared by

H_RESET, S_RESE T, or by set-

ting the STOP bit.

3 MPINTE M agic Pa cket Interru pt Enabl e. If

MPINTE is set to 1, the MPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

MPINT is cleared to 0 by

H_RESET or S_RESET and is

not affecte d by set ting the S TOP

bit.

2 MPEN Magic Packet Enable. MPEN al-

lows activation of the Magic

Packet mode by the host. The

Am79C973/Am79C975 controller

will enter the Magic Packet mode

when both MPE N and MPMODE

are set to 1.

Read/Write accessible always.

MPEN is cleared to 0 by

H_RESET or S_RESET and is

not affecte d by set ting the S TOP

bit.

1 MPMO DE The Am 79C973/Am7 9C975 con-

trol le r w il l en t er the Ma gi c Pa ck et

mode when MP MODE is set to 1

and either PG is asserted or

MPEN is set to 1.

Read/Write accessible always.

MPMODE is cleared to 0 by

H_RESET or S_RESET and is

not affecte d by set ting the S TOP

bit

0 SPND Suspend. Setting SPND to 1 will

cause the Am79C973/

Am79C975 controller to start re-

questing entrance into suspend

mode. The host must poll SPND

until it reads back 1 to determ ine

that the Am79C973/Am79C975

controller has entered the sus-

pend mode. Setting SPND to 0

will get the Am79C973/

Am79C975 controller out of sus-

pend mode. SPND can only be

set to 1 if STOP (CSR0, bit 2) is

set to 0. H_RESET, S_RESET or

setting the STOP bit will get the

Am79C973/Am79C975 controller

out of suspend mode.

Requesting entrance into the

suspend mode by the host de-

pends on the setting of the

FASTSPNDE bit (CSR7, bit 15).

Refer to the bit des cription of the

FASTSPNDE bit and the Sus-

pend section in Detailed Func-

tions, Buffer Management Unit

for details.

Am79C973/Am79C975 133

PRELIMINARY

In suspend mo de, all of the CSR

and BCR registers are accessi-

ble. As long as the Am79C973/

Am79C9 75 control ler is no t reset

while in suspend mode (by

H_RESET, S_RESET or by set-

ting the STOP bit), no re-initial-

ization of the device is required

after the device comes out of sus-

pend mode. The Am79C973/

Am79C975 controller will contin-

ue at the transmit and receive de-

scriptor ring locations, from

where it had left, wh en it entered

the suspend mod e.

Read/Write accessible always.

SPND is cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 TLEN Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during the Am79C973/

Am79C975 controller initializa-

tion. This field is written during

the Am79C973/Am79C975 con-

troller initialization routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

TLEN is only de fined after i nitial-

ization. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

11-8 RLEN Contains a copy of the receive

encoded ring length (RLEN) read

from the initialization block during

Am79C973/Am79C975 controller

initialization. This field is written

during the Am79C973/

Am79C975 controller initializa-

tion routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

RLEN is only define d a fter ini tial-

ization. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

7-0 RES R eserved loc ations. Read as 0s .

Write operations are ignored.

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 FASTSPNDE Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C973/Am79C975 controller

performs a fast suspend whenev-

er the SPND bit is set.

When a fa st suspend is r equest-

ed, the Am79C973/Am79C975

controller performs a quick entry

into the suspend mode. At the

time the SPND bit is set, the

Am79C973/Am79C975 controller

will comple te the DMA pr oces s of

any transmit and/or receive pack-

et that had already begun DMA

activity. In addition, any transmit

packet that ha d started trans mis-

sion will be fully transmitted and

any receive packet that had be-

gun reception will be fully re-

ceived. However, no additional

packets wil l be transm itted or re-

ceived and no additional transmit

or receive DMA activity will begin.

Hence, the Am79C973/

Am79C975 controller may enter

the suspend mode with transmit

and/or r eceiv e packe ts st ill i n th e

FIFOs or the SRAM.

When FASTSPNDE is 0 an d the

SPND bit is set, the Am79C973/

Am79C975 controller may take

longer before entering the sus-

pend mode. At the time the

SPND bit is set, the Am79C973/

Am79C975 controller will com-

plete the DMA process of a trans-

mit packet if it had already begun

134 Am79C973/Am79C975

PRELIMINARY

and the Am79C973/Am79C975

controller will completely receive

a receive packet if it had already

begun. Additionally, all transmit

packets stored in the transmit

FIFOs and the transmit buffer

area in the SRAM (if one is en-

abled) will be transmitted and all

receive packets stored in the re-

ceive FIFOs, and the receive

buffer area in the SRAM (if one is

enabled) will be transferred into

system memory. Since the FIFO

and SRAM contents are flushed,

it may take much longer before

the Am79C973/Am79C975 con-

troller enters the suspend mode.

The amount of time that it takes

depends on many factor s includ-

ing the si ze of th e S RAM , bu s la -

tency, and network traffic level.

When a write to CSR5 is per-

formed with bit 0 (SPND) set to 1,

the value that is simultaneously

written to FASTSPNDE is used to

determine which approach is

used to enter suspend mode.

Read/Write accessible always.

FASTSPNDE is cleared by

H_RESET, S_RESET or by set-

ting the STOP bit.

14 RXFRTG Receive Frame Tag. When Re-

ceive Frame Tag is set to 1, a tag

word is put into the receive de-

scriptor supplied by the EADI.

See the section Receive Frame

Tagging for details. This bit is

valid only when the EADISEL

(BCR2, bit 3) is set to 1.

Read/Write accessible always.

RXFRTG is cleared by

H_RESET. RXFRTG is unaffect-

ed by S_RESET or by setting the

STOP bit.

13 RDMD Receive Demand, when set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the receive poll-time counter to

elapse. If RXON is not enabled,

RDMD has no meaning and no

receive Descriptor Ring access

will occur.

RDMD is requir ed to be set if th e

RXDPOLL bit in CSR7 is set. Set-

ting RDMD while RXDPOLL = 0

merely hastens the Am79C973/

Am79C975 controller’s response

to a receive Descriptor Ring En-

try.

Read/Write accessible always.

RDMD is s et by writin g a 1 . Wr it-

ing a 0 has no effect. R DMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a re-

ceive Descriptor. RDMD is

cleared by H_RESET. RDMD is

unaffected by S_RESET or by

setting the STOP bit.

12 RXDPOLL Rece ive Disable Polling. If RXD-

POLL is set, the Buffer Manage-

ment Unit will disable receive

polling. Likewise, if RXDPOLL is

cleared, automatic receive poll-

ing is enabled. If RXDPOLL is

set, RDMD bit in CSR7 must be

set in order to initiate a manual

poll of a receive descriptor. Re-

ceive Descriptor Polling will not

take place if RXON is reset.

Read/Write accessible always.

RXDPOLL is cleared by

H_RESET. RXDPOLL is unaf-

fected by S_R ES ET or by se ttin g

the STOP bit .

11 STINT Software Timer Interrupt. The

Software Timer interrupt is set by

the Am79C973/Am79C975 con-

troller when the Software Timer

counts down to 0. The Software

Timer will immediately load the

STVAL (BCR 31, bits 5-0) into the

Software Tim er and begin cou nt-

ing down.

When STINT is set to 1, INTA is

asserted if the enable bit STINTE

is set to 1.

Read/Write accessible always.

STINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. STINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

Am79C973/Am79C975 135

PRELIMINARY

10 STINTE S oftware Time r Interrupt E nable.

If STINTE is set, the STINT bit

will be able to set the INTR bit.

Read/Write accessible always.

STINTE is se t to 0 by H_RESE T

and is not affected by S_RESET

or setting the STOP bit

9 MREINT PHY Management Read Error In-

terrupt. The PHY Read Error in-

terrupt is set by the Am79C973/

Am79C975 controller to indicate

that the currently read register

fr om the PHY is i nvalid. The con-

tents o f BCR34 are inc or rec t an d

that the o peration sh ould be per -

formed again. The indication of

an inco rre ct re ad come s f rom t he

internal PHY.

When MREINT is set to 1, INTA is

asserted if the enable bit MREIN-

TE is set to 1.

Read/Write accessible always.

MREINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MREINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

8 MREINTE PHY Management Read Error In-

terrupt Enable. If MREINTE is

set, the MREINT bit will be able to

set the INTR bit.

Read/Write accessible always.

MREINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP bit

7 MAPINT PHY Management Auto-Poll In-

terrupt. The PHY Auto-Poll inter-

rupt is set by the Am79C973/

Am79C975 controller to indicate

that the currently read status

does not match the stored previ-

ous statu s indic ating a chang e in

state for the internal PHY. A

change in the Auto-Poll Access

Method (BCR32, Bit 11) will reset

the shadow register and will not

cause an inter rupt on the fir s t ac-

cess from the Auto-Poll section.

Subsequent accesses will gener-

ate an interrupt if the shadow reg-

ister and the read register

produce differences.

When MAPINT is set to 1, INTA is

asserted if the enable bit MAP-

INTE is set to 1.

Read/Write accessible always.

MAPINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MAPINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

6 MAPINTE PHY Auto-Poll Interrupt Enable.

If MAPINTE is set, the MAPINT

bit will be able to set the INTR bit.

Read/Write accessible always.

MAPINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP bit

5 MCCINT PHY Management Command

Complete Interrupt. The PHY

Management Command Com-

plete Interrupt is set by the

Am79C973/Am79C975 controller

when a read or write operation to

the internal PHY Data Port

(BCR34) is complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MCCINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

4 MCCINTE PHY Management Command

Complete Interrupt Enable. If

MCCINTE is set to 1, the MC-

CINT bit will be able to set the

INTR bit when the host reads or

writes to the internal PHY Data

Port (BCR34) only. Internal PHY

Managemen t Com mands wil l not

generate an interrupt. For in-

stance Auto-Poll state machine

generated management frames

will not generate an interrupt

upon completion unless there is a

compare error which get reported

136 Am79C973/Am79C975

PRELIMINARY

through the MAPINT (CSR7, bit

6) interrupt or the MCCIINTE is

set to 1.

Read/Write accessible always.

MCCINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

3 MCCIINT PHY Management Command

Complete Internal Interrupt. The

PHY Management Command

Complete Interrupt is set by the

Am79C973/Am79C975 controller

when a read or write operation on

the internal PHY management

port is complete from an internal

operation. Examples of internal

operations are Auto-Poll or PHY

Management Port generated

management frames. These are

normally hidden to the host.

When MCCIINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCIINT is cleared by the host

by writ ing a 1. W riti ng a 0 has n o

effect. MCCIINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

2 MCCIINTE PHY Management Command

Complete Internal Interrupt En-

able. If MCCIINTE is set to 1, the

MCCIINT bit will be able to set

the INTR bit when the internal

state machines generate man-

agement frames. For instance,

when MCCIINTE is set to 1 and

the Auto-P oll state machi ne gen-

erates a man agement frame, th e

MCCIINT will set the INTR bit

upon completion of the manage-

ment frame regardless of the

comparison outcome.

Read/Write accessible always.

MCCIINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

1 MIIPDTINT PHY Detect Transition Interrupt.

The PHY Dete ct Transit ion Inter-

rupt is set by the Am79C973/

Am79C975 controller whenever

the MIIPD bit (BCR32, bit 14)

transitions from 0 to 1 or vice ver-

sa.

Read/Write accessible always.

MIIPDTINT is cleared by the host

by writing a 1. W r iting a 0 has n o

effect. MIIPDTINT is cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

0 MIIPDTINTE PHY Detect Transition Interrupt

Enable. If MIIPDTINTE is set to 1,

the MIIPDTINT b it will be able t o

set the INTR bit.

Read/Write accessible always.

MIIPDTINTE is set to 0 by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

CSR8: Logical Address Filter 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[15:0] Logical Address Filter, LADRF-

[15:0]. The content of this register

is undefined until loaded from the

initialization block after the INIT

bit in C SR0 has bee n set or a d i-

rect register write has been per-

formed on this register.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR9: Logical Address Filter 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[31:16] Logical Address Filter, LADRF-

[31:16]. The content of this regis-

ter is unde fin ed until l oaded f rom

the initialization block after the

INIT bit in CSR0 has been s et or

a direct register write has been

performed on this register.

Am79C973/Am79C975 137

PRELIMINARY

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR10: Logical Address Filter 2

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[47:32]Logical Address Filter,

LADRF[47:32]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has be en per for m ed o n th is

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR11: Logical Address Filter 3

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[63:48] Logical Address Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has be en per for m ed o n th is

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR12: Physical Address Register 0

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[15:0] Physical Address Register,

PADR[15:0]. T he c ont ents of this

PROM after H_RESET or by an

EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR13: Physical Address Register 1

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[31:16]Physical Address Register,

PADR[31:16]. The contents of

this regis ter are loaded f rom EE-

PROM after H_RESET or by an

EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR14: Physical Address Register 2

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

138 Am79C973/Am79C975

PRELIMINARY

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[47:32]Physical Address Register,

PADR[47:32].The contents of

this regis ter are loaded f rom EE-

PROM after H_RESET or by an

EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR15: Mode

This register’s fields are loaded during the Am79C973/

Am79C9 75 control ler initi aliz ation routi ne with the cor -

responding Initialization Block values, or when a direct

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PROM Promiscuous Mode. When

PROM = 1, all incoming receive

frames are accepted.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

14 DRCVBC Disable Receive Broadcast.

When set, disables the

Am79C973/Am79C975 controller

from receiving broadcast mes-

sages. Used for protocols that do

not support broadcast address-

ing, except as a function of multi-

cast. DRCVBC is cleared by

activation of H_RESET or

S_RESET (broadcast messages

will be received) and is unaffect-

ed by STOP.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

13 DRCVPA Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) o f t h e A m 79 C 973 / Am 79 C 975

controller will be disabled.

Frames addressed to the nodes

individual physical address will

not be recognized .

Read/Write accessible only when

either the STO P or the SPND bit

is set.

12-9 RES Reserved locations. Written as

zeros and read as undefined.

8-7 PORTSEL[1:0] Port Select bits allow for software

controlled selection of the net-

work medium. The only legal val-

ues for this field is 11.

Read/Write accessible only when

either t he STOP or the SPND bit

is set. Cleared by H_RESET or

S_RESET and is unaffected by

STOP.

6 INTL Internal Loopback. See the de-

scr ipti on of LO OP (CSR1 5, bit 2).

Read/Write accessible only when

either the STO P or the SPND bit

is set.

5 DRTY Disable Retry. When DRTY is set

to 1, the Am79C973/Am79C975

controller will attempt only one

transmission. In this mode, the

device will not pro tect the fir st 64

bytes of fra me data in the Tran s-

mit FIFO from being overwritten,

because automatic retransmis-

sion will not be nec essary. Whe n

DRTY is set to 0, the Am79C973/

Am79C975 controller will attempt

16 transmissions before signal-

ing a retry error.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

4 FCOLL Force Collision. This bit allows

the collision logic to be tested.

The Am79C973/Am79C975 con-

Am79C973/Am79C975 139

PRELIMINARY

troller must be in internal loop-

back for FCOLL to be valid. If

FCOLL = 1, a collision will be

forced dur ing loopback trans mis-

sion attem pts, whic h wil l result i n

a Retry Error. If FCOLL = 0, the

Force Collision logic will be dis-

abled. FCOLL is defined after the

initialization block is read.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

3 DXMTFCS Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. W hen DXM T FC S is s et t o

1, no FCS is generated or sent

with the transmitted frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in TMD1 .

When APAD_XMT bit (CSR4,

bit11) is set to 1, the setting of

DXMTFCS has no effect on

frames shorter than 64 bytes.

If DXMTFCS is set and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

If ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in TMD1.

This bit was called DTCR in the

LANCE (Am7990) device.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

2 LOOP Loopback Enable allows the

Am79C973/Am79C975 controller

to operate in full-duplex mode for

test purposes. The setting of the

full- duplex control bits in BCR9

have no effect when the device

operates in loopback mode.

When LOOP = 1, loopback is en-

abled. In combination with INTL

and MIIILP, various loopback

modes are defined as follows in

Table 24.

Refer to Loop Back Operation

section for more details.

Read/Write accessible only

when either the STOP or the

SPND bit is set. LOOP is cleared

by H_RESET or S_RESET and

is unaffected by STOP.

1 DTX Disable Transmit results in

Am79C973/Am79C975 controller

not accessing the Transmit De-

scriptor Ring and, therefore, no

transmissions are attempted.

DTX = 0, will set TXON bit (CSR0

bit 4) i f STRT (CS R0 bit 1) is as-

serted.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

0 DRX Disable Receiver results in the

Am79C973/Am79C975 controller

not accessing the Receive De-

scriptor Ring and, therefore, all

receive frame data are ignored.

DRX = 0, will set RXON bit

(CSR0 bit 5) if STRT (CSR0 bit 1)

is asserted.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

CSR16: Initialization Block Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADRL This register is an alias of CSR1.

Read/Write accessible only when

either the STO P or the SPND bit

is set.

Table 24. Loopback Configuration

LOOP INTL MIIILP Function

0 0 0 Normal Operation

0 0 1 Internal Loop

1 0 0 External Lo op

140 Am79C973/Am79C975

PRELIMINARY

CSR17: Initialization Block Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADRH This register is an alias of CSR2.

Read/Write accessible only when

either the ST OP or the SPND bit

is set.

CSR18: Current Receive Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRBAL Contains the lower 16 bi ts of the

current receive buffer address at

which the Am79C973/

Am79C975 controller will store

incoming frame data.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR19: Current Receive Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRBAU Co ntains the upper 16 bits of the

current receive buffer address at

which the Am79C973/

Am79C975 controller will store

incoming frame data.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR20: Current Transmit Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXBAL Co ntains the lo wer 16 bits of th e

current transmit buffer address

from which the Am79C973/

Am79C9 75 con troller is tran sm it-

ting.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR21: Current Transmit Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXBAU C onta ins the uppe r 16 bits of th e

current transmit buffer address

from which the Am79C973/

Am79C9 75 con troller is tran sm it-

ting.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR22: Next Receive Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRBAL Contains the lower 16 bits of the

next receive buffer address to

which the Am79C973/

Am79C975 controller will store

incoming frame data.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR23: Next Receive Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRBAU Conta ins the uppe r 16 bits of th e

next receive buffer address to

which the Am79C973/

Am79C975 controller will store

incoming frame data.

Am79C973/Am79C975 141

PRELIMINARY

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR24: Base Address of Receive Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADRL Contains th e lower 16 bits o f the

base address of the Receive

Ring.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR25: Base Address of Receive Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADRU Co ntains the upper 16 bits of th e

base address of the Receive

Ring.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR26: Next Receive Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRDAL Co ntains the lower 16 bits o f the

next receive descriptor address

pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR27: Next Receive Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NRDAU Conta ins the uppe r 16 bits of the

next receive descriptor address

pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR28: Current Receive Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRDAL Contains the l ower 16 bits of the

current receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR29: Current Receive Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRDAU Conta ins the uppe r 16 bits of the

current receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR30: Base Address of Transmit Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADXL Conta ins the lower 16 bi ts of the

base address of the Transmit

Ring.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

142 Am79C973/Am79C975

PRELIMINARY

by H_RESET, S_RESET, or

STOP.

CSR31: Base Address of Transmit Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADXU Conta ins the uppe r 16 bits of th e

base address of the Transmit

Ring.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR32: Next Transmit Descriptor Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXDAL Conta ins the lower 16 bits of the

next transmit descriptor address

pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR33: Next Transmit Descriptor Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXDAU Contains the uppe r 16 bits of th e

next transmit descriptor address

pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR34: Current Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXDAL C ontains the lower 16 bits of th e

current transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR35: Current Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXDAU Conta ins the upper 16 bits of the

current transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR36: Next Next Receive Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNRDAL Contains th e lower 16 bits of th e

next next receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR37: Next Next Receive Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNRDAU Contains the upper 16 bits of the

next next receive descriptor ad-

dress pointer.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

Am79C973/Am79C975 143

PRELIMINARY

by H_RESET, S_RESET, or

STOP.

CSR38: Next Next Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNXDAL Co ntains the lower 16 bits of th e

next next transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR39: Next Next Transmit Descriptor Address

Uper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NNXDAU Co ntains the uppe r 16 bits of th e

next next transmit descriptor ad-

dress pointer.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR40: Current Receive Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 CRBC Current Receive Byte Count.

This field is a copy of the BCNT

field of RMD1 of the current re-

ceive descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR41: Current Receive Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CRST Current Receive Status. This

field is a copy of bits 31-16 of

RMD1 of the current receive de-

scriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR42: Current Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 CXBC Current Transmit Byte Count.

This field is a copy of the BCNT

field of TMD1 of the current trans-

mit descriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR43: Current Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CXST Current Transmit Status. This

field is a copy of bits 31-16 of

TMD1 of th e current transm it de-

scriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR44: Next Receive Byte Count

Bit Name Description

144 Am79C973/Am79C975

PRELIMINARY

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 NRBC Next Receive Byte Count. This

field is a copy of the BCNT field of

RMD1 of the next receive de-

scriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR45: Next Receive Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 NRST Nex t Re ce iv e S tat us . Thi s fie ld is

a copy of bits 31-16 of RMD1 of

the next receive descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR46: Transmit Poll Time Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 TXPOLL Transmi t P ol l T im e C oun ter . Th is

counter is incremented by the

Am79C9 73/ Am 79C9 75 c on tr oll er

microcode and is used to trigger

the transmit descriptor ring poll-

ing operation of the Am79C973/

Am79C9 75 co ntrol ler .

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR47: Transmit Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 TXPOLLINT Transmit Polling Interval. This

Am79C 973 /Am 79C9 75 c on tr oll er

will wait between successive poll-

ing operations. The TXPOLLINT

value is expressed as the two’s

complement of the desired inter-

val, where each bit of TXPOL-

LINT represents 1 clock period of

time. TXPOLLINT[3:0] are ig-

nored. (TXPOLLINT[16] is im-

plied to be a one, so

TXPOLLINT[15] is significant and

does not represent the sign of the

two’s complement TXPOLLINT

value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when

CLK = 33 MHz). The TXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR47 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for POLLINT other than the

default, then the correct proce-

dure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR47 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the st an-

dard initialization procedure

(standard implies use of an initial-

ization block in memory and set-

ting the INIT bit of CSR0), but

instead, chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is im perativ e that the user

also writes all zeros to CSR47 as

part of the alternative initialization

sequence.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

Am79C973/Am79C975 145

PRELIMINARY

by H_RESET, S_RESET, or

STOP.

CSR48: Receive Poll Time Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 RXPOLL Receive Poll Time Counter. This

counter is incremented by the

Am79C9 73/ Am 79C9 75 c on tr oll er

microcode and is used to trigger

the receiv e desc ri pto r ring poll in g

operation of the Am79C973/

Am79C9 75 co ntrol ler .

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR49: Receive Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 RXPOLLINT Receive Polling Interval. This reg-

ister contains the time that the

Am79C9 73/ Am 79C9 75 c on tr oll er

will wait between successive poll-

ing operations. The RXPOLLINT

value is expressed as the two’s

complement of the desired inter-

val, where each bit of RXPOL-

LINT approximately represents

one clock time period. RXPOL-

LINT[3:0] are ignored. (RXPOL-

LINT[16] is implied to be a 1, so

RXPOLLINT[15] is significant

and does not represent the sign

of the two’s compl ement RXPOL -

LINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when

CLK = 33 MHz). The RXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR49 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for RX POLLINT other tha n

the default, then the correct pro-

cedure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR49 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the st an-

dard initialization procedure

(standard implies use of an initial-

ization block in memory and set-

ting the INIT bit of CSR0), but

instead, chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is im perativ e that the user

also writes all zeros to CSR49 as

part of the alternative initialization

sequence.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR58: Software Style

This register is an alias of the location BCR20. Accesses

to and from th is register are equivalent to ac cesses to

BCR20.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-11 RES Reserved locations. Written as

zeros and read as undefined.

10 APERREN Advanced Parity Error Handling

Enable. When APERREN is set

to 1, the BPE bits (RMD1 and

TMD1, bit 23) start having a

meaning. BPE will be set in the

descriptor associated with the

buffer th at was a ccess ed when a

data parity error occurred. Note

that since the advanced parity er-

ror handling uses an additional bit

in the descriptor, SWSTYLE (bits

7-0 of this register) must be set to

2 or 3 to program the Am79C973/

146 Am79C973/Am79C975

PRELIMINARY

Am79C975 controller to use 32-

bit software structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur when

the Am79C973/Am79C975 con-

tr ol le r i s t he ta r g e t of t h e t ran s fe r.

Read anytime, write accessible

only when either the STOP or the

SPND bit is set. APERREN is

cleared by H_RESET and is not

affected by S_RESET or STOP.

9 RES Reserved locations. Written as

zeros and read as und efi ned.

8 SS IZE32 So ftware Size 32 b its. When se t,

this bit indicates that the

Am79C9 73/ Am 79C9 75 c on tr oll er

utilizes 32 -bit software str uctures

for the in itializati on block an d the

transmit and receive descriptor

entries. W hen c leared, t his bi t in-

dicates that the Am79C973/

Am79C975 controller utilizes 16-

bit software structures for the ini-

tialization block and the transmit

and rece ive descr iptor entrie s. In

this mode, the Am79C973/

Am79C975 controller is back-

wards compatible with the

Am799 0 LANCE and Am79C96 0

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined by the Am79C973/

Am79C975 controller according

to the setting of the Software

Style (SW STYLE, bits 7- 0 of this

Read accessible always.

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-b it add re ss

bus durin g maste r acc esses i niti-

ated by the Am79C973/

Am79C975 controller. This action

is required, since the 16-bit soft-

ware structures specified by the

SSIZE32 = 0 setting will yield

only 24 bits of address for the

Am79C973/Am79C975 controller

bus master accesses.

If SSIZE32 is set, then the soft-

ware stru ctu re s that ar e co mmo n

to the Am79C973/Am79C975

controller and the host system

will supply a full 32 bits for each

address pointer that is needed by

the Am79C973/Am79C975 con-

troller for performing master ac-

cesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are alway s driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE3 2 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0 SWSTYLE Software Style register. The val-

ue in thi s register de termines th e

style of register and memory re-

sources that sha ll be used by the

Am79C973/Am79C975 control-

ler. The Software Style selection

will affect the interpretation of a

few bits within the CSR space,

the order of the descriptor entries

and the width of the descriptors

and initialization block entries.

All Am79C973/Am79C975 con-

troller CSR bits and BCR bits and

all descriptor, buffer, and initial-

ization block entries not cited in

Table 25 are unaffected by the

Software St yl e se lec ti on an d are ,

therefore, always fully functional

as specified in the CSR and BCR

sections.

Read/Write accessible only when

either the STO P or the SPND bit

is set. The SWSTYLE register will

contain the value 00h following

H_RESET and wi ll be un affecte d

by S_RESET or STOP.

Am79C973/Am79C975 147

PRELIMINARY

CSR60: Previous Transmit Descriptor Address

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 PXDAL Contains the lower 16 bits of the

previous transmit descriptor ad-

dress pointer. The Am79C973/

Am79C 975 c ontroller ha s the c a-

pability to stack multiple transmit

frames.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

Table 25. Software Styles

SWSTYLE

[7:0] Style

Name SSIZE32 Initialization Block

Entries Descriptor Ring Entries

00h LANCE/

PCnet-ISA

controller 016-bit software structures,

non-burst or burst access 16-bit softw are structures ,

non-burst access only

01h RES 1RES RES

02h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access 32-bit softw are structures ,

non-burst access only

03h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access 32-bit softw are structures ,

non-b urst o r b urst ac cess

All Other Reserved Undefined Undefined Undefined

148 Am79C973/Am79C975

PRELIMINARY

CSR61: Previous Transmit Descriptor Address

Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 PXDAU Con tains the upper 16 b its of th e

previous transmit descriptor ad-

dress pointer. The Am79C973/

Am79C9 75 control ler has the ca-

pability to stack multiple transmit

frames.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR62: Previous Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-12 RES Reserved locations.

11-0 PXBC Previous Transmit Byte Count.

This field is a copy of the BCNT

field of TMD1 of the previous

transmit descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR63: Previous Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 PXST Previous Transmit Status. This

field is a copy of bits 31-16 of

TMD1 of the previous transmit

descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR64: Next Transmit Buffer Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXBAL Contains the lower 16 bits of the

next trans mit buffer address fro m

whic h the Am 79C973/ Am79C9 75

controller will transmit an outgo-

ing frame.

Read/Write accessible only when

either t he STOP or the SP ND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR65: Next Transmit Buffer Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 NXBAU Con tains the upper 16 b its of th e

next trans mit buffer address fro m

whic h the Am 79C973/ Am79C9 75

controller will transmit an outgo-

ing frame.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR66: Next Transmit Byte Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved locations. Read and

written as zeros.

11-0 NXBC Next Transmit Byte Count. This

field is a copy of the BCNT field of

TMD1 of the next transmit de-

scriptor.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

Am79C973/Am79C975 149

PRELIMINARY

CSR67: Next Transmit Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 NXST Next Transmit Status. This field is

a copy of bits 31-16 of TMD1 of

the next transmit descriptor.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

7-0 RES Reserved locations. Read and

written as zeros. Accessible only

when either the STOP or the

SPND bit is set.

CSR72: Receive Ring Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 RCVRC Receive Ring Counter location.

Contains a two’s complement bi-

nary nu mber used to number the

current receive descriptor. This

counter interprets the value in

CSR76 as pointing to the first de-

scriptor. A counter value of zero

corresponds to the last descriptor

in the ring.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR74: Transmit Ring Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 XMTRC Transmit Ring Counter location.

Contains a two’s complement bi-

nary nu mber used to number the

current transmit descriptor. This

counter interprets the value in

CSR78 as pointing to the first de-

scriptor. A counter value of zero

corresponds to the last descriptor

in the ring.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR76: Receive Ring Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RCVRL Receive Ring Length. Contains

the two’s complement of the re-

ceive descriptor ring length. This

Am79C 973 /Am 79C9 75 c on tr oll er

initial ization rout ine based on th e

value in the RLEN fiel d of the ini-

tialization block. However, this

regist er can be manua lly altered.

The actual receive ring length is

defined by the current value in

this register. The ring length can

be defined as any value from 1 to

65535.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR78: Transmit Ring Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 XMTRL Transmit Ring Length. Contains

the two’s complement of the

transmit descriptor ring length.

This register is initialized during

the Am79C973/

Am79C975Am79C973/

Am79C975 controller initializa-

tion routine based on the value in

the TLE N field of the i nitia liza tio n

block. H owever, this regi ster can

be manually altered. The actual

transmit ring length is defined by

the current value in this register.

The ring length can be defined as

any value from 1 to 65535.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

150 Am79C973/Am79C975

PRELIMINARY

by H_RESET, S_RESET, or

STOP.

CSR80: DMA T ransfer Counter and FIFO Threshold

Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-14 RES Reserved locations. Written as

zeros and read as und efi ned.

13-12 RCVFW[1:0] Receive FIFO Watermark.

RCVFW controls the point at

which receive DMA is requested

in relation to the number of re-

ceived bytes in the Receive FIFO.

RCVFW specifies the number of

bytes which must be present

(once the frame has been verified

as a non-runt) before receive

DMA is request ed. Note howev er

that, if the network interface is op-

erating in half-duplex mode, in or-

der for receive DMA to be

performed for a new frame, at

least 64 bytes must have been re-

ceived. This effectively avoids

having to react to re ceive fra mes

which are runts or suffer a colli-

sion during the slot time (512 bit

times). If t he Runt P acket A ccept

feature is enabled or if the net-

work interfac e is operati ng in full-

duplex mode, receive DMA will

be requested as soon as either

the RCVFW threshold is reached,

or a com pl e te vali d r ece iv e f ra me

is detected (regardless of length).

When the FDRPAD (BCR9, bit 2)

is set and the Am79C973/

Am79C975 controller is in full-du-

plex mode, in order for receive

DMA to be performed for a new

frame, at least 64 bytes must

have been received. This effec-

tive ly dis able s th e runt pack et ac-

cept feature in full duplex.

When operating in the NO-SRAM

mode (no SRAM enabled), the

Bus Receive FIFO and the MAC

Receive operate like a single

FIFO and the watermark value

selected by RCVFW[1:0] sets the

number of bytes that must be

present in the FIFO before re-

ceive DMA is requested.

When operating with the SRAM,

the Bus Receive FIFO, and the

MAC Receive FIFO operate inde-

pendently on the bus side and

MAC side of the SRAM, respec-

tively. In this case, the watermark

value set by RCVFW[1:0] sets the

number of bytes that must be

presen t in the Bus Receiv e FIFO

only. See Table 26.

Table 26. Receive Watermark Programming

Read/Write accessible only when

either the STO P or the SPND bit

is set. RCVFW[1:0] is set to a val-

ue of 01b (64 bytes) after

H_RESET or S_RESET and is

unaffected by STOP.

11-10 XMTSP[1:0] Transmit Start Point. XMTSP

controls the point at which pream-

ble transmission attempts to com-

mence in relation to the number

of bytes written to the MAC

Transmit FIFO for the current

transmit frame. When the entire

frame is in the MAC Transmit

FIFO, transmission will start re-

gardless of the value in XMTSP.

If the netwo rk inter face is oper at-

ing in half-duplex mode, regard-

less of XMTSP, the FIFO will not

internally overwrite its data until

at least 64 bytes (or the entire

frame if shorter than 64 bytes)

have been transmitted onto the

network. This ensures that for

collisions within the slot time win-

dow, transmit data need not be

rewritten to the Transmit FIFO,

and retries will be handled auton-

omously by the MAC. If the Dis-

able Retry feature is enabled, or if

the network is operating in full-du-

plex mode, the Am79C973/

Am79C975 controller can over-

write the beginning of the frame

as soon as the data is transmit-

RCVFW[1:0] Bytes Received

00 16

01 64

10 112

11 Reserved

Am79C973/Am79C975 151

PRELIMINARY

ted, because no collision han-

dling is required in these modes.

Note that when the SRAM is be-

ing used, if the NOUFLO bit

(CSR80, b it 14) is set t o 1, there

is the additional restriction that

the complete transmit frame must

be DMA’d into the Am79C973/

Am79C975 controller and reside

within a combination of the Bus

Transmit FIFO, the SRAM, and

the MAC Transmit FIFO.

When the SRAM is used,

SRAM_SIZE > 0, there is a re-

striction that the number of bytes

written is a combination of bytes

written into the Bus Transmit

FIFO and the MAC Transmit

FIFO. The Am79C973/

Am79C975 controller supports a

mode that will wait until a full

packet is available before com-

mencing with t he tran smissi on of

preamble. This mode is useful in

a system where high latencies

cannot be avoided. See Table 27.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. XMTSP is set to a value of

01b (64 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

Table 27. Transmit Start Point Programming

9-8 XMTFW[1:0] Transmit FIFO Watermark. XMT-

FW specifies the point at which

transmit DMA is requested,

based upon the number of bytes

that could be written to the Trans-

mit FIFO without FIFO overflow.

Transmit DMA is requested at

any time when the number of

bytes sp ecified by XM TFW coul d

be written to the FIFO without

causing Transmit FIFO overflow,

and the internal microcode en-

gine has reached a point where

the Transmit FIFO is checked to

determi ne if DMA ser vicing is r e-

quired.

When operating in the NO-SRAM

mode (no SRAM enabled),

SRAM_SIZE set to 0, the Bus

Transmit FIFO and the MAC

Transmit FIFO operate like a sin-

gle FIFO and the watermark val-

ue selec ted by XMTFW[1: 0] sets

the number of FIFO byte loca-

tions that must be available in the

FIFO before receive DMA is re-

quested.

When operating with the SRAM,

the Bus Transmit FIFO and the

MAC Transmit FIFO operate in-

depend ently on the bu s side and

MAC side of the SRAM, respec-

tively. In this case, the watermark

value set by XMTFW[1:0] sets the

number of FIFO byte locations

that m ust be avai lable i n the Bus

Transmit FIFO. See Table 28.

Read/Write accessible only when

either the STO P or the SPND bit

is set. XMTFW is set to a value of

00b (16 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

7-0 DMATC[7:0] DMA Transfer Counter. Writing

and reading to this field has no ef-

fect. Use MAX_LAT and

MIN_GNT in the PCI configura-

tion space.

XMTSP[1:0] SRAM_SIZE Bytes Written

00 0 20

01 0 64

10 0 128

11 0 220 max

00 >0 36

01 >0 64

10 >0 128

11 >0 Full Packet when

NOUFLO bit is se t

Table 28. Transmit Wa termark Programming

XMTFW[1:0] Bytes Available

00 16

01 64

10 108

11 Reserved

152 Am79C973/Am79C975

PRELIMINARY

CSR82: Transmit Descriptor Address Pointer

Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 TXDAPL Contains the lower 16 bits of the

transmit descriptor address cor-

responding to the last buffer of

the previous transmit frame. If the

previous transmit frame did not

use buffer chaining, then TXDA-

PL contains the lower 16 bits of

the previous frame’s transmit de-

scriptor address.

When both the STOP or SPND

bits are cleared, this register is

updated by Am79C973/

Am79C9 75 controll er immedia t e-

ly before a transmit descriptor

write.

Read accessible always. Write

accessible through the PXDAL

bits (CSR60) when the STOP or

SPND bit is set. TXDAPL is set to

0 by H_RESET and are una ffec t-

ed by S_RESET or STOP.

CSR84: DMA Address Register Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 DMABAL This register contains the lower

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAL register is undefined

until the first Am79C973/

Am79C975 controller DMA o per-

ation.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR85: DMA Address Register Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 DMABAU This register contains the upper

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAU register is undefined

until the first Am79C973/

Am79C975 controller DMA oper-

ation.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR86: Buffer Byte Counter

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 RES Reserved. Read and written with

ones.

11-0 DMABC DMA Byte Count Register. Con-

tains the two's complement of the

current size of the remaining

transmit or receive buffer in

bytes. This register is increment-

ed by the B us Interface Un it. T h e

DMABC r eg ister i s u ndefined un-

til written.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR88: Chip ID Register Lower

Bit Name Description

31-28 VER Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the S PND bi t is se t.

Am79C973/Am79C975 153

PRELIMINARY

VER is read only. Write opera-

tions are ignored.

27-12 PA RTID Part number. T he 16-bit code for

the Am79C973 controller is

0010 0110 0010 0101 (2625h)

and the code for the Am79C975

is 0010 0110 0010 0111 (2627h).

This register is exactly the same

as the Device ID register in the

JTAG description. However, this

part numb er is differ ent from that

stored in the Device ID register in

the PCI config urati on spa ce .

Read accessible only when either

the STOP or the SPND bit is set.

PARTID is read o nly . Wr i te o per -

ations are ignored.

11-1 MANFID Manufacturer ID. The 11-bit man-

ufacturer code for AMD is

00000000001b. This code is per

the JEDEC Publication 106-A.

Note that this code is not the

same as the Vendor ID in the PCI

configur ati on sp ac e.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. MANFID is

read only. Write operations are

ignored.

0 ONE Always a logic 1.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. ONE is read

only. Write operations are ig-

nored.

CSR89: Chip ID Register Upper

Bit Name Description

31-16 RES Res erved locations . Read as un-

defined.

15-12 VER Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. VER is read

only. Write operations are ig-

nored.

11-0 PARTIDU Upper 12 bits of the Am79C973/

Am79C975 controller part num-

ber, i.e., 0010 0110 0010b

(262h).

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. PARTIDU is

read only . Write oper ations ar e

ignored.

CSR92: Ring Length Conversion

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RCON Ring Length Conversion Regis-

ter. This register performs a ring

length conversion from an encod-

ed value as found in the initializa-

tion block to a two’s complement

value used for internal counting.

By writing bits 15-12 with an en-

coded ring length, a two’s com-

plemented value is read. The

RCON register is undefined until

written.

Read/Write accessible only when

either the STO P or the SPND bit

is set. These bits are unaffected

by H_RESET, S_RESET, or

STOP.

CSR100: Bus Timeout

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MERRTO This register contains the value of

the longest allowable bus latency

(interval between assertion of

REQ and assertion of GNT) that a

system may insert into an

Am79C 973 /Am 79C9 75 c on tr oll er

master transfer. If this value of

bus latency is exceeded, then a

MERR will be indica ted in CSR0 ,

bit 11, and an interrupt may be

generated, depending upon the

Device CSR88

Am79C973 5003h

Am79C975 7003h

154 Am79C973/Am79C975

PRELIMINARY

setting of the MERRM bit (CSR3 ,

bit 11) and the IENA bit (CSR0,

bit 6).

The va lue in this registe r is inter -

preted as the unsigned number of

bus clock periods divided by two,

(i.e., the value in this register is

given in 0.1 ms increments.) For

example, the value 0600h (1536

decimal) will cause a MERR to be

indicated after 153.6 ms of bus

latency. A value of 0 will allow an

infinitely long bus latency, i.e.,

bus timeout error will never oc-

cur.

Read/Write accessible only when

either the ST OP or the SPND bit

is set. This register is set to

0600h by H_RESET or

S_RESET and is unaffected by

STOP.

CSR112: Missed Frame Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 MFC Missed Frame Count. Indicates

the number of missed frames.

MFC will roll over to a count of 0

from the value 65535. The MFCO

bit of CSR4 (bit 8) will be set each

time that this occurs.

Read accessible always. MFC is

read only, write operations are ig-

nored. MFC is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

CSR114: Receive Collision Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 RCC Receive Collision Count. Indi-

cates the total number of colli-

sions encountered by the

receiver since the last reset of the

counter.

RCC will roll over to a count o f 0

from the value 65535. The

RCVCCO bit of CSR4 (bit 5) will

be set each time that this occurs.

Read accessible always. RCC is

read only, write operations are ig-

nored. RCC is cleared by

H_RESET or S_RESET, or by

setting the STOP bit.

CSR116: OnNow Power Mode Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-14 RES Reserved locations. Written as

zeros and read as undefined.

13 LCMODE_D3C. This bit is a read/write from the

PCI bus and is reset only at

power-on. This bit is not written

from the EEPROM. Power man-

agement s oftware can set th is bi t

before go ing to D3cold a nd even

if there is a reset and the EE-

PROM loads because of an incor-

rect PG signal , the contro l bit will

not be changed. This bit is OR’ed

with LCMODE (CSR116 bit 8) for

OnNow link chnage, but not for

hardware link change

12 MPPEN_D3 C Thi s bit is read/write from the the

PCI bus and is reset only at

power-on. This bit is not written

from the EEPROM. Power man-

agement s oftware can set th is bi t

before going to D3cold and even

if there is a reset and the EE-

PROM loads because of an incor-

rect PG signal , the contro l bit will

not be changed. This bit is OR’ed

with MPPEN (CSR116 bit 4) for

both hardware magic packet or

OnNow magic packet.

11 PMAT_MO DE_ D 3C

This bit is read/writ e from the the

PCI bus and is reset only at

power-on. This bit is not written

from the EEPROM. Power man-

agement s oftware can set th is bi t

before going to D3cold and even

if there is a reset and the EE-

PROM loads because of an incor-

rect PG signal , the contro l bit will

not be changed. This bit is OR’ed

with PMAT_MODE (BCR45 bit 7)

for OnNow magic packet.

Am79C973/Am79C975 155

PRELIMINARY

10 PME_EN_OVR PME_EN Overwrite. When this

bit is set and the MPMAT or

LCDET bit is set, the PME pin wil l

always be asserted rega rdle ss of

the state of PME_EN bit.

Read /Write accessi b le onl y wh en

either th e STOP bit or the S PND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

9 LCDET Link Change Detected. This bit is

set when the MII auto-polling log-

ic detec ts a change in link sta tus

and the LCMODE bit is set.

LCDET is c leared when power is

initially applied (POR).

Read/Wr ite accessible always.

8 LCMODE Link Change Wake-up Mode.

When this bit is set to 1, the

LCDET bit ge ts set when the MII

auto polling logic detects a Link

Change.

Read /Write accessi b le onl y wh en

either th e STOP bit or the S PND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

7 PMAT Pattern Matched. This bit is set

when the PMMODE bit is set and

an OnNow pattern match occurs.

PMAT is cleared when power is

initially applied (POR).

Read access ible always.

6 EMPPLBA Magic Packet Physical Logi cal

Broadcast Accept. If both EMP-

PLBA and MPPLBA (CSR5, bit 5)

are at their default value of 0, the

Am79C973/Am79C975 controller

will only detect a Magic Packet

frame if the destination address

of the packet matches the con-

tent of the physical address regis-

ter (PADR). If either EMPPLBA or

MPPLBA is set to 1, the destina-

tion ad dress o f the Ma gic P acke t

frame can be unicast, multicast,

or broadcast. Note that the set-

ting of EMPPLBA and MPPLBA

only affects the address detection

of the Magic Packet frame. The

Magic Packet frame’s data se-

quence must be made up of 16

consecutive physical addresses

(PADR[47:0]) regardless of what

kind of destination address it has.

Read/Write accessible always.

EMPPLBA is set to 0 by

H_RESET or S_RESET and is

not affecte d by set ting the S TOP

bit.

5 MPMAT Magic Packet Match. This bit is

set when PCnet-FAST+ detects a

Magic Packet while it is in the

Magic Packet mode.

MPMAT is cleared when power is

initially applied (POR).

Read/Write ac cess ib le alwa ys .

4 MPPEN Magic Packet Pin Enable. When

this bit is set, the device enters

the Magic Packet mode when the

PG inpu t goes LOW or MPEN bi t

(CSR5, bit 2) gets set to 1. This

bit is OR’ed with MPEN bit

(CSR5, bit 2).

Read/Write is accessible only

when either the STOP bit or the

SPND bit is set. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

3 RWU_DRIVER RWU Driver Type. If this bit is set

to 1, RWU is a totem po le driver ;

otherwise RWU is an open drain

output.

Read/Write is accessible only

when either the STOP bit or the

SPND bit is set. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

2 RWU_GATE RWU Gate Control. If this bit is

set, RWU is forced to the high Im-

pedance Sta te when PG is LOW,

regardless of the state of the MP-

MAT and LCDET bits.

Read/Write accessible only when

either t he STOP bit or the SPND

156 Am79C973/Am79C975

PRELIMINARY

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

1 RWU_POL RWU Pin Polarity. If RWU_POL

is set to 1, the RWU pin is normal-

ly HIGH and asserts LOW; other-

wise RWU is normally LOW and

asserts HIGH.

Read /Write accessi b le onl y wh en

either th e STOP bit or the S PND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

0 RST_POL PHY_RST Pin Polarity. If the

PHY_POL is set to 1, the

PHY_ RST pi n is acti ve LOW ; oth-

erwise PHY_RST is active HIGH.

Read /Write accessi b le onl y wh en

either th e STOP bit or the S PND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

CSR122: Advanced Feature Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-1 RES Reserved locations. Written as

zeros and read as und efi ned.

0 RCVA LGN Rec eive Packet Ali gn. When set,

this bit forces the data field of ISO

8802-3 (IEEE/ANSI 802.3) pack-

ets to align to 0 MOD 4 address

boundaries (i.e., DWord aligned

addresses). It is important to note

that this feature will only function

correctly if all receive buffer

boundaries are DWord aligned

and all receive buffers have 0

MOD 4 lengths. In order to ac-

complish the data alignment, the

Am79C9 73/ Am 79C9 75 c on tr oll er

simply inserts two bytes of ran-

dom data at the beginning of the

receive packet (i.e., before the

ISO 8802-3 (IEEE/ANSI 802.3)

destination address field). The

MCNT field reported to the re-

ceive descriptor will not include

the extra two bytes.

Read/Write accessible always.

RCVALGN is cleared by

H_RESET or S_RESET and is

not affected by STOP.

CSR124: Test Register 1

This register is used to place the Am79C973/

Am79C975 controller into various test modes. The Runt

P acket Accept is the only user accessible test mode. All

other test modes are for AMD internal us e only.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-4 RES Reserved locations. Written as

zeros and read as undefined.

3 RPA Runt Packet Accept. This bit

forces the Am79C973/

Am79C975 controller to accept

runt packets (packets shorter

than 64 bytes).

Read accessible always; write

accessible only when STOP is

set to 1. RPA is cleared by

H_RESET or S_RESET and is

not affected by STOP.

2-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR125: MAC Enhanced Configuration Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 IPG Inter Packet Gap. Changing IPG

allows the user to program the

Am79C 973 /Am 79C9 75 c on tr oll er

for aggressiveness on a network.

By changing the default value of

96 bit times (60h) the user can

adjust the fairness or aggressive-

ness of the Am79C973/

Am79C 975 MAC on the networ k.

By prog ramming a lower number

of bit times other then the ISO/

IEC 8802-3 standard requires,

the Am79C973/Am79C975 MAC

will become more aggressive on

the network. This aggressive na-

ture will give rise to the

Am79C 973 /Am 79C9 75 c on tr oll er

possibly “capturing the network”

at times by forci ng other less ag-

Am79C973/Am79C975 157

PRELIMINARY

gressive nodes to defer. By pro-

gramming a larger number of bit

times, the Am79C973/

Am79C975 MAC will become

less aggressive on the network

and may defer more often than

normal. The performance of the

Am79C9 73/ Am 79C9 75 c on tr oll er

may decrease as the IPG value is

increased from the default value.

Note: Programming of the IPG

should be done in nibble intervals

instea d of absolu te bit times. Th e

decimal and hex values do not

match due to delays in the part

used to make up the final IPG.

Changes should be added or sub-

tracted from the provided hex val-

ue on a one-for-one basis.

CAUTION: Use this parameter

with care. By lowering the IPG

below the ISO/I EC 88 02-3 st an-

dard 96 bit times, the

Am79C973/Am79C975 control-

ler can interrupt normal net-

work behavior.

Read/Write is accessible only

when either the STOP bit or the

SPND bit is set. IPG is set to 60h

(96 Bit times) by H_RESET or

S_RESET a nd is not affected by

STOP.

7-0 IFS1 InterFrameSpacingPart1. Chang-

ing IFS1 allows the user to pro-

gram the value of the InterFrame-

SpacePart1 timing. The

Am79C9 73/ Am 79C9 75 c on tr oll er

sets the default value at 60 bit

times (3ch). See the subsection

on Medium Allocation in the sec-

tion Media Access Management

for more details.

The equation for setting IFS1

when IPG ≥ 96 bit ti me s is a s fo l-

lows:

IFS1 = IPG - 36 bit times

Note: Programming of the IPG

should be done in nibble intervals

instead of absolute bit times due

to the MII. The decimal and hex

values do not match due to de-

lays in the part used to make up

the final IPG.

Changes should be added or

subtracted from the provided hex

value on a one-for-one basis.

Due to changes in synchroniza-

tion dela ys internally through dif-

ferent network ports, the IFS1

can b e off b y as mu ch as +12 bit

times.

Read/Write is accessible only

when either the STOP bit or the

SPND bit is set. IFS1 is set to 3ch

(60 bit times) by H_RESET or

S_RESET a nd is not affected by

STOP.

Bus Configuration Registers

The Bus Configuration Registers (BCR) are used to

program the configuration of the bus interface and oth-

er spec ial features of the Am 79C973/Am 79C975 con-

troller that are not related to the IEEE 8802-3 MAC

functions. The BCRs are accessed by first setting the

appropriate RAP value and then by performing a slave

access to the BDP. See Table 29.

All BCR registers are 16 bits in width in W ord I/O mode

(D WIO = 0, BCR18, bit 7) and 32 bits in width in D Word

I/O mode (DWIO = 1). The upper 16 bits of all BCR reg-

isters is undefined when in DWord I/O mode. These

bits should be written as zeros and should be treated

as undefined when read. The default value given for

any BCR is the value in the register after H_RESET.

Some of these values may be changed shortly after

H_RESET when the contents of the e xternal EEPROM

is autom atica lly read i n. None of the BCR regist er val-

ues are affected by the assertion of the STOP bit or

S_RESET.

Note that several registers have no default value.

BCR0, BCR1, BCR3, BCR8, BCR10-17, and BCR21

are reserved and have undefined values. BCR2 and

BCR34 are not observable without first being pro-

grammed through the EEPROM read operation or a

user register write operation.

BCR0, BCR1, B CR16, BCR17, and BCR21 are regi s-

ters that are used by other devices in the PCnet family.

Wri ting t o these registe rs h ave no effect on the op era-

tion of the Am79C973/Am79C975 controller.

Writes to those registers marked as “Reserved” will

hav e no effect. Reads from these locations will produce

undefined values.

158 Am79C973/Am79C975

PRELIMINARY

BCR0: Master Mode Read Active

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 MSRDA Reserved locations. After

H_RESET, the value in this regis-

ter will be 0005h. The setting of

this registe r has no effect on any

Am79C9 73/ Am 79C9 75 c on tr oll er

function. It is only included for

software compatibility with other

PCnet family devices.

Read always. MSRDA is read

only. Write operations have no ef-

fect.

BCR1: Master Mode Write Active

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MSWRA Reserved locations. After

H_RESET, the value in this regis-

ter will be 0005h. The setting of

this regist er has no effect on any

Am79C 973 /Am 79C9 75 c on tr oll er

function. It is only included for

software compatibility with other

PCnet fami ly de vic es.

Read always. MSWRA is read

only. Write operations have no ef-

fect.

Am79C973/Am79C975 159

PRELIMINARY

Table 29. BCR Registers (Am79C973)

RAP Mnemonic Default Name Programmability

User EEPROM

0MSRDA 0005h Reserved No No

1MSWRA 0005h Reserved No No

2MC 0002h Miscellaneous Configuration Yes Yes

3Reserved N/A Reserved No No

4LED0 00C0h LED0 Status Yes Yes

5LED1 0084h LED1 Status Yes Yes

6LED2 0088h LED2 Status Yes Yes

7LED3 0090h LED3 Status Yes Yes

8Reserved N/A Reserved No No

9FDC 0000h Full-Duplex Control Yes Yes

10-15 Reserved N/A Reserved No No

16 IOBASEL N/A Reserved No No

17 IOBASEU N/A Reserved No No

18 BSBC 9001h Burst and Bus Control Yes Yes

19 EECAS 0002h EEPROM Control and Status Yes No

20 SWS 0000h Software Style Yes No

21 INTCON N/A Reserved No No

22 PCILAT FF06h PCI Latency Yes Yes

23 PCISID 0000h PCI Subsystem ID No Yes

24 PCISVID 0000h PCI Subsystem Vendor ID No Yes

25 SRAMSIZ 0000h SRAM Size Yes Yes

26 SRAMB 0000h SRAM Boundary Yes Yes

27 SRAMIC 0000h SRAM Interface Control Yes Yes

28 EBADDRL N/A Expansion Bus Address Lower Yes No

29 EBADDRU N/A Expansion Bus Address Upper Yes No

30 EBD N/A Expansion Bus Data Port Yes No

31 STVAL FFFFh Software Timer Value Yes No

32 MIICAS 0000h PHY Control and Statu s Yes Yes

33 MIIADDR 0000h PHY Address Yes Yes

34 MIIMDR N/A PHY Managem ent Data Yes No

35 PCIVID 1022h PCI Vendor ID No Yes

36 PMC_A C811h PCI Power Management Capabilities (PMC)

Alias Register No Yes

37 DATA0 0000h PCI DATA Register Zero Alias Register No Yes

38 DATA1 0000h PCI DATA Register On e Alia s Register No Yes

39 DATA2 0000h PCI DATA Register Two Alias Register No Yes

40 DATA3 0000h PCI DATA Register Three Alias Register No Yes

41 DATA4 0000h PCI DATA Register Four Alias Register No Yes

42 DATA5 0000h PCI DATA Register Five Alias Register No Yes

43 DATA6 0000h PCI DATA Register Six Alias Register No Yes

44 DATA7 0000h PCI DATA Register Seven Alias Register No Yes

45 PMR1 N/A Pattern Matching Register 1 Yes No

46 PMR2 N/A Pattern Matching Register 2 Yes No

47 PMR3 N/A Pattern Matching Register 3 Yes No

48 Reserved 0000h Reserved (for Am79C975) Yes* Yes*

49 Reserved 0000h Reserved (for Am79C975) Yes* Yes*

50 Reserved 0000h Reserved (for Am79C975) Yes* Yes*

51 Reserved 0000h Reserved (for Am79C975) Yes* Yes*

52 Reserved 0000h Reserved (for Am79C975) Yes* Yes*

160 Am79C973/Am79C975

PRELIMINARY

Note: *Program only as ‘0’ value.

53 Reserved 0000h Reserved (for Am79C975) Yes* Yes*

54 Reserved 0000h Reserved (for Am79C975) Yes* Yes*

Table 29. BCR Registers (Am79C973)

Am79C973/Am79C975 161

PRELIMINARY

Table 30. BCR Registers (Am79C975)

RAP Mnemonic Default Name Programmability

User EEPROM

0MSRDA 0005h Reserved No No

1MSWRA 0005h Reserved No No

2MC 0002h Miscellaneous Configuration Yes Yes

3Reserved N/A Reserved No No

4LED0 00C0h LED0 Status Yes Yes

5LED1 0084h LED1 Status Yes Yes

6LED2 0088h LED2 Status Yes Yes

7LED3 0090h LED3 Status Yes Yes

8Reserved N/A Reserved No No

9FDC 0000h Full-Duplex Control Yes Yes

10-15 Reserved N/A Reserved No No

16 IOBASEL N/A Reserved No No

17 IOBASEU N/A Reserved No No

18 BSBC 9001h Burst and Bus Control Yes Yes

19 EECAS 0002h EEPROM Control and Status Yes No

20 SWS 0000h Software Style Yes No

21 INTCON N/A Reserved No No

22 PCILAT FF06h PCI Latency Yes Yes

23 PCISID 0000h PCI Subsystem ID No Yes

24 PCISVID 0000h PCI Subsystem Vendor ID No Yes

25 SRAMSIZ 0000h SRAM Size Yes Yes

26 SRAMB 0000h SRAM Boundary Yes Yes

27 SRAMIC 0000h SRAM Interface Control Yes Yes

28 EBADDRL N/A Expansion Bus Address Lower Yes No

29 EBADDRU N/A Expansion Bus Address Upper Yes No

30 EBD N/A Expansion Bus Data Port Yes No

31 STVAL FFFFh Software Timer Value Yes No

32 MIICAS 0000h PHY Control and Statu s Yes Yes

33 MIIADDR 0000h PHY Address Yes Yes

34 MIIMDR N/A PHY Managem ent Data Yes No

35 PCIVID 1022h PCI Vendor ID No Yes

36 PMC_A C811h PCI Power Management Capabilities (PMC)

Alias Register No Yes

37 DATA0 0000h PCI DATA Register Zero Alias Register No Yes

38 DATA1 0000h PCI DATA Register On e Alia s Register No Yes

39 DATA2 0000h PCI DATA Register Two Alias Register No Yes

40 DATA3 0000h PCI DATA Register Three Alias Register No Yes

41 DATA4 0000h PCI DATA Register Four Alias Register No Yes

42 DATA5 0000h PCI DATA Register Five Alias Register No Yes

43 DATA6 0000h PCI DATA Register Six Alias Register No Yes

44 DATA7 0000h PCI DATA Register Seven Alias Register No Yes

45 PMR1 N/A Pattern Matching Register 1 Yes No

46 PMR2 N/A Pattern Matching Register 2 Yes No

47 PMR3 N/A Pattern Matching Register 3 Yes No

48 N_IP_ADR[15:0] 0000h Node IP Address [15:0] Yes Yes

49 N_IP_ADR[31:16] 0000h Node IP Address [31:16] Yes Yes

50 M_IEEE_ADR[15:0] 0000h Management IEEE Address [15:0] Yes Yes

51 M_IEEE_ADR[31:16] 0000h Management IEEE Address [31:16] Yes Yes

52 M_IEEE_ADR[47:32] 0000h Management IEEE Address [47:32] Yes Yes

162 Am79C973/Am79C975

PRELIMINARY

BCR2: Miscellaneous Configuration

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 SMIUEN (For Am79C975 only) SMIUEN is

used to enable /disable the Serial

Management Interface Unit in the

Am79C9 75 co ntrol ler .

If SMIUEN is set to 0 (default),

the SMIU is disable. If SMIUEN is

set to 1, the SMIU is enabled.

Read/Write accessible always.

SMIUEN is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

14 DISSCR_SFEX

This bit is used to disable the

scrambler/descrambler when the

device is used in PECL mode.

This bit defaults to 0, which en-

ables the scrambler/descrambler

for MLT3 applications.

When DISSCR_ SFE X is set to 1,

the scrambler will be disabled for

fiber applications.

Read/Write accessible always.

This bit is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

13 PHYSELEN This bit enables writes to

BCR18[4:3] for software selec-

tion of various o peration and test

modes. When PHYSELEN is set

to 0 (default), the two bits can

only be written from the EE-

PROM. When PHYSELEN is set

to 1, wri t es t o BC R18[ 4:3 ] a re en -

abled.

Read/Write accessible always.

PHYSELEN is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

12 LEDPE LED Program Enable. When

LEDPE is set to 1, programming

of the LED0 (BCR4), LED1

(BCR5), LED2 (BCR6), and

LED3 (BCR7) registers is en-

able d. When LEDPE is cleared to

0, programming of LED0 (BCR4),

LED1 (BCR5), LED2 (BCR6),

and LED3 (BCR7) registers is

disabled. Writes to those regis-

ters will be ignored.

Read/Write accessible always.

LEDPE is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

11 RESET_SFEX

This bit is used to re set the i nter-

nal PHY. When RESET_SFEX is

set to 1, the internal PHY will stay

reset until RESET_SFEX is

cleared to 0.

Read/Write accessible always.

RESET_SFEX is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

10 I2C_M3 (Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D6 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M3 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

9 I2C_M2 (Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

53 M_IP_ADR[15:0] 0000h Management IP Address [15:0] Yes Yes

54 M_IPADR[31:16] 0000h Management IP Address [31:16] Yes Yes

Table 30. BCR Registers (Am79C975)

Am79C973/Am79C975 163

PRELIMINARY

value in the D5 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M2 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

8 APROMWE Address PROM Write Enable.

The Am79C973/Am79C975 con-

troller contains a shadow RAM on

board for storage of the first 16

bytes loaded from the serial EE-

PROM. Accesses to Address

PROM I/O Resources will be di-

rected toward this RAM. When

APROMWE is set to 1, then write

access to the shadow RAM will

be enabled .

Read/Write accessible always.

APROMWE is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

7 INTLEVEL Interrupt Level. This bit allows the

interr upt outp ut si gna ls to be pro-

grammed for level or edge-

sensitive applications.

When I NTLEVEL is cl eared to 0,

the INTA pin is configured for

level-sensitive applications. In

this mode, an int errupt re quest is

signaled by a low level driv en on

the INTA pin by the Am79C973/

Am79C975 controller. When the

interrupt is cleared, the INTA pin

is tri-stated by the Am79C973/

Am79C975 controller and al-

lowed to be pulled to a high level

by an external pullup device. This

mode is intended for systems

which allow the interrupt signal to

be shared by multip le devices.

When INTLEVEL is set to 1, the

INTA pin is configured for edge-

sensitive applications. In this

mode, an in terru pt re que st is sig-

naled by a high level driven on

the INTA pin by the Am79C973/

Am79C975 controller. When the

interrupt is cleared, the INTA pin

is driven to a low level by the

Am79C973/Am79C975 control-

ler. This mode is intended for sys-

tems that do not allow interrupt

channels to be shared by multiple

devices.

INTLEVEL sho uld no t be se t to 1

when the Am79C973/Am79C975

controller is used in a PCI bus ap-

plication.

Read/Write accessible always.

INTLEVEL is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

6 I2C_M1 (Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D4 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M1 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

5 I2C_M0 (Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D3 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M0 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

4 I2C_N2 (Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D2 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_N2 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

3 EADISEL EADI Select. When set to 1, this

bit enables the three EADI inter-

face pins that are multiplexed

with other functions. E ESK/ LED1

becomes SFBD, EEDO/LED3

becomes MIIRXFRTGD, and

LED2 becomes MIIRXFRTGE.

164 Am79C973/Am79C975

PRELIMINARY

See the section on External Ad-

dress Dete cti on for more details.

Read/Write accessible always.

EADISEL is cleared by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

2 SLEEP_SFEX

Setting this bit will reduce the

power consumption of the inter-

nal PHY substantially.

Read/Write accessible always.

SLEEP_SFEX is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

1 I2C_N1 (Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D1 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_N1 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

0 I2C_N0 (Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D0 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_N0 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

BCR4: LED 0 Status

BCR4 controls the function(s) that the LED0 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED displa y will indicate the

logical OR of the enabled functions. BCR4 defaults to

Link Status (LNKST) with pulse stretcher enabled

(PSE = 1) and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED0 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED0 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of th e LED

output pin. A v alue of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical val ue of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

Read acce ssible al ways. This bi t

is read only; writes have no ef-

fect. LEDOUT is unaffected by

H_RESET, S_RESET, or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s f als e (i .e., t he L ED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole ou tput and the ou tput value

will be the same polarity as the

LEDOUT status bit.).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible always.

LEDPOL is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

Am79C973/Am79C975 165

PRELIMINARY

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be g overned by the LE DOUT

and LEDPOL values.

Read/Write accessible always.

LEDDIS is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a v alue of 1 is passe d

to the LEDOUT bit in this register

when the Am79C973/Am79C975

controller is operating at 100

Mbps mode.

Read/Write accessible always.

100E is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

11-10 RES Reserved locations. Written and

read as zero s.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passed to the LE DOUT bit in

this register when Magic Packet

frame mode is enabled and a

Magic Packet frame is detected

on the network.

Read/Write accessible always.

MPSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C973/

Am79C975 controller is function-

ing in a Link Pass state and full-

duplex operation is enabled.

When the Am79C973/

Am79C975 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

Read/Write accessible always.

FDLSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible always.

PSE is set to 1 by H_RESET and

is not affected by S_RESET or

setting the STOP bit.

6 LNKSE Link Status Enable. When this bit

is set, a val ue of 1 w ill be pas sed

to the LEDOUT bit in this register

when in Link Pass state.

Read/Write accessible always.

LNKSE is set to 1 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast and promiscuous.

Read/Write accessible always.

RCVME is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

activity on the network.

Read/Write accessible always.

XMTE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

3 RES Reserved location. Written and

read as zeros.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

166 Am79C973/Am79C975

PRELIMINARY

tivity on the network.

Read/Write accessible always.

RCVE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

1 RES Reserved location. Written and

read as zero s.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible always.

COLE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

BCR5: LED1 Status

BCR5 controls the function(s) that the LED1 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED displa y will indicate the

logical OR of the enabled functions. BCR5 defaults to

Receive Status (RCV) with pulse stretcher enabled

(PSE = 1) and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED1 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED1 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 LEDOUT This bit indicates the current

(non-stretched) value of the LED

output pin. A va lue of 1 in this bi t

indicates that the OR of the en-

abled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

Read acce ssible always. This bit

is read only, writes have no ef-

fect. LEDOUT is unaffected by

H_RESET, S_RESET, or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s f als e (i .e., t he L ED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole ou tput and the ou tput value

will be the same polarity as the

LEDOUT status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible always.

LEDPOL is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be governed by th e LEDOUT

and LEDPOL values.

Read/Write accessible always.

LEDDIS is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C973/Am79C975

controller is operating at 100

Mbps mode.

Read/Write accessible always.

100E is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

Am79C973/Am79C975 167

PRELIMINARY

11-10 RES Reserved locations. Written and

read as zero s.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passed to the LE DOUT bit in

this register when Magic Packet

mode is enabled and a Magic

Packet frame is detected on the

network.

Read/Write accessible always.

MPSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C973/

Am79C975 controller is function-

ing in a Link Pass state and full-

duplex operation is enabled.

When the Am79C973/

Am79C975 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

Read/Write accessible always.

FDLSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible always.

PSE is set to 1 by H_RESET and

is not affected by S_RESET or

setting the STOP bit.

6 LNKSE Link Status Enable. When this bit

is set, a v alu e of 1 w ill be p as se d

to the LEDOUT bit in this register

in Link Pass state.

Read/Write accessible always.

LNKSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

Read/Write accessible always.

RCVME is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

activity on the network.

Read/Write accessible always.

XMTE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

3 RES Reserved location. Written and

read as zeros.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network.

Read/Write accessible always.

RCVE is set to 1 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

1 RES Reserved location. Written and

read as zeros.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

activity on the network.

Read/Write accessible always.

COLE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

168 Am79C973/Am79C975

PRELIMINARY

BCR6: LED2 Status

BCR6 controls the function(s) that the LED2 pin dis-

plays. Multiple functions can be simultaneously enabled

on this LED pin. The LED display will indicate the logical

OR of the enabled functions.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED2 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED2 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM PREAD operation.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 LEDOUT This bit indicates the current

(non-stretched) value of the LED

output pin. A va lue of 1 in this bi t

indicates that the OR of the en-

abled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

Read acce ssible always. This bit

is read only; writes have no ef-

fect. LEDOUT is unaffected by

H_RESET, S_RESET, or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s fals e ( i.e., the LED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole outpu t and the ou tput value

will be the same polarity as the

LEDOUT status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible always.

LEDPOL is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be governed by th e LEDOUT

and LEDPOL values.

Read/Write accessible always.

LEDDIS is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C973/Am79C975

controller is operating at 100

Mbps mode.

Read/Write accessible always.

100E is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

11-10 RES Reserved locations. Written and

read as zeros.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passe d to the LEDOUT bit in

this register when Magic Packet

frame mode is enabled and a

Magic Packet frame is detected

on the network.

Read/Write accessible always.

MPSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C973/

Am79C973/Am79C975 169

PRELIMINARY

Am79C975 controller is function-

ing in a Link Pass state and full-

duplex operation is enabled.

When the Am79C973/

Am79C975 c ontroll er is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

Read/Write accessible always.

FDLSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible always.

PSE is set to 1 by H_RESET and

is not affected by S_RESET or

setting the STOP bit.

6 LNKSE Link Status Enable. When this bit

is set, a v alu e of 1 w ill be p as se d

to the LEDOUT bit in this register

in Link Pass state.

Read/Write accessible always.

LNKSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

Read/Write accessible always.

RCVME is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible always.

XMTE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

3 RES Reserved location. Written and

read as zeros.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

tivity on the network.

Read/Write accessible always.

RCVE is set to 1 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

1 RES Reserved location. Written and

read as zeros.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDO UT bit in th is

activity on the network.

Read/Write accessible always.

COLE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

BCR7: LED3 Status

BCR7 controls the function(s) that the LED3 pin dis-

plays. Multiple functions can be simultaneously enabled

on this LED pin. The LED display will indicate the logical

OR of the enabled functions. BCR7 defaults to Transmit

Status (XMT) with pulse stretcher enabled (PSE = 1)

and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED3 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED3 register is disabled. Writes to those registers will

be ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of th e LED

output pin. A v alue of 1 in this bit

indicates that the OR of the en-

abled signals is true.

170 Am79C973/Am79C975

PRELIMINARY

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

Read acce ssible always. This bit

is read only; writes have no ef-

fect. LEDOUT is unaffected by

H_RESET, S_RESET, or STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the n the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals i s fals e ( i.e., the LED o ut-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit.).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole outpu t and the ou tput value

will be the same polarity as the

LEDOU T status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible always.

LEDPOL is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be g overned by the LE DOUT

and LEDPOL values.

Read/Write accessible always.

LEDDIS is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C973/Am79C975

controller is operating at 100

Mbps mode.

Read/Write accessible always.

100E is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

11-10 RES Reserved locations. Written and

read as zeros.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value of

1 is passe d to the LEDOUT bit in

this register when magic frame

mode is enabled and a magic

frame is detected on the network.

Read/Write accessible always.

MPSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C973/

Am79C975 controller is function-

ing in a Link Pass state and full-

duplex operation is enabled.

When the Am79C973/

Am79C 975 c ontroll er i s not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

Read/Write accessible always.

FDLSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible always.

PSE is set to 1 by H_RESET and

is not affected by S_RESET or

setting the STOP bit.

Am79C973/Am79C975 171

PRELIMINARY

6 LNKSE Link Status Enable. When this bit

is set, a v alu e of 1 w ill be p as se d

to the LEDOUT bit in this register

in Link Pass state.

Read/Write accessible always.

LNKSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

Read/Write accessible always.

RCVME is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible always.

XMTE is set to 1 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

3 RES Reserved location. Written and

read as zero s.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

Read/Write accessible always.

RCVE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

1 RES Reserved location. Written and

read as zero s.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible always.

COLE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

BCR9: Full-Duplex Control

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-3 RES Reserved locations. Written as

zeros and read as undefined.

2 FDRPAD Full-Duplex Runt Packet Accept

Disable. When FDRP AD is set t o

1 and full-duplex mode is en-

abled, the Am79C973/

Am79C975 controller will only re-

ceive frames that meet the mini-

mum Ethe rn et fra me l en gth of 6 4

bytes. R ec eiv e DMA will not s tar t

until at least 64 bytes or a com-

plete frame have been received.

By default, FDRPAD is cleared to

0. The Am79C973/Am79C975

controller will accept any length

frame and receive DMA will start

according to the programming of

the receive FIFO watermark.

Note that there should not be any

runt packets in a full-duplex net-

work, since the main cause for

runt packets is a network collision

and there are no collisions in a

full-duplex network. This bit

needs to be set if in full-duplex

mode and external address rejec-

tion (EAR (BCR9, bit 2)) function-

ality is desired.

Read/Write accessible always.

FDRPAD is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

1 RES Reserved locations. Written as

zeros and read as undefined.

0 FDEN Full-Duplex Enable. FDEN con-

trols whether full-duplex opera-

tion is enabled. When FDEN is

cleare d and the Auto- Negotia tion

is disabled, full-duplex operation

is not enabled and the

Am79C 973 /Am 79C9 75 c on tr oll er

172 Am79C973/Am79C975

PRELIMINARY

will always operate in the half-du-

plex mode. When FDEN is set,

the Am79C973/Am79C975 con-

troller will operate in full-duplex

mode. Do not set this bit when

Auto-Negotiatio n is enabled.

Read/Write accessible always.

FDEN is reset to 0 by H_RESET,

and is unaffected by S_RESET

and the STOP bit .

BCR16: I/O Base Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-5 IOBASEL Reserved locations. After

H_RESET, the value of these bits

will be u ndefin ed. Th e setting s of

these bits will have no effect on

any Am79C973/Am79C975 con-

troller fu nction. It is only inc luded

for software compatibility with

other PCnet family devices.

Read/Write accessible always.

IOBASEL is not affected by

S_RESET or STOP.

4-0 RES Reserved locations. Written as

zeros, read as undefined.

BCR17: I/O Base Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 IOBASEU Reserved locations. After

H_RESET, the value in this regis-

ter will be undefined. The settings

of this regis ter will have no effec t

on any Am79C973/Am79C975

controller function. It is only in-

cluded for software compatibility

with other PCnet family devices.

Read/Write accessible always.

IOBASEU is not affected by

S_RESET or STOP.

BCR18: Burst and Bus Control Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 ROMTMG Expansion ROM Timing. The val-

ue of ROMTMG is used to tune

the timing for all EBDATA

(BCR30) accesses to Flash/

EPROM as wel l as all Expansion

ROM accesses to Flash/EPROM.

ROMTMG, during read opera-

tions, defines the time from when

the Am79C973/Am79C975 con-

troller drives the lower 8 or 16 bits

of the Expansion Bus Address

bus to when the Am79C973/

Am79C975 controller latches in

the data on the 8 or 16 bits of the

Expansion Bus Data inputs.

ROMTMG, during write opera-

tions, defines the time from when

the Am79C973/Am79C975 con-

troller drives the lower 8 or 16 bits

of the Expansion Bus Data to

when the EBWE and EROMCS

deassert.

The register value specifies the

time in number of clock cycles +1

according to Table 31.

Note: Programming ROMTNG

with a value of 0 is not permitted.

The access time for the Expan-

sion ROM or the EBDATA

(BCR30) device (tACC) during

read operations can be calculat-

ed by subtracting the clock to out-

put delay for the EBUA_EBA[7:0]

outputs (tv_A_D) and by subtract-

ing the input to clock setup time

for the EBD[7:0] inputs (ts_D)

from the time defined by ROMT-

MG:

tACC = ROMTMG * CLK period

*CLK_FAC - (tv_A_D) - (ts_D)

Table 31. ROMTNG Programming Values

ROMTMG (bits 15-12) No. of Expansion Bus Cycles

1h<=n <=Fh n+1

Am79C973/Am79C975 173

PRELIMINARY

The access time for the Expan-

sion ROM or for the EBDATA

(BCR30) device (tACC) during

write operations can be calculat-

ed by subtracting the clock to out-

put delay for the EBUA EBA [7:0]

outputs (tv_A_D) and by adding

the input to clock setup time for

Flash/EPRO inputs (ts_D) from

the time defined by ROMTMG.

tACC = ROMTM G * C LK per iod *

CLK_FAC - (tv_A_D) - (ts_D)

For an adapter card application,

the value used for clock period

should be 30 ns to guarantee cor-

rect interface timing at the maxi-

mum clock frequency of 33 MHz.

Read accessible always; write

accessible only when the STOP

bit is set. ROMTMG is set to the

value of 1001b by H_RESET and

is not affected by S_RESET or

STOP. The default value allows

usi ng an Ex pansi on RO M with an

access time of 250 ns in a system

with a max imum clock freq uency

of 33 MHz.

11 NOUFLO No Underflow on Transmit. When

the NOUFLO bit is set to 1, the

Am79C9 73/ Am 79C9 75 c on tr oll er

will not s tart transmit ting the pre-

amble for a packet until the

Transmit Start Point (CSR80, bits

10-11) requirement (except when

XMTSP = 3h, Full Packet has no

meaning when NOUFLO is set to

1) has been met and the com-

plete packet has been DMA’d into

the Am79C973/Am79C975 con-

troller. The complete packet may

reside in any combination of the

Bus Transmit FIFO, the SRAM,

and the MAC Transmit FIFO, as

long as enough of the packet is in

the MAC Transmit FIFO to meet

the Transmit Start Point require-

ment. When the NOUFLO bit is

cleared to 0, the Transmit Start

Point is the only restriction on

when preamble transmission be-

gins for transmit packets.

Setting the NOUFLO bit guaran-

tees that the Am79C973/

Am79C975 controller will never

suffer transmit underflows, be-

cause the arbiter that controls

transfers to and from the SRAM

guarantees a worst case latency

on transfers to and from the MAC

and Bus Transmit FIFOs such

that it will never underflow if the

complete packet has been

DMA’d into the Am79C973/

Am79C975 controller before

packet transmission begins.

The NOUFLO bit has no effect

when the Am79C973/Am79C975

controller is operat ing in the NO-

SRAM mode.

Read/Write accessible only when

either the STO P or the SPND bit

is set. NOUFLO is cleared to 0 af-

ter H_RESET or S_RESET and

is unaffected by STOP.

10 RES Reserved location. Written as ze-

ros and read as undefined.

9 MEMCMD Memory Command used for burst

read accesses to the transmit

buffer. When MEMCMD is set to

0, all burst read accesses to the

transmit buffer are of the PCI

command type Memory Read

Line (type 14). When MEMCMD

is set to 1, all burst read accesses

to the transmit buffer are of the

PCI command type Memory

Read Multiple (type 12).

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

MEMCMD is cleared by

H_RESET an d is not affected by

S_RESET or STOP.

8 EXTREQ Extended Request. This bit con-

trols the deassertion of REQ for a

burst transaction. If EXTREQ is

set to 0, REQ is deasserted at the

beginning of a burst transaction.

(The Am79C973/Am79C975

controller never performs more

than one burst transaction within

a single bus mastership period.)

In this mode, the Am79C973/

Am79C975 controller relies on

the PCI latency timer to get

enough bus bandwidth, in case

the system arbiter also removes

174 Am79C973/Am79C975

PRELIMINARY

GNT at the beginning of the burst

transaction. If EXTREQ is set to

1, REQ stays asserted until the

last but one data phase of the

burst transaction is done. This

mode is useful for systems that

implemen t an arbitration scheme

without preemption and require

that REQ stays asserted through-

out the transaction.

EXTREQ should not be set to 1

when the Am7 9C97 3/A m79 C97 5

controller is used in a PCI bus ap-

plication.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set. EX-

TREQ is cleared by H_RESET

and is not affected by S_RESET

or STOP.

7 DWIO Double Word I/O. When set, this

bit indicates that the Am79 C973/

Am79C975 controller is pro-

grammed for DWord I/O (DWIO)

mode. When cleared, this bit indi-

cates that the Am79C973/

Am79C975 controller is pro-

grammed for Word I/O (WIO)

mode. This bit affects the I/O Re-

source Offset map and it affects

the defined width of the

Am79C973/Am79C975 control-

lers I /O reso urces. S ee the DWIO

and WIO sections for more de-

tails.

The initial value of the DWIO bit is

determined by the programming

of the EEPROM.

The value of DWIO can be al-

tered automatically by the

Am79C973/Am79C975 control-

ler. Specifically, the Am79C973/

Am79C975 controller will set

DWIO if it d etects a DWord write

access to offset 10h from the

Am79C973/Am79C975 controller

I/O base add ress ( corr espond in g

to the RDP resource).

Once th e DWIO bit has been se t

to a 1, only a H_RES ET or an EE-

PROM read can reset it to a 0.

(N ot e th at t he EEPRO M re ad op -

eration will only set DWIO to a 0 if

the appropriate bit inside of the

EEPROM is set to 0.)

Read accessible always. DWIO

is read only, write operations

have no effect. DWIO is cleared

by H_RES ET and is not affe cted

S_RESET or by setting the STOP

bit.

6 BREADE Burst Read Enable. When set,

this bit enables burst mode during

memory read accesses. When

cleared, this bit prevents the de-

vice from performing bursting

during read accesses. The

Am79C 973 /Am 79C9 75 c on tr oll er

can perform bu rst t rans fer s whe n

reading the initialization block,

the descriptor ring entries (when

SWSTYLE = 3) and the buffer

memory.

BREADE should be set to 1 when

the Am79C973/Am79C975 con-

troller is used in a PCI bu s appli-

cation to guarantee maximum

performance.

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

BREADE is cleared by H_RESET

and is not affected by S_RESET

or STOP.

5 BWRITE Burst Write Enable. When set,

this bit enables burst mode during

memory write accesses. When

cleared, this bit prevents the de-

vice from performing bursting

during write accesses. The

Am79C 973 /Am 79C9 75 c on tr oll er

can perform bu rst t rans fer s whe n

writing the descriptor ring entries

(when SWSTYLE = 3) and the

buffer memory.

BWRITE should be set to 1 when

the Am79C973/Am79C975 con-

troller is used in a PCI bu s appli-

cation to guarantee maximum

performance.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set.

BWRITE is cleared by H_RESET

Am79C973/Am79C975 175

PRELIMINARY

and is not affected by S_RESET

or STOP.

4-3 PHYSEL[1:0]

PHYSEL[1:0] bits allow for soft-

ware controlled selection of differ-

ent operation and test modes.

The normal mode of operation is

when both bi ts 0 and 1 are set t o

0 to select the Expansion ROM/

Flash. Setti ng bit 0 to 1 and bit 1

to 0 allow s snooping of th e inter-

nal MII-compatible bus to allow

External Address Detection Inter-

face (EADI). Setting PHY-

SEL[1:0] = 10 enables the

external MII mode. Since the in-

ternal 10/100 PHY is disabled in

this mode, the Am79C973/

Am79C975 controller behaves

like an Am79C972 PCnet-FAST+

device. Tehese controllers are

not designed to support two

PHYs a t a time as only one PHY

can be used at a given time. An

external or internal PHY can be

used by reconfiguring the EE-

PRO M or the BCI 18 regi ster. See

the following table for details.

Read accessible always, these

bits can only be written from the

EEPROM unless a write-enable

bit BCR2[13], is set. PHYSEL

[1:0] is cleared by H_RESET and

is not affected by S_RESET or

STOP.

2-0 LINB C Reser v ed loca t ion s. Read ac ces-

sible always; write accessible

only when either the STOP or the

SPND bit is set. A fter H_RE SET,

the value in these bits will be

001b. The setting of these bits

have no effect on any

Am79C9 73/ Am 79C9 75 c on tr oll er

function. LINBC is not affected by

S_RES ET or STOP .

BCR19: EEPROM Control and Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PVALID EEPROM Valid status bit. Read

accessible only. PVALID is read

only; write operations have no ef-

fect. A value of 1 in this bit indi-

cates that a PREAD operation

has occurred, and that (1) there is

an EEPROM connected to the

Am79C 973 /Am 79C9 75 c on tr oll er

interface pins and (2) the con-

tents read from the EEPROM

have passed the c hecksum verifi -

cation operation.

A value of 0 in thi s bi t indi ca tes a

failure in reading the EEPROM.

The checksum for the entire 82

bytes of EEPROM is incorrect or

no EEPROM is connected to the

interface pins.

PVALID is set to 0 during

H_RESET and is unaffected by

S_RESET or the STO P bi t. How-

ever, following the H_RESET op-

eration, an automatic read of the

EEPROM will be per fo rm ed. Just

as is true for the normal PREAD

command, at the end of this auto-

matic read operation, the PVALID

bit may be set to 1. Therefore,

H_RESET will set the PVALID bit

to 0 at first, but the automatic EE-

PROM read operation may later

set PVALID to a 1.

If PVALID becomes 0 following

an EEPROM read operation (ei-

ther automatically generated af-

ter H_RESET, or requested

through PREAD), then all EE-

PROM-pro gramm abl e B CR l oca-

tions will be reset to their

H_RESET values. The content of

the Address PROM locations,

however, will not be cleared.

If no EEPROM is present at the

EESK, EEDI, and EEDO pins,

then all attempted PREAD com-

mands will terminate early and

PVALID will not be set. This ap-

plies to th e autom atic read of the

PHYSEL [1:0] Mode

00 Expansion ROM/Flash - Normal Mode

01 EADI/Internal MII Snoop Mode

10 Full MII Mode - An External PHY

Required

11 Reserved

176 Am79C973/Am79C975

PRELIMINARY

EEPROM after H_RESET, as

well as to host-initiated PREAD

commands.

14 PREAD EEPROM Read command bit.

When this bit is set to a 1 by the

host, the P VALID bit (BCR19 , bit

15) will imm ediate ly be res et to a

0, and then the Am79C973/

Am79C975 controller will perform

a read operation of 82 bytes from

the EEPROM through the inter-

face. The EEPROM data that is

fetched during the read will be

stored in the appropriate internal

registers on board the

Am79C973/Am79C975 control-

ler. Upon completion of the EE-

PROM read operation, the

Am79C9 73/ Am 79C9 75 c on tr oll er

will assert the PVALID bit. EE-

PROM contents will be indirectly

accessible to the host through

read accesses to the Address

PROM (offsets 0h through Fh)

and through read accesses to

other EEPROM programmable

registers. Note that read access-

es from these locations will not

actually access the EEPROM it-

self, but instead will access the

Am79C973/Am79C975 control-

lers internal copy of the EEPROM

contents. Write accesses to these

locations may change the

Am79C9 73/ Am 79C9 75 c on tr oll er

PROM locations will not be affect-

ed. EEPROM locations may be

accessed directly through

BCR19.

At the end of the read operation,

the PREAD bit will automatically

be reset to a 0 by the Am79C973/

Am79C975 controller and

PVALID wi ll b e s et, prov i ded tha t

an EEPROM existed on the inter-

face pins an d that the checksum

for the entire 82 bytes of EE-

PROM was corre ct.

Note that when PREAD is set to a

1, then the Am79C973/

Am79C975 controller will no

longer respond to any accesses

directed toward it, until the

PREAD operation has completed

successfully. The Am79C973/

Am79C975 controller will termi-

nate thes e acces ses with the a s-

sertion of DEVSEL and STOP

while TRDY is not asserted, sig-

naling to the initiator to discon-

nect and retry the access at a

later time.

If a PREA D c omm and is gi v en t o

the Am79C973/Am79C975 con-

troller but no EEPROM is at-

tached to the interface pins, the

PREAD bi t will be c leared to a 0 ,

and the PVALID bit will remain re-

set with a value of 0. This applies

to the automatic read of the EE-

PROM after H_RESET as well as

to host initiated PREAD com-

mands. EE P RO M programm abl e

locations on board the

Am79C973/Am79C975 controller

will be set to their default values

by such an aborted PREAD oper-

ation. For example, if the aborted

PREAD operation immediately

followed the H_RESET opera-

tion, then the final state of the EE-

PROM programmable locations

will be equal to the H_RESET

programming for those locations.

If a PREA D c omm and is gi v en t o

the Am79C973/Am79C975 con-

troller and the auto-detection pin

(EESK/LED1/SFBD) indicates

tha t no EEP ROM is pres ent , t hen

the EEPR OM read operation will

still be attempted.

Note that at the end of the

H_RESET operation, a read of

the EEPROM will be performed

automatically. This H_RESET-

generated EEPROM read func-

tion will not proceed if the auto-

detection pin (EESK/LED1/SF-

BD) indicates that no EEPROM is

present.

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

PREAD is set to 0 during

H_RESET and is unaffected by

S_RESET or the STO P bit.

13 EEDET EEPROM Detect. This bit indi-

cates the sampled value of the

Am79C973/Am79C975 177

PRELIMINARY

EESK/LED1/SFBD pin at the end

of H_RESET. This value indi-

cates whether or not an EE-

PROM is pr esent at the EEPROM

interface. If this bit is a 1, it indi-

cates that an EEPROM is

present. If this bit is a 0, it indi-

cates that an EEPROM is not

present.

Read accessible only. EEDET is

read only; write operations have

no effect. The value of this bit is

determined at the end of the

H_RESET operation. It is unaf-

fected by S_RESET or the STOP

bit.

Table 32 indicates the possible

combinations of EEDET and the

existence of an EEPROM and the

resulti ng op erati ons that ar e pos-

sible on the EEPROM interface.

12-5 RES Reserved locations. Written as

zeros; read as undefined.

4 EEN EEPROM Port Enable. When this

bit is set to a 1, it causes th e val-

ues of ECS, ESK, and EDI to be

driven onto the EECS, EESK,

and EEDI pins, respectively. If

EEN = 0 and no EEPROM read

function is currently active, then

EECS will be driven LOW. When

EEN = 0 and no EEPROM read

function is currently active, EESK

and EEDI pins will be driven by

the LED registers BCR5 and

BCR4, respectively. See Table

32.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set.

EEN is set to 0 by H_RESET and

is unaffected by the S_RESET or

STOP bit.

3 RES Reserved location. Written as

zero and read as undefined.

2 ECS EEPROM Chip Select. This bit is

used to control the value of the

EECS pin of the interface when

the EEN bit is set to 1 and the

PREAD b it is se t to 0 . If E EN = 1

and PREAD = 0 and ECS is set to

a 1, then the EECS pin will be

forced to a HIGH level at the ris-

ing edge o f the next clock follow-

ing bit programming.

If EEN = 1 and PREAD = 0 and

ECS is set to a 0, then the EECS

pin will be forced to a LOW lev el

at the rising edge of the next

clock following bit programming.

ECS has no effect on the output

value of the EECS pin unless the

PREAD bit is set to 0 and the

EEN bit is set to 1.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set.

ECS is set to 0 by H_RESET and

is not affected by S_RESET or

STOP.

1 ESK EEPROM Serial Clock. This bit

and the EDI/EDO bit are used to

control host access to the EE-

PROM. Values programmed to

this bit are pla ced onto the EE SK

pin at t he rising edge of the next

clock following bit programming,

except when the PREAD bit is set

to 1 or the EEN bit is set to 0. If

both the ESK bit and the EDI/

EDO bit va lues are chan ged dur -

ing one BCR19 write operation,

Table 32. Interface Pin Assignment

RST Pin PREAD or Auto

Read in Progress EEN EECS EESK EEDI

Low X X 0 Tri-State Tri-State

High 1 X Active Active Active

High 0 1 From ECS

Bit of BCR19 From ESK Bit of

BCR19 From EEDI Bit of

BCR19

High 0 0 0 LED1 LED0

178 Am79C973/Am79C975

PRELIMINARY

while EEN = 1, then setup and

hold times of the EEDI pin value

with respect to the EESK signal

edge are not guaranteed.

ESK has no effect on the EESK

pin unless the PREAD bit is set to

0 and the EEN bit is set to 1.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set. ESK

is reset to 1 by H_RES ET and is

not affected by S_RESET or

STOP.

0 EDI/EDO EEPROM Data In/EEPROM

Data Out. Data that is written to

this bit will appear on the EEDI

output of the interface, except

when the PREAD bit is set to 1 or

the EEN bit is set to 0. Data that

is read from this bit reflects the

value of the EEDO input of the in-

terface.

EDI/EDO has no effect on the

EEDI pin unless the PREAD bit is

set to 0 and the E EN bit is set to

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set. EDI/

EDO is reset to 0 by H_RESET

and is not affected by S_RESET

or STOP.

BCR20: Software Style

This register is an alias of the location CSR58. Accesses

to and from thi s register are eq uivalent to accesses to

CSR58.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-11 RES Reserved locations. Written as

zeros and read as und efi ned.

10 APERREN Advanced Parity Error Handling

Enable. When APERREN is set

to 1, the BPE bits (RMD1 and

TMD1, bit 23) start having a

meaning. BPE will be set in the

descriptor associated with the

buffer tha t was a ccessed wh en a

data parity error occurred. Note

that since the advanced parity er-

ror handling uses an additional bit

in the descriptor, SWSTYLE (bits

7-0 of this register) must be set to

2 or 3 to program the Am79C973/

Am79C975 controller to use 32-

bit software structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur when

the Am79C973/Am79C975 con-

troller is the target of the transfer.

Read anytime; write accessible

only when either the STOP or the

SPND bit is set. APERREN is

cleared by H_RESET and is not

affected by S_RESET or STOP.

9 RES Reserved locations. Written as

zeros; read as undefined.

8 SS IZE32 Softwa re Size 32 bits. W hen set,

this bit indicates that the

Am79C 973 /Am 79C9 75 c on tr oll er

utilizes 32 -bit software structur es

for the i nitializati on block an d the

transmit and receive descriptor

entries. W hen c leared, t his b it in-

dicates that the Am79C973/

Am79C975 controller utilizes 16-

bit softwa re struct ures for the ini-

tialization block and the transmit

and rece ive descr iptor entries. In

this mode, the Am79C973/

Am79C975 controller is back-

wards compatible with the

Am799 0 LANCE and Am79C96 0

PCnet-I S A con tr oll ers .

The value of SSIZE32 is deter-

mined by the Am79C973/

Am79C975 controller according

to the setting of the Software

Style (SW STYLE, bits 7- 0 of this

Read accessible always.

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

Am79C973/Am79C975 179

PRELIMINARY

upper 8 bits of the 32-b it add re ss

bus durin g maste r acc esses i niti-

ated by the Am79C973/

Am79C975 controller. This action

is required, since the 16-bit soft-

ware structures specified by the

SSIZE32 = 0 setting will yield

only 24 bits of address for

Am79C973/Am79C975 controller

bus master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

to the Am79C973/Am79C975

controller and the host system

will supply a full 32 bits for each

address pointer that is needed by

the Am79C973/Am79C975 con-

troller for performing master ac-

cesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress p ins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE3 2 bit has no effe ct on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0 SWSTYLE Software Style register. The val-

ue in thi s register de termines th e

style of register and memory re-

sources that sha ll be used by the

Am79C973/Am79C975 control-

ler. The Software Style selection

will affect the interpretation of a

few bits within the CSR space,

the order of the descriptor entries

and the width of the descriptors

and initialization block entries.

All Am79C973/Am79C975 con-

troller CSR bits and all descriptor,

buffer, and i nitial ization block en-

tries no t cite d in the Ta bl e 33 are

unaffected by the So ftware Style

selection and are, therefore, al-

ways full y functional a s specified

in the CSR and BCR sections .

Read/Write accessible only when

either the STO P or the SPND bit

is set. The SWSTYLE register will

contain the value 00h following

H_RESET and wi ll be un affecte d

by S_RESET or STOP.

BCR22: PCI Latency Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-8 MAX_LAT Maximum Latency. Specifies the

maximum arbitration latency the

Am79C9 73/ Am 79C9 75 c on tr oll er

can sustain without causing prob-

lems to the network activity. The

in units of 1/4 microseconds.

MAX_LAT is aliased to the PCI

configuration space register

MAX_LAT (offset 3Fh). The host

will use the value in the register to

determine the setting of the

Am79C973/Am79C975 Latency

Timer register.

Table 33. Software Styles

SWSTYLE

[7:0] Style

Name SSIZE32 Initialization Block

Entries Descriptor Ring Entries

00h LANCE/

PCnet-ISA

controller 016-bit software

structures, non-burst or

burst access

16-bit sof tware structu res,

non-burst access only

01h RES 1RES RES

02h PCnet-PCI

controller 132-bit software

structures, non-burst or

burst access

32-bit sof tware structu res,

non-burst access only

03h PCnet-PCI

controller 132-bit software

structures, non-burst or

burst access

32-bit sof tware structu res,

non-burst or burst access

All Other Reserved Undefined Undefined Undefined

180 Am79C973/Am79C975

PRELIMINARY

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

MAX_LAT is set to the value of

FFh by H_RESET which results

in a default maximum latency of

63.75 microseconds. It is recom-

mended to program the value of

18H via EEPROM. MAX_LAT is

not affected by S_RESET or

STOP.

7-0 MIN_GNT Minimum Grant. Specifies the

minimum length of a bu rst p eriod

the Am79C973/Am79C975 con-

troller needs to keep up with the

network activity. The length of the

burst perio d is cal culat ed assu m-

ing a clock rate of 33 MHz. The

in units of 1/4 ms. MIN_GNT is

aliased to the PCI configuration

space register MIN_GNT (offset

3Eh). The host will use the valu e

in the register to determine the

setting of the Am79C973/

Am79C975 Latency Timer regis-

ter.

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

MIN_GNT is set to the value of

06h by H_RESET which results

in a default minimum grant of

1.5 ms, whi ch is the tim e it takes

to Am79C973/Am79C975 con-

troller to read/write half of the

FIFO. (16 DWord transfers in

burst mode with one extra wait

state per data phase inserted by

the target.) Note that the default

is only a typical value. It also does

not take into account any descrip-

tor accesses. It is recommended

to program the value of 18H via

EEPROM. MIN_GNT is not af-

fected by S_RESET or STOP.

BCR23: PCI Subsystem Ve ndor ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 SVID Subsystem Vendor ID. SVID is

used together with SID (BCR24,

bits 15-0) to uniq uely identify the

add-in board or subsystem the

Am79C 973 /Am 79C9 75 c on tr oll er

is used in. Subsystem Vendor IDs

can be obtained form the PCI

SIG. A value of 0 ( the defaul t) in-

dicates that the Am79C973/

Am79C975 controller does not

support subsystem identification.

SVID is aliased to the PCI config-

uration space register Subsystem

Vendor ID (offset 2Ch).

Read acces sib le always . SVID is

read only. Write operations are

ignored. SVID is cleared to 0 by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

BCR24: PCI Subsystem ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 SID Subsystem ID. SID is used to-

gether with SVID (BCR23, bits

15-0) to uniquely identify the add-

in board or subsystem the

Am79C 973 /Am 79C9 75 c on tr oll er

is used in. The value of SID is up

to the system vendor. A value of

0 (the default) indicates that the

Am79C 973 /Am 79C9 75 c on tr oll er

does not support subsystem

identification. SID is aliased to the

PCI configuration space register

Subsystem ID (offset 2Eh).

Read accessible always. SID is

read only. Write operations are

ignored. SID is cleared to 0 by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

BCR25: SRAM Size Register

Bit Name Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

Am79C973/Am79C975 181

PRELIMINARY

31-8 RES Reserved locations. Written as

zeros and read as und efi ned.

7-0 SRAM_SIZE SRAM Size. Specifies the upper

8 bi ts of the 16-bit tota l size of the

SRAM buffer. Each bit in

SRAM_SIZ E accounts for a 51 2-

byte page. The starting address

for the low er 8 bi ts i s ass um ed to

be 00h and the ending address

for the lower is assumed to be

FFh. Therefore, the maximum ad-

dress range is the starting ad-

dress of 0000h to ending address

of ((SRAM_SIZE +1) * 256

words) or 17FFh. An

SRAM_SIZE value of all zeros

specifies that no SRAM will be

used and the internal FIFOs will

be joined into a contig uous FIFO

similar to the PCnet-PCI II con-

troller.

Note: The minimum allowed

number of pa ges is eight for nor-

mal network operation. The

Am79C973/Am79C975 controller

will not operate correctly with less

than the eig ht pages of memory.

When the minimum number of

pages is us ed, the se pages m ust

be allocated four each for trans-

mit and receive.

CAUTION: Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM_SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_SIZE is set to

000000b during H_RESET and is

unaffected by S_RESET or

STOP.

BCR26: SRAM Boundary Register

Bit Name Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

31-8 RES Reserved locations. Written as

zeros and read as und efi ned.

7-0 SRAM_BND SRAM Boundary. Specifies the

upper 8 bits of the 16-bit addre ss

boundary where the receive buffer

begins in the SRAM. The transmit

buffer in the SRAM begins at ad-

dress 0 and ends at the address

located just before the address

specified by SRAM_BND. There-

fore , th e re ceiv e bu ff er al ways b e-

gins on a 512 byte boundary. The

lower bits are assumed to be ze-

ros. SRAM_BND has no effect in

the Low Latency Receive mode.

Note: The minimum allowed

number of pages is four. The

Am79C973/Am79C975 controller

will not operate correctly with less

than four pages of memory per

queue. See Table 34 for

SRAM_BND programming de-

tails.

CAUTION: Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_BND is set to

00000000b during H_RESET

and is unaffected by S_RESET or

STOP.

BCR27: SRAM Interface Control Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PTR TST Reserved. Reserved for manu-

facturing tests. Written as zero

and read as undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

Read/Write accessible always.

PTR_TST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

Table 34. SRAM_BND Programming

SRAM Addresses SRAM_BND [7:0]

Minimum SRAM_BND

Address 04h

Maximum SRAM_BND Address 13h

182 Am79C973/Am79C975

PRELIMINARY

14 LOLATRX Low Latency Receive. When the

LOLATRX bit is set to 1, the

Am79C9 73/ Am 79C9 75 c on tr oll er

will switch to an architecture ap-

plicable to cut-through switches.

The Am79C973/Am79C975 con-

troller will assert a receive frame

DMA after only 16 bytes of the

current receive frame has been

receiv ed reg ardless of wher e the

RCVFW (CSR 80, bits 13-12) ar e

set. The watermark is a fixed val-

ue and cannot be changed. The

receive FIFOs will be in

NO_SRAM mode while all trans-

mit traffic is buffered through the

SRAM. This bit is only valid and

the low latency receive only en-

abled when the SRAM_SIZE

(BC R25, bit s 7-0) bits ar e non -ze-

ro. SRAM_BND (BCR26, bits 7-

0) has no meaning when the

Am79C9 73/ Am 79C9 75 c on tr oll er

is in the Low Latenc y mode. See

the section on SRAM Configura-

tion for more details.

When the LOLATRX bit is set to

0, the Am79C973/Am79C975

controller will return to a normal

receive configuration. The runt

packet accept bit (RPA, CSR124,

bit 3) must be set when LOLA-

TRX is set.

CAUTION: To provide data in-

tegrity when switching into

and out of the low latency

mode, DO NOT SET the

FASTSPNDE (CSR7, bit 15) bit

when setting the SPND bit. Re-

ceive frames WILL be overwrit-

ten and the Am79C973/

Am79C975 controlle r may g ive

erratic behavior when it is en-

able again. The minimum al-

lowed number of pa ges is four.

The Am79C973/Am79C975

controller will not operate cor-

rectly in the LOLATRX mode

with less than four pages of

memory.

Read/Write accessible only when

the ST OP bi t is s et. L OLATRX is

cleared to 0 after H_RESET or

S_RESET and is unaffected by

STOP.

13-6 RES Reserved locations. Written as

zeros and read as undefined.

5-3 EBCS Expansion Bus Clock Source.

These bits are u sed to sel ect the

source of the fundamental clock

to drive the SRAM and Expansion

ROM access cycles. Table 35

shows the selected clock source

for the various values of EBCS.

Note that the actual frequency

that the Expansion Bus access

cycles run at is a function of bot h

the EBCS and CLK_FAC

(BCR27, bits 2-0) bit field set-

tings. When EBCS is set to either

the PCI clock or the Time Base

clock , no ex ter na l cl oc k so ur ce is

requir ed as the cloc ks a re route d

internally and the EBCLK pin

should b e pulled to VDD t hrough

a resistor.

Read accessible always; write

accessible only when the STOP

bit is set. EBCS is set to 000b

(PCI clock selected) during

H_RESET and is unaffected by

S_RESET or the STO P bit.

Note: The clock frequency driv-

ing the Expansion Bus access cy-

cles that results from the s etti ngs

of the EBCS and CLK FAC bits

must not exceed 33 MHz at any

time. Whe n E BCS is se t to eit her

the PCI clock or the Time Base

clock, no external clock source is

required because the clocks are

routed internally and the EBCLK

pin should be pulled to VDD

through a resistor.

CAUTION: Care should be ex-

ercised w hen choosing the PCI

clock pin because of the nature

of the PCI clock signal. The PCI

specification states that the

PCI clock can be stopped. If

Table 35. EBCS Values

EBCS Expansion Bus Clock Source

000 CLK pin (PCI Clock)

001 Time Bas e Cloc k

010 EBCLK pin

011 Reserved

1XX Reserved

Am79C973/Am79C975 183

PRELIMINARY

that can occu r wh ile it is being

used for the Expansion Bus

clock data, corruption will re-

sult.

CAUTION: The Time Base

Clock will not support 100 Mbit

operation and should only be

selected in 10 Mbit only config-

urations.

CAUTION: The external clock

source used to drive the

EBCLK pin must be a continu-

ou s clock source at all times.

2-0 CLK_FAC Clock Factor. These bits are used

to select whether the clock select-

ed by EBCS is used directly or if it

is divided down to give a slower

clock for running the Expansion

Bus access cycles. The possible

factors are given in Table 36.

Read accessible always; write

accessible only when the STOP

bit is set. CLK_FAC is set to 000b

during H_RESET and is unaffect-

ed by S_RESET or STOP.

BCR28: Expansion Bus Port Address Lower (Used

for Flash/EPROM and SRAM Accesses)

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 EPADDRL Expansion Port Address Lower.

This address is used to provide

addresses for the Flash and

SRAM port accesses.

SRAM accesses are started

whe n a read or w rite is pe rform ed

on BCR30 a nd the FL ASH (BCR

29, bit 15) is set to 0. During

SRAM accesses only bits in the

EPADDRL are valid. Since all

SRAM acce ss es are wor d or ie nt-

ed only, EPADDRL[0] is the least

significant word address bit. On

any byte write accesses to the

SRAM, the user will have to fol-

low the read-modify-write

scheme. On any byte read ac-

cesses to the SRAM, the user will

have to chose which byte is

needed from the complete word

returned in BCR30.

Flash acc esses ar e sta rt ed whe n

a read or write is performed on

BCR30 and the FLASH (BCR 29,

bit 15) is set to 1. During Flash

accesses a ll bits in EPADDR are

valid.

Read accessible always; write

accessible only when the STOP

is set or when SRAM SIZE

(BC R25, b its 7- 0) is 0. EPA DDRL

is undefi ned after H_R ESET and

is unaffected by S_RESET or

STOP.

BCR29: Expansion Port Address Upper (Used for

Flash/EPROM Accesses)

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 FLASH Flash Access. When the FLASH

bit is set to 1, th e Exp ansion B us

access will be a Flash cycle.

When FLASH i s set to 0, the Ex-

pansion Bus access will be a

SRAM cycle. For a complete de-

scription, see the section on Ex-

pansion Bus Accesses. This bit is

only app lica ble to reads or w rites

to EBDATA (BCR30). It does not

affect Expansion ROM accesses

from the PCI syst em bus .

Read accessible always; write

accessible only when the STOP

bit is set. FLASH is 0 after

H_RESET and is unaffected by

S_RESET or the STO P bit.

14 LAAINC Lower Address Auto Increment.

When the LAAINC bit i s set to 1 ,

the Expansion Port Lower Ad-

dress will automatically increment

by one after a read or write ac-

cess to EBDATA (BCR30). When

Table 36. CLK_FAC Values

CLK_FAC Clock Factor

000 1

001 1/2 (divide by 2)

010 Reserved

011 1/4 (divide by 4)

1XX Reserved

184 Am79C973/Am79C975

PRELIMINARY

EBADDRL reaches FFFFh and

LAAINC is set to 1, the Expansion

Port Lower Address (EPADDRL)

will roll over to 0000h. When the

LAAINC bit is set to 0, the Expan-

sion Port Lower Address will not

be affected in any way after an

access to EBDATA (BCR30) and

must be programmed.

Read accessible always; write

accessible only when the STOP

bit is set. LAINC is 0 after

H_RESET and is unaffected by

S_RESET or the STOP bit.

13-4 RES Reserved locations. Written as

zeros and read as und efi ned.

3-0 EPADDRU Expansion Port Address Upper.

This upper portion of the Expan-

sion Bus address is used to pro-

vide addresses for Flash/EPROM

port accesses.

Read accessible always; write

accessible only when the STOP

bit is set or when SRAM SIZE

(BCR25, bits 7-0) is 0. EPADD-

RU is undefined after H_RESET

and is unaffected by S_RESET or

the STOP bit.

BCR30: Expansion Bus Data Port Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-0 EBDA TA Expan sio n Bus D ata Po rt. EB DA-

TA is the data port for op erations

on the Expansion Port accesses

involving SRAM and Flash ac-

cesses. The type of access is set

by the FLASH bit (BCR 29, bit

15). When the FLASH bit is set to

1, the Exp ansion Bus access wi ll

follow the Flash access timing.

When the FLASH bit is set to 0,

the Expansion Bus access will

follow the SRAM access timing.

Note: It is important to set the

FLASH bit and load Expansion

Port Address EPADDR (BCR28,

BCR29) with the required ad-

dress before attempting read or

write to the Expansion Bus data

port. The Flash and SRAM ac-

cesses use different address

phases. Incorrect configuration

will result in a possible corruption

of data.

Flash read cycles are performed

when BCR30 is read and the

FLASH bit (BCR2 9, bit 15) is set

to 1. Upon completion of the read

cycle, the 8-bit result for Flash ac-

cess is stored in EBDATA[7:0],

EBDATA[15:8] is undefined.

Flash wri te cycles are p erformed

when BCR30 is written and the

FLASH bit (BCR2 9, bit 15) is set

to 1. EBDATA[7:0] only is valid

for write cycles.

SRAM read cycles are performed

when BCR30 is read and the

FLASH bit (BCR2 9, bit 15) is set

to 0. Upon completion of the read

cycle, the 16-bit result for SRAM

access is stored in EBDATA.

Write cycles to the SRAM are in-

voked when BCR30 is written

and the FLASH bit (BCR29, bit

15) is s et to 0. Byte w rites to the

SRAM must use a read-modify-

write scheme since the word is al-

ways valid for SRAM write or

read access es .

Read and write accessible only

when the STOP is set or when

SRAM SIZ E (BCR25, bit s 7-0) is

0. EBDATA is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR31: Software Timer Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 STVAL Software Timer Value. STVAL

controls the maximum time for

the Software Timer to count be-

fore generating the STINT

(CSR7, bit 11) interrupt. The Soft-

ware Timer is a free-running timer

that is star ted upon the first write

to STVAL. After the first write, the

Software Timer will continually

count and set the STINT interrupt

at the STVAL period.

Am79C973/Am79C975 185

PRELIMINARY

The STVAL value is interpreted

as an unsigned number with a

resolution of 256 Time Base

Clock periods. For instance, a

value of 122 ms would be pro-

grammed with a value of 9531

(253Bh) if the Time Base Clock is

running at 20 MHz. A value of 0 is

undefined and will result in erratic

behavior.

Read and write accessible al-

ways. STVAL is set to FFFFh af-

ter H_RESET and is unaffected

by S_RESET and the STOP bit.

BCR32: PHY Control and Status Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 ANTST Reserved for manufacturing

tests. Written as 0 and read as

undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

Read/Write accessible always.

ANTST is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit .

14 MIIPD MII PHY Detect. MIIPD reflects

the quiescent state of the MDIO

pin. MIIPD is continuous ly updat-

ed whenever there is no manage-

ment operation in progress on the

MII interface. When a manage-

ment operation begins on the in-

terface, the state of MIIPD is

preserved until the operation

ends, when the quiescent state is

again monitored and con tinuous-

ly updates the MIIPD bit. When

the MDIO pin is at a quiescent

LOW state, MIIPD is cleared to 0.

When the MDIO pin is at a quies-

cent HIGH state, MIIPD is set to

1. MIIPD is used by the automatic

port selection logic to select the

MII port. When the MIIPD bit is

set to 1, the MII port is selected.

Any transition on the MIIPD bit

will set the MIIPDTI bit in CSR7,

bit 3.

Read accessible always. MIIPD

is read only. Write operations are

ignored and should not be per-

formed.

13-12 F MDC Fas t Managemen t Data Clock (is

used for manufacturing tests).

When FMDC is set to 2h the MII

Management Data Clock will run

at 10 MHz max. The Manage-

ment Data Clock will no longer be

IEEE 802.3u-compliant and set-

ting this bit should be used with

care. The accompanying external

PHY must also be able to accept

management frames at the new

clock rate. When FMDC is set to

1h, the MII Management Data

Clock wi ll ru n at 5 MHz ma x. Th e

Management Data Clock will no

longe r be IEEE 802.3u - compl ian t

and setting this bit should be

used with care. The accom pany-

ing external PHY must also be

able to accept management

frames at the new clock rate.

When F MDC is s et to 0h , the M II

Management Data Clock will run

at 2.5 MHz max and will be fully

compliant to IEEE 802.3u stan-

dards. See Table 37.

Read/Write accessible always.

FMDC is set to 0 during

H_RESET, and is unaffected by

S_RESET and the STOP bit

11 APEP Auto-Poll PHY. APEP when set to

1 the Am79C973/Am79C975

controller will poll the status regis-

ter in the PHY. This feature al-

lows the software d river or up per

layers to see any changes in the

status of the PHY. An interrupt

when enabled is generated when

the contents of the new status is

different from the previous status.

Table 37. FMDC Values

FMDC Fast Management Data Clock

00 2.5 MHz max

01 5 MHz max

10 10 MHz max

11 Reserved

186 Am79C973/Am79C975

PRELIMINARY

Read/Write accessible always.

APEP is set to 0 during

H_RESET and is unaffected by

S_RESET and the STOP bit.

10-8 APDW Auto- Poll Dwel l Time. APDW de-

termines the dwell time between

PHY Management Frame

accesses when Auto-Poll is

turned on. See Table 38.

Read/Write accessible always.

APDW is set to 100h after

H_RESET and is unaffected by

S_RESET and the STO P bit.

7 DANAS Disable Auto-Negotiation Auto

Setup. When DANAS is set, the

Am79C9 73/ Am 79C9 75 c on tr oll er

after a H_RESET or S_RESET

will remain dormant and not auto-

matically startup the Auto-Negoti-

ation section or the enhanced

automatic port selection section.

Instead, the Am79C973/

Am79C975 c ontroll er will wait for

the software driver to setup the

Auto-Negotiation portions of the

device. The PHY Address and

Data programming in BCR33 and

BCR34 is still valid. The

Am79C9 73/ Am 79C9 75 c on tr oll er

will not generate any manage-

ment frames unless Auto-Poll is

enabled.

Read/write accessible always.

DANAS is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit .

6 XPHYRST PHY Reset. When XPHYRST is

set, the Am79C973/Am79C975

controller after an H_RESET or

S_RESET will issue manage-

ment frames that will reset the

PHY. This bit is needed when

there is no way to guarantee the

state of the external PHY. This bit

must be reprogrammed after ev-

ery H_RESET.

Read/Write accessible always.

XPHYRST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYRST is on ly v alid when th e

internal Network Po rt Mana ger is

scanning for a network port.

5 XPHYANE PHY Auto-Negotiation Enable.

This bit will force the PHY into en-

abling Auto-Negotiation. When

set to 0 the Am79C973/

Am79C975 controller will send a

management frame disabling

Auto-Negotiation.

Read/Write accessible always.

XPHYANE is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYANE i s onl y v ali d when th e

internal Network Po rt Mana ger is

scanning for a network port.

4 XPHYFD PHY Full Duplex. When set, this

bit will forc e the PHY int o full du-

plex when Auto-Negotiation is not

enabled.

Read/Write accessible always.

XPHYFD is set to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

3 XPHYSP PHY Speed. When set, this bit

will for ce the PHY into 10 0 Mbps

mode when Auto-Negotiation is

not enabled.

Read/Write accessible always.

XPHYSP is set to 0 by

H_RESET, and is unaffected by

S_RESET and the STOP bit.

2 RES Reserved location. Written as ze-

ros and read as undefined.

1 MIIILP Media Independent Interface In-

ternal Loopback. When set, this

bit will cause the internal portion

of the MII data port to loopback

on itself. The interface is mapped

in the following way. The

Table 38. APDW Values

APDW Auto-Poll Dwell Time

000 Continuous (26µs @ 2.5 MHz)

001 Every 128 MDC cycles (103µs @ 2.5 MHz)

010 Every 256 MDC cycles (206µs @ 2.5 MHz)

011 Every 512 MDC cycles (410 µs @ 2.5 MHz)

100 Every 1024 MDC cycles (819 µs @ 2.5 MHz)

101 Every 2048 MDC cycles (1640 µs @ 2.5 MHz)

110-111 Reserved

Am79C973/Am79C975 187

PRELIMINARY

TXD[3:0] nibble data path is

looped back onto the RXD[3:0]

nibble data path. TX_CLK is

looped b ack as RX _CLK . TX_E N

is looped back as RX_DV. CRS is

correctly OR’d with TX_EN and

RX_DV and always encompass-

es the transmit frame. TX_ER is

looped back as RX_ER. Howev-

er, TX_ER will not get asserted

by the Am79C973/Am79C975

controller to signal an error. The

TX_ER function is reserved for

future use.

Read/Write accessible always.

MIIILP is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit .

0 RES Reserved location. Written as ze-

ros and read as undefi ned.

BCR33: PHY Address Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15 RES Reserved locations. Written as

zeros and read as und efi ned.

9-5 PHYAD Management Frame PHY Ad-

dress. PHYAD contains the 5-bit

PHY Addr ess fiel d that is used i n

the managem ent frame that gets

clocked out via the MII manage-

ment port pins (MDC and MDIO)

whenever a read or write transac-

tion occurs to BCR34. The PHY

address 1Fh is not valid. The

PHY addr ess of th e inte rnal PHY

unit is 1Eh (30 dec.)

The Network Port Manager cop-

ies the PHYAD after the

Am79C973/Am79C975 controller

reads the EEPROM and uses it to

communicate with the external

PHY. The PHY address must be

programmed into the EEPROM

prior to starting the Am79C973/

Am79C975 controller.

Read/Write accessible always.

PHYAD is undefined after

H_RESET and is unaffected by

S_RESET and the STOP bit.

4-0 REGAD Management Frame Register Ad-

dress. REGAD contains the 5-bit

used in the management frame

that gets cloc ked out via t he inter -

nal MII management interface

whenever a read or write transac-

tion occurs to BCR34.

Read/Write accessible always.

REGAD is undefined after

H_RESET and is unaffected by

S_RESET and the STOP bit.

BCR34: PHY Management Data Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MIIMD MII Management Data. MIIMD is

the data port for operations on the

MII management interface (MDIO

and MDC). The Am79C973/

Am79C975 device builds man-

agement frames using the PHY-

AD and REGAD values from

BCR33. The operation code used

in each frame is based upon

whether a read or write operation

has been performed to BCR34.

Read cycles on the MII manage-

ment interface are invoked when

BCR34 is r ead. Upon com pletion

of the read cycle, the 16-bit result

of the read operation is stored in

MIIMD. Write cycles on the MII

management interface are in-

voked when BCR34 is written.

The value writte n to MIIM D is th e

value used in the data field of the

management write frame.

Read/Write accessible always.

MIIMD is undefined after

H_RESET and is unaffected by

S_RESET and the STOP bit.

BCR35: PCI Vendor ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 VID Vendor ID. The PCI Vendor ID

188 Am79C973/Am79C975

PRELIMINARY

identifi es the manufac turer of the

Am79C973/Am79C975 control-

ler. AMD’s Vendor ID is 1022h.

Note that this Vendor ID is not the

same as the Manufacturer ID in

CSR88 and CSR89. The Vendor

ID is assigned by the PCI Special

Interest Group.

The Vendor ID is not normally

programmable, but the

Am79C973/Am79C975 controller

allows this due to legacy operat-

ing systems that do not look at

the PCI Subsystem Vendor ID

and the Vendor ID to uniquely

identify the add-in board or sub-

system that the Am79C973/

Am79C975 controller is used in.

Note: If the operating system

or the network operating sys-

tem supports PCI Subsystem

Vendor ID and Subsystem ID,

use those to identi fy the add-i n

board or subsystem and pro-

gram the VID with the default

value of 1022h.

VID is aliased to the PCI configu-

ration space register Vendor ID

(offset 00h).

Read accessible always. VID is

read only. Write operations are

ignored. VID is set to 1022h by

H_RESET an d is not affected by

S_RESET or by setting the STOP

bit.

BCR36: PCI Power Management Capabilities (PMC)

Alias Register

Note: This register is an alias of the PMC register

located at offset 42h of the PCI Configuration Space.

Since PMC register is read only, BCR36 provides a

means of programming it through the EEPROM. The

contents of this register are copied into the PMC regis-

ter. For the def ini tio n o f the bi ts in thi s regis te r, refer to

the PMC register definition. Bits 15-0 in this register are

programmable through the EEPROM. Read accessible

alwa ys. Read only. Cleared by H_RESET and is not af-

fected by S_RESET or setting the STOP bit.

BCR37: PCI DATA Register Zero (DATA0) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE fiel d of the PMCSR reg ister.

Since these two are read only, BCR37 provides a

means of programming them indirectly . The contents of

this register are copied into the corresponding fields

pointed with the DATA_SEL fie ld set to zero. Bits 15-0

in this register are programmable through the EE-

PROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D0_SCALE These bits correspond to the

DATA_SCALE field of the

PMCSR (offset Register 44 of the

PCI configuration space, bits 14-

13). Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D0_SCALE is r ead only. Cl eare d

by H_RESET and is not affecte d

by S_RESET or setting the STOP

bit.

7-0 DAT A0 These bit s cor res pon d to th e P C I

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

Read accessible always. DATA0

is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP bit

BCR38: PCI DATA Register One (DATA1) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE fiel d of the PMCSR reg ister.

Since these two are read only, BCR38 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

spondin g fi eld s p oi nted wit h the DATA_SEL field s et t o

one. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D1_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (off set Reg ister 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

Am79C973/Am79C975 189

PRELIMINARY

Read accessible always.

D1_SCALE is r ead only. Cl eare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DATA1 These bits cor r espon d to the P CI

DAT A re gi st e r (o f fs e t Re gi st e r 47

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

Read accessible always. DATA1

is read only. Cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR39: PCI DATA Register Two (DATA2) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE fiel d of the PMCSR reg ister.

Since these two are read only, BCR39 provides a

means of programming them through the EEPROM.

The co ntents of th is reg ister are c opied i nto th e cor re-

sponding fi eld s p oin ted with the DATA_SEL field s et t o

two. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D2_SCALE These bits correspond to the

DATA_SCALE field of the

PMCSR (offset Register 44 of the

PCI configuration space, bits 14-

13). Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D2_SCALE is r ead only. Cl eare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DAT A2 These bits c or res pon d to the P CI

DAT A re gi st e r (o f fs e t Re gi st e r 47

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

Read accessible always. DATA2

is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP bit

BCR40: PCI DATA Register Three (DATA3) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR40 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

spondin g fi eld s p oi nted wit h the DATA_SEL field s et t o

three. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D3_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (off set Reg ister 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D3_SCALE is r ead only. Cl eare d

by H_RESET and is not affecte d

by S_RESET or setting the STOP

bit.

7-0 DAT A3 These bit s cor res pon d to th e P C I

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

Read accessible always. DATA3

is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR41: PCI DATA Register Four (D ATA4) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR41 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

spondin g fi eld s p oi nted wit h the DATA_SEL field s et t o

four. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

190 Am79C973/Am79C975

PRELIMINARY

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D4_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D4_SCALE is r ead only. Cl eare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit

7-0 DAT A4 These bits c or res pon d to the P CI

DAT A re gi st e r (o f fs e t Re gi st e r 47

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

Read accessible always. DATA4

is read only. Cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR42: PCI DATA Register Five (DATA5) Alias

Note: This register is an alias of the DATA register and

also of t he DATA_SCALE field of the PCMCR reg ister.

Since these two are read only, BCR42 provides a

means of programming them through the EEPROM.

The co ntents of th is reg ister are c opied i nto th e cor re-

sponding fi eld s p oin ted with the DATA_SEL field s et t o

five. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D5_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offse t Regis ter 44 of t he PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D5_SCALE is r ead only. Cl eare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit

7-0 DAT A5 These bit s cor res pon d to th e P C I

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

Read accessible always. DATA5

is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR43: PCI DATA Register Six (DATA6) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR43 provides a

means of programming them through the EEPROM.

The conte nts o f this reg ister are cop ied into the c orre-

spondin g fi eld s p oi nted wit h the DATA_SEL field s et t o

six. Bits 15-0 in this register are programmable through

the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D6_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (off set Reg ister 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D6_SCALE is r ead only. Cl eare d

by H_RESET and is not affecte d

by S_RESET or setting the STOP

bit

7-0 DAT A6 These bit s cor res pon d to th e P C I

DAT A re gi st er (o f fset R egiste r 47

of the PCI configuration space,

bits 7-0) . Refer to the d escriptio n

of DATA regi s ter for t he mea nin g

of this field.

Read accessible always. DATA6

is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

Am79C973/Am79C975 191

PRELIMINARY

BCR44: PCI DATA Register Seven (D ATA7) Alias

Note: This register is an alias of the DATA register and

also of t he DATA_SCALE field of the PCMCR reg ister.

Since these two are read only, BCR44 provides a

means of programming them through the EEPROM.

The co ntents of th is reg ister are c opied i nto th e cor re-

sponding fi eld s p oin ted with the DATA_SEL field s et t o

seven. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as und efi ned.

9-8 D7_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offse t Regis ter 44 of t he PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

Read accessible always.

D7_SCALE is r ead only. Cl eare d

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DAT A7 These bits c or res pon d to the P CI

DATA register (offset register 47

of the PCI configuration space,

bits 7-0) . Refer to the de scriptio n

of DATA regi st er for t he m ean in g

of this field.

Read accessible always. DATA7

is read only. Cleared by

H_RESET an d is not affected by

S_RESET or setting the STOP

bit.

BCR45: OnNow Pattern Matching Register 1

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PM AT_MODE b it i s 0 ,

the P attern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress o f the PMR word to b e accessed. Following th e

write to BCR45, the PMR word ma y be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, t he write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

writ ten unti l the writ e to BCR47 is comp lete. The wr ite

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 PMR_B0 Pattern Match RAM Byte 0. This

byte is written into or read from

Byte 0 of the Pattern Match RAM

Read and write accessible al-

ways. PMR_B0 is undefined after

H_RESET, and is unaffected by

S_RESE T and the STOP bit .

7 PMAT_MODEPattern Match Mode. Writing a 1 to

this bit will enable Pattern Match

Mode and should only be done

after the Patter n Match R AM has

been programmed.

Read and write accessible al-

ways. PMAT_MODE is reset to 0

after H_RESET, and is unaffect-

ed by S_RESET and the STOP

bit.

6-0 PMR_ADDRP attern M atch Ra m Address. Th ese

bits are the Pattern Match Ram

address to be written to or read

from.

Read and write accessible al-

ways. PMR_ADDR is reset to 0

after H_RESET, and is unaffect-

ed by S_RESET and the STOP

bit.

BCR46: OnNow Pattern Matching Register 2

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

ex cept for PMAT_MODE.

When BCR4 5 is written a nd th e P MAT_MODE bit is 0,

the P attern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

192 Am79C973/Am79C975

PRELIMINARY

dress o f the PMR word to b e accessed. Following th e

write to BCR45, the PMR word ma y be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

writ ten until the write to BCR47 is complete. The writ e

to BCR47 c auses all 5 bytes ( four by tes of BCR46- 47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as und efi ned.

15-8 PMR_B2 Pattern Match RAM Byte 2. This

byte is written into or read from

Byte 2 of the Pattern Match RAM.

Read and write accessible al-

ways. PMR_B2 is undefined after

H_RESET, and is unaffected by

S_RESET and the STO P bit.

7-0 PMR_B1 Pattern Match RAM Byte 1. This

byte is written into or read from

Byte 1 of Pattern Match RAM.

Read and write accessible al-

ways. PMR_B1 is undefined after

H_RESET, and is unaffected by

S_RESET and the STO P bit.

BCR47: OnNow Pattern Matching Register 3

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PM AT_MODE b it i s 0 ,

the P attern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress o f the PMR word to b e accessed. Following th e

write to BCR45, the PMR word ma y be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

writ ten until the write to BCR47 is complete. The writ e

to BCR47 c auses all 5 bytes ( four by tes of BCR46- 47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

When PMAT _M OD E i s 0, the cont ents of the word ad-

dressed by bits 6 :0 of BCR45 can be read by rea ding

BCR45-47 in any order.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 PMR_B4 Pattern Match RAM Byte 4. This

byte is written into or read from

Byte 4 of Pattern Match RAM.

Read and write accessible al-

ways. PMR_B4 is undefined after

H_RESET, and is unaffected by

S_RESE T and the STOP bit .

7-0 PMR_B3 Pattern Match RAM Byte 3. This

byte is written into or read from

Byte 3 of Pattern Match RAM.

Read and write accessible al-

ways. PMR_B3 is undefined after

H_RESET, and is unaffected by

S_RESE T and the STOP bit .

BCR48-BCR55: Reserved Locations for Am79C975

These registers must be 00h for the Am79C973 con-

troller.

PHY Management Registers (ANRs)

The Am79C973/Am79C975 device supports the MII

basic reg ister s et and extended regi ster set. Bo th sets

of registers are accessible through the PHY Manage-

ment Interface. As specified in the IEEE sta ndard, the

basic register set consists of the Control Register (Reg-

ister 0) and the Status Register (Register 1). The ex-

tended register set consists of Registers 2 to 31

(decimal).

Table 39 lists all the registers implemented in the de-

vice. All the reserved registers should not be written to ,

and reading them will return a zero value.

Am79C973/Am79C975 193

PRELIMINARY

Table 39. Am79C973/Am79C975 Internal PHY

Management Register Set

Address

(in Decimal) Register Name Basic/

Extended

0 PHY Control B

1PHY StatusB

2-3 PHY Identifier E

4Auto-Negotiation

Advertisement E

5Auto-Negotiation Link

Par tner Ability E

6Auto-Negotiation

Expansion E

7Auto-Negotiation Next

Page E

8-15 Reserved E

16 Interrupt Enable and

Status E

17 PHY Contro l/St atus E

18 Descrambler Resynch.

Timer E

19 PHY Management

Extension E

20-23 Reserved E

24 Summary Status E

25-31 Reserved E

194 Am79C973/Am79C975

PRELIMINARY

Table 40. ANR0: PHY Control Register (Register 0)

Notes:

1. R/W = Read/Write, SC = Self Clearing, RO = Read only.

2. Soft Reset does not reset the PDX block. Refer to the Soft Reset Section for details.

3. Bits 8 and 13 have no effect if Auto-Negotiation is enabled (Bit 12 = 1).

Reg Bits Name Description Read/Write

(Note 1) Default

Value Soft

Reset

0 15 Soft Reset (Note 2)

When write: 1 = PHY software reset,

0 = normal operation.

When read: 1 = reset in process,

0 = reset done.

R/W, SC 0 0

014 Loopback 1 =asserts the internal LPBCK,

0 = deasserts the internal LPBCK R/W 0 0

013Speed Selection

(Not e 3) 1 = 100 Mbps,

0 = 10 Mbps R/W 1 1

012Auto-Negotiation

Enable 1 = enable Auto-Negotiation,

0 = disable Auto-Negotiation R/W 1 1

0 11 Power Down 1 = power down, 0 = normal operation R/W 0 0

010 Isolate 1 = electrically isolate PHY

0 = normal operation R/W 1 1

09 Restart Auto-

Negotiation 1 = restart Auto-Negotiation,

0 = normal operation R/W, SC 0 0

08 Duplex Mode

(Not e 3) 1 = full duplex,

0 = half duplex R/W 1 Retains

value

0 7 Collision Test 1 = enable COL signal test,

0 = disable COL signal test R/W 0 0

0 6-0 Reserved Write as 0, ignore on read RO 0 0

Am79C973/Am79C975 195

PRELIMINARY

ANR1: Status Register (Register 1)

The Status Register identifies the physical and Auto-

negotiation capabilities of the local PHY. This register is

read only; a write will have no effect.

Table 41. ANR1: PHY Status Register (Register 1)

Note:

1. LH = Latching High, LL = Latching Low.

2. The lin k stat us bit 2 is fed from re gister 24 bit 3. R egister 2 4 bit 3 tra cks the real time st ate of the PHY, but l ink st atus in ANR1

is latched. After a change of the state of the link, ANR1 must be read twice. The first read will provide old information but it

causes the link status bit to be updated from register 24 bit 3. The second read will then provide the correct state of the link.

Reg Bits Name Description Read/Write

(Note 1) Default

Value

1 15 100BASE-T4 1 = 100 BASE-T4 abl e,

0 = not 100BASE-T4 able RO 0

1 14 100BASE-X Full Duplex 1 = 100BASE -X full duple x abl e,

0 = not 100BASE-X full duplex able RO 1

1 13 100BASE-X Half Duplex 1 = 100BASE-X half duple x ab le,

0 = not 100BASE-X half duplex able RO 1

1 12 10 Mbps Full Duplex 1 = 10 Mbps full duplex able,

0 = not 10 Mb ps full duplex able RO 1

1 11 10 Mbps Half Duplex 1 = 10 Mbps full duplex able,

0 = not 10 Mb ps full duplex able RO 1

1 10-7 Reserved Ignore when read RO 0

1 6 MF Preamble Suppression

1 = PHY can accept management

(mgmt) frames with or without preamb le,

0 = PHY can only accept mgmt frames

with preamble

RO 1

1 5 Auto-Negotiation Complete 1 = Auto-Negotiation completed,

0 = Auto-Negotiation not completed RO 0

1 (Note

1) 4 Remote Fault 1 = remote fault detected,

0 = no remote fault detected RO, LH 0

1 3 Auto-Negotiation Ability 1 = PHY able to auto-negotiate,

0 = PHY not able to auto-negotiate RO 1

1 (Note

1) 2Link Status 1 = link is up,

0 = link is down RO, LL 0

1 1 Jabber Detect 1 = jabber condition detected,

0 = no jabber condition detected RO 0

1 0 Extended Capability 1 = ex tended regi ster capabiliti es,

0 = basic regist er set capabilities only RO 1

196 Am79C973/Am79C975

PRELIMINARY

ANR2 and ANR3: PHY Identifier (Registers 2 and 3)

Registers 2 and 3 contain a unique PHY identifier , con-

sisting of 22 bits of the organizationally unique IEEE

Identifier, a 6-bit manufacturer’s model number, and a

4-bit manufacturer’s revision numbe r. The mo st sig nifi-

cant bit of the P HY identifi er is bit 15 of re gister 2; the

least sig nificant bit of the PHY identifie r is bit 0 of reg-

ister 3. Register 2, bit 15 corresponds to bit 3 of the

IEEE Identifier a nd register 2, bit 0 corresponds t o bit

18 of the IEEE Identifier . Register 3, bit 15 corresponds

to bit 19 of the IEEE Identifier and register 3, bit 10 cor-

responds to bit 24 of the IEEE Identifier. Register 3, bits

9-4 contai n the manufacturer’s model number and bits

3-0 contain the manufacturer’s revision number. These

registers are shown in Table 42 and Table 43.

Table 42. ANR2: PHY Identifier (Register 2)

Table 43. ANR3: PHY Identifier (Register 3)

Reg Bits Name Description Read/

Write Default Value Soft Reset

2 15-0 PHY_ID[31-16] IEEE Address (bits 3-18);

Identifier RO 0000000000000000

(0000 Hex) Retain s original

Value

Reg Bits Name Description Read/Write Default Value Soft Reset

3 15-10 PHY_ID[15-10] IEEE Address (bits

19-24) RO 011010

(1A Hex) Retains original

value

3 9-4 PHY_ID[9-4] Manufacturer’s

Model Numb er (bits

5-0) RO 110110

(36 He x ) Retains original

value

3 3-0 PHY_ID[3-0]

Revision Number

(bits 3-0); Register 3,

bit 0 is LS bit of PHY

Identifier

RO 0000 Retains original

value

Am79C973/Am79C975 197

PRELIMINARY

ANR4: Auto-Negotiation Advertisem ent Register

(Register 4)

This register contains the advertised ability of the

Am79C973/Am79C975 device. The purpose of this

regist er is to advertis e the te ch nol ogy ability to the li nk

partner device. See Table 44.

When this register is modified, Restart Auto-

Negotiation (Register 0, bit 9) must be enabled to guar-

antee the change is implemented.

Table 44. ANR4: Auto-Negotiation Advertisement Register (Register 4)

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 N ext Page When set, the device wis hes t o enga ge in ne xt pa ge e x chan ge. If

clear, the de vice do es not wi sh to enga ge in n ex t page e xch ange. R/W 0

14 Reserved RO 0

13 Remote Fault

When set, a remote fault bit is inserted into the base link code

word during the Auto Negotiation process. When cleared, the

base link code work will have the bit position for remote fault as

cleared.

R/W 0

12:11 Reserved RO 0

10 PA USE Th is bit should be set if the PA U SE capability is to be adv ertised. R/W 0

9 Reserved RO 0

8Full Duplex -

100BASE-TX This bit advertises Full Duplex capability. When set, Full Duplex

capability is advertised. When cleared, Full Duplex capability is

not advertised. R/W 1

7Half duplex -

100BASE-TX Th is bit advertises Half Dupl e x cap abili ty f or the Auto-negotiatio n

process. Setting this bit advertises Half Duplex capability . Clearing

this bit does not advertise Half Duplex capability. R/W 1

6Full Duplex -

10BASE-T This bit advertises Full Duplex capability. When set, Full Duplex

capability is advertised. When cleared, Full Duplex capability is

not advertised. R/W 1

5Half duplex -

10BASE-T This bit advertises Half Dupl e x capabi lity for the A uto-neg otiatio n

process. Setting this bit advertises Half Duplex capability . Clearing

this bit does not advertise Half Duplex capability. R/W 1

4:0 Selector Field The Am79C973/Am79C975 device is an 802.3 compliant device RO 0x01

198 Am79C973/Am79C975

PRELIMINARY

ANR5: Auto-Negotiation Link Partner Ability

The Auto-Negotiation Link Partner Ability Register is

Read Only. The reg ister co nta ins the adverti se d ab il ity

of the lin k partner. The bit d efinit ions rep rese nt the re-

ceived link code word. This register contains either the

base page or the link pa rtne r’s nex t pages. See Table

45 and Table 46.

Table 45. ANR5: Auto- Negotiation Link Partner Ability Register (Register 5) - Base Page Format

Table 46. ANR5: Auto -Negotiation Link Partner Ability Register (Register 5) - Next Page Format

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 Next Page Link partner next page request. RO 0

14 Acknowledge Link partner acknowledgment RO 0

13 Remote Fault Link partner remote fault request RO 0

12:5 Technology Ability Link partner technology ability field RO 0

4:0 Selector Field Link partner selector field. RO 0

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 Next Page Link partner next page request. RO 0

14 Acknowledge Link partner acknowledgment RO 0

13 Message Page Link partner message page request RO 0

12 Acknowledge 2 1 = Link partner can comply with the request

0 = Link partner cannot comply with the request RO 0

11 Toggle Link partner toggle bit. RO 0

10:0 Message Field Link partner’s message code. RO 0

Am79C973/Am79C975 199

PRELIMINARY

ANR6: Auto-Negotiation Expansion Register

(Register 6)

The Auto-Negotiation Expansion Register provides ad-

ditional information which aids the Auto-Negotiation

process. The A uto-Negotiation Expansion Register bits

are Read Only. See Table 47.

Table 47. ANR6: Auto-Negotiation Expansion Register (Register 6)

ANR7: Auto-Negotiation Next Page Register

(Register 7)

The Auto-Negotiation Next Page Register contains the

next page link code word to be transmitted. On power-

up the default value of 0x2001 represents a message

page with the message code set to null. See Table 48.

Table 48. ANR7: Auto-Negotiation Next Page Register (Register 7)

Reserved Registers (Registers 8-15, 20-23, and 25-

31)

The Am79C973/Am79C975 device contains reserved

registers at addresses 8-15, 20-23, and 25-31. These

registe rs shoul d be ignore d when read and shou ld not

be written at any time.

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15:5 Reserved RO 0

4Para llel Dete ction

Fault 1=Parallel detection fault

0=No parallel detection fault RO, LH 0

3Link Partner Next

Page Able 1 = Link partner is next page able.

0 = Link partner is not next page able. RO 0

2 Next Page Able 1 = Am79C973/Am79C975 device channel is next page able

0 = Am79C9 73 /Am7 9C975 device channel is not next page ab l e RO 1

1 Page Received 1 = A new page has been received.

0 = A new page has not been received. RO, LH 0

0Link Partner ANEG

Able 1 = Link partner is Auto-Negotiation able.

0 = Link partner is not Auto-Negotiation able. RO 0

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15 Next Page Am79C973/Am79C975 device channel next page request. R/W 0

14 Reserved RO 0

13 Message Page Am79C973/Am79C975 device channel message page request R/W 1

12 Acknowledge 2

1 = Am79C973/Am79C975 device channel can comply with the

request

0 = Am79C973/Am79C975 device channel cannot comply with

the requ est

R/W 0

11 Toggle Am79C973/Am79C975 device channel toggle bit. RO 0

10:0 Message Field Message code field. R/W 0x001

200 Am79C973/Am79C975

PRELIMINARY

ANR16: INTERRUPT Status and Enable Register (Register 16)

The Interrupt bits indicate when there is a change in the

Link St atus, Duplex Mode, Auto-Nego tiation stat us, or

Speed status. Register 16 contains the interrupt status

and interrupt enable bits. The status is always updated

whether or not the interr upt enable bits are set . When

an interrupt occurs, the system will need to read the in-

terrupt register to clear the status bits and determine

the course of action needed. See Table 49.

Table 49. ANR16: INTERRUPT Status and Enable Register (Register 16)

Note:

1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.

ANR17: PHY Control/Status Register (Register 17)

This reg ister is used to con trol the con figurati on of th e

10/100 PHY unit of the Am79C973/Am79C975 device.

See Table 50.

When configuring the device to enable/disable the

scrambler/descrambler (SDISSCR), and/or to enable/

disable the alignment (SDISALIGN), a software reset

after a write operation to the appropriate bits in this reg-

ister is mandatory for proper configuration. If a register

bit is only appropriate to use at one speed, then the

speed will be indicated in parenthesis in the Name col-

umn, for example, (10M).

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15:14 Reserved RO 0

13 Interrupt Test Enable

(Not e 1)

1 = When this bit is set, setting bits 12:9 of this register

will cause an INTR condition and will set bits 4:1

accordin gly. The eff ect is to test the regi ster bits with

a forced interrupt condition.

0 = Bits 4:1 are only set if the interrupt condition (if any

bits in 12:9 are set) occurs.

R/W 0

12 Link Status Chang e

Interrupt Enable 1 = Link Status Change

0 = This interrupt is masked. R/W 0

11 Duplex Mode Change

Interrupt Enable 1 = Duplex Mode Change

0 = This interrupt is masked. R/W 0

10 A uto -Neg C han ge

Interrupt Enable 1 = Auto-Neg Change

0 = This interrupt is masked. R/W 0

9Speed Change

Interrupt Enable 1 = Speed Change

0 = This interrupt is masked. R/W 0

8Global

Interrupt Enable 1= Global Interrupt

0 = This interrupt is masked. R/W 0

7:5 Reserved RO 0

4Link Status Chang e

Interrupt 1 = Link Status h as changed on a port.

0 = No change in Link Status RO,

LH 0

3Duplex Mode Change

Interrupt 1 = Duplex Mode has changed on a port

0 = No change in Duplex mode RO,

LH 0

2A uto -Neg C han ge

Interrupt 1 = Auto-Neg status has changed on a port

0 = No change in Auto-Neg status RO,

LH 0

1Speed Change

Interrupt 1 = Speed status has changed on a port

0 = No change RO,

LH 0

0Global

Interrupt

1 = Indicates a change in status of any of the above

interrupts

0 = Indicates no change in Interrupt Status

RO,

LH 0

Am79C973/Am79C975 201

PRELIMINARY

Table 50. ANR17: PHY Control/Status Register (Register 17)

Reg Bits Name Description Read/Write H/W

Reset Soft Reset

17 15 SDISALIGN

(100M) 1 = pass unaligned data to internal PHY

0 = enable alignment block R/W 0 Retains

Value

17 14 SDISSCR

(100M) 1 = disable scrambler/descrambler

0 = enable scrambler/descrambler R/W 0 Retains

Value

17 13 Force Link Good

Enable 1 = link status forced to link up state.

0 = link status is determined by the device. R/W 0 0

17 12 Disab le Lin k Pulse

(10M) 1 = Link pulses sent from the

10BASE-T trans mitter are sup pre ssed. R/W 0 0

17 11 SQE_TEST Disable

(10M)

1 = Disable s the SQE hea rtbeat which

occurs after each 10BASE-T transmission.

0 = The h eart beat assertion occu rs on the

COL pin approximately 1 µs after

transmission and for a duration of 1 µs.

R/W 0 0

17 10 EN_FEFI

(100M) 1 = enable FEFI, 0 = disable FEFI

This bit is ignored if auto-neg is enabl ed. R/W 0 0

17 9 Jabber Detect

Disable (10M) 1 = disable jabber detect

0 = enable jabber detect R/W 0 0

17 8:7 LBK[1-0]

(100M)

00 = normal operation

01 = unused

10 = unused

11 = serial loopback

R/W 00 00

17 6 Receive Polarity

Reversed

(10M)

1 = Receive polarity of the 10BASE-T

receiver is reversed.

0 = Receive polarity is correct. RO 0 0

17 5 Auto Receive

Polarity Correction

Disable (10M)

1 = pol arity corr ection circ uit is disab le d for

10BASE-T.

0 = Self correcting polarity circuit is enabled R/W 0 0

17 4 Extended Distance

Enable

(10M)

1 = 10BASE-T receive squelch thresholds

are reduced to allow reception of frames

which are greater than 100 meters.

0 = Squelch thresholds are set fo r standard

distance of 100 meters.

R/W 0 0

17 3 TX_DISABLE 1 = TX± outputs not active for MLT-3 and

10BASE-T. TX± outputs to logical “0” for

PECL.

0 = Transmit valid data.

R/W 0 0

17 2 TX_CRS

1 = CRS is asserted when transmit or

receive medium is active.

0 = CRS is as serted when receiv e medium

is active.

RO 1 1

17 1 Reserved Reserved. RO 0 0

17 0 PHY Isolate d 1 = Internal PHY is isolated

0 = Internal PHY is enabled RO 0/1 0/1

202 Am79C973/Am79C975

PRELIMINARY

ANR18: Descrambler Resynchronization Timer

Descrambler Resynchronization Timer Register

(shown in Table 51) allows the user to program the time

it takes for the descram bler to start the resynchron iza-

tion proc ess . This is to ens ure th at the Descr amb ler r e-

synchronizes itself to the next IDLE symbol stream

after it receives a packet of excessive length. This reg-

ister sh ould be programmed as descri bed in the Table

51. The programmed timer value should always be

greater than the length of the ma ximum size packet in

nor m al ope ratio n.

Table 51. ANR18: Descrambler Resynchronization Timer (Register 18)

Note:

1. The corresponding time to this setting is 1ms.

ANR19: PHY Management Extension Register

(Register 19)

Table 52 contains the PHY Management Extension

Table 52. ANR19: PHY Management Extension Register (Register 19)

ANR24: Summary Status Register (Register 24)

The Summ ary Sta tus register is a global register con-

taining status information. This register is Read/Only

and re pres ent s t he mo st impo rtant da t a whi ch a si ng le

registe r acc ess can convey. The Summ ary Sta tus reg-

ister indicates the following: Link Status, Full Duplex

Status, Auto-Negotiation Alert, and Speed. See Table

53.

Reg Bits Name Description Read/

Write Default

Value Soft

Reset

18 15-0 Descrambler Resynch Time r

Each bit indicates 4 clocks, or 160

ns. The co unt dec rem en ts from a

default value of 1 ms or an initial

value loaded by the user. This

counter provides a maximum timer

value of 10.5 ms.

R/W 000110000

1101010

(Note 1)

0001100

0011010

(Not e 1)

Reg Bits Name Description Read/Write Default Value Soft Reset

19 15:6 Reserved Write as 0, ignore on read. RO 0 0

19 5 Mgmt Frame

Format

1 = last management frame

was invalid (opcode error , etc.);

0 = last management frame

was valid.

RO 0 0

19 4-0 PHY Address PHY Address defaults to

11110. RO 11110 Retains

Value

Am79C973/Am79C975 203

PRELIMINARY

Table 53. ANR24: Summary Status Register (Register 24)

Initialization Block

Note: When SSIZE32 (BCR20, bit 8) is set to 0, the

software structures are defined to be 16 bits wide. The

base address of the initialization block must be aligned

to a DWord boundar y, i.e., CSR1, bit 1 an d 0 must be

cleared to 0. When SSIZE32 is set to 0, the initialization

block looks like Table 54.

Note: The Am79C973/Am79C975 controller performs

DWord accesses to read the initialization block. This

statement is always true, regardless of the setting of

the SSIZE32 bit.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide. The base ad-

dress of the initialization block must be aligned to a

DWord boundary, i.e., CSR1, bits 1 and 0 must be

cleared to 0. When SSIZE32 is set to 1, the initialization

block looks like Table 55.

Bit(s) Name Description Read/

Write H/W or Soft

Reset

15-4 Reserved Write as 0; Ignore on Read 0 0

3Link Status

1 = Link Status is up.

0 = L ink Status is down. R/O 0

2 Full Duplex 1 = Operating in full duplex mode

0 = Operating in half duplex mode R/O 0

1AutoNEG

Alert 1 = AutoNEG status has changed

0 = AutoNEG status unchanged R/O 0

0 Speed 1 = Operating at 100 Mbps

0 = Operating at 10 Mbps R/O 1

Table 54. Initialization Block (SSIZE32 = 0)

Address Bits 15-13 Bit 12 Bits 11-8 Bits 7-4 Bits 3-0

IADR+00h MODE 15-00

IADR+02h PADR 15-00

IADR+04h PADR 31-16

IADR+06h PADR 47-32

IADR+08h LADRF 15-00

IADR+0Ah LADRF 31-16

IADR+0Ch LADRF 47-3 2

IADR+0Eh LADRF 63-48

IADR+10h RDRA 15-00

IADR+12h RLEN 0RES TDRA 23-16

IADR+14h TDRA 15-00

IADR+16h TLEN 0RES TDRA 23-16

204 Am79C973/Am79C975

PRELIMINARY

RLEN and TLEN

When SSIZE32 (BCR20, bit 8) is set to 0, the software

structures are defined to be 16 bits wide, and the RLEN

and TLEN fields in the initialization block are each three

bits wide. The values in these fields determine the num-

ber of transmit and receive Descriptor Ring Entries

(DRE) which are used in the descriptor rings. Their

meaning is shown in T able 56. If a value other than those

listed in Tab le 56 is desired, CSR76 and CSR78 can be

written after initialization is complete.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide, and the RLEN

and TLEN fields in the initialization block are each 4 bits

wide. The values in these fields dete rmine the number

of transmit a nd recei ve Descrip tor Ring En trie s (DRE)

which are used in the descr iptor rings. Their meaning

is shown in Table 57.

If a value other than those listed in Table 57 is desired,

CSR76 an d CS R78 can be written after initia li zat ion is

complete.

RDRA and TDRA

RDRA and TDRA indicate where the transmit and re-

ceive descriptor rings begin. Each DRE must be located

at a 16-byte address boundary when SSIZE32 is set to

1 (BCR20, bit 8). Each DRE must be located at an 8-

byte address boundary when SSIZE32 is set to 0

(BCR20, bit 8).

LADRF

The Logical Address Filter (LADRF) is a 64-bit mask

that is used to accept incoming Logical Addresses. If

the fir st bit in th e incom ing a ddress (as transmitted on

the wire) is a 1, it indicates a logical address. If the first

bit is a 0, it is a physical address and is compared

against the physical address that was loaded through

the initialization block.

A logical address is passed through the CRC generator,

producing a 32-bit result. The high order 6 bits of the

CRC is used to select one of the 64 bit positions in the

Logical Address Filter . If the selected filter bit is set, the

address is accepted and the frame is placed into mem-

ory.

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message may

be intended for the node. It is the no de’s respons ibil ity

to determine if the message is actually intended f or the

node by comparing the destination address of the stored

message with a list of acceptable logical addresses.

Table 55. Initialization Block (SSIZE32 = 1)

Address Bits Bits Bits Bits Bits Bits Bits Bits

31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

IADR+00h TLEN RES RLEN RES MODE

IADR+04h PADR 31-00

IADR+08h RES PADR 47-32

IADR+0Ch LADRF 31-00

IADR+10h LADRF 63-32

IADR+14h RDRA 31-00

IADR+18h TDRA 31-0 0

Table 56. R/TLEN Decoding (SSIZE32 = 0)

R/TLEN Number of DREs

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

Table 57. R/TLEN Decoding (SSIZE32 = 1)

R/TLEN Number of DREs

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

11XX 512

1X1X 512

Am79C973/Am79C975 205

PRELIMINARY

If the Logical Address Filter is loaded with all zeros and

promiscuous mode is disabled, all incoming logical ad-

dresses except broadcast will be rejected. If the

DRCVBC bit (CSR15, bit 14) is set as well, the broad-

cast packets will be rejected. See Figure 51.

PADR

This 48-bit value represents the unique node address

assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and

used for internal address comparison. PADR[0] is com-

pared with the first bit in the destination address of the

incoming frame. It must be 0 since only the destination

address of a unicast frames is compared to PADR. The

six hex-digit nomenclature used by the ISO 8802-3

(IEEE/ANSI 802.3) maps to the Am79C973/

Am79C975 PADR register as follows: the first byte is

compared with PADR[7:0], with PADR[0] being the

least significant bit of the byte. The second ISO 8802-3

(IEEE/ ANS I 802.3 ) byte is compared with PADR[15:8],

again from the least significant bit to the most signifi-

cant bit, and so on. The sixth byte is compared with

PADR[47:40], the least significant bit being PADR[40].

Mode

The mode register field of the initialization block is cop-

ied into CSR15 and inter preted according to the de-

scription of CSR15.

Figure 51. Address Match Logic

Receive Descriptors

When SWSTYLE (BCR20, bits 7-0) is set to 0, then the

software structures are defined to be 16 bits wide, and

receive descriptors look like Table 58 (CRDA = Current

Receive Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 2, then the

software structures are defined to be 32 bits wide, and

receive descriptors look like Table 59 (CRDA = Current

Receive Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the

software structures are defined to be 32 bits wide, and

receive descriptors look like Table 60 (CRDA = Current

Receive Descriptor Address).

Table 58. Receive Descriptor (SWSTYLE = 0)

CRC

GEN

SEL

31 26

MUX

63 0

Match = 1 Packet Accepted

Match = 0 Packet Rejected

Match

Logical

Address Filter

(LADRF)

32-Bit Resultant CRC

Received Message

Destination Address

21510B-56

Address 151413121110 9 8 7-0

CRDA+00h RBADR[15:0]

CRDA+02h OWN ERR FRAM OFLO CRC BUFF STP ENP RBADR[23:16]

CRDA+04h1111 BCNT

CRDA+06h0000 MCNT

206 Am79C973/Am79C975

PRELIMINARY

RMD0

Bit Name Description

31-0 RBADR Receive Buffer address. This field

contains the address of the re-

ceive buffer that is associated

with this descriptor.

RMD1

Bit Name Description

31 OWN This bit indicates whether the de-

scriptor entry is owned by the

host (OWN = 0) or by the

Am79C9 73/ Am 79C9 75 c on tr oll er

(OWN = 1). The Am79C973/

Am79C975 controller clears the

OWN bit after filling the buffer that

the desc riptor poi nts to. The hos t

sets the OWN bit after emptying

the buffer.

Once the Am79C973/Am79C975

controller or host has relin-

quished ownership of a buffer, it

must not change any field in the

descriptor entr y.

30 ERR ERR is the OR of FRAM, OFLO,

CRC, BUFF, or BPE. ERR is set

by the Am79C973/Am79C975

controller and cleared by the

host.

29 FRAM Framing error indicates that the

incoming frame contains a non-

integer multiple of eight bits and

there was an FCS error. If there

was no FCS error on the incom-

ing frame , then FRAM will no t be

set even if there was a non-

integer multiple of eight bits in the

frame. F RAM is not valid in inter -

nal loopback mode. FRAM is val-

id only when ENP is set and

OFLO is not. FR AM is set by the

Am79C 973 /Am 79C9 75 c on tr oll er

and cleared by the host.

28 OFLO Overflow error indicates that the

receiv er has lost all o r par t of th e

incoming frame, due to an inabili-

ty to move data from the receive

FIFO into a memory buffer before

the internal FIFO overflowed.

OFLO is set by the Am79C973/

Am79C975 controller and

cleared by the host.

27 CRC CRC indicates that the receiver

has detected a CRC (FCS) error

on the incoming frame. CRC is

valid only when ENP is set and

OFLO is not. CRC is set by the

Am79C 973 /Am 79C9 75 c on tr oll er

and cleared by the host. CRC will

also be set when Am79C973/

Am79C975 receives an RX_ER

indication from the external PHY

through the MII.

26 BUFF Buffer error is set any time the

Am79C 973 /Am 79C9 75 c on tr oll er

does not own the next buffer

Table 59. Receive Descriptor (SWSTYLE = 2)

Address 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-12 11-0

CRDA+00h RBADR[31:0]

CRDA+04h OWN ERR FRA

MOFL

OCRC BUF

FSTP ENP BPE PAM LAFM BAM RES 1111 BCNT

CRDA+08h RES RFRTAG[14:0] 0000 MCNT

CRDA+0Ch USER SPACE

Table 60. Receive Descriptor (SWSTYLE = 3)

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-0

CRDA+00h RES RES RES 0000 MCNT

CRDA+04h OWN ERR FRAM OFLO CRC BUFF STP ENP BPE RES 1111 BCNT

CRDA+08h RBADR[31:0]

CRDA+0Ch USER SPACE

Am79C973/Am79C975 207

PRELIMINARY

while data chaining a received

frame. This can occur in either of

two ways:

1. The OWN bit of the next buffer

is 0.

2. FIFO overflow occurred before

the Am79C973/Am79C975

controller was able to read the

OWN bit of the next descrip-

tor.

If a Buffer Er ror occur s, an Over -

flow Error may also occur inter-

nally in the FIFO, but will not be

reported in the descriptor status

entry unless both BUFF and

OFLO errors occur at the same

time. BUFF is set by the

Am79C973/Am79C975 controller

and cleared by the host.

25 STP Start of Pac ket i ndicates that th is

is the first buffer used by the

Am79C9 73/ Am 79C9 75 c on tr oll er

for this frame. If STP and ENP

are both set to 1, the frame fits

into a single buffer. Otherwise,

the frame is spread over more

than one buffer. When LAPPEN

(CSR3, bit 5) is cleared to 0, STP

is set by the Am79C973/

Am79C975 controller and

cleared by the host. When LAP-

PEN is set to 1 , ST P mus t be se t

by the host.

24 ENP End of Packet indicates that this

is the last buffer used by the

Am79C9 73/ Am 79C9 75 c on tr oll er

for this frame. It is used for data

chainin g buffer s. If both STP and

ENP are set, the frame fits into

one buffer and there is no data

chaining. ENP is set by the

Am79C9 73/ Am 79C9 75 c on tr oll er

and cleared by the host.

23 BPE Bus Parity Error is set by the

Am79C9 73/ Am 79C9 75 c on tr oll er

when a parity error occurred on

the bus interface during data

transfers to a receive buffer. BPE

is valid only when ENP, OFLO, or

BUFF are set. The Am79C973/

Am79C975 controller will only set

BPE when the advanced parity

error handling is enabled by set-

ting APERREN (BCR20, bit 10) to

1. BPE is set by the Am79C973/

Am79C975 controller and

cleared by the host.

This bit does not exist when the

Am79C973/Am79C975 controller

is programmed to use 16-bit soft-

ware structures for the descriptor

ring entries (BCR20, bits 7-0,

SWSTYLE is cleared to 0).

22 PAM Ph ysi cal A ddres s Ma tc h is se t by

the Am79C973/Am79C975 con-

troller when it accepts the re-

ceived frame due to a match of

the frame’s destination address

with the content of the physical

address register. PAM is valid

only when ENP is set. PAM is set

by the Am79C973/Am79C975

controller and cleared by the

host.

This bit does not exist when the

Am79C973/Am79C975 controller

is programmed to use 16-bit soft-

ware structures for the descriptor

ring entries (BCR20, bits 7-0,

SWSTYLE is cleared to 0).

21 LAFM Logical Address Filter Match is

set by the Am79C973/

Am79C 975 controller when it ac-

cepts the received frame based

on the value in the logical ad-

dress filter register. LAFM is valid

only when ENP is set. LAFM is

set by the Am79C973/

Am79C975 controller and

cleared by the host.

Note that if DRCVBC (CSR15, bit

14) is cleared to 0, only BAM, but

not LAFM will be set when a

Broadcast frame is received,

even if the Logic al Address Filter

is programmed in such a way that

a Broadcast frame would pass

the hash filter. If DRCVBC is set

to 1 an d the Logica l Address F il-

ter is progr ammed in suc h a way

that a Broadcast frame would

pass the hash filter, LAFM will be

set on the reception of a Broad-

cast fra m e.

This bit does not exist when the

Am79C973/Am79C975 controller

208 Am79C973/Am79C975

PRELIMINARY

is programmed to use 16-bit soft-

ware structures for the descriptor

ring entries (BCR20, bits 7-0,

SWSTYLE is cleared to 0).

20 BAM Broadcast Address Match is set

by the Am79C973/Am79C975

control ler when it accept s the re-

ceived frame, because the

frame’s destination address is of

the type ’Broadcast.’ BAM is valid

only when ENP is set. BAM is set

by the Am79C973/Am79C975

controller and cleared by the

host.

This bit does not exist when the

Am79C973/Am79C975 controller

is programmed to use 16-bit soft-

ware structures for the descriptor

ring entries (BCR20, bits 7-0,

SWSTYLE is cleared to 0).

19-16 RES Reserved locations. These loca-

tions should be read and written

as zeros.

15-12 ONES These four bits must be written as

ones. They are written by the host

and unchanged by the

Am79C973/Am79C975 control-

ler.

11-0 BCNT Buffer Byte Count is the length of

the buffer pointed to by this de-

scriptor, expressed as the two’s

complement of the length of the

buffer. This field is written by the

host and unchanged by the

Am79C973/Am79C975 control-

ler.

RMD2

Bit Name Description

31 ZERO This field is reserved. The

Am79C 973 /Am 79C9 75 c on tr oll er

will write a zero to this location.

30-16 RFRTAG Receive Frame Tag. Indicates

the Receive Frame Tag applied

from the EADI interface. This field

is use r define d and has a default

value of all zeros. When RX-

FRTG (CSR7, bit 14) is set to 0,

RFRTAG will be read as all zeros.

See the section on Receive

Frame Tagging for details.

15-12 ZEROS This field is reserved.

Am79C 973 /Am 79C9 75 c on tr oll er

will write zeros to these locations.

11-0 MCNT Message Byte Count is the length

in bytes of the received message,

expresse d as an uns i gned bina ry

integer . MCNT is v al id onl y whe n

ERR is clear and ENP is set.

MCNT is written by the

Am79C 973 /Am 79C9 75 c on tr oll er

and cleared by the host.

RMD3

Bit Name Description

31-0 US User Space. Reserved for user

defined space.

Am79C973/Am79C975 209

PRELIMINARY

Transmit Descriptors

When SWSTYLE (BCR20, bits 7-0) is set to 0, the soft-

ware structures are defined to be 16 bits wide, and trans-

mit descriptors look like Table 61 (CXDA = Current

Transmit Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 2, the

software structures are defined to be 32 bits wide, and

transmit descriptors look like Table 62 (CXD A = Current

Transmit Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the

software structures are defined to be 32 bits wide, and

transmit descriptors look like Table 63 (CXD A = Current

Transmit Descriptor Address).

TMD0

Bit Name Description

31-0 TBADR Transmit Buffer address. This

field contains the address of the

transmit buffer that is associated

with this descriptor.

TMD1

Bit Name Description

31 OWN This bit indicates whether the de-

scriptor entry is owned by the

host (OWN = 0) or by the

Am79C9 73/ Am 79C9 75 c on tr oll er

(OWN = 1). The host sets the

OWN bit after filling the buffer

pointed to by the descriptor entry.

The Am79C973/Am79C975 con-

troller clears the OWN bit after

transmitting the contents of the

buffer. Both the Am79C973/

Am79C975 controller and the

host must not alter a descriptor

entry after it has relinquished

ownership.

30 ERR ERR is the OR of UFLO, LCOL,

LCAR, RTRY or BPE. ERR is set

by the Am79C973/Am79C975

controller and cleared by the

host. Thi s bit is set in the curren t

descriptor when the error occurs

Table 61. Transmit Descriptor (SWSTYLE = 0)

Address 15 14 13 12 11 10 9 8 7-0

CXDA+00h TBADR[15:0]

CXDA+02h OWN ERR ADD_

FCS MORE/

LTINT ONE DEF STP ENP TBADR[23:16]

CXDA+04h 1 1 1 1 BCNT

CXDA+06h BUFF UFLO EX

DEF LCOL LCAR RTRY TDR

Table 62. Transmit Descriptor (SWSTYLE = 2)

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0

CXDA+00h TBADR[31:0]

CXDA+04h OWN ERR ADD_

FCS MORE/

LTINT ONE DEF STP ENP BPE RES 1111 BCNT

CXDA+08h BUFF UFLO EX

DEF LCOL LCAR RTRY RES RES RES RES RES RES TRC

CXDA+0Ch USER SPACE

Table 63. Transmit Descriptor (SWSTYLE = 3)

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0

CXDA+00h BUFF UFLO EX

DEF LCOL LCAR RTRY RES RES TRC

CXDA+04h OWN ERR ADD_

FCS MORE/

LTINT ONE DEF STP ENP BPE RES 1111 BCNT

CXDA+08h TBADR[31:0]

CXDA+0Ch USER SPACE

210 Am79C973/Am79C975

PRELIMINARY

and, there for e, m ay be se t in any

descriptor of a chained buffer

transmission.

29 ADD_FCS ADD_FCS dynamically controls

the generation of FCS on a frame

by frame basis. This bit should be

set with the ENP bit. However, for

backward compatibility, it is rec-

ommended th at this bit be se t for

every descriptor of the intended

frame. When ADD_FCS is set,

the state of DXMTFCS is ignored

and transmitter FCS generation is

activated. When ADD_FCS is

cleared to 0, FCS generation is

controlled by DXMTFCS. When

APAD _XM T ( C SR 4, b it 11) i s set

to 1, the setting of ADD_FCS has

no effect on frames shorter than

64 byt es. AD D_F CS is se t by th e

host, and is not changed by the

Am79C973/Am79C975 control-

ler. This is a reserved bit in the C-

LANCE (Am7 9C90 ) contr ol ler.

28 MORE/LTINT Bit 28 always functions as

MORE. The value of MORE is

written by the Am79C973/

Am79C975 c ontrolle r and is rea d

by the host. When LTINTEN is

cleared to 0 (CSR5, bit 14), the

Am79C9 73/ Am 79C9 75 c on tr oll er

will never look at the contents of

bit 28, write operations by the

host have no effect. When LTINT-

EN is set to 1 bit 28 changes its

function to LTINT on host write

operations and on Am79C973/

Am79C975 controller read opera-

tions.

MORE MORE indicates that more than

one retry was ne eded to transmi t

a frame. The value of MORE is

written by the Am79C973/

Am79C975 controller. This bit

has meaning only if the ENP bit is

set.

LTINT LTINT is used to suppress inter-

rupts after successful transmis-

sion on selected frames. When

LTINT is cl eared to 0 and ENP is

set to 1, the Am79C973/

Am79C975 controller will not set

TINT (CSR0, bit 9) after a suc-

cessful transmission. TINT will

only be set when the last descrip-

tor of a frame has both LTINT and

ENP set to 1. When LTINT is

cleared to 0, it will only cause the

suppre ssion of inter rupts for su c-

cessful transmission. TINT will al-

ways be set if the transmission

has an error. The LTINTE N over-

rides the function of TOKINTD

(CSR5, bit 15).

27 ONE ONE indicates that exactly one

retry was needed to transmit a

frame. ONE flag is not valid when

LCOL is set. The value of the

ONE bit is written by the

Am79C973/Am79C975 control-

ler. This bit has meaning only if

the ENP bit is set.

26 DEF Deferred indicates that the

Am79C 973 /Am 79C9 75 c on tr oll er

had to defer while tryin g to tran s-

mit a frame. This condition occurs

if the channel is busy when the

Am79C 973 /Am 79C9 75 c on tr oll er

is ready to transmit. DEF is set by

the Am79C973/Am79C975 con-

troller and cleared by the host.

25 STP Start of Pac ket i ndicates that th is

is the first buffer to be used by the

Am79C 973 /Am 79C9 75 c on tr oll er

for this frame. It is used for data

chaining buffers. The STP bit

must be set in the first buffer of

the frame, or the Am79C973/

Am79C975 controller will skip

over the descriptor and poll the

next descriptor(s) until the OWN

and STP bits are set. STP is set

by the host and is not changed by

the Am79C973/Am79C975 con-

troller.

24 ENP End of Packet indicates that this

is the last buffer to be used by the

Am79C 973 /Am 79C9 75 c on tr oll er

for this frame. It is used for data

chainin g buffers . If both STP and

ENP are set, the frame fits into

one buffer and there is no data

chaining. ENP is set by the host

and is not changed by the

Am79C973/Am79C975 control-

ler.

23 BPE Bus Parity Error is set by the

Am79C 973 /Am 79C9 75 c on tr oll er

Am79C973/Am79C975 211

PRELIMINARY

when a parity error occurred on

the bus interface during a data

transfers from the transmit buf fer

associated with this descriptor.

The Am79C973/Am79C975 con-

troller wil l only set BPE when the

advance d parity error handling is

enabled by setting APERREN

(BCR20, bit 10) to 1. BPE is set

by the Am79C973/Am79C975

controller and cleared by the

host.

This bit does not exist, when the

Am79C973/Am79C975 controller

is programmed to use 16-bit soft-

ware structures for the descriptor

ring entries (BCR20, bits 7-0,

SWSTYLE is cleared to 0).

22-16 RES Reserved locations.

15-12 ONES These four bits must be written as

ones. This field is written by the

host and unchanged by the

Am79C973/Am79C975 control-

ler.

11-00 BCNT Buffer Byte Count is the usable

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length of

the buffer. This is the number of

bytes from this buffer that will be

transmitted by the Am79C973/

Am79C975 controller. This field is

written by the host and is not

changed by the Am79C973/

Am79C975 controller. There are

no minimum buffer size restric-

tions.

TMD2

Bit Name Description

31 BUFF Buffer error is set by the

Am79C9 73/ Am 79C9 75 c on tr oll er

during transmission when the

Am79C9 73/ Am 79C9 75 c on tr oll er

does not find the E NP flag in th e

current descriptor and does not

own the next descriptor. This can

occur in eit her of two ways:

1. The OWN bit of the next buffer

is 0.

2. FIFO underflow occurred be-

fore the Am79C973/Am79C975

controller obtained the STATUS

byte (TMD1[31:24]) of the next

descriptor. BUFF is set by the

Am79C973/Am79C975 controller

and cleared by the host.

If a Buffer Error occurs, an Un-

derflow Error will also occur.

BUFF is set by the Am79C973/

Am79C975 controller and

cleared by the host.

30 UFLO Underflow error indicates that the

transmitter has truncated a mes-

sage because it could not read

data from memory fast enough.

UFLO indicates that the FIFO has

emptied before the end of the

frame was reached.

When DXSUFLO (CSR3, bit 6) is

cleared to 0, the transmitter is

turned off when an UFLO error

occurs (CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C973/Am79C975 controller

gracefully recovers from an

UFLO error. It scans the transmit

descriptor ring until it finds the

start of a new fram e and starts a

new transmission.

UFLO is set by the Am79C973/

Am79C975 controller and

cleared by the host.

29 EXDEF Excessive Deferral. Indicates that

the transmitter has experienced

Excessive Deferral on this trans-

mit frame, where Excessive De-

ferral is defined in the ISO 8802-3

(IEEE/ ANSI 802.3) stan dard. Ex-

cessive Deferral will also set the

interrupt bit EXDINT (CSR5, bit

7).

28 LCOL Late Collision indicates that a col-

lision has occurred after the first

channel slot time has elapsed.

The Am79C973/Am79C975 con-

troller doe s not ret ry on late coll i-

sions. LCOL is set by the

Am79C 973 /Am 79C9 75 c on tr oll er

and cleared by the host.

27 LCAR Loss of Carrier is set when the

carrier is lost during an

Am79C 973 /Am 79C9 75 c on tr oll er

212 Am79C973/Am79C975

PRELIMINARY

initiate d transmi ssion wh en oper -

ating in half-duplex mode. The

Am79C9 73/ Am 79C9 75 c on tr oll er

does not retry upon loss of carri-

er. It will continue to transmit the

whole frame until done. LCAR will

not be set wh en th e dev ice i s op-

erating in full-duplex mode. LCAR

is not valid in Internal Loopback

Mode. LCAR is set by the

Am79C9 73/ Am 79C9 75 c on tr oll er

and cleared by the host.

LCAR will be set when the PHY is

in Link Fai l st a t e du ri ng tr an sm i s-

sion.

26 RTRY Retry error indicates that the

transmitter has failed after 16 at-

tempts to successfully transmit a

message, due to repeated colli-

sions on the medium. If DRTY is

set to 1 in the MODE register,

RTRY will set after one failed

transmission attempt. RTRY is

set by the Am79C973/

Am79C975 controller and

cleared by the host.

25-4 RES Reserved locations.

3-0 TRC Transmit Retry Count. Indicates

the number of transmit retries of

the associated packet. The maxi-

mum count is 15. However, if a

RETRY error occurs, the count

will roll over to 0.

In this case only, the Transmit

Retry Cou nt val ue of 0 sh oul d b e

interpreted as meaning 16. TRC

is written by the Am79C973/

Am79C975 controller into the last

transmit de scriptor of a fra me, or

when an error terminates a

frame. Valid only when OWN is

cleared to 0.

TMD3

Bit Name Description

31-0 US User Space. Reserved for user

defined space.

Am79C973/Am79C975 213

PRELIMINARY

PCI Configuration Registers

Note: RO = read only, RW = read/write

Offset Name Width

in Bit Access

Mode Default

Value

00h PCI Vendor ID 16 RO 1022h

02h PCI Device ID 16 RO 2000h

04h PCI Command 16 RW 0000h

06h PCI Status 16 RW 0290h

08h PCI Revision ID 8RO 40h

09h PCI Programming IF 8RO 00h

0Ah PCI Sub-Class 8RO 00h

0Bh PCI Base-Class 8RO 02h

0Ch Reserved 8RO 00h

0Dh PCI Latency Timer 8RW 00h

0Eh PCI Header Type 8RO 00h

0Fh Reserved 8RO 00h

10h PCI I/O Base Address 32 RW 0000 0001h

14h PCI Memory Mapped I/O Base Address 32 RW 0000 0000h

18h - 2Bh Reserved 8RO 00h

2Ch PCI Subsystem Vendor ID 16 RO 00h

2Eh PCI Subsystem ID 16 RO 00h

30h PCI Expansion ROM Base Addres s 32 RW 0000 0000h

31h - 33h Reserved 8RO 00h

34h Capabilities Pointer 8RO 40h

35h - 3Bh Reserved 8RO 00h

3Ch PCI Interrupt Line 8RW 00h

3Dh PCI Interrupt Pin 8RO 01h

3Eh PCI MIN_GNT 8RO 06h

3Fh PCI MAX_LAT 8RO FFh

40h PCI Capability Identifier 8RO 01h

41h PCI Next Item Pointer 8RO 00h

42h PCI Power Management Capabilities 16 RO 00h

44h PCI Power Management Control/Status 8RO 00h

46h PCI PMCSR Bridge Support Extensions 8RO 00h

47h PCI Data 8RO 00h

48h - FFh Reserved 8RO 00h

214 Am79C973/Am79C975

PRELIMINARY

Control and Status Registers

Note:

u = undefined value, R = Running register, S = Setup register, T = Test register; all default values are in hexadecimal format.

RAP

Addr Symbol Default Value Comments Use

00 CSR0 uuuu 0004 Am79C973/Am79C975 Controller Status Register R

01 CSR1 uuuu uuuu Lower IADR: maps to location 16 S

02 CSR2 uuuu uuuu Upper IADR: maps to location 17 S

03 CSR3 uuuu 0000 Interrupt Masks and Deferral Control S

04 CSR4 uuuu 0115 Test and Features Control R

05 CSR5 uuuu 0000 Extended Control and Interrupt 1 R

06 CSR6 uuuu uuuu RXTX: RX/TX Encoded Ring Lengths S

07 CSR7 0uuu 0000 Extended Control and Interrupt 1 R

08 CSR8 uuuu uuuu LADRF0: Logical Address Filter — LADRF[15:0] S

09 CSR9 uuuu uuuu LADRF1: Logical Address Filter — LADRF[31:16] S

10 CSR10 uuuu uuuu LADRF2: Logical Address Filter — LADRF[47:32] S

11 CSR11 uuuu uuuu LADRF3: Logical Address Filter — LADRF[63:48] S

12 CSR12 uuuu uuuu PADR0: Physical Address Register — PADR[15:0][ S

13 CSR13 uuuu uuuu PADR1: Physical Address Register — PADR[31:16] S

14 CSR14 uuuu uuuu PADR2: Physical Address Register — PADR[47:32] S

15 CSR15 see register

description MODE: Mode Register S

16 CSR16 uuuu uuuu IADRL: Base Address of INIT Block Lower (Copy) T

17 CSR17 uuuu uuuu IADRH: Base Address of INIT Block Upper (Copy) T

18 CSR18 uuuu uuuu CRBAL: Current RCV Buffer Address Lower T

19 CSR19 uuuu uuuu CRBAU: Current RCV Buffer Address Upper T

20 CSR20 uuuu uuuu CXBAL: Current XMT Buffer Address Lower T

21 CSR21 uuuu uuuu CXBAU: Current XMT Buffer Address Upper T

22 CSR22 uuuu uuuu NRBAL: Next RCV Buffer Address Lower T

23 CSR23 uuuu uuuu NRBAU: Next RCV Buffer Address Uppe r T

24 CSR24 uuuu uuuu BADRL: Base Address of RCV Ring Lower S

25 CSR25 uuuu uuuu BADRU: Base Address of RCV Ring Upper S

26 CSR26 uuuu uuuu NRDAL: Next RCV Descriptor Address Lower T

27 CSR27 uuuu uuuu NRDAU: Next RCV Descriptor Address Up per T

28 CSR28 uuuu uuuu CRDAL: Current RCV Descri ptor Address Lower T

29 CSR29 uuuu uuuu CRDAU: Current RCV Descriptor Address Upper T

30 CSR30 uuuu uuuu BADXL: Base Address of XMT Ring Lower S

31 CSR31 uuuu uuuu BADXU: Base Address of XMT Ring Upper S

32 CSR32 uuuu uuuu NXDAL: Next XMT Descriptor Address Lower T

33 CSR33 uuuu uuuu NXDAU: Next XMT Descriptor Address Upper T

Am79C973/Am79C975 215

PRELIMINARY

Control and Status Registers (Continued)

RAP

Addr Symbol Default Value

After H_RESET Comments Use

34 CSR34 uuuu uuuu CXDAL: Current XMT Descriptor Address Lower T

35 CSR35 uuuu uuuu CXDAU: Current XMT Descriptor Address Upper T

36 CSR36 uuuu uuuu NNRDAL: Next Next Receive Descriptor Address Lower T

37 CSR37 uuuu uuuu NNRDAU: Next Next Receive Descriptor Address Upper T

38 CSR38 uuuu uuuu NNXDAL: Next Next Transmit Descriptor Address Lower T

39 CSR39 uuuu uuuu NNXDAU: Next Next Transmit Descriptor Address Upper T

40 CSR40 uuuu uuuu CRBC: Current Receive Byte Count T

41 CSR41 uuuu uuuu CRST: Current Receive Status T

42 CSR42 uuuu uuuu CXBC: Current Transmit Byte T

43 CSR43 uuuu uuuu CXST: Cu rrent Transmit Status T

44 CSR44 uuuu uuuu NRBC: Next RCV Byte Count T

45 CSR45 uuuu uuuu NRST: Next RCV Status T

46 CSR46 uuuu uuuu POLL: Poll Time Counter T

47 CSR47 uuuu uuuu PI: Polling Interval S

48 CSR48 uuuu uuuu Reserved

49 CSR49 uuuu uuuu Reserved

50 CSR50 uuuu uuuu Reserved

51 CSR51 uuuu uuuu Reserved

52 CSR52 uuuu uuuu Reserved

53 CSR53 uuuu uuuu Reserved

54 CSR54 uuuu uuuu Reserved

55 CSR55 uuuu uuuu Reserved

56 CSR56 uuuu uuuu Reserved

57 CSR57 uuuu uuuu Reserved

58 CSR58 see regist er

description SWS: Software Style S

59 CSR59 uuuu uuuu Reserved T

60 CSR60 uuuu uuuu PXDAL: Previous XMT Descriptor Address Lower T

61 CSR61 uuuu uuuu PXDAU: Previous XMT Descriptor Address Upper T

62 CSR62 uuuu uuuu PXBC: Previous Transmit Byte Count T

63 CSR63 uuuu uuuu PXST: Previous Transmit Status T

64 CSR64 uuuu uuuu NXBAL: Next XMT Buffer Address Lower T

65 CSR65 uuuu uuuu NXBAU: Next XMT Buffer Address Upper T

66 CSR66 uuuu uuuu NXBC: Next Transmit Byte Count T

67 CSR67 uuuu uuuu NXST: Next Transmit Statu s T

68 CSR68 uuuu uuuu Reserved

69 CSR69 uuuu uuuu Reserved

70 CSR70 uuuu uuuu Reserved

216 Am79C973/Am79C975

PRELIMINARY

Control and Status Registers (Continued)

RAP

Addr Symbol Default Value

After H_RESET Comments Use

71 CSR71 uuuu uuuu Reserved

72 CSR72 uuuu uuuu RCVRC: RCV Ring Counter T

73 CSR73 uuuu uuuu Reserved

74 CSR74 uuuu uuuu XMTRC: XMT Ring Counter T

75 CSR75 uuuu uuuu Reserved

76 CSR76 uuuu uuuu RCVRL: RCV Ring Length S

77 CSR77 uuuu uuuu Reserved

78 CSR78 uuuu uuuu XMTRL: XMT Ring Length S

79 CSR79 uuuu uuuu Reserved

80 CSR80 uuuu 1410 DMATCFW: DMA Transfer Counter and FIFO Threshold S

81 CSR81 uuuu uuuu Reserved

82 CSR82 uuuu uuuu Transmit Descriptor Pointer Address Lower S

83 CSR83 uuuu uuuu Reserved

84 CSR84 uuuu uuuu DMABA: Address Register Lower T

85 CSR85 uuuu uuuu DMABA: Address Register Upper T

86 CSR86 uuuu uuuu DMABC: Buffer Byte Counter T

87 CSR87 uuuu uuuu Reserved

88 CSR88

262 5003

(Am79C973)

262 7003

(Am79C975)

Chip ID Register Lowe r T

89 CSR89 uuuu 262 Chip ID Register Upper T

90 CSR90 uuuu uuuu Reserved

91 CSR91 uuuu uuuu Reserved T

92 CSR92 uuuu uuuu RCON: Ring Length Conversion T

93 CSR93 uuuu uuuu Reserved

94 CSR94 uuuu uuuu Reserved

95 CSR95 uuuu uuuu Reserved

96 CSR96 uuuu uuuu Reserved

97 CSR97 uuuu uuuu Reserved

98 CSR98 uuuu uuuu Reserved

99 CSR99 uuuu uuuu Reserved

100 CSR100 uuuu 0200 Bus Timeout S

101 CSR101 uuuu uuuu Reserved

102 CSR102 uuuu uuuu Reserved

103 CSR103 uuuu 0105 Reserved

104 CSR104 uuuu uuuu Reserved

105 CSR105 uuuu uuuu Reserved

106 CSR106 uuuu uuuu Reserved

107 CSR107 uuuu uuuu Reserved

Am79C973/Am79C975 217

PRELIMINARY

Control and Status Registers (Concluded)

RAP

Addr Symbol Default Value

After H_RESET Comments Use

108 CSR108 uuuu uuuu Reserved

109 CSR109 uuuu uuuu Reserved

110 CSR110 uuuu uuuu Reserved

111 CSR111 uuuu uuuu Reserved

112 CSR112 uuuu uuuu Missed Frame Count R

113 CSR113 uuuu uuuu Reserved

114 CSR114 uuuu uuuu Received Collision Count R

115 CSR115 uuuu uuuu Reserved

116 CSR116 0000 0000 OnNow Miscellaneous S

117 CSR117 uuuu uuuu Reserved

118 CSR118 uuuu uuuu Reserved

119 CSR119 uuuu 0105 Reserved

120 CSR120 uuuu uuuu Reserved

121 CSR121 uuuu uuuu Reserved

122 CSR122 uuuu 0000 Receive Frame Alignment Control S

123 CSR123 uuuu uuuu Reserved

124 CSR124 uuuu 0000 Test Register 1 T

125 CSR125 003c 0060 MAC Enhanced Configuration Control T

126 CSR126 uuuu uuuu Reserved

127 CSR127 uuuu uuuu Reserved

218 Am79C973/Am79C975

PRELIMINARY

Bus Configuration Registers

Wri tes to thos e re g ister s ma rked as “Reserved” will have no effect. Reads from these locat ions wil l produce unde-

fined values.

RAP

Mnemonic Default Name Programmability

User EEPROM

0MSRDA 0005h Reserved No No

1MSWRA 0005h Reserved No No

2MC 0002h Miscellaneous Configuration Yes Yes

3Reserved N/A Reserved No No

4LED0 00C0h LED0 Status Yes Yes

5LED1 0084h LED1 Status Yes Yes

6LED2 0088h LED2 Status Yes Yes

7LED3 0090h LED3 Status Yes Yes

8Reserved N/A Reserved No No

9FDC 0000h Full-Duplex Control Yes Yes

10-15 Reserved N/A Reserved No No

16 IOBASEL N/A Reserved No No

17 IOBASEU N/A Reserved No No

18 BSBC 9001h Burst and Bus Control Yes Yes

19 EECAS 0002h EEPROM Control and Status Yes No

20 SWS 0200h Software Style Yes No

21 Reserved N/A Reserved No No

22 PCILAT FF06h PCI Latency Yes Yes

23 PCISID 0000h PCI Subsystem ID No Yes

24 PCISVID 0000h PCI Subsystem Vendor ID No Yes

25 SRAMSIZ 0000h SRAM Size Yes Yes

26 SRAMB 0000h SRAM Boundary Yes Yes

27 SRAMIC 0000h SRAM Interface Control Yes Yes

28 EBADDRL N/A Expansion Bus Address Lower Yes No

29 EBADDRU N/A Expansion Bus Address Upper Yes No

30 EBDR N/A Expansion Bus Data Port Yes No

31 STVAL FFFFh Software Timer Value Yes No

32 MIICAS 0000h PHY Control and Status Yes Yes

33 MIIADDR N/A PHY Address Yes Yes

34 MIIMDR N/A PHY Management Data Yes No

35 PCIVID 1022h PCI Vendor ID No Yes

36 PMC_A C811h PCI Power Management Capabilities

(PMC) Alias Register No Yes

37 DATA0 0000h PCI DATA Register Zero Alias Register No Yes

38 DATA1 0000h PCI DATA Register One Alias Register No Yes

39 DATA2 0000h PCI DATA Register Two Al ias Register No Yes

40 DATA3 0000h PCI DATA Register Three Alias Register No Yes

41 DATA4 0000h PCI DATA Register Four Alias Register No Yes

42 DATA5 0000h PCI DATA Register Five Alias Register No Yes

43 DATA6 0000h PCI DATA Register Six Alias Register No Yes

44 DATA7 0000h PCI DATA Register Seven Alias Register No Yes

45 PMR1 N/A Pattern Matching Register 1 Yes No

46 PMR2 N/A Pattern Matching Register 2 Yes No

47 PMR3 N/A Pattern Matching Register 3 Yes No

Am79C973/Am79C975 219

PRELIMINARY

PHY Management Registers

Wri tes to register s mar ked “Reserved” will have no ef-

fect. Reads from these locations will produce unde-

fined values.

Address Symbol Name Default Value After

H_RESET

0ANR0 PHY Control Register 2500h

1ANR1 PHY Status Register 7849h

2ANR2 PHY_ID[31:16] 0000h

3ANR3 PHY_ID[15:0] 6BA0h

4ANR4 Auto-Negotiation Advertisement Register 03C1h

5ANR5 Auto-Negotiation Link Partner Ability Register 0000h

6ANR6 Auto-Negotiation Expansion Register 0004h

7ANR7 Auto-Negotiation Next Page Register 2001h

8-15 ANR8-ANR15 Reserved --

16 ANR16 Interrupt Status and Enable Register 0000h

17 ANR17 PHY Control/Status Register 0001h

18 ANR18 Descrambler Resynchronizati on Timer Register 186Ah

19 ANR19 PHY Management Extension Register --

20-23 ANR20-ANR23 Reserved --

24 ANR24 Summary Status Register 0001h

25-31 ANR25-ANR31 Reserved --

220 Am79C973/Am79C975

PRELIMINARY

PROGRAMMABLE REGISTER SUMMARY

Am79C973/Am79C975 Control and Status Registers

CSR0 Status and control bits: (DEFAULT = 0004)

8000 ERR

4000 --

2000 CERR

1000 MISS

0800 MERR

0400 RINT

0200 TINT

0100I IDON

0080 INTR

0040 IENA

0020 RXON

0010 TXON

0008 TDMD

0004 STOP

0002 STRT

0001 INIT

CSR1 Lower IADR (Maps to CSR 16)

CSR2 Upper IADR (Maps to CSR 17)

CSR3 Interrupt masks and Deferral Control: (DEFAULT = 0)

8000 --

4000 --

2000 --

1000 MISSM

0800 MERRM

0400 RINTM

0200 TINTM

0100 IDONM

0080 --

0040 DXSUFLO

0020 LAPPEN

0010 DXMT2PD

0008 EMBA

0004 BSWP

0002 --

0001 --

CSR4 Interrupt masks, configuration and status bits: (DEFAULT = 0115)

8000 --

4000 DMAPLUS

2000 --

1000 TXDPOLL

0800 APAD_XMT

0400 ASTRP_RCV

0200 MFCO

0100 MFCOM

0080 UNITCMD

0040 UNIT

0020 RCVCCO

0010 RCVCCOM

0008 TXSTRT

0004 TXSTRTM

0002 --

0001 --

CSR5 Extended Interrupt masks, configuration and status bits: (DEFAULT = 0XXX)

8000 TOKINTD

4000 LTINTEN

2000 --

1000 --

0800 SINT

0400 SINTE

0200 --

0100 --

0080 EXDINT

0040 EXDINTE

0020 MPPLBA

0010 MPINT

0008 MPINTE

0004 MPEN

0002 MPMODE

0001 SPND

CSR7 Extended Interrupt masks, configuration and status bits: (DEFAULT = 0000)

8000 FASTSPND

4000 RXFRMTG

2000 RDMD

1000 RXDPOLL

0800 STINT

0400 STINTE

0200 MREINT

0100 MREINTE

0080 MAPINT

0040 MAPINTE

0020 MCCINT

0010 MCCINTE

0008 MCCIINT

0004 MCCIINTE

0002 MIIPDTINT

0001 MIIPDTNTE

CSR8 - CSR11 Logical Address Filter

CSR12 - CSR14 Physical Address Register

CSR15

MODE: (DEFAULT = 0)

bits [8:7] = PORTSEL, Port Selection

11 PHY Selected

10 Reserved

8000 PROM

4000 DRCVBC

2000 DRCVPA

1000 --

0800 --

0400 --

0200 --

0100 PORTSEL1

0080 PORTSEL0

0040 INTL

0020 DRTY

0010 FCOLL

0008 DXMTFCS

0004 LOOP

0002 DTX

0001 DRX

CSR47 TXPOLLINT: Transmit Polling Interval

CSR49 RXPOLLINT: Receive Polling Interval

CSR58

Software Style (mapped to BCR20)

bits [7:0] = SWSTYLE, Software Style Register.

0000 LANCE/PCnet-ISA

0002 PCnet-32

8000 --

4000 --

2000 --

1000 --

0800 --

0400 APERREN

0200 --

0100 SSIZE32

0080 --

0040 --

0020 --

0010 --

0008 SWSTYLE3

0004 SWSTYLE2

0002 --

0001 SWSTYLE0

Am79C973/Am79C975 221

PRELIMINARY

Am79C973/Am79C975 Control and Status Registers (Concluded)

CSR76 RCVRL: RCV Descriptor Ring length

CSR78 XMTRL: XMT Descri ptor Ring length

CSR80 FIFO threshold and DMA burst control (DEFAULT = 2810)

8000 Reserved

4000 Reserved

bits [13:12] = RCVFW, Receive FIFO Watermark

0000 Request DMA when 16 bytes are present

1000 Request DMA when 64 bytes are present

2000 Request DMA when 112 bytes are present

3000 Reserved

bits [11:10] = XMTSP, Transmit Start Point

0000 Start transmission after 20/36 (No SRAM/SRAM) bytes have been written

0400 Start transmission after 64 bytes have been written

0800 Star t transmission after 128 bytes have been written

0C00 Start transmission after 220 max/Full Packet (No SRAM/SRAM with UFLO bit set) bytes

have been written

bits [9:8] = XMTFW, Transmit FIFO Watermark

0000 Star t DMA when 16 write cycles can be made

0100 Star t DMA when 32 write cycles can be made

0200 Star t DMA when 64 write cycles can be made

0300 Star t DMA when 128 write cycles can be made

bits [7:0] = DMA Burst Register

CSR88~89 Chip ID (Contents = v2625003 (for Am79C973); v = Version Number)

Chip ID (Contents = v2627003 (for Am79C975); v = Version Number)

CSR112 Missed Frame Co un t

CSR114 Receive Collision Count

CSR116 OnNow Miscellaneous

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 PME_EN_OVR

0100 LCDET

0080 PMAT

0040 EMPPLBA

0020 MPMAT

0010 MPPEN

0008 RWU_DRIVER

0004 RWU_GATE

0002 RWU_POL

0001 RST_POL

CSR122 Receive Frame Alignment Control

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008 --

0004 --

0002 --

0001 RCVALGN

CSR124 BMU Test Register (DEFAULT = 0000)

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008 --

0004 RPA

0002 --

0001 --

CSR125 MAC Enhanced Configuration Control (DEFAUT = 603c

bits [15:8] = IPG, InterPacket Gap (Default=60xx, 96 bit times)

bits [8:0] = IFS1, InterFrame Space Part 1 (Default=xx3c, 60 bit times)

222 Am79C973/Am79C975

PRELIMINARY

Am79C973/Am79C975 Bus Configuration Registers

RAP Addr Register Contents

0MSRDA Programs width of DMA read signal (DEFAULT = 5)

1MSWRA Programs width of DMA write signal (DEFAULT = 5)

2MC Miscellaneous Configuration bits: (DEFAULT = 2)

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 APROMWE

0080 INITLEVEL

0040 --

0020 --

0010 --

0008 EADISEL

0004 --

0002 ASEL 0001

4LED0 Programs the function and width of the LED0 signal. (DEFAULT = 00C0)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 --

0004 RCVE

0002 --

0001 COLE

5LED1 Programs the function and width of the LED1 signal. (DEFAULT = 0084)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 --

0004 RCVE

0002 --

0001 COLE

6LED2 Programs the function and width of the LED2 signal. (DEFAULT = 0088)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 --

0004 RCVE

0002 --

0001 COLE

7LED3 Programs the function and width of the LED3 signal. (DEFAULT = 0090)

8000 LEDOUT

4000 LEDPOL

2000 LEDDIS

1000 100E

0800 --

0400 --

0200 MPSE

0100 FDLSE

0080 PSE

0040 LNKSE

0020 RCVME

0010 XMTE

0008 --

0004 RCVE

0002 --

0001 COLE

9FDC Full-Duplex Control. (DEFAULT= 0000)

8000 --

4000 --

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008 --

0004 FDRPAD

0002 --

0001 FDEN

16 IOBASEL I/O Base Address Lower

17 IOBASEU I/O Base Address Upper

18 BSBC Burst Size and Bus Control (DEFAULT = 2101)

8000 ROMTMG3

4000 ROMTMG2

2000 ROMTMG1

1000 ROMTMG0

0800 NOUFLO

0400 --

0200 MEMCMD

0100 EXTREQ

0080 DWIO

0040 BREADE

0020 BWRITE

0010 --

0008 --

0004 --

0002 --

0001 --

19 EECAS EEPROM Control and Status (DEFAULT = 0002)

8000 PVALID

4000 PREAD

2000 EEDET

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 EEN

0008 --

0004 ECS

0002 ESK

0001 EDI/EDO

20 SWSTYLE Software Style (DEFAULT = 0000, maps to CSR 58)

Am79C973/Am79C975 223

PRELIMINARY

Am79C973/Am79C975 Bus Configuration Registers (Concluded)

RAP Addr Register Contents

22 PCILAT PCI Latency (DEFAULT = FF06)

bits [15:8] = MAX_LAT

bits [7:0] = MIN_GNT

25 SRAMSIZE SRAM Size (DEFAULT = 0000)

bits [7:0] = SRAM_SIZE

26 SRAMBND SRAM Boundary (DEFAULT = 0000)

bits [7:0] = SRAM_BND

27 SRAMIC SRAM Interface Control (Default = 0000)

8000PTR TST

4000LOLATRX

bits [5:3] = EBCS, Expansion Bus Clock Source

0000 CLK pin, PCI clock

0008 Time Base Clock

0010 EBCLK pin, Expansion Bus Clock

bits [2:0] = CLK_FAC, Expansion Bus Clock Factor

0000 1/1 cloc k factor

0001 1/2 cloc k factor

0002 --

0003 --

28 EPADDRL Expan si on Port Address Low er (D efault = 0000)

29 EPADDRU Expansion Port Address Upper (Default = 0000)

8000 FLASH

4000 LAINC

2000 --

1000 --

0800 --

0400 --

0200 --

0100 --

0080 --

0040 --

0020 --

0010 --

0008

EPADDRU3

0004

EPADDRU2

0002

EPADDRU1

0001

EPADDRU0

30 EBDATA Expan si on Bus Data Port

31 STVAL Software Timer Interrupt Value (DEFAULT = FFFF)

32 MIICAS PHY Status and Control (DEFAULT = 0000)

8000 ANTST

4000 MIIPD

2000 FMDC1

1000 FMDC0

0800 APEP

0400 APDW2

0200 APDW1

0100 APDW0

0080 DANAS

0040

XPHYRST

0020

XPHYANE

0010 XPHYFD

0008 XPHYSP

0004 --

0002 MIILP

0001 --

33 MIIADDR PHY Address (DEFAULT = 0000)

bits [9:5] = PHYAD, Physical Layer Device Address

bits [4:0] = REGAD, Auto-Negotiation Register Address

34 MIIMDR PHY Data Po rt

35 PCI Vendor ID PCI Vendor ID Register (DEFAULT = 1022h)

36 PMC Alias PCI Power Management Capabilities (DEFAULT = 0000)

37 DATA 0 PCI Data Register Zero Alias Register (DEFAULT = 0000)

38 DATA 1 PCI Data Register One Alias Register (DEFAULT = 0000)

39 DATA 2 PCI Data Register Two Alias Register (DEFAULT = 0000)

40 DATA 3 PCI Data Register Three Alias Register (DEFAULT = 0000)

41 DATA 4 PCI Data Register Four Alias Register (DEFAULT = 0000)

42 DATA 5 PCI Data Register Five Alias Register (DEFAULT = 0000)

43 DATA 6 PCI Data Register Six Alias Register (DEFAULT = 0000)

44 DATA 7 PCI Data Register Seven Alias Register (DEFAULT = 0000)

45 PMR 1 OnNow Patter n Matching Register 1

46 PMR 2 OnNow Patter n Matching Register 2

47 PMR 3 OnNow Patter n Matching Register 3

224 Am79C973/Am79C975

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature. . . . . . . . . . . . . -65°C to +70°C

Supply voltage with respect to VSSB, VSS, DVSSD,

DVSSP

, and DVSSX . . . . . . . . . . . . . . –0.3 V to 3.63 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent de vice failure. Functionality at or above

these limits is not implied. Exposure to Absolute Maximum

Ratings for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Temperature (TA) . . . . . . . . . . . . . . . . . .0°C to +70°C

Supply Volta ges :

VDD, VDDB, VDD_PCI, . . . . . . . . . . . . . . +3.0 V to 3.6 V

DVDDD, DVDDA, DVDDP, D VDDTX, D VDDRX,

and DVDDCO . . . . . . . . . . . . . . . . . . . . .+3.3 V ±5%

All inputs within the range: . . . . . .VSS - 0.5 V to 5.5 V

Opera ting range s define those li mits between w hich the func-

tionality of the device is guaranteed.

Am79C973/Am79C975 225

PRELIMINARY

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES

(unless otherwise specified)

Parameter

Symbol Param e t er De scriptio n Test Conditions Min Max Units

Digital I/O (Non-PCI Pins)

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

VOL Output LOW Voltage IOL1 = 4 mA

IOL2 = 6 mA

IOL3 = 12 mA (Note 1) 0.4 V

VOH Output HIGH Voltage (Notes 2, 3) IOH1= -4 mA

IOH2= -2 mA

(Note 3) 2.4 V

IOZ Output Leakage Current (Note 4) 0 V <VOUT <VDD -10 10 µA

IIX Input Leakage Current (Note 5) 0 V <VIN <VDD -10 10 µA

IIL Input LOW Current (Note 6) VIN = 0 V; VDD = 3.6 V -200 -10 µA

IIH Input HIGH Current (Note 6) VIN = 2.7 V; VDD = 3.6 V -50 10 µA

PCI Bus Interface - 5 V Signaling

VIH Input HIGH Voltage 2.0 5.5 V

VIL Input LOW Voltage -0.5 0.8 V

IOZ Output Leakage Current (Note 4) 0 V <VIN < VDD_PCI -10 10 µA

IIL Input LOW Current VIN = 0.5 V -- -70 µA

IIH Input HIGH Current VIN = 2.7 V -- 70 µA

IIX_PME Input Leakage Current (Note 7) 0 V = < VIN < 5.5 V -1 1µA

VOH Output HIGH Voltage (Note 2) IOH = -2 mA 2.4 V

VOL Output LOW Voltage IOL4 = 3 mA

IOL2 = 6 mA (Note 1) 0.55 V

PCI Bus Interface - 3.3 V Signaling

VIH Input HIGH Voltage 0.5 VDD_PCI VDD_PCI +

0.5 V

VIL Input LOW Voltage -0.5 0.3 V DD_PCI V

IOZ Output Leakage Current (Note 4) 0 V < VOUT < VDD_PCI -10 10 µA

IIL Input HIGH Current 0 V < VIN < VDD_PCI -10 10 µA

IIX_PME Input Leakage Current (Note 7) 0 V = < VIN < 5.5 V -1 1µA

VOH Output HIGH Voltage (Note 2) IOH = -500 µA 2.4 V

VOL Output LOW Voltage IOL = 1500 µA 0.1 VDD_PCI V

226 Am79C973/Am79C975

PRELIMINARY

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise

specified (Concluded)

Notes:

1. IOL2 applies to DEVSEL, FRAME, INTA, IRDY, PERR, SERR, STO P, TRDY, EECS, EEDI, EBUA_EBA[7:0], EBDA[15:8],

EBD[7:0], EROMCS, AS_EBOE, EBWE, and PHY_RST.

IOL3 applies to LED0, LED1, LED2, LED3, and WUMI.

IOL4 applies to AD[31:0], C/BE[3:0], PAR, and REQ pins in 5 V signalling environment.

2. VOH does not apply to open-drain output pins.

3. IOH2 applies to all other outputs.

4. IOZ applies to all output and bidirectional pins, except the PME pin. Tests are performed at VIN = 0 V and at VDD only.

5. IIX applies to all input pins except PME, TDI, TCLK, and TMS pins.

6. IIL and IIH apply to the TDI, TCLK, and TMS pins.

7. IIX_PME applies to the PME pin only. Tes ts are performed at V IN = 0 V and 5.5 V only.

8. Parameter not tested. Value determined by characterization.

9. CCLK applies only to the CLK pin.

10. CIDSEL applies only to the IDSEL pin.

11.Power supply current values listed here are preliminary estimates and are not guaranteed.

Parameter

Symbol Parameter Description Test Conditions Min Max Units

Pin Capacitance

CIN Pin Capacitance FC = 1 MHz (Note 8) 10 pF

CCLK CLK Pin Capacitance FC = 1 MHz (Notes 8,9) 512 pF

CIDSEL IDSEL Pin Capacitance Fc = 1 MHz (Notes 8, 10 8pF

LPIN Pin Inductance Fc = 1 MHz (Not e 8) 20 nH

Power Supply Current (Note 11)

IDD Dynamic Current PCI CLK at 33 MHz 320.0 mA

IDD_WU1

Wake-up current when the device is

in the D1, D2, or D3 state and the

PCI bus is in the B0 or B1 stat e.

PCI CLK at 33 MH z, Dev ice in Magic

Packet or OnNow mode, receiving

non-matching packets 300.0 mA

IDD_WU2

Wake-up current when the device is

in the D2 or D3 state and the PCI bus

is in the B2 or B3 state.

PCI CLK LOW, PG LOW, Device at

Magic Packet or OnNow mode,

receiving non-matching packets 290.0 mA

IDD_S Static IDD PCI CLK, RST, and RST HIGH. 135.0 mA

Am79C973/Am79C975 227

PRELIMINARY

SWITCHING CHARACTERISTICS: BUS INTERFACE

Para meter

Symbol Parameter Name Test Condition Min Max Unit

Clock Timing

FCLK CLK Frequency 033 MHz

tCYC CLK Period @ 1.5 V for 5 V signaling

@ 0.4 VDD for 3.3 V signaling 30 _ns

tHIGH CLK High Time @ 2.0 V for 5 V signaling

@ 0.4 VDD for 3.3 si gnaling 12 ns

tLOW CLK Low Time @ 0.8 V for 5 V signaling

@ 0.3 VDD for 3.3 V sign ali ng 12 ns

tFALL CLK Fall Time over 2 V p-p for 5 V si gnaling

over 0.4 VDD for 3.3 V signaling

(Note 1) 1 4 V/ns

tRISE CLK Rise Time over 2 V p-p for 5 V signaling

over 0.4 VDD for 3.3 V signaling

(Note 1) 1 4 V/ns

Output and Float Delay Timing

tVAL

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRD Y, STOP, DEVSEL, PERR,

SERR

Valid Delay

211 ns

tVAL (REQ)REQ Valid Delay 212 ns

tON

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY, STOP, DEVSEL Active

Delay 2ns

tOFF

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY, STOP, DEVSEL Float

Delay 28 ns

Setup and Hold Timing

tSU

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY, STOP, DEVSEL, IDSEL

Setup Time 7ns

AD[31:00], C/BE[3:0 ], PAR, FRAME,

IRDY, TRDY, STOP, DEVSEL, IDSEL

Hold Time 0ns

tSU (GNT)GNT Setup Time 10 ns

tH (GNT)GNT Hold Time 0ns

228 Am79C973/Am79C975

PRELIMINARY

SWITCHING CHARACTERISTICS: BUS INTERFACE (CONCLUDED)

Notes:

1. Not tested; parameter guaranteed by design characterization.

2. Parameter value is give n for automatic EEPROM read operation. When EEPROM port (BCR19) is used to access the EE-

PROM, software is responsible for meeting EEPROM timing requirements.

Analog I/O - PECL Mode

Notes:

1. Applies to RX+, RX-, SDI+, SDI- inputs only. Any voltage applied to these pins must not be below VI min or above VI max.

2. Tested for DVDD = Minimum, shown limits are specified over entire DVDD operating range.

3. Applies to TX+,TX- outputs only. Measured with the load of 82 W to DVDD and 150 W to DVSS on each SDI+ and SDI-.

Para meter

Symbol Pa rameter Name Test Condition Min Max Unit

EEPROM Timing

fEESK EESK Frequency (Note 2) 650 kHz

tHIGH (EESK) EESK High Time 780 ns

tLOW (EESK) EESK Low Time 780 ns

tVAL (EEDI) EEDI Valid Output Delay from EESK ( No te 2) -15 15 ns

tVAL (EECS) EECS V alid Output Delay from EESK (Note 2) -15 15 ns

tLOW (EECS) EECS Low Time 1550 ns

tSU (EEDO) EEDO Setup Time to EESK (Note 2) 50 ns

tH (EEDO) EEDO Hold Time from EESK (Note 2) 0ns

JTAG (IEEE 1149.1) Test Signal Timing

tJ1 TCK Frequency 10 MHz

tJ2 TCK Period 100 ns

tJ3 TCK High Time @ 2.0 V 45 ns

tJ4 TCK Low Time @ 0.8 V 45 ns

tJ5 TCK Rise Time 4ns

tJ6 TCK Fall Time 4ns

tJ7 TDI, TMS Setup Time 8ns

tJ8 TDI, TMS Hold Time 10 ns

tJ9 TDO Valid Delay 330 ns

tJ10 TDO Float Delay 50 ns

tJ11 All Outputs (Non-Test) Valid Delay 325 ns

tJ12 All Outputs (Non-Test) Float Delay 36 ns

tJ13 All Inputs (Non-Test)) Setup Time 8ns

tJ14 All Inputs (Non-Test) Hold Time 7ns

Symbol Parameter Description Test Conditions Minimum Maximum Unit

VIInput Voltage Range (Note 1) 2.0 V DVDD-0.30 V

VOH Output High Voltage PECL Load (Notes 2, 3) DVDD-0.45 DVDD-0.30 V

VOL Output Low Voltage PECL Load (Notes 2, 3) DVDD-1.4 DVDD-1.15 V

VDIFF Input Differential Voltage

(Note 1) DVDD=Maximum 0.40 1.1 V

Am79C973/Am79C975 229

PRELIMINARY

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION

INTERFACE

Note:

1. May need to delay RX_CLK to capture Start Frame Byte Delimi ter (SFBD) at 100 Mbps ope ration. Analog I/O - MLT-3 Mode

Analog I/O - MLT-3 Mode

10BASE-T Mode

Parameter

Symbol Parameter Name Test Condition Min Max Unit

External Address Detection Interface: Internal PHY @ 25 MHz

tEAD7 SFBD change to ↓ RX_CLK 020 (Note 1) ns

tEAD8 EAR deassertion to ↑ RX_CLK (first

rising edge) 40 ns

tEAD9 EAR assertion after SFD event

(frame rejection) 05,080 ns

tEAD10 EAR asserti on width 50 ns

External Address Detection Interface: Internal PHY @ 2.5 MHz

tEAD11 EAR deassertion to ↑ RX_CLK (first

rising edge) 400 ns

tEAD12 EAR assertion after SFD event

(frame rejection) 050,800 ns

tEAD13 EAR asserti on width 500 ns

Receive Frame Tag Timing with Media Independent Interface

tEAD14 RXFR TGE assertion to ↑SF/BD (first

rising edge) 0ns

tEAD15 RXFRTGE, RXFRTGD setup to ↑

RX_CLK 10 ns

tEAD16 RXFRTGE, RXFRTGD hold to ↑

RX_CLK 10 ns

tEAD17 RXFRTGE deassertion to ↓ RX_DV RX _CLK @25 MHz

RX_CLK @2.5 MHz 40

400 ns

Symbol Parameter Description Test Conditions Minimum Maximum Unit

VTXD Out put Peak Voltage 950 1050 mV

VSDA Input Differential Assert

Threshold (peak to peak) -- 1,000 mV

VSDD Input Differential Deassert

Threshold (peak to peak) 200 -- mV

IIX Input Leakage Current -10 10 µA

Symbol Parameter Description Test Conditions Minimum Maximum Unit

VOUT Output Voltage on TX± (peak) 1.55 1.98 V

VDIFF Input Differential Squelch

Asser t on RX± (peak) 300 520 mV

230 Am79C973/Am79C975

PRELIMINARY

Note: VOUT reflects output levels prior to 1:÷2 transformer stage.

VDIFF Input Differential De-Assert

Voltage on RX± (peak) 150 300 mV

IIX Input Leakage Current -10 10 µa

Am79C973/Am79C975 231

PRELIMINARY

EXTERNAL CLOCK

Figure 52 External Clock Timing

Table 64. Clock (XTAL1, XCLK = 1) Switching Characteristics

Table 65. Crysta l (XTAL1, XTAL2, XCLK = 0) Requirements

Table 66. Crysta l (XTAL1, XTAL2, XCLK = 0) Requirements

Parameter

Symbol Parameter Name Test Condition Min Nom Max Unit

FXTAL1 XTAL1 Frequency - 25 - MHz

tPER XTAL1 Per iod @ 0.4 VDD (3.3V) - 40 - ns

tPWH XTAL1 High Time @ 0.4 VDD (3.3V) 18 22 - ns

tPWL XTAL1 Low Time @ 0.3 VDD (3.3V) 18 22 - ns

tRISE XTAL1 Rise Time over 0.4 VDD (3.3V) 1 4 V/ns

tFALL XTAL1 Fall Time o ver 0.4 VDD (3.3V) 1 4 V/ns

Item Test Condition Min Nom Max Unit

Frequency -25 - MHz

Drive Level -- - mW

Load Capacitance - 18 - pF

Frequency Stability - - 50 to 100 ppm

ESR - - 50 ohms

Component Manufacturer Part Number

Crystal Epson America MA-505-25.000M

Crystal Ecliptek EC-AT-25.000M

Crystal Ecliptek ECSM-AT-25.000M

232 Am79C973/Am79C975

PRELIMINARY

PMD Interface

PECL

Note:

1. Not included in the production test.

Figure 53 PMD Interface Timing (PECL)

MLT-3

Figure 54 PMD Interface Timing (MLT-3)

No. Symbol Parameter Description Test Conditions Min Max Unit

160 tR (Note 1) TX+, TX- Rise Time PECL Load 0.5 3 ns

161 tF (Note 1) TX+, TX- Fall Time PECL Load 0.5 3 ns

162 tSK (Note 1) TX+ to TX- skew PECL Load -- +200 ps

TX+,TX–

TX+

TX–

162

161

80%

20%

160

21510D-57

No. Symbol Parameter Description Test Conditions Min Max Unit

170 tR (Note 1) TX+, TX- Rise Time 3 5 ns

171 tF (Note 1) TX+, TX- Fall Time 3 5 ns

172 tSK Note 1) TX+ to TX- skew -- +250 ps

171

172

170

TX+,

TX–

TX±

TX–

80%

20%

21510D-58

Am79C973/Am79C975 233

PRELIMINARY

10BASE-T

Note: RX± pulses narrowe r than tPWDRD (min) will maintain internal Carrier Sense on. RX± pulses wider than tPWKRD (max)

will turn internal Carrier Sense off.

Figure 55 10 Mbps Transmit (TX±) Timing Diagram

Figure 56 10 Mbps Receive (RX±) Timing Diagram

No. Symbol Parameter Description Test Conditions Min Max Unit

tTETD Transmit End of Transmission 250 375 ns

tPWKRD RX± Pulse Width Maintain/Turn Off

Threshold |VIN| > |VTHS| (Note 1) 136 200 ns

TX±

tTETD

21510D-59

RX±

t(PWKRD)

tPWKRD

VTSQ+

VTSQ-

t(PWKRD)

21510D-60

234 Am79C973/Am79C975

PRELIMINARY

SWITCHING WAVEFORMS

Key to Switching Waveforms

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010-PAL

Am79C973/Am79C975 235

PRELIMINARY

SWITCHING TEST CIRCUITS

Figure 57 Normal and Tri -State Outputs

Sense Point

THRESHOLD

21510D-61

236 Am79C973/Am79C975

PRELIMINARY

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE

Figure 58 CLK Waveform for 5 V Signaling

Figure 59 CLK Waveform for 3.3 V Signaling

Figure 60 Input Setup and Hold Timing

CLK

tHIGH

tFALL

tCYC

tRISE

tLOW 2.0 V

1.5 V

0.8 V

0.4 V

2.0 V

1.5 V

0.8 V

2.4 V

21510D-62

CLK

tHIGH

tFALL

tCYC

tRISE

tLOW 0.5 VDD_PCI

0.4 VDD_PCI

0.3 VDD_PCI

0.2 VDD_PCI

0.5 VDD_PCI

0.4 VDD_PCI

0.3 VDD_PCI

0.6 VDD_PCI

21510B21510D-63

CLK

AD[31:00], C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP,

DEVSEL, IDSEL

tSU

GNT

tH(GNT)

tSU(GNT)

Tx Tx

21510B21510D-64

Am79C973/Am79C975 237

PRELIMINARY

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (Contin ued)

Figure 61 Output Valid Delay Timing

Figure 62 Output Tri-state Delay Timing

Figure 63 EEPROM Read Funct ional Timing

CLK

tVAL(REQ)

Tx Tx Tx

MIN MAX

Valid n Valid n+1

REQ

MIN MAX

Valid n Valid n+1

tVAL

AD[31:00] C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP, DEVSEL,

PERR, SERR

21510D-65

CLK

Tx Tx Tx

AD[31:00], C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP,

DEVSEL, PERR

AD[31:00], C/BE[3:0],

PAR, FRAME, IRDY,

TRDY, STOP,

DEVSEL, PERR

Valid n

tOFF

tON

Valid n

21510D-66

EECS

EESK

EEDI

EEDO

01 1A6A5 A4 A3 A2 A1 A0

D15 D14 D13 D2 D1 D0

21510D-67

238 Am79C973/Am79C975

PRELIMINARY

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (Contin ued)

Figure 64 Automatic PREAD EEPROM Timing

Figure 65 JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling

EESK

EEDO

Stable

EEDI

EECS

tHIGH (EESK) tLOW (EESK)

tLOW (EECS)

tSU (EEDO)

tH (EEDO)

tVAL (EEDI,EECS)

21510D-68

TCK

tJ3

tJ6

tJ2

tJ5

tJ4 2.0 V

1.5 V

0.8 V

2.0 V

1.5 V

0.8 V

21510D-69

Am79C973/Am79C975 239

PRELIMINARY

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (Concluded)

Figure 66 JTAG (IEEE 1149.1) Test Signal Timing

TCK

TDI, TMS

TDO

tJ8

Output

Signals

tJ2

tJ7

tJ9

tJ11

tJ14

Input

Signals

tJ12

tJ13

21510D-70

240 Am79C973/Am79C975

PRELIMINARY

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE

Figure 67 EBCLK Waveform

Figure 68 Expansion Bus Read Timing

EBCLK

tHIGH

tFALL

tCYC

tRISE

tLOW 2.0 V

1.5 V

0.8 V

0.4V

2.0 V

1.5 V

0.8 V

2.4 V

21510D-71

EBCLK

EBUA_EGA[7:0]

EBD[7:0]

EROMCS

EBWE

AS_EBOE

tv_A_D t_HZ ts_D t_LZ

t_CS_L

th_D

t_CS_H

t_AS_L

t_AS_H

Upper

Address Lower

Address

EBDA[15:8]

Data

21510D-72

Am79C973/Am79C975 241

PRELIMINARY

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE (Concl uded)

Figure 69 Expansion Bus Write Timing

EBCLK

EBUA_EBA[7:0]

EBD[7:0]

EBWE, EROMCS

AS_EBOE

tv_A_D

t_CS_L t_CS_H

t_WE_CSAD

t_AS_L

t_AS_H

EBDA[15:8]

Upper

Address Lower

Address

DATA

21510D-73

242 Am79C973/Am79C975

PRELIMINARY

PHYSICAL DIMENSIONS*

PQR160

Plastic Quad Flat Pa ck (measured in millimeters)

*For reference only. BSC is an ANSI standard for Basic Space Centering.

25.35

REF

27.90

28.1031.00

31.40

Pin 120

Pin 80

0.65 BASIC

3.20

3.60

0.25

Min

Pin 40

Pin 1 I.D.

25.35

REF

Pin 160

27.90

28.10

31.00

31.40

3.95

MAX

SEATING PLANE

16-038-PQR-1

PQR160

12-22-95 lv

Am79C973/Am79C975 243

PRELIMINARY

PQL176

Thin Quad Flat Pack (measured in millimeters)

25.80

26.20

23.80

24.20

25.80

26.20

23.80

24.20

176

1.00 REF.

1.60 MAX

11° – 13°

0.50 BSC

1.35

1.45

16-038-PQT-1_AL

PQL176

5.12.97 lv

Trade marks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Device s, Inc.

Auto-Poll, C-LANCE, IMR100, LANCE, Mace, Magic Packet, PCnet, PCnet-ISA, PCnet-ISA+, PCnet-ISA-II, PCnet-32, PCnet-PCI,

PCnet-PCI II, and PCnet-FAST are trademarks of Advanced Micro Device s, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

21510E

APPENDIX A

Am79C973/Am79C975 244

PCnet™-FAST III

Recommended Ma gnetics

APPENDIX A: PCnet™-FAST III Recommended Magnetics

The PCnet-FAST II I controller uses magnetics that

have a Transmit (TX) tur ns ratio of 1:1.414 and a Re-

ceive (RX) turns ratio of 1:1. The following table shows

the current approved vendor list of 3.3 V magnetics rec-

ommended for use with the PCnet-FAST III device.

These m agneti cs modul es are p in co mpatible with th e

AMD Am79C873 NetPHY-1 10/100 PHY magnetics

and LevelOne LXT970 10/100 PHY magnetics that are

used today with PCnet-FAST and PCnet-FAST+, but

are not the same part numbers since the turns ratios

are different.

Table 67. Recommended Magnetics Vendors

Vendor Part Number Package

Halo TG22-SI43ND 16-pin module

Halo TG22-SI41N2 16-pin module

Halo TG110-SI41N2 16-pin module

Bel Fuse S558-5999-G9 16-pin module

Bel Fuse S558-5999-G8 16-pin module

Pulse Engineering H1081 16-pin module

Pulse Engineering H1119 16-pin module

Bothhand 16ST61A8 16-pin module

PCA Electronics EPF8095G 16-pin module

PCA Electronics EPF8096G 16-pin module

Transpower Technologies RJ622-CL1 RJ45/Magnetics Combo

XFMRS XF973-COMBO1-4 RJ45/Magnetics Combo

APPENDIX B

Am79C973/Am79C975 245

Serial Management Interface Unit

(Am79C975 only)

APPENDIX B: Serial Management Interface Unit (Am79C975 only)

Related Documents :

nSystem Management Bus Specification Revision

1.0, February 15, 1995

nPhillips Semiconductors: The I2C-bus and how to

use it (including specifications), April 1995

Overview

The Am79C973 and Am79C975 devices are fully-

integrated 32-bit PCI bus 10/100 Mbps Ethernet con-

trollers with advanced power and network manage-

ment features. With the Ser ial Management Interface,

the Am79C975 device offers a very powerful system

management feature in addition to the management

features offered with the Am79C973 device.

The Serial Management Interface Unit (SMIU) is based

on the industry standard Inter-IC (I2C) bus and System

Management Bus (SMBus) specifications. It enables a

system to exchange short message with another net-

work station (e.g., management console) for remote

monitoring and alerting of system management param-

eter s and e v ent s. Th e SMIU is capab le of commu nicat-

ing within the system and over the network during

normal operation or in low power mode, even if the

Am79C975 controller is not initialized or setup for

transmit or receive operation by a network driver.

One application for the Serial Management Interface is

a system where a dedicated microcontroller monitors

various hardware components (e.g., fan, memory, chip

set) and parameters (e.g., temperature, voltage) in

order to obtain informati on about the statu s of the sys-

tem. If there is any problem or issue with the system,

the micr ocontroller can send a message via the serial

management interface of the Am79C975 Am79C975

control ler to anot her stat ion on th e networ k, for exam-

ple, to alert the system administrator of the trouble

event.

A less ro bust (but more cost effective) impleme ntation

in a typical PC system simply uses the host processor

to contro l op eration o f the I2C/SMBu s i nter faces of th e

PCI chipset (southbridge) and hardware monitoring de-

vice, and the Serial Management Interface of the

Am79C 975 co ntr ol ler.

The independent interface allows access to the net-

work even at times when there is no operating system

and network driver running on the system. The inter-

face, howe ver, also allows access to the network in par-

allel to the normal traffic.

The electrical interface of the SMIU is comprised of 3

pins: cl ock, data, a nd i nterru pt. The hos t can access a

set of registers via the interface to identify the

Am79C975 controller, to obtain information about the

status of the dev ice, to get the network addr ess of the

local node and the management station of the network,

and to con trol the transmi ssion and recepti on of man-

agement frames. The Am79C975 controller provides

internal transmit and receive data memories of 128

bytes each to store the management frames. The re-

ceive path inclu des a patter n match filter to quali fy in-

coming frames.

The SMIU is designed such that the amount of software

running on the microcontroller in order to transmit or re-

ceive management frames is minimized. The SMIU

does not use the PCI clock (CLK). It will operate with

CLK stopped or running.

The electrical interface of the SMIU follows the I2C

specific ation. Th e sig nalin g and regi ster acces s proto-

col of the SMIU is a subset of the System Management

Bus (SMB us ) protoc ol.

Am79C975 PIN DESIGNATIONS

Listed by Pin Number

160-pi n PQFP package 176-pin TQ FP pa ckage

Pin No Pin Name Pin No Pin Name

96 MIRQ 106 MIRQ

98 MDATA 108 MDATA

100 MCLOCK 110 MCLOCK

246 Am79C973/Am79C975

PRELIMINARY

Listed By Group

Note: OD6 = Open Drain Output, IOL = 6 mA, 50 pF

load.

Listed By Function

MCLOCK

SMIU Clock Input/Output

MCLOCK is the clock pin of the serial management in-

terface. MCLOCK is typically driven by an external

master (e.g., the southbridge or a dedicated microcon-

troller). The Am79C975 controller will drive the clock

line low in order to insert wait states before it starts

sending out data in response to a read. The frequency

of the clock signal can vary between 10 KHz and 100

KHz and it can change from cycle to cycle.

Note: MCLOCK is capable of running at a frequency

as high as 1.25 MHz to allow f or shorter production test

time.

MDATA

SMIU Data Input/Output

MDATA is the data pin of the serial management inter-

f ace. MDATA can be driven by an external master (e.g.,

the microcontroller or southbridge) or by the

Am79C975 controller. The interface protocol defines

exactly at what time Am79C975 has to listen to the

MDATA pin and at what time the controller must drive

the pin (see section Basic Operations fo r more details).

MIRQ

SMIU Interrupt Output

MIRQ is an asynchronous attention signal that the

Am79C975 controller provides to in dicate that a man-

agement frame has been transm itted or rec eived. The

assertion of the MIRQ signal can be controlled by a glo-

bal mask bit (MIRQEN) or individual mask bits

(MRX_DONEM, MTX_DONEM), located in the Com-

mand register. Note that the SMIU interrupt acknowl-

edge does not follow the SMB alert protocol, but simply

requires clearing the interrupt bit.

Basic Operation

Transferring Data

The Serial Management Interface Unit (SMIU) of the

Am79C 975 controll er uses a two pin interface to com-

municate with other devices. MCLOCK is the clock pin.

MDATA is the data pin. Both signals are bussed and

shared with other devices in the system. There is at

least one master device in the system (e.g., a micro-

controller). A master is a device that initiates a transfer

and also provides the clock signal. The Am79C975

controller is always a slave device.

The master starts a data transfer on the serial manage-

ment bus by asserting the START condition. The

STA RT condition is defined a s a HIGH to LOW transi-

tion on MD ATA while MCLOCK is HIGH. Data will follow

with the most significant bit (MSB) of a byte transferred

first. Data can only change during the LOW period of

MCLO CK and m ust be s table on th e MDATA pin duri ng

the HIGH period of MCLOCK. Every byte of data must

be acknowledged by the rec eiving device with the Ac-

knowledge bi t (ACK). ACK is de fined as a LOW pulse

on MDATA that follows the same timing as a regular

data bit. In a write operation, the Am79C975 controller

is the rece iving device an d it must generate ACK. In a

read operation , the master i s the receiving device and

it must generate ACK. An inverted Acknowledge bit

(NACK) is used to signal the transmitting device that

the data transfer should terminate. A data transfer is

ended when the master asserts the STOP condition.

The STOP condition is defined as a LOW to HIGH tran-

sition on MDATA while MCLOCK is HIGH.

Implementation note: The assertion of START forces

the state machine in the decoder logic to look for the

slave address of the A m79 C975 device. The assertion

of STOP forces the st ate machine to reset and to wait

for the assertion of a START condition.

The first byte in ev ery data transfer is the 7-bit address

of the Am79C975 device followed by the Read/Write

bit. The MS B of the 7-bit address i s the first bit o n the

MDATA line. A 0 in the Rea d/Write bit i ndi cates a write

operation from the master to the Am79C975 controller,

a 1 indicates a read operation. The Am79C975 control-

ler does not su ppo rt the General Call addr ess (00 h). It

will ignore the address by not asserting ACK.

Serial Management Interface Unit (SMIU)

Name Pin

Function Type Driver No. of

Pins

MCLOCK SMIU

Clock I/O OD6 1

MDATA SMIU

Data I/O OD6 1

MIRQ SMIU

Interrupt OOD61

Am79C973/Am79C975 247

PRELIMINARY

Figure 70. Standard Data Transfer on the Serial Management Interface

A data transfer that invo lves a change in the direction

data is transf erred is a more complex operation. An e x-

ample is a data write transfer followed by a data read

transfer. After finishing the data write transfer, the mas-

ter must initiate the turn-around of the MDATA line by

asserting a repeated START condition followed b y a re-

peated 7-bit slave address and the READ bit. The

Am79C975 controller will driv e the MCLOCK line low in

order to insert wait states before it starts driving the

read data onto the MD ATA pin., The master acts as the

receiver and must generate ACK. (See section Byte

Read Command or Block Read Command f or more de-

tails).

Figure 71. Data Transfer with Change in Direction (with wait state)

Am79C975 Slave Address

The default value for the 7-bit slave address of the

Am79C975 SMIU is 5Bh. This is the address assigned

for a device from the class Networking Controller by

Phillips. The address v alue can be changed via the EE-

PROM. If bit 7 of EEPROM location 50h is set to 0, the

default slave address will be used. Otherwi se, bits 6-0

of EEPROM l ocation 50h de fine the sl ave addres s for

the SMIU. If a system uses multiple Am79C975 control-

lers, recommended values for the slave address of the

other devices are 58h, 59h and 5Ah.

The I2C specification allows for an unlimited number of

bytes being transferred per data transfer. The SMB

specifi cation def ines a s et of comm ands th at stru ct ure

the data transfers and limit their length. The SMIU of

the Am79C 975 c ontro ller follo ws the S MB spec ific ation

and implements a subset of the commands to allow ac-

cess to the SMIU registers and internal memories.

Write Byte Command

The Write Byte command is used to write 1 byte of data

to an SMIU register. The command starts with the

STA RT condition (S). The next 7 bits a re the slave ad-

dress of the Am79C975 controller , followed by a 0 bit to

indicate a write operation (W). The Am79C975 control-

ler will drive SDATA LOW for 1 bit time to acknowledge

the first byte (A). The next 8 bits specify the address of

the SMIU r egiste r (MRe g) th at is accesse d, f ol low ed b y

another ACK from the Am 79C975 con troller. The third

byte is the wr ite data to th e SMIU regi ster, foll owed by

ACK. The master terminates the transfer with the as-

sertion of the STOP condition (P).

MDATA

MCLOCK

R/W A

ACK

from the receiver

A/A

First Byte of Data

S 12345678912 3 - 8 9 P

Star Condition Stop Condition

7-Bit AddressMSB

0=Write

1 = Read 21510D-B74

MDATA

MCLOCK

Data

Repeated Start Condition

789 S Wait State 12

Data

21510D-B75

76-0

DSlave

Address

D=0: Default address will be used as

slave address

D=1: Bits 6 -0 d efin e t he s lave address

248 Am79C973/Am79C975

PRELIMINARY

Key:

Figure 72. Write Byte Command

Note that the Am79C975 controller does not validate

the register address specified in the Write Byte com-

mand. A Wr ite Byte comman d to a non-existin g regis-

ter, or to register that is read-only, or to one of the

registe rs that re quire a Bl ock Read or Wri te comm and

may cause unexpected reprogramming of an SMIU

Read Byte Command

The Read Byte command is used to read 1 byte of data

from an SMIU register . This command is more complex

compared to the Write Byte command, since it involv es

a change in the direction of the data transfer. The com-

mand starts with the START condition (S). The next 7

bits are the slave address of the Am79C975 controller,

followed by a 0 bit to indicate that the data transfer

starts with a write operation from the master to the

Am79C975 controller (W). The Am79C975 controller

must acknowledge the first byte by driving MDATA LOW

for 1 bit time (A). The next byte specifies the address of

the SMIU r egiste r (MRe g) th at is accesse d, f ol low ed b y

another ACK from the Am79C975 controller. The mas-

ter initiates the tur n-around of the transfer directio n by

asserting a repeated START condition, followed by the

repeated 7-bit slave address. This time, the Read/Write

bit is set to 1 to indicate that the next byte of data is

driven by the Am79C975 controller (R). The

Am79C975 controller acknowledges the transfer and

then drives the one byte of register data onto the

MDATA line. The acknowledge for the register data is

generated by the master, since he is the receiver of the

data. The master generates a NACK (N) to force the

Am79C975 controller to stop driving the MDATA line

since the data transfer consists of only one byte. The

Read Byte command terminates with the assertion of

the STOP condition (P) by the master.

Key:

Figure 73. Read Byte Command

Note: The Am79C9 75 co ntr ol ler doe s not validate the

A Read Byte command to a non-existing register, or to

require a Block Read or Write command will yield un-

defined data.

If the second slave address in the Read Byte Com-

mand is not the one of the Am79C975 controller, the

device will release the MDATA line to generate a NACK.

The master, receiving the NACK, must abort the cycle

by generating a STOP condition.

Block Write Command

The Block Wri te command is used to wr ite data to the

SMIU Transmit Data memory or to the Receive P attern

RAM. The command starts with the START condition

(S). The next 7 bits are the slave address of the

Am79C975 controller, followed by a 0 bit to indicate a

write operation (W). The next byte specifies the ad-

dress of the SMIU register (MReg) that is accessed.

The address of the Receive Pattern RAM Data port

(34) or the address of the Tr ansmit Data port (36) is the

only valid values for the MReg a ddress. Th e third byte

171181811

S Slave Address W A MReg Address A MReg Data AP

Master to Am79C975 controller

Am79C975 controller to Master

1711 8 11711 8 11

S Slave Address W A MReg Address A S Slave Address R A MReg Data N P

Master to Am79C975 controller

Am79C975 controller to Master

Am79C973/Am79C975 249

PRELIMINARY

of the Block Write command specifies the byte count.

The byte count value is ignored by the Am79C975 con-

troller. The device is capable of receiving any amoun t

of data even passed the limit of 32 bytes as defined b y

the SMB specification. Since the Am79C975 controller

is the receiver of all data transfers, it must acknowledge

each byte by driving the MD ATA line LO W for 1 bit time

(A). The master indicates the termination of the Block

Wri te comm and with the ass er ti on of the STOP condi-

tion (P).

Note that the Am79C975 controller does not validate

the regi ster address specified in t he Block Write com-

mand. A Block Write command to a register other than

the Transmit Data port or the Receive Pattern RAM

Data port ma y cause unexpected reprogramming of an

SMIU register . The Am79C975 controller also does not

check the length of the Block Write command. The

master must make sure that the Transmit Data memory

or the Receive Pattern RAM are not written beyond

their respective length.

Key:

Figure 74. Block Write Command

Block Read Command

The Block Read command is used to read data from

the SMIU Receive Data memory. This command is

more complex compared to the Block Write command,

since it involves a change in the direction of the data

transfer . The command starts with the START condition

(S). The next 7 bits are the slave address of the

Am79C975 controller , followed by a 0 bit to indicate that

the data transfer starts with a wr ite operation f rom the

master to the Am79C975 controller (W). The

Am79C975 controller must acknowledge the first byte

by driving MDATA LOW f or 1 bit time (A). The next by te

specifies the address of the SMIU register (MReg) that

is accessed, followed by another ACK from the

Am79C975 controller. The address of the Receive

Data port (40), is the only valid value for the MReg ad-

dress. The master initiates the turn-around of the trans-

fer direc ti on by asserting a r epea ted START condition ,

f ollowed by the repeated 7-bit slav e address. This time,

the Read/Write bit is set to 1 to indicate that the next

bytes of data are driven by the Am79C975 controller

(R). The Am79C975 controller acknowledges the

transfer and then continues driving the MDATA line.

The first byte is the byte count indicating how many

bytes of data will follow. The byte count field will indi-

cate 32 in al l but the last trans acti on, in whi ch the byte

count field will indicate the remaining bytes of the

frame. This time, the ACK is generated by the master,

since he is the receiver of the data. Receive data will

follow. Being the receiver, the master must ACK each

byte by drivi ng the MDATA line LOW for 1 bit time. The

last byte, however, must be followed by a NACK (N) to

force the Am79C975 controller to stop driving the

MDATA line. The Am79C975 device is capable of a

block read past the 32 byte limit that is indicated in the

byte count field. If the host does not assert NACK after

the 32nd byte, the Am79C975 controller will continue

dri ving rece ive data onto the MDATA line unt il the hos t

asserts NACK. If the master runs out of storage space

for the incoming data, he can abort the data transfer

after any byte by asserting NACK. The Block Read

command terminates with the assertion of the STOP

condition (P) by the master.

Note: The Am79C9 75 co ntr ol le r does not validate the

A Block Read command to a register other than the Re-

ceive Data port will yield unexpected data. The master

must al so make sur e to on ly i ssue a B lock Read com-

mand when there is data left in the Receive Data mem-

ory.

17118181

S Slave Address W A MReg Address A Byte Count N A

81 811

Data Byte 1 A….Data Byte NAP

Master to Am79C975 controller

Am79C975 controller to Master

250 Am79C973/Am79C975

PRELIMINARY

If the second slave address in the Block Read Com-

mand is not the one of the Am79C975 controller, the

device will release the MDATA line to generate a NACK.

The mast er, receiving the NACK, must abort the cycl e

by generating a STOP condition.

Key:

Figure 75. Block Read Command

Detailed Functions

Global Enable/Disable

Bit 15 (SMIUEN) in BCR2 is used to enable/disable the

Serial Management Interface Unit in the Am79C975

controlle r. If S MIUEN is set to 0 ( defaul t), the SMIU is

disabled. If SMIUEN is set to 1, the SMIU is enabled.

BCR2 is programmable via the EEPROM.

Identification

The SMIU of the Am79C975 controller provides a com-

prehens ive set of registe rs that allow the identif ication

of the device. ID information includes Vendor ID, De-

vice ID and Revision ID. In addition, the Subsystem

Vendor ID and Subsystem ID allow a system manufac-

turer to differentia te his product f rom a product by an-

other vendor who is also using the Am79C975

controller. All SMIU ID registers are shadow registers

of the respective PCI registers and can be initialized via

the EEPROM (with the exception of the Revision ID).

The host can verify that the registers are correctly ini-

tialized from th e E EP ROM by checking the P VALID bi t

in the SMIU Am79C975 Status register.

Initialization

The SMIU of the Am79C975 controller does not require

any complex initialization in order to transmit or receive

management frames. Only the acknowledgment frame

filter needs to be setup in order to receive incoming

frames (see section Receive Operation later).

The host should check the content of the Transceiver

Status r egist er to make su re the Am79C9 75 con troller

is connected to a network (LINK set to 1), before any

transmit or receive operation is started.

Note that the SMIU is not accessible while the

Am79C 975 contr ol le r is readi ng the cont ent of the EE-

PROM after H_R ESET (for ~ 1.7 ms). The device will

not dr ive the Acknowledge bit dur ing that time and th e

access by the master will time-out.

SMIU Bus Frequency

The SMIU o perating frequenc y is set by programming

BCR2 register bits. The equation for SMIU bus fre-

quency i s FI2C = 250 0/( M+ 1)*2 N+1 kHz , assu ming tha t

a 25 MHz crys tal has been used . The maximum value

of M is F (Hex) and N is 7 (Hex). With different comb i-

nation s of M and N, the SM IU bus frequen cy can vary

from 0.5 kHz to 1.25 MH z. It should be noted that th e

frequencies that can be programmed through BCR2

are not continuous. For example, say FI2C = 10 kHz,

then (M+1 )*2N+1 = 250. It is impo ssib le to have su ch M

and N combinations that make an exact 250. With

M = E (Hex) and N = 3 (Hex), we get FI2C = 10.41,

which will work with a 10 kHz bus frequency. The fol-

lowing is a li st of BCR2 co nten ts for various SM IU bus

frequencies.

1711 8 11711

SSlave AddressWA MReg Address A S Slave Address R A

8181 811

Byte Count N AData Byte 1A…. Data Byte N N P

Master to Am79C975 controller

Am79C975 controller to Master

BCR2 (Hex) FI2C (kHz)

A643 10

A463 13

A642 20

A422 30

A641 40

A461 50

A202 60

A640 80

A460 100

Am79C973/Am79C975 251

PRELIMINARY

Notes:

1. Bit 15 and 13 are default 1.

2. M = bit (10, 9, 6, 5) and N = bit (4, 1, 0).

3. Similarly, other FI2C can be programmed with proper

combinations of M and N.

BCR2 Register Bits for setting SMIU Frequency

The frequency at which the SMIU will operate is calcu-

lated using the following expression: FI2C = 2500/

(M+1)*2N+1 kHz.

Where: FI2C is the desired frequency (10-100 kHz)

M is the value stored in bits D3-D6

N is the value stored in bits D0-D2.

Status

The SMIU of the Am79C975 controller provides two

registers to determine the status of the device.

The Am79 C975 Status regis ter indicates the status of

the current power state of the device (D0-D3). The

power state its elf h as no affect on the operatio n of th e

SMIU. The management interface will operate in any

power state, as long as power is provided, i.e. opera-

tion in D3cold is not possible.

The Am79 C975 Status re gister also in dicates the s ta-

tus of the nor ma l operation of the device. The register

contains bits to i ndica ted if the contr oller i s stopped or

started and if the transceiv er and receiver are enabled.

The Transceiver Status reg ister provides the status of

the physical layer interface that is integrated into the

Am79C975 controller. The host can read this register to

determine if the controller is connected to an active net-

work (LINK set to 1), the speed of the connection (100

Mbps: SPEED=1, 10 Mbps: SPEED=0) and if the con-

nection is half dupl ex (DUPLEX= 0) or full du plex (DU-

PLEX=1). In most cases, the transceiver will be

configured using the autonegotiation process.

A UT ONEG_DONE will be set to ONE, when autonego-

tiation with the other end of the network cable has com-

pleted. LINK, SPEED and DUPLEX reflect the result of

the autonegotiation process. If AUTONEG_DONE is

ZERO, the LINK, SPEE D and DULPE X bits refle ct the

status of a manual transceiver configuration.

Transmit Operation

The S ystem M ana gem ent Int er face Unit ( SMI U) of th e

Am79C975 controller provides a separate 128-byte

Transmit Data memory to setup a management or alert

frame for transmission. The host must load the frame

byte by byte using one or multiple Block Write com-

mands to the Tran smit Data por t. The c ommand code

of the Block Write command must be set to 36, the ad-

dress of the Transmit Data port. The byte count field

can have any value since it is ignored by the

Am79C 975 co ntr oller. The device is capable of rec ei v-

ing any amount of transmi t data even passed the li mit

of 32 bytes as defined by the SMB specification. The lo-

cation within the Transmit Data memory where the next

byte is written to is controlled by the SMIU Transmit Ad-

dress register (MTX_ADR). This register will come up

cleared t o 0 after H_R ESET. With every byte wr ite th e

address register will auto-increment. This allows a

FIFO-type access to the Transmit Data memory and

the host does not need to keep track of the location he

is wr iting to. In addition, MTX_ADR can be set to any

address within the Transmit Data memory in order to

modify a specific location. The host must load all frame

information starting from the destination address and

ending with the last byte of data. The FCS is automati-

cally ap pended by the Am79C9 75 contro ller. The host

must load at least 60 bytes to the Transmit Data m em-

or y in order to create a legal length frame. Paddi ng is

not supported by the SMIU. The setting of the

APAD_XMT bit in CSR4 only effects the transmission

of normal frames and not of management frames.

The SMI U provides a set of regi sters that contai n net-

work address information. The address information can

be used to setup the alert frame. The six Node IEEE

Addres s r egisters co nta in the unique 48-bi t add ress of

the station, the Am79C975 controller is used in. The

four Node IP Address registers contain the 32-bit IP ad-

dress of that station. The six Management Station

IEEE Address registers contain the unique 48-bit ad-

dress of the station that is used as the management

console in the ne twork. The four Management Sta tion

IP Address registers contain the 32-bit IP address of

the management console. All 3 sets of registers are

loaded from the EEPROM. The Node IP Address, Man-

agement IE EE Address and Manageme nt IP Address

registers can also be used as general purpose regis-

ters to load information stored in the EEPROM and

make it accessible via the serial management interface

to the external host.

The host must setup the Transmit Message Length reg-

ister (MTX_LEN) with the number of bytes loaded to

the Transmi t Dat a mem ory so that t he MA C kno ws ho w

many bytes to transmit. The host is responsible to load

a valid value into the Transmit Message Length regis-

ter. A ny value below 60 will create a r unt frame on the

BCR2 (Bit No.) Name Po sition

10 I2C_M3 D6

9I2C_M2D5

6I2C_M1D4

5I2C_M0D3

4 I2C_N2 D2

1 I2C_N1 D1

0 I2C_N0 D0

252 Am79C973/Am79C975

PRELIMINARY

network. Any value above 128 will create unpredictable

results. Padding is not supported by the SMIU.

Once the Transmit Data memor y is filled wi th the data

of the alert frame and the Transmit Message Length

registe r is setup with the length of the ale rt frame, the

host must set th e M TX_S TART bit in the Transmit S ta-

tus register to star t the transmission. The Am79C975

controller will transmit the alert frame after any pending

frame transmission (including retries) has completed.

The host can poll the MTX_DONE bit in the Interrupt

frame has already ended. The MTX_DONE bit will be

set to a 1 after the end of transmission, independent of

the su ccess of the op eration. The MT X_DONE bit will

auto-clear after reading the Interrupt register.

The MTX_ADR register is cleared by setting the

MTX_START bit. The host must not load data for a ne w

alert frame into the Transmit Data memory until the

transmission of the current frame is ended as indicated

by the MTX_DONE bit. It is possible to issue a new

MTX_START command without loading new data to

the Transmit Data memor y or updating the MTX_LEN

The Am79C975 controller provides an asynchronous

interr upt pin to signa l the host that the transmi ssion of

the aler t frame is comp lete. After the end of the trans-

mission, the MIRQ pin will be asserted, if the global in-

terrupt enable bit MIRQEN in the Command register is

set to a 1 and the transmit interrupt mask bit

(MTX_DONEM) is cleared to 0 (default state). Once

MIRQ is asser ted, the host can read the MTX_DONE

bit in the Interr upt register to d etermine that the inter-

rupt was caused by the end of the transmission. The

read of the Interrupt register will clear the MTX_DONE

bit and cause the deassertion of the MIRQ pin. The In-

terrupt register also provides a global interrupt bit

MIRQ that is the OR of the MTX_DONE and

MRX_DONE bits.

Once the MTX_DONE bit indicates that the transmis-

sion of the alert frame has ended, MTX_START is

cleared and the SMIU T ransmit Status register provides

the error status for the transmission. Three error condi-

tions are reported: Late Collision, Loss of Carrier and

Retry Error. There is also an error summary bit

(MTX_ERR). The transmit status bits remain valid as

long as the MTX_START bit is set to 0.

The Transmit Retr y Er ror c onditi on re qui res specia l at-

tention. It can happen, that the START or STOP bit is

set in the Am79C975 controller to change normal oper-

ation. START and STOP caus e a reset of the trans mit

logic. Normal transmission of an alert frame will suc-

ceed. If, howe ver , the SMIU is in the middle of a backoff

interval or the trans mis sion of the al ert frame is suffer-

ing a collision, the transmission will abort and the

MTX_RTRY bit will be set. If MTX_RTRY is set in the

SMIU Transmit Status register, the host should re-

transmit the frame.

Receive Operation

The S ystem M ana gem ent Int er face Unit ( SMI U) of th e

Am79C975 controller provides a separate 128-byte

Receive Data memory to store an incoming manage-

ment or acknowledgment frame. The normal receive

address matching mechanism (physical address, logi-

cal address, broadcast address) of the MAC cannot be

used by the SM IU. The Am7 9C97 5 co n troll er p rovides

an Acknowledgment Frame Filter instead. The filter is

stored in a 40-byte Receive Pattern RAM.

The Receive Pattern RAM is organized as 8 pattern

words of 5 bytes each. Each pattern word holds four

bytes of data to be c ompared with th e incomi ng fram e

plus mask information that indicates which bytes

should be included in the comparison. The pattern

word also contains a field that indicates how many

Dwords of the incoming frame should be skipped be-

fore this Dword of pattern is compared with frame data.

This field makes it unnecessary to store data for long

ser ies of bytes that will be excluded from the co mpar i-

son anywa y. A maximum of 7 Dwords (28 bytes) can be

skipped. If the filter pattern contains a string of more

than 7 Dw ords that mus t be e x clude d from the c ompa r-

ison, one or more pattern words will be loaded with the

valu e 7h in the Skip field a nd 0h in the Mask fiel d. Fi-

nally the most significant bit of the pattern word indi-

cates whet her or not this word is the end of the store d

pattern.

The format of the pattern words is shown below.

Bits Name Description

31:0 Pattern Bytes of data to be compared with the incoming frame. The least significant byte corresponds to the

first byte of the Dword received from the network.

35:32 Mask Bits 3:0 of this field correspond to bytes 3:0 of the pattern field. If bit n of this field is 0, byte n of the

pattern is ignored in the comparison.

38:36 Skip This field in dicates ho w man y Dwords of the inc oming fra me must be skipped before the pattern in this

word is compared with data from the incoming frame. A maximum of 7 Dwords may be skipped per

pattern word.

39 EOP End of Pattern. If this bit is set, this pattern word contains the last Dword of the frame filter.

Am79C973/Am79C975 253

PRELIMINARY

The host must load the Receive Pattern RAM using

one or mul tiple Bl ock Write commands to the Re ceive

Pattern RAM Data port. The command code of the

Block Write command must be set to 34, the address

of the Receive Pattern RAM Data po rt. The byte count

field can have any value since it is ignored by the

Am79C9 75 controll er. The device i s c ap able of r ec eiv -

ing any amount of frame filter bytes even passed the

limit of 32 bytes as defined by the SMB specification.

The location within the Receive P attern RAM where the

next by te i s writte n to is contr ol led by the Rec eive Pat-

tern RAM Address register (MRX_PADR). This register

will come up cleared to 0 after H_RESET. With every

byte write the address register will auto-increment. This

allows a FIFO-type access to the Receive P attern RAM

and the host does not need to keep track of the location

he is wr iting to. In addit ion, MRX_PADR can be set to

any address within the Receive Pattern RAM in order

to modify a specific location. The sequence the Re-

ceive Patt er n RAM must be wr itten is LS B (bits 7 :0) of

the first patter n word, followed by bits 15:8 of the first

patter n word. The first pattern word is followed by the

second pattern word. The host need not write all 8 pat-

tern words. The last patter n word must have the EOP

bit set, even if the pattern word number 8 is the last

one. W ords following the EOP bit are ignored. The host

must make sure that no more than 40 bytes are written

to the Receive Pattern RAM. When MRX_ENABLE is

set to 1, the MRX_PADR register will clear to 0 and no

write to the Receive P attern RAM ma y occur . A new ac-

knowledgment frame filter can be written to the Re-

ceive Pattern RAM after disabling the receiver by

setting MRX_ENABLE to 0.

The table below shows how a sample pattern would be

stored in th e Receive Patter n RAM. Note that i n the 4

columns containing the frame data, the byte in the left-

most column is closer to the start of the frame than the

byte in the rightmost column. The 4 columns showing

patter n data stored in the RAM show the least signifi-

cant byte of the RAM word in the rightmost column.

Once the acknowledgment frame filter has been loaded

to the Receive Pattern RAM, the host must set the

MRX_ENABLE bit in the Receive Status register to en-

able the reception of acknowledgment frames.

When an in co mi ng frame pass es the acknowledg men t

frame filter, the Am79C975 controller will store the

frame data in the Receive Data memor y. Runt frames

(frames shorter than 64 bytes) are automatically de-

leted, unless MRX_RPA (bit 2 in the SMIU Command

than 128 bytes (including FCS), the Am79C975 con-

troller will only store the first 128 bytes and discard the

rest. A message length between 129 and 132 bytes in-

dicates that only FCS bytes have been lost and all mes-

sage data bytes are available in the Receive Data

memory. A m es sag e le ngt h greater than 132 i ndi cates

that message data bytes have been lost from the en d

of the message. The Receive Message Length register

(MRX_LEN) will indicate the correct message length

up to 255 bytes. It wil l freeze at 25 5 for longer frames.

P ad stripping is not supported by the SMIU . The setting

of the ASTRP_RCV bit in CSR4 only effects the recep-

tion of normal frames and not of acknowledgment

frames. Note that if the main receiver of the Am79C975

device is enabled, the acknowledgment frame will also

be passed up to the network driver and from there to

the protocol stack. The frame format of the acknowl-

edgmen t frame s hou ld be des ign ed s uch t hat it wi ll b e

identifi ed by the protoc ol sta ck as a sp ecia l f rame and

thrown aw a y. There will be no real performance impact

Frame

Offset Offset +

0Offset +

1Offset +

2Offset +

3RAM

Word EOP Skip Mask Pattern

0 00 00 1A 00 1 0 0 1111 00 1A 00 00

4 E0 1B xx xx 2 0 0 0011 xx xx 1B E0

8 xxxxxxxx

12 08 06 xx xx 3 0 1 0011 xx xx 06 08

16 xx xx xx xx

20 xx 01 xx xx 4 0 1 0010 xx xx 01 xx

24 xx xx xx xx

28 xx xx xx xx

32 xx xx xx xx

36 xx xx 9d 37 5 0 3 1100 37 9d xx xx

40 c7 48 xx xx 6 1 0 0011 xx xx 48 c7

254 Am79C973/Am79C975

PRELIMINARY

since the frequency of the acknowledgment frames is

very low.

Once the receive activity has ended, the Am79C975

controller will set the MRX_DONE bit in the Interrupt

Status register. The MIRQ pin will be asserted, if the

global interrupt enable bit MIRQEN in the Command

registe r is set to a 1 and the re ceive interr upt m ask bi t

(MRX_DONEM) is cleared to 0 (default state). Once

MIRQ is asserted, the host can read the MRX_DONE

bit in the Interr upt register to d etermine that the inter-

rupt was cause d by the end of the reception. The read

of the Interr upt register will clear the MRX_DONE bit

and cause the deassertion of the MIRQ pin. The Inter-

rupt register also provides a global interrupt bit MIRQ

that is the OR of the MRX_DONE and MTX_DONE

bits.

Once the MRX_DONE bit indicates that the recep tion

of the acknowledgme nt frame h as ende d, the Re ceive

Status register provides the error status for the recep-

tion. Two error conditions are reported: Framing Error

and Frame Check Sequence Error. There is also an

error summary bit (MRX_ERR). The receive status bits

remain valid as lon g as th e MRX _EN AB LE bit is set t o

0. The host has the option to discard an erroneous

frame by simply not reading the receive data and un-

protecting the Receive Data memory by setting the

MRX_ ENABLE bit.

The host must read the Receive Message Length reg-

ister in order to dete r m in e the len gth of the frame. The

data from the Receive Data memory is read byte by

byte using one or multiple Block Read commands from

the Receive Data port. The command code of the Block

Read co mmand must be set to 40, the add ress of the

Receive Data por t. The Am 79C975 control ler will indi-

cate in the byte count field the number of bytes that will

f ollow. The byte count field will indicate 32 in all but the

last transaction in which the byte count field will indi-

cate the remaining bytes of the frame. The de vice is ca-

pable of transferring data beyond the 32 byte mark. If

the host does not assert NACK after the 32nd byte, the

Am79C975 controller will continue driving receive data

onto the MD ATA line until the host asserts NA CK. If the

master does not have enou gh buffer space for the in-

coming data, it can abort the data transfer after any

byte . The Am79C975 controller will start the ne xt Block

Read co mmand with the rema ining data. Th e location

within the Rece ive D ata memor y from where the next

byte is read is controlled by the Receive Address regis-

ter. This register will come up cleared to 0 after

H_RESET. With every byte read the address register

will auto-in crement. Th is all ows a FIF O-ty pe acces s to

the Receive Data memory and the host does not need

to keep track of the location he is reading from. In addi-

tion, MRX_ADR can be set to any address within the

Receive Data memory in order to read a specific loca-

tion or to star t the receive data read from an arbitrar y

address inside the Receive Data memory. Note, that

the byte count field in the Block Read command will

only reflect the correct amount of transfer data if the ac-

cess starts at Receive Data memory address 0. If

MRX_ADR is manually changed, the byte count field

should be ignored. The host must use the Receive

Message Length register (MRX_LEN) to determine the

length of the data read operation. Data will be unde-

fined, if the host reads fur ther than the Receive Mes-

sage Length register is indicating.

The Receive Data memory will be protected from ov er-

writing by another frame, until the host enables the next

receive by setting the MRX_ENABLE bit the Receive

Status register. The operation will also clear the Re-

ceive Address register.

Loopback Operation

The SMIU provides a looback mode f or diagnostic pur-

poses. If M LOOP i n the Comman d regis ter is set to 1 ,

the receive path is not being blocked while the device

is transmitting in half-duplex mode. Receive is never

blocked in full-dupl ex mode and MLOOP has no effect

in this mode.

For loopback operation, transmit data must be sent

back to the receiver. This is done at the transc eiver by

either using an extern al loopb ack connector or by pro-

gramming the transceiver for loopback mode. The pro-

gramming must be done using the Am79C975 CSR/

BCR register interface. This limits the SMIU loopback

mode to a debug or manufacturing test environment.

User Accessible Registers

The Serial Management Interface Unit (SMIU) of the

Am79C975 controller provides four types of user ac-

cessible registers: device ID registers, node address

registers, device status registers and control and status

registers. Most registers are accessible via the Read

Byte and/or Write By te c omm and s. Only t he access to

the Transmit and Receive Data port as well as to the

Receive Pattern RAM Data port is performed as a

Block Read or Block Write command. In all commands,

the command code is interpreted as the address of the

Device ID Registers

The following reg ist er al low the uniqu e i den tifi c ati on o f

the Am79C975 device in a system.

SMIU Vendor ID Register 0 (MReg Address 0)

This register is a shadow register of the PCI Vendor ID

from the EEPROM.

Bit No. Name and Description

7:0 MVENDOR_ID[7:0]

Am79C973/Am79C975 255

PRELIMINARY

Default: 22h Re ad only, wri te has no effect.

These are the lower 8-bits of a register that

identifies AMD as the manufacturer of the

Am79C9 75 devic e.

SMIU Vendor ID Register 1 (MReg Address 1)

This register is a shadow register of the PCI Vendor ID

loaded from the EEPROM.

Bit No. Name and Description

7:0 MVENDOR_ID[15:8]

Default: 10h Re ad only, wri te has no effect.

These are the upper 8-bits of a register that

identifies AMD as the manufacturer of the

Am79C9 75 devic e.

SMIU Device ID Register 0 (MReg Address 2)

This register is a shadow register of the PCI Device ID

Bit No. Name and Description

7:0 MDEVICE_ID[7:0]

Default: 00h Re ad only, wri te has no effect.

These are the lower 8-bits of a register that

identifie s the Am79C975 device within AMD’s

product line.

SMIU Device ID Register 1 (MReg Address 3)

This register is a shadow register of the PCI Device ID

Bit No. Name and Description

7:0 MDEVICE_ID[15:8]

Default: 20h Re ad only, wri te has no effect

These are the upper 8-bits of a register that

identifie s the Am79C975 device within AMD’s

product line.

SMIU Revision ID Register (MReg Address 4)

This register is a shadow register of the PCI Revision

ID Register.

Bit No. Name and Description

7:0 MREVISION_ID

Default: 40h Re ad only, wri te has no effect

This 8-bit register specifies the Am79C975

controller revision number. The upper 4 bits of

the register value are fixed to 4h, the lower four

bits are silicon-revision dependent. The initial

revision value will be 40h.

SMIU Subsystem Vendor ID Register 0 (MReg

Address 5)

This register is a shadow register of the PCI Subsystem

Vend or ID Regis ter bits 7: 0. The PCI S ubsystem Ven-

dor ID Register is loaded from the EEPROM.

Bit No. Name and Description

7:0 MSUBVEN_ID[7:0]Default: 00hRead only,

write has no effect

These are the lower 8-bits of a register that to-

gether with the Su bsystem I D uniquel y identi-

fies the add-in card or subsystem the

Am79C 975 dev ice is used in.

SMIU Subsystem Vendor ID Register 1 (MReg

Address 6)

This register is a shadow register of the PCI Subsystem

Vendor ID Register bits 15:8. The PCI Subsystem Ven-

dor ID Register is loaded from the EEPROM.

Bit No. Name and Description

7:0 MSUBVEN_ID[15:8]

Default: 00h Read only, write has no effect

These are the upper 8-bits of a register that to-

gether with the Su bsystem I D uniquel y identi-

fies the add-in card or subsystem the

Am79C 975 dev ice is used in.

SMIU Subsystem ID Register 0 (MReg Address 7)

This register is a shadow register of the PCI Subsystem

ID Register bits 7:0. The PCI Subsystem ID Register is

loaded from the EEPROM.

Bit No. Name and Description

7:0 MSUBSYS_ID[7:0]Default: 00hRead only,

write has no effect

These are the lower 8-bits of a register that to-

gether with the Subsystem Vendor ID uniquely

identifies the add-in card or subsystem the

Am79C 975 dev ice is used in.

SMIU Subsystem ID Register 1 (MReg Address 8)

This register is a shadow register of the PCI Subsystem

Vendor ID Register bits 15:8. The PCI Subsystem ID

Bit No. Name and Description

7:0 MSUBSYS_ID[15:8]

Default: 00h Read only, write has no effect.

256 Am79C973/Am79C975

PRELIMINARY

These are the upper 8-bits of a register that to-

gether with the Subsystem Vendor ID uniquely

identifies the add-in card or subsystem the

Am79C975 device is used in.

Node ID Registers

The following registers provide the IEEE and IP ad-

dresse s of the node usi ng the Am79C975 d evi ces, as

well as of the management station.

Node IEEE Address 0 (MReg Addr ess 9)

This regi ster is a sh adow register of the AP ROM loca-

tion 00h . APROM locatio n 00h is loaded from the EE-

PROM.

Bit No. Name and Description

7:0 N_IEEE_ADR[7:0]

Default: 00h Re ad only, wri te has no effect.

Byte 0 (the LSB) of the Node IEEE Address

48-bit address of the station, the Am79C975

controller is used in.

Node IEEE Address 1 (MReg Addr ess 10)

This regi ster is a sh adow register of the AP ROM loca-

tion 01h . APROM locatio n 01h is loaded from the EE-

PROM.

Bit No. Name and Description

7:0 N_IEEE_ADR[15:8]

Default: 00h Re ad only, wri te has no effect.

Byte 1 of the Node IEEE Address register. The

Node IEEE Address is the unique 48-bit ad-

dress of the station, the Am79C975 controller

is used in.

Node IEEE Address 2 (MReg Addr ess 11)

This regi ster is a sh adow register of the AP ROM loca-

tion 02h . APROM locatio n 02h is loaded from the EE-

PROM.

Bit No. Name and Description

7:0 N_IEEE_ADR[23:16]

Default: 00h Re ad only, wri te has no effect.

Byte 2 of the Node IEEE Address register. The

Node IEEE Address is the unique 48-bit ad-

dress of the station, the Am79C975 controller

is used in.

Node IEEE Address 3 (MReg Address 12)

This regi ster is a shadow register of th e APROM loc a-

tion 03h. AP ROM location 03 h is loaded from the E E-

PROM.

Bit No. Name and Description

7:0 N_IEEE_ADR[31:24]

Default: 00h Read only, write has no effect.

Byte 3 of the Node IEEE Address register. The

Node IEEE Address is the unique 48-bit ad-

dress of the sta tion, the A m79C975 con troller

is used in.

Node IEEE Address 4 (MReg Address 13)

This regi ster is a shadow register of th e APROM loc a-

tion 04h. AP ROM location 04 h is loaded from the E E-

PROM.

Bit No. Name and Description

7:0 N_IEEE_ADR[39:32]

Default: 00h Read only, write has no effect.

Byte 4 of the Node IEEE Address register. The

Node IEEE Address is the unique 48-bit ad-

dress of the sta tion, the A m79C975 con troller

is used in.

Node IEEE Address 5 (MReg Address 14)

This regi ster is a shadow register of th e APROM loc a-

tion 05h. AP ROM location 05 h is loaded from the E E-

PROM.

Bit No. Name and Description

7:0 N_IEEE_ADR[47:40]

Default: 00h Read only, write has no effect.

Byte 5 (the MSB) of the Node IEEE Address

48-bit address of the station, the Am79C975

control ler is used in.

Node IP Address 0 (MReg Address 15)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 N_IP_ADR[7:0]Default: 00hRead only, write

has no effect.

Byte 0 (the LSB) of the Node IP Address regis-

ter. The Node IP Address is the 32-bit address

used i n the IP p rotocol header to a ddress the

station, the Am79C975 controller is used in.

This regi ste r can al so be us ed as gene ral pur -

Am79C973/Am79C975 257

PRELIMINARY

pose 8-b it register tha t is loade d from the EE-

PROM.

Node IP Address 1 (MReg Address 16)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 N_IP_ADR[15:8]

Default: 00h Re ad only, wri te has no effect.

Byte 1 of the Node IP Address register. The

Node IP Ad dres s is the 32 -b it ad dres s us ed i n

the IP protocol header to address the stat ion,

the Am 79C975 controll er is used in. Th is reg-

ister can also be used as general purpose 8-bit

Node IP Address 2 (MReg Address 17)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 N_IP_ADR[23:16]

Default: 00h Re ad only, wri te has no effect.

Byte 2 of the Node IP Address register. The

Node IP Ad dres s is the 32 -b it ad dres s us ed i n

the IP protocol header to address the stat ion,

the Am 79C975 controll er is used in. Th is reg-

ister can also be used as general purpose 8-bit

Management Station IP Address 3 (MReg Address

18)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 N_IP_ADR[31:24]

Default: 00h Re ad only, wri te has no effect.

Byte 3 ( the MSB ) of t he No de IP Addres s reg-

ister. The Node IP Address is the 32-bit ad-

dress used in the IP protocol header to

address the station, the Am79C975 controller

is used in. This register can also be used as

general purpose 8-bit register that is loaded

from the EEPROM.

Management St ation IEEE Address 0 (MReg

Address 19)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IEEE_ADR[7:0]Default: 00hRead only,

write has no effect.

Byte 0 (the LSB) of the Management Station

IEEE Add r ess r egi s ter. T he M anag em ent S ta-

tion IEEE Address is the unique 48-bit address

of the stat ion tha t is used as the manage ment

console in the network. This regist er can also

be used as ge neral purpose 8- bit registe r that

is loaded from the EEPROM.

Management Station IEEE Address 1 (MReg

Address 20)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IEEE_ADR[15:8]

Default: 00h Read only, write has no effect.

Byte 1 of the Management Station IEEE Ad-

dress register. The Management Station IEEE

Address is the unique 48-bit address of the

station that is used as the management con-

sole in the network. This register can also be

used as general purpose 8-bit register that is

loaded from the EEPROM.

Management Station IEEE Address 2 (MReg

Address 21)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IEEE_ADR[23:16]

Default: 00h Read only, write has no effect.

Byte 2 of the Management Station IEEE Ad-

dress register. The Management Station IEEE

Address is the unique 48-bit address of the

station that is used as the management con-

sole in the network. This register can also be

used as general purpose 8-bit register that is

loaded from the EEPROM.

Management Station IEEE Address 3 (MReg

Address 22)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IEEE_ADR[31:24]

Default: 00h Read only, write has no effect.

Byte 3 of the Management Station IEEE Ad-

dress register. The Management Station IEEE

Address is the unique 48-bit address of the

station that is used as the management con-

sole in the network. This register can also be

used as general purpose 8-bit register that is

loaded from the EEPROM.

258 Am79C973/Am79C975

PRELIMINARY

Management St ation IEEE Address 4 (MReg

Address 23)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IEEE_ADR[39:32]

Default: 00h Re ad only, wri te has no effect.

Byte 4 of the Management Station IEEE Ad-

dress register. The Management Station IEEE

Address is the unique 48-bit address of the

station that is used as the management con-

sole in the network. This register can also be

used as general purpose 8-bit register that is

loaded from the EEPROM.

Management St ation IEEE Address 5 (MReg

Address 24)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IEEE_ADR[47:40]

Default: 00h Re ad only, wri te has no effect.

Byte 5 (the MSB) of the Management Station

IEEE Add re ss r egister. The Ma nag ement Sta-

tion IEEE Address is the unique 48-bit address

of the stat ion that is used as th e manage ment

console in the network. This register can also

be used as ge neral purpose 8- bit registe r that

is loaded from the EEPROM.

Management Station IP Address 0 (MReg Address

25)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IP_ADR[7:0]

Default: 00h Re ad only, wri te has no effect.

Byte 0 (the LSB) of the Management Station IP

Addres s regis ter. The M anageme nt Stati on IP

Address is the 32-bit address used in the IP

protocol header to address the station that

functions as the management console in the

network. This register can also be used as

general purpose 8-bit register that is loaded

from the EEPROM.

Management Station IP Address 1 (MReg Address

26)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IP_ADR[15:8]

Default: 00h Read only, write has no effect.

Byte 1 o f th e Managem ent Sta t io n I P A dd ress

regist er. The Ma nagemen t Stat ion IP Address

is the 32-bit address used in the IP protocol

header to address the station that functions as

the manage ment cons ole in the net work. This

8-bit register that is loaded from the EEPROM.

Management Station IP Address 2 (MReg Address

27)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IP_ADR[23:16]

Default: 00h Read only, write has no effect.

Byte 2 o f th e Managem ent Sta t io n I P A dd ress

regist er. The Ma nagemen t Stat ion IP Address

is the 32-bit address used in the IP protocol

header to address the station that functions as

the manage ment cons ole in the net work. This

8-bit register that is loaded from the EEPROM.

Management Station IP Address 3 (MReg Address

28)

This register is loaded from the EEPROM.

Bit No. Name and Description

7:0 M_IP_ADR[31:24]

Default: 00hRead only, write has no effect.

Byte 3 (the MSB) of the Management Station

IP Address register. The Management Station

IP Address is the 32-bit address used in the IP

protocol header to address the station that

functions as the management console in the

network. This register can also be used as

general purpose 8-bit register that is loaded

from the EEPROM .

Device Status Registers

The following registers allow to determine the status of

the Am79C975 device as it relates to the normal mode

of operation (i.e. not relate d to the Serial Ma nage men t

Am79C 975 Unit ).

SMIU Am79C975 Status (MReg Address 29)

This register is a shadow register of some bits in CSR0,

BCR19 and some bits in the PCI PCMCSR register.

Bit No. Name and Description

7:6 POWERSTATE

Am79C973/Am79C975 259

PRELIMINARY

Default: 00 Read only, write has no effect.

This two bit field indicates the current power

state of the Am79C975 controller. The defini-

tion of the field values is given below:

00b - D0

01b - D1

10b - D2

11b - D3

5 RESERVED Default: 0Read as ZERO only

Reserved bits. For future use only

4 PVALID Default: 0Read only, write has no

effect.

When PVALID is set to a 1, it indicates that

there is an EEPROM connected to the

Am79C975 controller and that the read opera-

tion of the EEPROM has passed the checksum

verification. All registers that are loaded from

the EEPROM contain data read from the EE-

PROM. PVALID is cleared by H_RESET.

3RXON

Default: 0 Read only, write has no effect.

When RXO N is set to a 1, i t indicat es that the

receive function for normal operation is en-

abled. Note th at the r ec ep tio n of man age men t

frames via the SMIU is only controlled by the

MRX_ENABLE bit in the Receive Status regis-

ter, but not of the state of RXON. RXON is

cleared by H_RESET.

2TXON

Default: 0 Read only, write has no effect.

When TX ON is set to a 1, it indi cates that the

transmit function for normal operation is en-

abled. Note that the transmission of manage-

ment frames via the SMIU is always active,

independent of the state of TXON. TXON is

cleared by H_RESET.

1STOP

Default: 1 Read only, write has no effect.

When STOP is set to a 1, it indicates that all

bus master activity of the Am79C975 controller

is disabled. STOP is set to 1 by H_RESET.

0STRT

Default: 0 Read only, write has no effect.

When STRT is set to a 1, it indicates that the

Am79C975 controller is initialized for normal

mode of operation and that the device is setup

to perform bus master activity. STRT is cleared

by H_RESET.

MIU Transceiver Status (MReg Address 30)

This register is a shadow register of some bits in the

transceiver status register.

Bit No. Name and Description

7:4 RESERVED

Default: 0000Re ad as Z ERO only

Reserved bits. For future use only

3LINK

Default: 0 Read only, write has no effect.

When LINK is set to 1, it indicates that the

physical layer interface of the Am79C975 con-

troller is in Link Pass state. A value of 0 indi-

cates a Link Fail state.

2 DUPLEX

Default: 0 Read only, write has no effect.

When DULPEX is set to 1, it indicates that the

physical layer interfa ce is operating in full-du-

plex mode. A value of 0 indicates half-duplex

mode.

1 SPEED

Default: 0 Read only, write has no effect.

When SPEED is set to 1, it indicates that the

physical layer interface is operating at 100

Mbps. A value of 0 indicates a speed of 10

Mbps.

0 AUTONEG_DONEDefault: 0Read only, write

has no effect.

When AUTONEG_DONE is set to 1, it indi-

cates that the autonegotiation process of the

physical layer interface with the other end of

the network cable has completed.

Control and Status Registers

The following registers control the transmission and re-

ception of management frames and provide status of

the operation.

260 Am79C973/Am79C975

PRELIMINARY

SMIU Command Register (MReg Address 31)

Bit No. Name and Description

7MIRQEN

Default: 0 Read/Write

MIRQEN allows the MIRQ pin to be active if

the interrupt flag MIRQ in the SMIU Interrupt

MIRQ pin will be disabled regardless of the

state of MIRQ. MRIRQEN is cleared by

H_RESET.

6MTX_DONEM

Default: 0 Read/Write

If MTX_DONEM is set to a 1, the MTX_DONE

bit in the SMIU Interrupt register will be

masked and unable to set the MIRQ bit.

MTX_DONEM is cleared by H_RESET.

5MRX_DONEM

Default: 0 Read/Write

If MRX_DONEM is set to a 1, the MRX_DONE

bit in the SMIU Interrupt register will be

masked and unable to set the MIRQ bit.

MRX_DONEM is cleared by H_RESET.

4 RESERVED

Default: 0 Read/Write as ZERO only

Reserved bit. For future use only

3 MLOOP

Default: 0 Read/Write

If MLOOP is set to 0, transmit frames will be

blocked fr om be ing r ec ei ved b ac k, in case th e

transceiver loops back the data. Setting

MLOOP to 1 enab les l oo pbac k mo de. Al l dat a

that is tr ansmitted wil l be receiv ed back, if th e

transceiver loop backs the data and the data

passes the acknowledgment frame filter. The

transceiv er loopbac k can be achieve d by pro-

gramming the device into loopback mode or by

using an external loopback connector. MLOOP

has no effect. , when the Am79 C975 con troller

is configured for full-duplex operation. Re-

ceives are never blocked in full-dup lex mode.

MLOOP is cleared by H_RESET.

2MRX_RPA

Default: 0 Read/Write

When MR X_R PA is set to a 1, the Am7 9C97 5

controller will accept runt frames (frames

shorter t han 64 bytes) tha t pass the acknowl-

edgment frame filte r. MRX_RPA i s cleare d by

H_RESET.

1:0 RESERVED

Default: 00 Read/Write as ZERO only

Reserved bits. For future use only

SMIU Interrupt Register (MReg Address 32)

Bit No. Name and Description

7MIRQ

Default: 0 Read clear, write has no effect.

MIRQ indi cates tha t one of t he foll owing i nter-

rupt causing conditions has occurred:

MTX_DONE or MRX_DONE and the associat-

ed mask b it is programm ed to allow the event

to caus e an in ter rupt. If the MIRQ EN b it in th e

SMIU Command register is set to 1 and MIRQ

is set, the MIRQ pin will be active. MIRQ is

cleare d by clearing all the active indi vidual in-

terrupt bits that have not been masked out, i.e.

MIRQ will clear afte r read ing the Int er rupt r eg-

ister. MIRQ is also cleared by H_RESET.

6MTX_DONE

Default: 0 Read clear, write has no effect.

MTX_DONE is set by the Am79C975 control-

ler after an alert frame has been transmitted.

When MTX _DONE is set, th e MIRQ pin is as-

serted if MIRQEN is set to a 1 and the mask bit

MTX_DONEM in the SMIU Command register

is 0. MTIRQ is automatically cleared after

reading the Interrupt register. MTX_DONE is

also cleared by H_RESET.

5MRX_DONE

Default: 0 Read clear, write has no effect.

MRX_DONE is set by the Am79C97 5 control-

ler after an acknowledgment frame has been

received . Wh en MRX_D ONE is se t, the M IRQ

pin is asserted if MIRQEN is set to a 1 and the

mask bit MRX_DONEM in the SMIU Com-

mand register is 0. MRX_DONE is automati-

cally cleared after reading the Interrupt

H_RESET.

4:0 RESERVED

Am79C973/Am79C975 261

PRELIMINARY

Default: 00000Read as ZERO only

Reserved bits. For future use only

SMIU Receive Pattern RAM Address Register

(MReg Address 33)

Bit No. Name and Description

7:0 MRX_PADR

Default: 00h Read/Write

The SMIU Receive Pattern RAM Address reg-

ister contains the address of the location in the

Receive Pattern RAM where the next byte of

the Acknowledgment Frame Filter is written to.

The regis ter is cleared to 0 by H_RESET an d

every time the MRX_ENABLE bit is set to 1.

The address register autoincrements with ev-

ery byte write to the Receive Pattern RAM.

This allows a FIFO-type acce ss to the Receive

Pattern RAM and the host does not need to

keep track of the location he is writing to. In ad-

dition, MR X_PA DR can be se t to any address

within the Receive Pattern RAM in order to

modify a specific location.

MIU Receive Pattern RAM Data Port (MReg Address

34)

Bit No. Name and Description

7:0 MRX_PDATA

Default: undefined Read/Write

This is the 8-bit data port used to write to th e

Receive Pattern RAM.

SMIU Transmit Address Register (MReg Address

35)

Bit No. Name and Description

7:0 MTX_ADR

Default: 00h Read/Write

The SMIU Tr ansmit Addr ess regis ter contains

the address of the location in the Transmit

Data memory where the next byte of data is

written to. The register is cleared to 0 by

H_RESET and every time the MTX_START bit

in the Transmit Status register transitions is set

to 1. The address register auto-increments

with every byte written to the Transmit Data

memory. This allows a FIFO-type access to

the Transm it Data memo ry and the host d oes

not need to keep track of the location he is writ-

ing to. In addition, MTX_ADR can be set to any

address within the Transmit Data memory in

order to modify a specific location.

SMIU Transmit Data Port (MReg Address 36)

Bit No. Name and Description

7:0 MTX_DATA

Default: undefined Write only, read has no ef-

fect.

This is the 8-bit data port used to write to the

Transmit Data memory.

SMIU Transmit Message Length Register (MReg

Address 37)

Bit No. Name and Description

7:0 MTX_ LEN

Default: 00h Read/Write

The SMIU Tran sm it Messa ge Le ngt h co ntai ns

the number of bytes from the Transmit Data

memory that will be transmitted by the

Am79C975 controller as the alert frame. The 4

bytes of FCS checksum are not part of the

memory content, but are calculated by the con-

troller and appende d to the fra me. Th e host is

responsible to load a valid value into the

Transmit Message Length register. An y value

below 60 will create a runt frame on the net-

work. Any value above 128 will create unpre-

dictable results.

SMIU Transmit Status Register (MReg Address 38)

Bit No. Name and Description

7MTX_START

Default: 0 Read/Write

When MTX_START is set to a 1, the

Am79C975 controller will take the content of

the SMIU Transmit Data memory and transmit

the data as the next frame. Setting

MTX_START will also clear the Transmit Ad-

dress register. MTX_START is automatically

cleared after every transmission.

MTX_START is cleared by H_RESET.

6:4 RESERVED

Default: 000 Read/Write as ZERO only

Reserved bits. For future use only

3 MTX_LCOL

Default: 0 Read only, write has no effect.

Transmit Late Collision indicates that during

the transmission of the alert frame a collision

has occurred after the first slot time has

262 Am79C973/Am79C975

PRELIMINARY

elapsed. The Am7 9C97 5 c on tr oller wil l not re-

try the transmission on late collision.

MTX_LCOL is valid while MTX_START is se t

to 0. MTX_LCOL is cleared by H_RESET.

2 MTX_LCAR

Default: 0 Read only, write has no effect.

Transmit Loss of Carrier indicates that the

transceiver was in Link Fail state during the

transmiss i on of th e al ert fr ame . MT X_ LCA R is

valid while MTX_START is set to 0.

MTX_LCAR is cleared by H_RESET.

1 MTX_RTRY

Default: 0 Read only, write has no effect.

Transmit Retry error indicates that the trans-

mission of the alert frame has failed after 16 at-

tempts, due to repeated collisions on the

network. MTX_RTRY is valid while

MTX_START is set to 0. MTX_RTRY is

cleared by H_RESET.

0MTX_ERR

Default: 0 Read only, write has no effect.

Transmit Error is the OR of the MTX_LCOL,

MTX_LCAR and MTX_RTRY error.

MTX_ERR is valid while MTX_START is set to

0. MTX_ERR is cleared by H_RESET.

SMIU Receive Address Register (MReg Address

39)

Bit No. Name and Description

7:0 MRX_ADR

Default: 00h Read/Write

The SMIU Receive Address register contains

the address within the Receive Data memory

from where the ne xt byte of data is read. The

setting MRX_ENABLE in the Receive Status

Data memory from being overwritten with a

new frame. The address register autoincre-

ments with every byte read from the Receive

Data memory. This allows a FIFO-type access

to the Receive Data memory and the host does

not need to keep track of the location he is

reading from. In addition, MRX_ADR can be

set to any address within the Receive Data

memory in order to modify a specific location.

SMIU Receive Data Port (MReg Address 40)

Bit No. Name and Description

7:0 MRX_DATA

Default: undefinedRead only, write has no ef-

fect.

This is the 8-bit data port used to read from the

Receive Data memory.

SMIU Receive Message Length Register (MReg

Address 41)

Bit No. Name and Description

7:0 MRX _LEN

Default: undefinedRead only, write has no ef-

fect.

The SMIU Receive Message Length contains

the length of the acknowledgment frame, in-

cluding FCS. MRX_LEN only contains valid in-

formation after the Am79C975 controller has

set the MRX_DONE bit in the Interrupt regis-

ter. A message length value of larger than 128

indicates, that the Receive Data memory has

overflowed. A message length between 129

and 132 bytes indicates that only FCS bytes

have been lost and all message data bytes are

available in the Receive Data memory. A mes-

sage length greater than 132 indicates that

message data bytes have been lost from the

end of the message and the host should dis-

card the frame. MRX_LEN will indicate the cor-

rect message length up to 255 bytes. It will

freeze at 255 for longer frames. MR X_LEN is

not affected by H_RESET.

SMIU Receive Status Register (MReg Address 42)

Bit No. Name and Description

7 MRX_ENABLE

Default: 0 Read/Write

When MRX_ENABLE is set to a 1, the

Am79C975 controller is enabled to receive ac-

knowledgment frames from the management

station. The host must program the acknowl-

edgment frame filter registers with valid data

before setting MRX_ENABLE. Setting

MRX_ENABLE to a 1 will also clear the Re-

ceive Pattern RAM Address and Receive Ad-

dress registers. MRX_ENABLE is

automatically cleared after every receive.

MRX_ENABLE is cleared by H_RESET.

6:3 RESERVED

Am79C973/Am79C975 263

PRELIMINARY

Default: 0000 Read/Write as ZERO only

Reserved bits. For future use only

2 MRX_FRAM

Default: 0 Read only, write has no effect.

Framing error indicates that the acknowledg-

ment frame contains a non-integer multiple of

eight bits and that there was an FCS error. If

there was no FCS error on the acknowledg-

ment frame, then MRX_FRAM will not be set

even if there was a non-integer multiples of

eight bits in the frame. MRX_FRAM is valid

while MRX_ENABLE is set to 0.

MTX_MRX_FRAM is cleared by H_RESET.

1 MRX_FCS

Default: 0 Read only, write has no effect.

Frame Check Sequence error indicates that

the receiver has detected an FCS (CRC) error

on the acknowledgment frame. MRX_FCS is

valid while MRX_ENABLE is set to 0.

MRX_FCS is cleared by H_RESET.

0 MRX_ERR

Default: 0 Read only, write has no effect.

Receive Error is the OR of the MRX_FRAM

and MRX_FCS error. MRX_ERR is valid while

MRX_ENABLE is set to 0. MRX_ERR is

cleared by H_RESET.

264 Am79C973/Am79C975

PRELIMINARY

Note: RO = Ready Only, RC = Read/Auto-Clear, RW = Read/Write, W = Write, WO = Write Only

Am79C975 EEPROM Map

The Am79C 975 PCnet-FAST III controller us es an ex-

tended EEPROM map compared to the Am79C973 de-

vice (locations reserved in Am79C973 EEPROM map),

since there are some new registers in the SMIU that

are loaded from the EEPROM.

MReg

Address Register Name Access

Mode Access Command Default

Value

0 Vendor ID 0 RO Read Byte 22h

1 Vendor ID 1 RO Read Byte 10h

2 Device ID 0 RO Read Byte 00h

3 Device ID 1 RO Read Byte 20h

4 Revision ID RO Read Byte 40h

5 Subsyste m Vendor ID 0 RO Read Byte 00h

6 Subsyste m Vendor ID 1 RO Read Byte 00h

7 Subsystem ID 0 RO Read Byte 00h

8 Subsystem ID 1 RO Read Byte 00

9 Node IEEE Address 0 RO Read Byte 00h

10 Node IEEE Address 1 RO Read Byte 00h

11 Node IEEE Address 2 RO Read Byte 00h

12 Node IEEE Address 3 RO Read Byte 00h

13 Node IEEE Address 4 RO Read Byte 00h

14 Node IEEE Address 5 RO Read Byte 00h

15 Node IP Address 0 RO Read Byte 00h

16 Node IP Address 1 RO Read Byte 00h

17 Node IP Address 2 RO Read Byte 00h

18 Node IP Address 3 RO Read Byte 00h

19 Management Station IEEE Address 0 RO Read Byte 00h

20 Management Station IEEE Address 1 RO Read Byte 00h

21 Management Station IEEE Address 2 RO Read Byte 00h

22 Management Station IEEE Address 3 RO Read Byte 00h

23 Management Station IEEE Address 4 RO Read Byte 00h

24 Management Station IEEE Address 5 RO Read Byte 00h

25 Management Station IP Address 0 RO Read Byte 00h

26 Management Station IP Address 1 RO Read Byte 00h

27 Management Station IP Address 2 RO Read Byte 00h

28 Management Station IP Address 3 RO Read Byte 00h

29 Am79C975 Status RO Read Byte 02h

30 Transceiver Status RO Read Byte 00h

32 Command RW Read/Write By te 00h

32 Interrupt RC Read Byte 00h

33 Receive Pattern RAM Address RC,W Read/Write Byte 00h

34 Receive Pattern RAM Data RW Block Write undefined

35 Tr an sm it Addre ss R W Read/Write Byte 00h

36 Tr an sm it Da ta WO Block Write undefined

37 Transmit Message Length RW Read/Write Byte 00h

38 Tr an sm it Statu s RW Read/Write Byte 00h

39 Receive Address RW Read/Write Byte 00h

40 Receive Data RO Block Read undefined

41 Receive Message Length RO Read Byte undefined

42 Receive Status RW Read/Write Byte 00h

Am79C973/Am79C975 265