Am2901B/Am2901C Four-Bit Bipolar Microprocessor Slice DISTINCTIVE CHARACTERISTICS @ Two-address architecture - Independent simultaneous access to two working regis- ters saves machine cycles. Ejght-function ALU - Performs addition, two subtraction operations, and five Jogic functions on two source operands. @ Expandable - Connect any number of Am2901s together for longer word lengths. @ Left/right shift independent of ALU - Add and shift operations take only one cycle. Four status flags - Carry, overflow, zero, and negative. Flexible data source selection ALU data is selected from five source ports for a total of 203 source operand pairs for every ALU function. GENERAL DESCRIPTION The Am2901 industry standard four-bit microprocessor slice is a high-speed cascadable ALU intended for use in CPUs, peripheral controllers, and programmable micropro- cessors. The microinstruction flexibility of the Am2901 permits efficient emulation of almost any digital computing machine. The device, as shown in the block diagram below, consists of a 16-word by 4-bit two-port RAM, a high-speed ALU, and the associated shifting, decoding and multiplexing circuitry. The nine-bit microinstruction word is organized into three groups of three bits each and selects the ALU source operands, the ALU function, and the ALU destination register. The microprocessor is cascadable with full look ahead or with ripple carry, has three-state outputs, and provides various status flag outputs from the ALU. AMD's ion-implanted micro-oxide (IMOX) processing is used to fabricate the 40-lead LSI chip. The Am2901C is a plug-in replacement for the Am2901B, but is 33% faster than the Am2901B. MICROPROCESSOR SLICE BLOCK DIAGRAM Add, am SUT W DATA IW A IREADI ADDRESS pa eas . (READAORITEL J] anoness ADDRESS tty o aan Ws ADOMESADE E REGIETERS. G o REGISTER DmecT oe DATAIN . s ALU DATA SOURCE SELECTOR k a rE o canny fe }Ciw FUNCTION ALU BD002120 iMOX is a trademark of Advanced Micro Devices. 5-1 01656B Refer to Page 13-1 for Essential Information on Military Devices OLO67WY/ElLo6zuyAm2901B/Am2901C RELATED PRODUCTS Part No. | Description Am2902 Carry Look-Ahead Generator Am2904 Status and Shift Control Unit Am2910 Microprogram Controller Am2914 Vectored Priority Interrupt Controller Am2917 Bus Transceiver Am2918 Pipeline Register Am2920 Octal Register Am2922 Condition Gode MUX Am2925 System Clock Generator Am2940 DMA Address Generator Am2952 Bidirectional |1/O Port Am27S35_ | Registered PROM For applications information see Chapters Ill and IV of Bit Slice Microprocessor Design, by Mick and Brick, McGraw Hill Publishers. 016568 5-2 Refer to Page 13-1 for Essential information on Military DevicesCONNECTION DIAGRAM Top View P-40, D-40 F-42 edi... EQ are Note: Pin 1 is marked for orientation Figure 1. METALLIZATION AND PAD LAYOUT SSees x Be 8h BNRBERRVEBSE DIE SIZE 0.130" x 0.123 ORDERING INFORMATION AMD products are available in several packages and operating ranges. The order number is formed by a combination of the following: Device number, speed option (if applicable), package type, operating range and screening option (if desired). Am2901B Valid Combinations Am2901C dD OG a PC Screening Option Blank - Standard processing Am2901B Oe DCB, DMB B - Burn-in XG, XM Temperature (See Operating Range) C -Commercial (0C to + 70C) PC M - Military (-55C to + 125C) DC, DCB, DMB Am2901G FMB Package LC, LMB D- 40-pin CERDIP XC, XM F ~ 42-pin flatpak L ~ 44-pin leadiess chip carrier P - 40-pin plastic DIP X- Dice Valid Combinations Device type Consult the AMD sales office in your area to Four-Bit Microprocessor Slice determine if a device is currently available in the combination you wish. . 016568 5-3 Refer to Page 13-1 for Essential Information on Military Devices > J X) e Qa ~ > 3 x 8 oOAm2901B/Am2901C PIN DESCRIPTION Pin No. |Name VO | Description 4.321 Ao-3 | The four address inputs to the register stack used to select one register whose contents are displayed through the A- port. 17, 18 Bo-3 i The four address inputs to the register stack used to select one register whose contents are displayed through the B- 19, 20 port and into which new data can be written when the clock goes Low. 10-8 l The nine instruction controt lines. Used to determine what data sources will be applied to the ALU (Io1 2), what function the ALU will perform (345), and what data is to be deposited in the Q-register or the register stack (1678). 16 Q3 1/0 | A shift line at the MSB of the Q register (Q3) and the register stack (RAMs). Electrically these lines are three-state RAM3 outputs connected to TTL inputs internal to the device. When the destination code on |g7g indicates an up shift (octal 6 or 7) the three-state outputs are enabled and the MSB of the Q register is available on the Qg3 pin and the MSB of the ALU output is available on the RAM3 pin. Otherwise, the three-state outputs are electrically OFF (high-impedance) and the pins are electrically LS-TTL inputs. When the destination cade calls for a down shift, the pins are used as the data inputs to the MSB of the Q register (octal 4) and RAM (octal 4 or 5). 21, 9 Qo VO | Shift lines like Qg and RAMg, but at the LSB of the Q-register and RAM. These pins are tied to the Q3 and RAMg pins RAMo of the adjacent device to transfer data between devices for up and down shifts of the Q register and ALU data. 25, 24 Do-.3 l Direct data inputs. A four-bit data field which may be selected as one of the ALU data sources for entering data inte 24, 22 the device. Do is the LSB. 36, 37 Yo-3 0 The four data outputs. These are three-state output lines. When enabled, they display either the four outputs of the 36, 39 ALU or the data on the A-port of the register stack, as determined by the destination code {g7a. 40 OE I Output Enable. When OF is HIGH, the Y outputs are OFF; when OE is LOW, the Y outputs are active (HIGH or LOW). 32, 35 GP 0 The carry generate and propagate outputs of the internal ALU. These signals are used with the Am2902 for carry- lookahead. 34 OVR Oo Overtlow. This pin is logically the Exclusive-OR of the carry-in and carry-out of the MSB of the ALU. At the most significant end of the word, this pin indicates that the result of an arithmetic two's complement operation has . overflowed into the sign-bit. "1 F=0 0 This is an open collector output which goes HIGH (OFF) if the data on the four ALU outputs Fg. are all LOW. in positive logic, it indicates the result of an ALU operation is zero. 31 Fg 3 The most significant ALU output bit. 29 Cn | The carry-in to the internal ALU. 33 Ch+4 oO The carry-out of the internal ALU. 15 cp | The clock input. The Q ragister and register stack outputs change on the clock LOW-to-HIGH transition. The clock LOW time is internally the write enable to the 16 x 4 RAM which compromises the master latches of the register stack. While the clock is LOW, the "slave" latches on the RAM outputs are closed, storing the data previously on the RAM outputs. This allows synchronous master-slave operation of the register stack. DETAILED Am2901C MICROPROCESSOR BLOCK DIAGRAM aay pc nay q c T TT... Ti + a 2m a zm a [ } t T_ . * o tr ew 4 <A T cor t | | wen. cote ee |e Mr | come | a > satnat json zn 2 2 im K a ey we PO * . t TTT Oy o er Oy = Ne en seen oie b<: % 4 o 7] Ls sz (2 * iM Ll a as as an 2 an a a b<+ of ste ee ES 4 vn tT 1 t TT t | nt T 1 | | YY Note: LSB is numbered 0; MSB is numbered 3. ro *. " 1 5 BD002050 Figure 2. 016568 5-4 Refer to Page 13-1 for Essential information on Military DevicesARCHITECTURE A detailed block diagram of the bipolar microprogrammable microprocessor structure is shown in Figure 1. The circuit is a four-bit slice cascadable to any number of bits. Therefore, all data paths within the circuit are four bits wide. The two key elements in the Figure 1 block diagram are the 16-word by 4- bit 2-port RAM and the high-speed ALU. Data in any of the 16 words of the Random Access Memory (RAM) can be read from the A-port of the RAM as controlled by the 4-bit A address field input. Likewise, data in any of the 16 words of the RAM as defined by the B address field input can be simultaneously read from the B-port of the RAM. The same code can be applied to the A select field and B select field in which case the identical file data will appear at both the RAM A-port and B-port outputs simultaneously. When enabled by the RAM write enable (RAM EN), new data is always written into the file (word) defined by the B address field of the RAM. The RAM data input field is driven by a 3- input multiplexer. This configuration is used to shift the ALU output data (F) if desired. This three-input multiplexer scheme allows the data to be shifted up one bit position, shifted down one bit position, or not shifted in either direction. The RAM A-port data outputs and RAM B-port data outputs drive separate 4-bit latches. These latches hold the RAM data while the clock input is LOW. This eliminates any possible race conditions that could occur while new data is being written into the RAM. The high-speed Arithmetic Logic Unit (ALU) can pertorm three binary arithmetic and five logic operations on the two 4-bit input words R and S. The R input field is driven from a 2-input multiplexer, while the S input field is driven from a 3-input multiplexer. Both multiplexers also have an inhibit capability; that is, no data is passed. This is equivalent to a zero"' source operand. Referring to Figure 2, the ALU R-input multiplexer has the RAM A-port and the direct data inputs (D) connected as inputs. Likewise, the ALU S-input multiplexer has the RAM A- port, the RAM B-port and the Q register connected as inputs. This multiplexer scheme gives the capability of selecting various pairs of the A, B, D, @ and "0" inputs as source operands to the ALU. These five inputs, when taken two at a time, result in ten possible combinations of source operand pairs. These combinations include AB, AD, AQ, AO, BD, BQ, BO, DQ, DO and QO. It is apparent that AD, AQ and AO are somewhat redundant with BD, BQ and 80 in that if the A address and B address are the same, the identical function results. Thus, there are only seven completely non-redundant source operand pairs for the ALU. The Am2901 microproces- sor implements eight of these pairs. The microinstruction inputs used to select the ALU source operands are the lo, 11, and lo inputs. The definition of Io, 11, and Iz for the eight source operand combinations are as shown in Figure 3. Also shown is the octal code for each selection. The two source operands not fully described as yet are the D input and Q input. The D input is the four-bit wide direct data field input. This port is used to insert all data into the working registers inside the device. Likewise, this input can be used in the ALU to modify any of the internal data tiles. The Q register is a separate 4-bit file intended primarily for multiplication and division routines but it can also be used as an accumulator or holding register for some applications. The ALU itself is a high-speed arithmetic/logic operator capable of performing three binary arithmetic and five logic functions. The lg, l4, and Is microinstruction inputs are used to select the ALU function. The definition of these inputs is shown in Figure 4. The octal code is also shown for reference. The normal technique for cascading the ALU of several devices is in a look-ahead carry mode. Carry generate, G, and carry propagate, P, are outputs of the device for use with a carry-look-ahead-generator such as the Am2902. A carry-out, Ch + 4, is also generated and is available as an output for use as the carry flag in a status register. Both carry-in (Cy) and carry-out (Ch +4) are active HIGH. The ALU has three other status-oriented outputs. These are Fg, F =0, and overflow (OVR). The F3 output is the most significant (sign) bit of the ALU and can be used to determine positive or negative results without enabling the three-state data outputs. Fg is non-inverted with respect to the sign bit output Y3. The F = 0 output is used for zero detect. It is an open-collector output and can be wire OR'ed between micro- processor slices. F = 0 is HIGH when all F outputs are LOW. The overfiow output (OVR) is used to flag arithmetic opera- tions that exceed the available two's complement number range. The overflow output (OVR) is HIGH when overflow exists. That is, when Cp + 3 and Cp + 4 are not the same polarity. The ALU data output is routed to several destinations. It can be a data output of the device and it can also be stored in the RAM or the Q register. Eight possible combinations of ALU destination functions are available as defined by the lg, |7, and lg microinstruction inputs. These combinations are shown in Figure 5. The four-bit data output field (Y) features three-state outputs and can be directly bus organized. An output control (OE) is used to enable the three-state outputs. When OE is HIGH, the Y outputs are in the high-impedance state. A two-input multiplexer is also used at the data output such that either the A-port of the RAM or the ALU outputs (F) are selected at the device Y outputs. This selection is controlled by tha Ig, lz, and Ig microinstruction inputs. Refer to Figure 12 for the selected output for each microinstruction code combination. As was discussed previously, the RAM inputs are driven from a three-input multiplexer. This allows the ALU outputs to be entered non-shifted, shifted up one position (X2) or shifted down one position (+2). The shifter has two ports; one is labeled RAMo and the other is labeled RAM3. Both of these ports consist of a buffer-driver with a three-state output and an input to the multiplexer. Thus, in the shift up mode, the RAMg buffer is enabled and the RAMg multiplexer input is enabled. Likewise, in the shift down mode, the RAMo buffer and RAM3 input are enabled. In the no-shift mode, both buffers are in the high-impedance state and the multiplexer inputs are not selected. This shifter is controlled from the Ig, 17 and lg microinstruction inputs as defined in Figure 5. Similarly, the Q register is driven from a 3-input multiplexer. In the no-shift made, the multiplexer enters the ALU data into the Q register. In either the shift-up or shift-down mode, the multiplexer selects the Q register data appropriately shifted up or down. The Q shifter also has two ports; one is labeled Qo and the other is Q3. The operation of these two ports is similar to the RAM shifter and is also controlled from Ig, l7, and Ig as shown in Figure 5. The clock input to the Am2901 controls the RAM, the Q register, and the A and B data latches. When enabled, data is clocked into the Q register on the LOW-te-HIGH transition of the clock. When the clock input is HIGH, the A and B latches are open and will pass whatever data is present at the RAM outputs. When the clock input is LOW, the latches are closed and wilt retain the last data entered. If the RAM-EN is enabled, new data will be written into the RAM file (word) defined by the B address field when the clock input is LOW. 5-5 016568 Refer to Page 13-1 tor Essential Information on Military Devices > 3 3 _ @ ~ > 3 = oOAm2901B/Am2901C FUNCTIONAL TABLES ALU SOURCE MICRO CODE OPERANDS Mnemonic Octal c lo | Iy | lo Code R s AQ Lyell 0 A Q AB tL] Ly] H 1 A B zQ L]HIL 2 0 Q 2B L | H] 4H 3 0 B ZA H/] LAL 4 0 A DA Hj; L]H 5 D A DQ H]|HYIL 6 D Q DZ H]|HIH 7 D 0 Figure 3. ALU Source Operand Control. MICRO CODE ALU Mnemonic ts | ta | ts Octal | Function SYMBOL Code ADD LI LEL oO |R Plus S R+S SUBR LJ] LH 1 |S Minus R S-R SUBS LIT HIL 2 {R Minus S R-S OR LiH|H 3 jJRORS Rvs AND HILCIL 4 IR ANDS RaS NOTRS H]L|H 5 |R AND S Ras EXOR HH] HI L 6 |R EX-OR S RVS EXNOR H| HH 7 |R EX-NOR S RYS Figure 4. ALU Function Control. RAM Q-REG. RAM Qa MICRO CODE FUNCTION FUNCTION y SHIFTER SHIFTER Mnemonic ; OUTPUT 7 Is | 7 | te ee Shift | Load | Shift | Load RAMg | RAM3 Qo Q3 QREG LeeLee 0 x NONE NONE F-Q F x x x x NOP t{[uc]H 1 x NONE x NONE F x x x x RAMA LHe 2 NONE F>B x NONE A x x x x RAMF L | Hi H 3 NONE FB x NONE F x X x x RAMOD HyJeE|]L 4 DOWN | F/27B | DOWN | Q/2-Q F Fo INg Qo IN3 RAMD HH] LH 5 DOWN | F/2-B x NONE F Fo INg Qo x RAMQU HH] HL 6 uP 2F-B uP 20-a F INg F3 INo Q3 RAMU H | H | H 7 UP 2F-B X NONE F INo Fg x Q3 X = Don't care. Electrically, the shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state. B = Register Addressed by 8 inputs. UP is toward MSB, DOWN is toward LSB. Figure 5. ALU Destination Control. 1249 OCTAL o | 1 | 2 > . fs |e |? OCTAL ALU ALU Source Is43 Function AQ AB 0,Q 0,B O,A DA D.Q Dc Ca= A+Q A+B Qa B A D+A D+Q D 0 R Plus S Cy= A+Q+1 A+B+1 Q+1 B+1 A+14 O+A+1 D+Q+1 D+1 Cn= Q-A-1 B-A~-1 Q-1 B-1 A-1 A-D-1 Q-D-1 -D-1 1 S Minus R Cn= Q-A B-A Q B A A-D a-p -D Chek A-Q-1 A-B-1 -Q-1 -B-1 -A-14 D-A-1 D-Q-1 D-1 2 R Minus S$ Ch= A-Q A-B -a -B ~A D-A D-aQ D 3 RORS AvQ AvB Q B A DvA pa D 4 R AND S AaQ AAB 0 0 0 DAA DaQ 0 5 RAND S AsQ AsB Q B A Baa Baa 0 6 R EX-OR S AVQ AVB Q B A. DVA pva D 7 R EX-NOR S AVG AVE 6 B A BVA BYa 5 + = Plus; - = Minus; v* OR; = AND; V = EX-OR Figure 6. Source Operand and ALU Function Matrix. 01656B 5-6 Refer to Page 19-1 for Essential Information on Military DevicesSOURCE OPERANDS AND ALU FUNCTIONS There are eight source operand pairs available to the ALU as selected by the Ip, I, and Iz instruction inputs. The ALU can perform eight functions; five logic and three arithmetic. The lg, I4, and is instruction inputs control this function selection. The carry input, Cp, also affects the ALU results when in the arithmetic mode. The Cp input has no effect in the logic mode. When |g through Is and Cp, are viewed together, the matrix of Figure 6 results. This matrix fully defines the ALU/source operand function for each state. The ALU functions can also be examined on a "task" basis, i.e., add, subtract, AND, OR, etc. in the arithmetic mode, the carry will affect the function performed while in the logic mode, the carry will have no bearing on the ALU output. Figure 7 defines the various logic operations that the Am2901 can perform and Figure 8 shows the arithmetic functions of the device. Both carry-in LOW (Cp = 0) and carry-in HIGH (Cp, = 1) are defined in these operations. leon tet0 Group Function 40 AAQ 1) mo | 46 DAQ 30 AvQ st | on | 36 DvQ 60 AvQ si | exon | AS 66 pva 70 AVG a EX-NOR Ave 76 ova 72 a ; ; INVERT 5 77 5B 62 Q : 3 PASS r 67 D 32 Q ; 3 PASS 37 D 42 0 4a "ZERO" 0 47 0 50 AaQ st | amok |S 56 Baa Figure 7. ALU Logic Mode Functions. Octal Cy= Cy=H I543, loio Group Function Group Function 00 A+Q A+Q+1 01 ADD A+B ADD plus | A+Bt+1 05 D+A one D+tAti1 06 D+Q D+Q+1 02 Q Qt+1 03 PASS B Increment B+t 04 A Att 07 D D+1 12 Q-1 Q 13 Decrement B-1 PASS B 14 A-1 A 27 D-1 D 22 -Q-1 -Q 23 1's Comp. ~B-1 2's Comp. -B 24 ~A-1 (Negate)} -A 17 -D-1 -D 10 Q-A-1 Q-A 1f Subtract B-A-1 Subtract B-A 15 (1's Comp) | A-D-1 | (2's Comp) A-D 16 Q-D-1 Q-D 20 A-Q-1 A-Q 21 A-B-1 A-B 26 D-A-1 D-A 26 D-Q-1 0-Q Figure 8. ALU Arithmetic Mode Functions. 01656B Refer to Page 13-1 for Essential Information on Military Oevices > 3 w 8 = a ~ > 3 N 3 = OoAm2901B/Am2901C LOGIC FUNCTIONS FOR G, P, Cy +4, AND OVR The four signals G, P, Cy 44, and OVR are designed to indicate carry and overflow conditions when the Am2901 is in the add or subtract mode. The table below indicates the logic equations for these four signals for each of the eight ALU functions. The R and S inputs are the two inputs selected according to Figure 3. Definitions (+ = OR) Po = Ro + So Go = RoSo Py=Ri+Sy Gy = R18 Pa =Ra+t Se Ga = RaSo Pg =Rg + Sg Gg = RaSa C4 = Gg + PgGo + PgP2Gy + P3P2P4Gp + PgP2P1PoCp Cy = Go + PaGy + PaP1Gq +PaP1PoC, 1543 | Function P G Cn+4 OVR 0 R+S PgPaP iP Gg + Pata + PoP2Gy + PaPaP iGo C4 C3VC4 1 S-R ~___--Same as R+S equations, but substitute Ri for Rj in definitions --_-_ 2 R-S Same as R +S equations, but substitute 5) fer Sj in definitions 3 Rvs LOW PaP2P1Po PaPaPsPo + Cn PPPPo+ Cn 4 Ras Low G3 + G2 + G; + Go Gg+Go+G,+Go+Cp | Got Go+G;+Go+Cp 5 Ras Low +--Same as RAS equations, but substitute Rj for Aj in definitions 6 RVS -__-Samme as FAVS, but substitute Fj for Aj in definitions-_ 7 AVS Gg +G2+G1+Go Gg + PyG2 + PaP2G1 + PgP2P1Po Ga Pate #PaPoGt See note + PgPoP1Po(Go + Ch) Note: [Pa+ GoP, +G2G1Po + G2G1GoC,] 7 + =OR [Pg+ GgPo+GaGoP, + GgGoG Py + GaGeG1GoCnl Figure 9. MINIMUM CYCLE TIME CALCULATIONS FOR 16-BIT SYSTEMS Speeds used in calculations for parts other than Am2901C are representative for available MSI parts. @ SOuENcER Am 210A, MICROPROGRAM MEMORY Lse sa @ .*F ee REGISTER ABC, am2ooic ove b+} srarus [STAD Fy REGISTER Am2901C c F-of ] 1 gad Co Am2@024 Pp na aecisTen ner CLOCK j AFO01621 Pipelined System. Add without Simultaneous Shift. DATA LOOP CONTROL LOOP @Register Clock to_Output 9 @Register Clock to Output 9 +@2001C A, B to G, 37 + @MUX Select to Output 13 + @2902A Gp. Po to Gn+z 7 + @2910A CC to Output 30 + @2901C Cr to Cr +4, OVA, 25 +@PROM Access Time 40 Fa, F=0, +@Register Setup Time 2 + @Register Setup Time 2 80ns 94ns Minimum clock period = 94ns 01656B 5-B Refer to Page 13-1 for Essential Information on Military Devices.> 3 2 a 5 iw ~O eee ss fit Gy to ay wux 2 aeaueveR Abicy ar Amaaorc 1G] a Fy Am2901c & @ Bao L Cnee A & Aad ee LL 3 name PT 1h a | AF001631 Pipelined System. Simultaneous Add and Shift Down. DATA LOOP CONTROL LOOP @Register Clock to_Output 9 @Register Clock to Output 9 + (@2901C A, B to GP 37 +@MUX Select to Output 13 + @2902A Go, Pp to Ch+z 7 +@2810A CC to Output 30 +@2901C Cn ta Fs, OVR 22 +@PROM Access Time 40 +@XOR and MUX 21 + @Register Setup Time 2 +@2901C RAMg Setup 12 one 168ns Minimum clock period = 108ns Figure 10. 01656B 5-9 Refer to Page 13-1 for Essential Information on Military DevicesAm2901B/Am2901C ABSOLUTE MAXIMUM RATINGS Storage Temperature ...........-..::eeeeeee -65C to + 150C Ambient Temperature Under Bias......... -55C to +125C Supply Voltage to Ground Potential CONTINUOUS 2.0... eect eee ee ee renee -0.5V to +7.0V DC Voltage Applied to Outputs For High Output State ..........-. -0.5V to +Vcoc max DC Input Voltage ........... cere ~0.5V to +5.5V DC Output Current, Into Outputs ............0. eee 30mA DC input Current ...........c ececeeeeee ees -30mA to +5.0mA Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature .... Supply Voliage ............-..cc Military (M) Devices Temperature .............ccceeee ees Supply Voltage seed ee ee ee et nee neneee arc to +70C +4,76V to +5.25V -86C to + 125C +4.5V to +5.5V Operating ranges define those limits over which the function- ality of the device is guaranteed. DC CHARACTERISTICS over operating range unless otherwise specified -10 Parameters Description Test Conditions (Note 1) Min Max Units !OH = -1.6MA Yo Y1, Ya, Ya 2A low =-1.0MA, Ch 44 24 - loo =-800uA, OVR, P 24 Voc = MIN Vou Output HIGH Voltage Vin = Vin oF Vib lon = -600pA, Fy 24 Volts. lon = -600nA 24 RAMo, 3, Qo,3 lou = -1.6mA, G 24 Output Leakage Current Voc = MIN, Vou = 5.5V ICex For F = 0 Output Vin = Vins or Vin. 250 BA jo = 20MA (COM'L) (Note 4) 0.5 Yo. Y1, Ya Y3 [iq. = 16mA (MIL) (Note 4) 05 Voc = MIN, | G, F=0 lo, = 16MA 05 VoL Output LOW Voltage Vin = Vin Cn+4 lo, = 10mMA 0.5 or Vit ova, P lo. = 8.0mA 0.5 7 sho. 3 lo. = 6.0MA 05 Guaranteed input logical HIGH Vin Input HIGH Levet voltage for all inputs (Note 6) 2.0 Volts Guaranteed input logical LOW VIL Input LOW Level voltage for all inputs (Note 6) 08 Volts v| Input Clamp Valtage Voc = MIN, lin = - 18mA -1.5 Volts Clock, DE -0.36 Ap, Ai, A2. Ag -0.36 Bo. By, Ba, Ba -0.36 Do, Dy, Dg, D3 -0.72 Ii Input LOW Current Voc = MAX, Vin = 0.5V lo. i, a, le Ie 0.36 mA Ig, l4, Is. I7 -0.72 RAMg, 3, Qo,3 (Note 3) -0.8 Cn -3.6 Clock, OF 20 Ag, At, Az, Ag 20 Bo, By, Ba, Ba 20 Do, D4, D2, Dg 40 WH Input HIGH Current Voc = MAX, Vin = 2.7V ig. 1. I Ie, Ip 20 pA Ig, 14, Is, Iz 40 RAM, 3, Qo,a (Note 3) 100 Ch 200 016568 Refer to Page 13-1 for Essential Information on Military DevicesParameters Description Test Conditions (Note 1) Min Max Units \ Input HIGH Current Voc = MAX, Vin = 5.5V 1.0 mA Yo. 4, Vo = 2.4V 50 Ya, Ya Vo = 0.5V -50 loa Output Carentan") | Voc = MAX FiAMo, 9 [tole 3) 100 | A Qo, 3 Vo =0.5V (Note 3) -800 Yo. Y1, Y2, 3, G -30 -85 Cn+4 -30 -85 los ies 3" Circuit Current | Vog = MAX + 0.5V, Vo =0.5V | OVA, P -30 ~85 mA F3 -30 -85 RANg, 3, Qo, 3 -30 -85 COM'L Only Ta =0C to + 70C 265 (Note 4) Ta = + 70C 220 lec (Now. gy Current Voc = MAX [Mit Only To = 55C tor 125C 280 mA (Note 4) To = + 125C 198 Note: 1. Voc conditions shown as MIN or MAX, refer to the military (110%) or commercial (5%) Vcc limits. . Not more than one output should be stored at a time. Duration of the short circuit test should not exceed one second. . These are three-state outputs internally connected to TTL inputs. Input characteristics are measured with lg7g in a state such that . These input levels provide zero noise immunity and should only be static tested in a noise-free environment, (not functionally tested). the three-state output is OFF. "MIL" = Am2901CXM, DM, FM, LM, COM'L" = Am2901CXC, PC, OC, LC. Worst case Icc is measured at the lowest temperature in the specified operating range. 016568 -11 Refer to Page 13-1 for Essential information on Military Devices > 3 N 3 _ a ~ > 3 X = oOAm2901B/Am2901C |. Am2901B Guaranteed Commercial A. Cycle Time and Clock Characteristics. Range Performance o - Read-Modify-Write Cycle (from selection of A, 69ns The tables below specify the guaranteed performance of the B registers to end of cycle.) Am2901B over the commercial operating range of 0C to Maximum Clock Frequency to shift Q (50% 16MH + 70C, with Vcc from 4.75V to 5.26V. All data are in ns. with duty cycle. |= 432 or 632) 2 inputs switching between OV and 3V at 1V/ns and measure- T ments made at 1.5V. All outputs have maximum DC load. Minimum Clock LOW Time 30ns Minimum Clock HIGH Time 30ns This data applies to the following part numbers: Am2901 BPC fai , Am2901 BDC Minimum Clock Period 69ns B. Combinational Propagation Delays. (Note 1) Ci = 50pF To Output RAMO Qo From Input Y F3 Ca+4 G, P F=0 OVR RAM3 Q3 A, B Address 60 61 59 50 70 67 71 - D 38 36 40 33 48 44 45 - Cn 30 29 20 - 37 29 38 - 1012 50 47 45 45 56 53 57 - 1345 51 52 52 45 60 49 53 - 1678 28 - - - - - 35 35 A Bypass ALU 37 _ _ _ _ _ _ _ (1 = 2XXx) Clock 7 49 48 47 37 58 55 59 29 C. Set-up and Hold Times Relative to Clock (CP) Input. (Note 1) CP: a Jf Input a _o Set-up Time Hold Time Set-up Time Hold Time Before H ~L After H -L Before L -H After i -H A, B Source Address 20 0 (Note 3} 69 (Note 4) 0 B Destination Address 16 Do Not Change (Note 2) 0 D - - 51 0 Cn - - 39 0 1012 - - 56 0 1345 - - 55 0 1678 W Do Not Change (Note 2) 0 RAMO, 3, QO, 3 - - | 16 0 D. Output Enable/Disable Times. Output disable tests performed with Cy. = 5pF and measured to 0.5V change of output voltage level. Input Output Disable OE Y 35 25 NOTES: 1. A dash indicates a propagation delay path or set-up time constraint does not exist. 2. Gertain signals must be stable during the entire clock LOW time to avoid erroneous operation. This is indicated by the phrase ''do not change". 3. Source addresses must be stable prior to the clock H~L transition to allow time to access the source data before the latches close. The A address may then be changed. . The B address could be changed if it is not a destination: ie., if data is not being written back into the RAM. Normally A and B are not changed during the clock LOW time. 4. The set-up time prior to the clock L~H transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It indicates all the time from stable A and B addresses to the clock L-H transition, regardless of when the clock H~L transition occurs. 016568 Refer to Page 13-1 for Essential information on Miitary Devicesll. Am2901B Guaranteed Military Range A. Cycle Time and Clock Characteristics. 5 Performance - - nD Read-Modify-Write Cycle (from selection of A, 88ns s The tables below specify the guaranteed performance of the B registers to end of cycle.) a Am29018 over the military operating range of ~55C to Maximum Clock Frequency to shift Q (50% =~ +125C, with Voc from 4.5V to 5.5V. All data are in ns, with duty cycle, | = 432 or 632) 1SMHz 5 inputs switching between OV and 3V at 1V/ns and measure- a : R ments made at 1.5V. All outputs have maximum DC load. Minimum Clock LOW Time 30ns s Minimum Clock HIGH Time 30ns 5 This data applies to the following part numbers: Am2901BDM Minimum Clock Period 88ns Am2901BFM B. Combinational Propagation Delays. (Note 1) Cy = 50pF To Output _ RAMO Qo From input Y F3 Cn+4 G, P F=0 OVR RAM3 Q3 A, B Address 82 84 80 70 90 86 94 - D 44 38 40 34 50 45 48 - Cn 34 32 24 - 38 31 39 - 1012 53 50 47 / 46 65 55 58 - 1345 58 58 58 48 64 56 55 - 1678 29 - ~ - - - 27 _ a7 A Bypass ALU 50 _ _ _ _ _ (I = 2XX) ~ ~ Clock 5 53 50 49 4 63 58 61 31 C. Set-up and Hold Times Relative to Clock (CP) Input. (Note 1) OOS ij Input ors KX Set-up Time Hold Time Set-up Time Hold Time Before H ~L After H ~L Before L -H After L ~H A, B Source Address 30 0 (Note 3) 88 (Note 4) 0 : saeetnation 15 Do Not Change (Note 2) 0 0 - - 55 0 Cn - - 42 0 lo12 - - 58 0 1345 - - 62 0 \678 14 Do Not Change (Note 2) 0 RAMO, 3, Q0, 3 - = | 18 3 D. Output Enable/Disable Times. Output disable tests performed with CL = 5pF and measured to 0.5V change of output voltage level. Input Output Enable Disable OE Y 40 25 NOTES: 1. A dash indicates a propagation delay path or set-up time constraint does not exist. . 2. Certain signais must be stable during the entire clock LOW time to avoid erroneous operation. This is indicated by the phrase do not change. 3. Source addresses must be stable prior to the clock HL transition to allow time to access the source data before the latches close. The A address may then be changed. The B address could be changed if it is not a destina- tion: ie., if data is not being written back inte the RAM. Normally A and B are not changed during the clock LOW time. 4. The set-up time prior to the clock LH transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It includes all the time from stable A and B addresses to the clock L7H transition, regardless of when the clock H-L transition occurs. 01656B 5-13 Refer to Page 13-1 for Essential Information on Military DevicesAm2901B/Am2901C iil, Am2901C Guaranteed Commercial A. Cycle Time and Clock Characteristics. Range Performance = - Read-Modify-Write Cycle (from selection of A, Er The tables below specify the guaranteed performance of the B registers to end of cycle.) ns Am2901C over the commercial operating range of 0C to : ; +70C, with Voc from 4.75V to 5.25V. All data are in ns, with a ook Frecuency to shift Q (50% = | somnz inputs switching between OV and 3V at 1V/ns and measure- ty_cycle, |= r ) ments made at 1.5V. All outputs have maximum DC load. Minimum Clock LOW Time 15ns This data applies to the following part numbers: Am2901CPC Minimum Clock HIGH Time 15ns Am2901CDC Minimum Clock Period 31ns Am2901CLC B. Combinational Propagation Delays. (Note 1) C_ = 50pF To Output RAMO ao From input Y F3 Cn+4 G, PB F=0 OVR RAM3 a3 A, B Address 40 40 40 37 40 40 40 - D 30 30 30 30 38 30 30 - Cn 22 22 20 - 25 22 25 - 1012 35 35 35 37 37 35 35 - 1345 35 35 35 35 38 35 35 - 1678 25 - - - - - 26 26 A Bypass ALU 35 _ _ _ . _ (I = 2XX) ~ - Clock 35 35 35 35 35 35 35 28 C. Set-up and Hold Times Relative to Clock (CP) Input. (Note 1) cP: 42 Input KL __ Set-up Time Hold Time Set-up Time Hoid Time Before H ~L After H -L Before L. -H After L -H 30, 15+ Tpwe A, B Source Address 15 1 (Note 3) (Note 4) 4 B Destination Address 15 Do Not Change (Note 2) 1 Oo - - 25 0 Cn - - 20 0 1012 - - 30 0 1345 - - 30 0 1678 10 Do Not Change (Note 2) QO RAMO, 3, G0, 3 - - | 12 0 D. Output Enable/Disable Times. Output disable tests performed with C, = S5pF and measured to 0.5V change of output voltage level. Input Output Enable Disable OE Y 23 23 NOTES: 1. A dash indicates a propagation delay path or set-up time constraint does not exist 2. Certain the phrase do not change. 3. Source addresses must be stable prior to the clock H~L transition to allow time to access the source data before the latches close. The A address may then be changed. The B address could be changed if it is not a destina- tion; i.e., if data is not being written back into the RAM. Normally A and B are not changed during the clock LOW time. signals must be stable during the entire clock LOW time to avoid erroneous operation. This is indicated by 4. The set-up time prior to the clock L-H transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It includes all the time from stable A and B addresses to the clock L-H transition, regardless of when the clock HL transition occurs. 5-14 016563 Refer to Page 13-1 for Essential Information on Military DevicesIV. Am2901C Guaranteed Military Range A. Cycle Time and Clock Characteristics. 3 Performance rs Read-Modify-Write Cycle (from selection of A, 32 The tables below specify the guaranteed performance of the B registers to end of cycle.) ns 2 Am2901C over the military operating range of 55C to . BD + 125C, with Voc from 4.5V to 5.5V. All data are in ns, with ae Sapeianue to shift Q (60% 3iMHz || > inputs switching between OV and 3V at 1V/ns and measure- uty cycle, | = or 632) 3 ments made at 1.5V. All outputs have maximum OC load. Minimum Clock LOW Time 15ns 8 This data applies to the following part numbers: Am2901CDM Minimum Clock HIGH Time 15ns 3 Am2901CFM Ss - Am2901CLM Minimum Clock Period 32ns B. Combinational Propagation Delays. (Note 1) C. = 50pF To Output _ RAMO Qo From Input F3 Cn+4 GP F=0 OVR RAM3 a3 A, B Address 48 48 48 44 48 48 48 - D 37 37 37 34 40 37 37 ~ Cn 25 25 21 - 28 25 28 - 1012 40 40 40 44 44 40 40 - 1345 40 40 40 40 40 40 40 - 1678 29 - - - - - 29 29 A Bypass ALU (= 2XX) 40 ~ ~ ~ ~ - ~ ~ Clock 5 40 40 40 40 40 40 40 33 C. Set-up and Hold Times Relative to Clock (CP) Input. (Note 1) : zt Input cr: XK _ " Set-up Time Hold Time Set-up Time Hold Time Betore H ~L After H L Before L ~H After & -H A, B Source Address 15 2 (Note 3) 9. Note ~e 2 t Destination 15 Do Not Change (Note 2) 2 D - - 25 0 Cn - - 20 0 1012 - - 30 0 1345 - - 30 0 1678 10 Do Not Change (Note 2) 0 RAMO, 3, QO, 3 = = i 12 o D. Output Enable/Disable Times. Output disable tests performed with C_ = 5pF and measured to 0.5V change of output voitage level. Input Output Enable Disable OE Y 25 25 NOTES: 1. A dash indicates a propagation delay path or set-up time constraint does not exist, 2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation. This is indicated by the phrase 'do not change. 3. Source addresses must be stable prior to the clock H~L transition to allow time to access the source data before the latches close. The A address may then be changed. The B address could be changed if it is not a destina- tion; ie. if data is not being written back into the RAM. Normally A and B are not changed during the clock LOW time. 4. The set-up time prior to the clock L~H transition is to altow time for data to be accessed, passed through the ALU, and returned to the RAM. It includes all the time from stable A and B addresses to the clock L~H transition, regardiess of when the clock H~L transition occurs. 016568 -15 Refer to Page 13-1 for Essential Information on Military DevicesAm2901B/Am2901C SWITCHING TEST CIRCUIT A. THREE-STATE OUTPUTS B. NORMAL OUTPUTS C. OPEN-COLLECTOR OUTPUTS Veco & sv sv Sy Ay 5, Ry 5, Ry Your OO y- Your OO Your OO CL | 3K Ro | om | a Sy TC001080 71001090 TC001100 2.4V = 'oH .0-VpeE- VoL _ 5.0-Vee- Voi Ri = 5.0-VoL lo. + VoL/1K lo. + VoL/Re TOL a Notes: 1. CL =50pF includes scope probe, wiring and stray capacitances without device in test fixture. 2. Si, Sz, Sg are closed during function tests and all AC tasts except output enable tests. 3. S1 and Sg are closed while So is open for tpz} test. S1 and Sg are closed while Sg is open for tpz;, test. 4. C_=5.0pF for output disable tests. TEST OUTPUT LOADS FOR Am2901C (DIP) Pin # Pin Label Test Circuit Ry Ro 8 RAM3 A 560 1K 9 RAMp A 560 1K W F=0 Cc 270 - 16 Q3 A 560 1K 21 Qo A 560 1K 31 Fg B 620 3.9K 32 G B 220 1.5K 33 Ch+4 B 360 2.4K 34 OVR B 470 3K 35 P B 470 3K 36-39 Yo-3 A 220 1K 016568 -16 Refer to Page 13-1 for Essential Information on Military DevicesTTL INPUT/OUTPUT CURRENT INTERFACES 5 N So mh wo ~~ MET SCHOTTKY PNP > DRIVEN INPUT DRIVEN INPUT DRIVEN INPUT 3 Veo , ; N o he or fo Ra he a 5 ST = Te = R= = a= = = A= 45,7 10k co 8k Ca bo1,8.8 20k b 104 On, 3, RAM, 3 18k om = Aos,Boa 6h Do.3 10k 1G000430 C, =5.0pF, all inputs ! ~ THREE-STATE OPEN COLLECTOR OUTPUT OUTPUT $ 500 NOM 1 P| ton tou lo. 3 | GF o, 3, RAMo, 3 ve a F=o 1000440 Co =5.0pF, all outputs Figure 11. 016568 5-17 Refer to Page 13-1 for Essential Information on Military DevicesAm2901B/Am2901C LIFE TEST AND BURN-IN CIRCUIT FOR MILITARY CLASS B PARTS. Voc AN - ec mh I [, ]r0 | ie |s |s lhe L O.1uF MR CEP CET Po Po Ps Voc |, GNO Am9316 = 5 2 18 crock > ce Te % a, a Q3 4 3 12 W 18 "7 wa 19 20 6 Yee cp Gy 8, Bo 83 i 4 8 ) lg F=0 WA 28 13 560 27 J \4 e Ar za, 20 5 & WA 34 40 a Am2801 over AA ah 33 470 hk = 3 Casa Yee AA Fy a3 16 880 v4 RAMg r 2 |g 480 Q RAM Ww lg |) 17 Ch Og Dy Dy 03 16 Vee GND Az Ap Ay Ag Yo Yy YQ Y5 ke [? ? 1G 17 {5 {* |? {2 |5 10 ii 1 [2 [3 [a [36 [37 [38 [39 Voc ANN + + tT wo Voc = 5.0V cc [270 |270 [270 [270 Frequency = 100KHz +s > > Ta = 128C 1 <9 9F This circuit confarms to MIL-STD-883, method 1015, condition D. Yee TC001070 (Contact Factory for Commercial Burn-in Conditions) Figure 12. Notes on Testing incoming test procedures on this device should be carefully planned, taking into account the high complexity and power levels of the part. The following notes may be useful. 1. Insure the part is adequately decoupled at the test head. Large changes in Vcc current as the device switches may cause erroneous function failures due to Vcc changes. 2. Do not leave inputs floating during any tests, as they may start to oscillate at high frequency. 3. Do not attempt to perform threshold tests at high speed. Following an input transition, ground current may change by as much as 400mA in 5-8ns. Inductance in the ground cable For additional information o "Guidelines on Testing Am2900 Family Devices in the Bipolar Microprocessor Logic and Interface Data Book. may allow the ground pin at the device to rise by 100s of millivolts momentarily. 4, Use extreme care in defining input levels for AC tests. Many inputs may be changed at once, so there will be significant noise at the device pins and they may not actually reach Vi_ or Vix until the noise has settled. AMD recommends using Vi SOV and Viq 2 3.0V for AC tests. 5. To simplify failure analysis, programs should be designed to perform DC, Function, and AC tests as three distinct groups of tests. 6. To assist in testing, AMD offers complete documentation on our test procedures and, in most cases, can provide Fairchild Sentry programs, under license. Nn testing, see section 5-18 01656B Refer to Page 13-1 for Essential Information on Military Devices