ORT4622-8BM680I - Lattice Semiconductor Corporation

Advance Data Sheet

November 19 99

ORCA

® ORT4622 Field-Programmable System Chip (FPSC)

Four-Channel x 622 Mbits/s Backplane Transceiver

Introduction

Lucent Technolo

ies Microelectronics Group has

developed a soluti on for desi

ners who need the

man

advanta

es of FPGA-based desi

n implemen-

tation, coupled with hi

h-speed serial backplane data

transfer. The 622 Mbits/s backplane transceiver

offers a clockless, hi

h-speed interface for interde-

vice communication on a board or across a back-

plane. The built-in clock recover

of the OR T4622

allows for hi

her s

stem performance, easier-to-

desi

n clock domains in a multiboard s

stem, and

fewer si

nals on the backplane. Network desi

ners

will benefit from the backplane transceiver as a net-

work termination device. The backplane transceiver

offe rs SONET scramblin

/descramblin

of data and

streamlined SONET frami n

, pointer movin

and

transport overhead handlin

, pl us t h e pro

rammable

ic to terminate the network into proprietar

tems.

Embedded Core Features

■Implemented in an

ORCA

Series 3 FPGA arra

■Allows wide ran

e of applications for SONET net-

work termination application as well as

eneric

data movin

for hi

h-speed backplane data trans-

fer.

■Hi

h-speed interface (HSI) function for clock/data

recover

serial backplane data transfer without

external clocks.

■HSI function uses Lucent Technolo

ies Microelec-

tro nics Group’s proven 622 Mbits/s serial interface

core.

■Four-channel HSI function provides 622 Mbits/s

serial interface per channel for a total chip band-

width of 2.5 Gbits/s (full duplex).

■LVDS I/Os for HSI compliant with

EIA

*-644.

■8:1 data multiplexin

/demultiplexin

for 77.76 MHz

te-wide data processin

in FPGA lo

ic.

■On-chip phase-lock loop (PLL) clock meets B jitter

tolerance specification of ITU-T Recommendation

G.958.

■Powerdown option of HSI receiver on a per-

channel basis.

■Pseudo- SON ET prot oc ol inclu di n

A1/A2 framin

■SONET scramblin

and descramblin

for required

ones densi t

(optiona l) .

■Selected transport overhead (TOH) b

tes inse rtion

and extraction for interdevice communication via

the TOH serial link.

■Streamlined pointer processor (pointer mover) for

8 kHz frame ali

nment.

■FIFOs ali

n incomin

data across all four channels

for STS-48 operation (in quad STS-12 format).

■Independent data stream enables in pseudo-

SONET processor.

■Supports STS-12/STS-48 redundanc

either

software or hardware control for protection switch-

applications.

EIA

is a registered trademark of Electronic Industries Associa-

tion.

Table 1.

ORCA

ORT4622—Available FPGA Logic

†The embedded core and interface are not included i n the above gate counts. The usabl e gate count range f rom a logic-only gate count to

a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate c ount includes each PFU/SLIC (counted as

108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each o f the

four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are

counted at four gates per bit, with each PFU capable of im plementing a 32 x 4 RAM (or 512 gates) per PFU.

Device Usable

Gates†Number of

LUTs Number of

Registers Max User

RAM Max User

I/Os Array Size Number of

PFUs

ORT4622 60K—120K 4032 5304 64K 259 18 x 28 504

Table of Contents

Contents Page Contents Page

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies 2

Introduction.................................................................1

Embedded Core Features..........................................1

FPSC Highlights.........................................................4

Software Support................ ...... .................... ...... ....... .4

Description..................................................................5

What Is an FPSC? ..... ................... ...... ....... ...... ....... .5

FPSC Overview .......................................................5

FPSC Gate Counting ...............................................5

FPGA/Embedded Core Interface.............................5

ORCA

Foundry Developme nt Sy ste m .................... .5

FPSC Design Kit......................................................6

FPGA Logic Overview..............................................6

PLC Logic ................................................................6

PIC Logic .................................................................7

System Features......................................................7

Routing.....................................................................7

Configuration............................................................7

More Series 3 Information........................................7

ORT4622 Overview....................................................8

Device Layout ..........................................................8

Backplane Transceiver Interface .............................8

HSI Interface..........................................................10

STM Macrocell.......................................................10

CPU Interface ........................................................10

FPGA Interface......................................................10

FPSC Configuration...............................................10

Backplane Transceiver Core Detailed Description...12

HSI Macro..............................................................12

STM Transmitter (FPGA -> Backplane).................14

STM Receiver (Backplane -> FPGA).....................15

Powerdown Mode ..................................................21

Redundancy and Protection Switching ..................21

Memory Map.............................................................22

Definition of Register Types...................................22

Memory Map Overview..........................................23

Memory Map Bit Descriptions................................27

Absolute Maximum Ratings......................................32

Recommend Operating Conditions ..........................32

Electrical Characteristics ..........................................33

HSI Circuit Specifications .........................................35

Input Data . ................... ....... ...... ....... ...... ....... ...... ...35

Jitter Tolerance ......................................................35

Generated Output Jitter .........................................35

PLL.........................................................................35

Input Reference Clock............... ....... ...... ....... ...... ...35

LVDS I/O .................. ...... ....... ...... ....... ...... ....... ...... ...36

LVDS Receiver Buffer Requirements.....................37

Timing Characteristics..............................................38

Input/Output Buffer Measurement Conditions ..........46

FPGA Output Buffer Characteristics.........................47

Estimating Power Dissipation...................................48

Pin Information .........................................................49

Package Thermal Characteristics Summary ............73

ΘJA.........................................................................73

ψJC.........................................................................73

ΘJC ........................................................................73

ΘJB ........................................................................73

FPGA Maximum Junction Temperature.................73

Package Thermal Characteristics.............................74

Package Coplanarity ................................................74

Package Parasitics...................................................74

Package Outline Diagrams.......................................76

Terms and Definitions............................................76

432-Pin EBGA........................................................77

680-Pin PBGAM.....................................................78

Ordering Information.................................................79

Lucent Technologies Inc. 3

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Table of Contents (continued)

Figure Page Table Page

Figure 1.

ORCA

ORT4622 Block Diagram.................8

Figure 2. ORT4622 Array...........................................9

Figure 3. Architecture of ORT4622

Backplane Transceiver .......................................... 11

Figure 4. HSI Functional Block Diagram..................13

Figure 5. Byte Ordering of Input/Output Interface in

STS-12 Mode ........................ ....... ...... ....... ...... ...... 14

Figure 6. Framer Circuit ...........................................16

Figure 7. Interconnect of Streams for

FIFO Alignment ..................................................... 17

Figure 8. Alignment of Four STS-12 Streams..........17

Figure 9. Examples of Link Alignment...................... 18

Figure 10. Pointer Mover State Machine..................20

Figure 11. Transmit Parallel Port Timing

(Backplane -> FPGA) ............................................ 38

Figure 12. Transmit Transport Delay

(FPGA -> Backplane) ...........................................39

Figure 13. Receive Parallel Port Timing

(Backplane -> FPGA) ............................................ 40

Figure 14. Protection Switch Timing.........................41

Figure 15. TOH Input Serial Port Timing

(FPGA -> Backplane) ............................................ 42

Figure 16. TOH Output Serial Port Timing

(Backplane -> FPGA) ............................................ 43

Figure 17. CPU Write Transaction ...........................44

Figure 18. CPU Read Transaction........................... 45

Figure 19. ac Test Loads..........................................46

Figure 20. Output Buffer Delays...............................46

Figure 21. Input Buffer Delays..................................46

Figure 22. Sinklim (TJ = 25 °C, VDD = 3.3 V)............47

Figure 23. Slewlim (TJ = 25 °C, VDD = 3.3 V)...........47

Figure 24. Fast (TJ = 25 °C, VDD = 3.3 V) ................47

Figure 25. Sinklim (TJ = 125 °C, VDD = 3.0 V)..........47

Figure 26. Slewlim (TJ = 125 °C, VDD = 3.0 V)... ...... 47

Figure 27. Fast (TJ = 125 °C, VDD = 3.0 V) .............. 47

Figure 28. Package Parasitics .................................75

Table Page

Ta ble 1.

ORCA

ORT4622—Available FPGA Logic...1

Table 2. Valid Starting Positions for an STS-MC.....19

Table 3. SPE and C1J1 Functionality......................21

Table 4. Structural Register Elements..................... 22

Table 5. Memory Map..............................................23

Table 6. Memory Map Bit Descriptions....................27

Table 7. Absolute Maximum Ratings.......................32

Table 8. Recommend Operating Conditions............32

Table 9. Electrical Characteristics for FPGA I/O......33

Table 10. Electrical Characteristics for Embedded

Core I/O Other than LVDS I/O...............................34

Table 11. Jitter Tolerance.........................................35

Table 12. PLL ..........................................................35

Table 13. Input Reference Clock .............................35

Table 14. LVDS Driver dc Data................................36

Table 15. LVDS Driver ac Data................................36

Table 16. LVDS Receiver dc Data ...........................37

Table 17. LVDS Receiver ac Data ...........................37

Table 18. LVDS Receiver Power Consumption .......37

Table 19. LVDS Operating Parameters ...................37

Table 20. Timing Requirements

(Transmit Parallel Port Timing)..............................38

Table 21. Timing Requirements

(Transmit Transport Delay)....................................39

Table 22. Timing Requirements

(Receive Parallel Port Ti ming)...............................40

Table 23. Timing Requirements

(Protection Switch Timing) ....................................41

Table 24. Timing Requirements

(TOH Input Serial Port Timing)..............................42

Table 25. Timing Requirements

(TOH Output Serial Port Timing)...........................43

Table 26. Timing Requirements

(CPU Write Transaction) .......................................44

Table 27. Timing Requirements

(CPU Read Transaction).......................................45

Table 28. FPGA Common-Function

Pin Description.....................................................49

Table 29. FPSC Function Pin Description ...............52

Table 30. Embedded Core/FPGA

Interface Signal Description ..................................54

Table 31. Embedded Core/FPGA

Interface Signal Locations.....................................56

Table 32. 432-Pin EBGA Pinout ..............................58

Table 33. 680-Pin PBGAM Pinout ...........................64

Table 34.

ORCA

ORT4622 Plastic

Package Thermal Guidelines................................74

Table 35.

ORCA

ORT4622 Package Parasitics ......75

Table 36. Voltage Options .......................................79

Table 37. Temperature Options ...............................79

Table 38. Package Type Options.............................79

Table 39.

ORCA

Series 3+ Package Matrix ............79

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

4Lucent Technologies Inc.

Lucent Technologies Inc.

FPSC Highlights

■Implemented as an embedded core in the

ORCA

Series 3+ FPSC architecture.

■Allows the user to integrate the core with up to 120K

gates of programmable logic (all in one device) and

provides up to 242 user I/Os in addition to the

embedded core I/O pins.

■FPGA portion retains all of the features of the

ORCA

Series 3 FPGA architecture:

— High-performance, cost-effectiv e, 0.25 µm, 5-le vel

metal technology.

— Twin-quad programmable function unit (PFU)

architecture with eight 16-bit look-up tables

(LUTs) per PFU, organized in two nibbles for use

in nibble- or byte-wide functions. Allows for mixed

arithmetic and logic functions in a single PFU.

— Softwired LUTs (SWL) allow fast cascading of up

to three le vels of LUT logic in a single PFU.

— Supplemental logic and interconnect cell (SLIC)

provides 3-statable buffers, up to 10-bit decoder,

and

PAL

*-like AND-OR-INVERT (AOI) in each

programmable logic cell (PLC).

— Up to three ExpressCLK inputs allow extremely

fast clocking of signals on- and off-chip plus

access to internal general clock routing.

— Dual-use microprocessor interface (MPI) can be

used for configuration, as well as for a general-

purpose interface to the FPGA. Glueless interface

i960

† and

PowerPC

‡

processors with user-

configurable address space provided.

— Programmable clock manager (PCM) adjusts

clock phase and duty cycle for input clock rates

from 5 MHz to 120 MHz. The PCM may be com-

bined with FPGA logic to create complex

functio ns, such as digit al phas e- l ocked loop s,

frequen cy cou nter s, and frequenc y sy nth esizers

or clock doublers. Two PCMs are provided per

device.

— True internal 3-state, bidirectional buses with

simple control provided by the SLIC.

— 32 x 4 RAM per PFU, configurable as single or

dual port. Create large, fast RAM/ROM blocks

(128 x 8 in only eight PFUs) using the SLIC

decoders as bank drivers.

— Built-in boundary scan (

IEEE

1149.1 J TAG) and

TS_ALL testability function to 3-state all I/O pins.

■High-speed on-chip interface provided between

FPGA logic and embedded core to reduce bottle-

necks typically found when interfacing off-chip.

Software Support

■Supported by

ORCA

Foundry software and third-

party CAE tools for implementing

ORCA

Series 3+

devices and simulation/timing analysis with the

embedded core functions.

■Embedded core configuration options and simulation

netlists generated by FPSC Configuration Manager

utility.

PAL

is a trademark of Advanced Micro Devices, Inc.

†

i960

is a registered trademark of Intel Corporation.

‡

PowerPC

is a registered trademark of International Business

Machines Corporation.

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

Lucent Technologies Inc. 5

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Description

What Is an FPSC?

FPSCs, or field-programmable system chips, are

devices that combine field-programmable logic with

ASIC or mask-programmed logic on a single device.

FPSCs provide the time to market and flexibility of

FPGAs, the design effort savings of using soft intellec-

tual property (IP) cores, and the speed, design density,

and economy of ASICs.

FPSC Overview

Lucent’s Series 3+ FPSCs are created from Series 3

ORCA

FPGAs. To create a Series 3+ FPSC, several

rows of programmable logic cells (see FPGA Logic

Overview section for FPGA logic details) are removed

from a Series 3

ORCA

FPGA, and the area is replaced

with an embedded logic core. Other than replacing

some FPGA gates with ASIC gates, at greater than

10:1 efficiency, none of the FPGA functionality is

changed—all of the Series 3 FPGA capability is

retained: MPI, PCMs, boundary scan, etc. The rows of

programmable logic are replaced at the bottom of the

device, allowing pins on the bottom and sides of the

replaced rows to be used as I/O pins for the embedded

core. The remainder of the device pins retain their

FPGA functionality as do special function FPGA pins

within the embedded core area.

The embedded cores can take many forms and gener-

ally come from Lucent Technologies ASIC libraries.

Future offerings will allow customers to supply their

own core functions for the creation of custom FPSCs.

FPSC Gate Counting

The total gate count for an FPSC is the sum of its

embedded core (standard cell/ASIC gates) and its

FPGA gates. Because FPGA gates are generally

expressed as a usable range with a nominal value, the

total FPSC gate count is sometimes expressed in the

same manner . Standard-cell/ASIC gates are, however ,

10 to 25 times more silicon area efficient than FPGA

gates. Therefore, an FPSC with an embedded function

is gate equivalent to an FPGA with a much larger gate

count.

FPGA/ E mbedded Core Interface

The interface between the FPGA logic and the embed-

ded core is designed to look like FPGA I/Os from the

FPGA side, simplifying interface signal routing and pro-

viding a unified approach with general FPGA design.

Effectively, the FPGA is designed as if signals were

going off of the device to the embedded core, but the

on-chip interface is much faster than going off-chip and

requires less power. All of the delays for the interface

are precharacterized and accounted for in the

ORCA

Foundry Developm ent Sy st em.

Clock spines also can pass across the FPGA/embed-

ded core boundary. This allows for fast, low-skew

clocking between the FPGA and the embedded core.

Many of the special signals from the FPGA, such as

DONE and global set/reset, are also available to the

embedded core, making it possible to fully integrate the

embedded core with the FPGA as a system.

For even greater system flexibility, FPGA configuration

RAMs are available for use by the embedded core.

This allows for user-programmable options in the

embedded core, in turn allowing for greater flexibility.

Multiple embedded core configurations may be

designed into a single device with user-programmable

control over which configurations are implemented, as

well as the capability to change core functionality sim-

ply by reconfiguring the device.

ORCA

Foundry Development System

The

ORCA

Foundry Development System is used to

process a design from a netlist to a configured FPSC.

This system is used to map a design onto the

ORCA

architecture and then place and route it using

ORCA

Foundry’ s timing-driven tools. The development system

also includes interf aces to , and libraries for, other popu-

lar CAE tools for design entry, synthesis, simulation,

and timing analysis.

The

ORCA

Foundry Dev elopment System interf aces to

front-end design entry tools and provides the tools to

produce a configured FPSC. In the design flow, the

user defines the functionality of the FPGA portion of

the FPSC and embedded core settings at two points in

the design flow: at design entry and at the bit stream

generation stage. Following design entry, the develop-

ment system’ s map , place, and route tools translate the

netlist into a routed FPSC. A static timing analysis tool

is provided to determine device speed and a back-

annotated netlist can be created to allow simulation.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

6Lucent Technologies Inc.

Lucent Technologies Inc.

Description (continued)

Timing and simulation output files from

ORCA

F oundry

are also compatible with many third-party analysis

tools. Its bit stream generator is then used to generate

the configuration data which is loaded into the FPSC’s

internal configuration RAM.

When using the bit stream generator, the user selects

options that affect the functionality of the FPSC. Com-

bined with the front-end tools,

ORCA

Foundry pro-

duces configuration data that implements the various

logic and routing options discussed in this data sheet.

FPSC Design Kit

Development is facilitated by an FPSC Design Kit

which, together with

ORCA

Foundry and third-party

synthesis and simulation engines, provides all software

and documentation required to design and verify an

FPSC implementation. Included in the kit are the FPSC

Configuration Manager, HDL gate-level structural

netlists, all necessary synthesis libraries, and complete

online documentation. The kit's software couples with

ORCA

Foundry, providing a seamless FPSC design

environment. More information can be obtained by vis-

iting the

ORCA

website or contacting a local sales

office, both listed on the last page of this document.

FPGA Logic Overview

ORCA

Series 3 FPGA logic is a new generation of

SRAM-based FPGA logic built on the successful

Series 2 FPGA line from Lucent Technologies Micro-

electronics Group, with enhancements and innov ations

geared toward today’s high-speed designs on a single

chip. Designed from the start to be synthesis friendly

and to reduce place and route times while maintaining

the complete routability of the

ORCA

Series 2 devices,

the Series 3 more than doubles the logic available in

each logic block and incorporates system-lev el f eatures

that can further reduce logic requirements and

increase system speed.

ORCA

Series 3 devic es con-

tain many new patented enhancements and are off ered

in a variety of packages, speed grades, and tempera-

ture ranges.

ORCA

Series 3 FPGA logic consists of three basic ele-

ments: programmable logic cells (PLCs), programma-

ble input/output cells (PICs), and system-le vel features.

An array of PLCs is surrounded by PICs. Each PLC

contains a programmable function unit (PFU), a sup-

plemental logic and interconnect cell (SLIC), local rout-

ing resources, and configuration RAM. Most of the

FPGA logic is performed in the PFU, but decoders,

PAL

-like functions, and 3-state buffering can be per-

formed in the SLIC. The PICs provide device inputs

and outputs and can be used to register signals and to

perform input demultiplexing, output multiplexing, and

other functions on two output signals. Some of the sys-

tem-level functions include the new microprocessor

interface (MPI) and the programmable clock manager

(PCM).

PLC Logic

Each PFU within a PLC contains eight 4-input (16-bit)

look-up tables (LUTs), eight latches/flip-flops (FFs),

and one additional flip-flop that may be used indepen-

dently or with arithmetic functions.

The PFU is organized in a twin-quad fashion: two sets

of four LUTs and FFs that can be controlled indepen-

dently. LUTs may also be combined for use in arith-

metic functions using fast-carry chain logic in either

4-bit or 8-bit modes. The carry-out of either mode may

be registered in the ninth FF for pipelining. Each PFU

may also be configured as a synchronous 32 x 4

single- or dual-port RAM or ROM. The FFs (or latches)

may obtain input from LUT outputs or directly from

invertible PFU inputs, or they can be tied high or tied

low. The FFs also have programmable clock polarity,

clock enables, and local set/reset.

The SLIC is connected to PLC routing resources and to

the outputs of the PFU. It contains 3-state, bidirectional

buffers and logic to perform up to a 10-bit AND function

for decoding, or an AND-OR with optional INVERT

(AOI) to perform

PAL

-like functions. The 3-state drivers

in the SLIC and their direct connections to the PFU out-

puts make fast, true 3-state buses possible within the

FPGA logic, reducing required routing and allowing for

real-wor ld sy stem per for ma nce.

Lucent Technologies Inc. 7

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Description (continued)

PIC Logic

The Series 3 PIC addresses the demand for ever-

increasing system clock speeds. Each PIC contains

four programmable inputs/outputs (PIOs) and routing

resources. On the input side, each PIO contains a fast-

capture latch that is clocked by an ExpressCLK. This

latch is followed by a latch/FF that is clocked by a sys-

tem clock from the internal general clock routing. The

combination provides for very low setup requirements

and zero hold times for signals coming on-chip. It may

also be used to demultiplex an input signal, such as a

multiplexed address/data signal, and register the sig-

nals without explicitly building a demultiplexer. Two

input signals are available to the PLC array from each

PIO, and the

ORCA

Series 2 capability to use any input

pin as a clock or other global input is maintained.

On the output side of each PIO, two outputs from the

PLC array can be routed to each output flip-flop, and

logic can be associated with each I/O pad. The output

logic associated with each pad allows for multiplexing

of output signals and other functions of two output sig-

nals.

The output FF, in combination with output signal multi-

plexing, is particularly useful for registering address

signals to be multiplexed with data, allowing a full clock

cycle for the data to propagate to the output. The I/O

buffer associated with each pad is the same as the

ORCA

Series 3 buffer.

System Features

The Series 3 also provides system-level functionality

by means of its dual-use microprocessor interface

(MPI) and its innovative programmable clock manager

(PCM). These functional blocks allow for easy glueless

system interfacing and the capability to adjust to vary-

ing conditions in today’s high-speed systems. Since

these and all other Series 3 features are available in

every Series 3+ FPSC, they can also interface to the

embedded core providing for easier system integration.

Routing

The abundant routing resources of

ORCA

Series 3

FPGA logic are organized to route signals individually

or as buses with related control signals. Clocks are

routed on a low-skew, high-speed distribution network

and may be sourced from PLC logic, externally from

any I/O pad, or from the very fast ExpressCLK pins.

ExpressCLKs may be glitchlessly and independently

enabled and disabled with a programmable control sig-

nal using the StopCLK feature. The improved PIC rout-

ing resources are now similar to the patented intra-PLC

routing resources and provide great flexibility in moving

signals to and from the PIOs. This flexibility translates

into an improved capability to route designs at the

required speeds when the I/O signals have been

lock ed to s pecific pi ns.

Configuration

The FPGA logic’s functionality is determined by inter-

nal configuration RAM. The FPGA logic’s internal ini-

tialization/configuration circuitry loads the configuration

data at powerup or under system control. The RAM is

loaded by using one of several configuration modes,

including seri al EEPROM, the microprocessor inter-

face, or the embedded function core.

More Series 3 Information

For more information on Series 3 FPGAs, please refer

to the Series 3 FPGA data sheet, available on the

ORCA

worldwide website or by contacting Lucent

Technologies as directed on the back of this data

sheet.

88 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

ORT4622 Overview

Device Layout

The ORT4622 FPSC provides a high-speed backplane

transceiver combined with FPGA logic. The device is

based on a 2.5 V/3.3 V OR3L125B FPGA. The

OR3L125B has a 28 x 28 array of programmable logic

cells (PLCs). For the ORT4622, the bottom ten rows of

PLCs in the array were replaced with the embedded

backplane transceiver core. The ORT4622 embedded

core comprises the HSI macrocell, the synchronous

transport module (STM) macrocell, a CPU interface,

and LVDS I/Os. The four full-duplex channels perform

data transfer, scrambling/descrambling and framing at

the rate of 622 Mbits/s. Figure 1 shows the ORT4622

block diagram.

Figure 2 shows a schematic view of the ORT4622. The

upper portion of the device is an 18 x 28 array of PLCs

surrounded on the left, top, and right by programmable

input/output cells (PICs). At the bottom of the PLC

array are the core interface cells (CICs) connecting to

the embedded core region. The embedded core region

contains the backplane transceiver functionality of the

device. It is surrounded on the left, bottom, and right by

backplane transceiver dedicated I/Os as well as power

and special function FPGA pins. Also shown are the

interquad routing blocks (hIQ, vIQ) present in the

Series 3 FPGA devices. System-level functions

(located in the corners of the PLC array), routing

resources, and configuration RAM are not shown in

Figure 2.

Backplane Transceiver Interface

The advantage of the ORT4622 FPSC is to bring spe-

cific networking functions to an early market presence

with programmable logic in FPG A syst em.

The 622 Mbits/s backplane transceiver core allows the

ORT4622 to communicate across a backplane or on a

given board at an aggregate speed of 2.5 Gbits/s, pro-

viding a physical medium for high-speed asynchronous

serial data transfer between system devices. This

device is intended for , but not limited to, connecting ter-

minal equipment in SONET/SDH and ATM systems.

For networking applications, the ORT4622 offers a

SONET framer and scrambler/descrambler interface

capable of frame synchronization and insertion/extrac-

tion of selectable transport overhead bytes and

SONET scrambling and descrambling for four STS-12

(622 Mbits/s) channels. The channels are synchro-

nized to each other by a user provided 8 kHz frame

pulse. The ORT4622 also provides STS-48

(2.5 Gbits/s) operation across all four channels as long

as each channel is in STS-12 format. Figure 3 shows

the architecture of the ORT4622 backplane transceiver

core.

5- 8113(F)

Figure 1.

ORCA

ORT4622 Block Diagram

• CLOCK/DATA

RECOVERY

4 FULL-

DUPLEX

SERIAL

CHANNELS

BYTE-

WIDE

DATA FPGA LOGIC STANDARD

FPGA

I/Os

LVDS

622 Mbits/s

DATA

622 Mbits/s

DATA STM

• POINTER MOVER

• SCRAMBLING

• FIFO ALIGNMENT

• TOH P ROCES SOR

I/Os

HSI

Lucent Technologies Inc. 9

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

ORT4622 Overview (continued)

Figure 2. ORT4622 Array

IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII

PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 PT10 PT11 PT12 PT13 PT14 PT15 PT16 PT17 PT18 PT19 PT20 PT21 PT22 PT23 PT24 PT25 PT26 PT27 PT28

IIII

PL1

C1 R1

C2 R1

C3 R1

C4 R1

C5 R1

C6 R1

C7 R1

C8 R1

C9 R1

C10 R1

C11 R1

C12 R1

C13 R1

C14 R1

C15 R1

C16 R1

C17 R1

C18 R1

C19 R1

C20 R1

C21 R1

C22 R1

C23 R1

C24 R1

C25 R1

C26 R1

C27 R1

C28

PR1

IIII

PL2

C1 R2

C2 R2

C3 R2

C4 R2

C5 R2

C6 R2

C7 R2

C8 R2

C9 R2

C10 R2

C11 R2

C12 R2

C13 R2

C14 R2

C15 R2

C16 R2

C17 R2

C18 R2

C19 R2

C20 R2

C21 R2

C22 R2

C23 R2

C24 R2

C25 R2

C26 R2

C27 R2

C28

PR2

IIII

PL3

C1 R3

C2 R3

C3 R3

C4 R3

C5 R3

C6 R3

C7 R3

C8 R3

C9 R3

C10 R3

C11 R3

C12 R3

C13 R3

C14 R3

C15 R3

C16 R3

C17 R3

C18 R3

C19 R3

C20 R3

C21 R3

C22 R3

C23 R3

C24 R3

C25 R3

C26 R3

C27 R3

C28

PR3

IIII

PL4

C1 R4

C2 R4

C3 R4

C4 R4

C5 R4

C6 R4

C7 R4

C8 R4

C9 R4

C10 R4

C11 R4

C12 R4

C13 R4

C14 R4

C15 R4

C16 R4

C17 R4

C18 R4

C19 R4

C20 R4

C21 R4

C22 R4

C23 R4

C24 R4

C25 R4

C26 R4

C27 R4

C28

PR4

IIII

PL5

C1 R5

C2 R5

C3 R5

C4 R5

C5 R5

C6 R5

C7 R5

C8 R5

C9 R5

C10 R5

C11 R5

C12 R5

C13 R5

C14 R5

C15 R5

C16 R5

C17 R5

C18 R5

C19 R5

C20 R5

C21 R5

C22 R5

C23 R5

C24 R5

C25 R5

C26 R5

C27 R5

C28

PR5

IIII

PL6

C1 R6

C2 R6

C3 R6

C4 R6

C5 R6

C6 R6

C7 R6

C8 R6

C9 R6

C10 R6

C11 R6

C12 R6

C13 R6

C14 R6

C15 R6

C16 R6

C17 R6

C18 R6

C19 R6

C20 R6

C21 R6

C22 R6

C23 R6

C24 R6

C25 R6

C26 R6

C27 R6

C28

PR6

IIII

PL7

C1 R7

C2 R7

C3 R7

C4 R7

C5 R7

C6 R7

C7 R7

C8 R7

C9 R7

C10 R7

C11 R7

C12 R7

C13 R7

C14 R7

C15 R7

C16 R7

C17 R7

C18 R7

C19 R7

C20 R7

C21 R7

C22 R7

C23 R7

C24 R7

C25 R7

C26 R7

C27 R7

C28

PR7

IIII

PL8

C1 R8

C2 R8

C3 R8

C4 R8

C5 R8

C6 R8

C7 R8

C8 R8

C9 R8

C10 R8

C11 R8

C12 R8

C13 R8

C14 R8

C15 R8

C16 R8

C17 R8

C18 R8

C19 R8

C20 R8

C21 R8

C22 R8

C23 R8

C24 R8

C25 R8

C26 R8

C27 R8

C28

PR8

IIII

PL9

C1 R9

C2 R9

C3 R9

C4 R9

C5 R9

C6 R9

C7 R9

C8 R9

C9 R9

C10 R9

C11 R9

C12 R9

C13 R9

C14 R9

C15 R9

C16 R9

C17 R9

C18 R9

C19 R9

C20 R9

C21 R9

C22 R9

C23 R9

C24 R9

C25 R9

C26 R9

C27 R9

C28

PR9

IIII

PL10

R10

C1 R10

C2 R10

C3 R10

C4 R10

C5 R10

C6 R10

C7 R10

C8 R10

C9 R10

C10 R10

C11 R10

C12 R10

C13 R10

C14 R10

C15 R10

C16 R10

C17 R10

C18 R10

C19 R10

C20 R10

C21 R10

C22 R10

C23 R10

C24 R10

C25 R10

C26 R10

C27 R10

C28

PR10

IIII

PL11

R11

C1 R11

C2 R11

C3 R11

C4 R11

C5 R11

C6 R11

C7 R11

C8 R11

C9 R11

C10 R11

C11 R11

C12 R11

C13 R11

C14 R11

C15 R11

C16 R11

C17 R11

C18 R11

C19 R11

C20 R11

C21 R11

C22 R11

C23 R11

C24 R11

C25 R11

C26 R11

C27 R11

C28

PR11

IIII

PL12

R12

C1 R12

C2 R12

C3 R12

C4 R12

C5 R12

C6 R12

C7 R12

C8 R12

C9 R12

C10 R12

C11 R12

C12 R12

C13 R12

C14 R12

C15 R12

C16 R12

C17 R12

C18 R12

C19 R12

C20 R12

C21 R12

C22 R12

C23 R12

C24 R12

C25 R12

C26 R12

C27 R12

C28

PR12

IIII

PL13

R13

C1 R13

C2 R13

C3 R13

C4 R13

C5 R13

C6 R13

C7 R13

C8 R13

C9 R13

C10 R13

C11 R13

C12 R13

C13 R13

C14 R13

C15 R13

C16 R13

C17 R13

C18 R13

C19 R13

C20 R13

C21 R13

C22 R13

C23 R13

C24 R13

C25 R13

C26 R13

C27 R13

C28

PR13

IIII

PL14

R14

C1 R14

C2 R14

C3 R14

C4 R14

C5 R14

C6 R14

C7 R14

C8 R14

C9 R14

C10 R14

C11 R14

C12 R14

C13 R14

C14 R14

C15 R14

C16 R14

C17 R14

C18 R14

C19 R14

C20 R14

C21 R14

C22 R14

C23 R14

C24 R14

C25 R14

C26 R14

C27 R14

C28

PR14

IIII

PL15

R15

C1 R15

C2 R15

C3 R15

C4 R15

C5 R15

C6 R15

C7 R15

C8 R15

C9 R15

C10 R15

C11 R15

C12 R15

C13 R15

C14 R15

C15 R15

C16 R15

C17 R15

C18 R15

C19 R15

C20 R15

C21 R15

C22 R15

C23 R15

C24 R15

C25 R15

C26 R15

C27 R15

C28

PR15

IIII

PL16

R16

C1 R16

C2 R16

C3 R16

C4 R16

C5 R16

C6 R16

C7 R16

C8 R16

C9 R16

C10 R16

C11 R16

C12 R16

C13 R16

C14 R16

C15 R16

C16 R16

C17 R16

C18 R16

C19 R16

C20 R16

C21 R16

C22 R16

C23 R16

C24 R16

C25 R16

C26 R16

C27 R16

C28

PR16

IIII

PL17

R17

C1 R17

C2 R17

C3 R17

C4 R17

C5 R17

C6 R17

C7 R17

C8 R17

C9 R17

C10 R17

C11 R17

C12 R17

C13 R17

C14 R17

C15 R17

C16 R17

C17 R17

C18 R17

C19 R17

C20 R17

C21 R17

C22 R17

C23 R17

C24 R17

C25 R17

C26 R17

C27 R17

C28

PR17

IIII

PL18

R18

C1 R18

C2 R18

C3 R18

C4 R18

C5 R18

C6 R18

C7 R18

C8 R18

C9 R18

C10 R18

C11 R18

C12 R18

C13 R18

C14 R18

C15 R18

C16 R18

C17 R18

C18 R18

C19 R18

C20 R18

C21 R18

C22 R18

C23 R18

C24 R18

C25 R18

C26 R18

C27 R18

C28

PR18

IIII

ASB1 ASB2 ASB3 ASB4 ASB5 ASB6 ASB7 ASB8 ASB9 ASB10 ASB11 ASB12 ASB13 ASB14 ASB15 ASB16 ASB17 ASB18 ASB19 ASB20 ASB21 ASB22 ASB23 ASB24 ASB25 ASB26 ASB27 ASB28

EMBE DD E D CORE AREA

IIII

IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

10 Lucent Technologies Inc.

Lucent Technologies Inc.

ORT4622 Overview (continued)

HSI Interface

The high-speed interconnect (HSI) macrocell is used

for clock/data recovery and MUX/deMUX between

77.76 MHz byte-wide internal data buses and

622 Mbits/s e xternal serial links .

The HSI interface receives f our 622 Mbits/s serial input

data streams from the LVDS inputs and provides four

independent 77.76 MHz byte-wide data streams and

recovered clock to the STM macro. There is no require-

ment for bit alignment since SONET type framing will

take place inside the ORT4622 core. For transmit, the

HSI converts four byte-wide 77.76 MHz data streams to

serial streams at 622 Mbits/s at the LVDS outputs.

STM Ma crocell

The STM portion of the embedded core consists of

transmitter (Tx) and receiver (Rx) sections. The STM

receives four byte-wide data streams at 77.76 MHz and

the associated clock from the HSI. The incoming

streams are SONET framed and descrambled before

they are written into a FIFO which absorbs phase and

dela y variations and allows the shift to the system

clock. The TOH is then ex tracted and sent out on the

four serial ports. The pointer interpreter will then put

the synchronous transport signal (STS) synchronous

pa yload env elopes (SPE) into a small elastic store from

which the pointer generator will produce f our b yte-wide

STS-12 streams of data that are aligned to the system

timing pulse. Transmitted data for each channel is

received through a parallel bus and a serial port from

the FPGA circuit. T OH bytes are received from the

serial input port and can be optionally inserted from

programmable registers or serial inputs to the STS-12

frame via the TOH processor. Each of the four parallel

input buses is synchronized to a free-running system

clock. Then the SPE and T OH data is transf erred to the

HSI.

The STM macrocell also has a scrambler/descrambler

disable feature, allowing the user to disable the scram-

bler of the transmitter and the descrambler of the

receiver.

CPU Interface

The embedded core has a dedicated, asynchronous,

MPC860 compatible, CPU interface that is used for de-

vice setup, control, and monitoring. Dual sets of I/O pins

of this C P U interface with a bit st ream configurable

scheme provide designers a convenient and flexib le op-

tion for configuration. One set of CPU I/O pins goes off

chip allowing direct connection with an onboard CPU.

Another set of CPU I/O pins are available to the FPGA

logic allowing f or a stand-alone system free of an e xter-

nal CPU interface.

The CPU interface is composed of an 8-bit data bus, a

7-bit address bus, a chip select signal, a read/write sig-

nal, and an interrupt signal.

FPGA Interface

The FPGA logic will receive/transmit frame aligned

streams of 77.76 MHz data (maximum of four streams

in each direction) from/to the backplane transceiver

embedded core. All frames transmitted to the FPGA

will be aligned to the FPGA frame pulse which will be

provided by the FPGA user’s logic to the STM macro.

All frames received from the FPGA logic will be aligned

to the system frame pulse that will be supplied to the

STM macro from the FPGA user’s logic.

FPSC Configuration

Configuration of the ORT4622 occurs in two stages,

FPGA bit stream configuration and embedded core

setup.

FPGA Configuration

The FPGA logic is configured by standard FPGA bit

stream configuration means as discussed in the Series

3 FPGA data sheet. Additionally, for the ORT4622, the

location of the CPU interface to the embedded core,

either on the device pins or at the FPGA/embedded

core boundary, is configured via FPGA configuration

and is defined via the ORT4622 design kit.

Embedded Core Setup

The embedded core operation is set up via the embed-

ded core CPU of the interface. All options for the oper-

ation of the core are configured according to the device

tion of this data sheet.

Lucent Technologies Inc. 11

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

ORT4622 Overview (continued)

5-8576 (F)

Figure 3. Architecture of ORT4622 Backplane Transceiver

TX TOH

PROCESSOR FRAME

PROC. TX CH A

(MACRO)

TX TOH

PROCESSOR FRAME

PROC. TX CH B

(MACRO)

TX TOH

PROCESSOR FRAME

PROC. TX CH D

(MACRO)

TX TOH

PROCESSOR FRAME

PROC. TX CH C

(MACRO)

LINE LBPK

(SOFT CTL)

TO RX TOH PROC. QUAD CHANNEL

TRANSMITTER

PLL

RX CH A

(MACROCELL)

77.76

MHz

FIFO

POINTER

MOVER

STS48

CH A

RX CH B

(MACROCELL)

77.76

MHz

CH B

RX CH C

(MACROCELL)

77.76

MHz

CH C

RX CH D

(MACROCELL)

77.76

MHz

CH D

LVDS LPBK

(SOFT CTL)

SOFT CTL

DEVICE I/O

RX TOH

PROCESSOR

TOH CLK

QUAD CHANNEL

RECEIVER

CH A

CH B

SOFT CTL

CH C

CH D

SOFT CTL

TOH RX B

TOH RX C

TOH RX D

RX TOH FRAME

TOH CLK

TX TOH CLK ENA

TOH TX A

TOH TX B

INPUT BUS A

TX BUS B

TOH TX C

TX BUS C

TOH TX D

TX BUS D

SYSTEM FRAME

LINE FRAME

PROT SWITCH A/B

DATA RX BUS A

DATA RX BUS B

PROT SWITCH C/D

DATA RX BUS C

LVDS

OUT A

LVDS

OUT B

LVDS

OUT C

LVDS

OUT D

LVDS

IN A

LVDS

IN B

LVDS

IN C

LVDS

IN D

FPGA I/F SIGNALS

CPU INTERFACE (ASYNC)

INT_N

DATA

ADDR

RD/WR_N

CS_N

RST_N

DEVICE I/O OR FPGA I/F SIGNALS (BIT STREAM SELECTABLE)

SOFT CTL

RX TOH CLK ENA

622 MHz Clks

REF

FDBK

77.76

MHz

622 MHz

77.76

MHz

FRAME

CLOCK

TOH RX A

TOH_EN

SYSTEM CLOCK

(77.76 MHz)

1212 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Backplane Transceiver Core Detailed

Description

HSI Macro

The high-speed interface (HSI) provides a physical

medium for high-speed asynchronous serial data trans-

fer between the ORT4622 and other devices. The

devices can be mounted on the same board or

mounted on different boards and connected through

the shelf backplane. The 622 Mbits/s CDR macro is a

four-channel clock phase select (CPS) and data retime

function with serial to parallel demultiplexing for the

incoming data stream and parallel to serial multiplexing

for outgoing data. The HSI macro consists of three

functionally independent blocks: receiver, transmitter,

and PLL synthesizer as shown in Figure 4.

The PLL synthesizer block receives a 77.76 MHz refer-

ence clock at its input, and provides a phase-locked

622.08 MHz clock to the transmitter block and phase

control signal to the receiver block. The PLL synthe-

sizer block is a comm on asset shared by four rec ei ve

and transmit channels.

The HSI receiver receives four channels of differential

622.08 Mbits/s serial data without clock at its LVDS

receive inputs. The received data must be scrambled,

conforming to SONET STS-12 and SDH STM-4 data

formats using either a PN7 or PN9 sequence. The PN7

characteristic polynomial is 1 + x6 + x7 and PN9 char-

acteristic polynomial is 1 + x4 + x9. The clock phase

select and data retime (CPS/DR) module performs a

clock recovery and data retiming function by using

phase control information. The resultant 622.08 Mbits/s

data and clock are then passed to the deserializer

module, which performs serial to parallel conversion

and provides a 77.76 Mbits/s parallel data and clock at

its output.

The HSI transmitter receives four channels of

77.76 Mbits/s parallel data that is synchronous to the

reference clock at its inputs. The serializer performs a

parallel to serial conversion using a 622.08 MHz clock

provided by the PLL/synthesizer block. The

622 Mbits/s serial data streams are then transmitted

through the LVDS drivers.

Lucent Technologies Inc. 13

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Backplane Transceiver Core Detailed Description (continued)

5-8592 (F)

Figure 4. HSI Functional Block Diagram

622.08 MHz

PLL

SYNTHESIZER

50 Ω

LOOPBKEN

CLOCK/DATA

ALIGNMENT

PHASE

ADJUSTMENT

DEMUX

622 Mbits/s SERIAL TO

78 MHz PARALLEL

LOOP-

BACKHSI_RX

622 Mbits/s

DATA

622 MHz

CLOCK

MUX

78 MHz PARALLEL

TO 622 Mbits/s SERIAL

BS-MUX

100 Ω

LOOP-

BACK

HDOUT

622 Mbits/s

622.08 MHz

CLOCK

HSI_TX

622 Mbits/s

DATA

(77.76 MHz REF CLOCK)

REF78

REXT

(RESISTOR)

622 Mbits/s

DATA

LVDS

BUFFER

(77.76 Mbytes DATA)

(77.76 Mbits/s

DATA)

(77.76 MHz

CLOCK)

77.76 MHz

77.76 Mbytes DATA

BSCANEN

HDIN

622 Mbits/s

LVDS

BUFFER

SELECT

BOUNDARY-

SCAN

CONTROL

1414 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Backplane Transceiver Core Detailed

Description (continued)

STM Transmitter (FPGA -> Backplane)

The STM has four STS-12 transmit channels which can

be treated as a single STS-48 channel. In general, the

transmitter circuit receives four byte-wide 77.76 MHz

data from the FPGA which nominally represents four

STS-12 streams (A, B, C, and D). This data is synchro-

nized to the system (reference) clock and an 8 kHz

system frame pulse from the FPGA logic. Transport

overhead bytes are then optionally inserted into these

streams and the streams are forwarded to the HSI. All

byte timing pulses required to isolate individual over-

head bytes (e.g., A1, A2, B1, D1—D3, etc.) are gener-

ated internally based on the system frame pulse

(SYS_FP) received from the FPGA logic. All streams

operate byte-wide at 77.76 MHz in all modes. The TOH

processor operates from 25 MHz to 77.76 MHz and

supports the following TOH signals: A1 and A2 inser-

tion and optional corruption; H1, H2, and H3 pass

transparently; BIP-8 parity calculation (after scram-

bling) and B1 byte insertion and optional corruption

(before scrambling); optional K1 and K2 insert; optional

S1/M0 insert; optional E1/F1/E2 insert; optional section

and line data communication channel (DCC, D1—D3)

insertion (for intercard communications channel);

scrambling of outgoing data stream with optional

scram ble r dis ab li ng; optional strea m disabl ing .

When the ORT4622 is used in nonnetworking applica-

tions as a generic high-speed backplane data mover,

the TOH serial ports are unused or can be used for

slow-speed off-channel communication between

devices. Data received on the parallel bus is optionally

scrambled and transferred to LVDS outputs.

Byte Ordering Information

The core supports quad STS-12 mode of operation on

the input/output ports. STS-48 is also supported when

received in quad STS-12 format. When operating in

quad STS-12 mode, each of the independent byte

streams carries an entire STS-12 within it. Figure 5

reveals the byte ordering of the individual STS-12

streams and for STS-48 operation.

5-8574 (F)

Figure 5. Byte Ordering of Input/Output Interface in STS-12 Mode

1, 12

2, 12

3, 12

4, 12

1, 9

2, 9

3, 9

4, 9

1, 6

2, 6

3, 6

4, 6

1, 3

2, 3

3, 3

4, 3

1, 11

2, 11

3, 11

4, 11

1, 8

2, 8

3, 8

4, 8

1, 5

2, 5

3, 5

4, 5

1, 2

2, 2

3, 2

4, 2

1, 10

2, 10

3, 10

4, 10

1, 7

2, 7

3, 7

4, 7

1, 4

2, 4

3, 4

4, 4

1, 1

2, 1

3, 1

4, 1

STS-12 #1

STS-12 #2

STS-12 #3

STS-12 #4

STS-12 #1

STS-12 #2

STS-12 #3

STS-12 #4

STS-48 IN QUAD STS-12 FORMAT

QUAD STS- 12

Lucent Technologies Inc. 15

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Backplane Transceiver Core Detailed

Description (continued)

Transport Overhead Insertion (Serial Link)

The TOH serial links are used to insert TOH bytes into

the transmit data. The transmit TOH data and

TOH_CLK_EN get retimed by TOH_CLK in order to

meet setup and hold specifications of the device.

The retimed TOH data is shifted into a 288-bit (32-bit

by 9-bit) shift register and then multiplexed as an 8-bit

bus to be inserted into the byte-wide data stream.

Insertion or passthrough of TOH is under software con-

trol.

A1/A2 Frame Insert and Testing

All 12 A1 bytes of each STS-12 are set to 0xF6 and all

12 A2 bytes of the STS-12 are set to 0x28 when not

overridden with a user-specified value for testing.

A1/A2 testing (corruption) is controlled per stream by

the A1/A2 error insert register. When A1/A2 corruption

detection is set for a particular stream, the A1/A2 val-

ues in the corrupted A1/A2 value registers are sent for

the number of frames defined in the corrupted A1/A2

frame count register. When the corrupted A1/A2 frame

count register is set to zero, A1/A2 corruption will con-

tinue until the A1/A2 error insert register is cleared.

On a per-device basis, the A1 and A2 byte values are

set, as well as the number of frames of corruption.

Then, to insert the specified A1/A2 values, each chan-

nel has an enable register . When the enable register is

set, the A1/A2 values are corrupted for the number

specified in the number of frames to corrupt. To insert

errors again, the per-channel fault insert register must

be cleared, and set again. Only the last A1 and the first

A2 are corrupted.

B1 Calculation and Insertion

The B1 calculation block computes a BIP-8 code, using

even parity over all bits of the previous STS-12 frame

after scrambling and is inserted in the B1 byte of the

current STS-12 frame before scrambling. Per-bit B1

corruption is controlled by the force BIP-8 corruption

inverted before insertion into the B1 byte position.

Each stream has an independent fault insert register

that enables the inversion of the B1 bytes. B1 bytes in

all other STS-1s in the stream are filled with zeros.

Stream Disable

When disabled via the appropriate bit in the stream

enable register, the prescrambled data for a stream is

set to all ones, feeding the HSI. The HSI macro is pow-

ered down on a per-stream basis, as are its LVDS out-

puts.

Scrambler

The data stream is scrambled using a frame synchro-

nous scrambler of sequence length 127. The scram-

bling function can be disabled by software. The

generating polynomial for the scrambler is 1 + x6 + x7.

This polynomial conforms to the standard SONET

STS-12 data format. The scrambler is reset to 1111111

on the first byte of the SPE (byte following the Z0 byte

in the twelfth STS-1). That byte and all subsequent

bytes to be scrambled are exclusive ORed, with the

output from the byte-wise scrambler. The scrambler

runs continuously from that byte on throughout the

remainder of the frame. A1, A2, J0, and Z0 bytes are

not scrambled.

STM Receiver (Backplane -> FPGA)

The ORT4622 has four receiving channels that can be

treated as one STS-48 stream, or treated as indepen-

dent channels. Incoming data is received through

LVDS serial ports at the data rate of 622 Mbits/s. The

receiver can handle the data streams with frame off-

sets of up to ±12 bytes. The received data streams are

processed in the HSI and the STM, then passed

through the CIC boundary to the FPGA logic.

16 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advanced Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Backplane Transceiver Core Detailed Description (continued)

Framer Block

The framer block, in Figure 6, takes byte-wide data from the HSI, and outputs a byte-aligned, byte-wide data

stream and 8 kHz sync pulse. The framer algorithm determines the out-of-frame/in-frame status of the incoming

data and will cause interrupts on both an errored frame and an out-of-frame (OOF) state. The framer detects the

A1/A2 framing pattern and generates the 8 kHz frame pulse. When the framer detects OOF, it will generate an

interrupt. Also, the framer detects an errored frame and increments an A1/A2 frame error counter . The counter can

be monitored by a processor to compile performance status on the quality of the backplane.

Because the ORT4622 is intended for use between another ORT4622 or other devices via a backplane, there is

only one errored frame state. Thus after two transitions are missed, the state machine goes into the OOF state and

there is no severely errored frame (SEF) or loss-of-frame (LOF) indication.

5-8582 (F)

Figure 6. Framer Circuit

IF OOF STATE:

FREEZE A1 OFFSET

WHEN = F6, OR USE

PREVIOUS OFFSET.

IF ~OOF STATE:

USE PREVIOUS OFFSET.

DATA IN 87

8ALIGNED

COMPARE TO A1A2

TRANSITION. F628

AND ON SUCCESS: ISSUE

8 kHz FP GO TO FRAME

DATA

A1 SEARCH A1A2 TRANSITION SEARCH

ALIGNED DATA OUT

8 kHz FP

STATE CONTROL

COUNTER SET

CONFIRM.

B1 Calculate and Descramble (Backplane -> FPGA)

Each Rx block receives byte- wide scrambled

77.76 MHz data and a frame sync from the framer.

Since each HSI is independently clocked, the Rx block

operates on individual streams. Timing signals required

to locate overhead bytes to be extracted are generated

internally based on the frame sync. The Rx block pro-

duces byte-wide (optionally) descrambled data and an

output frame sync for the alignment FIFO block.

The B1 calculation block computes a BIP-8 code, using

even parity over all bits of the previous STS-12 frame

before descrambling and this value is checked against

the B1 byte of the current frame after descrambling. A

per-stream B1 error counter is incremented for each bit

that is in error. The error counter may be read via the

CPU interface.

Descrambling. The streams are descrambled using a

frame synchronous descrambler of sequence length

127 with a generating polynomial of 1 + x6 + x7. The

section trace byte (J0) and the growth bytes (Z0) are

not descrambled. The descrambling function can be

disabled by software.

AIS-L Insertion. If enabled in the AIS_L force register,

AIS-L is inserted into the received frame by writing all

ones for all bytes of the descrambled stream.

Lucent Technologies Inc. 17

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Back

lane Transceiver Core Detailed

Descri

tion (continued)

AIS-L Insertion on Out-of-Frame. If enabled via the

writing all ones for all bytes of the descrambled stream

when the framer indicates that an out-of-frame condi-

tion exists.

Internal Parit

Generation

Even parity is generated on all data bytes and is routed

in parallel with the data to be checked before the pro-

tection switch MUX at the parallel output.

FIFO Ali

nment

(

Back

lane -> FPGA

)

The alignment FIFO allows the transfer of all data to

the system clock. The FIFO sync block (Figure 7)

allows the system to be configured to allow the frame

alignment of multiple slightly varying data streams.

This optional alignment ensures that matching STS-12

streams will arrive at the FPGA end in perfect data

sync. The frame alignment is configurable to allow for

the possibility of fully independent (i.e., total frame mis-

alignment) STS-12s.

5-8577 (F)

ure 7. Interconnect of Streams for FIFO Ali

nment

The incoming data from the clock and data recovery can be separated into four STS-12 channels (A, B, C, and D).

These streams can be frame aligned in the patterns shown in Figure 8.

5-8575 (F)

ure 8. Ali

nment of Four STS-12 Streams

There is also a provision to allow certain streams to be disabled (i.e., not producing interrupts or affecting synchro-

nization). These streams can be enabled at a later time without disrupting other streams.

The FIFO block consists of a 24 by 10-bit FIFO per link. This FIFO is used to align up to ±154.3 ns of interlink skew

and to transfer to the system clock. The FIFO sync circuit takes metastable hardened frame pulses from the write

control blocks and produces sync signals which indicate when the read control blocks should begin reading from

the first FIFO location. On top of the sync signals this block produces an error indicator which indicates that the sig-

nals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). Sync and error signals are sent

to read control block for alignment. The read control block is synched only once on start-up, any further synchroni-

zation is S/W controlled. The action of resynching a read control block will always cause a data hit. A S/W register

allows the read control block to be resynched.

STS-12

STREAM A

STS-12

STREAM B

STS-12

STREAM C

STS-12

STREAM D

FIFO

SYNC

STREAM A

STREAM B

STREAM C

STREAM D

STREAM A

STREAM B

STREAM C

STREAM D

1818 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Backplane Transceiver Core Detailed

Description (continued)

Link Alignment. The general operation of the link

alignment algorithm is to wait 12 clocks (i.e., half the

FIFO) from the arriving frame pulse and then signal the

read control block to begin reading. For perfectly

aligned frame pulses across the links, it is simply a

matter of counting down 12 and then signaling the read

control block.

The algorithm down counts by one until all of the frame

pulses have arrived and then by two when they are all

present. For example (Figure 9), if all pulses arrive

together then alignment algorithm would count 24

(12 clocks); if, however, the arriving pulses are spread

out over four clocks, then it would count one for the first

four pulses and then two per clock afterward which

gives a total of 14 clocks between first frame pulse and

the first read. This puts the center of arriving frame

pulses at the halfway point in the buffer. This is the

extent of the algorithm and it has no facility for actively

correcting problems once they occur.

The write control block receives byte-wide data at

77.76 MHz and a frame pulse two clocks before the

first A1 byte of the STS-12 frame. It generates the write

address for the FIFO block. The first A1 in every STS-

12 stream is written in the same location (address 0) in

the FIFO. Also, a frame bit is passed through the FIFO

along with the first byte before the first A1 of the STS-

12. The read control block synchronizes the reading of

the FIFO for streams that are to be aligned. Reading

begins when the FIFO sync signals that all of the appli-

cable A1s and the appropriate margin have been writ-

ten to the FIFO. All of the read blocks to be

synchronized begin reading at the same time and

same location in memory (address 0).

The alignment algorithm takes the difference between

read address and write address to indicate the relative

clock align men ts between STS-12 str eam s. If this

depth indication exceeds certain limits (12 clocks), then

an interrupt is given to the microprocessor (alignment

overflow). Each STS-12 stream can be realigned by

software if it gets too far out of line (this would cause a

data hit).

5-8584 (F)

Figure 9. Examples of Link Alignment

Pointer Mover Block (Backplane -> FPGA)

The pointer mover maps incoming frames to the line framing that is supplied by the FPGA logic. The K1/K2 bytes

and H1-SS bits are also passed through to the pointer generator so that the FPGA can receive them. The pointer

mover handles both concatenations inside the STS-12, and to other STS-12s inside the core.

24-byte

FIFO 24-byte

FIFO

ALL FPs

12 CLOCKS

SYNC. PULSEARRIVE

TOGETHER

(WRITING

BEGINS)

(READING

BEGINS)

SYNC. PULSE

(READING

BEGINS)

LAST FP

ARRIVES

4 CLOCKS

FIRST FP

ARRIVES

(WRITING

BEGINS)

10 CLOCKS

PERFECTLY ALIGNED FRAMES 4-byte SPREAD IN ARRIVING FRAMES

Lucent Technologies Inc. 19

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Backplane Transceiver Core Detailed Description (continued)

The pointer mover block can correctly process any length of concatenation of STS frames (multiple of three) as

long as it begins on an STS-3 boundary (i.e., STS-1 number one, four, seven, 10, etc.) and is contained within the

smaller of STS-3, 12, or 48. See details in Table 2.

Table 2. Valid Starting Positions for an STS-MC

STS-1

Number STS-3cSPE STS-6cSPE STS-9cSPE STS-12cSPE STS-15cSPE STS-18c to

STS-48c

SPEs

1 YES YES YES YES YES YES

4 YES YES YES NO YES —

7 YES YES NO NO YES —

10 YES NO NO NO YES —

13 YES YES YES YES YES —

16 YES YES YES NO YES —

19 YES YES NO NO YES —

22 YES NO NO NO YES —

25 YES YES YES YES YES —

28 YES YES YES NO YES —

31 YES YES NO NO YES —

34 YES NO NO NO YES NO

37 YES YES YES YES NO NO

40 YES YES YES NO NO NO

43 YES YES NO NO NO NO

46 YES NO NO NO NO NO

Note: YES = STS- Mc SPE can start in that STS -1.

NO = STS-Mc SPE cannot start in that S T S-1.

— = YES or NO, depending on the particular value of M.

Pointer Interpreter State Machine. The pointer inter-

preter’s highest priority is to maintain accurate dataflow

(i.e., valid SPE only) into the elastic store. This will

ensure that any errors in the pointer value will be cor-

rected by a standard, fully SONET compliant, pointer

interpreter without any data hits. This means that error

checking for increment, decrement, and new data flag

(NDF) (i.e., eight of 10) are maintained in order to

ensure accurate dataflow. A single valid pointer

(i.e., 0—782) that differs from the current pointer will be

ignored. Two consecutive incoming valid pointers that

differ from the current pointer will cause a reset of the

J1 location to the latest pointer value (the generator will

then produce an NDF). This block is designed to han-

dle single bit errors without affecting dataflow or chang-

ing state.

The pointer interpreter has only three states (NORM,

AIS, and CONC). NORM state will begin whenever two

consecutive NORM pointers are received. If two con-

secutive NORM pointers are received that both differ

from the current offset, then the current offset will be

reset to the last received NORM pointer. When the

pointer interpreter changes its offset it causes the

pointer generator to receive a J1 value in a new posi-

tion. When the pointer generator gets an unexpected

J1 it resets its offset value to the new location and

declares an NDF. The interpreter is only looking for two

consecutive pointers that are different from the current

value. These two consecutive NORM pointers do not

have to have the same value. For example, if the cur-

rent pointer is ten and a NORM pointer with offset of 15

and a second NORM pointer with offset of 25 are

received, then the interpreter will change the current

pointer to 25. The receipt of two consecutive CONC

pointers causes CONC state to be entered. Once in

this state offset values from the head of the concatena-

tion chain are used to determine the location of the

STS SPE for each STS in the chain. Two consecutive

AIS pointers cause the AIS state to occur. Any two con-

secutive normal or concatenation pointers will end this

AIS state. This state will cause the data leaving the

pointer generator to be overwritten with 0xFF.

20 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advanced Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Backplane Transceiver Core Detailed Description (continued)

5-8589 (F)

Figure 10. Pointer Mover State Machine

NORM

CONC AIS

2 x CONC

2 x NORM

2 x AIS

2 x CONC

2 x AIS

Pointer Generator. The pointer generator maps the

corresponding bytes into their appropriate location in

the outgoing byte stream. The generator also creates

offset pointers based on the location of the J1 byte as

indicated by the pointer interpreter. The generator will

signal NDFs when the interpreter signals that it is com-

ing out of AIS state. The pointer generator resets the

pointer value and generates NDF every time a byte

marked J1 is read from the elastic store that doesn’t

match the previous offset.

Increment and decrement signals from the pointer

interpreter are latched once per frame on either the F1

or E2 byte times (depending on collisions), this ensures

constant values during the H1 through H3 times. The

choice of on which byte time to do the latching is made

once when the relative frame phases (i.e., received

and system) are determined. This latch point is then

stable unless the relative framing changes and the

received H byte times collide with the system F1 or E2

times in which case the latch point would be switched

to the collision free byte time.

There is no restriction on how many or how often incre-

ments and decrements are processed. Any received

increment or decrement is immediately passed to the

generator for implementation regardless of when the

last pointer adjustment was made. The responsibility

for meeting the SONET criteria for max frequency of

pointer adjustments is left to an upstream pointer pro-

cessor.

When the interpreter signals an AIS state, the genera-

tor will immediately begin sending out 0xFF in place of

data and H1, H2, H3. This will continue until the inter-

preter returns to NORM or CONC (pointer mover state

machine) states and a J1 byte is received.

Transport Overhead Extraction

Transport overhead is extracted from the receive data

stream by the TOH extract block. The incoming data

gets loaded into a 36-byte shift register on the system

clock domain. This in turn is clocked onto the T OH

clock domain at the start of the SPE time, where it can

be clocked out.

During the SPE time, the receiver TOH frame pulse is

generated, RX_TOH_FP, which indicates the start of

the row of 36 TOH bytes. This pulse, along with the

receive TOH clock enable, RX_TOH_CK_EN, as well

as the T OH data, are all launched on the rising edge of

the TOH clock TOH_CLK.

Special TOH Byte Functions

K1 and K2 Handling. K1 and K2 bytes can be option-

ally passed through the pointer mover under software

control, or can set to zero with the other TOH bytes.

A1 and A2 Handling. A1 and A2 b ytes are always

regenerated and set to hexadecimal F6 and 28,

respectively.

Lucent Technologies Inc. 21

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Backplane Transceiver Core Detailed Description (continued)

SPE and C1J1 Outputs. These two signals f or each channel are passed to the FPGA logic to allow a pointer pro-

cessor or other function to extract payload without interpreting the pointers. F or the ORT4622, each frame has 12

STS-1s. In the SPE region, there are 12 J1 pulses for each STS-1s. There is one C1(J0) pulse in the TOH area for

one frame since all 12 STS-1s share the same row of TOH. Thus, there is a total of 12 J1 pulses and one C1(J0)

pulse per frame. C1(J0) pulse is coincident with the J0 of STS1 #1. In each frame, the SPE flag is active when the

data stream is in SPE area. SPE behavior is dependent on pointer mov ement and concatenation. Note that in the

T OH area, H3 can also carry valid data. When v alid SPE data is carried in this H3 slot, SPE is high in this particular

TOH time slot. In the SPE region, if there is no valid data during any SPE column, the SPE signal will be set to low.

SPE allow a pointer processor to extract pa yload without interpreting the pointers. The SPE and C1J1 functionality

are described in Table 3.

Table 3. SPE and C1J1 Functionality

Note: The following rules must be observed for generating SPE and C1J1 signals: on occurrence of AIS-P on any of the STS-1, there must be

no corresponding J1 pulse. In case of concatenated payloads (up to STS48c), only the head STS-1 of the group must have an associated

J1 pulse. C1J1 signal must track any pointer movements. During a negative justification event, SPE must be set high during the H3 byte

to indicate that payload data is available. During a positive justification event, SPE must be set low during the positive stuff opportunity

byte to indicate that payload data is not available.

SPE C1J1 Description

0 0 TOH information excluding C1(J0) of STS1 #1

0 1 Position of C1(J0) of STS1 #1

1 0 SPE information excluding the 12 J1 bytes

1 1 Position of the 12 J1 bytes

Powerdown Mode

Powerdown mode will be entered when the corre-

sponding channel is disabled. Channels can be inde-

pendently enabled or disabled under software control.

Parallel data bus output enable and TOH serial data

output enable signals are made available to the FPGA

logic. The outputs can be 3-stated when the corre-

sponding channel is disabled. The HSI macrocell’s cor-

responding channel is also powered down. The device

will power up with all four channels in powerdown

mode.

In addition, an L VDS_EN pin has been added to control

the LVDS pins during boundary scan. During functional

operation, enabling/disabling LVDS buffers is con-

trolled by software registers. When in boundary scan

mode, LVDS_EN controls the enabling/disabling of

LVDS buffers instead of softw are registers. This

LVDS_EN pin should be pulled high on the board for

functional operation, and pulled low during boundary

scan.

Redundancy and Protection Switching

The ORT4622 supports STS-12/STS-48 redundancy

by either software or hardware control for protection

switchi ng appl icat ions. For the transmitter mode, no

additional functionality is required for redundant opera-

tion. For receiving data, STS-12 data redundancy can

be implemented within the same device; while STS-48

data stream requires multiple devices to support redun-

dancy .

In STS-12 mode, the channel A receive data bus port is

used for both channel A and channel B. Similarly, the

channel C receive data bus port is used for both chan-

nel C and channel D. Channel B and channel D

become the redundant channels. The channel B and

channel D receive data bus ports are unused. Soft reg-

isters provide independent control to the protection

switching MUXes for both parallel data ports and serial

TOH data ports. When direct hardware control for pro-

tection switching is needed, external protection switch

pins are available for channels A and B, and also chan-

nels C and D. The hardware redundancy only supports

parallel SPE/TOH data protection switching, but not the

serial TOH data.

In STS-48 mode, both parallel and serial port output

pins on the FPGA side should be 3-stated if two or

more devices are tied to the appropriate data bus. The

existing local bus enable signals at the CIC can be

used as 3-state controls if needed, which can be easily

accessed by software control. Users can also create

their own protection switch 3-state enable signals

either in FPGA logic or, external to the device, depend-

ing on the specific application.

22 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advanced Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Memory Map

Definition of Register Ty pes

There are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. There are no mixed registers in

the chip. This means that all bits of a particular register (particular address) are structurally the same.

Table 4. Structural Register Elements

Element Register Description

sreg Status Register A status register is read only, and, as the name implies, is used to convey the status

information of a particular element or function of the ORT4622 core. The reset value

of an sreg is really the reset value of the particular element or function that is being

read. In some cases, an sreg is really a fixed value. An example of which is the fixed

ID and revision registers.

creg Control Register A control register is read and writable memory element inside core control. The

value of a creg will always be the value written to it. Events inside the ORT4622 core

cannot effect creg value. The only exception is a soft reset, in which case the creg

will return to its default value. The control register have default values as defined in

the default value column of Table 5, memory map.

preg Pulse Register Each element, or bit, of a pulse register is a control or event signal that is asserted

and then deasserted when a value of one is written to it. This means that each bit is

always of value 0 until it is written to, upon which it is pulsed to the value of one and

then returned to a value of 0. A pulse register will always have a read value of 0.

iareg Interrupt Alarm

produced in the ORT4622 core, its occurrence is latched by its associated iareg bit.

To clear a particular iareg bit, a value of one must be written to it. In the ORT4622

core, all iareg reset values are 0.

isreg Interrupt Status

consolidation of lower level interrupt alarms and/or isreg bits from other registers. A

direct result of the fact that each bit of the isreg is a logical OR function means that it

will have a read value of one if any of the consolidation signals are of value one, and

will be of value 0 if and only if all consolidation signals are of value 0. In the

ORT4622 core, all iareg default values are 0.

ereg Interrupt Enable

is set to value one, then the event is allowed to propagate to the next higher level of

consolidation. If this bit is set to zero, then the associated iareg or isreg bit can still

be asserted but an alarm will not propagate to the next higher level. An interrupt

enable bit is an interrupt mask bit when it is set to value 0.

Registers Access and General Description

The memory map comprises three address blocks:

■Generic register block: ID, revision, scratch pad,

lock, FIFO alignment, and reset registers.

■Device register block: control and status bits, com-

mon to the four channels.

■Channel register blocks: each of the four channels

have an address block. The four address blocks

have the exact same structure with a constant

address offset between channel register blocks.

All register s are write-pr ot ected by the loc k registe r,

except for the scratch pad register. The lock register is

a 16-bit read/write register. Write access is given to

registers only when the key value 0xA001 is present in

the lock register . An error flag will be set upon detecting

a write access when write permission is denied. The

default value is 0x0000.

After powerup reset or soft reset, unused register bits

will be read as zeros. Unused address locations are

also read as zeros. Write only register bits will be read

as zeros. The detailed information on register access

and function are described on the tables, memory map,

and memory map bit description.

Lucent Technologies Inc. 23

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Memory Map (continued)

Memory Map Overview

Table 5. Memory Map

ADDR

[6:0] Reg.

Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default

Value

(hex) Notes

Generic Register Block

00 sreg fixed ID MSB [7:0] A0 1

01 sreg fixed ID LSB [7:0] 01

02 sreg fixed rev [7:0] 01

03 creg scratch pad [7:0] 00

04 creg lockreg MSB [7:0] 00

05 creg lockreg LSB [7:0] 00

06preg—— ————FIFO

align-

ment

command

global

reset

command

Device Register Block

08 creg — — — Rx TOH

frame

and

Rx TOH

clock

enable

hi-z

control

ext prot

sw en ext prot

function

STS-48

STS-12

sel

LVDS

lpbk

control

00 2

09 creg — — — — parallel

port out-

put MUX

select for

ch C

parallel

port out-

put MUX

select for

ch A

serial port

output

MUX

select for

ch C

serial port

output

MUX

select fo r

ch A

0a creg — — — FIFO aligner threshold value (min) [4:0] 02

0b creg — — — FIFO aligner threshold value (max) [4:0] 15

0c creg — scrambler/

descram-

bler

control

input/

output

parallel

bus parity

control

line lpbk

control number of consecutive A1/A2 errors to

generate [3:0] 60 3

0d creg A1 error insert value [7:0] 00

0e creg A2 error insert value [7:0] 00

0f creg transmitter B1 error insert mask [7:0] 00

Notes:

1. Generic register block.

2. Device register block-Rx.

3. Device register block-Tx.

2424 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Device Register Block (continued)

10 isreg — — — per

device int ch D

interrupt ch C

interrupt ch B

interrupt ch A

interrupt 00 4

11 iereg — — — enable/mask register [4:0] 00

12iareg—— ————write to

locked register error flag

frame

offset

error flag

13iereg— ————— enable/mask

Channel Register Block

20, 38,

50, 68

creg hi-z

control of

TOH data

output

hi-z

control of

parallel

output bus

channel

enable/

disable

control

parallel

output

bus parity

err ins

cmd

Rx K1/K2

source

select

TOH

serial

output

port par

err ins

cmd

force ais-l

control Rx

behavior

in LOF

01 5

21, 39,

51, 69 c reg Tx mode

of opera-

tion

Tx E1 F1

E2 source

select

Tx S1 M0

source

select

Tx K1/K2

source

select

Tx D12

source

select

Tx D11

source

select

Tx D10

source

select

Tx D9

source

select

00 6

22, 3a,

52, 6a creg Tx D8

source

select

Tx D7

source

select

Tx D6

source

select

Tx D5

source

select

Tx D4

source

select

Tx D3

source

select

Tx D2

source

select

Tx D1

source

select

23, 3b,

53, 6b creg— ————— B1 error

insert command

A1/A2 error ins

command

24, 3c,

54, 6c sreg — — — — Concat

indication

Concat

indication

Concat

indication

Concat

indication

NA 7

25, 3d,

55, 6d sreg Concat

indication

Concat

indication

Concat

indication

Concat

indication

Concat

indication

Concat

indication

Concat

indication

Concat

indication

ADDR

[6:0] Reg.

Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default

Value

(hex) Notes

Memory Map (continued)

Table 5. Memory Map (continued)

Notes:

1. Generic register block.

2. Device register block-Rx.

3. Device register block-Tx.

4. Top level interrupts.

5. Rx control.

6. Tx control signals.

7. Per STS#1 cos flag.

* ADDR values delimited by a comma indicate the address for each of 4 channels, from channel A to D. For example, the register to Tx control sig-

nals has addresses of 20, 38, 50, and 68. This indicates that channel A Tx control signals are at address 20, channel B Tx control signals are at

address 38, channel C Tx control signals are at address 50, and channel D Tx control signals are at address 68.

Lucent Technologies Inc. 25

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Channel Re

ister Block (continued)

26, 3e,

56, 6e isreg — — — — — elastic

store

overflow

flag

ais-p flag per

STS-12

alarm flag

00 8

27, 3f,

57, 6f iereg — — — — — enable/mask register [2:0] 00

28, 40,

58, 70 iareg — — TOH

serial

input port

parity

error flag

input

parallel

bus

parity

error flag

LVDS link

B1 parity

error flag

LOF flag Receiver

internal

path

parity

error flag

FIFO

aligner

threshold

error flag

00 9

29,41,

59, 71 iereg — — enable/mask register [5:0] 00

2a, 42,

5a, 72 iareg————AIS

interrupt

flags 12

AIS

interrupt

flag 9

AIS

interrupt

flag 6

AIS

interrupt

flags 3

00 10

2b, 43,

5b, 73 iareg AIS

interrupt

flag 11

AIS

interrupt

flag 8

AIS

interrupt

flag 5

AIS

interrupt

flag 2

AIS

interrupt

flag 10

AIS

interrupt

flag 7

AIS

interrupt

flag 4

AIS

interrupt

flag 1

2c, 44,

5c, 74 iereg — — — — enable/

mask AIS

interrupt

flag 12

enable/

mask AIS

interrupt

flag 9

enable/

mask AIS

interrupt

flag 6

enable/

mask AIS

interrupt

flag 3

2d, 45,

5d, 75 iereg enable/

mask AIS

interrupt

flag 11

enable/

mask AIS

interrupt

flag 8

enable/

mask AIS

interrupt

flag 5

enable/

mask AIS

interrupt

flag 2

enable/

mask AIS

interrupt

flag 10

enable/

mask AIS

interrupt

flag 7

enable/

mask AIS

interrupt

flag 4

enable/

mask AIS

interrupt

flag 1

2e, 46,

5e, 76 iareg————ES

overflow

flag 12

overflow

flag 9

overflow

flag 6

overflow

flag 3

ADDR

[6:0] Re

pe DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default

Value

(hex) Notes

Memor

(continued)

Table 5. Memor

(contin ued)

Notes:

1. Generic register block.

2. Device register block-Rx.

3. Device register block-Tx.

4. Top level interrupts.

5. Rx control.

6. Tx control signals.

7. Per STS#1 cos flag.

8. Per channel interrupt.

9. Per STS–12 interrupt flags.

10. Per STS–1 interrupt flags.

2626 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Channel Register Block (continued)

2f, 47,

5f, 77 iareg ES

overflow

flag 11

overflow

flag 8

overflow

flag 5

overflow

flag 2

overflow

flag 10

overflow

flag 7

overflow

flag 4

overflow

flag 1

00 10

30, 48,

60, 78 iereg — — — — enable/

mask ES

overflow

flags

enable/

mask ES

overflow

flag

enable/

mask E S

overflow

flags

enable/

mask ES

overflow

flags

31, 49,

61, 79 iereg enable/

mask ES

overflow

flag 11

enable/

mask ES

overflow

flag 8

enable/

mask ES

overflow

flag 5

enable/

mask ES

overflow

flag 2

enable/

mask ES

overflow

flag 10

enable/

mask ES

overflow

flag 7

enable/

mask E S

overflow

flag 4

enable/

mask ES

overflow

flag 1

32, 4a,

62, 7a counter overflow LVDS link B1 parity error counter 00 11

33, 4b,

63, 7b counter overflow LOF counter 00

34, 4c,

64, 7c counter overflow A1/A2 frame error counter 00

ADDR

[6:0] Reg.

Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default

Value

(hex) Notes

Memory Map (continued)

Table 5. Memory Map (contin ued)

Notes:

1. Generic register block.

2. Device register block-Rx.

3. Device register block-Tx.

4. Top level interrupts.

5. Rx control.

6. Tx control signals.

7. Per STS#1 cos flag.

8. Per channel interrupt.

9. Per STS–12 interrupt flags.

10. Per STS–1 interrupt flags.

11. Binning.

Lucent Technologies Inc. 27

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Table 6. Memor

Bit Descri

tions

Bit/Register

Name(s

)

Bit/

Location

(hex)

Type

Default

Value

(hex) Description

Generic Re

ister Block

fixed ID MSB [7:0]

fixed ID LSB [7:0]

fixed rev [7:0]

00 [7:0]

01 [7:0]

02 [7:0]

sreg A0

—

scratch pad [7:0] 03 [7:0] creg 00 The scratch pad has no function and is not used anywhere in the

ORT4622 core. However, this register can be written to and read from.

lockreg MSB [7:0]

lockreg LSB [7:0] 04 [7:0]

05 [7:0] creg 00

00 In order to write to registers in memory locations 06 to 7F, lockreg MSB

and lockreg LSB must be respectively set to the values of A0 and 01. If

the MSB and LSB lockreg values are not set to {A0, 01}, then any val-

ues wri tten to the registers in m em ory locations 06 to 7F will be ign ored.

Aft er reset (both hard and soft) the ORT4622 core is in a write locked

mode. T he ORT 4622 core n eeds to be u nlocked before it can be writte n

to. Also note that the scratch pad register (03) can always be written to

as i t is unaffected by write lock mode.

FIFO alignment

command

global reset

command

06 [0 ]

06 [1 ] preg NA The FIFO ali gnm en t an d global reset commands are bo th acc es se d v ia

the pulse register in memory address 06. The FIFO alignment com-

man d is used to fram e align the outputs of the four receive stm s tream

FIFOs. The global reset command is a soft (software initiated) reset.

Nevertheless, the global reset command will have the exact reset effect

as a hard (RST_N pin) reset.

Device Re

ister Block

LVDS lpbk control 08 [0] creg 0 0 No loopback.

1 LVDS loopback, transmit to receive on.

STS48 STS12 sel 08 [1] creg 0 This control signal is untracked in the ORT4622 core. It is a scratch bit,

and it’s value has no effect on the ORT4622 core.

ext prot sw en

ext prot sw func 08 [3:2] creg 0 ext

prot

ext

prot

func

Switching Control Master.

0 — MUX is controlled by software (one control bit per MUX).

Out put b uffers are controlled by software (one control bit

per channel).

1 0 MUX on parallel output bus of channel A is controlled by

Prot_Switch A/B pin (0-> channel A, 1-> channel B).

MUX on parallel output bus of channel C is controlled by

Prot_Switch C/D pin (0 -> channel C, 1-> channel D).

Out put b uffers are controlled by software (one control bit

per channel).

1 1 MUX is controlled by software (one control bit per MUX).

Output buffers on parallel output bus of channels A and B

are controlled by Prot_Switch A/B pin (0-> buffers active,

1-> hi-z).

Output buffers on parallel output bus of channels C and D

are controlled by Prot_Switch C/D pin (0 -> buffers active,

1-> hi-z).

Memor

(continued)

Memory Map Bit Descriptions

2828 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Device Register Block (continued)

Rx TOH frame and

Rx TOH clock enable

hi-z control

08 [4] creg 0 0 hi-z.

1 Enable receive TOH CLK and FP outputs.

serial port output

MUX select for

channel A serial port

output MUX select for

channel C

parallel port outpu t

MUX select for

channel A parallel

port output MUX

select for channel C

09 [0]

09 [1]

09 [2]

09 [3]

creg 1

Serial Port Output MUX Select for Channel 1

0 TOH output one is multiplexed to channel B.

1 TOH output one is multiplexed to channel A.

Serial Port Output MUX Select for Channel 3

0 TOH output three is multiplexed to channel D.

1 TOH output three is multiplexed to channel C.

Parallel Port Output MUX Select for Channel 1

0 Parallel output data bus one is multiplexed to channel B.

1 Parallel output data bus one is multiplexed to channel A.

Parallel Port Output MUX Select for Channel 3

0 Parallel outpu t data bus three is multiplexed to channel D.

1 Parallel outpu t data bus three is multiplexed to channel C.

FIFO aligner thresh-

old value (min) [4:0]

FIFO aligner thresh-

old value (max) [4:0]

0A [4:0]

0B [4:0] creg 02

15 These are the minimum and maximum thresholds values for the per

channel receiv e dir ect ion al ignm ent FIF Os. I f and when the minim um or

maximum threshold value is violated by a particular channel, then the

interrupt event FIFO aligner threshold error will be generated for that

channel and latched as a FIFO aligner threshold error flag in the

respective per STS-12 inte rrupt alarm register.

The allo wable range for minimum th resh old values is 0 to 23.

The allowable range for maximum threshold values is 0 to 22.

Note that the minimal and maximum FIFO aligner threshold values

apply to all four channels.

number of consecu-

tive A1/A2 errors to

generate [3:0]

A1 error insert value

[7:0]

A2 error insert value

[7:0]

0C [7:0]

0D [7:0]

0E [7:0]

creg 00

These three per device control signals are used in conjunction with the

per channel A1/A2 error insert command control bits to force A1/A2

errors in the transmit direction.

If a particula r cha nne l’s A1/A2 error insert comm an d co ntro l bi t is s et to

the value one then the A1 and A2 error insert value s will be inserted into

that channels respective A1 and A2 bytes. The number of consecutive

frames to be co rrupted is determine d b y th e n umber of consecutiv e A1 ,

A2 errors to generate[3:0] control bits.

The error inse rtio n is bas ed on a ri sin g ed ge d ete cto r. As suc h, th e co n-

trol must be set to value 0 before trying to initiate a second A1/A2 cor-

ruption.

line lpbk control 0C [4] creg 0 0 No loopback.

1 Receive to transmit loopback on FPGA side.

input/output parallel

bus parity control 0C [5] creg 0 0 Even parity.

1 Odd parity.

Bit/Register

Name(s)

Bit/

Location

(hex)

Type

Default

Value

(hex) Description

Memory Map (continued)

Table 6. Memory Map Bit Descriptions (continued)

Lucent Technologies Inc. 29

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Device Re

ister Block (continued)

scrambler/

descramble r control 0C [6] creg 1 0 No receive direction descramble/transmit direction scramble.

1 In receive direction descramble channel after SONET frame

recovery.

In transmit direction scramble data just before parallel to serial

conversion.

transmit B1 error

insert mask [7:0] 0F [7:0] creg 00 0 No error insertion.

1 Invert corresponding bit in B1 byte.

channel A int

channel B int

channel C int

channel D int

per device int

enable/m ask registe r

[4:0]

10 [0 ]

10 [1 ]

10 [2 ]

10 [3 ]

10 [4 ]

11 [4:0]

creg

iereg

Consolidation Interrupts

0 No interrupt.

1 Interrupt.

frame offset error flag

write to locked

enable/m ask registe r

[1:0]

12 [0 ]

12 [1 ]

13 [1:0]

iareg

iereg

If in the receive direction the phase offset between any two channels

exceeds 17 bytes, then a frame offset error event will be issued. This

condition is continuously monitored.

If the ORT4622 core memory map has no t been unlocked (by writing

A1 00 to the loc k registers ), and any addres s other th an the lo ckreg reg-

isters o r s cra tc h pad re gis ter is written to, th en a write to lo ck ed re gis ter

event will be generated.

Channel Re

ister Block

Rx behavior in LOF

force AIS-L control 20 38 50

68 [0 ]

20 38 50

68 [1 ]

—1

0Receive Behavior in Log

0 When receive direction OOF occurs, do not insert AIS-L.

1 When receive direction OOF occurs, insert AIS-L.

Force AIS-1 Control

0 Do not force AIS-L.

1 Force AIS-L.

TOH serial output

port par err ins cmd 20 38 50

68 [2 ] — 0 0 Do not insert a parity error.

1 Insert parity error in parity bit of receive TOH serial output for as

long as this bit is set.

Rx K1/K2 source

select 20 38 50

68 [3 ] — 0 0 Set receive direction K1/K2 bytes to 0.

1 Pass receive direction K1/K2 though pointer mover.

parallel outp ut bus

parity err ins cmd 20 38 50

68 [4 ] — 0 0 Do not insert pari ty error.

1 Insert parity error in the parity bit of receive direction parallel out-

put bus for as long as this bit is set.

Bit/Register

Name(s

)

Bit/

Location

(hex)

Type

Default

Value

(hex) Description

Memor

(continued)

Table 6. Memor

Bit Descri

tions (continued)

3030 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Channel Register Block (continued)

chann el ena ble /

disable co ntrol

hi-z control of parallel

output bus

hi-z control of TOH

data output

20, 38,

50, 68 [5]

20, 38,

50, 68 [6]

20, 38,

50, 68 [7]

creg

Channel Enable/Disable Control

0 Powerdown channel and 3-state output buses.

1 Functional mode.

hi-z Control of Parallel Output Bus

0 3-state output bus.

1 Functional mode.

hi-z Control of TOH Data Output

0 3-state output lines.

1 Functional mode.

Tx mode of operation

Tx E1 F2 E2 source

select

Tx S1 M0 source

select

Tx K1 K2 source

select

Tx D12—D9 source

select

Tx D8—D1 source

select

21, 39,

51, 69 [7]

21, 39,

51, 69 [6]

21, 39,

51, 69 [5]

21, 39,

51, 69 [4]

21, 39,

51, 69

[3:0]

22, 40,

52, 70

[7:0]

creg

4’h0

8’h00

Transmit Mode of Operation

0 Insert TOH from serial ports.

1 Pass through all TOH.

Other Registers

0 Insert TOH from serial ports.

1 Pass through that particular TOH byte.

A1/A2 error insert

command

B1 error insert

command

23, 3b,

53, 6b [0]

23, 3b,

53, 6b [1]

creg

creg 0

00 Do not insert error*.

1 Insert error for number of frames in register he x 0C*.

0 Do not insert error†.

1 Insert error for one frame in B1 bits defined by register hex 0F†.

concat indication 12,

9, 6, 3

concat indication 11,

8, 5, 2, 10, 7, 4, 1

24, 3c,

54, 6c

[3:0]

25, 3d,

55, 6d

[7:0]

sreg

sreg 0

0The value one in any bit location indicates that STS# is in CONCAT

mode. A 0 indicates that the STS in not in CONCAT mode, or is the head

of a concat group.

per STS–12 alarm

flag

AIS-P flag

elastic sto re ov erflow

flag

enable/m ask registe r

[2:0]

26, 3e,

56, 6e [0]

26, 3e,

56, 6e [1]

26, 3e,

56, 6e [2]

27, 3f,

57, 6f [3]

isreg

iereg

3’b000

These flag register bits per STS-12 alarm flag, AIS-P flag, and elastic

store overfl ow flag are the per-channel interrupt status (consolidation)

Bit/Register

Name(s)

Bit/

Location

(hex)

Type

Default

Value

(hex) Description

Memory Map (continued)

Table 6. Memory Map Bit Descriptions (continued)

* The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before tr ying to initiate a second A1/A2

corruption.

† The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second B1

corruption.

Lucent Technologies Inc. 31

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Channel Re

ister Block (continued)

FIFO aligner

threshold error flag

receiver internal path

parity error flag

LOF flag

LVDS link B1 parity

error flag

input parallel bus

parity error flag

TOH se rial in put port

parity error flag

enable/m ask registe r

[5:0]

28, 40,

58, 70 [0]

28, 40,

58, 70 [1]

28, 40,

58, 70 [2]

28, 40,

58, 70 [3]

28, 40,

58, 70 [4]

28, 40,

58, 70 [5]

28, 40,

58, 70 [6]

iareg

6’h00

These are per the STS-12 alarm flag s.

AIS inte rrupt flags 12,

9, 6, 3

AIS inte rrupt flags 11,

8, 5, 2, 10, 7, 4, 1

enable/m ask registe r

12, 9, 6, 3

enable/m ask registe r

11, 8, 5, 2, 10, 7, 4, 1

29, 41,

59,

71[3:0]

2a, 42,

5a, 72

[7:0]

2b, 43,

5b,

73[3:0]

2c, 44,

5c, 74

[7:0]

iareg

iereg

4’h0

8’h00

4’h0

8’h00

These are the AIS-P alarm flags.

ES overflow flag s 12,

9, 6, 3

ES overflow flag s 11,

8, 5, 2, 10, 7, 4, 1

enable/m ask registe r

12, 9, 6, 3

enable/m ask registe r

11, 8, 5, 2, 10, 7, 4, 1

2d, 45,

5d, 75

[3:0]

2e, 46,

5e, 76

[7:0]

2f, 47, 5f,

77 [3:0]

30, 48,

60, 78

[7:0]

—4’h0

8’h00

4’h0

8’h00

These are the elasti c sto r e over flow alarm flags.

LVDS link B1 parity

error counter 31, 49,

61, 79

[7:0]

cou nter 8’h00 7-bit count + overflow-reset on read.

LOF counter 32, 4a,

62, 7a

[7:0]

cou nter 8’h00 7-bit count + overflow-reset on read.

A1/A2 frame error

counter 33, 4b,

63, 7b

[7:0]

cou nter 8’h00 7-bit count + overflow-reset on read.

Bit/Register

Name(s

)

Bit/

Location

(hex)

Type

Default

Value

(hex) Description

Memor

(continued)

Table 6. Memor

Bit Descri

tions (con tin ued)

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

32 Lucent Technologies Inc.

Lucent Technologies Inc.

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

The

ORCA

Series 3+ FPSCs include circuitry designed to protect the chips from damaging substrate injection cur-

rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed

during storage, handling, and use to avoid exposure to excessive electrical stress.

Table 7. Absolute Maximum Ratings

Recommend Operating Conditions

Table 8. Recommend Operating Conditions

Symbol Parameter Min Max Unit

Tstg Storage Temperature 65 150 °C

VDD Supply Voltage with Respect to Ground 0.5 7.0 V

— Input Signal with Respect to Ground 0.5 VDD + 0.3 V

— Signal Applied to High-impedance Output 0.5 VDD + 0.3 V

— Maximum Package Body Temperature — 220 °C

ORT4622

Temperature Range

(Ambient) Temperature Range

(Junction) I/O Supply Voltage

(VDD)Internal Supply Voltage

(VDD2)

–40 °C to +85 °C –40 °C to +125 °C 3.135 V to 3.465 V 2.3 V to 2.7 V

Lucent Technologies Inc. 33

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Electrical Characteristics

Table 9. Electrical Characteristics for FPGA I/O

ORT4622 Industrial: VDD = 3.0 V to 3.6 V, VDD2 = 2.3 V to 2.7 V, –40 °C < TA < +85 °C.

* On the Series 3 devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD.

Symbol Parameter Test Conditions ORT4622 Unit

Min Max

VIH

VIL

Input V oltage:

High

Low

Input configured as CMOS

(clamped to VDD) 50% VDD

GND – 0.5 VDD + 0.3

30% VDD V

VIH

VIL

Input V oltage:

High

Low

Input configured as 5 V tolerant 50% VDD

GND – 0.5 5.8

30% VDD V

VOH

VOL

Output Voltage:

High

Low VDD = min, IOH = 6 mA or 3 mA

VDD = min, IOL = 12 mA or 6 mA 2.4

——

0.4 V

ILInput Leakage Current VDD = max, VIN = VSS or V DD –10 10 µA

IDDSB Standby Current (TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)

internal os cillator runnin g, no ou tput loads,

inputs at VDD or GND

(after configuration)

—5.3mA

IDDSB Standby Current (TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)

internal oscillator stopped, no output

loads, inputs at VDD or GND

(after configuration)

—1.4mA

VDR Data Retention Voltage TA = 25 °C2.3—V

IPP Powerup Current Power supply current at approximately

1 V, within a recommended power supply

ramp rate of 1 ms—200 ms

2.7 — mA

CIN Input Capacitance (TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)

test frequency = 1 MHz —8pF

COUT Output Capacitance (TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)

test frequency = 1 MHz —9pF

RDONE DONE Pull-up Resistor* — 100 — kΩ

RMM[3:0] Pull-up Resistors* — 100 — kΩ

IPU I/O Pad St atic Pul l- up

Current* (VDD = 3.6 V,

VIN = VSS, TA = 0 °C) 14.4 50.9 µA

IPD I/O Pad Stati c Pul l-d o wn

Current (VDD = 3.6 V,

VIN = VSS, TA = 0 °C) 26 103 µA

RPU I/O Pad Pull-up Resistor* VDD = all, VIN = VSS, TA = 0 °C 100 — kΩ

RPD I/O Pad Pull-down Resistor VDD = all, VIN = VDD, TA = 0 °C 50 — kΩ

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

34 Lucent Technologies Inc.

Lucent Technologies Inc.

Electrical Characteristics (continued)

Table 10. Electrical Characteristics for Embedded Core I/O Other than LVDS I/O

Note: All outputs are driving 35 pF, except CPU data bus pins which drive 100 pF. It is assumed that the TTL buffers from the

standard-cell library can handle the 100 pF load.

Symbol Parameter Min Max Unit

VIH Input High Voltage (TTL input) 2.0 5.5 V

VIL Input Low Voltages (TTL input) — 0.8 V

VOH Output High Voltage (TTL output) 2.4 — V

VOH Output Low Voltage (TTL output) — 0.4 V

Lucent Technologies Inc. 35

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

HSI Circuit Specifications

Input Data

The 622 Mbits/s scrambled input data stream must conform to SONET STS-12 and SDH STM-4 data format using

either a PN7 or PN9 sequence. The PN7 characteristic is 1 + x6 + x7 and the PN9 characteristic is 1 + x4 + x9. The

longest allowable stream of nontransitional 622 Mbits/s input data is 60 bits. This sequence should not occur more

often than once per minute. An input signal phase change of no more than 100 ps is allowed over 200 ns time

interval, which translates to a frequency change of 500 ppm. The signal eye opening must be greater than

0.4 UIp-p and the unit interval for 622 Mbits/s is 1.6075 ns.

Jitter Tolerance

The input jitter tolerance of the ORT4622 is shown in Table 11.

Table 11. Jitter Tolerance

Generated Output Jitter

The generated output jitter is a maximum of 0.2 UIp-p from 250 kHz to 5 MHz.

PLL

PLL requires an external 10 kΩ pull-down resistor.

Table 12. PLL

Input Reference Cloc k

Table 13. Input Reference Clock

Frequency UIp-p

250 kHz 0.6

25 kHz 6.0

2 kHz 60

Parameter Min Max Unit

Loop Bandwi dth — 6 MHz

Jitter Peaking — 2 dB

Powerup Reset Duration 10 — µs

Lock Acquisition — 1 ms

Parameter Min Max

Frequency Deviation — ± 20 ppm

Frequency Change — 500 ppm

Phase Change in 200 ns — 100 ps

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36 Lucent Technologies Inc.

Lucent Technologies Inc.

LVDS I/O

Table 14. LVDS Driver dc Data*

* External reference, REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%

Table 15. LVDS Driver ac Data

Symbol Parameter Test Conditions Min Typ Max Unit

VOH Driver Output Voltage High, VOA or VOB R

LOAD = 100 Ω ± 1% — — 1.475* V

VOL Driver Output Voltage Low, V OA or VOB RLOAD = 100 Ω ± 1% 0.925* — — V

VOD Driver Output Differential Voltage

VOD = (VOA – VOB)

(with External Reference Resistor)

RLOAD = 100 Ω ± 1% 0.25 — 0.45* V

VOS Dri ver Output Offse t Vol tage

VOS = (VOA + VOB)/2 RLOAD = 100 Ω ± 1% 1.125* — 1.275* V

RoOutput Impedance, Single Ended VCM = 1.0 V and 1.4 V 40 50 60 Ω

delta RORO Mismatch Between A and B VCM = 1.0 V and 1.4 V — — 10 %

— Change in |VOD| Between 0 and 1 RLOAD = 100 Ω ± 1% — — 25 mV

— Change in |VOS| Between 0 and 1 RLOAD = 100 Ω ± 1% — — 25 mV

ISA, ISB Output Current Driver shorted to

ground ——24mA

ISAB Output Current Drivers shorted

together ——12mA

|xa|, |xb| Power-off Output Leakage VDD = 0 V

VPAD, VPADN = 0 – 3 V — — 30 µA

Symbol Parameter Test Conditions Min Max Unit

TFALL VOD Fall Time, 80% to 20% ZLOAD = 100 Ω ± 1%

CPAD = 3.0 pF, CPAD = 3.0 pF 100 200 ps

TRISE VOD Rise Time, 20% to 80% ZLOAD = 100 Ω ± 1%

CPAD = 3.0 pF, CPAD = 3.0 pF 100 200 ps

TSKEW1 Differential Skew

|tpHLA–tpLHB| or

|tpHLB–tpLHA|

Any differential pair on package at 50% point

of the transition —50ps

TSKEW2 Channel-to-channel Skew

|tpDIFFm–tpDIFFn|, Any two signals on package at 0 V differential — — ps

TPLH

TPHL Propagation Delay Time ZLOAD = 100 W ± 1%

CPAD = 3.0 pF, CPADN = 3.0 pF 0.50

0.55 0.90

1.03 ps

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ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

LVDS I/O (continued)

LVDS Receiver Buffer Requirements

Table 16. LVDS Receiver dc Data

* Buffer will not produce output transition when input is open-circuited.

Note: VDD = 3.1V—3.5 V, 0 °C —125 °C , slow-fast process.

Table 17. LVDS Receiver ac Data

Table 18. LVDS Receiver Power Consumption

Table 19. LVDS Operating Parameters

Note: Under worst-case operating condition, the LVDS driver will withstand a disabled or unpowered receiver for an

unlimited period of time without being damaged. Similarly, when outputs are short-circuited to each other or to

ground, the LVDS will not suffer permanent damage.

Symbol Parameter Te st Conditions Min Typ Max Unit

VIReceiver Input Voltage Range, VIA or

VIB |VGPD| < 925 mVdc 1 MHz 0 1.2 2.4 V

|VIDTH| Receiver Input Differential Threshold |VGPD| < 925 mV 400 MHz –100 — 100 mV

VHYST Receiver Input Differential Hysteresis VIDTHH – VIDTHL ———*mV

RIN Receiver Differential Input Impedance With built-in termination,

center-tapped 80 100 120 Ω

Symbol Parameter Test Conditions Min Max Unit

TPWD Receiver Output Pulse-width Distortion |VIDTH| = 100 mV

311 MHz —TBDps

TPLH,

TPHL Propagation Dela y Time CL = 1.5 pF 0.75

0.74 1.65

1.82 ns

— With Common-mode Variation, (0 V to 2.4 V) CL = 1.5 pF — 50 ps

TRISE Receiver Output Signal Rise Time, VOD 20% to 80% CL = 1.5 pF 150 350 ps

TFALL Receiver Output Signal Fall Time, VOD 80% to 20% CL = 1.5 pF 150 350 ps

Symbol Parameter Te st Conditions Min Max Unit

PRdc Receiver dc Power dc — 34.8 mW

PRac Receiver ac Power ac, CL = 1.5 pF — 0.026 mW/MHz

Parameter Test Conditions Min Normal Max Unit

Transmit Termination Resistor — — 100 — Ω

Receiver Termination Resistor — — 50 — Ω

Temperature Range — –40 — 125 °C

Power Supply VDD —3.1—3.5V

Power Supply VSS ——0—V

ORCA

ORT4622 FPSC Advance Data Sheet

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38 Lucent Technologies Inc.

Lucent Technologies Inc.

Timing Characteristics

5-8605 (F)

Figure 11. Transmit Parallel Port Timing (Backplane -> FPGA)

Table 20. Timing Requirements (Transmit Parallel Port Timing)

Symbol Parameter Min Max Unit

TPClock Peri od 12.86 — n s

TLClock Low Time 5.1 7.7 ns

THClock High Time 5.1 7.7 ns

TSU Data Setup Time 3 — ns

THD Data Hold Time 0 — ns

TSU THD

FIRST A1 OF STS1 #1

SYS_CLK

SYS_FP

DATA_TX BUS

(DATA BUS

FROM FPGA

TO EMBE DDED

CORE)

Lucent Technologies Inc. 39

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ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Timing Characteristics (continued)

5-8606

Figure 12. Transmit Transport Delay (FPGA -> Backplane)

Table 21. Timing Requirements (Transmit Transport Delay)

Symbol Parameter Min Nom Max Unit

TPROP Number of Clocks of Delay from Parallel

Bus Input to LVDS Output 4 7 8 SYS_CLK

TPROP

A1 OF STS1 #1

SYS_CLK

SYS_FP

DATA_TX BU S

(PARALLEL

DATA

FROM FPGA

TO EMBE DDED

CORE)

HDOUT

(LVDS

DATA

OUT) FIRST A1 OF STS1 #1

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

40 Lucent Technologies Inc.

Lucent Technologies Inc.

Timing Characteristics (continued)

5-8607 (F)

Figure 13. Receive Parallel Port Timing (Backplane -> FPGA)

Table 22. Timing Requirements (Receive Parallel Port Timing)

Symbol Parameter Min Nom Max Unit

TPClock Period 12.86 — — ns

TLClock Low Time 5.1 6.43 7.7 ns

THClock High Time 5.1 6.43 7.7 ns

TSU Data Setup Time 3 — — ns

THD Data Hold Time 0 — — ns

TCO Clock to Output Ti me of Data, Parity,

SPE, and C1J1 Pins 1.3 — 7 ns

TSU THD

SYS_CLK

LINE_FP

DATA_RX BUS

(FROM EM BED DED

CORE TO

FPGA) FIRST A1 OF STS1 #1

TCO

PARITY,

SPE,

C1J1 PINS

Lucent Technologies Inc. 41

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ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Timing Characteristics (continued)

5-8608 (F)

* Data bus refers to 8 bits data, 1 bit parity, 1 bit SPE, and 1 bit C1J1.

† Channel A or C refers to whether the PROT_SW_A or PROT_SW_C pins that are activated. For example, if the PROT_SW_A pin is

activated, the timing diagram for output bus A or C refers to output bus A.

Figure 14. Protection Switch Timing

Table 23. Timing Requirements (Protection Switch Timing)

Symbol Parameter Min Nom Max Unit

TTR Transport Delay from Latching of

PROT_SW_A/C to Actual Data Switch 7 8 9 Leading edge

SYS_CLKs

THIZ Transport Delay from Latching of

PROT_SW_A/C to Actual Hi-z 4 5 6 Leading edge

SYS_CLKs

TCH Propag ati on Dela y from

SYS_CLK to HI-Z of Output Bus — — 25 Leading edge

SYS_CLKs

TSU Setup Time Required from Change in

PROT_SW_A/C to Rising SYS_CLK 3—— ns

THD Hold Time Required from Rising SYS_CLK to

Change in PROT_SW_A/C 0—— ns

SYS_CLK

PROT_SW_A

...

PROT_SW_C

...

DATA_RX BUS*

A OR C

SYS_CLK

DATA _ RX BUS†

A & B OR

C & D

CH A/C CH A/C CH A/C CH A/C CH B/D

TSU

THD

HIZ

CH A & B/

CH C & D CH A & B/

CH C & D

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

42 Lucent Technologies Inc.

Lucent Technologies Inc.

Timing Characteristics (continued)

5-8609 (F)

Figure 15. TOH Input Serial Port Timing (FPGA -> Backplane)

Table 24. Timing Requirements (TOH Input Serial Port Timing)

Symbol Parameter Min Nom Max Unit

TPClock Period 12.86 — 40 ns

THI Clock High Time 5.1 6.43 7.7 ns

TLO Clock Low Time 5.1 6.43 7.7 ns

TSData Setup Time 3 — — ns

THData Hold Time 0 — — ns

SYS_CLK

SYS_FP

...

DATA_TX BUS

TOH_CLK

1044 bytes SPE

...

TX TOH_

(PARALLEL

BUS)

TOH SER I A L

INPUT

CLK_ENA

ROW #1 ROW #9

36 bytes TOH 1044 bytes SPE 36 bytes TOH

GUARD BAND

(4 TOH CLK) GUARD BAND

(4 TOH CLK)

MSbit(7)

OF B 1 b y te

STS1 #1

bit 6

OF B 1 b y te

STS1 #1

THI TLO

Lucent Technologies Inc. 43

Advance Data Sheet

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ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Timing Characteristics (continued)

5-8610 (F)

Note: The total delay from A1 STS1 #1 arriving at LV DS input to RX_TOH_FP is 56 SYS_CLKs and 6 TOH_CLKs. This will vary by ±14

SYS_CLKs, 12 each way for the FIFO alignment, and ±2 SYS_CLKs due to the variability in the clock recovery of the HSI macro.

Figure 16. TOH Output Serial Port Timing (Backplane -> FPGA)

Table 25. Timing Requirements (TOH Output Serial Port Timing)

Symbol Parameter Min Nom Max Unit

TCO Data Clock to Out 2 — 8 ns

TTRANS_SYS Delay from First A1 LVDS Serial Input to

Transfer to TOH_CLK 44 56 68 SYS_CLKs

TTRANS_TOH Delay from Transfer to TOH_CLK to

RX_TOH_FP — 6 — TOH_CLKs

RX TOH FP

HDIN

TOH_CLK

1044 bytes SPE

RX TOH

(INPUT LVDS

SERIAL 622M

DATA)

TOH SERIA L

OUTPUT

CLK ENA

ROW #1 ROW #9

36 bytes TOH 1044 bytes SPE 36 bytes TOH

MSbit(7)

OF A 1 b y te

STS #1

bit 6

OF A 1 b y te

STS #1

TTRANS_SYS

TTRANS_TOH

TCO

bit 0

OF A 1 b y te

STS #1

...

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

44 Lucent Technologies Inc.

Lucent Technologies Inc.

Timing Characteristics (continued)

5-8611 (F)

Note: The CPU interface can be bit stream selected either from device I/O or FPGA interface. The timing diagram applies to both interfaces.

Figure 17. CPU Write Transaction

Table 26. Timing Requirements (CPU Write Transaction)

Symbol Parameter Min Max Unit

TPULSE Minimum Pulse Width for CS_N 5 — ns

TADDR_MAX Maximum Time from Negative Edge

of CS_N to ADDR Valid —18ns

TDAT_MAX Maximum Time from Negative Edge

of CS_N to Data Valid —25ns

TRD_WR_MAX Maximum Time from Negative Edge

of CS_N to Negative Edge of RD_WR_N —26ns

TWRITE_MAX Maximum T ime from Negative Edge of CS_N to

Contents of Internal Register Latching DB[7:0] — 60 ns

TACCESS_MIN Minimum Time Between a Write Cycle (Falling

Edge of CS_N) and Any Other Transaction

(Read or Write at Falling Edge of CS_N)

60 — ns

TINT_MAX Maximum Time from Register FF to Pad — 20 ns

TRW_WR_N,

ADDR, DB_HOLD Minimum Hold Time that RD_WR_N,

ADDR and DB Must be Held Valid from

the Negative Edge of CS_N

57 — ns

DATA VALID

TACCESS_MIN

TPULSE

OLD VALUE NEW VALUE

TWRITE_MAX

TINT_MAX

TADDR_MAX

TDAT_MAX RD_WR_MAX

CPU_CS_N

CPU_RD_WR_N

CPU_ADDR[6:0]

CPU_DATA[7:0]

INTERNAL REGISTER

(SYS_CLK

DOMAIN)

CPU_INT_N

TRD_WR_N, ADDR_MAX, DB_HOLD

(CS_N)

(RD_WR_N)

(ADDR[6:0])

(DB[7:0])

(INT_N)

Lucent Technologies Inc. 45

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ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Timing Characteristics (continued)

5-8612 (F)

Notes:

The CPU interface can be bit stream selected either from device I/O or FPGA interface. The timing diagram applies to both interfaces.

The time delay between the adva nced SYS _CLK and the distributed SYS_CLK used to sample CS_N is of no consequence. However, the

path delay of CS_N from pad to where is it sampled by SYS_CLK must be minimized.

The calculated delays assume a 100 pF loading on the DB pins.

Figure 18. CPU Read Transaction

Table 27. Timing Requirements (CPU Read Transaction)

Symbol Parameter Min Max Unit

TPULSE Minimum Pulse Width for CS_N 5 — ns

TADDR_MAX Maximum Time from Negative Edge of

CS_N to ADDR Valid —5 ns

TRD_WR_MAX Maximum Time from Negative Edge of

CS_N to RD_WR_N Falling —5 ns

TDATA_MAX Maximum Time from Negative Edge of

CS_N to Data Valid on DB Port —56 ns

THIZ_MAX Maximum Time from Rising Edge of

CS_N to DB Port Going HI-Z —12 ns

TACCESS_MIN Minimum Time Between a Read Cycle

(Falling Edge of CS_N) and Any Other T ransaction

(Read or Write at Falling Edge of CS_N)

60 — ns

DATA VALID

TACCESS_MIN

TPULSE

TDATA_MAX

CPU_CS_N

CPU_RD_WR_N

CPU_ADDR[6:0]

CPU_DATA[7:0]

THIZ_MAX

TADDR_MAX

TRD_WR_MAX

(CS_N)

(RD_WR_N)

(ADDR[6:0])

(DB[7:0])

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

46 Lucent Technologies Inc.

Lucent Technologies Inc.

Input/Output Buffer Measurement Conditions

Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH.

Figure 19. ac Tes t Loads

Figure 20. Output Buffer Delays

Figure 21. Input Buffer Delays

5-3234(F)

50 pF

A. Load Used to Measure Propagation Delay

TO THE O UTPUT UNDER TEST

TO THE OUTPUT UNDER T EST

50 pF

VCC GND

1 kΩ

B. Load Used to Measure Rising/Falling Edges

5-3233.a(F)

VDD

TPHH

VDD/2

VSS

out[i]

PAD

OUT 1.5 V

0.0 V TPLL

PAD

out[i] ac TEST LOADS (SHOWN ABOVE)

ts[i]

OUT

5-3235(F)

0.0 V

1.5 V

TPHH TPLL

PAD in[i]

3.0 V

VSS

VDD/2

VDD

PAD IN

in[i]

Lucent Technologies Inc. 47

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ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

FPGA Output Buffer Characteristics

5-6865(F)

Figure 22. Sinklim (TJ = 25 °C, VDD = 3.3 V)

5-6867(F)

Figure 23. Slewlim (TJ = 25 °C, VDD = 3.3 V)

5-6867(F)

Figure 24. Fast (TJ = 25 °C, VDD = 3.3 V)

5-6866(F)

Figure 25. Sinklim (TJ = 125 °C, VDD = 3.0 V)

5-6868(F)

Figure 26. Slewlim (TJ = 125 °C, VDD = 3.0 V )

5-6868(F)

Figure 27. Fast (TJ = 125 °C, VDD = 3.0 V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

110

OUTP UT VOLTAGE, VO (V)

IOL

IOH

OUTPU T CURRENT, IO (mA)

100

0.0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT VOLTAGE, VO (V)

IOL

100

IOH

OUTPUT CURRENT, IO (mA)

120

140

3.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT VOLTAGE, VO (V)

IOL

100

IOH

OUTPUT CURRENT, IO (mA)

120

140

3.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPU T VOLTAGE, VO (V)

IOL

IOH

OUTPU T CURRENT, IO (m A)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT VOLTAGE, VO (V)

IOL

100

IOH

OUTPUT CURRENT, IO (mA)

120

0.0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT VOLTAGE, VO (V)

IOL

100

IOH

OUTPUT CURRENT, IO (mA)

120

ORCA

ORT4622 FPSC Advance Data Sheet

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48 Lucent Technologies Inc.

Lucent Technologies Inc.

Estimating Power Dissipation

This section will be included in a future release of this data sheet.

General FPGA power estimation parameters can be found in the

ORCA

Series 3 data sheet.

Lucent Technologies Inc. 49

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Pin Information

Table 28. FPGA Common-Function Pin Description

* The

ORCA

Series 3 FPGA data sheet contains more information on how to control these si gnals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti vation of all

user I/Os) is controlled by a s econd set of options.

Symbol I/O Description

Dedicated Pins

VDD —3.3 V power supply.

VDD2—

2.5 V power supply

GND — Ground supply.

RESET I

During co nfigur ati on, RESET forces the restart of configuration and a pull-up is

enabled. After configuration, RESET can be used as an FPGA logic direct input,

which causes all PLC latches/FFs to be asynchronously set/reset.

CCLK I In the master and asynchronous peripheral modes, CCLK is an output which

strobes configuration data in. In the slave or synchronous peripheral mode, CCLK is

input synchronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK is

used internally and output for daisy-chain operation.

DONE I As an input, a low level on DONE delays FPGA start-up after configuration.*

OAs an active-high, open-drain output, a high level on this signal indicates that config-

uration is complete. DONE has a permanent pull-up resistor.

PRGM IPRGM

is an active-low input that forces the restart of configuration and resets the

boundary-scan circuitry. This pin always has an active pull-up.

RD_CFG IThis pin must be held high during device initialization until the INIT pin goes high.

This pin always has an active pull-up.

During configuration, RD_CFG is an active-low input that activates the TS_ALL

function and 3-states all of the I/O.

After configuration, RD_CFG can be selected (via a bit stream option) to activate the

TS_ALL function as described above, or, if readback is enabled via a bit stream

option, a high-to-low transition on RD_CFG will initiate readback of the configuration

data, including PFU output states, starting with frame address 0.

RD_DATA/TDO ORD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con-

figuration data out. If used in boundary scan, TDO is test data out.

Special-Purpose Pins

M0, M1, M2 I During powerup and initialization, M0, M1, and M2 are used to select the configura-

tion mode with their values latched on the rising edge off INIT. During configuration,

a pull-up is enabled. After configuration, these pins cannot be user-programmable

I/Os.

M3 I During powerup and initialization, M3 is used to select the speed of the internal

oscillator during configuration with their values latched on the rising edge of INIT.

When M3 is low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator

is 1.25 MHz. During configuration, a pull-up is enabled.

I/O After configuration, this pin is a user-programmab le I/O pin.*

ORCA

ORT4622 FPSC Advance Data Sheet

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50 Lucent Technologies Inc.

Lucent Technologies Inc.

Pin Information (continued)

Table 28. FPGA Common-Function Pin Description (continued)

* The

ORCA

Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the t iming of the simultaneous release of all other configuration pins (and the activation of all

user I/Os) is controlled by a s econd set of options.

Symbol I/O Description

Special-Purpose Pins (continued)

TDI, TCK, TMS I If boundary scan is used, these pins are test data in, test cloc k, and test mode select

inputs. If boundary scan is not selected, all boundary-scan functions are inhibited

once configuration is complete. Even if boundary scan is not used, either TCK or

TMS must be held at logic one during configuration. Each pin has a pull-up enabled

during configuration.

I/O After configuration, these pins are user-programmable I/O.*

RDY/RCLK/

MPI_ALE O During configuration in peripheral mode, RDY/RCLK indicates another byte can be

written to the FPGA. If a read operation is done when the device is selected, the

same status is also available on D7 in asynchronous peripheral mode.

O During the master parallel configuration mode, RCLK is a read output signal to an

external memory. This output is not normally used.

IIn

i960

microprocessor mode, this pin acts as the address latch enable (ALE) input.

I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*

HDC O High during configuration (HDC) is output high until configuration is complete. It is

used as a control output indicating that configuration is not complete.

LDC O Low during configurati on (LDC) is output low until configuration is complete. It is

used as a control output indicating that configuration is not complete.

INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a

pull-up is enabled, but an ex ternal pull-up resistor is recommended. As an active-lo w

open-drain output, INIT is held low during power stabilization and internal clearing of

memory. As an active-low input, INIT holds the FPGA in the wait-state before the

start of configuration.

CS0, CS1 I CS0 and CS1 are used in the asynchronous peripheral, slav e parallel, and micropro-

cessor configuration modes. The FPGA is selected when CS0 is low and CS1 is

high. During configuration, a pull-up is enabled.

I/O After configuration, these pins are user-programmable I/O pins.*

RD/MPI_STRB IRD is used in the asynchronous peripheral configuration mode. A low on RD

changes D7 into a status output. As a status indication, a high indicates ready, and a

low indicates busy. WR and RD should not be used simultaneously. If they are, the

write strobe o verrides.

This pin is also used as the microprocessor interface (MPI) data transfer strobe. For

PowerPC

, it is the transfer start (TS). For

i960

, it is the address/data strobe (ADS).

I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*

WR IWR is used in the asynchronous peripheral configuration mode. When the FPGA is

selected, a low on the write strobe, WR, loads the data on D[7:0] inputs into an inter-

nal data buffer. WR and RD should not be used simultaneously. If they are, the write

strobe overrides.

I/O After configuration, this pin is a user-programmab le I/O pin.*

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ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Pin Inform ation (continued)

Table 28. FPGA Common-Function Pin Description (continued)

Symbol I/O Description

Special-Purpose Pins (continued)

MPI_IRQ O MPI active-low interrupt request output.

MPI_BI O

PowerPC

mode MPI burst inhibit output.

I/O If the MPI is not in use, this is a user-programmable I/O.

MPI_ACK OIn

PowerPC

mode MPI operation, this is the active-high transfer acknowledge (TA)

output. For

i960

MPI operation, it is the active-low ready/record (RDYRCV) output.

If the MPI is not in use, this is a user-programmable I/O.

MPI_RW I In

PowerPC

mode MPI operation, this is the activ e-low write/active-high read control

signa ls. For

i960

operation, it is the active-high write/active-low read control signal.

I/O If the MPI is not in use, this is a user-programmable I/O.

MPI_CLK I This is the clock used f or the synchronous MPI interf ace. F or

PowerPC

, it is the CLK-

OUT signal. For

i960

, it is the system clock that is chosen for the

i960

external bus

interface.

I/O If the MPI is not in use, this is a user-programmable I/O.

A[4:0] I For

PowerPC

operation, these are the

PowerPC

address inputs. The address bit

mapping (in

PowerPC

/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/

A[3], A[27]/A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs

are not used in

i960

MPI

mode.

I/O If the MPI is not in use, this is a user-programmable I/O.

A[1:0]/MPI_BE[1:0] IFor

i960

operation, MPI_BE[1:0] provide the

i960

byte enable signals, BE[1:0], that

are used as address bits A[1:0] in

i960

byte-wide operation.

D[7:0] I During peripheral, and slave parallel configuration modes, D[7:0] receive configura-

tion data, and each pin has a pull-up enabled. During serial configuration modes, D0

is the DIN input. D[7:0] are also the data pins for

PowerPC

microprocessor mode

and the address/data pins for

i960

microprocessor mode.

I/O After configuration, the pins are user-programmable I/O pins.*

DIN I During slav e serial or master serial configuration modes, DIN accepts serial configu-

ration data synchronous with CCLK. During parallel configuration modes, DIN is the

D0 input. During configuration, a pull-up is enabled.

I/O After configuration, this pin is a user-programmable I/O pin.*

DOUT O During configuration, DOUT is the serial data output that can drive the DIN of daisy-

chained slave LCA devices. Data out on DOUT changes on the falling edge of

CCLK.

I/O After configuration, DOUT is a user-programmable I/O pin.*

* The

ORCA

Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of

all user I/Os) is controlled by a second set of options.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

52 Lucent Technologies Inc.

Lucent Technologies Inc.

Pin Information (continued)

This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary.

Table 29. FPSC Function Pin Description

Symbol I/O Description

HSI LVDS Pins

STS_INA I LVDS input receiver A.

STS_INAN I LVDS input receiver A.

STS_INB I LVDS input receiver B.

STS_INBN I LVDS input receiver B.

STS_INC I LVDS input receiver C.

STS_INCN I LVDS input receiver C.

STS_IND I LVDS input receiver D.

STS_INDN I LVDS input receiver D.

STS_OUTA O LVDS output receiver A.

STS_OUTAN O LVDS output receiver A.

STS_OUTB O LVDS output receiver B.

STS_OUTBN O LVDS output receiver B.

STS_OUTC O LVDS output receiver C.

STS_OUTCN O LVDS output receiver C.

STS_OUTD O LVDS output receiver D.

STS_OUTDN O LVDS output receiver D.

CTAP_REFA — LVDS input center tap (RX A) (use 0.01 µF to GND).

CTAP_REFB — LVDS input center tap (RX B) (use 0.01 µF to GND).

CTAP_REFC — LVDS input center tap (RX C) (use 0.01 µF to GND).

CTAP_REFD — LVDS input center tap (RX D) (use 0.01 µF to GND).

REF10 I LVDS reference voltage: 1.0 V ± 3%.

REF14 I LVDS reference voltage: 1.4 V ± 3%.

RESHI — Resistor input (use 100 Ω ± 1% to RESLO input).

RESLO — Resistor input.

REXT — Reference resistor for PLL (10 kΩ to ground).

PLL_VDDA — PLL analog VDD (3.3 V ± 5%).

PLL_VSSA — PLL analog VSS (GND).

HSI Test Signals

TSTMODE I Enables CDR test mode

BYPASS I Enables bypassing of the 622 MHz clock synthesis with TSTCLK.

TSTCLK I Test clock for emulation of 622 MHz clock during PLL b ypass.

MRESET I Test mode reset.

RESETRN I Resets receiver clock division counter.

RESETTN I Resets transmitter clock division counter.

Lucent Technologies Inc. 53

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

HSI Test Signals (continued)

TSTSHFTLD I Enables the test mode control register for shifting in selected tests by a

serial port.

ECSEL I Enables external test control of 622 MHz clock phase selecion.

EXDNUP I Dir ect ion of phase change.

ETOGGLE I Move s 622.08 MHz clock selection on phase per positive pulse .

LOOPBKEN I Enables 622 Mbits/s loopback mode.

TSTPHASE I Controls bypass of 16 PLL-generated phases with 16 low-speed phases.

TSTMUX[8:0]S O Test mode output port.

CPU Interface Pins

DB<7:0> I/O CPU interface data bus.

ADDR<6:0> I CPU interface address bus.

RD_WR_N I CPU interface read/write.

CS_N I Ch ip se lec t.

INT_N O Interrupt output.

MISC System Signals

RST_N I Global reset.

Exte rnal pull-down allows chip to stay in reset st ate when external driver

loses power.

SYS_CLK I System clock (77.76 MHz), 50% duty cycle, also the reference clock of PLL.

DXP — Temperature sensing diode (anode +).

DXN — Temperature sensing diode (cathode –).

SCAN and BSCAN Pins*

SCAN_TSTMD I Scan test mode input.

SCANEN I Scan mode enable input.

LVDS_EN I LVDS enable used during BSCAN. During normal operation, LVDS_EN

needs to be pulled high. LVDS_EN needs to be pulled low for boundary

scan.

Universal BIST Controller Pins

SYS_DOBIST I SYS_DOBIST is asserted high to start the BIST, should be kept high during

the entire BIST operation.

SYS_RSSIGO O This 32-bit serial out RSB signature consists of the 4-bit FSM state and the

BIST flag flip-flop states from each SBRIC_RS element.

BC O This flag is asserted to one when BIST is complete, is used for polling the

end of BIST.

Symbol I/O Description

* BSCAN pins-TDI, TDO , TCK, TMS are on FPGA side.

Pin Information (continued)

Table 29. FPSC Function Pin Description (con tinued)

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

54 Lucent Technologies Inc.

Lucent Technologies Inc.

Pin Information (continued)

In Table 30, an input refers to a signal flowing into the FGPA logic (out of the embedded core) and an output refers

to a signal flowing out of the FPGA logic (into the embedded core).

Table 30. Embedded Core/FPGA Interface Signal Description

Pin Name I/O Description

DATA_TXA<7:0> O Parallel bus of transmitter A. MSB is bit 7.

DATA_TXA_PAR O Parity for transmitter A.

DATA_TXB<7:0> O Parallel bus of transmitter B. MSB is bit 7.

DATA_TXB_PAR O Parity for transmitter B.

DATA_TXC<7:0> O Parallel bus of transmitter C. MSB is bit 7.

DATA_TXC_PAR O Parity for transmitter C.

DATA_TXD<7:0> O Parallel bus of transmitter D. MSB is bit 7.

DATA_TXD_PAR O Parity for transmitter D.

DATA_RXA<7:0> I Parallel bus of receiver A. MSB is bit 7.

DATA_RXA_PAR I Parity for parallel bus of receiver A.

DATA_RXA_SPE I SPE signal for parallel bus of receiver A.

DATA_RXA_C1J1 I C1J1 signal for parallel bus of receiver A.

DATA_RXA_EN I Enable for parallel bus of receiver A.

DATA_RXB<7:0> I Parallel bus of receiver B. MSB is bit 7.

DATA_RXB_PAR I Parity for parallel bus of receiver B.

DATA_RXB_SPE I SPE signal for parallel bus of receiver B.

DATA_RXB_C1J1 I C1J1 signal for parallel bus of receiver B.

DATA_RXB_EN I Enable for parallel bus of receiver B.

DATA_RXC<7:0> I Parallel bus of receiver C . MSB is bit 7.

DATA_RXC_PAR I Parity for parallel bus of receiver C.

DATA_RXC_SPE I SPE signal for parallel bus of receiver C.

DATA_RXC_C1J1 I C1J1 signal for parallel bus of receiver C.

DATA_RXC_EN I Enable for parallel bus of receiver C.

DATA_RXD<7:0> I Parallel bus of receiver D. MSB is bit 7.

DATA_RXD_PAR I Parity for parallel bus of receiver D.

DATA_RXD_SPE I SPE signal for parallel bus of receiver D.

DATA_RXD_C1J1 I C1J1 signal for parallel bus of receiver D.

DATA_RXD_EN I Enable for parallel bus of receiver D.

TOH_CLK O TX and RX TOH serial links clock (25 MHz to 77.76 MHz).

TOH_TXA O TOH serial link for transmitter A.

TOH_TXB O TOH serial link for transmitter B.

TOH_TXC O TOH serial link for transmitter C.

TOH_TXD O TOH serial link for transmitter D.

TX_TOH_CK_EN O TX TOH serial link clock enable.

TOH_RXA I TOH serial link for receiver A.

TOH_RXB I TOH serial link for receiver B.

TOH_RXC I TOH serial link for receiver C.

Lucent Technologies Inc. 55

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

TOH_RXD I TOH serial link for receiver D.

RX_TOH_CK_EN I RX TOH serial link clock enable.

RX_TOH_FP I RX TOH serial link frame pulse.

TOH_CK_FP_EN I TX TOH clock and frame pulse enable.

TOH_EN_A I TX TOH enab le, soft register control.

Can be used for channel A, B, C, or D.

CPU_DATA_TX<7:0> O CPU interface data bus.

CPU_DATA_RX<7:0> I CPU interface data bus.

CPU_ADDR<6:0> O CPU interface address bus.

CPU_RD_WR_N O CPU interface read/write.

CPU_CS_N O Chip select.

CPU_INT_N I Interrupt.

SYS_FP O System frame pulse for transmitter section.

LINE_FP O Line frame pulse for receiver section.

FPGA_SYSCLK O System clock (77.76 MHz).

PROT_SW_A O Protection switching control signal.

PROT_SW_C O Protection switching control signal.

CORE_READY I Flag indicates that the embedded core is out of its reset state.

FIFOSYNC_FP I The alignment FIFO synchronizes and locates the data frames

and outputs an optimal frame pulse for the four arriving data

streams.

CDR_CLK_A I 77.76 MHz recovered clock for channel A.

CDR_CLK_B I 77.76 MHz recovered clock for channel B.

CDR_CLK_C I 77.76 MHz recovered clock for channel C.

CDR_CLK_D I 77.76 MHz recovered clock for channel D.

RB_MP_SEL I Bit stream selection for microprocessor interface selection.

A 0 indicates the microprocessor interface on the core side is

selected. A 1 selects the CPU interface from the FPGA side.

Pin Name I/O Description

Pin Information (continued)

Table 30. Embedded Core/FPGA Interface Signal Description (c on tinued)

5656 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

T able 31. Embedded Core/FPGA Interface Signal Locations

Embedded

Core/FPGA

Interface

Site

FPGA Input

Signal FPGA Output

Signal

ASB1A TOH_RXA TOH_TXA

ASB1B TOH_RXB TOH_TXB

ASB1C TOH_RXC TOH_TXC

ASB1D TOH_RXD TOH_TXD

CKTOASB1 — TOH_CLK

ASB2A RX_TOH_CK_EN —

ASB2B RX_TOH_FP —

ASB2C TOH_CK_FP_EN TX_TOH_CK_EN

ASB2D TOH_EN_A —

ASB3A DATA_RXA7 —

ASB3B DATA_RXA6 —

ASB3C DATA_RXA5 —

ASB3D DATA_RXA4 —

ASB4A DATA_RXA3 —

ASB4B DATA_RXA2 —

ASB4C DATA_RXA1 —

ASB4D DATA_RXA0 —

ASB5A DATA_RXA_PAR PROT_SW_A

ASB5B DATA_RXA_SPE —

ASB5C DATA_RXA_C1J1 —

ASB5D DATA_RXA_EN —

ASB6A DATA_RXTB7 —

ASB6B DATA_RXB6 —

ASB6C DATA_RXB5 —

ASB6D DATA_RXB4 —

ASB7A DATA_RXB3 —

ASB7B DATA_RXB2 —

ASB7C DATA_RXB1 —

ASB7D DATA_RXB0 —

ASB8A DATA_RXB_PAR —

ASB8B DATA_RXB_SPE —

ASB8C DATA_RXB_C1J1 —

ASB8D DATA_RXB_EN —

ASB9A DATA_RXC7 —

ASB9B DATA_RXC6 —

ASB9C DATA_RXC5 —

ASB9D DATA_RXC4 —

ASB10A DATA_RXC3 —

ASB10B DATA_RXC2 —

Embedded

Core/FPGA

Interface

Site

FPGA Input

Signal FPGA Output

Signal

ASB10C DATA_RXC1 —

ASB10D DATA_RXC0 —

ASB11A DATA_RXC_PAR PROT_SW_C

ASB11B DATA_RXC_SPE —

ASB11C DATA_RXC_C1J1 —

ASB11D DATA_RXC_EN

ASB12A DATA_RXD7 —

ASB12B DATA_RXD6 —

ASB12C DATA_RXD5 —

ASB12D DATA_RXD4 —

ASB13A DATA_RXD3 —

ASB13B DATA_RXD2 —

ASB13C DATA_RXD1 —

ASB13D DATA_RXD0 —

ASB14A DATA_RXD_PAR LINE_FP

ASB14B DATA_RXD_SPE SYS_FP

ASB14C DATA_RXD_C1J1 —

ASB14D DATA_RXD_EN —

CKFRASB14 — —

ASB15A FIFOSYNC_FP DATA_TXA7

ASB15B — DATA_TXA6

ASB15C — DATA_TXA5

ASB15D — DATA_TXA4

ASB16A — DATA_TXA3

ASB16B — DATA_TXA2

ASB16C — DATA_TXA1

ASB16D — DATA_TXA0

ASB17A — DATA_TXB7

ASB17B — DATA_TXB6

ASB17C — DATA_TXB5

ASB17D — DATA_TXB4

ASB18A — DATA_TXB3

ASB18B — DATA_TXB2

ASB18C — DATA_TXB1

ASB18D — DATA_TXB0

ASB19A — DATA_TXA_PAR

ASB19B — DATA_TXB_PAR

ASB19C — DATA_TXC_PAR

ASB19D — DATA_TXD_PAR

Pin Information (continued)

Table 31 lists the physical locations of all signals on the embedded core/FPGA interface.

Lucent Technologies Inc. 57

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Embedded

Core/FPGA

Interface

Site

FPGA Input

Signal FPGA Output

Signal

ASB20A — DATA_TXC7

ASB20B — DATA_TXC6

ASB20C — DATA_TXC5

ASB20D — DATA_TXC4

ASB21A — DATA_TXC3

ASB21B — DATA_TXC2

ASB21C — DATA_TXC1

ASB21D — DATA_TXC0

ASB22A — DATA_TXD7

ASB22B — DATA_TXD6

ASB22C — DATA_TXD5

ASB22D — DATA_TXD4

ASB23A — DATA_TXD3

ASB23B — DATA_TXD2

ASB23C — DATA_TXD1

ASB23D — DATA_TXD0

ASB24A CPU_DATA_RX7 CPU_DATA_TX7

ASB24B CPU_DATA_RX6 CPU_DATA_TX6

ASB24C CPU_DATA_RX5 CPU_DATA_TX5

Embedded

Core/FPGA

Interface

Site

FPGA Input

Signal FPGA Output

Signal

ASB24D CPU_DATA_RX4 CPU_DATA_TX4

ASB25A CPU_DATA_RX3 CPU_DATA_TX3

ASB25B CPU_DATA_RX2 CPU_DATA_TX2

ASB25C CPU_DATA_RX1 CPU_DATA_TX1

ASB25D CPU_DATA_RX0 CPU_DATA_TX0

ASB26A CPU_INT_N CPU_ADDR6

ASB26B — CPU_ADDR5

ASB26C — CPU_ADDR4

ASB26D CORE_READY CPU_ADDR3

ASB27A — CPU_ADDR2

ASB27B — CPU_ADDR1

ASB27C — CPU_ADDR0

ASB27D — CPU_RD_WR_N

ASB28A CDR_CLK_A CPU_CS_N

ASB28B CDR_CLK_B —

ASB28C CDR_CLK_C —

ASB28D CDR_CLK_D —

BMLKCNTL FPGA_SYSCLK —

Pin Information (continued)

Table 31. Embedded Core/FPGA Interface Signal Locations (continued)

5858 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin Information (continued)

The ORT4622 is pin compatible with a Series 3 OR3L125B device in the same package in terms of VDD, VSS,

configuration, and special function pins. The uses and characteristics of the FPGA user I/O pins in the embed-

ded core area of the device have changed to support the ORT4622 functionality. Additionally, the lower-left pro-

grammable clock manager (PCM) clock input pin (SECKLL) has been relocated.

Table 32. 432-Pin EBGA Pinout

Pin ORT4622 Pad Function

E4 PRD_CFGN RD_CFG

D3 PR1D I/O

D2 PR1C I/O

D1 PR1B I/O

F4 PR1A I/O

E3 PR2D I/O

E2 PR2C I/O

E1 PR2B I/O

F3 PR2A I/O

F2 PR3D I/O

F1 PR3C I/O

H4 PR3B I/O

G3 PR3A I/O-WR

G2 PR4D I/O

G1 PR4C I/O

J4 PR4B I/O

H3 VDD2V

DD2

H2 PR5A I/O

J3 PR6C I/O

K4 PR6A I/O

J2 PR7A I/O-RD/MPI_STRB

J1 PR8D I/O

K3 PR8C I/O

K2 PR8B I/O

K1 PR8A I/O

L3 PR9D I/O

M4 PR9C I/O

L2 PR9B I/O

L1 PR9A I/O-CS0

M3 PR10D I/O

N4 PR10A I/O

M2 PR11D I/O

N3 PR11A I/O-CS1

N2 PR12D I/O

P4 PR12C I/O

N1 PR12A I/O

P3 PR13D I/O

P2 PR13C I/O

Pin ORT4622 Pad Function

P1 VDD2V

DD2

R3 PR14D I/O

R2 PR14C I/O

R1 PR14B I/O

T2 PECKR I/O-ECKR

T4 PR15D I/O

T3 PR15C I/O

U1 PR15B I/O

U2 PR15A I/O

U3 PR16D I/O

V1 PR16B I/O

V2 PR16A I/O

V3 PR17D I/O

W1 PR17A I/O-M3

V4 PR18D I/O

W2 PR18B I/O

W3 PR18A I/O

Y2 PR19D —

W4 PR19A M2

Y3 PR20D —

AA1 PR20C —

AA2 PR20B —

Y4 PR20A —

AA3 VDD2V

DD2

AB1 PR21C —

AB2 PR21B —

AB3 PR21A —

AC1 PR22D M1

AC2 PR23D —

AB4 PR23B —

AC3 PR23A —

AD2 PR24A —

AD3 PR25C —

AC4 PR25B —

AE1 PR25A DB3 (core)

AE2 PR26D DB2 (core)

AE3 PR26C DB1 (core)

AD4 PR26B DB0 (core)

Lucent Technologies Inc. 59

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Pin Information (continued)

Table 32. 432-Pin EBGA Pinout (continued)

Pin ORT4622 Pad Function

AF1 PR26A DB7 (core)

AF2 PR2 7D DB6 (core)

AF3 PR2 7C DB5 (core)

AG1 PR27B DB4 (core)

AG2 VDD2V

DD2

AG3 PR28D INT_N (core)

AF4 PR28C —

AH1 PR28B RST_N

AH2 PR28A M0

AH3 PPRGMN PRGM

AG4 PRESETN RESET

AH5 PDONE DONE

AJ4 PB28D RD_WR_N (core)

AK4 PB28C CS_N (core)

AL4 PB28B ADDR0 (core)

AH6 PB28A ADDR1 (core)

AJ5 PB27D ADDR2 (core)

AK5 PB27C ADDR3 (core)

AL5 PB27B ADDR4 (core)

AJ6 PB27A ADDR5 (core)

AK6 PB26D ADDR6 (core)

AL6 PB26C TSTMUX0S (core)

AH8 PB26B TSTMUX1S (core)

AJ7 PB26A TSTMUX2S (core)

AK7 PB25D TSTMUX4S (core)

AL7 PB25C TSTMUX7S (core)

AH9 PB25B TSTMUX3S (core)

AJ8 VDD2V

DD2

AK8 PB24D TSTMUX6S (core)

AJ9 PB24C TSTMUX5S (core)

AH10 PB24B TSTMUX8S (core)

AK9 PB24A INIT

AL9 PB23D TSTPHASE (core)

AJ10 PB23C LOOPBKEN (co re)

AK10 PB23A EXDNUP (core)

AL 10 PB22A ECSEL (core)

AJ11 PB21D ETOGGLE (core)

AH12 PB21A RESETTN (core)

AK11 PB20D MRESET (core)

Pin ORT4622 Pad Function

AL11 PB20A LDC

AJ12 PB19D TSTSHFTLD (core)

AH13 PB19B RESETRN (core)

AK12 PB19A TSTCLK (core)

AJ13 P B1 8D BYPASS (cor e)

AK13 PB18B TSTMOD E (core)

AH14 PB18A HDC

AL13 PB17D —

AJ14 PB17B —

AK14 PB17A SYS_CLK (cor e)

AL14 PB16D —

AJ15 VDD2V

DD2

AK15 PB15D STS_OUTD (core)

AL15 PB15C STS_OUTDN (core)

AK16 PB15B —

AH16 PECKB STS_OUTC (core)

AJ16 PB14D STS_OUTCN (core)

AL17 PB14C RESLO (core)

AK17 PB14B RESHI (core)

AJ17 PB14A —

AL18 PB1 3D REF14 (core)

AK18 PB13B REF10 (core)

AJ18 PB13A REXT

AL19 PB12D PLL_VSSA

AH18 PB12A PLL_VDDA

AK19 PB11D STS_OUTB (cor e)

AJ19 PB11B STS_OUTBN (core)

AK20 PB11A —

AH19 PB10D STS_OU TA (core)

AJ20 PB10B STS_OUTAN (core)

AL21 VDD2V

DD2

AK21 PB9D CTAP_REFD (core)

AH20 PB9A STS_IND (core)

AJ21 PB8D STS_INDN (core)

AL22 PB8A STS_INC (core)

AK22 PB7D STS_INCN (core)

AJ22 PB7A C TAP_R EFC (core)

AL23 PB 6D STS_INB (cor e)

AK23 PB6A STS_INBN (core)

6060 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin Information (contin ued)

Table 32. 432-Pin EBGA Pinout (continued)

Pin ORT4622 Pad Function

AH22 PB5D CTAP_REFB (core)

AJ23 PB5C STS_INA (core)

AK24 PB5B STS_INAN (core)

AJ24 PB5A CTAP_REFA (core)

AH23 PB4D —

AL25 PB4C —

AK25 PB4B —

AJ25 PB4A LVDS_EN (core)

AH24 PB3D SCAN_TSTMD (core)

AL26 PB3C SCANEN (core)

AK26 PB3 B DXP (core)

AJ26 PB 3A DXN (core)

AL27 VDD2V

DD2

AK27 PB2C SYS_DOBIST (core)

AJ27 PB2B SYS_RSSIGO (core)

AH26 PB2A BC (core)

AL28 PB1D —

AK28 PB1C —

AJ28 PB1B —

AH27 PB1A —

AG28 PCCLK CCLK

AH29 PL28A —

AH30 PL28B —

AH31 PL28C —

AF28 PL28D —

AG29 PL27A —

AG30 PL27B —

AG31 PL27C —

AF29 PL27D —

AF30 PL26A —

AF31 PL26B —

AD28 PL26C —

AE29 VDD2V

DD2

AE30 PL25A —

AE31 PL25B —

AC28 PL25C —

AD29 PL24A —

AD30 PL24D —

AC29 PL23D —

AB28 PL22C —

Pin ORT4622 Pad Function

AC30 PL22D —

AC31 PL21A —

AB29 PL21B —

AB30 PL21C —

AB31 PL21D —

AA29 PL20A —

Y28 PL20B —

AA30 PL20C —

AA31 PL20D —

Y29 PL19A MPI_IRQ

W28 PL19D —

Y30 PL18A I/O-SECKLL

W29 PL18C I/O

W30 PL18D I/O

V28 PL17A I/O-MPI_BI

W31 PL17C I/O

V29 PL17D I/O

V30 PL16A I/O

V31 PL16C I/O

U29 PL16D I/O

U30 PL15A I/O-MPI_RW

U31 PL15B I/O

T30 VDD2V

DD2

T28 PL15D I/O

T29 PL14A I/O-MPI_CLK

R31 PL14B I/O

R30 PL14C I/O

R29 PECKL I/O-ECKL

P31 PL13A I/O

P30 PL13D I/O

P29 PL12A I/O

N31 PL12C I/O

P28 PL12D I/O

N30 PL11A I/O-A4

N29 PL11C I/O

M30 PL11D I/O

N28 PL10A I/O

M29 PL10C I/O

L31 VDD2V

DD2

L30 PL9A I/O-A3

Lucent Technologies Inc. 61

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Pin Information (continued)

Table 32. 432-Pin EBGA Pinout (continued)

Pin ORT4622 P ad Function

M28 PL9B I/O

L29 PL9C I/O

K31 PL9D I/O

K30 PL8A I/O-A2

K29 PL8B I/O

J31 PL8C I/O

J30 PL8D I/O

K28 PL7D I/O-A1/MPI_BE1

J29 PL6B I/O

H30 PL6C I/O

H29 PL6D I/O

J28 PL5D I/O

G31 PL4B I/O

G30 PL4C I/O

G29 VDD2V

DD2

H28 PL3A I/O

F31 PL3B I/O

F30 PL3C I/O

F29 PL3D I/O

E31 PL2A I/O

E30 PL2B I/O

E29 PL2C I/O

F28 PL2D I/O-A0/MPI_BE0

D31 PL1A I/O

D30 PL1B I/O

D29 PL1C I/O

E28 PL1D I/O

D27 PRD_DATA RD_DATA/TDO

C28 PT1A I/O-TCK

B28 PT1B I/O

A28 PT1C I/O

D26 PT1D I/O

C27 PT2A I/O

B27 PT2B I/O

A27 PT2C I/O

C26 PT2D I/O

B26 PT3A I/O

A26 PT3B I/O

D24 PT3C I/O

Pin ORT4622 P ad Function

C25 PT3D I/O

B25 PT4A I/O-TMS

A25 PT4B I/O

D23 PT4C I/O

C24 PT4D I/O

B24 VDD2V

DD2

C23 PT5B I/O

D22 PT5C I/O

B23 PT5D I/O

A23 PT6A I/O-TDI

C22 PT6D I/O

B22 PT7A I/O

A22 PT7D I/O

C21 PT8A I/O

D20 PT8D I/O

B21 PT9A I/O

A21 PT9D I/O

C20 PT10A I/O-DOUT

D19 PT10D I/O

B20 PT11A I/O

C19 PT11C I/O

B19 PT11D I/O

D18 PT12A I/O-D0/DIN

A19 PT12C I/O

C18 PT12D I/O

B18 PT13A I/O

A18 PT13C I/O

C17 PT13D I/O-D1

B17 PT14A I/O-D2

A17 VDD2V

DD2

B16 PT14C I/O

D16 PT14D I/O

C16 PT15A I/O-D3

A15 PT15B I/O

B15 PT15C I/O

C15 PECKT I/O-ECKT

A14 PT16A I/O-D4

B14 PT16B I/O

C14 PT16D I/O

6262 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin Information (continued)

Table 32. 432-Pin EBGA Pinout (continued)

Pin ORT4622 P ad Function

A13 PT17A I/O

D14 PT17B I/O

B13 PT17D I/O

C13 PT18A I/O-D5

B12 PT18B I/O

D13 VDD2V

DD2

C12 PT19A I/O

A11 PT19D I/O

B11 PT20A I/O

D12 PT20D I/O-D6

C11 PT21A I/O

A10 PT21D I/O

B10 PT22D I/O

C10 PT23B I/O

A9 PT23C I/O

B9 VDD2V

DD2

D10 PT24A I/O

C9 PT24B I/O

B8 PT24C I/O

C8 PT24D I/O-D7

D9 PT25A I/O

A7 PT25B I/O

B7 PT25C I/O

C7 PT25D I/O

D8 PT26A I/O

A6 PT26B I/O

B6 PT26C I/O

C6 PT26D I/O

A5 PT27A I/O-RDY/RCLK

B5 PT27B I/O

C5 PT27C I/O

D6 PT27D I/O

A4 PT28A I/O

B4 PT28B I/O

C4 PT28C I/O

D5 PT28D I/O-SECKUR

A12 VSS VSS

A16 VSS VSS

A2 VSS VSS

A20 VSS VSS

A24 VSS VSS

A29 VSS VSS

Pin ORT4622 Pad Function

A3 VSS VSS

A30 VSS VSS

A8 VSS VSS

AD1 VSS VSS

AD31 VSS VSS

AJ1 VSS VSS

AJ2 VSS VSS

AJ30 VSS VSS

AJ31 VSS VSS

AK1 VSS VSS

AK29 VSS VSS

AK3 VSS VSS

AK31 VSS VSS

AL12 VSS VSS

AL16 VSS VSS

AL2 VSS VSS

AL20 VSS VSS

AL24 VSS VSS

AL29 VSS VSS

AL3 VSS VSS

AL30 VSS VSS

AL8 VSS VSS

B1 VSS VSS

B29 VSS VSS

B3 VSS VSS

B31 VSS VSS

C1 VSS VSS

C2 VSS VSS

C30 VSS VSS

C31 VSS VSS

H1 VSS VSS

H31 VSS VSS

M1 VSS VSS

M31 VSS VSS

T1 VSS VSS

T31 VSS VSS

Y1 VSS VSS

Y31 VSS VSS

A1 VDD VDD

A31 VDD VDD

AA28 VDD VDD

AA4 VDD VDD

Lucent Technologies Inc. 63

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Pin Information (continued)

Table 32. 432-Pin EBGA Pinout (continued)

Pin ORT4622 Pad Function

AE28 VDD VDD

AE4 VDD VDD

AH11 VDD VDD

AH15 VDD VDD

AH17 VDD VDD

AH21 VDD VDD

AH25 VDD VDD

AH28 VDD VDD

AH4 VDD VDD

AH7 VDD VDD

AJ29 VDD VDD

AJ3 VDD VDD

AK2 VDD VDD

AK30 VDD VDD

AL1 VDD VDD

AL31 VDD VDD

B2 VDD VDD

B30 VDD VDD

Pin ORT4622 Pad Function

C29 VDD VDD

C3 VDD VDD

D11 VDD VDD

D15 VDD VDD

D17 VDD VDD

D21 VDD VDD

D25 VDD VDD

D28 VDD VDD

D4 VDD VDD

D7 VDD VDD

G28 VDD VDD

G4 VDD VDD

L28 VDD VDD

L4 VDD VDD

R28 VDD VDD

R4 VDD VDD

U28 VDD VDD

U4 VDD VDD

6464 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin Information (continued)

Table 33. 680-Pin PBGAM Pinout

Pin ORT4622 Pad Function

D1 PL1D I/O

E2 — —

E1 — —

F4 PL1C I/O

F3 PL1B I/O

F2 PL1A I/O

F1 PL2D I/O-A0

G5 PL2C I/O

G4 PL2B I/O

G2 PL2A I/O

G1 PL3D I/O

H5 PL3C I/O

H4 PL3B I/O

H2 PL3A I/O

H1 PL4C I/O

J5 PL4B I/O

J4 PL4A I/O

J3 PL5D I/O

J2 PL5C I/O

J1 PL5B I/O

K5 PL5A I/O

K4 PL6D I/O

K3 PL6C I/O

K2 PL6B I/O

K1 PL6A I/O

L5 PL7D I/O-A1

L4 PL7C I/O

L2 PL7B I/O

L1 PL7A I/O

M5 PL8D I/O

M4 PL8C I/O

M2 PL8B I/O

M1 PL8A I/O-A2

N5 PL9D I/O

N4 PL9C I/O

N3 PL9B I/O

N2 PL9A I/O-A3

N1 PL10C I/O

P5 PL10B I/O

P4 PL10A I/O

Pin ORT4622 Pad Function

P3 PL11D I/O

P2 PL11C I/O

P1 PL11B I/O

R5 PL11A I/O-A4

R4 PL12D I/O-A5

R2 PL12C I/O

R1 PL12B I/O

T5 PL13D I/O

T4 PL13C I/O

T2 PL13B I/O

T1 PL13A I/O

U5 PECKL I/O-ECKL

U4 — —

U3 PL14C I/O

U2 PL14B I/O

U1 PL14A I/O

V1 PL15D I/O

V2 PL15B I/O

V3 PL15A I/O

V4 PL16D I/O

V5 PL16C I/O

W1 PL16B I/O

W2 PL16A I/O

W4 PL17D I/O

W5 PL17C I/O

Y1 PL17B I/O

Y2 PL17A I/O

Y4 PL18D I/O

Y5 PL18C I/O

AA1 PL18B I/O

AA2 PL18A I/O-SECKLL

AA3 PL19D —

AA4 PL19C —

AA5 PL19B —

AB1 PL19A MPI_IRQ

AB2 PL20D —

AB3 PL20C —

AB4 PL20A —

AB5 PL21D —

AC1 PL21C —

Lucent Technologies Inc. 65

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Pin ORT4622 Pad Function

AC2 PL21B —

AC4 PL21A —

AC5 PL22D —

AD1 PL22C —

AD2 PL22B —

AD4 PL22A —

AD5 PL23D —

AE1 PL23C —

AE2 PL23B —

AE3 PL23A —

AE4 PL24D —

AE5 PL24C —

AF1 PL24B —

AF2 PL24A —

AF3 PL25D —

AF4 PL25C —

AF5 PL25B —

AG1 PL25A —

AG2 PL26C —

AG4 PL26B —

AG5 PL26A —

AH1 PL27D —

AH2 PL27C —

AH4 PL27B —

AH5 PL27A —

AJ1 — —

AJ2 — —

AJ3 PL28D —

AJ4 PL28C —

AK1 PL28B —

AK2 PL28A —

AL1 PCCLK CCLK

AP4 PB1A —

AN5 PB1B —

AP5 — —

AL6 — —

AM6 PB1C —

AN6 PB1D —

AP6 PB2A BC

AK7 PB2B SYS_RSSIGO

AL7 PB2C SYS_DOBIST

Pin ORT4622 Pad Function

AN7 PB3A DXN (core)

AP7 PB3B DXP (core)

AK8 PB3C SCANEN (core)

AL8 PB3D SCAN_TSTMD (core)

AN8 PB4A LVDS_EN (co re)

AP8 PB4B —

AK9 PB4C —

AL9 PB4D —

AM9 PB5A CTAP_REFA (c ore)

AN9 PB5B STS_INAN (core)

AP9 PB5C STS_INA (core)

AK10 PB5D CTAP_REFB (core)

AL10 PB6A STS_INBN (core)

AM10 PB6B STS_INB (core)

AN10 PB6C —

AP10 PB6D —

AK11 PB7A C TAP_REFC (core)

AL11 PB7B —

AN11 PB7C —

AP11 PB7D —

AK12 PB8A STS_INCN (core)

AL12 PB8B STS_INC (core)

AN12 PB8C STS_INDN (core)

AP12 PB8D STS_IND (core)

AK13 PB9A —

AL13 PB9B —

AM13 PB9C —

AN13 PB 9D CTAP_REFD (core)

AP13 PB10B —

AK14 PB10C STS_OUTAN (core)

AL14 PB10D STS_OUTA (core)

AM14 PB11A —

AN14 PB11B STS_OUTBN (core)

AP14 PB11C STS_OUTB (core)

AK15 PB11D —

AL15 PB12A PLL_VDDA (core)

AN15 PB12B —

AP15 PB12C —

AK16 PB12D PLL_VSSA (core)

Pin Information (continued)

Table 33. 680-Pin PBGA M Pinout (continued)

6666 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin ORT4622 Pad Function

AL16 PB13A REXT (core)

AN16 PB 13B REF10 (core)

AP16 PB13C —

AK17 PB1 3D RE F 14 (cor e)

AL17 — —

AM17 PB14B RESHI (core)

AN17 — —

AP17 PB14C RESLO (core)

AP18 PB14D STS_OUTCN (core)

AN18 PECKB STS_OUTC (core)

AM18 PB15B —

AL18 PB15C STS_OUTDN (core)

AK18 PB15D STS_OUTD (core)

AP19 PB16B —

AN19 PB16C —

AL19 PB16D —

AK19 PB17A SYS_CLK

AP20 PB17B —

AN20 PB17C —

AL20 PB17D —

AK20 PB18A HDC

AP21 PB18B TSTMODE

AN21 PB18C —

AM21 PB18D BYPASS

AL21 PB19A TSTCLK

AK21 PB19B RESETRN

AP22 PB19C TSTSHFTLD

AN22 PB20A LDC

AM22 PB20B —

AL22 PB20C —

AK22 PB20D MRESET (core)

AP23 PB21A RESETTN (core)

AN23 PB21B —

AL23 PB21C —

AK23 PB21D ETOGGLE (core)

AP24 PB22A ECSEL (core)

AN24 PB22B —

AL24 PB22C —

Pin ORT4622 Pad Function

AK24 PB22D —

AP25 PB23A EXDNUP (core)

AN25 PB23B —

AM25 PB23C LOOPBKEN (core)

AL25 PB23D TSTPHASE (core)

AK25 PB24A INIT

AP26 PB24B TSTMUX8S (core)

AN26 PB24C TSTMUX5S (core)

AM26 PB24D TSTMUX6S (core )

AL26 PB25B TSTMUX3S (core)

AK26 PB25C TSTMUX 7S (core)

AP27 PB25D TSTMUX 4S (core)

AN27 PB26A TSTMUX2S (core)

AL27 PB26B TSTMUX1S (core)

AK27 PB26C TSTMUX 0S (core)

AP28 PB26D ADDR 6 (core)

AN28 PB27A ADDR5 (core)

AL28 PB27B ADDR4 (core)

AK28 PB27C ADDR 3 (core)

AP29 PB27D ADDR 2 (core)

AN29 PB28A ADDR1 (core)

AM29 PB28B ADDR0 (core)

AL29 — —

AP30 PB28C CS_N (core)

AN30 PB28D RD_WR_N (core)

AP31 PDONE DONE

AL34 PRESETN RESET

AK33 PPRGMN PRGM

AK34 PR28A M0

AJ31 PR28B RST_N

AJ32 PR28C —

AJ33 PR28D INT_N

AJ34 PR27B DB4 (core)

AH30 PR27C DB5 (core)

AH31 PR27D DB6 (core)

AH33 PR26A DB7 (core)

AH34 PR26B DB0 (core)

AG30 PR26C DB1 (core)

Pin Information (continued)

Table 33. 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc. 67

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Pin Information (continued)

Table 33. 680-Pin PBGA M Pinout (continued)

Pin ORT4622 Pad Function

AG31 PR26D DB2 (core)

AG33 PR25A DB3 (core)

AG34 PR25B —

AF30 PR25C —

AF31 PR25D —

AF32 PR24A —

AF33 PR24B —

AF34 PR24C —

AE30 PR24D —

AE31 PR23A —

AE32 PR23B —

AE33 PR23C —

AE34 PR23D —

AD30 PR22A —

AD31 PR22B —

AD33 PR22C —

AD34 PR22D M1

AC30 PR21A —

AC31 PR21B —

AC33 PR21C —

AC34 PR20A —

AB30 PR20B —

AB31 PR20C —

AB32 PR20D —

AB33 PR19A M2

AB34 PR19B —

AA30 PR19C —

AA31 PR19D —

AA32 PR18A I/O

AA33 PR18B I/O

AA34 PR18C I/O

Y30 PR18D I/O

Y31 PR17A I/O-M3

Y33 PR17B I/O

Y34 PR17C I/O

W30 PR17D I/O

W31 PR16A I/O

W33 PR16B I/O

W34 PR16C I/O

V30 PR15A I/O

V31 — —

V32 PR15B I/O

Pin ORT4622 Pad Function

V33 PR15C I/O

V34 PR15D I/O

U34 PECKR I/O-ECKR

U33 PR14B I/O

U32 PR14C I/O

U31 PR14D I/O

U30 PR13B I/O

T34 PR13C I/O

T33 PR13D I/O

T31 PR12A I/O

T30 PR12B I/O

R34 PR12C I/O

R33 PR12D I/O

R31 PR11A I/O-CS1

R30 PR11B I/O

P34 PR11C I/O

P33 PR11D I/O

P32 PR10A I/O

P31 PR10B I/O

P30 PR10C I/O

N34 PR9A I/O-CS0

N33 PR9B I/O

N32 PR9C I/O

N31 PR9D I/O

N30 PR8A I/O

M34 PR8B I/O

M33 PR8C I/O

M31 PR8D I/O

M30 PR7A I/O-RD

L34 PR7B I/O

L33 PR7C I/O

L31 PR7D I/O

L30 PR6A I/O

K34 PR6B I/O

K33 PR6C I/O

K32 PR6D I/O

K31 PR5A I/O

K30 PR5B I/O

J34 PR5C I/O

J33 PR5D I/O

J32 PR4B I/O

J31 PR4C I/O

6868 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin Information (continued)

Table 33. 680-Pin PBGAM Pinout (continued)

Pin ORT4622 Pad Function

J30 PR4D I/O

H34 PR3A I/O-WR

H33 PR3B I/O

H31 PR3C I/O

H30 PR3D I/O

G34 PR2A I/O

G33 PR2B I/O

G31 PR2C I/O

G30 PR2D I/O

F34 PR1A I/O

F33 — —

F32 PR1B I/O

F31 PR1C I/O

E34 — —

E33 PR1D I/O

D34 PRD_CFGN RD_CFG

A31 PT28D I/O-SECKUR

B30 — —

A30 PT28C I/O

D29 — —

C29 PT28B I/O

B29 PT28A I/O

A29 PT27D I/O

E28 PT27C I/O

D28 PT27B I/O

B28 PT27A I/O-RDY/RCLK

A28 PT26D I/O

E27 PT26C I/O

D27 PT26B I/O

B27 PT26A I/O

A27 PT25D I/O

E26 PT25C I/O

D26 PT25B I/O

C26 PT25A I/O

B26 PT24D I/O-D7

A26 PT24C I/O

E25 PT24B I/O

D25 PT24A I/O

C25 PT23C I/O

B25 PT23B I/O

A25 PT23A I/O

E24 PT22D I/O

Pin ORT4622 Pad Function

D24 PT22C I/O

B24 PT22B I/O

A24 PT22A I/O

E23 PT21D I/O

D23 PT21C I/O

B23 PT21B I/O

A23 PT21A I/O

E22 PT20D I/O-D6

D22 PT20C I/O

C22 PT20B I/O

B22 PT20A I/O

A22 PT19D I/O

E21 PT19C I/O

D21 PT19B I/O

C21 PT19A I/O

B21 PT18C I/O

A21 PT18B I/O

E20 PT18A I/O-D5

D20 PT17D I/O

B20 PT17C I/O

A20 PT17B I/O

E19 PT17A I/O

D19 PT16D I/O

B19 PT16C I/O

A19 PT16B I/O

E18 PT16A I/O-D4

D18 PECKT I/O-ECKT

C18 PT15B I/O

B18 — —

A18 PT15A I/O-D3

A17 PT14D I/O

B17 PT14C I/O

C17 PT14A I/O-D2

D17 PT13D I/O-D1

E17 PT13C I/O

A16 PT13B I/O

B16 PT13A I/O

D16 PT12D I/O

E16 PT12C I/O

A15 PT12B I/O

B15 PT12A I/O-D0/DIN

D15 PT11D I/O

Lucent Technologies Inc. 69

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Pin ORT4622 Pad Function

E15 PT11C I/O

A14 PT11B I/O

B14 PT11A I/O

C14 PT10D I/O

D14 PT10C I/O

E14 PT10B I/O

A13 PT10A I/O-DOUT

B13 PT9C I/O

C13 PT9B I/O

D13 PT9A I/O

E13 PT8D I/O

A12 PT8C I/O

B12 PT8B I/O

D12 PT8A I/O

E12 PT7D I/O

A11 PT7C I/O

B11 PT7B I/O

D11 PT7A I/O

E11 PT6D I/O

A10 PT6C I/O

B10 PT6B I/O

C10 PT6A I/O-TDI

D10 PT5D I/O

E10 PT5C I/O

A9 PT5B I/O

B9 PT4D I/O

C9 PT4C I/O

D9 PT4B I/O

E9 PT4A I/O-TMS

A8 PT3D I/O

B8 PT3C I/O

D8 PT3B I/O

E8 PT3A I/O

A7 PT2D I/O

B7 PT2C I/O

D7 PT2B I/O

E7 PT2A I/O

A6 PT1D I/O

B6 — —

C6 PT1C I/O

D6 PT1B I/O

A5 — —

B5 PT1A I/O-TCK

Pin ORT4622 Pad Function

A4 PRD_DATA RD_DATA/TDO

A1 VSS VSS

A2 VSS VSS

A33 VSS VSS

A34 VSS VSS

B1 VSS VSS

B2 VSS VSS

B33 VSS VSS

B34 VSS VSS

C3 VSS VSS

C8 VSS VSS

C12 VSS VSS

C16 VSS VSS

C19 VSS VSS

C23 VSS VSS

C27 VSS VSS

C32 VSS VSS

D4 VSS VSS

D31 VSS VSS

H3 VSS VSS

H32 VSS VSS

M3 VSS VSS

M32 VSS VSS

N13 VSS VSS

N14 VSS VSS

N15 VSS VSS

N20 VSS VSS

N21 VSS VSS

N22 VSS VSS

P13 VSS VSS

P14 VSS VSS

P15 VSS VSS

P20 VSS VSS

P21 VSS VSS

P22 VSS VSS

R13 VSS VSS

R14 VSS VSS

R15 VSS VSS

R20 VSS VSS

R21 VSS VSS

R22 VSS VSS

T3 VSS VSS

T16 VSS VSS

Pin Information (continued)

Table 33. 680-Pin PBGAM Pinout (continued)

7070 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin Information (continued)

Table 33. 680-Pin PBGAM Pinout (continued)

Pin ORT4622 Pad Function

T17 VSS VSS

T18 VSS VSS

T19 VSS VSS

T32 VSS VSS

U16 VSS VSS

U17 VSS VSS

U18 VSS VSS

U19 VSS VSS

V16 VSS VSS

V17 VSS VSS

V18 VSS VSS

V19 VSS VSS

W3 VSS VSS

W16 VSS VSS

W17 VSS VSS

W18 VSS VSS

W19 VSS VSS

W32 VSS VSS

Y13 VSS VSS

Y14 VSS VSS

Y15 VSS VSS

Y20 VSS VSS

Y21 VSS VSS

Y22 VSS VSS

AA13 VSS VSS

AA14 VSS VSS

AA15 VSS VSS

AA20 VSS VSS

AA21 VSS VSS

AA22 VSS VSS

AB13 VSS VSS

AB14 VSS VSS

AB15 VSS VSS

AB20 VSS VSS

AB21 VSS VSS

AB22 VSS VSS

AC3 VSS VSS

AC32 VSS VSS

AG3 VSS VSS

AG32 VSS VSS

AL4 VSS VSS

AL31 VSS VSS

Pin ORT4622 Pad Function

AM3 VSS VSS

AM8 VSS VSS

AM12 VSS VSS

AM16 VSS VSS

AM19 VSS VSS

AM23 VSS VSS

AM27 VSS VSS

AM32 VSS VSS

AN1 VSS VSS

AN2 VSS VSS

AN33 VSS VSS

AN34 VSS VSS

AP1 VSS VSS

AP2 VSS VSS

AP33 VSS VSS

AP34 VSS VSS

C5 VDD2V

DD2

C30 VDD2V

DD2

D5 VDD2V

DD2

D30 VDD2V

DD2

E3 VDD2V

DD2

E4 VDD2V

DD2

E5 VDD2V

DD2

E6 VDD2V

DD2

E29 VDD2V

DD2

E30 VDD2V

DD2

E31 VDD2V

DD2

E32 VDD2V

DD2

F5 VDD2V

DD2

F30 VDD2V

DD2

N16 VDD2V

DD2

N17 VDD2V

DD2

N18 VDD2V

DD2

N19 VDD2V

DD2

P16 VDD2V

DD2

P17 VDD2V

DD2

P18 VDD2V

DD2

P19 VDD2V

DD2

R16 VDD2V

DD2

R17 VDD2V

DD2

R18 VDD2V

DD2

R19 VDD2V

DD2

Lucent Technologies Inc. 71

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Back

lane Transceiver

Lucent Technologies Inc.

Pin Information (continued)

Table 33. 680-Pin PBGA M Pinout (continued)

Pin ORT4622 Pad Function

T13 VDD2V

DD2

T14 VDD2V

DD2

T15 VDD2V

DD2

T20 VDD2V

DD2

T21 VDD2V

DD2

T22 VDD2V

DD2

U13 VDD2V

DD2

U14 VDD2V

DD2

U15 VDD2V

DD2

U20 VDD2V

DD2

U21 VDD2V

DD2

U22 VDD2V

DD2

V13 VDD2V

DD2

V14 VDD2V

DD2

V15 VDD2V

DD2

V20 VDD2V

DD2

V21 VDD2V

DD2

V22 VDD2V

DD2

W13 VDD2V

DD2

W14 VDD2V

DD2

W15 VDD2V

DD2

W20 VDD2V

DD2

W21 VDD2V

DD2

W22 VDD2V

DD2

Y16 VDD2V

DD2

Y17 VDD2V

DD2

Y18 VDD2V

DD2

Y19 VDD2V

DD2

AA16 VDD2V

DD2

AA17 VDD2V

DD2

AA18 VDD2V

DD2

AA19 VDD2V

DD2

AB16 VDD2V

DD2

AB17 VDD2V

DD2

AB18 VDD2V

DD2

AB19 VDD2V

DD2

AJ5 VDD2V

DD2

AJ30 VDD2V

DD2

AK3 VDD2V

DD2

AK4 VDD2V

DD2

AK5 VDD2V

DD2

Pin ORT4622 Pad Function

AK6 VDD2V

DD2

AK29 VDD2V

DD2

AK30 VDD2V

DD2

AK31 VDD2V

DD2

AK32 VDD2V

DD2

AL5 VDD2V

DD2

AL30 VDD2V

DD2

AM5 VDD2V

DD2

AM30 VDD2V

DD2

A3 VDD VDD

A32 VDD VDD

B3 VDD VDD

B4 VDD VDD

B31 VDD VDD

B32 VDD VDD

C1 VDD VDD

C2 VDD VDD

C4 VDD VDD

C7 VDD VDD

C11 VDD VDD

C15 VDD VDD

C20 VDD VDD

C24 VDD VDD

C28 VDD VDD

C31 VDD VDD

C33 VDD VDD

C34 VDD VDD

D2 VDD VDD

D3 VDD VDD

D32 VDD VDD

D33 VDD VDD

G3 VDD VDD

G32 VDD VDD

L3 VDD VDD

L32 VDD VDD

R3 VDD VDD

R32 VDD VDD

Y3 VDD VDD

Y32 VDD VDD

AD3 VDD VDD

AD32 VDD VDD

7272 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Pin ORT4622 Pad Function

AH3 VDD VDD

AH32 VDD VDD

AL2 VDD VDD

AL3 VDD VDD

AL32 VDD VDD

AL33 VDD VDD

AM1 VDD VDD

AM2 VDD VDD

AM4 VDD VDD

AM7 VDD VDD

AM11 VDD VDD

AM15 VDD VDD

Pin ORT4622 Pad Function

AM20 VDD VDD

AM24 VDD VDD

AM28 VDD VDD

AM31 VDD VDD

AM33 VDD VDD

AM34 VDD VDD

AN3 VDD VDD

AN4 VDD VDD

AN31 VDD VDD

AN32 VDD VDD

AP3 VDD VDD

AP32 VDD VDD

Pin Information (continued)

Table 33. 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc. 73

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Package Thermal Characte ristics

Summary

There are three thermal parameters that are in com-

mon use: ΘJA, ψJC , and ΘJC. It should be noted that all

the parameters are affected, to varying degrees, by

package design (including paddle size) and choice of

materials, the amount of copper in the test board or

system board, and system airflow.

ΘJA

This is the thermal resistance from junction to ambient

(a.k.a. theta-JA, R-theta, etc.).

where TJ is the junction temperature, TA is the ambient

air temperature, and Q is the chip power.

Experimentally, ΘJA is determined when a special ther-

mal test die is assembled into the package of interest,

and the part is mounted on the thermal test board. The

diodes on the test chip are separately calibrated in an

oven. The package/board is placed either in a JEDEC

natural convection box or in the wind tunnel, the latter

for forced conv ection measurements. A controlled

amount of power (Q) is dissipated in the test chip’s

heater resistor, the chip’s temperature (TJ) is deter-

mined by the f orward drop on the diodes, and the ambi-

ent temperature (TA) is noted. Note that ΘJA is

expressed in units of °C/watt.

ψJC

This JEDEC designated parameter correlates the junc-

tion temperature to the case temperature. It is generally

used to infer the junction temperature while the device

is operating in the system. It is not considered a true

thermal resistance, and it is defined by:

where TC is the case temperature at top dead center,

TJ is the junction temperature, and Q is the chip power.

Duri ng the ΘJA measurements described above,

besides the other parameters measured, an additional

temperature reading, TC, is made with a thermocouple

attached at top-dead-center of the case. ψJC is also

expressed in units of °C/watt.

ΘJC

This is the thermal resistance from junction to case. It

is most often used when attaching a heat sink to the

top of the package. It is defined by:

The parameters in this equation have been defined

above. However , the measurements are performed with

the case of the part pressed against a water-cooled

heat sink to draw most of the heat generated by the

chip out the top of the package. It is this difference in

the measurement process that differentiates ΘJC from

ψJC. ΘJC is a true thermal resistance and is expressed

in units of °C/watt.

ΘJB

This is the thermal resistance from junction to board

(a.k.a. ΘJL). It is defined by:

where TB is the temperature of the board adjacent to a

lead measured with a thermocouple. The other param-

eters on the right-hand side have been defined above.

This is considered a true thermal resistance, and the

measurement is made with a water-cooled heat sink

pressed against the board to draw most of the heat out

of the leads. Note that ΘJB is expressed in units of

°C/watt, and that this parameter and the way it is mea-

sured are still in JEDEC committee.

FPGA Maximum Junctio n Tempe rature

Once the pow er dissipated by the FPGA has been

determined (see the Estimating Power Dissipation sec-

tion), the maximum junction temperature of the FPGA

can be f ound. This is needed to determine if speed der-

ating of the device from the 85 °C junction temperature

used in all of the delay tables is needed. Using the

maximum ambient temperature, TAmax, and the power

dissipated by the device, Q (expressed in °C), the max-

imum junction temperature is approximated by:

TJmax = TAmax + (Q • ΘJA)

Table 34 lists the thermal characteristics for all pack-

ages used with the

ORCA

ORT4622 Series of FPGAs.

ΘJA TJTA

–

--------------------

ψJC TJTC

–

--------------------

ΘJC TJTC

–

--------------------

ΘJB TJTB

–

--------------------

74 Lucent Technologies Inc.

ORCA

ORT4622 FPSC Advanced Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

Lucent Technologies Inc.

Package Thermal Characteristics

Table 34

. ORCA

ORT4622 Plastic Package Thermal Guidelines

Package ΘJA (°C/W) TAMB = 70 °C Max

TJ = 125 °C Max

0 fpm (W)

0 fpm 200 fpm 500 fpm

432-Pin EBGA 11 8.5 5 5

680-Pin PBGAM 14.5 TBD TBD 3.8

Package Coplanarity

The coplanarity limits of the

ORCA

Series 3/3+ pack-

ages are as follows:

■EBGA: 8.0 mils

■PBGAM: 8.0 mils

Package Parasitics

The electrical performance of an IC package, such as

signal quality and noise sensitivity, is directly affected

b y the pac kage pa rasiti cs. Tab le 35 li sts eight pa rasiti cs

associated with the

ORCA

packages. These parasitics

represent the contributions of all components of a

package, which include the bond wires, all internal

package routing, and the external lea ds.

Four inductances in nH are listed: LSW and LSL, the

self-inductance of the lead; and LMW and LML, the

mutual inductance to the nearest neighbor lead. These

parameters are important in determining ground

bounce noise and inductive crosstalk noise. Three

capacitances in pF are listed: CM, the mutual capaci-

tance of the lead to the nearest neighbor lead; and C1

and C2, the total capacitance of the lead to all other

leads (all other leads are assumed to be grounded).

These parameters are important in determining capaci-

tive crosstalk and the capacitive loading effect of the

lead. Resistance v alues are in mΩ.

The parasitic values in Table 35 are for the circuit model

of bond wire and package lead parasitics. If the mutual

capacitance value is not used in the designer’s model,

then the value listed as mutual capacitance should be

added to each of the C1 and C2 capacitors.

Lucent Technologies Inc. 75

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Package Parasitics (continued)

Table 35.

ORCA

ORT4622 Package Parasitics

5-3862(C)r2

Figure 28. Package Parasitics

Package Type LSW LMW RWC1C2CMLSL LML

432-P in EBG A 4 1.5 50 0 1 .0 1 .0 0.3 3—5.5 0.5—1

680-P in PBG AM 3.8 1.3 25 0 1 .0 1 .0 0.3 2.8—5 0.5—1

PAD N LSW RW

CIRCUIT

BOARD PAD

LSW RWLSL

LMW

LML

LSL

PAD N + 1

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

76 Lucent Technologies Inc.

Lucent Technologies Inc.

Package Outline Diagrams

Te rm s an d Defi ni tio ns

Basic Size (BSC): The basic size of a dimension is the size from which the limits f or that dimension are derived

by the application of the allowance and the tolerance.

Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit

and tolerance.

Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is

specified or repeated basic size if a tolerance is not specified.

Ref erence (REF): The ref erence dimension is an untoleranced dimension used f or informational purposes only.

It is a repeated dimension or one that can be derived from other values in the drawing.

Minimum (MIN) or

Maximum (MAX): Indicates the minimum or maximum allowab le size of a dimension.

Lucent Technologies Inc. 77

Advance Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Package Outline Diagrams (continued)

432-Pin EBGA

Dimensions are in millimeters.

0.91 ± 0.06 1.54 ± 0.13

SEATING PLANE

SOLDER BALL

0.63 ± 0.07

0.20

40.00 ± 0.10

40.00

A1 BALL

19 3026

528242223 25720 312915 21

32711 17

4 6 81012141629131

30 SPACES @ 1.27 = 38.10

30 SPACES

A1 BALL

0.75 ± 0.15

IDEN TI FIER ZON E

± 0.10

@ 1.27 = 38.10

CORNER

ORCA

ORT4622 FPSC Advance Data Sheet

Four-Channel x 622 Mbits/s Backplane Transceiver November 1999

78 Lucent Technologies Inc.

Lucent Technologies Inc.

Package Outline Diagrams (continued)

680-Pin PBGAM

Dimensions are in millimeters.

5-4406(F)

SEATING PLANE

SOLDER BALL

0.50 ± 0.10

0.20

35.00

19 3026 2824 322220184 6 8 10121416234

523257312915 2132711 17913133

33 SPACES @ 1.00 = 33.00

33 SPACES

A1 BAL L

0.64 ± 0.15

A1 BALL

@ 1.00 = 33.00

CORNER

30.00

1.170

+ 0.70

– 0.00

35.00

30.00 + 0.70

– 0.00

IDENTI FIER ZONE

2.51 MAX

0.61 ± 0.08

Lucent Technologies Inc. 79

Advanced Data Sheet

ORCA

ORT4622 FPSC

November 1999 Four-Channel x 622 Mbits/s Backplane Transceiver

Lucent Technologies Inc.

Ordering Information

5-6435 (F).i

DEVICE TYPE

PACK AGE TYPE

ORT4622 -8 BC

NUMBER OF PINS

TEMPERATURE RANGE

432

FPGA SPEED GR ADE

Table 36. Voltage Options

Table 37. Temperature Options

Table 38. Package Type Options

Table 39

. ORCA

Series 3+ Package Matrix

Key: C = commercial, I = industrial.

Device Voltage

ORT4622 2.5 V/3.3 V

Symbol Description Temperature

(Blank) Commercial 0 °C to 70 °C

I Industrial –40 °C to +85 °C

Symbol Description

BC Enhanced Ball Grid Array (EBGA)

BM Plastic Ball Grid Array, Mult ilayer

Device

Package

432-Pin

EBGA 680-Pin

PBGAM

BC432 BM680

ORT4622 CI CI

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No

rights under any patent accompany the sale of any such product(s) or information.

ORCA

is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.

November 1999

DS99-334FPGA

For additional information, contact your Microelectronics Group Account Manager or the following:

INTERNET: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca

E-MAIL: docmaster@micro.lucent.com

N. AMERICA: Microelectronics Group, Lucent Tech no logies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road,

Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652

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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

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Technical Inqui ries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 13 44 865 90 0 (Ascot),

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