Standard Products UT80C196KDS Microcontroller Advanced Datasheet May, 2003 INTRODUCTION q 20MHz 16-bit Microcontroller compatible with industry standard's MCS-96 ISA - Register to Register Architecture - 1000 Byte Register RAM q Three 8-bit I/O Ports q On-board Interrupt Controller q Three Pulse-Width Modulated Outputs q High Speed I/O q UART Serial Port q Dedicated Baud Rate Generator q Software and Hardware Timers - 16-Bit Watchdog Timer, Four 16-Bit Software Timers - Three 16-Bit Counter/Timers q Error detection and correction for external memory accesses q QML Q compliant part q Standard Microcircuit Drawing 5962-02523 The UT80C196KDS is compatible with industry standard's MCS-96 instruction set. The UT80C196KDS is supported by commercial hardware and software development tools. EL O PM EN T FEATURES The UT80C196KDS accesses instruction code and data via a 16-bit address and data bus. The 16-bit bus allows the microcontroller to access 128K bytes of instruction/data memory. Integrated software and hardware timers, high speed I/O, pulse width modulation circuitry, and UART make the UT80C196KD ideal for control type applications. The CPU's ALU supports byte and word adds and subtracts, 8 and 16 bit multiplies, 32/16 and 16/8 bit divides, as well as increment, decrement, negate, compare, and logical operations. The UT80C196KDS's interrupt controller prioritizes and vectors 18 interrupt events. Interrupts include normal interrupts and special interrupts. To reduce power consumption, the microcontroller supports software invoked idle and power down modes. 1000 Bytes RAM CPU ALU Interrupt Controller F Co irst re P a IP ss IN D EV The UT80C196KDS is packaged in a 68-lead quad flatpack. PTS Register File MicroCode Engine Memory Controller Queue Watchdog Timer PWM Serial Port HSIO and Timers Alternate Functions Alternate Functions PORT0 EXTINT PORT2 HSI HSO PORT1 ECB0ECB5 Figure 1. UT80C196KDS Microcontroller 1 Control Signals Address /Data Bus HOLD HLDA BREQ PWM1 PWM2 1.0 SIGNAL DESCRIPTION Port 0 (P0.0 - P0.7): Port 0 is an 8-bit input only port when used in its default mode. When configured for their alternate function, five of the bits are bi-directional EDAC check bits as shown in Table 1. Table 2. Port 1 Alternate Functions Port 2 (P2.0 - P2.7): Port 2 is an 8-bit, multifunctional, I/O port. These pins are shared with timer 2 functions, serial data I/O and PWM0 output, per Table 3. AD0-AD7: The lower 8-bits of the multiplexed address/data bus. The pins on this port are bidirectional during the data phase of the bus cycle. AD8-AD15: The upper 8-bits of the multiplexed address/data bus. The pins on this port are bidirectional during the data phase of the 16-bit bus cycle. When running in 8-bit bus width, these pins are non-multiplexed, dedicated upper address bit outputs. P1.0 P1.0 I/O Pin P1.1 P1.1 I/O Pin P1.2 P1.2 I/O Pin P1.3 PWM1 Setting IOC3.2=1 enables P1.3 as the Pulse Width Modulator (PWM1) output pin. P1.4 PWM2 Setting IOC3.3=1 enables P1.4 as the Pulse Width Modulator (PWM2) output pin. P1.5 BREQ Bus Request, output activated when the bus controller has a pending external memory cycle. P1.6 HLDA Bus Hold Acknowledge, output indicating the release of the bus. P1.7 HOLD Bus Hold, input requesting control of the bus. EV HSI: Inputs to the High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2, and HSI.3. Two of these pins (HSI.2 and HSI.3) are shared with the HSO Unit. Two of these pins (HSI.0 and HSI.1) have alternate functions for Timer 2. IN D HSO: Outputs from the High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSO.3, HSO.4, and HSO.5. Pins HSO.4 and HSO.5 are shared with pins HSI.2 and HSI.3 of the HSI Unit respectively. Table 1. Port 0 Alternate Functions Port Pin Alternate Name P0.0-P0.3, P0.6 ECB0-ECB4 P0.4 P0.5 P0.7 Alternate Function Table 3. Port 2 Alternate Functions Port Pin Alternate Name P2.0 TXD Transmit Serial Data. P2.1 RXD Receive Serial Data. P2.2 EXTINT External interrupt. Clearing IOC1.1 will allow P2.2 to be used for EXTINT (INT07) P2.3 T2CLK Timer 2 clock input and Serial port baud rate generator input. P2.4 T2RST Timer 2 Reset P2.5 PWM0 Pulse Width Modulator output 0 P2.6 T2UP-DN Controls the direction of the Timer 2 counter. Logic High equals count down. Logic low equals count up. P2.7 T2CAPTURE A rising edge on P2.7 causes the value of Timer 2 to be captured into this register, and generates a Timer 2 Capture interrupt (INT11). Alternate Function Error Detection & Correction Check Bits Input Port Pins EXTINT T Alternate Name EL O PM EN Port 1 (P1.0 - P1.7): Port 1 is an 8-bit, quasi-bidirectional, I/O port. All pins are quasi-bidirectional unless the alternate function is selected per Table 2. When the pins are configured for their alternate functions, they act as standard I/O, not quasibidirectional. Port Pin Setting IOC1.1=1 will allow P0.7 to be used for EXTINT (INT07) 2 Alternate Function 1.1 Hardware Interface There are 8 configuration bits available in the CCR. However, bits 7 and 6 are not used by the UT80C196KDS. Bits 5 and 4 comprise the READY mode control which define internal limits for waitstates generated by the READY pin. Bit 3 controls the definition of the ALE/ADV pin for system memory controls while bit 2 selects between the different write modes. Bit 1 selects whether the UT80C196KDS will use a dynamic 16-bit bus or whether it will be locked in as an 8-bit bus. Finally, Bit 0 enables the Power Down mode and allows the user to disable this mode for protection against inadvertent power downs. 1.1.1 Interfacing with External Memory The UT80C196KDS can interface with a variety of external memory devices. It supports either a fixed 8-bit bus width or a dynamic 8-bit/16-bit bus width, internal READY control for slow external memory devices, a bus-hold protocol that enables external devices to take over the bus, and several bus-control modes. These features provide a great deal of flexibility when interfacing with external memory devices. 1.1.1.2 Bus Width and Memory Configurations The UT80C196KDS external bus can operate as either an 8-bit or 16-bit multiplexed address/data bus (see figure 2). The value of bit 1 in the CCR determines the bus operation. A logic low value on CCR.1 locks the bus controller in 8-bit bus mode. If, however, CCR.1 is a logic high, then the BUSWIDTH signal is used to decide the width of the bus. The bus is 16 bits wide when the BUSWIDTH signal is high, and is 8 bits when the BUSWIDTH signal is low. 1.1.1.1 Chip Configuration Register The Chip Configuration Register (CCR) is used to initialize the UT80C196KDS immediately after reset. The CCR is fetched from external address 2018H (Chip Configuration Byte) after removal of the reset signal. The Chip Configuration Byte (CCB) is read as either an 8-bit or 16-bit word depending on the value of the BUSWIDTH pin. The composition of the bits in the CCR are shown in Table 4. T 1.1.2 Reset To reset the UT80C196KDS, hold the RESET pin low for at least 16 state times after the power supply is within tolerance and the oscillator has stabilized. Resets following the power-up reset may be asserted for at least one state time, and the device will turn on a pull-down transistor for 16 state times. This enables the RESET signal to function as the system reset. The reset state of the external I/O is shown in Table 9, and the register reset values are shown in Table 8. 1.1.3 Instruction Set The instruction set for the UT80C196KDS is compatible with the industry standard MCS-96 instruction set used on the 8XC196KDS. EL O Function N/A N/A IRC1 - Internal READY Mode Control IRC0 - Internal READY Mode Control Address Valid Strobe Select (ALE/ADV) Write Strobe Mode Select (WR and BHE/WRL and WRH) Dynamic Bus Width Enable Enable Power Down Mode PM EN Table 4. Chip Configuration Register EV Table 5. Memory Map Memory Description External Memory1 Reserved PTS Vectors Upper Interrupt Vectors Reserved Reserved Chip Configuration Byte Reserved Lower Interrupt Vectors External Memory Internal Memory (RAM) Special Function Registers D IN Bit 7 6 5 4 3 2 1 0 Begin 02080H 0205EH 02040H 02030H 02020H 02019H 02018H 02014H 02000H 00400H 0001AH 00000H End 0FFFFH 0207FH 0205DH 0203FH 0202FH 0201FH 02018H 02017H 02013H 1FFFH 003FFH 00019H Notes: 1.The first instruction read following reset will be from location 2080h. All other external memory can be used as instruction a nd/or data memory. 3 Table 6. Interrupt Vector Sources, Locations, and Priorities Number Interrupt Vector Source(s) Interrupt Vector Location PTS Vector Location Priority1 (0 is the Lowest Priority) Unimplemented Opcode Unimplemented Opcode 2012h N/A N/A Special Software Trap Software Trap 2010h N/A N/A INT 15 NMI 2 NMI 203Eh N/A 15 INT 14 HSI FIFO Full HSI FIFO Full 203Ch 205Ch 14 INT 13 EXTINT 1 2 Port 2.2 203Ah 205Ah 13 INT 12 Timer 2 Overflow Timer 2 Overflow 2038h 2058h 12 INT 11 Timer 2 Capture 2 Timer 2 Capture 2036h 2056h 11 INT 10 HSI FIFO 4 HSI FIFO Fourth Entry 2034h INT 9 Receive RI Flag3 INT 8 Transmit TI Flag3 INT 7 EXTINT2 INT 6 Serial Port 10 2032h 2052h 9 2030h 2050h 8 Port 2.2 or Port 0.7 200Eh 204Eh 7 RI Flag and 200Ch 204Ch 6 Software Timer 0-3 Timer 2 Reset 200Ah 204Ah 5 HSI.0 Pin 2008h 2048h 4 Events on HSO.0 thru HSO.5 Lines 2006h 2046h 3 HSI FIFO Full or HSI Holding Reg. Loaded 2004h 2044h 2 EDAC Bit Error Single Bit Error Single Bit Error OVF Double Bit Error 2002h 2042h 1 Timer Overflow Timer 1 or Timer 2 2000h 2040h 0 INT 4 HSI.02 INT 3 High Speed Outputs INT 2 HSI Data Available INT 0 PM O EL Software Timer IN D EV INT 5 4 EN 2054h TI Flag INT 1 T Special All of the previous maskable interrupts can be assigned to the PTS. Any PTS interrupt has priority over all other maskable interrupts. 4 IN D EV EL O PM EN T Notes: 1. The Unimplemented Opcode and Software Trap interrupts are not prioritized. The Interrupt Controller immediately services these interrupts when they are asserted. NMI has the highest priority of all prioritized interrupts. Any PTS interrupt has priority over lower priority interru pts, and over all other maskable interrupts. The standard maskable interrupts are serviced according to their priority number with INT0 has the lowest priority o f all interrupts. 2. These interrupts can be configured to function as independent, external interrupts. 3. If the Serial interrupt is masked and the Receive and Transmit interrupts are enabled, the RI flag and TI flag generate separate Receive and Transmit interrupts. 4. If the Receive and Transmit interrupts are masked and the Serial interrupt is enabled, both RI flag and TI flag generate a Serial Port interrupt. 5 Table 7. SFR Memory Mapping HWin 0 Read HWin 0 Write HWin 1 HWin 151 Stack Pntr (hi) Stack Pntr (hi) Stack Pntr (hi) Stack Pntr (hi) 018H Stack Pntr (lo) Stack Pntr (lo) Stack Pntr (lo) Stack Pntr (lo) 017H IOS2 PWM0_CTRL PWM2_CTRL *** 016H IOS1 IOC1 PWM1_CTRL *** 015H IOS0 IOC0 EDAC-CS2 *** 014H WSR WSR WSR WSR 013H INT_MASK1 INT_MASK1 INT_MASK1 INT_MASK1 012H INT_PEND1 INT_PEND1 INT_PEND1 INT_PEND1 011H SP_STAT SP_CON RESERVED *** 010H PORT 2 PORT 2 RESERVED PSW2 00FH PORT 1 PORT 1 Timer 3(hi)2 RESERVED 00EH PORT 0 BAUD RATE Timer 3(lo)2 RESERVED 00DH Timer 2 (hi) Timer 2 (hi) WDT-SCALE2 T2CAPTURE (hi) 00CH Timer 2 (lo) Timer 2 (lo) IOC3 T2CAPTURE (lo) 00BH Timer 1 (hi) IOC2 INT_PRI(hi)2 *** 00AH Timer 1 (lo) Watchdog INT_PRI(lo)2 *** 009H INT_PEND INT_PEND INT_PEND INT_PEND 008H INT_MASK INT_MASK INT_MASK INT_MASK 007H SBUF (RX) SBUF (TX) PTSSRV (hi) *** 006H HSI_status HSO_command PTSSRV (lo) *** 005H HSI_time(hi) HSO_time (hi) PTSSEL (hi) *** 004H HSI_time (lo) HSO_time (lo) PTSSEL (lo) *** 003H RESERVED HSI_mode RESERVED *** 002H RESERVED RESERVED RESERVED RESERVED 001H Zero_reg (hi) Zero_reg (hi) Zero-reg (hi) Zero_reg (hi) 000H Zero_reg (lo) Zero_reg (lo) Zero_reg (lo) Zero_reg (lo) EN PM O EL EV IN T 019H D Address Notes: 1. For some functions that share a register address in HWindow0, the opposite access type (read/write) is available in HWindow 15 if indicated by the three asterisks (***). 2. These registers are not available in the industry standard 8XC196KDS. Therefore, industry standard development software will not recognize these mnemonics, and you will only be able to access them via their physical addresses. 6 Table 8: Special Function Register Reset Values Internal Register Hexadecimal Reset Value Binary Reset State XXXX XXXX XXXX XXXX XXXX I/O Status Register 2 (IOS2) 0000 0000 00 I/O Status Register 1 (IOS1) 0000 0000 00 I/O Status Register 0 (IOS0) 0000 0000 00 Window Select Register (WSR) 0000 0000 00 Interrupt Mask Register 1 (INT_MASK1) 0000 0000 00 Interrupt Pending Register 1 (INT_PEND1) 0000 0000 00 Serial Port Status Register (SP_STAT) 0000 1011 0B Port 2 Register (PORT2) 110X XXX1 XX Port 1 Register (PORT1) PM EN T Stack Pointer (SP) 1111 1111 FF XXXX XXXX XX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00 Interrupt Mask Register (INT_MASK) 0000 0000 00 Receive Serial Port Register (SBUF (RX)) 0000 0000 00 X0X0 X0X0 XX XXXX XXXX XXXX XXXX XXXX 0000 0000 0000 0000 0000 0000 0000 00 I/O Control Register 1 (IOC1) 0010 0001 21 I/O Control Register 0 (IOC0) 0000 00X0 0X Serial Port Control Register (SP_CON) 0000 1011 0B 0000 0000 0000 0001 0001 X00X X000 XX 0000 0000 00 Port 0 Register (PORT0) Timer 2 Value Register (TIMER2) Timer 1 Value Register (TIMER1) HSI Status Register (HSI_status) EV HSI Time Register (HSI_time) EL O Interrupt Pending Register (INT_PEND) Zero Register (ZERO_REG) IN D PWM0 Control Register (PWM0_CTRL) Baud Rate Register (BAUD_RATE) I/O Control Register 2 (IOC2) Watch Dog Timer Register (WATCHDOG) 7 Table 8: Special Function Register Reset Values Internal Register Hexadecimal Reset Value Binary Reset State Transmit Serial Port Buffer (SBUF (TX)) 0000 0000 00 HSO Command Register (HSO_command) 0000 0000 00 HSO Time Register (HSO_time) 0000 0000 0000 0000 0000 HSI Mode Register (HSI_mode) 1111 1111 FF PWM2 Control Register (PWM2_CTRL) 0000 0000 00 PWM1 Control Register (PWM1_CTRL) 0000 0000 00 EDAC Control and Status Register (EDAC_CS) 0000 0000 00 Timer 3 Value Register (TIMER3) 0000 0000 0000 0000 0000 0000 0000 00 EN T Watchdog Timer Prescaler (WDT_SCALE) I/O Control Register 3 (IOC3) 1111 0000 F0 0000 0000 00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Interrupt Priority Register (INT_PRI) PM PTS Service Register (PTSSRV) PTS Select Register (PTSSEL) O Timer 2 Capture Register (T2CAPTURE) IN D EV Chip Configuration Register (CCR) EL Program Counter (PC) 8 0010 0000 1000 0000 2080 XX10 1111 XF Table 9: External I/O Reset State External I/O I/O Function After Reset I/O State During Reset I/O State After Reset Address/Data Bus Pulled High Driven Output ALE ADV ALE Pulled High Driven Output RD RD Pulled High Driven Output WR WRL WR Pulled High Driven Output Port 0 (P0.0-P0.3; P0.6) ECB(4:0) [P0.0-P0.3; P0.6] and ECB(4:0) Undefined Inputs1 Undefined I/O1,2 Port 0 (P0.4 and P0.5) P0.4 and P0.5 Undefined Inputs1 Undefined Inputs1 Port 0 (P0.7) EXTINT P0.7 Undefined Input1 Undefined Input1 NMI NMI HSI.0 T2RST HSI.0 HSI.1 T2CLK HSI.1 HSI.2/HSO.4 Undefined HSI.3/HSO.5 PM EN T Address/Data Bus (AD15:0) Pulled Down Disabled Input1 Disabled Input1 Disabled Input1 Disabled Input1 Disabled I/O1 Disabled I/O1 Undefined Disabled I/O1 Disabled I/O1 HSO.0 through HSO.3 HSO.0-HSO.3 Pulled Down Driven Low Outputs Port 1 (P1.0-P1.7) PWM1; PWM2; BREQ; HLDA; HOLD P1.0-P1.7 Pulled Up Pulled Up TXD Pulled Up Driven High Output RXD Undefined Input1 Undefined Input1 Port 2 (P2.2) EXTINT P2.2 and EXTINT Undefined Input1 Undefined Input1 Port 2 (P2.3) T2CLK P2.3 and T2CLK Undefined Input1 Undefined Input1 Port 2 (P2.4) T2RST P2.4 Undefined Input1 Undefined Input1 IN Port 2 (P2.1) RXD EV D Port 2 (P2.0) TXD EL O Pulled Down 9 Table 9: External I/O Reset State External I/O I/O Function After Reset I/O State During Reset I/O State After Reset PWM0 Pulled Down Driven Low Output Port 2 (P2.6) T2UP-DN P2.6 Pulled Up Pulled Up Port 2 (P2.7) T2CAPTURE P2.7 and T2CAPTURE Pulled Up Pulled Up EDACEN EDACEN Undefined Input1 Undefined Input1 ECB5/ADV_RD_WR ECB5/ADV_RD_WR Undefined I/O1 Undefined I/O1,2 READY READY Undefined Input1 Undefined Input1 BUSWIDTH BUSWIDTH Undefined Input1 Undefined Input1 BHE WRH BHE Pulled Up Driven Output CLKOUT CLKOUT Driven Output Driven Output INST INST Pulled Down Driven Output RESET RESET Pulled Low by System Pulled Up PM EN T Port 2 (P2.5) PWM0 IN D EV EL O Notes: 1. These pins must not be left floating. Input voltages must not exceed V DD during power-up. 2. Do not directly tie these pins to VDD or GND; if EDACEN goes low, they may be driven by the UT80C196KDS and bus contention may occur. 10 Bus Control Bus Control UT80C196KDS UT80C196KDS AD8-AD15 8-Bit Latched Address High AD0-AD15 AD0-AD7 PM EN Figure 2. Bus Width Options IN D EV EL O 16-Bit Bus T 16-Bit Multiplexed Address/Data 11 8-Bit Multiplexed Address/Data 8-Bit Bus IN 12 Figure 3. 68-pin Quad Flatpack Package READY PM EN T TOP VIEW T2RST/P2.4 BHE/WRH WR/WR L 38 39 40 41 42 43 35 36 37 34 O 26 PWM0/P2.5 25 T2CAPTURE/P2.7 T2CLK/HSI.1 HSI.2/HS0.4 EDACEN 24 VSS T2RST/HSI.0 HS0.3 23 33 PWM2/P1.4 19 20 HS0.2 22 32 21 PWM1/P1.3 EL P1.2 31 18 HOLD/P1.7 TXD/P2.0 P1.0 P1.1 30 17 HLDA/P1.6 RXD/P2.1 29 16 BR EQ/P1.5 RESET EV 15 28 EXTINT/P2.2 HS0.1 14 11 12 UT80C196KDS ECB 5/ADV_RD_WR VSS XTAL1 VSS CLKOUT BUSWIDTH INST ALE/ADV 2 1 68 67 66 65 64 63 62 61 P0.1/ECB3 P0.3/ECB4 NMI 5 4 3 RD VDD P0.2/ECB1 P0.0/ECB2 P0.7/EXTINT P0.6/ECB0 8 7 6 9 V SS 27 13 HS0.0 VDD T2UP-DN/P2.6 D 10 HSI.3/HSO.5 P0.5 P0.4 V SS 60 59 55 58 AD0 AD1 AD2 57 AD3 56 AD4 AD5 54 53 52 51 50 49 AD6 AD7 AD8 AD9 AD10 AD11 48 47 AD12 46 AD14 45 AD15 44 P2.3/T2CLK AD13 Legend for I/O fields: TDI TO TI CI TUO TB TUQ = = = = TTL compatible output TTL compatible input CMOS only input TTL compatible output (internally pulled high) = TTL compatible output (internally pulled low) = TTL compatible input (internally pulled high) TDO TUI TUB TUBS PWR GND = TTL compatible input (internally pulled low) = TTL compatible bidirectional = TTL compatible quasi-bidirectional (internally pulled high) = TTL compatible bidirectional (internally pulled high) = TTL compatible bidirectional Schmitt Trigger (internally pulled high) = +5V (VDD ) = OV (VSS) Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active 1 PWR VDD --- Description Digital supply voltage (+5V). There are 2 VDD pins, both of which must be connected. TO ADV_RD_ WR --- Advanced Read and Write . This pin has multiplexed functionality: coincident with the Address/Data bus multiplexing. When address information is output on the AD pins, ADV_RD_WR is output. When data information is on the AD pins, ECB5 is an I/ O. ADV_RD_WR is output high for an external memory read cycle, and low for an external memory write cycle. TB ECB51 -- EDAC Check Bit 5. Asserting the EDACEN pin will cause the error detection and correction engine to pass the EDAC Check Bit 5 through pin 2 of the UT80C196KDS during the data phase of an external memory cycle. 3 TDI NMI High Non-Maskable Interrupt. A positive transition causes a vector through the NMI interrupt at location 203Eh. Assert NMI for at least 1 state time to guarantee acknowledgment by the interrupt controller. 4 TI P0.3 --- Port 0 Pin 3. An input only port pin that is read at location 0Eh in HWindow 0. TB ECB41 TB EL O EV D TI P0.1 IN 5 ECB31 PM EN T 2 --- EDAC Check Bit 4. Asserting the EDACEN pin will cause the error detection and correction engine to pass the EDAC Check Bit 4 through pin 4 of the UT80C196KDS. --- Port 0 Pin 1. An input only port pin that is read at location 0Eh in HWindow 0. --- EDAC Check Bit 3. Asserting the EDACEN pin will cause the error detection and correction engine to pass the EDAC Check Bit 3 through pin 5 of the UT80C196KDS. 13 Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active Description 6 TI P0.0 --- Port 0 Pin 0. An input only port pin that is read at location 0Eh in HWindow 0. TB ECB2 1 --- EDAC Check Bit 2. Asserting the EDACEN pin will cause the error detection and correction engine to pass the EDAC Check Bit 2 through pin 6 of the UT80C196KDS. TI P0.2 --- Port 0 Pin 2. An input only port pin that is read at location 0Eh in HWindow 0. TB ECB1 1 --- EDAC Check Bit 1. Asserting the EDACEN pin will cause the error detection and correction engine to pass the EDAC Check Bit 1 through pin 7 of the UT80C196KDS. TI P0.6 --- Port 0 Pin 6. An input only port pin that is read at location 0Eh in HWindow 0. TB ECB0 1 --- EDAC Check Bit 0. Asserting the EDACEN pin will cause the error detection and correction engine to pass the EDAC Check Bit 0 through pin 8 of the UT80C196KDS. TI P0.7 --- Port 0 Pin 7. An input only port pin that is read at location 0Eh in HWindow 0. TI EXTINT High External Interrupt. Setting IOC1.1 = 1 enables pin 9 as the source for the external interrupt EXTINT. A rising edge on this pin will generate EXTINT (INT07, 200Eh). Assert EXTINT for at least 2 state times to ensure acknowledgment by the interrupt controller. 7 PM O 9 EN T 8 TI P0.5 --- 11 TI P0.4 12 GND V SS IN 13 D 10 EV EL During Power Down mode, asserting EXTINT places the chip back into normal operation, even if EXTINT is masked. PWR V DD Port 0 Pin 5. An input only port pin that is read at location 0Eh in HWindow 0. --- Port 0 Pin 4. An input only port pin that is read at location 0Eh in HWindow 0. --- Digital circuit ground (0V). There are 4 V SS pins, all of which must be connected and one additional recommended VSS connection. --- Digital supply voltage (+5V). There are 2 V DD pins, both of which must be connected. 14 GND V SS --- Digital circuit ground (0V). There are 4 V SS pins, all of which must be connected and one additional recommended V SS connection. 14 Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active Description 15 TI P2.2 --- Port 2 Pin 2. An input only port pin that is written at location 10h of HWindow 0. P2.2 will always generate EXTINT1 (INT13, 203Ah) unless masked by the INT_MASK1 register. Assert EXTINT1 for at least 2 state times to guarantee acknowledgment by the interrupt controller. TI EXTINT High External Interrupt. Setting IOC1.1 = 0 enables pin 15 as the source for the external interrupt EXTINT. A rising edge on this pin will generate EXTINT (INT07, 200Eh). Assert EXTINT for at least 2 state times to ensure acknowledgment by the interrupt controller. During Power Down mode, asserting EXTINT places the chip back into normal operation, even if EXTINT is masked. TUBS RESET Low Master Reset. The first external reset signal supplied to the UT80C196KDS must be active for at least 16 state times. All subsequent RESET assertions need only be active for 1 state time because the UT80C196KDS will continue driving the RESET signal for an additional 16 state times. See section 1.1.2 for more information on the RESET function of the UT80C196KDS. 17 TI P2.1 --- Port 2 Pin 1. An input only port pin that is read at location 10h of HWindow 0. PM EN T 16 TUO EV TUO --- P2.0 TXD --- RXD is a bidirectional serial data port. When operating in Serial Modes 1, 2, and 3, RXD receives serial data. When using Serial Mode 0, RXD operates as an input and an open-drain output for data. Setting SPCON.3 = 1 enables the RXD function of pin 17. Port 2 Pin 0. An output only port pin that is written at location 10h of HWindow 0. Setting IOC1.5 = 0 enables the P2.0 function of pin 18. --- IN 18 2 RXD D TB EL O Setting SPCON.3 = 0 enables the P2.1 function of pin 17. Transmit Serial Data (TXD). When set to Serial Mode 1, 2, or 3, TXD transmits serial port data. When using Serial Mode 0, TXD is used as the Serial Clock output. Setting IOC1.5 = 1 enables the TXD function of pin 18. TUI ICT Low In-Circuit Test. The UT80C196KDS will enter the In-Circuit Test mode if this pin is held low during the rising edge of RESET. 15 Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active Description 19 TUQ P1.0 --- Port 1 Pin 0. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. 20 TUQ P1.1 --- Port 1 Pin 1. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. 21 TUQ P1.2 --- Port 1 Pin 2. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. 22 TUQ P1.3 --- Port 1 Pin 3. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. Setting IOC3.2 = 0 enables the P1.3 function of pin 22. PWM1 --- Pulse Width Modulator (PWM) Output 1. The output signal will be a waveform whose duty cycle is programmed by the PWM1_CONTROL register, and the frequency is selected by IOC2.2. T TUO TUQ P1.4 --- Port 1 Pin 4. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. PM 23 EN Setting IOC3.2 = 1 enables the PWM1 function of pin 22. Setting IOC3.3 = 0 enables the P1.4 function of pin 23. PWM2 --- Pulse Width Modulator (PWM) Output 2. The output signal will be a waveform whose duty cycle is programmed by the PWM2_CONTROL register, and the frequency is selected by IOC2.2. EL O TUO Setting IOC3.3 = 1 enables the PWM2 function of pin 23. HSI.0 --- High Speed Input Module, input pin 0. Unless masked, a rising edge on this input will generate the HSI.0 Pin interrupt (INT04, 2008h). Assert the HSI.0 pin for at least 2 state times to ensure acknowledgment by the interrupt controller. D EV TI TI T2RST IN 24 Setting IOC0.0 = 1 enables pin 24 as an HSI input, and allows events on this pin to be loaded into the HSI FIFO. High Timer 2 Reset. A rising edge on the T2RST pin resets Timer 2. To enable the T2RST function of pin 24, set IOC0.3 = 1 and IOC0.5 = 1. 16 Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active 25 TI HSI.1 --- Description High Speed Input Module, input pin 1. Setting IOC0.2 = 1 enables pin 25 as an HSI input, and allows events on this pin to be loaded into the HSI FIFO. TI T2CLK --- Timer 2 Clock. Setting IOC0.7 = 1 and IOC3.0 = 0 enables pin 25 to function as the Timer 2 clock source. 26 TO HSO.4 --- High Speed Output Module, output pin 4. This pin can simultaneously operate in the HSI and HSO modes of operation. As a result, this pin acts as an output that the HSI monitors. Setting IOC1.4 = 1 enables the HSO.4 function of pin 26. HSI.2 --- High Speed Input Module, input pin 2. This pin can simultaneously operate in the HSI and HSO modes of operation. As a result, this pin can monitor events on the HSO. PM EN T TI Setting IOC0.4 = 1 enables pin 26 as an HSI input pin, and allows events on this pin to be loaded into the HSI FIFO. 27 TO HSO.5 --- High Speed Output Module, output pin 5. This pin can simultaneously operate in the HSI and HSO modes of operation. As a result, this pin acts as an output that the HSI monitors. 29 TDO EV TDO --- HSO.0 HSO.1 High Speed Input Module, input pin 3. This pin can simultaneously operate in the HSI and HSO modes of operation. As a result, this pin can monitor events on the HSO. Setting IOC0.6 = 1 enables pin 27 as an HSI input pin, and allows events on this pin to be loaded into the HSI FIFO. --- High Speed Output Module, output pin 0. The HSO.0 pin is a dedicated output for the HSO module. --- High Speed Output Module, output pin 1. The HSO.1 pin is a dedicated output for the HSO module. IN 28 HSI.3 D TI EL O Setting IOC1.6 = 1 enables the HSO.5 function of pin 27. 17 Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active Description 30 TUQ P1.5 --- Port 1 Pin 5. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. Setting WSR.7 = 0 enables the P1.5 function of pin 30. TUO BREQ Low Bus Request. The BREQ output signal asserts during a HOLD cycle when the internal bus controller has a pending external memory cycle. During a HOLD cycle, BREQ will not be asserted until the HLDA signal is asserted. Once asserted, BREQ does not deassert until the HOLD signal is released. Setting WSR.7 = 1 enables the BREQ function of pin 30. TUQ P1.6 --- Port 1 Pin 6. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. T 312 HLDA Low Bus Hold Acknowledge. The UT80C198KD asserts the HLDA signal as a result of another device activating the HOLD signal. By asserting this signal, the UT80C196KDS is indicating that it has released the bus. PM TUO EN Setting WSR.7 = 0 enables the P1.6 function of pin 31. Setting WSR.7 = 1 enables the HLDA function of pin 31. TUQ P1.7 --- Port 1 Pin 7. A quasi-bidirectional port pin that is read and written at location 0Fh of HWindow 0. O 32 HOLD Low P2.6 EV TUI EL Setting WSR.7 = 0 enables the P1.7 function of pin 32. Bus Hold. The HOLD signal is used to request control of the bus by another DMA device. Setting WSR.7 = 1 enables the HOLD function of pin 32. --- D TUQ TUI IN 33 T2UP-DN Port 2 Pin 6. A quasi-bidirectional port pin that is read and written at location 10h of HWindow 0. Setting IOC2.1 = 0 enables the P2.6 function of pin 33. --- Timer 2 Up or Down. The T2UP-DN pin will dynamically change the direction that Timer 2 counts. T2UP-DN = 1 then Timer 2 counts down. T2UP-DN = 0 then Timer 2 counts up. Setting IOC2.1 = 1 enables the T2UP-DN function of pin 33. When IOC2.1 = 0, Timer 2 will only count up. 18 Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active Description 34 TDO HSO.2 --- High Speed Output Module, output pin 2. The HSO.2 pin is a dedicated output for the HSO module. 35 TDO HSO.3 --- High Speed Output Module, output pin 3. The HSO.3 pin is a dedicated output for the HSO module. 36 GND V SS --- Digital circuit ground (0V). There are 4 VSS pins, all of which must be connected and one additional recommended VSS connection. TI EDACEN Low 38 TUQ P2.7 --- Port 2 Pin 7. A quasi-bidirectional port pin that is read and written at location 10h of HWindow 0. TUQ T2CAPTURE High Timer 2 Capture. A rising edge on this pin loads the value of Timer 2 into the T2CAPTURE register, and generates a Timer 2 Capture interrupt (INT11, 2036h). Assert the T2CAPTURE signal for at least 2 state times to guarantee acknowledgment by the interrupt controller. Using INT_Mask1.3 controls whether or not a rising edge causes an interrupt. TDO P2.5 --- PM EN Port 2 Pin 5. An output only port pin that is written at location 10h of HWindow 0. EL O 39 EDAC Enable. Asserting the EDACEN signal activates the error detection and correction engine. This causes the UT80C196KDS to include ECB(5:0) as the EDAC check bit pins in all external memory cycles. T 37 Setting IOC1.0 = 0 enables the P2.5 function of pin 39. --- WR Low D TUO IN 40 2 PWM0 EV TDO TUO WRL Pulse Width Modulator (PWM) Output 0. The output signal will be a waveform whose duty cycle is programmed by the PWM0_CONTROL register, and the frequency is selected by IOC2.2. Setting IOC1.0 = 1 enables the PWM0 function of pin 39. Write. The WR signal indicates that an external write is occurring. Activation of this signal only occurs during external memory writes. Setting CCR.2 = 1 enables the WR function of pin 40. Low Write Low. The WRL signal is activated when writing the low byte of a 16-bit wide word, and is always asserted for 8-bit wide memory writes. Setting CCR.2 = 0 enables the WRL function of pin 40. 19 Table 10: 68-lead Flat Pack Pin Descriptions QFP Pin# I/O Name Active Description 41 TUO BHE Low Byte High Enable. The assertion of the BHE signal will occur for all 16-bit word writes, and high byte writes in both 8- and 16bit wide bus cycles. Setting CCR.2 = 1 enables the BHE function of pin 41. TUO WRH Low Write High. The WRH signal is asserted for high byte writes, and word writes for 16-bit wide bus cycles. Additionally, WRH is asserted for all write operations when using an 8-bit wide bus cycle. Setting CCR.2 = 0 enables the WRH function of pin 41. TI P2.4 --- Port 2 Pin 4. An input only port pin that is read at location 10h of HWindow 0. TI T2RST High Timer 2 Reset. Asserting the T2RST signal will reset Timer 2. T 42 TI READY High READY input. The READY signal is used to lengthen memory cycles by inserting "wait states" for interfacing to slow peripherals. When the READY signal is high, no "wait states" are generated, and the CPU operation continues in a normal fashion. If READY is low during the falling edge of CLKOUT, the memory controller inserts "wait states" into the memory cycle. "Wait state" generation will continue until a falling edge of CLKOUT detects READY as logically high, or until the number of "wait states" is equal to the number programmed into CCR.4 and CCR.5. EL O PM 43 EN To enable the T2RST function of pin 42, set IOC0.3 = 1 and IOC0.5 = 0. P2.3 TI T2CLK D TI --- Port 2 Pin 3. An input only port pin that is read at location 10h of HWindow 0. --- Timer 2 Clock input. Setting IOC0.7 = 0 and IOC3.0 = 0 enables this pin as the external clock source for Timer 2. IN 44 EV Note: The READY signal is only used for external memory accesses, and is functional during the CCR fetch. 45 TUB AD15 IOC0.7: X 0 1 --- IOC3.0: 1 0 0 Timer 2 Clock Source: Internal Clock Source P2.3 External Clock Source HSI.1 External Clock Source Bit 15 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 20 I/O Name Active Description 46 TUB AD14 --- Bit 14 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 47 TUB AD13 --- Bit 13 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 48 TUB AD12 --- Bit 12 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 49 TUB AD11 --- Bit 11 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 50 TUB AD10 --- Bit 10 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 51 TUB AD9 --- Bit 9 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 52 TUB AD8 --- Bit 8 of the Address/Data bus. This pin is a dedicated address pin when operating with 8-bit wide bus cycles. For 16-bit wide bus cycles, this pin is used as multiplexed address and data. 53 TUB AD7 --- Bit 7 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 54 TUB AD6 --- Bit 6 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 55 TUB AD5 --- Bit 5 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 56 TUB AD4 --- Bit 4 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 57 TUB --- Bit 3 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 58 TUB AD2 --- Bit 2 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 59 TUB AD1 --- Bit 1 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 60 TUB AD0 --- Bit 0 of the Address/Data bus. This pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. EL O EV D AD3 PM EN T QFP Pin# IN Table 10: 68-lead Flat Pack Pin Descriptions 21 Table 10: 68-lead Flat Pack Pin Descriptions I/O Name Active 61 2 TUO RD Low Read. The RD signal is an output to external memory that is only asserted during external memory reads. 62 2 TUO ALE High Address Latch Enable. The ALE signal is an output to external memory that is only asserted during external memory accesses. ALE is used to specify that valid address information is available on the address/data bus, and signals the start of a bus cycle. ALE is used by an external latch to demultiplex the address from the address/data bus. Setting CCR.3 = 1 enables the ALE function of pin 62. TUO ADV Low Address Valid. The ADV signal is an output to external memory that is only asserted during external memory accesses. ADV is driven high to specify that valid address information is available on the address/data bus. The ADV signal is held low during the data transfer portion of the bus cycle, and is driven high when the bus cycle completes. ADV is used by an external latch to demultiplex the address from the address/data bus. Setting CCR.3 = 0 enables the ADV function of pin 62. TDO INST High Instruction Fetch. The INST signal indicates the type of external memory cycle being performed. The INST signal will be high during instruction fetches, and will be low for data fetches. EN 63 Description T QFP Pin# TI BUSWIDTH --- Bus Width. The BUSWIDTH pin dynamically modifies the width of bus cycles. When a high logic value is supplied, the bus width will be set to 16-bits wide. When a low logic level is supplied, the bus width will be set to 8-bits wide. O 64 PM Note: CCB bytes and Interrupt vectors are considered data. TUO CLKOUT 66 GND VSS 3 --- Clock Output. The CLKOUT signal is the output of the internal clock. This signal has a 50% duty cycle, and runs at 1/2 the frequency of the system clock input to XTAL1. Setting IOC3.1 = 0 will enable the CLKOUT output signal. IN D EV 65 EL Setting CCR.1 = 1 enables the BUSWIDTH pin. Setting CCR.1 = 0 disables the BUSWIDTH pin. As a result, the UT80C196KDS will only perform 8-bit wide bus cycles. --- Digital circuit ground (0V). Recommended connection for signal integrity improvement. There are 4 other VSS pins, all of which must be connected. 67 CI XTAL1 --- External oscillator or clock input to the UT80C196KDS. The XTAL1 input is fed to the on-chip clock generator. 68 GND V SS --- Digital circuit ground (0V). There are 4 VSS pins, all of which must be connected and one additional recomended V SS connection. Notes: 1. These pins should be pulled high or low when using EDAC (i.e. EDACEN = 0) to prevent the voltages on these pins from floating to the switching threshold of the input buffers during long read cycles. 2. These pins must be high on the rising edge of RESET in order to avoid entering any test modes. 3. This pin is a recommended V SS connection. The remaining 4 VSS pins are required to be tied to the circuit card ground plane. 22 2.0 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to V SS ) SYMBOL PARAMETER LIMITS UNITS VDD DC Supply Voltage -0.3 to 6.0 V VI/O 2 Voltage on Any Pin -0.3 to VDD+0.3V V TSTG Storage Temperature -65 to +150 C 175 C 2 C/W 10 mA TJ Maximum Junction Temperature JC II 2 Thermal Resistance, Junction-to-Case 3 DC Input Current IN D EV EL O PM EN T Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. These ratings are provided as design guidelines. They are not guaranteed by test or characterization. 3. Test per MIL-STD-883, Method 1012. 23 3.0 DC ELECTRICAL CHARACTERISTICS (VDD = 5.0V 10%) (TC = -55C to +125C for "C" screening and -40C to +125C for "W" screening) V TVH V OL V OH I OH1 I IH ILI I LI1 I LI2 CIO I OL = 100A6 (TTL load) I OL = 4.0mA High-level Output Voltage8 (CMOS load) (Standard outputs) (TTL load) I OH = -100A 6 High-level Output Current1 V OH = V SS (see Note 6) (Open drain outputs with pullups) V IN = V IH V IN = V SS or VDD I/O Leakage Current, with pullups 3 V IN = V SS I/O Leakage Current, with V IN = V DD pulldowns 4 @ 1MHZ, 25C Pin Capacitance6 Quiescent Power Supply Current I DDPD Power Supply Current in Power Down Power Supply Current in Idle Mode No Active I/O, Clk@20MHZ IOS I OS1 IN D QIDD Power Supply Current in Reset V .7VDD V .3VDD V .5VDD .7V DD V .3VDD .4V DD V V 0.25 V 0.4 V V V 2.4 I OH = -4.0mA Active Power Supply Current IDDRESET V VDD -.25 IDD IDDIDLE 0.8 .6 Typical Range of Hysteresis6 RESET Low-level Output Voltage (CMOS load) Logical 1 Input Current 2 (Test mode entry avoidance) I/O Leakage Current, standard inputs/outputs in Z state UNIT 2.2 T VT + MAXIMUM EN V IL1 Low-level Input Voltage (except XTAL1, RESET) High-level Input Voltage (except XTAL1, RESET) High-level Input Voltage (XTAL1) Low-level Input Voltage (XTAL1) Positive Going Threshold RESET Negative Going Threshold RESET PM V IH1 MINIMUM O VIH CONDITION EL V IL PARAMETER EV SYMBOL -225 -20 A -225 -20 A -10 +10 A -225 -20 A 20 225 A 15 pF 110 mA 20 1000 1000 6 A mA 55 mA 65 mA -100 100 mA -200 200 mA Clk@20MHz, typical program flow Unloaded TMIN t +25C Outputs, +125C No Clock +25C post-rad No Active I/O, Clk@20MHz CLK @20 MHz, RESET < V IL Short Circuit output current (except V DD = 5.5V for pins listed in Note 5)6,7 V DD = 5.5V Short Circuit output current5,6,7 24 IN D EV EL O PM EN T Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883. 1. Open-drain outputs with pullups include Port 1, P2.6 and P2.7. 2. Test modes are entered at the RESET rising edge by applying VIL to one or more of the following pins: TXD, RD, WR , HLDA. To avoid entering a test mode, ensure that these pins remain above V IH at the rising edge of RESET. 3. Inputs/outputs with pullup resistors include: RESET, Port 1, P2.0, P2.6, P2.7, W R, BHE, AD0-15, RD, ALE, CLKOUT. 4. Inputs/outputs will pulldown resistors include: NMI, HS0.0-HS0.3, P2.5, INST. 5. The IOS1 spec applies to pins RESET, BHE, RD, C LKOUT. 6. Tested only at initial qualification and after any design or process changes which may affect this characteristic. 7. Not more than one output may be shorted at a time for maximum duration of one second. 8. For standard outputs not covered by IOH1 spec. 25 4.0 AC CHARACTERISTICS READ CYCLE (V DD = 5.0V 10%) (TC = -55C to +125C for "C" screening and -40C to +125C for "W" screening) SYMBOL PARAMETER MINIMUM tAVYV 5 Address VALID to READY setup tYLYH 5 Non-READY time tCLYX 1,5 READY hold after CLKOUT low tLLYX1,5 READY hold after ALE low tAVGV 5 Address valid to BUSWIDTH setup tCLGX 5 BUSWIDTH hold after CLKOUT low tAVDV 2,5 MAXIMUM UNIT 2TOSC - 30 ns No upper limit ns 0 2TOSC - 20 ns TOSC 3TOSC - 20 ns 2TOSC - 30 ns 0 ns Address valid to input data valid 3TOSC - 29 ns 5 (see Note 5) TOSC - 26 ns RD Active to input data valid tCLDV 5 CLKOUT low to input data valid 5 TOSC - 26 ns tRHDZ 5 End of RD to input data float 0 TOSC -10 ns tRXDX5 Data hold after RD inactive 0 TOSC -10 ns EN T tRLDV 2 Frequency on XTAL1 1 (see Note 7) 20 (see Note 6) Mhz T OSC5 XTAL1 period (1/f OSC ) 50 (see Note 6) 1000 (see Note 7) ns tXHCH XTAL1 high to CLKOUT high or low +25 ns tCLCL6 CLKOUT cycle time tCHCL5 CLKOUT high period tCLLH tLLCH 5 O PM f OSC5 0 2T OSC Typical ns TOSC +10 ns CLKOUT falling edge to ALE rising -5 +15 ns ALE falling edge to CLKOUT rising -10 +10 ns EL TOSC - 10 ALE cycle time tLHLL5 ALE high period TOSC - 10 tAVLL5 Address setup to ALE falling edge TOSC - 15 tLLAX Address hold after ALE falling edge TOSC - 20 TOSC +5 ns T OSC - 5 TOSC +10 ns -5 +10 ns tRLCL tRLRH2 tRHLH 3,5 tRLAZ 5 D IN tLLRL 4T OSC Typical EV tLHLH 2, 6 ALE falling edge to RD falling edge RD low to CLKOUT falling edge ns TOSC +15 ns ns RD low period T OSC - 5 RD rising edge to ALE rising edge T OSC-10 TOSC +10 ns -5 +5 ns RD low to address float 26 ns tLLWL 5 ALE falling edge to WR falling edge tCLWL CLKOUT low to WR falling edge tQVWH 2 Data stable to WR rising edge tCHWH5 CLKOUT high to WR rising edge T OSC - 10 TOSC +10 ns -5 +10 ns T OSC - 10 TOSC +10 ns -10 +15 ns WR low period T OSC - 10 Data hold after WR rising edge T OSC - 10 TOSC +10 ns WR rising edge to ALE rising edge T OSC - 10 TOSC +10 ns BHE, INST after WR rising edge T OSC - 10 TOSC +10 ns tWHAX 4,5 AD8-15 HOLD after WR rising T OSC - 25 tRHBX 5 BHE, INST after RD rising edge T OSC - 10 tRHAX 4,5 AD8-15 HOLD after RD rising T OSC - 25 tAVENV 5 Address valid to EDACEN valid tLHENX 5 EDACEN hold after ALE high tAVEV 2,5 Address valid to EDAC input valid tWHLH 3,5 tWHBX5 tRXEX5 EDAC hold after RD inactive EDAC output stable to WR rising tWHEX 5 EDAC output hold after WR rising ns TOSC +10 0 EV D IN ns ns 3TOSC -29 ns 0 TOSC -10 ns TOSC -10 TOSC +10 ns TOSC -10 TOSC +10 ns Note: * Post-radiation performance guaranteed at 25 C per MIL-STD-883 Method 1019 at 1.0E5 rads(Si). 1. If max exceeded, additional wait state occurs. 2. If wait states are used, add 2 T OSC *N, where N = number of wait states. 3. Assuming back-to-back bus cycles. 4. 8-bit only 5. Tested only at initial qualification, and after any design or process changes which may affect this characteristic. 6. These specs are verified using functional vectors (strobed) only. 7. Low speed tests performed at 5MHz. 1MHz operation is guaranteed by design. 27 ns ns 2TOSC -30 EL O tEVWH 2,5 ns T tWHQX 5 PM EN tWLWH 2,5 TOSC XTAL1 tXHCH t CHCL t CLCL CLKOUT tCLLH t LLCH t RLCL t LHLH ALE tLHLL tLLRL tRHLH t RLRH READ tRHDZ tCLDV tAVLL tLLAX tRLDV t RXDX tRLAZ ADDRESS OUT DATA tAVDV tLLWL tWLWH WRITE tCLWL t WHQX t QVWH ADDRESS OUT DATA OUT PM BUS T t CHWH t WHLH EN BUS ADDRESS tWHBX, t RHBX VALID BHE, INST O tWHAX, t RHAX AD8-15 tAVEV ECB(4:0) READ CYCLE EV tWHEX VALID t EVWH D t AVEV t AVLL IN t AVLL ECB5/ADV_RD_WR WRITE CYCLE t RXEX VALID ECB(4:0) WRITE CYCLE ECB5/ADV_RD_WR READ CYCLE EL ADDRESS OUT t RXEX tLLAX ECB5 VALID t LLAX tWHEX t EVWH ECB5 VALID Figure 4. System Bus Timings 28 TOSC XTAL1 tXHCH tCLCL tCHCL CLKOUT tCLYX max tCLLH tLLYX max tYLYH ALE tLHLH + 2T OSC tLLYX min READY tAVYV tCLYX tRLRH + 2T OSC READ ADDRESS OUT BUS tRLDV+ 2T OSC PM EN tAVDV+ 2T OSC T min DATA tWLWH +2T OSC WRITE ADDRESS EL O BUS DATA OUT tQVWH + 2T OSC IN D EV Figure 5. READY Timing (One Wait State) 29 ADDRESS XTAL1 CLKOUT ALE tCLGX BUSWIDTH VALID tAVGV BUS ADDRESS OUT DATA tLHENX EDACEN EN VALID T tAVENV IN D EV EL O PM Figure 6. BUSWIDTH and EDACEN Timings 30 5.0 XTAL1 CLOCK DRIVE TIMING CHARACTERISTICS SYMBOL PARAMETER MINIMUM MAXIMUM UNIT 1(note 1) 20 MHz 50 1000(note 1) ns f OSC Oscillator Frequency T OSC Oscillator Period tOSCH High Time 17 (note 1) ns tOSCL Low Time 17 (note 1) ns tOSCR Rise Time 10 (note 2) ns tOSCF Fall Time 10 (note 2 ) ns Note: 1. Tested only at initial qualification, and after any design or process changes which may affect this characteristic. 2. Supplied as a design limit, but not guaranteed or tested. tOSCH t OSCR 0.3V DD 0.7 VDD 0.3V DD PM EN 0.7 V D D T t OSCL 0.7 VDD t OSCF T OSC IN D EV EL O Figure 7. External Clock Drive Timing Waveforms 31 Table 11. DC Specifications in Hold 1 DESCRIPTION MIN MAX CONDITIONS Pullups on ADV, RD, WR, WRL, BHE, ALE 24.4K 275K VDD =5.5V, V IN = VSS Pulldown on INST 24.4K 275K V DD =5.5V, VIN = VDD Note: 1.Tested only at initial qualification, and after any design or process changes which may affect this characteristic. 6.0 HOLD/HLDA Timings SYMBOL PARAMETER MINIMUM MAXIMUM UNIT HOLD Setup 25 tCLHAL1 CLKOUT low to HLDA low -15 15 ns tCLBRL1 CLKOUT low to BREQ low -15 15 ns tHALAZ1 HLDA low to address float 10 ns tHALBZ1 HLDA low to BHE, INST, RD, WR driven weakly 15 ns tCLHAH 1 CLKOUT low to HLDA high -15 15 ns tCLBRH1 CLKOUT low to BREQ high -15 15 ns tHAHAX 1 HLDA high to address no longer float tHAHBV 1 EN PM O ns HLDA high to BHE, INST, RD, WR valid -10 ns CLKOUT low to ALE high -5 EL -15 EV tCLLH 1 ns T tHVCH1 IN D Note: 1.Tested only at initial qualification, and after any design or process changes which may affect this characteristic. 32 15 ns CLKOUT tHVCH tHVCH HOLD tCLHAH tCLHAL HLDA T tCLBRH BREQ tHALAZ EL O BUS PM EN tCLBRL tHALBZ BHE, INST RD, WR tCLLH D EV Weakly Driven Inactive IN ALE/ADV tHAHBV Weakly Driven High Figure 8. DC Specifications In Hold 33 tHAHAX External Clock Input XTAL1 UT80C196KDS V DD TEST POINTS 1.4V 1.4V PM 0.0V EN T Figure 9. External Clock Connections O AC Testing inputs are driven at VDD for a Logic "1" and 0.0V for a Logic "0". Timing measurements are made at 1.4V. IN V LOAD D V OH - 0.5V EV EL Figure 10. AC Testing Input, Output Waveforms V OH - 0.5V TIMING REFERENCE POINTS V OL + 0.5V V OL + 0.5V For timing purposes a port pin is no longer floating when it changes to a voltage outside the reference points shown and begins to float when it changes to a voltage inside the reference points shown. I OL = 4mA, IOH = -4mA. Figure 11. Float Waveforms 34 Table 12. Serial Port Timing SYMBOL PARAMETER MINIMUM MAXIMUM 6 TOSC typical UNIT tXLXL2 Serial port clock period (BRR > 8002H) tXLXH 1 Serial port clock falling edge to rising edge (BRR > 8002H) tXLXL2 Serial port clock period (BRR = 8001H) tXLXH 1 Serial port clock falling edge to rising edge (BRR = 8001H) 2 T OSC -50 tQVXH1 Output data valid to clock rising edge 2 T OSC -50 ns tXHQX1 Output data hold after clock rising edge 2 T OSC -50 ns tXHQV1 Next output data valid after clock rising edge tDVXH1 Input data setup to clock rising edge tXHDX1 Input data hold after clock rising edge tXHQZ 1 Last clock rising to output float 4 T OSC -50 ns 4 T OSC +50 ns 4 TOSC typical ns 2 T OSC +50 ns 2 T OSC +50 ns ns 0 ns 2 T OSC +10 ns PM EN 2 T OSC -10 T T OSC +50 Note: 1.Tested only at initial qualification, and after any design or process changes which may affect this characteristic. 2. These specs are verified using functional vectors (strobed) only. TXD RXD (OUT) 0 tXLXH 1 tXHQX tXHQV 2 EV tQVXH EL O TXLXL 3 tXHQZ 4 5 6 7 0 IN RXD (IN) D tDVXH 1 2 3 tXHDX 4 5 Figure 12. Serial Port Waveform - Shift Register Mode 35 6 7 APPENDIX A Difference Between Industry Standard and UT80C196KDS reading bits 3 through 0 of the EDAC_CS Register tells you how many single bit errors have been corrected. The EDAC_CS Register is located at location 15h of HWindow 1. 1.3 Clocking The XTAL2 output is not used and the UT80C196KDS expects the input on the XTAL 1 to be a valid digital clock signal. The clock should be stable before reset is removed or Power Down mode is exited. In Power Down mode, a small number of gates will be clocked by the XTAL1 input. The UT80C196KDS XTAL2 has been replaced with a VSS pin. 1.4 CCB Read after Reset The CCB fetch after Reset will be a normal fetch as if the chosen bus width is selectable based on the BUSWIDTH input. Systems with an 8-bit wide interface should tie BUSWIDTH to ground. Systems that use BUSWIDTH should perform a normal decode based on the memory configuration of the system. The Industry Standard 80C196KD treats the CCB fetch as an 8-bit fetch (driving the upper 8-bits with address 20H) regardless of the state of BUSWIDTH. 1.5 Internal Program Memory EL 1.6 Ports 3 and 4 D EV Since the UT80C196KDS will not have internal program memory, Ports 3 and 4 will always be used as the multiplexed Address and Data bus. Therefore, these ports will not be configured as I/O ports, and the bidirectional port function of these pins will not be implemented. The pins will only be configured as Address and bidirectional data pins. 1.7 Built in EDAC The instruction queue is eight bytes deep instead of four. The instruction queue also interfaces to the CPU through a 16-bit bus. This configuration will speed up the operation of the UT80C196KDS. 1.9 WDT and Prescalar The WDT can now be disabled through the software. The disable feature should allow the user flexibility in using the Watch Dog Timer. The WDT also now has a prescalar which can slow down the counter by a factor of 20 to 27. The prescalar will give the user extra time between clears of the WDT. The WDT prescaler (WDT_SCALE) is located at location 0Dh of HWindow 1. 1.10 Interrupt Priority Levels An additional level of priority encoding is available to the user. Every standard interrupt can be programed to a higher level of priority. All interrupts in the higher priority will maintain their relative priority, but low priority interrupts can then be programmed for a higher interrupt priority if necessary. The interrupt priority register is 16-bits wide, and maps to the standard interrupts in the same fashion as the INT_MASK and INT_MASK1 registers. The high byte of the Interrupt Priority Register (IN_PRI(hi)) is located at 0Bh of HWindow 1, and the low byte (INT_PRI(lo)) is located at 0Ah of HWindow 1. O The UT80C196KDS does not have internal program memory, and pin 2 (EA) will be ignored for choosing between internal and external program reads. The user may tie this pin to ground for compatibility reasons, unless EDAC is enabled. 1.8 Instruction Queue T The Analog to Digital Converter will not be implemented in the UT80C196KDS. EN 1.1 Analog to Digital Converter PM 1.0 DIFFERENCES TO INDUSTRY STANDARD 80C196KD IN The UT80C196KDS incorporates a built in Error Detection and Correction circuit for external memory reads and writes. The EDAC can be controlled from an external pin. The external pin (Pin 37) can be used to enable or disable this feature interactively. Therefore, different regions of external memory can be assigned to have EDAC as necessary. Additionally, the EDAC check bits will be passed through Port 0, which varies from the industry standard version where Port 0 is an input only port. You can control the interrupt behavior of the EDAC engine by setting bits 6 and 5 of the EDAC Control and Status Register (EDAC_CS). Additionally, reading bit 4 of the EDAC_CS allows you to determine if a double bit error occurred, and 1.11 Faster Multiply and Divide The multiplier and divider have been optimized to perform their operations in fewer state times than in the current version. 1.12 Instructions State Time Reduction The CPU has been streamlined for faster execution where possible. Examples include 1 state reduction for WORD immediate instructions, 1 state reductions for long indexed instructions, and state reductions for the BMOV instructions. 1.13 STACK_PNTR implemented as Special Function Register The STACK_PNTR has been implemented as a true Special Function Register instead of in the RAM to allow for quicker pushes and pops. If the stack is not used, the SFR can be used for general purpose data storage. 1.14 Timer3 An additional 16-bit timer/counter has been implemented as a general purpose timer that can be used if Timer1 and Timer 2 are being dedicated to other functional uses. The current value 36 of Timer3 can be found in locations 0Fh (high byte), and 0Eh (low byte) of HWindow 1. PROCESSING FLOW FOR THE ST R0, [R0]+ INSTRUCTION UT80C196KDS Industry Standard Address = [R0]; 1000h Address = [R0]; 1000h R0 ---> Address R0 = R0+1; 1001h R0 = R0+1; 1001h R0 ---> Address * The contents in address * The contents in address 1000h are 1000h 1000h are 1001h 1.15 Input/Output Pullup/Pulldown Currents Leakage currents may not meet the industry standard specs due to differently sized weak pullups/pulldowns, during QuasiBidirectional and reset/powerdown modes. Refer to specs for I LI1 and ILI2 . 1.16 Power-down exit Pin 37 will not be used to exit power-down mode. Since a digital clock is supplied, no connection between this V pp pin and the power-down circuitry exists. 1.23 AC Timing Differences There are some AC timing differences between the UT80C196KDS and the industry standard 80C196KD. Most changes resulted in loosened timing specifications. However, the tRHDZ and tRXDX timing specifications were tightened by 5ns. If you have been designing to the industry standard timing specifications, it is important to recognize these two shortened timing specifications. 1.17 Test Mode Entry Test mode entry will be via four pins: WR, RD, ALE and HLDA instead of PWM0. 1.19 Pullup/Pulldown states The INST pin will be driven to a weak low during Reset. The ALE signal will be driven to a weak high during Bus Hold. 1.20 Modifying the INT_PEND registers 1.21 Serial Port Synchronous Mode 1.24 T2UP-DN Input Signal Port 2.6 has an alternate function of T2UP-DN enabled by IOC2.1. The industry standard device appears to allow writes into Port 2.6 to directly affect the pin state when in the T2UPDN mode. (This would allow software control of the T2 direction, but requires ensuring a one (QBD pullup) is written to Port 2.6 if the pin is driven externally). The UT80C196KDS device is designed to disable the Port 2.6 output when T2UPDN is enabled. This protects the P2.6/T2UP-DN pin from contention with an externally driven signal, independent of the value written into Port 2. EL O Two operand rd-modify-wr instructions should be used to modify the INT_PEND registers. Three operand rd-modify-wr instructions may lose an incoming interrupt. NOTE: Please visit the UTMC website at www.utmc.com to obtain the latest data sheet updates, application notes, software examples, advisories and erratas for the UT80C196KDS. PM EN The UT80C196KDS will not guarantee the 16-state "pulse stretching" function of a Reset_n pulse applied at power-up. The user must hold Reset_n low until the power and clocks stabilize plus 16-state times, or provide a high to low transition after the power and clocks have stabilized. T 1.18 Power-on Reset EV The last clock rising edge to output float time (TXHQZ ) is made consistent with the output data hold (TXHQX ) time of 2 TOSC +/ -50nsec. This is longer than the industry standard of 1 TOSC max. 1.25 NEG 8000h Instruction Operation 1.22 Industry Standard Register Indirect with Auto Increment The industry standard increments the auto-incremented register after determining the external address instead of at the end of the instruction completion. The UT80C196KDS performs the auto-increment function at the end of the instruction processing. Please reference the example below that shows the processing difference between the UT80C196KDS and the industry standard: ST R0, [R0]+ assume R0 holds the value 1000h before the instruction is executed. IN D The UT80C196KDS and the industry standard 80C196KD set the N-Flag differently when executing the NEG 8000h instruction. NEG represents the MCS-96 opcode to negate a defined operand (8000h). When the UT80C196KDS executes the NEG 8000h instruction, the result becomes 8000h with both the NFlag and the V-Flag set. The industry standard 80C196KD, however, executes the NEG 8000h instruction with a result of 8000h and only the V-Flag set. 1.26 Reserved Opcode EEH The industry standard 80C196KD using the MCS-96 ISA declares the opcode EEH as a reserved opcode and does not 37 guarantee the generation of the Unimplemented Opcode Interrupt. The UT80C196KDS, on the other hand, generates the Unimplemented Opcode Interrupt when the EEH opcode is executed. 1.27 Advanced Read/Write Signal (ADV_RD_WR) The UT80C196KDS provides an early indication of an external memory cycle direction being a read or write. This signal is output on pin 2. See Table 10 and Figure 4 for description of operation. IN D EV EL O PM EN T 1.28 Byte-Wide Reads of the HSI_Time SFR In order to ensure that the next HSI event is loaded from the FIFO into the HSI holding register, the HSI_TIME special function register must be read as a 16-bit word. Byte-wide reads of the HSI_TIME register will not result in successful loading of the HSI holding register. 38 IN D EV EL O PM EN T 8.0 PACKAGE Notes: 1. All package finishes are per MIL-PRF-38535. 2. Letter designations are for cross-reference to MIL-STD-1835. 3. All leads increase max. limit by 0.003 measured at the center of the flat, when lead finish A (solder) is applied. 4. ID mark: Configuration is optional. 5. Lettering is not subject to marking criteria. 6. Total weight is approx. 8.0 grams. 7. All dimensions are in inches. Figure 14. 68-lead Quad Flatpack 39 ORDERING INFORMATION UT80C196KDS 16-Bit Microcontroller: SMD 5962 * 02523 ** * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (X) = 68-lead top brazed flatpack Class Designator: (Q) = Class Q Device Type (01) = 20 Mhz, 16-bit microcontroller (-55oC to +125oC) (02) = 20 Mhz, 16-bit microcontroller, Extended Industrial Temp (-40oC to +125 o C ) Drawing Number: 02523 EN T Total Dose: None PM Federal Stock Class Designator: No options IN D EV EL O Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, part number will match the lead finish and will be either "A" (solder) or "C" (gold). 40 UT80C196KDS Microcontroller UT80C196KDS - * * * Lead Finish: (Notes 1, 2) (A) = Solder (C) = Gold (X) = Optional Screening:(Notes 3, 4, 5) (C) = Mil Temp (P) = Prototype (W) = Extended Industrial Temp (-40oC to +125 oC) Package Type: (W) = 68-lead top brazed Flatpack O PM EN T UTMC Core Part Number IN D EV EL Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part number will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation i s neither tested nor guaranteed. 4. Prototype flow per UTMC Manufacturing Flows Document Tested at 25C only. Lead finish is gold only. Radiation is neither tested nor guaranteed. 5. Extended Industrial Temperature Range Flow per UTMC Manufacturing Flows Document. Devices are tested at -40 o C, room temp, and +125 oC. Radiation is neither tested nor guaranteed. 41 IN D EV EL O PM EN T Notes 42 IN D EV EL O PM EN T Notes 43