FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2007-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.11
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
16-bit Microcontroller
CMOS
F2MC-16LX MB90920 Series
MB90F922NC/F922NCS/922NCS/F923NC/F923NCS/
MB90F924NC/F924NCS/V920-101/V920-102
■DESCRIPTION
The MB90920 series is a family of general-purpose Fujitsu Microelectronics 16-bit microcontrollers designed for
applications such as vehicle instrument panel control.
The instruction set retains the AT architecture from the F2MC-8L and F2MC-16LX families, with further refinements
including high-level language instructions, extended addressing modes, improved multiplication and division
operations (signed), and bit processing. In addition, long word processing is made possible by the inclusion of
a built-in 32-bit accumulator.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■FEATURES
•Clock
Built-in PLL clock frequency multiplication circuit.
Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 32 MHz).
Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed.
• 16-bit input capture (8 channels)
Detects rising, falling, or both edges.
16-bit capture register × 8
The value of a 16-bit free-run timer counter is latched upon detection of an edge input to pin and an interrupt
request is generated.
(Continued)
DS07-13750-3E
MB90920 Series
2DS07-13750-3E
(Continued)
• 16-bit reload timer (4 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Selectable event count function
• Real time watch timer (main clock)
Operates directly from oscillator clock.
Interrupt can be generated by second/minute/hour/date counter overflow.
• PPG timer (6 channels)
Output pins (3 channels), external trigger input pin (1 channel)
Operation clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interrupts to CPU can be generated/cleared by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• 8/10-bit A/D converter (8 channels)
Conversion time : 3 µs (at fCP = 32 MHz)
External trigger activation available (P50/INT0/ADTG)
Internal timer activation available (16-bit reload timer 1)
• UART(LIN/SCI) (4 channels)
Equipped with full duplex double buffer
Clock-asynchronous or clock-synchronous serial transfer is available
• CAN interface (4 channels : CAN0 and CAN2, and CAN1 and CAN3 share transmission and reception pins,
and interrupt control registers).
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and ID
Multiple message support
Flexible configuration for receive filter : Full bit compare/full bit mask/two partial bit masks
Supports up to 1 Mbps
CAN wakeup function (RX connected to INT0 internally)
• LCD controller/driver (32 segment x 4 common)
Segment driver and command driver with direct LCD panel (display) drive capability
• Reset on detection of low voltage/program loop
Automatic reset when low voltage is detected
Program looping detection function
• Stepping motor controller (4 channels)
High current output for each channel × 4
Synchronized 8/10-bit PWM for each channel × 2
• Sound generator (2 channels)
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 125 kHz, 62.5 kHz, 31.2 kHz, 15.6 kHz (at fCP = 32 MHz)
Tone frequencies : PWM frequency /2/ , divided by (reload frequency +1)
• Input/output ports
General-purpose input/output port (CMOS output) 93 ports
• Function for port input level selection
Automotive/CMOS-Schmitt
• Flash memory security function
Protects the contents of Flash memory (Flash memory product only)
MB90920 Series
DS07-13750-3E 3
■PRODUCT LINEUP
Part number
Parameter
MB90
F922NC
MB90
F922NCS
MB90
F923NC
MB90
F923NCS
MB90
F924NC
MB90
F924NCS
MB90
922NCS
MB90
V920-101
MB90
V920-102
Type Flash memory product
MASK
ROM
product
Evaluation product
CPU F2MC-16LX CPU
System clock PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, × 8, 1/2 when PLL stopped)
Minimum instruction execution time 31.25 ns (with 4 MHz oscillation clock × 8)
Sub clock pins
(X0A, X1A) Yes No Yes No Yes No No No Yes
ROM Flash memory
256 Kbytes
Flash memory
384 Kbytes
Flash memory
512 Kbytes
256 K
bytes External
RAM 10 Kbytes 16 Kbytes 24 Kbytes 10 K
bytes 30 Kbytes
I/O port 91 ports 93 ports 91 ports 93 ports 91 ports 93 ports 93 ports 93 ports 91 ports
LCD controller 32 segment × 4 common
LIN-UART UART (LIN/SCI) 4 channels
CAN interface 4 channels
16-bit
input capture 8 channels
16-bit
reload timer 4 channels
16-bit free-run
timer 1 channel
Real time watch
timer 1 channel
16-bit PPG timer 6 channels
External interrupt 8 channels
8/10-bit
A/D converter 8 channels
Low-voltage/
CPU operating
detection reset
Yes No
Stepping motor
controller 4 channels
Sound generator 2 channels
Flash memory
security Yes ⎯
Operating
voltage 4.0 V to 5.5 V 4.5 V to 5.5 V
Package LQFP-120 PGA-299
MB90920 Series
4DS07-13750-3E
■PIN ASSIGNMENT
(TOP VIEW)
(FPT-120P-M21)
* : MB90V920-101, MB90F922NCS,MB90F923NCS,MB90F924NCS,MB90922NCS : P92, P93
MB90V920-102, MB90F922NC,MB90F923NC,MB90F924NC : X0A, X1A
P30/SEG06
P31/SEG07
P32/SEG08
P33/SEG09
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
* P92/X0A
* P93/X1A
VCC
VSS
C
P44/SEG18
P45/SEG19
P46/SEG20
P47/SEG21
P90/SEG22
P91/SEG23
PD0/SIN2
PD1/SOT2
PD2/SCK2
PD3/SIN3
PD4/SOT3
PD5/SCK3
PD6/TOT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RST
MD0
MD1
MD2
DVSS
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
DVCC
PE2/SGO1
P55/RX0/RX2/INT2
RSTO
P54/TX0/TX2/SGA1
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P94/V0
P95/V1
P96/V2
V3
AVCC
AVRH
P50/INT0/ADTG
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PC0/SIN0/INT4
PC1/SOT0/INT5/IN3
PC2/SCK0/INT6/IN2
PC3/SIN1/INT7
PC4/SOT1
PC5/SCK1/TRG
PC6/PPG0/TOT1/IN7
PC7/PPG1/TIN1/IN6
PE0/TOT3
PE1/TIN3
P51/INT1/RX1/RX3
P52/TX1/TX3
P53/INT3
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P27/SEG05
P26/SEG04
P25/SEG03
P24/SEG02
P23/SEG01
P22/SEG00
COM3
COM2
COM1
COM0
P15/IN0
P14/TIN2/IN1
X0
X1
VSS
VCC
P13/PPG5
P12/TIN0/PPG4
P11/TOT0/PPG3/IN4
P10/PPG2/IN5
P07/SEG31
P06/SEG30
P05/SEG29
P04/SEG28
P03/SEG27
P02/SEG26
P01/SEG25
P00/SEG24
P57/SGA0
P56/SGO0/FRCK
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
LQFP-120
MB90920 Series
DS07-13750-3E 5
■PIN DESCRIPTIONS
(Continued)
Pin no. Pin name I/O circuit
type*1Function
108 X0 AHigh-speed oscillation input pin
107 X1 High-speed oscillation output pin
13 X0A B Low-speed oscillation input pin
P92 I General-purpose I/O port
14 X1A B Low-speed oscillation output pin
P93 I General-purpose I/O port
90 RST C Reset input pin
93 P00 FGeneral-purpose I/O port
SEG24 LCD controller/driver segment output pin
94 P01 FGeneral-purpose I/O port
SEG25 LCD controller/driver segment output pin
95 P02 FGeneral-purpose I/O port
SEG26 LCD controller/driver segment output pin
96 P03 FGeneral-purpose I/O port
SEG27 LCD controller/driver segment output pin
97 P04 FGeneral-purpose I/O port
SEG28 LCD controller/driver segment output pin
98 P05 FGeneral-purpose I/O port
SEG29 LCD controller/driver segment output pin
99 P06 FGeneral-purpose I/O port
SEG30 LCD controller/driver segment output pin
100 P07 FGeneral-purpose I/O port
SEG31 LCD controller/driver segment output pin
101
P10
I
General-purpose I/O port
PPG2 16-bit PPG ch.2 output pin
IN5 Input capture ch.5 trigger input pin
102
P11
I
General-purpose I/O port
TOT0 16-bit reload timer ch.0 TOT output pin
PPG3 16-bit PPG ch.3 output pin
IN4 Input capture ch.4 trigger input pin
103
P12
I
General-purpose I/O port
TIN0 16-bit reload timer ch.0 TIN input pin
PPG4 16-bit PPG ch.4 output pin
MB90920 Series
6DS07-13750-3E
(Continued)
Pin no. Pin name I/O circuit
type*1Function
104 P13 IGeneral-purpose I/O port
PPG5 16-bit PPG ch.5 output pin
109
P14
I
General-purpose I/O port
TIN2 16-bit reload timer ch.2 TIN input pin
IN1 Input capture ch.1 trigger input pin
110 P15 IGeneral-purpose I/O port
IN0 Input capture ch.0 trigger input pin
111 COM0 P LCD controller/driver common output pin
112 COM1 P LCD controller/driver common output pin
113 COM2 P LCD controller/driver common output pin
114 COM3 P LCD controller/driver common output pin
115 P22 FGeneral-purpose I/O port
SEG00 LCD controller/driver segment output pin
116 P23 FGeneral-purpose I/O port
SEG01 LCD controller/driver segment output pin
117 P24 FGeneral-purpose I/O port
SEG02 LCD controller/driver segment output pin
118 P25 FGeneral-purpose I/O port
SEG03 LCD controller/driver segment output pin
119 P26 FGeneral-purpose I/O port
SEG04 LCD controller/driver segment output pin
120 P27 FGeneral-purpose I/O port
SEG05 LCD controller/driver segment output pin
1P30 FGeneral-purpose I/O port
SEG06 LCD controller/driver segment output pin
2P31 FGeneral-purpose I/O port
SEG07 LCD controller/driver segment output pin
3P32 FGeneral-purpose I/O port
SEG08 LCD controller/driver segment output pin
4P33 FGeneral-purpose I/O port
SEG09 LCD controller/driver segment output pin
5P34 FGeneral-purpose I/O port
SEG10 LCD controller/driver segment output pin
6P35 FGeneral-purpose I/O port
SEG11 LCD controller/driver segment output pin
MB90920 Series
DS07-13750-3E 7
(Continued)
Pin no. Pin name I/O circuit
type*1Function
7P36 FGeneral-purpose I/O port
SEG12 LCD controller/driver segment output pin
8P37 FGeneral-purpose I/O port
SEG13 LCD controller/driver segment output pin
9P40 FGeneral-purpose I/O port
SEG14 LCD controller/driver segment output pin
10 P41 FGeneral-purpose I/O port
SEG15 LCD controller/driver segment output pin
11 P42 FGeneral-purpose I/O port
SEG16 LCD controller/driver segment output pin
12 P43 FGeneral-purpose I/O port
SEG17 LCD controller/driver segment output pin
18 P44 FGeneral-purpose I/O port
SEG18 LCD controller/driver segment output pin
19 P45 FGeneral-purpose I/O port
SEG19 LCD controller/driver segment output pin
20 P46 FGeneral-purpose I/O port
SEG20 LCD controller/driver segment output pin
21 P47 FGeneral-purpose I/O port
SEG21 LCD controller/driver segment output pin
37
P50
I
General-purpose I/O port
INT0 INT0 external interrupt input pin
ADTG A/D converter external trigger input pin
58
P51
I
General-purpose I/O port
INT1 INT1 external interrupt input pin
RX1 CAN interface 1 RX input pin
RX3 CAN interface 3 RX input pin
59
P52
I
General-purpose I/O port
TX1 CAN interface 1 TX output pin
TX3 CAN interface 3 TX output pin
60 P53 IGeneral-purpose I/O port
INT3 INT3 external interrupt input pin
MB90920 Series
8DS07-13750-3E
(Continued)
Pin no. Pin name I/O circuit
type*1Function
61
P54
I
General-purpose I/O port
TX0 CAN interface 0 TX output pin
TX2 CAN interface 2 TX output pin
SGA1 Sound generator ch.1 SGA output pin
63
P55
I
General-purpose I/O port
RX0 CAN interface 0 RX input pin
RX2 CAN interface 2 RX input pin
INT2 INT2 external interrupt input pin
91
P56
I
General-purpose I/O port
SGO0 Sound generator ch.0 SGO output pin
FRCK Free-run timer clock input pin
92 P57 IGeneral-purpose I/O port
SGA0 Sound generator ch.0 SGA output pin
39 P60 HGeneral-purpose I/O port
AN0 A/D converter input pin
40 P61 HGeneral-purpose I/O port
AN1 A/D converter input pin
41 P62 HGeneral-purpose I/O port
AN2 A/D converter input pin
42 P63 HGeneral-purpose I/O port
AN3 A/D converter input pin
43 P64 HGeneral-purpose I/O port
AN4 A/D converter input pin
44 P65 HGeneral-purpose I/O port
AN5 A/D converter input pin
45 P66 HGeneral-purpose I/O port
AN6 A/D converter input pin
46 P67 HGeneral-purpose I/O port
AN7 A/D converter input pin
67 P70 LGeneral-purpose output-only port
PWM1P0 Stepping motor controller ch.0 output pin
68 P71 LGeneral-purpose output-only port
PWM1M0 Stepping motor controller ch.0 output pin
69 P72 LGeneral-purpose output-only port
PWM2P0 Stepping motor controller ch.0 output pin
MB90920 Series
DS07-13750-3E 9
(Continued)
Pin no. Pin name I/O circuit
type*1Function
70 P73 LGeneral-purpose output-only port
PWM2M0 Stepping motor controller ch.0 output pin
71 P74 LGeneral-purpose output-only port
PWM1P1 Stepping motor controller ch.1 output pin
72 P75 LGeneral-purpose output-only port
PWM1M1 Stepping motor controller ch.1 output pin
73 P76 LGeneral-purpose output-only port
PWM2P1 Stepping motor controller ch.1 output pin
74 P77 LGeneral-purpose output-only port
PWM2M1 Stepping motor controller ch.1 output pin
77 P80 LGeneral-purpose output-only port
PWM1P2 Stepping motor controller ch.2 output pin
78 P81 LGeneral-purpose output-only port
PWM1M2 Stepping motor controller ch.2 output pin
79 P82 LGeneral-purpose output-only port
PWM2P2 Stepping motor controller ch.2 output pin
80 P83 LGeneral-purpose output-only port
PWM2M2 Stepping motor controller ch.2 output pin
81 P84 LGeneral-purpose output-only port
PWM1P3 Stepping motor controller ch.3 output pin
82 P85 LGeneral-purpose output-only port
PWM1M3 Stepping motor controller ch.3 output pin
83 P86 LGeneral-purpose output-only port
PWM2P3 Stepping motor controller ch.3 output pin
84 P87 LGeneral-purpose output-only port
PWM2M3 Stepping motor controller ch.3 output pin
22 P90 FGeneral-purpose I/O port
SEG22 LCD controller/driver segment output pin
23 P91 FGeneral-purpose I/O port
SEG23 LCD controller/driver segment output pin
31 P94 GGeneral-purpose I/O port
V0 LCD controller/driver reference power supply pin
32 P95 GGeneral-purpose I/O port
V1 LCD controller/driver reference power supply pin
MB90920 Series
10 DS07-13750-3E
(Continued)
Pin no. Pin name I/O circuit
type*1Function
33 P96 GGeneral-purpose I/O port
V2 LCD controller/driver reference power supply pin
34 V3 ⎯LCD controller/driver reference power supply pin
48
PC0
J
General-purpose I/O port
SIN0 UART ch.0 serial data input pin
INT4 INT4 external interrupt input pin
49
PC1
I
General-purpose I/O port
SOT0 UART ch.0 serial data output pin
INT5 INT5 external interrupt input pin
IN3 Input capture ch.3 trigger input pin
50
PC2
I
General-purpose I/O port
SCK0 UART ch.0 serial clock I/O pin
INT6 INT6 external interrupt input pin
IN2 Input capture ch.2 trigger input pin
51
PC3
J
General-purpose I/O port
SIN1 UART ch.1 serial data input pin
INT7 INT7 external interrupt input pin
52 PC4 IGeneral-purpose I/O port
SOT1 UART ch.1 serial data output pin
53
PC5
I
General-purpose I/O port
SCK1 UART ch.1 serial clock I/O pin
TRG 16-bit PPG ch.0 to ch.5 external trigger input pin
54
PC6
I
General-purpose I/O port
PPG0 16-bit PPG ch.0 output pin
TOT1 16-bit reload timer ch.1 TOT output pin
IN7 Input capture ch.7 trigger input pin
55
PC7
I
General-purpose I/O port
PPG1 16-bit PPG ch.1 output pin
TIN1 16-bit reload timer ch.1 TIN input pin
IN6 Input capture ch.6 trigger input pin
24 PD0 JGeneral-purpose I/O port
SIN2 UART ch.2 serial data input pin
25 PD1 IGeneral-purpose I/O port
SOT2 UART ch.2 serial data output pin
MB90920 Series
DS07-13750-3E 11
(Continued)
*1 : For I/O circuit type, refer to “ ■ I/O CIRCUIT TYPES”.
*2 : The I/O circuit type is D for Flash memory products and E for evaluation products.
Pin no. Pin name I/O circuit
type*1Function
26 PD2 IGeneral-purpose I/O port
SCK2 UART ch.2 serial clock I/O pin
27 PD3 JGeneral-purpose I/O port
SIN3 UART ch.3 serial data input pin
28 PD4 IGeneral-purpose I/O port
SOT3 UART ch.3 serial data output pin
29 PD5 IGeneral-purpose I/O port
SCK3 UART ch.3 serial clock I/O pin
30 PD6 IGeneral-purpose I/O port
TOT2 16-bit reload timer ch.2 TOT output pin
56 PE0 IGeneral-purpose I/O port
TOT3 16-bit reload timer ch.3 TOT output pin
57 PE1 IGeneral-purpose I/O port
TIN3 16-bit reload timer ch.3 TIN input pin
64 PE2 IGeneral-purpose I/O port
SGO1 Sound generator ch.1 SGO output pin
62 RSTO N Internal reset signal output pin
65, 75, 85 DVCC ⎯Power supply input pins dedicated for high current output buffer
66, 76, 86 DVSS ⎯Power supply GND pins dedicated for high current output buffer
35 AVCC ⎯A/D converter dedicated power supply input pin
38 AVSS ⎯A/D converter dedicated power supply GND pin
36 AVRH ⎯A/D converter Vref+ input pin. Vref- is fixed to AVSS.
89 MD0 D Mode setting input pin. Connect to VCC pin.
88 MD1 D Mode setting input pin. Connect to VCC pin.
87 MD2 D/E*2 Mode setting input pin. Connect to VSS pin.
17 C ⎯External capacitor pin.
Connect a 0.1 µF capacitor between this pin and the VSS pin.
15, 105 VCC ⎯Power supply input pins
16, 47, 106 VSS ⎯GND power supply pins
MB90920 Series
12 DS07-13750-3E
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A Oscillation circuit
High-speed oscillation feedback
resistance :
approx. 1 MΩ
(Flash memory product/MASK ROM
product/Evaluation product)
B Oscillation circuit
Low-speed oscillation feedback
resistance : approx. 10 MΩ
C Input-only pin (with pull-up resistance)
• Attached pull-up resistor :
approx. 50 kΩ
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
D Input-only pin
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
Note: The MD2 pin of the Flash
memory products uses this
circuit type.
X1
X0
Xout
Standby control signal
X1A
X0A
Xout
Standby control signal
CMOS hysteresis input
Pull-up resistor
CMOS hysteresis input
MB90920 Series
DS07-13750-3E 13
(Continued)
Type Circuit Remarks
E Input-only pin (with pull-down
resistance)
• Attached pull-down resistance :
approx. 50 kΩ
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
Note: The MD2 pin of the evaluation
products uses this circuit type.
F LCD output common general-
purpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
G LCDC reference power supply com-
mon general-purpose port
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Pull-down resistor
P-ch
N-ch
Standby control signal or
LCD input enable signal
LCD input
CMOS hysteresis input
Standby control signal or
LCD input enable signal
Automotive input
Pout
Nout
P-ch
N-ch
LCDC reference power supply
input
CMOS hysteresis input
Standby control signal or
LCD output switching signal
Automotive input
Standby control signal or
LCD output switching signal
Pout
Nout
MB90920 Series
14 DS07-13750-3E
(Continued)
Type Circuit Remarks
H A/D converter input common
general-purpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
I General-purpose port
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
J General-purpose port (serial input)
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
P-ch
N-ch
Analog input
CMOS hysteresis input
Standby control signal or
analog input enable signal
Automotive input
Standby control signal or
analog input enable signal
Pout
Nout
P-ch
N-ch
CMOS hysteresis input
Standby control signal
Automotive input
Standby control signal
Pout
Nout
P-ch
N-ch
CMOS hysteresis input
Standby control signal
Automotive input
Standby control signal
CMOS input (SIN)
Standby control signal
Pout
Nout
MB90920 Series
DS07-13750-3E 15
(Continued)
Type Circuit Remarks
K A/D converter input common general-
purpose port (serial input)
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
L High current output port (SMC pin)
CMOS output (IOH/IOL = ± 30 mA)
M LCDC output common general-
purpose port (serial input) )
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
P-ch
N-ch
Analog output
CMOS hysteresis input
Standby control signal
or analog input enable signal
Automotive input
Standby control signal
or analog input enable signal
CMOS input (SIN)
Standby control signal
or analog input enable signal
Pout
Nout
P-ch
N-ch
High current
Pout
Nout
P-ch
N-ch
LCDC output
CMOS hysteresis input
Standby control signal or
LCDC output switching signal
Automotive input
Standby control signal or
LCDC output switching signal
CMOS input (SIN)
Standby control signal or
LCDC output switching signal
Pout
Nout
MB90920 Series
16 DS07-13750-3E
(Continued)
Type Circuit Remarks
N N-ch open-drain pin
IOL = 4 mA
O Input-only pin
Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
P LCDC output pin (COM pin)
N-ch
P-ch
N-ch
Flash memory productEvaluation product
Nout Nout
Automotive input
N-ch
P-ch
LCDC output
MB90920 Series
DS07-13750-3E 17
■HANDLING DEVICES
• Strictly observe maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium or high withstand voltage pins, or if the voltage applied between
VCC and VSS pins exceeds the rated voltage level. If a latch-up occurs, the power supply current may increase
dramatically and may destroy semiconductor elements. When using semiconductor devices, always take suffi-
cient care to avoid exceeding maximum ratings.
When the analog system power supply is switched on or off, be careful not to apply the analog power supply
(AVCC, AVRH), the analog input voltages and the power supply voltage for the high current output buffer pins
(DVCC) in excess of the digital power supply voltage (VCC).
Once the digital power supply voltage (VCC) has been disconnected, the analog power supply (AVCC, AVRH) and
the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence.
• Supply voltage stabilization
Rapid fluctuations in the power supply voltage can cause malfunctions even if the Vcc power supply voltage
remains within the warranted operating range. It is recommended that the power supply be stabilized such that
ripple fluctuations (P-P value) at commercial frequencies (50 Hz/60 Hz) be limited to within 10% of the standard
VCC value, and that transient fluctuations due to power supply switching, etc. be limited to a rate of 0.1 V/ms or less.
• Precautions when turning the power on
In order to prevent the built-in step-down circuits from malfunctioning, the time taken for the voltage to rise
(0.2 V to 2.7 V) during power-on should be less than 50 µs.
• Handling unused pins
If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage
to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at
least 2 kΩ.
Unused input/output pins may be set to the output state and left open, or set to the input state and connected
to a pull-up or pull-down resistance of 2 kΩ or more.
• Handling A/D converter power supply pins
Even if the A/D converter is not used, the power supply pins should be connected such as AVCC = VCC, and
AVSS = AVRH = VSS.
• Notes on using an external clock
Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset
or release from sub clock mode or stop mode. Furthermore, only the X0A pin should be driven when an external
clock is used, with the X1A pin open as shown in the following diagram. Do not use high-speed oscillation pins
(X0 and X1) for external clock input.
X0A
X1A
OPEN
MB90920 Series
Sample external clock connection
MB90920 Series
18 DS07-13750-3E
• Notes on operating in PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
• Crystal oscillator circuit
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable
operation it is strongly recommended that printed circuit artwork places ground bypass capacitors as close as
possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross
the lines of other circuits.
Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Power supply pins
Devices including multiple VCC or VSS pins are designed such that pins that need to be at the same potential
are interconnected internally to prevent malfunctions such as latch-up. To reduce unnecessary radiation, prevent
malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output
current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Always connect all of the VCC pins to the same potential and all of the VSS pins to ground as shown in the
following diagram. The device will not operate correctly if multiple VCC or VSS pins are connected to different
voltages, even if those voltages are within the guaranteed operating ranges.
In addition, care must be given to connecting the VCC and VSS pins of this device to the current supply source
with as low impedance as possible. It is recommended that a 1.0 µF bypass capacitor be connected between
the VCC and VSS pins as close to the pins as possible.
• Sequence for connecting the A/D converter power supply and analog inputs
The A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN7) must be applied after the digital
power supply (VCC) is switched on. When turning the power off, the A/D converter power supply and analog
inputs must be disconnected before the digital power supply is switched off (VCC). Ensure that AVRH does not
exceed AVcc during either power-on or power-off. Even when pins which double as analog input pins are used
as input ports, be sure that the input voltage does not exceed AVCC (turning on/off the analog and digital power
supplies simultaneously is acceptable).
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
Power supply input pins (Vcc/Vss)
MB90920 Series
DS07-13750-3E 19
•Handling the power supply for high-current output buffer pins (DVCC, DVSS)
• Flash memory products and MASK ROM products (MB90F922NC/F922NCS/922NCS/F923NC/
F923NCS/F924NC/F924NCS)
In the Flash memory products and MASK ROM products, the power supply for the high-current output
buffer pins (DVCC, DVSS) is isolated from the digital power supply (VCC).
Therefore, DVcc can therefore be set to a higher voltage than Vcc. If the power supply for the high-current
output buffer pins (DVCC, DVSS) is supplied before the digital power supply (VCC), however, care needs
to be taken because it is possible that the port 7 or port 8 stepping motor outputs may momentarily output
an “H” or “L” level. In order to prevent this, connect the digital power supply (VCC) prior to connecting the
power supply for the high-current output buffer pins. Even when the high-current output buffer pins are
used as general-purpose ports, power should be supplied to the power supply pins for the high-current
output buffer pins (DVCC, DVSS).
• Evaluation product (MB90V920-101/MB90V920-102)
In the evaluation products, the power supply for the high-current output buffer pins (DVCC, DVSS) is not
isolated from the digital power supply (VCC). Therefore, DVCC must therefore be set to a lower voltage than
Vcc. The power supply for the high-current output buffer pins (DVCC, DVSS) must always be applied after
the digital power supply (VCC) has been connected, and disconnected before the digital power supply (Vcc)
is disconnected (the power supply for the high-current output buffer pins may also be connected and
disconnected simultaneously with the digital power supply).
Even when the high-current output buffer pins are used as general-purpose ports, power should be
supplied to the power supply pins for the high-current output buffer pins (DVCC, DVSS).
• Pull-up/pull-down resistors
MB90920 series does not support internal pull-up/pull-down resistors. Use external components as necessary.
• Precautions when not using a sub clock signal
If the X0A and X1A pins are not connected to an oscillator, apply a pull-down resistance to the X0A pin and
leave the X1A pin open.
• Notes on operating when the external clock is stopped
The MB90920 series is not guaranteed to operate correctly using the internal oscillator circuit when there is no
external oscillator or the external clock input is stopped.
• Flash memory security function
A security bit is located within the Flash memory region. The security function is activated by writing the protection
code 01H to the security bit.
Do not write the value 01H to this address if you are not using the security function.
Please refer to following table for the address of the security bit.
Flash memory size Address for security bit
MB90F922NC
MB90F922NCS Built-in 2 Mbits Flash Memory FC0001H
MB90F923NCS Built-in 3 Mbits Flash Memory F80001H
MB90F924NCS Built-in 4 Mbits Flash Memory F80001H
MB90920 Series
20 DS07-13750-3E
■BLOCK DIAGRAM
LIN-UART 0
Prescaler 0
Prescaler 1
Prescaler 2
Prescaler 3
16-bit PPG timer 0
16-bit PPG timer 1
16-bit PPG timer 2
16-bit PPG timer 3
16-bit PPG timer 4
16-bit PPG timer 5
16-bit reload timer 0
16-bit reload timer 1
16-bit reload timer 2
16-bit reload timer 3
16-bit ICU 0 (2 channels)
16-bit ICU 1 (2 channels)
16-bit ICU 2 (2 channels)
16-bit ICU 3 (2 channels)
16-bit free-run timer
: Flash memory product and MASK ROM product only
: Evaluation product only
Real-time watch timer
(main)
Clock control circuit
Interrupt controller
CPU operation
detection reset
Low-voltage reset
Stepping motor controller 0
Stepping motor controller 1
Stepping motor controller 2
Stepping motor controller 3
A/D converter
(8 channels)
LCD controller/driver
(32 SEG/4 COM)
RAM
ROM/Flash
Tool interface
CPU
F2MC-16LX core
Watchdog timer
Time-base timer
Sound generator 0
Sound generator 1
CAN controller 0
CAN controller 1
CAN controller 2
CAN controller 3
External interrupt
(8 channels)
Watch timer
(for sub clock)
LIN-UART 1
LIN-UART 2
LIN-UART 3
F2MC-16LX BUS
MB90920 Series
DS07-13750-3E 21
■ MEMORY MAP
Note : To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in
Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order
to enable efficient use of small C compiler models. The lower 16-bits of the FF bank addresses are allocated
to the same addresses as the lower 16-bits of the 00 bank, making it possible to reference tables in ROM
without declaring the “far” modifier with the pointers. For example, when an access is made to the address
00C000H, the actual address to be accessed is FFC000H in ROM. Because the size of the FF bank ROM
area exceeds 32 Kbytes, it is not possible to view the entire region in the 00 bank image. Therefore because
the ROM data from FF8000H to FFFFFFH appears in the image from 008000H to 00FFFFH, it is
recommended that ROM data tables be stored in the area from FF8000H to FFFFFFH.
* : Evaluation products do not contain internal ROM. Treat this address as the ROM decode area used by the tools.
Parts No. ROM (Flash)
capacitance
RAM
capacitance Address #1 Address #2 Address #3
MB90F922NC/F922NCS/922NCS 256 Kbytes 10 Kbytes FC0000H004000H002900H
MB90F923NC/F923NCS 384 Kbytes 16 Kbytes FA0000H004A00H003700H
MB90F924NC/F924NCS 512 Kbytes 24 Kbytes F80000H006A00H003700H
000000H
0000F0H
000100H
003700H
004000H
008000H
010000H
F80000H
FFFFFFH
000000H
000100H
0000EFH
003700H
Address #3
Address #2
Address #1
004000H
008000H
010000H
FFFFFFH
Peripheral area
Peripheral area
RAM area
(13.5 Kbytes)
RAM area
(16 Kbytes)
RAM area
ROM area
(FF bank image)
Peripheral area
RAM area
Peripheral area
ROM area
(FF bank image)
ROM area*
ROM area*
MB90V920 (Evaluation product)
: Internal access prohibited
: Internal access
Register Register
MB90F923 / MB90F924
MB90F922 / MB90922
MB90920 Series
22 DS07-13750-3E
■I/O MAP
(Continued)
Address Register name Symbol Read/write Resource name Initial value
000000HPort 0 data register PDR0 R/W Port 0 XXXXXXXXB
000001HPort 1 data register PDR1 R/W Port 1 XXXXXXXXB
000002HPort 2 data register PDR2 R/W Port 2 XXXXXXXXB
000003HPort 3 data register PDR3 R/W Port 3 XXXXXXXXB
000004HPort 4 data register PDR4 R/W Port 4 XXXXXXXXB
000005HPort 5 data register PDR5 R/W Port 5 XXXXXXXXB
000006HPort 6 data register PDR6 R/W Port 6 XXXXXXXXB
000007HPort 7 data register PDR7 R/W Port 7 XXXXXXXXB
000008HPort 8 data register PDR8 R/W Port 8 XXXXXXXXB
000009HPort 9 data register PDR9 R/W Port 9 XXXXXXXXB
00000AH,
00000BH (Disabled)
00000CHPort C data register PDRC R/W Port C XXXXXXXXB
00000DHPort D data register PDRD R/W Port D XXXXXXXXB
00000EHPort E data register PDRE R/W Port E XXXXXXXXB
00000FH (Disabled)
000010HPort 0 direction register DDR0 R/W Port 0 00000000B
000011HPort 1 direction register DDR1 R/W Port 1 XX000000B
000012HPort 2 direction register DDR2 R/W Port 2 000000XXB
000013HPort 3 direction register DDR3 R/W Port 3 00000000B
000014HPort 4 direction register DDR4 R/W Port 4 00000000B
000015HPort 5 direction register DDR5 R/W Port 5 00000000B
000016HPort 6 direction register DDR6 R/W Port 6 00000000B
000017HPort 7 direction register DDR7 R/W Port 7 00000000B
000018HPort 8 direction register DDR8 R/W Port 8 00000000B
000019HPort 9 direction register DDR9 R/W Port 9 X0000000B
00001AHAnalog input enable ADER6 R/W Port 6, A/D 11111111B
00001BH (Disabled)
00001CHPort C direction register DDRC R/W Port C 00000000B
00001DHPort D direction register DDRD R/W Port D X0000000B
00001EHPort E direction register DDRE R/W Port E XXXXX000B
00001FH (Disabled)
000020HLower A/D control status register ADCS0 R/W
A/D converter
000XXXX0B
000021HHigher A/D control status register ADCS1 R/W 0000000XB
000022HLower A/D control status register ADCR0 R 00000000B
000023HHigher A/D data register ADCR1 R XXXXXX00B
MB90920 Series
DS07-13750-3E 23
(Continued)
Address Register name Symbol Read/write Resource name Initial value
000024HCompare clear register CPCLR R/W
16-bit
free-run timer
XXXXXXXXB
000025HR/W XXXXXXXXB
000026HTimer data register TCDT R/W 00000000B
000027HR/W 00000000B
000028HLower timer control status register TCCSL R/W 00000000B
000029HHigher timer control status register TCCSH R/W 01-00000B
00002AHLower PPG0 control status register PCNTL0 R/W 16-bit PPG0 00000000B
00002BHHigher PPG0 control status register PCNTH0 R/W 00000001B
00002CHLower PPG1 control status register PCNTL1 R/W 16-bit PPG1 00000000B
00002DHHigher PPG1 control status register PCNTH1 R/W 00000001B
00002EHLower PPG2 control status register PCNTL2 R/W 16-bit PPG2 00000000B
00002FHHigher PPG2 control status register PCNTH2 R/W 00000001B
000030HExternal interrupt enable ENIR R/W
External interrupt
00000000B
000031HExternal interrupt request EIRR R/W 00000000B
000032HLower external interrupt level ELVRL R/W 00000000B
000033HHigher external interrupt level ELVRH R/W 00000000B
000034HSerial mode register 0 SMR0 R/W, W
UART
(LIN/SCI) 0
00000000B
000035HSerial control register 0 SCR0 R/W, W 00000000B
000036HReception/transmission data register 1 RDR0/
TDR0 R/W 00000000B
000037HSerial status register 0 SSR0 R/W, R 00001000B
000038HExtended communication control
register 0 ECCR0 R/W, R 000000XXB
000039HExtended status control register 0 ESCR0 R/W 00000100B
00003AHBaud rate generator register 00 BGR00 R/W 00000000B
00003BHBaud rate generator register 01 BGR01 R/W, R 00000000B
00003CH
to
00003FH
(Disabled)
000040H
to
00004FH
Area reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
000050HLower timer control status register 0 TMCSR0L R/W
16-bit reload timer
0
00000000B
000051HHigher timer control status register 0 TMCSR0H R/W XXX10000B
000052HTimer register 0/reload register 0 TMR0/
TMRLR0 R/W XXXXXXXXB
000053HXXXXXXXXB
MB90920 Series
24 DS07-13750-3E
(Continued)
Address Register name Symbol Read/write Resource name Initial value
000054HLower timer control status register 1 TMCSR1L R/W
16-bit reload timer
1
00000000B
000055HHigher timer control status register 1 TMCSR1H R/W XXX10000B
000056HTimer register 1/reload register 1 TMR1/
TMRLR1 R/W XXXXXXXXB
000057HXXXXXXXXB
000058HLCD output control register 1 LOCR1 R/W LCDC 11111111B
000059HLCD output control register 2 LOCR2 R/W 00000000B
00005AHLower sound control register 0 SGCRL0 R/W
Sound generator 0
00000000B
00005BHHigher sound control register 0 SGCRH0 R/W 0XXXX100B
00005CHFrequency data register 0 SGFR0 R/W XXXXXXXXB
00005DHAmplitude data register 0 SGAR0 R/W 00000000B
00005EHDecrement grade register 0 SGDR0 R/W XXXXXXXXB
00005FHTone count register 0 SGTR0 R/W XXXXXXXXB
000060HInput capture register 0 IPCP0 R
Input capture 0/1
XXXXXXXXB
000061HXXXXXXXXB
000062HInput capture register 1 IPCP1 R XXXXXXXXB
000063HXXXXXXXXB
000064HInput capture register 2 IPCP2 R
Input capture 2/3
XXXXXXXXB
000065HXXXXXXXXB
000066HInput capture register 3 IPCP3 R XXXXXXXXB
000067HXXXXXXXXB
000068HInput capture control status 0/1 ICS01 R/W Input capture 0/1 00000000B
000069HInput capture edge register 0/1 ICE01 R/W XXX0X0XXB
00006AHInput capture control status 2/3 ICS23 R/W Input capture 2/3 00000000B
00006BHInput capture edge register 2/3 ICE23 R/W XXXXXXXXB
00006CHLower LCD control register LCRL R/W LCD controller/
driver
00010000B
00006DHHigher LCD control register LCRH R/W 00000000B
00006EHLow voltage/CPU operation
detection reset control register LVRC R/W
Low voltage/CPU
operation
detection reset
00111000B
00006FHROM mirror ROMM W ROM mirror XXXXXXX1B
000070H
to
00007FH
Area reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
000080HPWM control register 0 PWC0 R/W Stepping motor
controller 0 000000X0B
000081H (Disabled)
000082HPWM control register 1 PWC1 R/W Stepping motor
controller 1 000000X0B
MB90920 Series
DS07-13750-3E 25
(Continued)
Address Register name Symbol Read/write Resource name Initial value
000083H (Disabled)
000084HPWM control register 2 PWC2 R/W Stepping motor
controller 2 000000X0B
000085H (Disabled)
000086HPWM control register 3 PWC3 R/W Stepping motor
controller 3 000000X0B
000087H (Disabled)
000088HLCD output control register 3 LOCR3 R/W LCDC XXXXX111B
000089H (Disabled)
00008AHA/D setting register 0 ADSR0 R/W A/D converter 00000000B
00008BHA/D setting register 1 ADSR1 R/W 00000000B
00008CHPort input level select 0 PIL0 R/W
Port input level
select
00000000B
00008DHPort input level select 1 PIL1 R/W XXXX0000B
00008EHPort input level select 2 PIL2 R/W XXXX0000B
00008FH
to
00009DH
(Disabled)
00009EHProgram address detection control
register PACSR R/W Address match
detection XXXX0X0XB
00009FHDelayed Interrupt/Release Register DIRR R/W Delay interrupt XXXXXXX0B
0000A0HPower saving mode control register LPMCR R/W Power saving
control circuit
00011000B
0000A1HClock select register CKSCR R/W, R 11111100B
0000A2H
to
0000A7H
(Disabled)
0000A8HWatchdog timer control register WDTC R, W Watchdog timer XXXXX111B
0000A9HTime-base timer control register TBTC R/W, W Time-base timer 1XX00100B
0000AAHWatch timer control register WTC R/W, W, R Watch timer
(sub clock) 10001000B
0000ABH
to
0000ADH
(Disabled)
0000AEHFlash memory control status register FMCS R/W Flash interface 000X0000B
0000AFH (Disabled)
MB90920 Series
26 DS07-13750-3E
(Continued)
Address Register name Symbol Read/write Resource name Initial value
0000B0HInterrupt control register 00 ICR00 R/W
Interrupt controller
00000111B
0000B1HInterrupt control register 01 ICR01 R/W 00000111B
0000B2HInterrupt control register 02 ICR02 R/W 00000111B
0000B3HInterrupt control register 03 ICR03 R/W 00000111B
0000B4HInterrupt control register 04 ICR04 R/W 00000111B
0000B5HInterrupt control register 05 ICR05 R/W 00000111B
0000B6HInterrupt control register 06 ICR06 R/W 00000111B
0000B7HInterrupt control register 07 ICR07 R/W 00000111B
0000B8HInterrupt control register 08 ICR08 R/W 00000111B
0000B9HInterrupt control register 09 ICR09 R/W 00000111B
0000BAHInterrupt control register 10 ICR10 R/W 00000111B
0000BBHInterrupt control register 11 ICR11 R/W 00000111B
0000BCHInterrupt control register 12 ICR12 R/W 00000111B
0000BDHInterrupt control register 13 ICR13 R/W 00000111B
0000BEHInterrupt control register 14 ICR14 R/W 00000111B
0000BFHInterrupt control register 15 ICR15 R/W 00000111B
0000C0H
to
0000C3H
(Disabled)
0000C4HSerial mode register 1 SMR1 R/W, W
UART
(LIN/SCI) 1
00000000B
0000C5HSerial control register 1 SCR1 R/W, W 00000000B
0000C6HReception/transmission
data register 1
RDR1/
TDR1 R/W 00000000B
0000C7HSerial status register 1 SSR1 R/W, R 00001000B
0000C8HExtended communication
control register 1 ECCR1 R/W, R 000000XXB
0000C9HExtended status control register 1 ESCR1 R/W 00000100B
0000CAHBaud rate generator register 10 BGR10 R/W 00000000B
0000CBHBaud rate generator register 11 BGR11 R/W, R 00000000B
0000CCHLower watch timer control register WTCRL R/W
Real-time
watch timer
000XXXX0B
0000CDHMiddle watch timer control register WTCRM R/W 00000000B
0000CEHHigher watch timer control register WTCRH R/W XXXXXX00B
0000CFHSub clock control register PSCCR W Sub clock XXXX0000B
0000D0HInput capture control status 4/5 ICS45 R/W Input capture 4/5 00000000B
0000D1HInput capture edge register 4/5 ICE45 R/W, R XXXXXXXXB
0000D2HInput capture control status 6/7 ICS67 R/W Input capture 6/7 00000000B
0000D3HInput capture edge register 6/7 ICE67 R/W, R XXX0X0XXB
MB90920 Series
DS07-13750-3E 27
(Continued)
Address Register name Symbol Read/write Resource name Initial value
0000D4HLower timer control status register 2 TMCSR2L R/W 16-bit
reload timer 2
00000000B
0000D5HHigher timer control status register 2 TMCSR2H R/W XXX10000B
0000D6HLower timer control status register 3 TMCSR3L R/W 16-bit
reload timer 3
00000000B
0000D7HHigher timer control status register 3 TMCSR3H R/W XXX10000B
0000D8HLower sound control register 1 SGCRL1 R/W Sound generator 1 00000000B
0000D9HHigher sound control register 1 SGCRH1 R/W 0XXXX100B
0000DAHLower PPG3 control status register PCNTL3 R/W 16-bit PPG3 00000000B
0000DBHHigher PPG3 control status register PCNTH3 R/W 00000001B
0000DCHLower PPG4 control status register PCNTL4 R/W 16-bit PPG4 00000000B
0000DDHHigher PPG4 control status register PCNTH4 R/W 00000001B
0000DEHLower PPG5 control status register PCNTL5 R/W 16-bit PPG5 00000000B
0000DFHHigher PPG5 control status register PCNTH5 R/W 00000001B
0000E0HSerial mode register 2 SMR2 R/W, W
UART
(LIN/SCI) 2
00000000B
0000E1HSerial control register 2 SCR2 R/W, W 00000000B
0000E2HReception/transmission data register 2 RDR2/
TDR2 R/W 00000000B
0000E3HSerial status register 2 SSR2 R/W, R 00001000B
0000E4HExtended communication control
register 2 ECCR2 R/W, R 000000XXB
0000E5HExtended status control register 2 ESCR2 R/W 00000100B
0000E6HBaud rate generator register 20 BGR20 R/W 00000000B
0000E7HBaud rate generator register 21 BGR21 R/W, R 00000000B
0000E8HSerial mode register 3 SMR3 R/W, W
UART
(LIN/SCI) 3
00000000B
0000E9HSerial control register 3 SCR3 R/W, W 00000000B
0000EAHReception/transmission data register 3 RDR3/
TDR3 R/W 00000000B
0000EBHSerial status register 3 SSR3 R/W, R 00001000B
0000ECHExtended communication control
register 3 ECCR3 R/W, R 000000XXB
0000EDHExtended status control register 3 ESCR3 R/W 00000100B
0000EEHBaud rate generator register 30 BGR30 R/W 00000000B
0000EFHBaud rate generator register 31 BGR31 R/W, R 00000000B
001FF0HProgram address detection register 0 PADR0 R/W
Address match
detection
XXXXXXXXB
001FF1HProgram address detection register 1 PADR0 R/W XXXXXXXXB
001FF2HProgram address detection register 2 PADR0 R/W XXXXXXXXB
001FF3HProgram address detection register 3 PADR1 R/W XXXXXXXXB
001FF4HProgram address detection register 4 PADR1 R/W XXXXXXXXB
001FF5HProgram address detection register 5 PADR1 R/W XXXXXXXXB
MB90920 Series
28 DS07-13750-3E
(Continued)
Address Register name Symbol Read/write Resource name Initial value
003700H
to
0037FFH
Area reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
003800H
to
0038FFH
Area reserved for CAN Controller 3. Refer to “■ CAN CONTROLLERS”
003900H
to
00391FH
(Disabled)
003920HPPG0 down counter register PDCR0 R
16-bit PPG0
11111111B
003921H11111111B
003922HPPG0 cycle setting register PCSR0 W 11111111B
003923H11111111B
003924HPPG0 duty setting register PDUT0 W 16-bit PPG0
00000000B
003925H00000000B
003926HPPG0 output division setting register PPGDIV0 R/W, R 11111100B
003927H (Disabled)
003928HPPG1 down counter register PDCR1 R
16-bit PPG1
11111111B
003929H11111111B
00392AHPPG1 cycle setting register PCSR1 W 11111111B
00392BH11111111B
00392CHPPG1 duty setting register PDUT1 W 00000000B
00392DH00000000B
00392EHPPG1output division setting register PPGDIV1 R/W, R 11111100B
00392FH (Disabled)
003930HPPG2 down counter register PDCR2 R
16-bit PPG2
11111111B
003931H11111111B
003932HPPG2 cycle setting register PCSR2 W 11111111B
003933H11111111B
003934HPPG2 duty setting register PDUT2 W 00000000B
003935H00000000B
003936HPPG2 output division setting register PPGDIV2 R/W, R 11111100B
003937H
to
00393FH
(Disabled)
003940HInput capture register 4 IPCP4 R
Input capture 4/5
XXXXXXXXB
003941HXXXXXXXXB
003942HInput capture register 5 IPCP5 R XXXXXXXXB
003943HXXXXXXXXB
MB90920 Series
DS07-13750-3E 29
(Continued)
Address Register name Symbol Read/write Resource name Initial value
003944HInput capture register 6 IPCP6 R
Input capture 6/7
XXXXXXXXB
003945HXXXXXXXXB
003946HInput capture register 7 IPCP7 R XXXXXXXXB
003947HXXXXXXXXB
003948H
to
00394FH
(Disabled)
003950HMinute data register 2/Reload register 2 TMR2/
TMRLR2 R/W 16-bit reload timer
2
XXXXXXXXB
003951HXXXXXXXXB
003952HMinute data register 3/Reload register 3 TMR3/
TMRLR3 R/W 16-bit reload timer
3
XXXXXXXXB
003953HXXXXXXXXB
003954H
to
003957H
(Disabled)
003958H
Sub second data register WTBR R/W
Real time
watch timer
XXXXXXXXB
003959HXXXXXXXXB
00395AHXXXXXXXXB
00395BHSecond data register WTSR R/W XX000000B
00395CHMinute data register WTMR R/W XX000000B
00395DHHour data register WTHR R/W XXX00000B
00395EHDay data register WTDR R/W 00X00001B
00395FH (Disabled)
003960H
LCD display RAM VRAM R/W
LCD
controller/
driver
XXXXXXXXB
003961HXXXXXXXXB
003962HXXXXXXXXB
003963HXXXXXXXXB
003964HXXXXXXXXB
003965HXXXXXXXXB
003966HXXXXXXXXB
003967HXXXXXXXXB
003968HXXXXXXXXB
003969HXXXXXXXXB
00396AHXXXXXXXXB
00396BHXXXXXXXXB
00396CHXXXXXXXXB
00396DHXXXXXXXXB
00396EHXXXXXXXXB
00396FHXXXXXXXXB
MB90920 Series
30 DS07-13750-3E
(Continued)
Address Register name Symbol Read/write Resource name Initial value
003970HClock supervisor control register CSVCR R, R/W Clock supervisor 00011100B
003971H
to
003973H
(Disabled)
003974HFrequency data register 1 SGFR1 R/W
Sound generator 1
XXXXXXXXB
003975HAmplitude data register 1 SGAR1 R/W 00000000B
003976HDecrement grade register 1 SGDR1 R/W XXXXXXXXB
003977HTone count register 1 SGTR1 R/W XXXXXXXXB
003978H
to
00397FH
(Disabled)
003980HPWM1 compare register 0 PWC10 R/W
Stepping motor
controller 0
XXXXXXXXB
003981HXXXXXXXXB
003982HPWM2 compare register 0 PWC20 R/W XXXXXXXXB
003983HXXXXXXXXB
003984HPWM1 select register 0 PWS10 R/W 00000000B
003985HPWM2 select register 0 PWS20 R/W X0000000B
003986H,
003987H (Disabled)
003988HPWM1 compare register 1 PWC11 R/W
Stepping motor
controller 1
XXXXXXXXB
003989HXXXXXXXXB
00398AHPWM2 compare register 1 PWC21 R/W XXXXXXXXB
00398BHXXXXXXXXB
00398CHPWM1 select register 1 PWS11 R/W 00000000B
00398DHPWM2 select register 1 PWS21 R/W X0000000B
00398EH,
00398FH (Disabled)
003990HPWM1 compare register 2 PWC12 R/W
Stepping motor
controller 2
XXXXXXXXB
003991HXXXXXXXXB
003992HPWM2 compare register 2 PWC22 R/W XXXXXXXXB
003993HXXXXXXXXB
003994HPWM1 select register 2 PWS12 R/W 00000000B
003995HPWM2 select register 2 PWS22 R/W X0000000B
003996H,
003997H (Disabled)
MB90920 Series
DS07-13750-3E 31
(Continued)
Address Register name Symbol Read/write Resource name Initial value
003998HPWM1 compare register 3 PWC13 R/W
Stepping motor
controller 3
XXXXXXXXB
003999HXXXXXXXXB
00399AHPWM2 compare register 3 PWC23 R/W XXXXXXXXB
00399BHXXXXXXXXB
00399CHPWM1 select register 3 PWS13 R/W 00000000B
00399DHPWM2 select register 3 PWS23 R/W X0000000B
00399EH
to
0039A5H
(Disabled)
0039A6HFlash write control register 0 FWR0 R/W Flash I/F 00000000B
0039A7HFlash write control register 1 FWR1 00000000B
0039A8H
to
0039BFH
(Disabled)
0039C0H
to
0039DFH
Area reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
0039E0H
to
0039FFH
Area reserved for CAN Controller 3. Refer to “■ CAN CONTROLLERS”
003A00H
to
003AFFH
Area reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
003B00H
to
003BFFH
Area reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
003C00H
to
003CFFH
Area reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
003D00H
to
003DFFH
Area reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
003E00H
to
003EFFH
Area reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
003F00H
to
003FFFH
Area reserved for CAN Controller 3. Refer to “■ CAN CONTROLLERS”
MB90920 Series
32 DS07-13750-3E
■CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmission/reception message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers(1)
Address Register Abbreviation Access Initial Value
CAN0 CAN1 CAN2 CAN3
003C00H003D00H003E00H003F00HControl status register CSR R/W, R 00---000B
0----0-1B
003C01H003D01H003E01H003F01H
003C02H003D02H003E02H003F02HLast event indicator
register LEIR R/W --------B
000-0000B
003C03H003D03H003E03H003F03H
003C04H003D04H003E04H003F04HRX/TX error counter RTEC R 00000000B
00000000B
003C05H003D05H003E05H003F05H
003C06H003D06H003E06H003F06HBit timing register BTR R/W -1111111B
11111111B
003C07H003D07H003E07H003F07H
MB90920 Series
DS07-13750-3E 33
List of Control Registers(2)
Address Register Abbre-
viation Access Initial Value
CAN0 CAN1 CAN2 CAN3
000040H000070H0039C0H0039D0HMessage buffer valid register BVALR R/W 00000000B
00000000B
000041H000071H0039C1H0039D1H
000042H000072H0039C2H0039D2HTransmit request register TREQR R/W 00000000B
00000000B
000043H000073H0039C3H0039D3H
000044H000074H0039C4H0039D4HTransmit cancel register TCANR W 00000000B
00000000B
000045H000075H0039C5H0039D5H
000046H000076H0039C6H0039D6HTransmit complete register TCR R/W 00000000B
00000000B
000047H000077H0039C7H0039D7H
000048H000078H0039C8H0039D8HReceive complete register RCR R/W 00000000B
00000000B
000049H000079H0039C9H0039D9H
00004AH00007AH0039CAH0039DAHRemote request receive
register RRTRR R/W 00000000B
00000000B
00004BH00007BH0039CBH0039DBH
00004CH00007CH0039CCH0039DCHReceive overrun register ROVRR R/W 00000000B
00000000B
00004DH00007DH0039CDH0039DDH
00004EH00007EH0039CEH0039DEHReceive interrupt enable
register RIER R/W 00000000B
00000000B
00004FH00007FH0039CFH0039DFH
003C08H003D08H003E08H003F08HIDE register IDER R/W XXXXXXXXB
003C09H003D09H003E09H003F09HXXXXXXXXB
003C0AH003D0AH003E0AH003F0AHTransmit RTR register TRTRR R/W 00000000B
003C0BH003D0BH003E0BH003F0BH00000000B
003C0CH003D0CH003E0CH003F0CHRemote frame receive wait
register RFWTR R/W XXXXXXXXB
XXXXXXXXB
003C0DH003D0DH003E0DH003F0DH
003C0EH003D0EH003E0EH003F0EHTransmit interrupt enable
register TIER R/W 00000000B
00000000B
003C0FH003D0FH003E0FH003F0FH
003C10H003D10H003E10H003F10H
Acceptance mask select
register AMSR R/W
XXXXXXXXB
XXXXXXXXB
003C11H003D11H003E11H003F11H
003C12H003D12H003E12H003F12HXXXXXXXXB
XXXXXXXXB
003C13H003D13H003E13H003F13H
003C14H003D14H003E14H003F14H
Acceptance mask register 0 AMR0 R/W
XXXXXXXXB
XXXXXXXXB
003C15H003D15H003E15H003F15H
003C16H003D16H003E16H003F16HXXXXX---B
XXXXXXXXB
003C17H003D17H003E17H003F17H
003C18H003D18H003E18H003F18H
Acceptance mask register 1 AMR1 R/W
XXXXXXXXB
XXXXXXXXB
003C19H003D19H003E19H003F19H
003C1AH003D1AH003E1AH003F1AHXXXXX---B
XXXXXXXXB
003C1BH003D1BH003E1BH003F1BH
MB90920 Series
34 DS07-13750-3E
List of Message Buffers (ID Registers)
(Continued)
Address Register Abbre-
viation Access Initial Value
CAN0 CAN1 CAN2 CAN3
003A00H
to
003A1FH
003B00H
to
003B1FH
003700H
to
00371FH
003800H
to
00381FH
General-purpose RAM ⎯R/W
XXXXXXXXB
to
XXXXXXXXB
003A20H003B20H003720H003820H
ID register 0 IDR0 R/W
XXXXXXXXB
XXXXXXXXB
003A21H003B21H003721H003821H
003A22H003B22H003722H003822HXXXXX---B
XXXXXXXXB
003A23H003B23H003723H003823H
003A24H003B24H003724H003824H
ID register 1 IDR1 R/W
XXXXXXXXB
XXXXXXXXB
003A25H003B25H003725H003825H
003A26H003B26H003726H003826HXXXXX---B
XXXXXXXXB
003A27H003B27H003727H003827H
003A28H003B28H003728H003828H
ID register 2 IDR2 R/W
XXXXXXXXB
XXXXXXXXB
003A29H003B29H003729H003829H
003A2AH003B2AH00372AH00382AHXXXXX---B
XXXXXXXXB
003A2BH003B2BH00372BH00382BH
003A2CH003B2CH00372CH00382CH
ID register 3 IDR3 R/W
XXXXXXXXB
XXXXXXXXB
003A2DH003B2DH00372DH00382DH
003A2EH003B2EH00372EH00382EHXXXXX---B
XXXXXXXXB
003A2FH003B2FH00372FH00382FH
003A30H003B30H003730H003830H
ID register 4 IDR4 R/W
XXXXXXXXB
XXXXXXXXB
003A31H003B31H003731H003831H
003A32H003B32H003732H003832HXXXXX---B
XXXXXXXXB
003A33H003B33H003733H003833H
003A34H003B34H003734H003834H
ID register 5 IDR5 R/W
XXXXXXXXB
XXXXXXXXB
003A35H003B35H003735H003835H
003A36H003B36H003736H003836HXXXXX---B
XXXXXXXXB
003A37H003B37H003737H003837H
003A38H003B38H003738H003838H
ID register 6 IDR6 R/W
XXXXXXXXB
XXXXXXXXB
003A39H003B39H003739H003839H
003A3AH003B3AH00373AH00383AHXXXXX---B
XXXXXXXXB
003A3BH003B3BH00373BH00383BH
003A3CH003B3CH00373CH00383CH
ID register 7 IDR7 R/W
XXXXXXXXB
XXXXXXXXB
003A3DH003B3DH00373DH00383DH
003A3EH003B3EH00373EH00383EHXXXXX---B
XXXXXXXXB
003A3FH003B3FH00373FH00383FH
MB90920 Series
DS07-13750-3E 35
(Continued)
Address Register Abbre-
viation Access Initial Value
CAN0 CAN1 CAN2 CAN3
003A40H003B40H003740H003840H
ID register 8 IDR8 R/W
XXXXXXXXB
XXXXXXXXB
003A41H003B41H003741H003841H
003A42H003B42H003742H003842HXXXXX---B
XXXXXXXXB
003A43H003B43H003743H003843H
003A44H003B44H003744H003844H
ID register 9 IDR9 R/W
XXXXXXXXB
XXXXXXXXB
003A45H003B45H003745H003845H
003A46H003B46H003746H003846HXXXXX---B
XXXXXXXXB
003A47H003B47H003747H003847H
003A48H003B48H003748H003848H
ID register 10 IDR10 R/W
XXXXXXXXB
XXXXXXXXB
003A49H003B49H003749H003849H
003A4AH003B4AH00374AH00384AHXXXXX---B
XXXXXXXXB
003A4BH003B4BH00374BH00384BH
003A4CH003B4CH00374CH00384CH
ID register 11 IDR11 R/W
XXXXXXXXB
XXXXXXXXB
003A4DH003B4DH00374DH00384DH
003A4EH003B4EH00374EH00384EHXXXXX---B
XXXXXXXXB
003A4FH003B4FH00374FH00384FH
003A50H003B50H003750H003850H
ID register 12 IDR12 R/W
XXXXXXXXB
XXXXXXXXB
003A51H003B51H003751H003851H
003A52H003B52H003752H003852HXXXXX---B
XXXXXXXXB
003A53H003B53H003753H003853H
003A54H003B54H003754H003854H
ID register 13 IDR13 R/W
XXXXXXXXB
XXXXXXXXB
003A55H003B55H003755H003855H
003A56H003B56H003756H003856HXXXXX---B
XXXXXXXXB
003A57H003B57H003757H003857H
003A58H003B58H003758H003858H
ID register 14 IDR14 R/W
XXXXXXXXB
XXXXXXXXB
003A59H003B59H003759H003859H
003A5AH003B5AH00375AH00385AHXXXXX---B
XXXXXXXXB
003A5BH003B5BH00375BH00385BH
003A5CH003B5CH00375CH00385CH
ID register 15 IDR15 R/W
XXXXXXXXB
XXXXXXXXB
003A5DH003B5DH00375DH00385DH
003A5EH003B5EH00375EH00385EHXXXXX---B
XXXXXXXXB
003A5FH003B5FH00375FH00385FH
MB90920 Series
36 DS07-13750-3E
List of Message Buffers (DLC Registers)
Address Register Abbrevia-
tion Access Initial Value
CAN0 CAN1 CAN2 CAN3
003A60H003B60H003760H003860HDLC register 0 DLCR0 R/W ----XXXXB
003A61H003B61H003761H003861H
003A62H003B62H003762H003862HDLC register 1 DLCR1 R/W ----XXXXB
003A63H003B63H003763H003863H
003A64H003B64H003764H003864HDLC register 2 DLCR2 R/W ----XXXXB
003A65H003B65H003765H003865H
003A66H003B66H003766H003866HDLC register 3 DLCR3 R/W ----XXXXB
003A67H003B67H003767H003867H
003A68H003B68H003768H003868HDLC register 4 DLCR4 R/W ----XXXXB
003A69H003B69H003769H003869H
003A6AH003B6AH00376AH00386AHDLC register 5 DLCR5 R/W ----XXXXB
003A6BH003B6BH00376BH00386BH
003A6CH003B6CH00376CH00386CHDLC register 6 DLCR6 R/W ----XXXXB
003A6DH003B6DH00376DH00386DH
003A6EH003B6EH00376EH00386EHDLC register 7 DLCR7 R/W ----XXXXB
003A6FH003B6FH00376FH00386FH
003A70H003B70H003770H003870HDLC register 8 DLCR8 R/W ----XXXXB
003A71H003B71H003771H003871H
003A72H003B72H003772H003872HDLC register 9 DLCR9 R/W ----XXXXB
003A73H003B73H003773H003873H
003A74H003B74H003774H003874HDLC register 10 DLCR10 R/W ----XXXXB
003A75H003B75H003775H003875H
003A76H003B76H003776H003876HDLC register 11 DLCR11 R/W ----XXXXB
003A77H003B77H003777H003877H
003A78H003B78H003778H003878HDLC register 12 DLCR12 R/W ----XXXXB
003A79H003B79H003779H003879H
003A7AH003B7AH00377AH00387AHDLC register 13 DLCR13 R/W ----XXXXB
003A7BH003B7BH00377BH00387BH
003A7CH003B7CH00377CH00387CHDLC register 14 DLCR14 R/W ----XXXXB
003A7DH003B7DH00377DH00387DH
003A7EH003B7EH00377EH00387EHDLC register 15 DLCR15 R/W ----XXXXB
003A7FH003B7FH00377FH00387FH
MB90920 Series
DS07-13750-3E 37
List of Message Buffers (Data register)
Address Register Abbre-
viation Access Initial Value
CAN0 CAN1 CAN2 CAN3
003A80H
to
003A87H
003B80H
to
003B87H
003780H
to
003787H
003880H
to
003887H
Data register 0 (8 bytes) DTR0 R/W
XXXXXXXXB
to
XXXXXXXXB
003A88H
to
003A8FH
003B88H
to
003B8FH
003788H
to
00378FH
003888H
to
00388FH
Data register 1 (8 bytes) DTR1 R/W
XXXXXXXXB
to
XXXXXXXXB
003A90H
to
003A97H
003B90H
to
003B97H
003790H
to
003797H
003890H
to
003897H
Data register 2 (8 bytes) DTR2 R/W
XXXXXXXXB
to
XXXXXXXXB
003A98H
to
003A9FH
003B98H
to
003B9FH
003798H
to
00379FH
003898H
to
00389FH
Data register 3 (8 bytes) DTR3 R/W
XXXXXXXXB
to
XXXXXXXXB
003AA0H
to
003AA7H
003BA0H
to
003BA7H
0037A0H
to
0037A7H
0038A0H
to
0038A7H
Data register 4 (8 bytes) DTR4 R/W
XXXXXXXXB
to
XXXXXXXXB
003AA8H
to
003AAFH
003BA8H
to
003BAFH
0037A8H
to
0037AFH
0038A8H
to
0038AFH
Data register 5 (8 bytes) DTR5 R/W
XXXXXXXXB
to
XXXXXXXXB
003AB0H
to
003AB7H
003BB0H
to
003BB7H
0037B0H
to
0037B7H
0038B0H
to
0038B7H
Data register 6 (8 bytes) DTR6 R/W
XXXXXXXXB
to
XXXXXXXXB
003AB8H
to
003ABFH
003BB8H
to
003BBFH
0037B8H
to
0037BFH
0038B8H
to
0038BFH
Data register 7 (8 bytes) DTR7 R/W
XXXXXXXXB
to
XXXXXXXXB
003AC0H
to
003AC7H
003BC0H
to
003BC7H
0037C0H
to
0037C7H
0038C0H
to
0038C7H
Data register 8 (8 bytes) DTR8 R/W
XXXXXXXXB
to
XXXXXXXXB
003AC8H
to
003ACFH
003BC8H
to
003BCFH
0037C8H
to
0037CFH
0038C8H
to
0038CFH
Data register 9 (8 bytes) DTR9 R/W
XXXXXXXXB
to
XXXXXXXXB
003AD0H
to
003AD7H
003BD0H
to
003BD7H
0037D0H
to
0037D7H
0038D0H
to
0038D7H
Data register 10 (8 bytes) DTR10 R/W
XXXXXXXXB
to
XXXXXXXXB
003AD8H
to
003ADFH
003BD8H
to
003BDFH
0037D8H
to
0037DFH
0038D8H
to
0038DFH
Data register 11 (8 bytes) DTR11 R/W
XXXXXXXXB
to
XXXXXXXXB
003AE0H
to
003AE7H
003BE0H
to
003BE7H
0037E0H
to
0037E7H
0038E0H
to
0038E7H
Data register 12 (8 bytes) DTR12 R/W
XXXXXXXXB
to
XXXXXXXXB
003AE8H
to
003AEFH
003BE8H
to
003BEFH
0037E8H
to
0037EFH
0038E8H
to
0038EFH
Data register 13 (8 bytes) DTR13 R/W
XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
003AF7H
003BF0H
to
003BF7H
0037F0H
to
0037F7H
0038F0H
to
0038F7H
Data register 14 (8 bytes) DTR14 R/W
XXXXXXXXB
to
XXXXXXXXB
003AF8H
to
003AFFH
003BF8H
to
003BFFH
0037F8H
to
0037FFH
0038F8H
to
0038FFH
Data register 15 (8 bytes) DTR15 R/W
XXXXXXXXB
to
XXXXXXXXB
MB90920 Series
38 DS07-13750-3E
■INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
(Continued)
Interrupt source EI2OS
corresponding
Interrupt vector Interrupt control
register Priority
*2
Number Address ICR Address
Reset × #08 08HFFFFDCH⎯⎯High
INT9 instruction × #09 09HFFFFD8H⎯⎯
Exception processing × #10 0AHFFFFD4H⎯⎯
CAN0 received/CAN2 received × #11 0BHFFFFD0H
ICR00 0000B0H*1
CAN0 transmitted/node status/
CAN2 transmitted/node status × #12 0CHFFFFCCH
CAN1 received/CAN3 received × #13 0DHFFFFC8H
ICR01 0000B1H*1
CAN1 transmitted/node status/
CAN3 transmitted/node status/SIO × #14 0EHFFFFC4H
Input capture 0 #15 0FHFFFFC0H
ICR02 0000B2H*1
DTP/ external interrupt
- ch.0/ch.1 detected #16 10HFFFFBCH
Reload timer 0 #17 11HFFFFB8HICR03 0000B3H*1
Reload timer 2 #18 12HFFFFB4H
Input capture 1 #19 13HFFFFB0H
ICR04 0000B4H*1
DTP/ external interrupt
- ch.2/ch.3 detected #20 14HFFFFACH
Input capture 2 #21 15HFFFFA8HICR05 0000B5H*1
Reload timer 3 #22 16HFFFFA4H
Input capture 3/4/5/6/7 #23 17HFFFFA0H
ICR06 0000B6H*1
DTP/ external interrupt
- ch.4/ ch.5 detected UART3 RX #24 18HFFFF9CH
PPG timer 0 #25 19HFFFF98H
ICR07 0000B7H*1
DTP/ external interrupt
- ch.6/ ch.7 detected UART3 TX #26 1AHFFFF94H
PPG timer 1 #27 1BHFFFF90HICR08 0000B8H*1
Reload timer 1 #28 1CHFFFF8CH
PPG timer 2/3/4/5 #29 1DHFFFF88H
ICR09 0000B9H*1
Real time watch timer
watch timer (sub clock) × #30 1EHFFFF84H
Free-run timer overflow/clear × #31 1FHFFFF80HICR10 0000BAH *1
A/D converter conversion complete #32 20HFFFF7CH
Sound generator 0/1 × #33 21HFFFF78HICR11 0000BBH*1
Time-base timer × #34 22HFFFF74H
UART2 RX #35 23HFFFF70HICR12 0000BCH*1
UART2 TX #36 24HFFFF6CHLow
MB90920 Series
DS07-13750-3E 39
(Continued)
: Usable, and has expanded intelligent I/O services (EI2OS) stop function
: Usable
: Usable when interrupt sources sharing ICR are not in use
× : Unusable
*1 : • Peripheral functions that share the ICR register have the same interrupt level.
• If the expanded intelligent I/O service (EI2OS) is used with peripheral functions that share the ICR register,
only one of the peripheral functions that share the register can be used.
• When the expanded intelligent I/O service (EI2OS) is specified for one of the peripheral functions that shares
the ICR register, interrupts cannot be used from the other peripheral functions that share the register.
*2 : Priority applies when interrupts of the same level are generated.
Interrupt source EI2OS
corresponding
Interrupt vector Interrupt control
register Priority
*2
Number Address ICR Address
UART 1 RX #37 25HFFFF68HICR13 0000BDH*1High
UART 1 TX #38 26HFFFF64H
UART 0 RX #39 27HFFFF60HICR14 0000BEH*1
UART 0 TX #40 28HFFFF5CH
Flash memory status × #41 29HFFFF58HICR15 0000BFH*1
Delay interrupt generator module × #42 2AHFFFF54HLow
MB90920 Series
40 DS07-13750-3E
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH must not exceed VCC, and AVRH must not exceed AVCC.
When using an evaluation product, DVCC must not exceed VCC (however, DVCC can be set to a higher voltage
than VCC when using a Flash memory product).
*3 : If the input current or the maximum input current is limited using external components, ICLAMP is the applicable
rating instead of VI.
*4 : Maximum output current is defined as the peak value of current through any one of the corresponding pins.
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*2
AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*2
DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*2
Input voltage*1VIVSS − 0.3 VCC + 0.3 V *3
Output voltage*1VOVSS − 0.3 VCC + 0.3 V
Maximum clamp current ICLAMP − 4 + 4mA*7
Total maximum clamp current Σ| ICLAMP |⎯40 mA *7
“L” level maximum
output current*4
IOL1 ⎯15 mA Except P70 to P77 and P80 to P87
IOL2 ⎯40 mA P70 to P77 and P80 to P87
“L” level average output
current*5
IOLAV1 ⎯4 mA Except P70 to P77 and P80 to P87
IOLAV2 ⎯30 mA P70 to P77 and P80 to P87
“L” level maximum
total output current
ΣIOL1 ⎯100 mA Except P70 to P77 and P80 to P87
ΣIOL2 ⎯330 mA P70 to P77 and P80 to P87
“L” level average total
output current
ΣIOLAV1 ⎯50 mA Except P70 to P77 and P80 to P87
ΣIOLAV2 ⎯250 mA P70 to P77 and P80 to P87
“H” level maximum
output current
IOH1*4⎯−15 mA Except P70 to P77 and P80 to P87
IOH2*4⎯−40 mA P70 to P77 and P80 to P87
“H” level average
output current
IOHAV1*5⎯−4 mA Except P70 to P77 and P80 to P87
IOHAV2*5⎯−30 mA P70 to P77 and P80 to P87
“H” level maximum
total output current
ΣIOH1 ⎯−100 mA Except P70 to P77 and P80 to P87
ΣIOH2 ⎯−330 mA P70 to P77 and P80 to P87
“H” level average total
output current
ΣIOHAV1*6⎯−50 mA Except P70 to P77 and P80 to P87
ΣIOHAV2*6⎯−250 mA P70 to P77 and P80 to P87
Power consumption PD⎯625 mW
Operating temperature TA − 40 + 105 °C
Storage temperature TSTG − 55 + 150 °C
MB90920 Series
DS07-13750-3E 41
(Continued)
*5 : Average output current is defined as the average value of the current flowing through any one of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “operating factor”.
*6 : Average total output current is defined as the average value of the current flowing through all of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “ operating factor”.
*7 : • Applicable to pins: P10 to P15,P50 to P57,P60 to P67,P70 to P77,P80 to P87,PC0 to PC7,PD0 to PD6,
PE0 to PE2
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the
microcontroller may partially malfunction on power supplied through the +B signal pin.
• Note that if the +B input is applied during power-on, the power supply voltage may reach a level such that
the power-on reset does not function due to the power supplied from the +B signal.
• Care must be taken not to leave +B input pins open.
• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept
+B signal inputs.
• Sample recommended circuit :
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
+B input (0 V to 16 V)
Limiting
resistance
Protective diode
• Input/output equivalent circuit
MB90920 Series
42 DS07-13750-3E
2. Recommended Operating Conditions
(VSS = DVSS = AVSS = 0.0 V)
* : Refer to the following diagram for details on the connection of the smoothing capacitor CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply
voltage
VCC
AVCC
DVCC
4.0 5.5 V The low voltage detection reset operates when the power
supply voltage reaches 4.2 V ± 0.2 V.
4.4 5.5 V
Maintain stop operation status
The low voltage detection reset operates when the power
supply voltage reaches 4.2 V ± 0.2 V.
Smoothing
capacitor* CS0.1 1.0 µF
Use a ceramic capacitor or other capacitor of equivalent
frequency characteristics. Use a capacitor with a capaci-
tance greater than this capacitor as the bypass capacitor for
the VCC pin.
Operating
temperature TA − 40 + 105 °C
C
CSVSS DVSS AVSS
• C pin connection diagram
MB90920 Series
DS07-13750-3E 43
3. DC Characteristics
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
(Continued)
Parameter Symbol Pin
name Conditions Value Unit Remarks
Min Typ Max
“H” level
input voltage
VIHA ⎯⎯0.8 VCC ⎯⎯V
Pin inputs if
Automotive input
levels are selected
VIHS ⎯⎯0.8 VCC ⎯⎯V
Pin inputs if CMOS
hysteresis input
levels are selected
VIHC ⎯⎯0.7 VCC ⎯⎯VRST input pin
(CMOS hysteresis)
“L” level
input voltage
VILA ⎯⎯⎯⎯0.5 VCC V
Pin inputs if
Automotive input
levels are selected
VILS ⎯⎯⎯⎯0.2 VCC V
Pin inputs if CMOS
hysteresis input
levels are selected
VILR ⎯⎯⎯
⎯0.3 VCC VRST input pin
(CMOS hysteresis)
Power supply
current*
ICC
VCC
Maximum operating
frequency FCP = 32 MHz,
normal operation
⎯35 45 mA
Maximum operating
frequency FCP = 32 MHz,
writing Flash memory
⎯55 65 mA
ICCS
Operating frequency
FCP = 32 MHz,
sleep mode
⎯13 20 mA
ICTS
Operating frequency
FCP = 2 MHz,
time-base timer mode
⎯0.6 1.0 mA
ICTSPLL
Operating frequency
FCP = 32 MHz,
PLL timer mode,
External frequency = 4 MHz
⎯2.5 4 mA
ICCL
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
sub clock operation
⎯120 270 µA
ICCLS
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
sub sleep operation
⎯100 200 µA
ICCT
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
watch mode
⎯90 180 µA
ICCH TA = + 25 °C, stop mode ⎯80 170 µA
MB90920 Series
44 DS07-13750-3E
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
(Continued)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
Input leakage
current IIL All input pins
VCC = DVCC = AVCC =
5.5 V,
VSS < VI < VCC
⎯⎯10 µA
Input
capacitance 1 CIN1
All pins except
VCC, VSS,
DVCC, DVSS,
AVCC, AVSS,
C,
P70 to P77,
P80 to P87
⎯⎯⎯15 pF
Input capacitance 2 CIN2 P70 to P77,
P80 to P87 ⎯⎯⎯45 pF
Pull-up resistance RUP RST ⎯25 50 100 kΩ
Pull-down
resistance RDOWN MD2 ⎯⎯⎯100 kΩ
Excluding
Flash
memory
product
General-purpose
output “H” voltage VOH1
All pins except
P70 to P77,
P80 to P87
VCC = 4.5 V,
IOH = −4.0 mA VCC − 0.5 ⎯⎯V
Stepping motor
output “H” voltage VOH2 P70 to P77,
P80 to P87
VCC = 4.5 V,
IOH = −30.0 mA VCC − 0.5 ⎯⎯V
General-purpose
output “L” voltage VOL1
All pins except
P70 to P77,
P80 to P87
VCC = 4.5 V,
IOL = 4.0 mA ⎯⎯0.4 V
Stepping motor
output “L” voltage VOL2 P70 to P77,
P80 to P87
VCC = 4.5 V,
IOL = 30.0 mA ⎯⎯0.55 V
Stepping motor
output phase
variation “H”
∆VOH
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n = 0 to 3
VCC = 4.5 V,
IOH = −30.0 mA,
maximum deviation
VOH2
⎯⎯90 mV
Stepping motor
output phase
variation “L”
∆VOL
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n = 0 to 3
VCC = 4.5 V,
IOL = 30.0 mA,
maximum deviation
VOH2
⎯⎯90 mV
LCD internal
divider resistance RLCD
Between V0
and V1,
Between V1
and V2,
Between V2
and V3
⎯
50 100 200 kΩEvaluation
product
8.75 12.5 17.0 kΩ
Flash
memory
product
MB90920 Series
DS07-13750-3E 45
(Continued)
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
* : Power supply current values assume an external clock supplied to the X1 pin and X1A pin. Users must be aware
that power supply current levels differ depending on whether an external clock or oscillator is used.
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
LCDC leakage
current ILCDC
V0 to V3,
COMm
(m = 0 to 3) ,
SEGn,
(n = 00 to 31)
⎯⎯⎯5.0 µA
MB90920 Series
46 DS07-13750-3E
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Condi-
tions
Value Unit Remarks
Min Typ Max
Clock frequency FCX0, X1
⎯
3⎯16 MHz
1/2 (PLL stopped)
When using the
oscillator circuit
3⎯32 MHz
1/2 (PLL stopped)
When using an external
clock
4⎯32 MHz PLL multiplied by 1
3⎯16 MHz PLL multiplied by 2
3⎯10.7 MHz PLL multiplied by 3
3⎯8 MHz PLL multiplied by 4
3⎯5.33 MHz PLL multiplied by 6
3⎯4 MHz PLL multiplied by 8
FLC X0A, X1A ⎯32.768 ⎯kHz
Clock cycle time tCYL X0, X1 62.5 ⎯333 ns When using an
oscillator
31.25 ⎯333 ns External clock input
tLCYL X0A, X1A ⎯30.5 ⎯µs
Input clock pulse
width
PWH, PWL X0 5 ⎯⎯ns Use duty ratio of
50% ± 3% as a guideline
PWLH, PWLL X0A ⎯15.2 ⎯µs
Input clock
rise and fall time tcr, tcf X0 ⎯⎯ 5ns
When using an external
clock signal
Internal operating
clock frequency
FCP ⎯1.5 ⎯32 MHz Using main clock
(PLL clock)
FLCP ⎯⎯8.192 ⎯kHz Using sub clock
Internal operating
clock cycle time
tCP ⎯31.25 — 666 ns Using main clock
(PLL clock)
tLCP ⎯⎯122.1 ⎯µs Using sub clock
MB90920 Series
DS07-13750-3E 47
X0
X1
tcf tcr
0.8 V
CC
0.2 V
CC
P
WL
t
CYL
P
WH
X0A
X1A
t
LCYL
tcf tcr
0.8 V
CC
0.1 V
CC
P
WLH
P
WLL
• X0, X1 clock timing
• X0A, X1A clock timing
MB90920 Series
48 DS07-13750-3E
(Continued)
• Guaranteed PLL Operation Range
Notes : • For PLL 1 × only, use with tcp = 4 MHz or greater.
• Refer to “5. A/D Converter (1) Electrical Characteristics” for details on the A/D converter operating
frequency.
324
1.5
5.5
4.0
Internal operating clock frequency vs. Power supply voltage
Range of warranted PLL operation
Normal operating range
Internal clock fCP (MHz)
Power supply voltage VCC (V)
MB90920 Series
DS07-13750-3E 49
(Continued)
*1 : When the PLL multiplier is × 1, × 2, × 3 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, set
DIV2 bit = “1”*4, CS2 bit = “1” in the PSCCR register.
[Example] When using a base oscillator frequency of 24 MHz at PLL × 1 :
CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4 ,CS2 bit = “1”
[Example] When using a base oscillator frequency of 6 MHz at PLL × 3 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4 , CS2 bit = “1”
*2 : When the PLL multiplier is × 2 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, the following
settings are also supported.
PLL × 2 : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “0”
PLL × 4 : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “0”
*3 : When the PLL multiplier is set to × 6 or × 8 set “DIV2 bit = “0”*4 CS2 bit = “1”
and “PLL2 bit = 1” in the PSCCR register.
[Example] When using a base oscillator frequency of 4 MHz at PLL × 6 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PLLOS register : DIV2 bit = “0”*4 ,CS2 bit = “1”
[Example] When using a base oscillator frequency of 3 MHz at PLL × 8 :
CKSCR register : CS1 bit = “1”, CS0 bit = “1”
PLLOS register : DIV2 bit = “0”*4 ,CS2 bit = “1”
*4 : The DIV2 bit is assigned to bit 9 of the PSCCR register and the CS2 bit is assigned to bit 8 of the PSCCR
register. Both bits have a default value of “0”.
32
No multiplier
25
24
20
18
16
12
9
8
6
4
1.5
356 810 12.5 16 20 25 32
4
x 3*
1
x 6*
3
x 4
*
1,
*
2
x 2*
1,
*
2
x 1*
1
x 8*
3
Base oscillator frequency vs. Internal operating clock frequency
Base oscillator clock FCP (MHz)
Internal clock fCP (MHz)
MB90920 Series
50 DS07-13750-3E
(2) Reset input
(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
*: The oscillation time of the oscillator is the time taken to reach 90% of the amplitude. The oscillation time of a
crystal oscillator is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between
hundreds of µs and several ms. The oscillation time of an external clock is 0 ms.
Note : tCP is the internal operating clock cycle time. (Unit : ns)
Parameter Symbol Pin name Value Unit Remarks
Min Max
Reset input time tRSTL RST
500 ⎯ns During normal
operation
Oscillator oscillation time* + 16 tCP ⎯ms
In stop mode,
sub clock mode,
sub sleep mode,
and watch mode
100 ⎯µsIn time-base timer
mode
RST
X0
16 tCP
t
RSTL
0.2 Vcc 0.2 Vcc
Internal
operating
clock
Internal
reset
90 % of
amplitude
Oscillator
oscillation time
Oscillation stabilization wait time
Execution of the instructions
• In stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
0.2 VCC
tRSTL
0.2 VCC
• During normal operation
MB90920 Series
DS07-13750-3E 51
(3) Power-on reset
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Symbol Pin
name Conditions Value Unit Remarks
Min Max
Power supply rise time tR
VCC ⎯
0.05 30 ms
Power off time tOFF 1⎯ms Waiting time until
power-on
VCC
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
Note : Extreme variations in power supply voltage may trigger a power-on reset. When the power
supply voltage is changed during operation, it is recommended that increases in the voltage
smoothed out as shown in the following diagram. The PLL clock of the device should not be
in use when varying the voltage. However, the PLL clock may continue to be used if the rate
of the voltage drop is 1 V/s or less.
0 V
VCC
VSS
5.0 V
RAM data hold
It is recommended that rises
in voltage have a slope of
50 mV/ms or less
MB90920 Series
52 DS07-13750-3E
(4) UART0/1/2/3 (LIN/SCI)
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90920 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↓ → SOT delay time tSLOVI SCK0 to SCK3,
SOT0 to SOT3 − 50 + 50 ns
Valid SIN → SCK ↑tIVSHI SCK0 to SCK3,
SIN0 to SIN3
tCP + 80 ⎯ns
SCK ↑ → valid SIN hold time tSHIXI 0⎯ns
Serial clock “L” pulse width tSLSH SCK0 to SCK3
External shift clock
mode output pin
CL = 80 pF + 1TTL
3 tCP − tR⎯ns
Serial clock “H” pulse width tSHSL tCP + 10 ⎯ns
SCK ↓ → SOT delay time tSLOVE SCK0 to SCK3,
SOT0 to SOT3 ⎯2 tCP + 60 ns
Valid SIN → SCK ↑tIVSHE SCK0 to SCK3,
SIN0 to SIN3
30 ⎯ns
SCK ↑ → valid SIN hold time tSHIXE tCP + 30 ⎯ns
SCK ↓ time tFSCK0 to SCK3 ⎯10 ns
SCK ↑ time tR⎯10 ns
MB90920 Series
DS07-13750-3E 53
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOVI
tIVSHI tSHIXI
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
VIH
VIL
VIH
VIL
SCK
SOT
SIN
tSLSH tSHSL
tSLOVE
t
IVSHE
tSHIXE
VIL VIL
VIH VIH
2.4 V
0.8 V
VIH
VIL
VIH
VIL
tFtR
MB90920 Series
54 DS07-13750-3E
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90920 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↑ → SOT delay time tSHOVI SCK0 to SCK3,
SOT0 to SOT3 − 50 + 50 ns
Valid SIN → SCK ↓tIVSLI SCK0 to SCK3,
SIN0 to SIN3
tCP + 80 ⎯ns
SCK ↓ → valid SIN hold time tSLIXI 0⎯ns
Serial clock “H” pulse width tSHSL SCK0 to SCK3
External shift clock
mode output pin
CL = 80 pF + 1TTL
3 tCP − tR⎯ns
Serial clock “L” pulse width tSLSH tCP + 10 ⎯ns
SCK ↑ → SOT delay time tSHOVE SCK0 to SCK3,
SOT0 to SOT3 ⎯2 tCP + 60 ns
Valid SIN → SCK ↓tIVSLE SCK0 to SCK3,
SIN0 to SIN3
30 ⎯ns
SCK ↓ → valid SIN hold time tSLIXE tCP + 30 ⎯ns
SCK ↓ time tFSCK0 to SCK3 ⎯10 ns
SCK ↑ time tR⎯10 ns
MB90920 Series
DS07-13750-3E 55
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSHOVI
tIVSLI tSLIXI
2.4 V 2.4 V
0.8 V
2.4 V
0.8 V
VIH
VIL
VIH
VIL
SCK
SOT
SIN
tSHSL tSLSH
tSHOVE
tIVSLE tSLIXE
VIH
VIL
VIH
VIL
2.4 V
0.8 V
VIH
VIL
VIH
VIL
tRtF
MB90920 Series
56 DS07-13750-3E
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90920 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↑ → SOT delay time tSHOVI SCK0 to SCK3,
SOT0 to SOT3 − 50 + 50 ns
Valid SIN → SCK ↓tIVSLI SCK0 to SCK3,
SIN0 to SIN3
tCP + 80 ⎯ns
SCK ↓ → valid SIN hold time tSLIXI 0⎯ns
SOT → SCK ↓ delay time tSOVLI SCK0 to SCK3,
SOT0 to SOT3 3 tCP − 70 ⎯ns
SCK
SOT
SIN
tSHOVI
tSCYC
tSOVLI
tIVSLI tSLIXI
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
VIH
VIL
VIH
VIL
2.4 V
0.8 V
MB90920 Series
DS07-13750-3E 57
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by
some parameters. These parameters are shown in “MB90920 series hardware manual”.
• C
L is the load capacitance connected to the pin during testing.
• t
CP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↓ → SOT delay time tSLOVI SCK0 to SCK3,
SOT0 to SOT3 − 50 + 50 ns
Valid SIN → SCK ↓tIVSHI SCK0 to SCK3,
SIN0 to SIN3
tCP + 80 ⎯ns
SCK ↑ → valid SIN hold time tSHIXI 0⎯ns
SOT → SCK ↑ delay time tSOVHI SCK0 to SCK3,
SOT0 to SOT3 3 tCP − 70 ⎯ns
SCK
SOT
SIN
tSLOVI
tSCYC
tSOVHI
tIVSHI tSHIXI
0.8 V
2.4 V 2.4 V
2.4 V
0.8 V
VIH
VIL
VIH
VIL
2.4 V
0.8 V
MB90920 Series
58 DS07-13750-3E
(5) Timer input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Note : tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Input pulse width tTIWH
tTIWL
TIN0, TIN1,
IN0 to IN3 ⎯4 tCP ⎯ns
TIN0, TIN1
IN0 to IN3
VIH VIH
VIL VIL
tTIWH tTIWL
• Timer input timing
MB90920 Series
DS07-13750-3E 59
(6) Trigger input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Note : tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
Input pulse width tTRGH,
tTRGL
INT0 to INT7 ⎯200 ⎯ns During normal
operation
ADTG ⎯tCP + 200 ⎯ns
INT0 to INT7
ADTG
V
IH
V
IH
V
IL
V
IL
t
TRGH
t
TRGL
• Trigger input timing
MB90920 Series
60 DS07-13750-3E
(7) Low voltage detection
(VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
Detection voltage VDL VCC ⎯
4.0 4.2 4.4 V
Flash memory
product, during
voltage drop
3.7 4.0 4.3 V Evaluation product,
during voltage drop
Hysteresis width VHYS VCC ⎯
190 ⎯⎯mV
Flash memory
product, during
voltage rise
0.1 ⎯⎯VEvaluation product,
during voltage rise
Power supply voltage
change rate dV/dt VCC ⎯
− 0.1 ⎯ + 0.1 V/µs
Flash memory
product, dV/dt at low
voltage reset
−0.004 ⎯ + 0.004 V/µs
Flash memory
product, dV/dt at
standard value of
low voltage
detection/release
voltage
− 0.1 ⎯ + 0.02 V/µs Evaluation product
Detection delay time td⎯⎯
⎯⎯3.2 µs
Flash memory
product, when
dV/dt ≤ 0.004 V/µs
⎯⎯35 µs Evaluation product
VHYS
dV
dt
td
VCC
td
Internal reset
MB90920 Series
DS07-13750-3E 61
5. A/D Converter
(1) Electrical Characteristics
(VCC = AVCC = AVRH = 4.0 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
*1 : The time per channel (4.5 V ≤ AVCC ≤ 5.5 V, and internal operating frequency = 32 MHz) .
*2 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in
stop mode.
Parameter Symbol Pin name Value Unit Remarks
Min Typ Max
Resolution ⎯⎯ ⎯⎯10 bit
Total error ⎯⎯ − 3.0 ⎯ + 3.0 LSB
Non-linear error ⎯⎯ − 2.5 ⎯ + 2.5 LSB
Differential linear error ⎯⎯ − 1.9 ⎯ + 1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB V1 LSB =
(AVRH − AVSS) /
1024
Full scale transition
voltage VFST AN0 to AN7 AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB V
Sampling time tSMP ⎯0.4 ⎯16500 µs4.5 V ≤ AVcc ≤ 5.5 V
1.0 4.0 V ≤ AVcc ≤ 4.5 V
Compare time tCMP ⎯0.66 ⎯ ⎯µs4.5 V ≤ AVcc ≤ 5.5 V
2.2 4.0 V ≤ AVcc ≤ 4.5 V
A/D conversion time tCNV ⎯1.44 ⎯⎯µs*1
Analog port
input current IAIN AN0 to AN7 − 0.3 ⎯ + 10 µA
Analog input voltage VAIN AN0 to AN7 0 ⎯AVRH V
Reference voltage AV+AVRH AVss +
2.7 ⎯AVCC V
Power supply current IAAVCC
⎯2.3 6.0 mA
IAH ⎯⎯ 5µA*2
Reference voltage
supply current
IRAVRH ⎯520 900 µAV
AVRH = 5.0 V
IRH ⎯⎯ 5µA*2
Inter-channel variation — AN0 to AN7 ⎯⎯ 4LSB
MB90920 Series
62 DS07-13750-3E
• Notes on the external impedance and sampling time of analog inputs
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
If the sampling time is still not sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
R
Comparator
C
Analog input
• Analog input equivalent circuit
During sampling : ON
Note : The values are reference values.
MB90F922NC/F922NCS/ F923NC/F923NCS/F924NC/F924NCS
MB90922NCS
R C
4.5 V ≤ AVcc ≤ 5.5 V : 2.6 kΩ (Max) 8.5 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 12.1 kΩ (Max) 8.5 pF (Max)
MB90V920-101/102
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 14.4 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) 14.4 pF (Max)
MB90920 Series
DS07-13750-3E 63
•About errors
As |AVRH - AVSS| becomes smaller, the relative errors grow larger.
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20 25 3035
MB90F922NC/F922NCS/922NCS/
MB90F923NC/F923NCS/
MB90F924NC/F924NCS
MB90V920-101/102 20
18
16
14
12
10
8
6
4
2
0
0123456 87
MB90F922NC/F922NCS/922NCS/
MB90F923NC/F923NCS/
MB90F924NC/F924NCS
MB90V920-101/102
(External impedance = 0 kΩ to 100 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
(External impedance = 0 kΩ to 20 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
• The relationship between the external impedance and minimum sampling time
20
18
16
14
12
10
8
6
4
2
0
0123456 87
MB90F922NC/F922NCS/922NCS
/
MB90F923NC/F923NCS/
MB90F924NC/F924NCS
MB90V920-101/102
(External impedance = 0 kΩ to 20 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20 25 3035
MB90F922NC/F922NCS/922NCS
/
MB90F923NC/F923NCS/
MB90F924NC/F924NCS
MB90V920-101/102
(External impedance = 0 kΩ to 100 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
• At 4.5 V ≤ AVcc ≤ 5.5 V
• At 4.0 V ≤ AVcc ≤ 4.5 V
MB90920 Series
64 DS07-13750-3E
(2) Definition of terms
(Continued)
Resolution : Analog changes that are identifiable by the A/D converter.
Non-Linear error : The deviation of the straight line connecting the zero transition point
(“00 0000 0000” ←→ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ←→ “11 1111 1111”) from actual conversion characteristics.
Differential linear
error
: The deviation from the ideal value of the input voltage needed to change the output code by
1 LSB.
Total error : The total error is the difference between the actual value and the theoretical value,
and includes zero-transition error/full-scale transition error and linear error.
Total error
Actual conversion
value
Analog input
Total error for digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB [LSB]
1 LSB (Ideal) = AVRH − AVSS
1024 [V]
VOT (Ideal) = AVss + 0.5 LSB [V]
VFST (Ideal) = AVRH − 1.5 LSB [V]
VNT : Voltage when the digital output changes from (N - 1)H to NH
Actual conversion
value
Ideal
characteristics
(Measured value)
Digital output
AVSS AVRH
3FFH
3FEH
3FDH
004H
003H
002H
001H
1.5 LSB
VNT
{1 LSB x (N - 1) + 0.5 LSB}
0.5 LSB
N : A/D converter digital output value
MB90920 Series
DS07-13750-3E 65
(Continued)
Non-Linear error
Digital output
Differential linear error
(Measured
value)
(Measured value)
Non-linear error of
digital output N
VNT − {1 LSB × (N − 1) + VOT}
1 LSB [LSB]
=
Differential linear error
of digital output N
V (N + 1) T − VNT
1 LSB − 1 [LSB]
=
VFST − VOT
1022 [V]
1 LSB =
N : A/D converter digital output value
VOT : Voltage when digital output changes from “000H” to “001H”
VFST : Voltage when digital output changes from “3FEH” to “3FFH”
Actual conversion
value
Actual conversion
value
Ideal
characteristics
Digital output
Analog input Analog input
Actual conversion
value
{1 LSB x (N -1)
+ VOT}
Actual conversion
value
Ideal
characteristics
(Measured value)
AVss AVRH
3FFH
3FEH
3FDH
004H
003H
002H
001H
VNT
VOT (Measured value)
VFST
(Measured
value)
AVss AVRH
(N + 1)H
NH
(N - 1)H
(N - 2)H
V(N + 1)T
VNT
MB90920 Series
66 DS07-13750-3E
6. Flash Memory Program/Erase Characteristics
* : This value is calculated from the results of evaluating the reliability of the technology (using Arrhenius equation
to translate high temperature measurements into normalized value at + 85 °C) .
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase time TA = + 25 °C
VCC = 5.0 V
⎯0.9 3.6 s Excludes pre-programming before
erase
Word (16-bit width)
programming time ⎯23 370 µs Excludes system-level overhead
Chip programming
time
TA = + 25 °C,
VCC = 5.0 V ⎯3.4 55 s
Erase/program cycle ⎯10000 ⎯⎯cycle
Flash memory data
retention time
Average
TA = + 85 °C20 ⎯⎯year *
MB90920 Series
DS07-13750-3E 67
■ORDERING INFORMATION
Part number Package Remarks
MB90F922NCPMC
MB90F922NCSPMC
MB90922NCSPMC
MB90F923NCPMC
MB90F923NCSPMC
MB90F924NCPMC
MB90F924NCSPMC
120-pin plastic LQFP
(FPT-120P-M21)
MB90V920-101
MB90V920-102
299-pin ceramic PGA
(PGA-299C-A01) For evaluation
MB90920 Series
68 DS07-13750-3E
■PACKAGE DIMENSION
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
120-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 16.0 × 16.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.88 g
Code
(Reference) P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
(FPT-120P-M21)
C
2002 FUJITSU LIMITED F120033S-c-4-4
130
60
31
90 61
120
91
SQ
18.00±0.20(.709±.008)SQ
0.50(.020) 0.22±0.05
(.009±.002)
M
0.08(.003)
INDEX
.006 –.001
+.002
–0.03
+0.05
0.145
"A"
0.08(.003)
LEAD No.
.059 –.004
+.008
–0.10
+0.20
1.50
Details of "A" part
(Mounting height)
0.60±0.15
(.024±.006) 0.25(.010)
(.004±.002)
0.10±0.05
(Stand off)
0~8
˚
*
.630–.004
+.016
–0.10
+0.40
16.00
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
MB90920 Series
DS07-13750-3E 69
■MAIN CHANGES IN THIS EDITION
The vertical lines marked in the left side of the page show the changes.
Page Section Change Results
⎯⎯
Changed the part numbers;
MB90F922NB → MB90F922NC,
MB90F922NBS → MB90F922NCS,
MB90922NAS → MB90922NCS,
MB90F923NA → MB90F923NC,
MB90F923NAS → MB90F923NCS,
MB90F924NA → MB90F924NC,
MB90F924NAS → MB90F924NCS
3
■ PRODUCT LINEUP The position of the ruled line is changed.
Frame size is changed so that MB90922NCS,
MB90V920-101, and MB90V920-102 may be included,
and the description is changed to “-”.
12 ■ I/O CIRCUIT TYPE The circuit diagram A of EVA product is changed to that of
Flash/MASK ROM product.
20 ■ BLOCK DIAGRAM The item of "Clock supervisor & RC oscillation" is deleted.
44
■ ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Chenge the values as follows of Pull-up resistance.
Minimum value : “-”→25 kΩ
Typical value : “-”→50 kΩ
MB90920 Series
70 DS07-13750-3E
MEMO
MB90920 Series
DS07-13750-3E 71
MEMO
MB90920 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
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Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
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#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
