Features * * * * * * * * * * * * * * * * * Fully Compliant to VAN Specification ISO/11519-3 Handles All Specified Module Types Handles All Specified Message Types Handles Retransmission of Frames on Contention and Errors 3 Separate Line Inputs with Automatic Diagnosis and Selection Normal or Pulsed (Optical and Radio Mode) Coding VAN Transfer Rate: 1 Mbit/s Maximum SPI/SCI Interface SPI Transfer Rate: 4 Mbits/s Maximum SCI Transfer Rate: 125 Kbits/s Maximum Idle and Sleep Modes 128 Bytes of General Purpose RAM 14 Identifier Registers with All Bits Individually Maskable 6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the Reset Pin Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output Single +5V Power Supply 0.5 m CMOS Technology SO16 Package VAN Data Link Controller with Serial Interface TSS463C Description The TSS463C is a circuit that allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, thereby minimizing electrical wire usage. It can be used to interconnect powerful functions and to control and interface car body electronics (lights, wipers, power window, etc.). The TSS463C is fully compliant with the VAN ISO standard 11519-3. This standard supports a wide range of applications such as low-cost remote controlled switches, typically it is used for lamp control, up to complex, highly autonomous, distributed systems that require fast and secure data transfers. The TSS463C is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like dashboard controllers, car stereo or mobile telephone CPUs. The microprocessor interface consists of a 256-byte RAM and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general-purpose RAM, used as a message storage area, and a 6-source maskable interrupt. The circuit operates in the RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor, including SPI/SCI interface, to be connected with ease to the TSS463C. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS463C analyzes the messages received or transmitted according to 6 different criteria including some higher level checks. In addition, the bus interface has three separate inputs with automatic source diagnosis and selection, allowing for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. 7601B-AUTO-02/06 1 Block Diagram 2 TSS463C 7601B-AUTO-02/06 TSS463C Pin Configuration TOP VIEW 1 16 2 15 3 14 VDD 4 13 GND XTAL1 5 12 TXD XTAL2 6 11 RXD0 TEST/VSS 7 10 RXD2 CKOUT 8 9 RXD1 MISO SS INT MOSI SCLK RESET Pin Description I/O Type Pin Name Pin No O 3-state MISO 1 SPI/SCI Data Output I trigger CMOS SS 2 SPI/SCI Slave Select (active low) Open-drain INT 3 Interrupt (active low) Power VDD 4 + 5V power supply I CMOS XTAL1 5 Crystal oscillator or clock input pin O XTAL2 64 Crystal oscillator output pin TEST/VSS 7 Test mode input CKOUT 8 Buffered clock output I CMOS Pull-down RXD1 9 VAN bus input 1 I CMOS Pull-down RXD2 10 VAN bus input 2 I CMOS Pull-down RXD0 11 VAN bus input 0 O 3-state TXD 12 VAN bus output Ground GND 13 RESET 14 Hardware Reset (active low) I trigger CMOS SCLK 15 SPI/SCI Clock Input I trigger CMOS MOSI 16 SPI/SCI Data Input Ground O I trigger CMOS pull-up Pin Function 3 7601B-AUTO-02/06 Application The TSS463C is a microprocessor controlled line controller for the VAN bus. It can interface to virtually any microprocessor that includes SPI or SCI interface. * The TSS463C provides one full Motorola(c) compatible SPI interface. * It includes one full compatible Intel(R) UART (mode 0 only). * One 9-bits SCI interface is also integrated. The circuit also features a single interrupt pin. This pin can be treated as level sensitive, i.e. if there is a pending interrupt inside the circuit when another interrupt is reset the INT pin will emit a high pulse with the same pulse width as the internal write strobe (typically 20 ns). Figure 1. Typical Application With Motorola SPI Mode Remaining pins MISO(2) PORT X.Y IRQ General I/O (if needed) 100K MISO SS 16 2 15 3 14 INT VDD CKOUT MOSI 1 XTAL1 4 5 XTAL2 6 RESET (1) Notes: 4 13 GND TxD 12 11 TEST/VSS CKOUT SCLK RESET (1) TSS463 Microcontroller mC SCLK MOSI 7 10 8 9 RxD0 RxD2 VAN Bus RxD1 1. The TSS463C RESET pin can be either connected to GND through a 1 F capacitor, or the C RESET pin or unconnected (inactive with internal pull-up). 2. Leaving MISO output pin floating in high impedance mode slightly increases standby consumption. A 100K pullup/pulldown resistor is recommended. TSS463C 7601B-AUTO-02/06 TSS463C Microprocessor Interface The processor controls the TSS463C by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. Interface Modes The TSS463C must be connected with an SPI or SCI serial interface.The following section provides information switching from one mode to another. Motorola SPI Mode The first two bytes to be sent by the master (CPU) are called 'Initialization Sequence': This sequence provides a proper asynchronous RESET in the TSS463C and it selects the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown on figure 4: two 0x00 will cause an internal RESET and assert the Motorola SPI mode, two '0xFF' will provide an internal RESET and assert the Intel SPI mode and '9 bits to 0 followed by 0xFF or 0xFE'will generate an internal RESET and assert the 9-bits SCI mode. Figure 2. Mode Configuration Byte SPI 8 Pulses SCLK MOSI 0x00 or 0xFF 0x00 0xFF Motorola Intel SS Internal RESET Internal RESET and SPI Mode (Intel or Motorola) SCI 9 Pulses SCLK MOSI 0 . 0000 . 0000 1 . 1111 . 1111 SS Internal RESET Internal RESET and SCI Mode The Motorola Serial Peripheral Interface (SPI) is fully compatible with the SPI Motorola protocol. The interface is implemented for slave-mode only (the TSS463C can not generate SPI frames by itself). The SPI interface allows the interconnection of several CPUs and peripherals on the same printed circuit board. The SPI mode interface consists of 4 pins: separate wires are required for data and clock, so the clock is not included in the data stream as shown on Figure 3. One pin is needed for the serial clock (SCLK), two pins for data communication MOSI and MISO and one pin for Slave Select (SS) 5 7601B-AUTO-02/06 Figure 3. SPI Data Stream SPI 8 Pulses SCLK MOSI 0x55 MISO 0x66 SS SCLK: Serial Clock The master device provides the serial clock for the slave devices. Data is transferred synchronously with this clock in both directions. The master and the slave devices send/receive a data byte during an eight-clock pulse sequence. MOSI: Master Out Slave In The MOSI pin is the master device data output (CPU) and the slave device data input (TSS463C). Data is transferred serially from the master to the slave on this line; most significant bit (MSB) first, least significant bit (LSB) last. MISO: Master In Slave Out The MISO pin is configured as the slave device data output (TSS463C) and as master device data input (CPU). When the slave device is not selected (SS = 1), this pin is in high impedance state. SS: Slave Select The SS pin is the slave chip select. It is low active. A low state on the Slave Select input allows the TSS463C to accept data on the MOSI pin and send data on the MISO pin. The Slave Select signal must not toggle between each transmitted byte and should be left at a low level during the whole SPI frame. SS must be asserted to inactive high level at the end of the SPI frame. As mentioned before, if SS is not asserted, MISO pin is in a high impedance state and incoming data is not driven to the serial data register. SPI Protocol The general format of the data communication in the SPI frame between the TSS463C and the host is a bit-for-bit exchange on each SCLK clock pulse. Data is arranged in the TSS463C such that the significance of a bit is determined by its position from the start for output and from the end for input, most significant bit (MSB) is sent first. Bit exchanges in multiples of 8 bits are allowed. The Idle Clock Polarity (CPOL) and the Clock Phase (CPHA) are not programmable: the CPOL and CPHA values to be programmed in the master (CPU) are CPOL = CPHA = 1. This is available for all modes. Waveforms with transmit and sample points are shown in Figure 6. 6 TSS463C 7601B-AUTO-02/06 TSS463C Figure 4. CPOL and CPHA in the TSS463C CPOL = CPHA = 1 Data Sample Points SPI 8 Pulses SCLK MOSI 0x55 MISO 0x66 SS Data Transmit Points At the beginning of a transmission over the serial interface, the first byte is the address of the TSS463C register to be accessed. The next byte transmitted is the control byte that determines the direction of the communication. The following bytes are data bytes (consecutive bytes are written in or read from Address, Address + 1, Address + 2, ..., Address + n with n = 0 to 28). To make sure the TSS463C is not out of synchronization, the SPI interface will transmit data '0xAA'and '0x55'on the MISO pin during address and control byte time. This way, the master always ensures the TSS463C is well-synchronized. If the TSS463C is out of synchronization, the master can assert the SS pin inactive to resynchronize the SPI interface or can assert the RESET pin active or can send an initialization sequence. When the SS pin is inactive, the SCLK is allowed to toggle. This will have no effect on the TSS463C SPI module. SPI Control Byte The SPI control byte is transmitted by the master (CPU) to the TSS463C. It specifies whether it is a TSS463C Write or Read. Table 1. SPI Control Byte DIR: Serial Transfer Direction 7 6 5 4 3 2 1 0 DIR 1 1 0 0 0 0 0 Zero: Read Operation. The data bytes will be read by the master (CPU) from the TSS463C. One: Write Operation. The data bytes will be written by the master (CPU) to the TSS463C. In both cases, address auto-increment mechanism will take place when more than one data byte is read or written. This mechanism is inhibited when address value reaches 0xFF. The seven following bits are reserved and must be equal to: 1100000. When the master (CPU) conducts a write, it sends an address byte, a control byte and data bytes on its MOSI line. The slave device (TSS463C) will send, if well-synchronized, '0xAA'during the address byte and '0x55'during the control byte on its MISO line. 7 7601B-AUTO-02/06 When the master (CPU) conducts a read, it sends an address byte, a control byte and dummy characters ('0xFF'for instance) on its MOSI line. In the case of a VAN messages RAM read (VAN frame received), the first data byte sent back by the TSS463C on its MISO pin is the data length so the master knows how many dummy characters it must send to read the VAN frame properly. When the TSS463C responds back with data, it will not take care of the MOSI line. The master must activate and desactivate SS between each data frame. Synchronization bytes must be monitored carefully. For instance, if '0xAA'and '0x55'are not monitored correctly, then the previous transmission may be incorrect too. A control byte containing '0x00'or '0xFF'is forbidden except during an 'Initialization Sequence '. Intel SPI Mode The Intel SPI mode is the second type of interface. As mentioned before, the TSS463C enters this mode if the Initialization Sequence contains (first two bytes received) '0xFF, 0xFF'. This mode is fully compatible to the Intel UART serial interface programmed in mode 0 only. It is the same as Motorola SPI mode (same CPOL and CPHA) but with inverted communication sense (LSB first and MSB last). The protocol is also the same. However, from the master point of view (host microcontroller), the hardware is different. Figure 5 shows how to connect the TSS463C and Intel type microcontroller. Figure 5. Typical Application With the 8051 UART in Mode 0 General I/O Remaining pins optional TXD RXD 100k PORT X.y PORT X.z SS 16 2 15 3 14 VDD RESET (1) C1 4 XTAL1 5 GND 13 TXD 12 XTAL2 RxD0 6 C2 XTAL1 Note: 11 RxD2 TEST/VSS CKOUT SCLK RESET (1) TSS463 Microcontroller 1 INT IRQ 8 MOSI MISO (if needed) 7 10 8 9 VAN Bus RxD1 1. The RESET pin can either be connected to GND through a 1 F capacitor, or to the microcontroller RESET pin, or unconnected (inactive with internal pull-up). TSS463C 7601B-AUTO-02/06 TSS463C The master device provides the serial clock on the TxD pin and is still connected to SCLK pin of the slave device. Then, the RxD replaces the MOSI and MISO pins and is a bidirectional pin. To achieve a correct communication, the user should add a few gates to connect the master RxD pin to the MOSI-MISO slave pins. Figure 5 proposes two 3-state buffers controlled by the master through a general purpose I/O pin. It is obvious that, in this Intel SPI mode, the master cannot monitor the '0xAA and 0x55'synchronization bytes while sending the address and control bytes. It is the only exception of this mode compared with the Motorola SPI mode. SCI Mode The SCI mode is the third type of interface. The TSS463C enters this mode if the Initialization Sequence contains (first two bytes received) '0x00, 0xFF'. The SCI is compatible with a 9-bits SCI protocol. The interface is implemented for slavemode only (the TSS463C cannot generate SCI frames by itself). The SCI interface allows an interconnection of several CPUs and peripherals on the same printed circuit board. The SCI mode interface consists of 4 pins: separate wires are required for data and clock, so the clock is not included in the data stream as shown in Figure 7. One pin is needed for the serial clock (SCLK), two pins for data exchange MOSI and MISO and one pin for Slave Select (SS). Figure 6. SCI Data Stream SCI 9 Pulses SCLK MOSI 0x55 MISO 0x66 SS SCLK: Serial Clock The master device provides the serial clock for the slave devices. Data is transferred synchronously with this clock in both directions. The master and the slave devices exchange a data byte during a nine clock pulses sequence. However, the TSS463C will only monitor 8 bits on its MOSI line and send 9 bits on its MISO line. MOSI: Master Out Slave In The MOSI pin is the master device data output (CPU) and the slave device data input (TSS463C). Data is transferred serially from the master to the slave on this line; least significant bit (LSB) first, most significant bit (MSB) last. The TSS463C will only monitor 8 bits starting from the LSB to MSB-1. MISO: Master In Slave Out The MISO pin is configured as the slave device data output (TSS463C) and as master device data input (CPU). When the slave device is not selected (SS = 1), this pin is in high impedance state. The value of the MSB (9th bit) sent on the MISO pin will always be '1'and should not be used by the master. SS: Slave Select The SS pin is the slave chip select. It is low active. A low state on the Slave Select input allows the TSS463C to accept data on the MOSI pin and send data on the MISO pin. 9 7601B-AUTO-02/06 The Slave Select signal must not toggle between each transmitted byte and therefore, should be left at a low level during the whole SCI frame. SS must be asserted to inactive high level at the end of the SCI frame. If SS is not asserted, MISO pin is in high impedance state and incoming data is not driven to the serial data register. SCI Protocol Same as the SPI protocol described before except for data arranging (LSB first and MSB last). Only 8 bits are monitored by the TSS463C and master must monitor the 8 first bits too (9th bit always equal to 1). SCI Control Byte Same as the SPI control byte. Clocks and Speed Considerations SCLK and XTAL Clocks The SPI/SCI speed rate is given by the CPU producing SCLK. XTAL clock controls the speed rate on the VAN bus. The two clocks are asynchronous but a minimum SPI/SCI interframe spacing must be apply according to XTAL clock. Intel and Motorola SPI Modes Within an SPI byte, the maximum speed allowed on the MOSI line is 4 Mbits/s. For example, when using a 1 MHz oscillator (Sufficient to provide 62.5 kTS/s on the VAN bus) the minimum inter-character delay is 12 s (12 oscillator periods). Speed considerations are detailed in Figure 7. Figure 7. SPI Speed Considerations 4 Mbits/s Max for SCLK SCLK MOSI Address Control Data SS 4 Xtal Min 8 Xtal Min (4 s at 1 MHz) (8 s at 1 MHz) SCI Mode 10 15 Xtal Min (15 s at 1 MHz) 12 Xtal Min (12 s at 1 MHz) Within an SCI 9-bits data, the maximum speed allowed on the MOSI line is 125 Kbits/s. When using a 1 MHz oscillator, the data transfer speed and the minimum delay time between SCI bytes are shown in Figure 8. TSS463C 7601B-AUTO-02/06 TSS463C Figure 8. SCI Speed Considerations 125 Kbits/s Max for SCLK SCLK Start Bit MOSI Stop Bit Address Control Data SS 4 Xtal Min (4 s at 1 MHz) Interrupts 8 Xtal Min (8 s at 1 MHz) 15 Xtal Min (15 s at 1 MHz) 12 Xtal Min (12 s at 1 MHz) If an event occurs in the TSS463C that needs the attention of the processor, this will be signalled on the active low, open drain interrupt request pin. The event that creates this request is controlled by the internal registers. Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B), the INT pin will be released momentarily. This enables the TSS463C to work with processors that have either edge or level sensitive interrupt inputs. Reset The reset is applied asynchronously or synchronously to the XTAL clock. Asynchronous Reset It can be done either by the RESET pin (hardware asynchronous reset) or by software (software asynchronous reset). The RESET pin is a CMOS trigger input with a pull-up resistor (~ 70 k). An external 1 F capacitor to GND provides to RESET pin an efficient behavior. The asynchronous software reset is made by the 'Initialization Sequence'described in "Motorola SPI Mode" on page 5. Two '0x00'bytes provide an asynchronous software reset and configure the TSS463C in the Motorola SPI mode while two '0xFF'bytes provide a reset and configure the component in the Intel SPI mode and '0x00 followed by 0xFF 'provide a reset and configure the component in the SCI mode. The SS pin must be asserted as shown on Figure 9. The SPI/SCI logic will monitor these two bytes and provide an internal reset pulse asserting the TSS463C in the right mode. Synchronous Reset A synchronous reset (regarding XTAL clock) is available on the TSS463C during current operation. It is made through the GRES command bit of the Command Register (address 0x03). The two kinds of reset are ordered and filtered. Then the internal reset, always asserted asynchronously, enables the internal oscillator. Then it waits for 12 clock periods and the oscillator stability. The different blocks of the TSS463C need to be turned on synchronously. So the release of the internal reset is synchronous and a loose of clock can let the TSS463C in permanent reset after applying Reset. It is important to note that even after a reset on the RESET pin, the user should wait for 12 clock periods before sending the 'Initialization Sequence'in order to select the SPI or SCI mode (because the default mode after a hardware reset is the Motorola SPI mode). 11 7601B-AUTO-02/06 Figure 9. Asynchronous Software Reset with UART Intel Mode 4 XTAL Min SCLK 15 XTAL Min MOSI 0xFF 0xFF SS Detection of Forbidden Control Reset Internal Pulse End of Chip Select Oscillator An oscillator is integrated in the TSS463C, and consists of an inverting amplifier of that the input is XTAL1 and the output XTAL2. A parallel resonance quartz crystal or ceramic resonator must be connected to these pins. As shown in Figure 5, two capacitors have to be connected from the crystal pins to ground. The values of C2 depend on the frequency chosen and can be selected using the schematic given in Figure 39. If the oscillator is not used, then a clock signal must be fed to the circuit via the XTAL1 input. Note that this pin will behave as a CMOS level compatible Schmitt trigger input. In this case the XTAL2 output should be left unconnected. The oscillator also features a buffered clock output pin CKOUT. The signal in this pin is directly buffered from the XTAL1 input, without inversion. There is one more pin used for the oscillator. The TEST/VSS pin is in fact its ground, and unless this pin is firmly connected to ground, with decoupling capacitors, the oscillator will not operate correctly. The test mode itself, i.e., when the TEST/VSS pin is held high, is only intended for factory use, and the functionality of this mode is not specified in any way. The TEST/VSS pin is subject to change without notice, the only exception is for incoming inspection tests using the test program. The clock signal is then fed to the clock generator that generates all the necessary timing signals for the operation of the circuit. The clock generator is controlled by a 4-bit code called the clock divider. f ( XTAL1 ) f ( TSCLK ) = ------------------------n x 16 12 TSS463C 7601B-AUTO-02/06 TSS463C Table 2. Clock Divider 8 MHz 6 MHz 4 MHz 2 MHz Clock Divider Divide by KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s 0000 1 500 400 375 300 250 200 125 100 0001 2 250 200 187.50 150 125 100 62.50 50 0010 4 125 100 93.75 75 62.50 50 31.25 25 0011 8 62.5 50 46.875+ 37.5 31.25 25 15.625 12.5 0100 16 31.25 25 23.438 18.75 15.625 12.5 7.813 6.25 0101 32 15.625 12.5 11.718 9.375 7.813 6.25 3.906 3.125 0110 64 7.813 6.25 5.859 4.688 3.906 3.125 1.953 1.562 0111 128 3.906 3.125 500 400 1.953 1.562 166.666 133.333 1000 1.5 333.333 266.666 250 200 166.666 133.333 83.333 66.666 1001 3 166.666 133.333 125 100 83.333 66.666 41.666 33.333 1010 6 83.333 66.666 62.50 50 41.666 33.333 20.833 16.666 1011 12 41.666 33.333 31.25 25 20.833 16.666 10.416 8.333 1100 24 20.833 16.666 15.625 12.50 10.416 8.333 5.208 4.166 1101 48 10.416 8.333 7.813 6.25 5.208 4.166 2.604 2.083 1110 96 5.208 4.166 3.906 3.125 2.604 2.083 1.302 1.042 1111 192 2.604 2.083 1.953 1.5625 1.302 1.042 0.651 0.521 13 7601B-AUTO-02/06 VAN Protocol Line Interface There are three line inputs and one line output available on the TSS463C. that of the three inputs to use is either programmable by software or automatically selected by a diagnosis system. The diagnosis system continuously monitors the data received through the three inputs, and compares it with each other and the selected bitrate. It then chooses the most reliable input according to the results. The data on the line is encoded according to the VAN standard ISO/11519-3. This means that the TSS463C is using a two level signal having a recessive (1) and a dominant (0) state. Furthermore, due to the simple medium used, all data transmitted on the bus is also received simultaneously. The VAN protocol is hence a CSMA/CD (Carrier Sense Multiple Access Collision Detection) protocol, allowing for continuous bitwise arbitration of the bus, and non-destructive (for the higher priority messa ge) collision detection. Figure 10. CSMA/CD Arbritration Arbitration field Node a: TxD R D Node b: TxD R D Node c: TxD R D On Bus: DATA R D 2 Node a loses the arbitration Node a releases the bus 3 1 R: Recessive Level Node b wins the arbitration Node c loses the arbitration Node c releases the bus D: Dominant Level In addition to the VAN specification there is also a pulsed coding of the dominant and recessive states. This mode is intended to be used with an optical or radio link. In this mode the dominant state for the transmitter is a low pulse (2x prescaled clocks at the beginning of the bit) and the recessive state is just a high level. When receiving in this mode it is not the state of the signal itself that is decoded, but the edges. Also, reception is imposed on the RxD0 input, and the diagnosis system does not operate correctly. In addition, in this mode there is an internal loopback in the circuit since optical transceivers are not able to receive the signal that they transmit. 14 TSS463C 7601B-AUTO-02/06 TSS463C In Figure 11 the pulsed waveforms are shown. In Figure 14 through Figure 20 the low 'timeslots'(i.e. blocks of 16 prescaled clocks) should be replaced by the dominant waveform showed in Figure 11 if the correct representations for pulsed coding are desired. Figure 11. State Encoding VAN Frame Figure 12. Van Bus Frame Identifier Field SOF Command EXT RAK R/W RTR Data Field Frame Check Sum EOD ACK EOF The VAN bus supports three different module (unit) types: * The Autonomous module, that is a bus master. It can transmit Start of Frame (SOF) sequences, it can initiate data transfers and can receive messages. * The Synchronous access module. It cannot transmit SOF sequences, but it can initiate data transfers and can receive messages. * The Slave module, that can only transmit using an in-frame mechanism and can receive messages. Figure 13. Hierarchical Access Methods Autonomous Rank 0 SOF ID COM DATA FCS EOD ACK EOF COM DATA FCS EOD ACK EOF DATA FCS EOD ACK EOF Synchronous Rank 1 ID Rank 16 RTR Slave Figure 12 shows a normal VAN bus frame. It is initiated with a Start Of Frame (SOF) sequence shown in Figure 14. The SOF can only be transmitted by an autonomous module. During the preamble, the TSS463C will synchronize its bit rate clock to the data received. 15 7601B-AUTO-02/06 Figure 14. Framing Sequences VAN BUS START SYNC PREAMBLE SEQUENCE START OF FRAME VAN BUS END OF DATA ACK SEQUENCE NUMBER OF PRESCALED CLOCKS 0 16 32 48 END OF FRAME 64 80 96 112 128 144 160 176 192 When the complete SOF sequence has been transmitted or received, the circuit will start the transmission or reception of the identifier field. All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are transmitted using enhanced Manchester code. In enhanced Manchester code, three NRZ bits are transmitted first followed by one Manchester bit, then three more NRZ bits followed by one Manchester bit and so on. Since the high state is recessive and the low state is dominant, the bus arbitration can be done. If a module wants access to the bus, it must first listen to the bus during one full End of Frame (EOF) and one full Inter Frame Spacing (IFS) period to determine whether the bus is free or not (i.e. no dominant states received). Figure 15. Data Encoding VAN BUS SEQUENCE NRZ 0 VAN BUS SEQUENCE NRZ 1 MANCHESTER 0 VAN BUS SEQUENCE MANCHESTER 1 NUMBER OF PRESCALED CLOCKS 0 8 16 24 32 The IFS is defined to be a minimum of 64 prescaled clock periods. The TSS463C, accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence. Once the bus has been determined as being free, the module must, if it is an autonomous module, emit an SOF sequence or, if it is a synchronous access module, wait until it detects a preamble sequence. 16 TSS463C 7601B-AUTO-02/06 TSS463C At this point there could be several modules transmitting on the bus, and there is no possibility of knowing if this is the case or not. Therefore, the first field in that arbitration can be performed is the identifier field. Since the logical zeroes on the bus are dominant, and all data is transmitted with the most significant bit (MSB) first, the first module to transmit a logical zero on the bus will be the prioritized module, i.e., the message that is tagged with the lowest identifier will have priority over the other messages. It is, however, possible that two messages transmitted on the bus will have the same identifier. The TSS463C, therefore, continues the arbitration of the bus throughout the whole frame. Moreover, if the identifier in transmission has been programmed for reception as well, it transmits and receives messages simultaneously, right up until the Frame Check Sequence (FCS). Only then, if the TSS463C has transmitted the whole message, it discards the message received. Arbitration loss in the FCS field is considered as a CRC error during transmission. This feature is called full data field arbitration, and it enables the user to extend the identifier. For instance it can be used to transmit the emitting modules address in the first bytes of the data field, thus enabling the identifier to specify the contents of the frame and the data field to specify the source of the information. The identifier field of the VAN bus frame is always 12 bits long, and it is always followed by the 4-bit command field: * The first bit of the command is the extension bit (EXT). This bit is defined by the user on transmission and is received and retained by the TSS463C. To conform with the standard, it should be set to 1 (recessive) by the user, else the frame is ignored without any IT generation. * The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the receiving module must acknowledge the transfer with an in-frame acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must contain an acknowledge absent sequence. * The third bit is the Read/Write (R/W). This bit indicates the direction of the data in a frame. * - If set to zero, it is a `write' message, i.e., data transmitted by one module to be received by another module. - If it is set to one, it implies a 'read' message, i.e., a request that another module should transmit data to be received by the one that requested the data (reply request message). Last in the command field is the Remote Transmission Request bit (RTR). This bit is a logical zero if the frame contains data and a logical one if the frame does not contain data. In order to conform with the standard a received frame included the combination R/W. RTR = 01 is ignored without any IT generation. All the bits in the command field are automatically handled by the TSS463C, so the user does not need to be concerned for encoding and decoding these bits. The command bits transmitted on the VAN bus are calculated from the current status of the active message. After the command field comes the data field. This is just a sequence of bytes transmitted MSB first. In the VAN standard, the maximum message length is set to 28 bytes, but the TSS463C handles messages up to 30 bytes. The next field is the FCS field. This field is a 15 bit CRC checksum defined by the following generator polynomial g(x) of order 15: g(x)= x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1 17 7601B-AUTO-02/06 The division is done with the rest initialized to 0x7FFF, and an inversion of the CRC bits is performed before transmission. However, since the CRC is calculated automatically from the identifier, command and data fields by the TSS463C, it need not concern the user of the circuit. When the frame check sequence has been transmitted, the transmitting module must transmit an End Of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to terminate the transfer. Figure 16. Acknowledge Sequences VAN BUS SEQUENCE POSITIVE ACKNOWLEDGE VAN BUS SEQUENCE NUMBER OF PRESCALED CLOCKS Frame Examples 18 ABSENT ACKNOWLEDGE 0 8 16 24 32 The frames transmitted on the VAN bus are generated by several modules, each supplying different parts of the message. Figure 17 through Figure 20 show the four frame types specified in the VAN standard, and the module that is generated by the different fields. * The most straightforward frame is the normal data frame in Figure 17 Like all other frames it is initiated with a SOF sequence. This sequence is generated by a bus master (not shown in the figure). During this frame there is basically only one module transmitting with the only exception being the acknowledgement, generated by the receiving module if requested in the RAK bit. * The reply request frame with immediate reply in Figure 18 is the only frame in that a slave module can transmit data by filling it into the appropriate field. The only difference for the frame on the bus is that the R/W bit has changed state compared to the normal frame. This is a highly interactive frame where a bus master generates the SOF and the initiator generates the identifier, the three first bits of the command, and the acknowledge. The RTR bit, the data field, the frame check, the EOD and the EOF are all generated by the replying module. * The reply request frame with deferred reply in Figure 19 is basically the same frame as the reply request frame with immediate reply, but since the requested module does not generate the RTR bit the requesting module will continue with the frame check, the EOD and the EOF. During this frame the requested module will only generate the acknowledge, and only if this was requested by the initiator through the RAK bit. * Finally the deferred reply frame in Figure 20 that is sent when a module has prepared a reply for a reply request that has been received before. This frame very closely mimics the normal data frame with the only exception being the R/W bit that has changed state. TSS463C 7601B-AUTO-02/06 TSS463C Figure 17. Normal Data Frame DATA CRC EOD ACK RTR (*) DATA CRC EOD ACK EOF CRC EOD ACK EOF CRC EOD ACK EOF IDENTIFIER SOF IDENTIFIER RECEIVING module FRAME on bus EOF ACK SOF EXT RAK R/W TRANSMITTING module EXT RAK R/W RTR (*) With acknowledgment EXT RAK R/W RTR ACK : : : : : Recessive from Transmitter Recessive for acknowledge from Transmitter Dominant from Transmitter Dominant from Transmitter - (*) Manchester bit Positive from Receiver because RAK is Recessive SOF IDENTIFIER EXT RAK R/W RTR (*) TRANSMITTING module DATA SOF IDENTIFIER EXT RAK R/W RTR (*) Without acknowledgment DATA RECEIVING module FRAME on bus EXT RAK R/W RTR ACK : Recessive from Transmitter : Dominant for no acknowledge from Transmitter : Dominant from Transmitter : Dominant from Transmitter - (*) Manchester bit : Absent from Transmitter and from Receiver because RAK is Dominant 19 7601B-AUTO-02/06 EXT RAK R/W RTR ACK : : : : : IDENTIFIER ACK ACK SOF CRC EOF DATA CRC ACK FRAME on bus DATA EOD REQUESTED module EOD IDENTIFIER RTR (*) SOF EXT RAK R/W RTR (*) REQUESTING module EXT RAK R/W RTR (*) Figure 18. Reply Request Frame with Immediate Reply EOF Recessive from Requestor Recessive for acknowledge from Requestor Recessive from Requestor Recessive from Requestor and Dominant from Requestee- (*) Manchester bit Absent from Requestee and Positive from Requestor because RAK is Recessive EOD ACK IDENTIFIER CRC REQUESTED Module FRAME on Bus EOF ACK SOF CRC ACK IDENTIFIER EOD SOF EXT RAK R/W RTR (*) REQUESTING Module EXT RAK R/W RTR (*) Figure 19. Reply Request Frame with Deferred Reply EOF EXT : Recessive from Requestor RAK : Recessive for acknowledge from Requestor R/W : Recessive from Requestor RTR : Recessive from Requestor - (*) Manchester bit ACK : Absent from Requestor and Positive from Requestee because RAK is Recessive 20 TSS463C 7601B-AUTO-02/06 TSS463C ACK DATA CRC EOF ACK IDENTIFIER CRC ACK SOF DATA EOD IDENTIFIER EOD SOF EXT RAK R/W RTR (*) REPLYING module EXT RAK R/W RTR (*) Figure 20. Deferred Reply Frame RECEIVING module FRAME on bus EXT RAK R/W RTR ACK : : : : : EOF Recessive from Replyer Recessive for acknowledge from Replyer Recessive from Replyer - (*) Manchester bit Dominant from Replyer Absent from Replyer and Positive from Receiver because RAK is Recessive 21 7601B-AUTO-02/06 Diagnosis System The purpose of the diagnosis system is to detect any short or open circuits on either the DATA or DATA lines and to permit, if it is possible, to carry the communications on the non-defective line. The diagnosis system is based on the assumption that three separate line receivers are connected to the VAN bus see Figure 1. * One of the line receivers is connected in differential mode, sensing both DATA and DATA signals, and is connected to the RxD0 input. * The other two line receivers are operating in single wire mode and are sensing only one of the two VAN bus signals: - The line receiver sensing DATA is connected to RxD1 - The line receiver sensing DATA is connected to RxD2 The diagnosis system analyzes and compares the data sent over both VAN lines. So, the diagnosis system executes a digital filtering and transition analyses. In order to perform its investigation, three internal signals are generated, RI (Return to Idle), SDC (Synchronous Diagnosis Clock) and TIP (Transmission In Progress). One of four operating modes can be chosen to manage the results of the diagnosis system. Diagnosis States If the diagnosis system finds a failure on any of the VAN bus signals, it changes from nominal to degraded mode, and connects the line receiver not coupled to the failing signal to the reception logic. When the diagnosis system finds that the failing signal is working again, it returns to nominal mode and re-connects the differential line receiver to the reception logic. A major error occurs when both the VAN bus signals are failed. Figure 21. Diagnosis States Nominal Major Error Degraded Data Degraded Data - Failure during the frame. - Default of transitions on the valid input between 2 consecutive SDC rising edges. - Protocol fault - In specified selection mode, every RI pulse when an EOF is detected or through an active SDC. - In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges. - General reset. 22 TSS463C 7601B-AUTO-02/06 TSS463C Status bits give permanent information on the diagnosis performed, whatever the programmed operating mode. This is encoded over three bits: Sa, Sb and Sc. * Sa and Sb bits indicate the four possible states of the VAN bus. Table 3. Status Bits: Sa and Sb Sa 0 0 1 1 * Sb 0 1 0 1 Communication Mode Nominal Fault No fault on VAN bus Status Differential communication on DATA and DATA Mode Degraded on DATA Fault Fault on DATA Status Communication on DATA Mode Degraded on DATA Fault Fault on DATA Status Communication on DATA Mode Major error Fault Fault on DATA and DATA Status No communication on DATA and DATA (attempt to communicate alternatively on DATA then DATA every SDC period) Sc: As soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others in the input comparison analysis performs by the diagnosis system, Sc is set. The only way to reset this status bit is through the RI signal or a general reset. Internal Operations Digital Filtering If several spurious pulses occur during one bit, the diagnosis for defective conductor may be corrupted. To avoid such errors, digital filters are implemented. Filtering operation is based on sampling of the comparator output signals. A transition is taken into account only if it is observed over five samples (1/16th of timeslot). Transition Analyses These analyses are continuously done on the effective edges on comparators after digital filtering. * Asynchronous diagnosis The asynchronous diagnosis is done by comparing the number of edges on DATA and DATA. If four edges are detected on one input and no edges on the other during the same period, the second input is considered faulty and the diagnosis mode will change to one of the degraded modes. * Synchronous diagnosis The synchronous diagnosis counts the number of edges on the data input connected to the reception logic during one SDC period. If there are less than four edges during one SDC period, the diagnosis mode will change to the major error mode. 23 7601B-AUTO-02/06 * Transmission diagnosis The transmission compares RxD1 and RxD2 inputs (through the input comparators and the filters) with the data transmitted on TxD output. At a time when the transmission logic generates a dominant - recessive transition, the inputs can give different values. Taking into account the filtering delay, the bus line seen as dominant is assumed to be correct, the other one, recessive, is considered faulty. The diagnosis mode is changed to reflect that. * Protocol fault The protocol fault is detected by counting the number of consecutive dominant timeslots. If eight consecutive timeslots are dominant, the diagnosis mode will change to the major error mode. Generation of Internal Signals RI Signal (Return to Idle) This signal is used to return to nominal mode in the three specified selection modes (see "Diagnosis States" on page 22 and "Programming Modes" on page 25). The RI signal is disabled in automatic selection mode. The RI signal is a pulse generated when an EOF is detected. Thus, at the end of each frame, regarding the diagnosis status bit Sa, Sb and Sc, the user can make its own choice. SDC Signal (Synchronous Diagnosis Clock) This time base is used by diagnosis system in automatic selection mode (see Section "Programming Modes", page 25) when no event is recorded on the bus. The SDC is generated either by a special SDC divider connected to the timeslot clock, or can be performed manually. The SDC clock period must be long compared to the timeslot duration. A typical SDC period should be greater than the maximum frame length appearing on the VAN network. TIP Signal (Transmission in Progress) This signal must be enabled to allow the transmission diagnosis (see Section "Transition Analyses", page 23). The TIP turns on synchronously with the beginning of the transmission: * for asynchronous bus access, the beginning of SOF; * for synchronous bus access, the beginning of the identifier field; and * for a request of in frame reply, the RTR bit of the command field. The TIP turns off synchronously with the end of the transmission: * after EOF; * after a losing of arbitration or a code violation detection; and * for a requestor of in frame reply, when the arbitration is lost on RTR the bit. This signal is not generated when the transmission logic only sends an ACK. 24 TSS463C 7601B-AUTO-02/06 TSS463C Programming Modes Four programming modes determine how to use the three different inputs and the diagnosis system. * 3 specified selection modes * 1 automatic selection mode Table 4. Programming Modes Ma Mb Operating Mode 0 0 Differential communication 0 1 Degraded communication on RxD2 (DATA) 1 0 Degraded communication on RxD1 (DATA) 1 1 Automatic selection according the diagnosis status 25 7601B-AUTO-02/06 Registers The TSS463C memory map consists of three different areas, the Control and Status registers, the Channel registers and the Message data (or Mailbox). Mapping Figure 22. Memory Map 0x78 to 0x7F (r/w) Channel 13 Channel 13 0x70 to 0x77 (r/w) Channel 12 0x68 to 0x6F (r/w) Channel 11 0x60 to 0x67 (r/w) Channel 10 0x58 to 0x5F (r/w) Channel 9 0x50 to 0x57 (r/w) Channel 8 0x48 to 0x4F (r/w) Channel 7 0x40 to 0x47 (r/w) Channel 6 0x38 to 0x3F (r/w) Channel 5 0x30 to 0x37 (r/w) Channel 4 0x28 to 0x2F (r/w) Channel 3 0x20 to 0x27 (r/w) Channel 2 0x18 to 0x1F (r/w) Channel 1 0x10 to 0x17 (r/w) Channel 0 0x0C to 0x0F Reserved Interrupt Reset 0x0B (w) 0x0A (r/w) Interrupt Enable (0x80) Interrupt Status (0x80) 0x09 (r) Reserved 0x08 Last Error Status (0x00) 0x07 (r) Last Message Status (0x00) 0x06 (r) Transmit Status (0x00) 0x05 (r) Line Status (0bx01xxx00) 0x04 (r) Command (0x00) 0x03 (w) Diagnosis Control (0x00) 0x02 (r/w) Transmit Control (0x02) 0x01 (r/w) Line Control (0x00) 0x00 (r/w) Register Notes: 26 Data Byte 127 0xFF 0x7F (r/w) 0x7E (r/w) ID_Mask [3..0] ID_Mask [11..4] 0x7C and 0x7D Reserved Reserved 0x7B (r/w) Message Length + Status 0x7A (r/w) DRAK + Message Address 0x79 (r/w) ID_TAG (lsb) + COM ID_TAG (msb) 0x78 (r/w) Channel 13 Registers 0x17 (r/w) 0x17 (r/w) ID_Mask [3..0] ID_Mask [11..4] ID_Mask [11..4] 0x16 (r/w) 0x14 and 0x15 Reserved 0x13 (r/w) Message Length + Status 0x12 (r/w) DRAK + Message Address 0x11 (r/w) ID_TAG [3..0] + COM 0x10 (r/w) ID_TAG [11..4] Channel 0 Registers 0x8C 0x8B 0x8A 0x89 0x88 0x87 0x86 0x85 Data Byte 12 Data Byte 11 Data Byte 10 Data Byte 9 Data Byte 8 Data Byte 7 Data Byte 6 Data Byte 5 0x84 0x83 0x82 0x81 0x80 Data Byte 4 Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Message 1. All the non specified addresses between 0x00 and 0x7F are considered as absent. 2. (r) means read only register. (w) means write only register. (r/w) means read/write register. 3. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET. TSS463C 7601B-AUTO-02/06 TSS463C Control and Status Registers Line Control Register (0x00) CD[3:0]:Clock Divider 7 6 5 4 3 2 1 0 CD3 CD2 CD1 CD0 PC 0 IVTX IVRX * Read/write register. * Default value after reset: 0x00 * Reserved: Bit 2, this bit must not be set by the user; a 0 must always be written to this bit. They control the VAN Bus rate through a Baud Rate generator according to the formula below: f ( XTAL1 ) f ( TSCLK ) = ------------------------n x 16 PC: Pulsed Code One: The TSS463C will transmit and receive data using the pulsed coding mode (i.e optical or radio link mode). The use of this mode implies communication via the RxD0 input and the non-functionality of the diagnosis system. Zero: (default at reset) The TSS463C will transmit and receive data using the Enhanced Manchester code. (RxD0, RxD1, RxD2 used). IVTX: Invert TxD output IVRX: Invert RxD inputs The user can invert the logical levels used on either the TxD output or the RxD inputs in order to adapt to different line drivers and receivers. One: A one on either of these bits will invert the respective signals. Zero: (default at reset) The TSS463C will set TxD to recessive state in Idle mode and consider the bus free (recessive states on RxD inputs). Transmit Control Register (0x01) MR[3:0]: Maximum Retries 7 6 5 4 3 2 1 0 MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT * Read/Write register. * Default value after reset: 0x02 These bits allow the user to control the amount of retries the circuit will perform if any errors occurred during transmission. 27 7601B-AUTO-02/06 Table 5. Retries Note: VER[2:0] = 001 MR [3:0] Max. Number of retries Max. Number of transmissions 0000 0 1 0001 1 2 0010 2 3 0011 3 4 0100 4 5 0101 5 6 0110 6 7 0111 7 8 1000 8 9 1001 9 10 1010 10 11 1011 11 12 1100 12 13 1101 13 14 1110 14 15 1111 15 16 Bus contention is not regarded as an error and an infinite number of transmission attempts will be performed if bus contention occurs continuously. DLC Version after reset. These bits must not be set by user. 001 must always be written to these bits. MT: Module Type The three different module types are supported (see "VAN Frame" on page 15): One: The TSS463C is at once an autonomous module (Rank 0), a synchronous access module (Rank 1) or a slave module (Rank 16). Zero: The TSS463C is at once an synchronous access module (Rank 1) or a slave module (Rank 16). Diagnosis Control Register (0x02): 7 6 5 4 3 2 1 0 SDC3 SDC2 SDC1 SDC0 Ma Mb ETIP ESDC * Read/Write register * Default value after reset: 0x00. The diagnosis is discussed in greater detail in the section "Diagnosis System" on page 22. 28 * In its four high order bits, the user can program the SDC rate SDC [3:0] * In its two medium order bits, the diagnosis system mode is controlled: M1, M0. TSS463C 7601B-AUTO-02/06 TSS463C * SDC [3:0]: SDC Divider In the two low order bits, the user controls if the SDC and TIP are to be generated automatically ETIP, ESDC. The input clock is the timeslot clock. Table 6. System Diagnosis Clock Divider SDC DIVIDER SDC [3:0] Divide by 0000 64 0001 128 0010 256 0011 512 0100 1024 0101 2048 0110 4096 0111 8192 1000 16384 1001 32768 1010 65536 1011 131072 1100 262144 1101 524288 1110 1048576 1111 2097152 SDC calculation: (see "SDC Signal (Synchronous Diagnosis Clock)" on page 24). Notes: 1. For each module, determine the largest interframe spacing, LIFS (*). 2. For the whole network, get the maximum LIFS, MAX-LIFS. 3. SDC period > MAX-LIFS. (*) IFS min. = 4 TS Example: For VAN frame speed rate = 62,5 KTS/s (1 TS = 16 s), SDC >100 ms => 100 ms / 16 s = 6250, divider chosen: 8192, SDC [3:0] = 0111. Ma, Mb: Operating Mode Command Bits Table 7. Diagnosis System Command Bits Ma Mb 0 0 Forces the Communication on RxD0 (differential) 0 1 Forces the Communication on RxD2 (DATA) 1 0 Forces the Communication on RxD1 (DATA) 1 1 Automatic selection 29 7601B-AUTO-02/06 ETIP: Enable Transmission In Progress The Transmission In Progress (TIP) tells the diagnosis system to enable transmission diagnosis. One: Enable TIP generation Zero: Disable TIP generation. ESDC: Enable System Diagnosis Clock The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous diagnosis. One: Enable SDC divider. Zero: Disable SDC divider. Command Register (0x03) GRES: General Reset 7 6 5 4 3 2 1 0 GRES SLEEP IDLE ACTI REAR 0 0 MSDC * Write only register. * Reserved: Bit 1, 2. These bits must not be set by the user; a zero must always be written to these bit. * If the circuit is operating at low bitrates, there might be a considerable delay between the writing of this register and the performing of the actual command (worst case 6 timeslots). The user is therefore recommended to verify, by reading the Line Status Register (0x04), that the commands have been performed. The Reset circuit command bit performs, if set, exactly as if the external reset pin was asserted. This command bit has its own auto-reset circuitry. One: Reset active Zero: Reset inactive SLEEP: Sleep command (Section "Sleep Command", page 51). If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in sleep mode, all non-user registers are setup to minimize power consumption. Read/write accesses to the TSS463C via the SPI/SCI interface are impossible, the oscillator is stopped. To exit from this mode the user must apply either an hardware reset (external RESET pin) either an asynchronous software reset (via the SPI/SCI interface). One: Sleep active Zero: Sleep inactive IDLE: Idle command (Section "Idle and Activate Commands", page 51). If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will operate, but the TSS463C will not transmit or receive anything on the bus, and the TxD output will be in tri-state One: Idle active Zero: Idle inactive ACTI: Activate command (Section "Idle and Activate Commands", page 51). The Activate command will put the circuit in the active mode, i.e it will transmit and receive normally on the bus. When the circuit is in activate mode the TxD tri-state output is enabled. One: Activate active Zero: Activate inactive 30 TSS463C 7601B-AUTO-02/06 TSS463C REAR: Re-Arbitrate command. This command will, after the current attempt, reset the retry counter and re-arbitrate the messages to be transmitted in order to find the highest priority message to transmit. One: Re-arbitrate active Zero: Re-arbitrate inactive MSDC: Manual System Diagnosis Clock. Rather than using the SDC divider described in Section "SDC Signal (Synchronous Diagnosis Clock)" , the user can use the manual SDC command to generate a SDC pulse for the diagnosis system. This MSDC pulse should be high at least 2 timeslot clocks. Line Status Register (0x04) 7 6 5 4 3 2 1 0 X SPG IDG Sc Sb Sa TXG RXG * Read only register * Default value after reset: 0bx01xxx00. * This register reports the operation mode of the TSS463C in the Sleep an Idle bits (Command Register located at address 0x03) as well as the diagnosis system status bits Sa to Sc discussed in the section "Diagnosis System" on page 22 SPG: Sleeping IDG: Idling Default mode at reset. Sa, Sb and Sc: Diagnosis System Status Bits * Sa and Sb Table 8. Diagnosis System Status Bits * Sb Sa Communication Indication 0 0 Nominal mode, differential communication 0 1 Degraded over DATA, fault on DATA 1 0 Degraded over DATA, fault on DATA 1 1 Major error, fault on DATA and DATA Sc: As soon as one of the three inputs (RxD2, RxD1, RxD0) differs from the others in the input comparison analysis performed by the diagnosis system, Sc is set. The only ways to reset this status bit is through the RI signal or a general reset. TXG: Transmitting If this status bit is active, it indicates that the TSS463C has chosen an identifier to transmit, and it will continue to make transmission attempt for this message until it succeeds or the retry count is exceeded. RXG: Receiving The receiving indicates that there is activity on the bus. Note: For safe modification of active channel registers both bits should be inactive (except "abort" command). 31 7601B-AUTO-02/06 Transmission Status Register (0x05) 7 6 5 4 3 2 1 0 NRT3 NRT2 NRT1 NRT0 IDT3 IDT2 IDT1 IDT0 * Read only register. * Default value after reset: 0x00. * The transmission Status register contains the number of retries made up-to-date, according to the Table 5., and the channel currently in transmission. NRT [3:0] Number of retries done in transmission. IDT [3:0] Channel number currently in transmission. Last Message Status Register (0x06) 7 6 5 4 3 2 1 0 NRTR3 NRTR2 NRTR1 NRTR0 IDTR3 IDTR2 IDTR1 IDTR0 * Read only register. * Default value after reset: 0x00. * This register is basically the same as the transmission status register. It contains the last identifier number that was successfully transmitted, received or exceeded its retry count. If it was a successful transmission, the number of retries performed can be seen in this register as well. NRTR [3:0] Number of retries done successfully in transmission. In case of reception NRTR[3:0] is undefined. IDTR [3:0] Channel number that was successfully transmitted, received or exceeded its retry count. Last Error Status Register (0x07) BOC: Buffer occupied 7 6 5 4 3 2 1 0 X BOC BOV X FCSE ACKE CV FV * Read only register. * Default value after reset: 0x00. * The Last Error Status Register contains the error code for the last transmission or reception attempt. It is updated after each attempt, i.e. several error codes can be reported during one single transmission (with several retries). * when one channel configured in "Reply request" mode has its "received" bit set when it attempts to transmit its request. * BOC with the link capability between two channels sharing the same received buffer, is set when one channel has already set its "received" bit in its "Message length and status Channel register" and a receive is attempt on the other one. One: BOC active Zero: BOC inactive 32 TSS463C 7601B-AUTO-02/06 TSS463C BOV: Buffer Overflow BOV indicates that the buffer length setup in the Channel Status Register was shorter than the number of bytes received plus 1, and thus, some data was lost. One: BOV active Zero: BOV inactive FCSE: Framing Check Sequence Error FCSE indicates a mismatch between the FCS received and the FCS calculated ACKE: Acknowledge Error ACKE indicates a physical violation or collision on ACK field of the frame when the TSS463C is a producer. One: FCSE active Zero: FCSE inactive One: ACKE active Zero: ACKE inactive Figure 23. ACKE Status Bit RAK = 0 DLC: Producer EOD field ACK field Expected ACKE = 0 Received ACKE = 1 Received ACKE = 1 Received ACKE = 1 RAK* = 1 *RAK: bit of the frame COMMAND field EOD field CV: Code Violation ACK field Expected ACKE = 0 Received ACKE = 1 Received ACKE = 1 Received ACKE = 1 CV indicates: * either a Manchester code violation (2 identical TS on Manchester bit), or a physical violation (transmitted bit "dominant", received bit "recessive"), on fields ID, COM, DATA and CRC. * or a physical violation or collision on field "preamble" and the "recessive" bit of the "Star Sync" field. One: CV active Zero: CV inactive FV: Frame Violation FV indicates a physical violation or collision on ACK field of the frame when the TSS463C is a consumer. One: FV active Zero: FV inactive 33 7601B-AUTO-02/06 Figure 24. FV Status bit DLC: Consumer EOD field ACK field Expected FV = 0 Received FV = 1 Received FV = 1 Received FV = 1 EOD field ACK field Expected FV = 0 Received FV = 1 Received FV = 1 Received FV = 1 Interrupt Status Register (0x09) RST: Reset Interrupt 7 6 5 4 3 2 1 0 RST X X TE TOK RE ROK RNOK * Read only register. * Default value after reset: 1xx0 0000 RE indicates that the circuit has detected a valid reset command via the RESET pin or the reset command bit GRES. This interrupt cannot be disabled, since its enable bit is set when a reset is detected. One: Status flag activated Zero: No status flag. TE: Transmit Error Status Flag (or Exceeded Retry) This flag is set only when the Max number of transmission (1 + MR [3:0]) is reached with error of transmission. One: Status flag activated Zero: No status flag. Figure 25. Exceeded Retry with MR[3..0] = 3 1st TX TOK: Transmit OK status flag 34 2nd TX 3rd TX set TE set CHER set CHTx One: Status flag activated Zero: No status flag. TSS463C 7601B-AUTO-02/06 TSS463C RE: Receive Error Status Flag One: Status flag activated Zero: No status flag. ROK: Receive "with RAK (RAK=1)" OK Status Flag One: Status flag activated Zero: No status flag. RNOK: Receive "with no RAK (RAK=0)" OK Status Flag One: Status flag activated Zero: No status flag. Interrupt Enable Register (0x0A) 7 6 5 4 3 2 1 0 1 X X TEE TOKE REE ROKE RNOKE * Read/write register. * Default value reset: 1xx0 0000 Note: On reset, the Reset Interrupt Enable bit is set to 1 instead of 0, as is the general rule. TEE: Transmit Error Enable One: IT enabled. Zero: IT disabled. TOKE: Transmission OK Enable One: IT enabled. Zero: IT disabled. REE: Reception Error Enable One: IT enabled. Zero: IT disabled. ROKE: Reception "with RAK" OK Enable One: IT enabled. Zero: IT disabled. RNOKE: Reception "with no RAK" OK Enable One: IT enabled. Zero: IT disabled. Interrupt Reset Register (0x0B): 7 6 5 4 3 2 1 0 RSTR 0 0 TER TOKR RER ROKR RNOKR * Write only register. * Reserved bit: 5 and 6. This bit must not be set by user; a zero must always be written to this bit. RSTR: Reset Interrupt Reset One: Status flag reset. Zero: Status flag unchanged. TER: Transmit Error Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. TOKR: Transmit OK Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. 35 7601B-AUTO-02/06 RER: Receive Error Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. ROKR: Receive "with RAK" OK Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. RNOKR: Receive "with no RAK" OK Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. Figure 26. Update of the Status Register Flag Flag Write Flag Flag Write Write REE TOKR ID+COM+DATA+CRC 4 TS ROKE RER Interrupt Status Register 1 to 2 TS Pin 3 RNOKE ROKR Interrupt Enable Register Reset RNOKR Interrupt Register 6 TS Set RXG Set TXG BUS TOKE RNOK INT Write TER SOF ROK Flag Write TEE RSTR RE Reset RXG, TXG Internal RESET TOK ACK TE EOD RST INT Line Status Register (0x04) 4 TS Write "IT Status Register" Write "Last error Register" Write "Last message Register" Write "Message Status" 36 Write "Message Length and Status Register" TSS463C 7601B-AUTO-02/06 TSS463C Channel Registers There is a total of 14 channel register sets, each occupying 8 bytes for addressing simplicity, integrated into the circuit. Each set contains two 2 x 8-bit registers for the identifier tag, identifier mask and command fields plus two 1 x 8-bit registers for DMA pointers and message status. The base_address of each set is: (0 x 10 + [0x08 * channel_number]). When the TSS463C is reset either via the external RESET pin or the general reset command, the channel registers are not affected. That is, on power-up of the circuit, all the channel registers start with random values. Due to this fact, the user should take care to initialize all the channel registers before exiting from idle mode. The easiest way to disable an channel register is to set the received and transmitted bits to 1 in the Message Length and Status Register. Table 9. Channel Register Sets Map Channel Number from to Channel Number from to 6 0x40 0x47 13 0x78 0x7F 5 0x38 0x3F 12 0x70 0x77 4 0x30 0x37 11 0x68 0x6F 3 0x28 0x2F 10 0x60 0x67 2 0x20 0x27 9 0x58 0x5F 1 0x18 0x1F 8 0x50 0x57 0 0x10 0x17 7 0x48 0x4F Table 10. Channel Register Set Structure Reg. Name Offset Bit 7 Bit 6 Bit 5 Bit 4 ID_MASK 0x07 ID_MASK 0x06 (No register) 0x05 x x x x (No register) 0x04 x x x x MESS_L / STA 0x03 MESS_PTR 0x02 ID_TAG / CMD 0x01 ID_TAG 0x00 ID_M [3:0] Bit 3 Bit 2 Bit 1 Bit 0 x x x x x x x x x x x x CHER CHTx CHRx RAK RNW RTR ID_M [11:4] M_L [4:0] DRACK M_P [6:0] ID_T [3: 0] EXT ID_T [11:4] 37 7601B-AUTO-02/06 Identifier Tag and Command Registers The identifier tag and command registers are located at the base_address and base_address + 1. It allows the user to specify the full 12-bit identifier field of the ISO standard and the 4-bit command. * 7 6 5 4 3 2 1 0 ID_T 3 ID_T 2 ID_T 1 ID_T 0 EXT RAK RNW RTR 7 6 5 4 3 2 1 0 ID_T 11 ID_T 10 ID_T 9 ID_T 8 ID_T 7 ID_T 6 ID_T 5 ID_T 4 base_address + 0x01 base_address + 0x00 Read/Write registers. ID_T [11:0]: Identifier Tag Upon a reception hit (i.e, a good comparison between the identifier received and an identifier specified, taking the comparison mask into account, as well as a status and command indicating a message to be received), the identifier tag bits value will be rewritten with the identifier bits actually received. EXT, RAK, RNW and RTR (See Section "Message Types", page 44). No comparison will be done on the command bits, except on EXT bit. The RAK, RNW and RTR bits will be written into the first byte of the Message upon a reception hit. The RNW and RTR bits, as well as the status bits in the length and status register, must be in a valid position for reception or transmission. If not, the message corresponding to this identifier is considered as inactive or invalid. The way of knowing if an acknowledge sequence was requested or not is to check the first byte of the Message. Message Pointer Register The message pointer register at address (base_address + 0x02) is 8 bits wide. It indicates where in the Message DATA RAM area the message buffer is located. * DRAK: Disable RAK (Used in `Spy Mode') 7 6 5 4 3 2 1 0 DRAK M_P 6 M_P 5 M_P 4 M_P 3 M_P 2 M_P 1 M_P 0 base_address + 0x02 Read/Write register. In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be set. If the message was successfully received, an IT is set (ROK or RNOK). In transmission: no action. One: disable active, "spy mode". Zero: disable inactive, normal operation. M_P [6:0]: Message Pointer Since the Message DATA RAM area base address is 0x80, the value in this register is the offset from that address. If the message buffer length value is illegal (i.e. zero), this register is redefined as being a link pointer, thus containing the channel number of the channel that contains the actual message pointer, message length and received status. However, the identifier, mask, error and transmitted status used will be that of the originally matched channel. In any case, if a link is intended, the three high bits of M_P [6:0] should be set to 0. This allows several channels to use the same actual reception buffer in Message DATA RAM, thus diminishing the memory usage. Note: 38 Only 1 level of link is supported. TSS463C 7601B-AUTO-02/06 TSS463C Message Length And Status Register The message length and status register at address (base_address + 0x03) is also 8 bits wide. It indicates the length of reserved for the message in the Message DATA RAM area. * M_L [4:0]: Message Length 7 6 5 4 3 2 1 0 M_L 4 M_L 3 M_L 2 M_L 1 M_L 0 CHER CHTx CHRx Read/Write register. The 5 high bits of this register allows the user to specify either the length of the message to be transmitted, or the maximum length of a message receivable in the pointed reception buffer. Note: The first byte in this register does not contain data, but the length of the message received. This implies that the length value has to be equal to or greater than the maximum length of a message to be received in this buffer (or the length of a message to be transmitted) plus 1, thus allowing a maximum length of 30 bytes and a minimum length of 0 byte. If the value of this field is "illegal" (i.e 0x00) then this message pointer is defined as being a link (see Message pointer and register and "Linked Channels" on page 52). Note: CHER: Channel Error Status and Abort Command base_address + 0x03 1. M_L [4:0] = 0x00 Linked channel M_L [4:0] = 0x01 Frame with no DATA field (1) M_L [4:0] = 0x02 Frame with 1 DATA byte ------- ---------------------- M_L [4:0] = 0x1D Frame with 28 DATA bytes M_L [4:0] = 0x1E Frame with 29 DATA bytes M_L [4:0] = 0x1F Frame with 30 DATA bytes Different of a reply request frame with no in-frame reply (deferred reply). As status, this bit is set by the TSS463C when error occurs in transmission or on a received frame. The user must reset it. To abort the transmission defined in the channel, this bit can be set to 1 by the user (see Section "Activate, Idle and Sleep Modes", page 51 and "Abort" on page 49) CHTx: Channel Transmitted and Transmit Enable Command CHRx: Channel Received and Receive Enable Command The 2 low order bits of this register contain the message status. Together with the RNW and RTR bits of the command register (base_address + 0x01), they define the message type of this channel (see section "Message Types" on page 44). As a general rule, the status bits are only set by the TSS463C, so the user must reset them to perform a transmission (CHTx) or/and a reception (CHRx). The received and transmitted bits are only set if the corresponding frame is without errors or if the retry count has been exceeded. 39 7601B-AUTO-02/06 Identifier Mask Registers The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise masking of the comparison between the identifier received and the identifier specified. * ID_M [11:0]: Identifier Mask 7 6 5 4 3 2 1 0 ID_M 3 ID_M 2 ID_M 1 ID_M 0 x x x x 7 6 5 4 3 2 1 0 ID_M 11 ID_M 10 ID_M 9 ID_M 8 ID_M 7 ID_M 6 ID_M 5 ID_M 4 base_address + 0x07 base_address + 0x06 Read/Write registers. A value of 1 indicates comparison enabled. A value of 0 indicates comparison disabled. Example: 40 - ID_M[11:0] = 0x0FF8 - Acceptance: ID's from 0x0FF8 up to 0x0FFF TSS463C 7601B-AUTO-02/06 TSS463C Mailbox The mailbox contains all the messages received or to be transmitted. Each messages is link to a channel. The Mailbox RAM area has 128 bytes and is mapped from 0x80 to 0xFF (see Section "Mapping", page 26 ). The message (or message buffer) is composed of: * 1 byte of message status (only used in receiving), * n bytes of data. These data are the bytes of the DATA field of the frame with the same organization. The message is pointed by the Message Pointer Register of the channel, the length of the message is given by the Message Length and Status Register of the channel (Section "Message Length And Status Register"). This area is a pure RAM, it contains a random value after reset. Figure 27. Message Buffer Structure for Reception Message Length and Status Register Message Pointer Register CHER CHTx CHRx ( M_L >= n + 2 ) M_L [4..0] M_P [6..0] DRAK Message Received DATA n M_P + 0x80 + n + 2 Received DATA 0 DATA n FCS ACK DATA 0 M_P + 0x80 EOD ID [11..0] RTR SOF EXT RAK RNW RAK RNW RTR M_L [4..0] = n+1 receivedreceivedreceived received EOF Received DATA Frame, immediate or deffered reply 41 7601B-AUTO-02/06 Figure 28. Message Buffer Structure for Transmission Message Length & Status Register Message Pointer Register CHER CHTx CHRx M_L [4..0] DATA n Transmitted DATA 0 M_P + 0x80 + n + 2 RTR RNW EXT RAK ID [11..0] M_P + 0x80 DATA 0 FCS DATA n ACK Transmitted EOD ( M_L >= n + 2 ) Message (Nothing) SOF M_P [6..0] DRAK EOF Transmitted DATA Frame Message Status (Pointed by: Message Pointer Register) * 7 6 5 4 3 2 1 0 RRAK RRNW RRTR RM_L4 RM_L3 RM_L2 RM_L1 RM_L0 (no significant value in case of message to be transmitted) RRAK: Received RAK Bit This bit is the RAK bit coming from the COM field of the received frame. RRNW: Received RNW Bit This bit is the RNW bit coming from the COM field of the received frame. RRTR: Received RTR Bit This bit is the RTR bit coming from the COM field of the received frame. RM_L[4:0]: Message Length of the Received Frame If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1, even if the reserved length (Message Length and Status Register) is larger. 42 TSS463C 7601B-AUTO-02/06 TSS463C Figure 29. Message Status Updating Frame Type Node x Communication Node A I, P C Data Frame Immediate Reply Deferred Reply Message Status on Node A after IT(*) I, C RAK RNW RTR RAK RNW RTR RAK RNW RTR Length P I, C Previous Value P C Previous Value I, P Data Frame previous values P Immediate Reply I, C P Deferred Reply P: Producer RNW RTR Length RAK RNW RTR Length I, C I: Initiator Note: RAK C: Consumer 1. After IT ROK or RNOK. In case of IT RE, the values can be erroneous. Message Data (String Pointed by: Message Pointer Register + 1) 7 6 5 4 3 2 1 0 --- --- -- - - --- DATAn --- --- --- --DATA0 DATA0 is the first received (or transmitted) byte, DATAn is the last one. Note: 1. If the length reserved (in the message length and status register) for an incoming frame is 2 bytes greater or more, the TSS463C will write the 2 bytes of the CRC field in the message string just after DATAn. Because the VAN frame does not contain a message length, the only way for the component to know the length of the DATA field is either the message length register value, or the EOD field detection. When the reserved length is too large, at the moment when it detects the EOD, the TSS463C has already written the 2 bytes of the CRC field, considering these bytes as normal DATA. 2. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80. 43 7601B-AUTO-02/06 Message Types There are 5 basic message types defined in the TSS463C. Two of them (transmit and receive message types) correspond to the normal frame, and the rest correspond to the different versions of reply frames. Transmit Message RNW RTR CHTx CHRx Initial setup 0 0 0 Don't care After transmission 0 0 1 Unchanged To transmit a normal data frame on the VAN bus, the user must program an identifier as a Transmit Message. The TSS463C will then transmit this message on the bus until it has succeeded or the retry count is exceeded. Receive Message RNW RTR CHTx CHRx Initial setup 0 1 Don't care 0 After transmission 0 1 Unchanged 1 The opposite of the transmit message type is the Receive Message type. This message type will not generate any frames on the bus. Instead, it will listen to the bus until a frame passes that matches its identifier, with the mask taken into account, and then receive the data in that frame. The data received will be stored in the message buffer and the length of the message received is stored in the first byte of the message buffer. The actual identifier received is stored in the identifier register itself. This identifier may differ from the identifier specified in the register due to the effect of the mask register. Normally this should not interfere with the next identifier comparison since the bits that may differ are masked via the mask register. Reply Request Message RNW RTR CHTx CHRx Initial setup 1 1 0 0 After transmission (Waiting for reply) 1 1 1 0 After reception (of reply) 1 1 1 1 The Reply Request Message type is a demand to transmit on the VAN bus a reply request. When this message type is programmed, three things can happen. In the first case no other modules on the bus responded with an in-frame reply, and in this case the TSS463C will set the message type to the after transmission state. When this message type is programmed, the TSS463C will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. 44 TSS463C 7601B-AUTO-02/06 TSS463C The second case is that another module on the bus replies with an in-frame reply. In this case the message type will pass immediately into the after reception state, without passing the after transmission state. Reply Request Message without transmission RNW RTR CHTx CHRx Initial setup 1 1 Don't care 0 After reception 1 1 Unchanged 1 In the third case the TSS463C has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. Warning! This should be avoided as it may result in an illegal message type (Illegal reply Request). Immediate Reply Message RNW RTR CHTx CHRx Initial setup 1 0 0 0 After transmission 1 0 1 1 The immediate Reply Message will attempt to transmit an in-frame reply, using the data in the message buffer. Deferred Reply Message RNW RTR CHTx CHRx Initial setup 1 0 0 1 After reception (of reply request) 1 0 1 1 Above a Deferred Reply Message is shown. This message type will immediately transmit a deferred reply frame. Reply Request Detection Message RNW RTR CHTx CHRx Initial setup 1 0 1 0 After reception 1 0 1 1 Finally there is the Reply Request Detector Message type. Its purpose is to receive a reply request frame and notify the processor, without transmitting an in-frame reply. Inactive Message RNW RTR CHTx CHRx Recommended Don't care Don't care 1 1 After transmission 0 0 1 Don't care After reception 0 1 Don't care 1 Illegal reply request 1 1 0 1 The table above shows all inactive messages types. The last combination will transmit a reply request, but will not receive the reply since its buffer is tagged as occupied. 45 7601B-AUTO-02/06 Priority Among the Different Channels The priority handling on the VAN bus itself is already explained in the Line interface section. The priorities for the messages in the TSS463C is however slightly different. For instance, it's possible that an identifier matches two or more of the identifiers programmed into the registers. In this case, it is the lowest identifier number that has priority. i.e. if both identifier 5 and 10 match the identifier received, it is the identifier 5 that will receive the message. However, since the identifier 5 will become an inactive message when it has received the frame, the next time the same identifier is seen on the bus, the corresponding data will be received by identifier 10. The same is valid for messages to be transmitted, i.e. if two or more messages are ready to be transmitted, it is the one with the lowest identifier number that will get priority. Retries, Rearbitrate and Abort Retries and rearbitrate commands are located, respectively, in the Transmit Control Register and in the Command Register. An abort command is located in each channel register set, in the Message Length and Status Register (base_address + 0x03). These three commands are available only when the TSS463C is producer. Figure 30. Transmit Function Activate Ch. Enabled in Xmit Mode ? No Yes Select The Lowest Disable of Ch. Number And Load "Max - Retries" Current Ch. Yes Abort Activated On Current Ch. ? No Wait For Bus Free (EOF+IFS= 12 Timeslots) Decrement Transmit Frame Retry Counter And Wait For The End Abort Required On Current Ch. Rearbitrate? Abort Rearbitrate No Yes 46 Retry Needed ? No TSS463C 7601B-AUTO-02/06 TSS463C Retries The purpose of the retries feature is to provide, for the user, the capability of retrying a transmit request in case of failure, when a node tries to reach another node, either on normal DATA frame or on REPLY REQUEST frame. The maximum number of retries is programmable through MR[3:0] of the Transmit Control Register (0x01). When a channel is enable - bit CHTx = 0 of Message Length and Status Register, a 4-bit counter is loaded with MR[3:0]. At each attempt, this counter will count-down to 0, an IT TE is set in the Interrupt Status Register (0x09), and the transmission is stopped. MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see Table 5, "Retries," on page 28). The number of retries performed, as well as the current channel number associated, can be read in the Transmission Status Register (0x05). The Last Error Status Register (0x07) informs about the trouble uncounted: * * Failure cases: - Code viol (CV error bit) - Acknowledge error (ACKE error bit) - CRC error (FCSE error bit) It should be noticed that contention is considered as normal CSMA/CD protocol and, therefore, is not taken into account in failure cases. So, an 'infinite' number of attempts can be performed if bus contention occurs continuously. There is only one retry counter for all channels. When the user writes the Max_Retries value, all channels start their transmission with this parameter. Rearbitrate The purpose of rearbitrate feature is to postpone a channel already in transmission in order to authorize an higher priority (see Section "Priority Among the Different Channels", page 46) message to be transmit. Typical Example * Max_retries = 1 (2 transmissions attempts). * If Ch8 is in a the retry loop and the user wants to transmit the Ch5 without waiting the end of the loop, the user can use the rearbitrate command. * The TSS463C will then wait until the end of the current transmission, reload the retries counter and enable the Ch5 to transmit. * At the end of this transmission Ch5, either when the attempt is successful or the exceeded retry count is reached, the retries counter is reloaded and the transmission is activated for the Ch8 again. 47 7601B-AUTO-02/06 48 EOF+IFS Second attempt Xmit Ch8 (Retries - 1) EOF+IFS Set CHER & CHTx /Ch8, and set ITTE Ex: set FSCE status bit (not seen by application) First attempt Xmit Ch8 Delay Second attempt Xmit Ch8 * (not seen by application means no IT generation) Ex: FCS Error (Load Max-retries) Set CHTx/Ch5 & ITROK Xmit Ch5 First attempt Xmit Ch8 * (not seen by application means no IT generation) (Retries - 1) Delay Viol Idle command (Load Max-retries) * (not seen by application) Ex: FCS Error Rearbitrate (Activate Ch5) (Load Max-retries) Viol First attempt Xmit Ch8 Xmit Ch5 First attempt Xmit Ch8 Set CHER & CHTx /Ch8, and set ITTE Ex: set FSCE status bit Ex: FCS Error (not seen by application) (Load Max-retries) Set CHTx/Ch5 & ITROK (Load Max-retries) * (not seen by application) Ex: FCS Error (Activate Ch5) Rearbitrate (Load Max-retries) Figure 31. Rearbritrate Example Delay Delay Viol Viol Delay Viol stand-by EOF+IFS: 8 + 4 Timeslots Delay Viol: 12 Timeslots Figure 32. Idle and Rearbitrate Example Idle Delay Viol EOF+IFS: 8 + 4 Timeslots Delay Viol: 12 Timeslots If the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at the end of all the transmit attempts (for more information about idle command, see "Activate, Idle and Sleep Modes" on page 51). TSS463C 7601B-AUTO-02/06 TSS463C (Load Max-retries) Ex: FCS Error (not seen by application) Disable Ch8(1) (Activate Ch5) Rearbitrate (Load Max-retries) Figure 33. Disable Channel After Rearbitrate Ex: ACK Error (not seen by application) Set CHER & CHTx /Ch5, and set ITTE Ex: setACKE status bit Delay Viol Delay Viol stand-by (Retries - 1) KO Delay Viol Second attempt Xmit Ch5 First attempt Xmit Ch5 First attempt Xmit Ch8 Set CHTx/Ch5 & ITTOK OK EOF+IFS stand-by EOF+IFS: 8 + 4 Timeslots Delay Viol: 12 Timeslots (1) The disable is applied setting the CHTx/Ch8 bit to 1. In this case, the TSS463C completes the current attempt (Ch8) and lets the transmission go into the new channel (Ch5 if validated), otherwise it stops all attempts on the current channel. Abort An abort command is dedicated to channels already enabled in transmission or in inframe response. For example, this command can be used to break the retry procedure on one channel. Abort channel is done by setting the Error bit (CHER) in the Message Length and Status Register (base_address + 0x02). This command is taken into account if the channel aborted is not transmitted. When this abort command is really done, the TSS463C set to 1 the Transmitted bit (CHTx) of the Message Length and Status Register. The abort mechanism is integrated into the transmit function. This mainly means, abort, priority and retries live together in the transmit function. 49 7601B-AUTO-02/06 50 Xmit Ch6 if Previously Failed Xmit Ch6 if Previously Failed Xmit Ch6 Xmit Ch4 /Ch6 & IT ROK SetorCHTx CHER or IT RE Set CHTx/Ch13 Set CHTx/Ch6 & ITROK if Successful Set CHTx/Ch6 & ITROK if Successful Set CHTx/Ch4 &ITROK Abort Ch4 (during Xmit) Abort Ch13 (before Xmit) Activate Abort Ch0 (before Xmit) Set CHTx/Ch0 Ch s Initialization Reset Figure 34. Abort Example 12 Timeslots TSS463C 7601B-AUTO-02/06 TSS463C Activate, Idle and Sleep Modes Sleep, idle and activate commands are located in the Command Register (0x03). These three commands are general commands for the TSS463C. Idle and Activate Commands After reset, the TSS463C starts in idle mode. In this mode, the oscillator operates (CKOUT pin active) but the circuit cannot transmit or receive anything on the VAN bus. The TxD output (pin 12) is in tri-state mode, a pull-up resistor must be provided externally or by the line driver to avoid floating state on the VAN bus. To activate the TSS463C, the user must set the activate bit (ACTI) and reset the idle bit (IDLE). Figure 35. Idle and Activate Timings Idle Mode Activate Mode SOF RxD Activate command After Reset SOF TxD 8 TS 12 TS 3 TS (max) TS: Timeslot Period Idle Mode ACK FCS EOD Activate Mode RxD Idle Command INT 4 TS 5 TS In both cases, the idle state can be verified reading the Line Status register (0x04). Sleep Command If the user sets the sleep bit (SLEEP), the TSS463C enters in sleep mode, regardless of the values of activate and idle bits. It means that, all non-user registers are set-up to reduce the power consumption and the internal oscillator is immediately stopped. Then, accesses to all registers (and to the messages) via the SPI/SCI interface are impossible and CKOUT is not provided. To exit from this mode the user must apply either an hardware reset (external reset pin) either an asynchronous software reset (via the SPI/SCI interface). In a typical application (see Figure 5), using the CKOUT feature (pin 8), if the TSS463C is put in sleep mode, the clock provided to the microcontroller is stopped. So, the system does not run and the only way to awake this application is an external reset. 51 7601B-AUTO-02/06 Linked Channels The linkage feature allows two channels to share the same Message area, the message pointer and the message length assumes this property: * Zero value as message length (M_L [4:0] - base_address + 0x03) declares the channel linked to another channel. * The number of this other channel is defined in the message pointer field (M_P [6:0] - base_address + 0x02). * The pointer and the length values for the Message area are defined only once, in the register set of this other Channel. Only one level of linkage can be created. This means, (see Figure 36) a Channel k can be linked to the Channel i but not to Channel j, already defined as linked to Channel i. All the others can be different between the two channels, for example the ID_Tag. Figure 36. Linkage Mechanism The Channel j linked Channel i and j .... share the same Message area to the Channel i ID_Mask j (msb) 0x00 DRAK ID_Tag j (lsb) --- Message for Channels i & j --- DATA n CHER CHTx CHRx i EXT RAK RNW RTR ID_Tag j (msb) Length = n+2 --- Channel j --- ID_Mask j (lsb) --- Channel i --- ID_Mask i (lsb) ID_Mask i (msb) Mess_Len = n+2 CHER CHTx CHRx Mess_Ptr DRAK ID_Tag i (lsb) EXT RAK RNW RTR DATA 0 Message Status ID_Tag i (msb) This Message area sharing permits either to optimize the allocation of the 128 bytes of DATA, either to perform some special communications between the different nodes of the network. 52 TSS463C 7601B-AUTO-02/06 TSS463C Electrical Characteristics Absolute Maximum Ratings *NOTICE: Ambient temperature under bias: Automotive........................................................-40C to 125C Storage Temperature ........................................-65C to 150C Voltage on VCC to VSS .......................................... -0.5 to +7.0V Voltage on any pin to VSS ..........................-0.5V to VCC +0.5V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions exceeding those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Characteristics Table 11. TA = -40C to 125C; VCC = 5 V + 10%; VSS = 0 V Symbol Parameter Min. Max Unit Test Conditions VIL Input Low Voltage -0.5 0.3*VCC*min V VIH Input High Voltage 0.7*VCC max VCC+0.5 V VHY Hyteresis Voltage of Trigger CMOS inputs 0.4 - V see Table VOL Output Low Voltage 0.4 V IOL = 3.2 mA, VCC min VOH Output High Voltage V IOH = -3.2 mA, VCC min 5 A 0 < VIN < VCC 5 A 0 < VIN < VCC k Note 4 10 pF Not tested 50 A (Note 1) 9 mA (Notes 2, 3) 2.4 Input Leakage Current IL (SCLK, MOSI, SS) Output Tri-state Leakage Current IOZ (MISO) RPU, RPD Input pull-up and pulldown resistors CIO I/O Buffer Capacitance ICCSB ICCOP Notes: 1. 2. 3. 4. Power Supply Current Sleep mode Power Supply Current Idle or Active mode 70 Sleep Mode ICCSB is measured according to a VSS Clock Signal. Active mode ICCOP is measured at: XTAL = 8 MHz clock, VAN speed rate = 125 KTS/s. ICC is a function of the Clock Frequency. Figure 38 displays a graph showing ICC versus Clock frequency. RESET, RxD0, RxD1, RxD2 inputs. 53 7601B-AUTO-02/06 Figure 37. ICC Figure 38. ICCOP versus Clock Frequency at 125 KTimeslot/s mA 9 8.5 8 7.5 MHz 2 54 4 6 8 TSS463C 7601B-AUTO-02/06 TSS463C AC Characteristics Table 12. Microprocessor Inrterface CLOAD = 200pF on SPI/SCI lines TA = -40C to 125C; VCC = 5V + 10%; VSS = 0V Symbol fOP Characteristic Min Max Unit Operating Frequency SPI dc 4 MHz SCI dc 125 kHZ 250 - ns SCI 8 - ms tLEAD Enable Lead Time 4 - XTAL Period 3 tLAG Enable Lead Time 12 - XTAL Period 4 tW(SCKH) Clock (SCLK) High Time 100 - ns 5 tW(SCKL) Clock (SCLK) Low Time 100 - ns 6 tSU Data Setup Time (Inputs) 40 - ns 7 tH Data Hold Time (Inputs) 40 - ns 8 tA 0 100 ns 9 tDIS Slave Disable Time (Hold Time to HighImpedance State) - 200 ns 10 tV Data Valid (After Enable Edge) - 60 ns 11 tHO Data Hold Time (Outputs After Enable Edge) 0 - ns 12 tIZIL(1) INT Float Pulse Width 20 1 tCYC 2 Note: Cycle Time SPI Slave Access Time (Time to Data Active from High-Impedance State) ns 1. Simulated Data SS (INPUT) t CYC t LEAD SCLK (INPUT) t FLAG t W(SCKL) t W(SCKH) t DIS A MISO (OUTPUT) tH t SU tV tHO MOSI (INPUT) t INT IZIL t IZIL float pulse only when address is 0x08 to 0x0B 55 7601B-AUTO-02/06 Interface Oscillator Characteristics Figure 39. C2 versus Frequency pF 200 100 33 1 Note: External Clock Drive Characteristics (XTAL1) 2 4 8 MHz C1 (no capacitance needed) see Figure 5. Symbol Parameter Min Max tCHCH Oscillator period 120 ns tCHCX High Time 20 ns tCLCX Low Time 20 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns t CHCL XTAL1 V IH Unit t CLCH V IH V IH V IL V IL t CHCX t CLCX t CHCH 56 TSS463C 7601B-AUTO-02/06 TSS463C Packaging Information SO16 SO MM Inch A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.35 0.49 0.014 0.019 C 0.23 0.32 0.009 0.013 D 10.10 10.50 0.398 0.413 E 7.40 7.60 0.291 0.299 e 1.27 BSC 0.050 BSC H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.029 L 0.40 1.27 0.016 0.050 N 16 16 a 0 8 0 8 57 7601B-AUTO-02/06 Ordering Information Part Number Supply Voltage Temperature Range Package Packing TSS463C-TESA-9 5V +10% -40C - +125C SO16 Stick TSS463C-TERA-9 5V +10% -40C - +125C SO16 Tape and Reel TSS463C-TERZ-9(1) 5V +10% -40C - +125C SO16 Tape and Reel Note: 58 1. These products are available in ROHS version. TSS463C 7601B-AUTO-02/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 e-mail literature@atmel.com Web Site http://www.atmel.com Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2006. All rights reserved. Atmel(R), logo and combinations thereof are trademarks, and Everywhere You Are (R) are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 7601B-AUTO-02/06 /xM