ESD7205DT5G - ON SEMICONDUCTOR

January, 2019 − Rev. 6

1Publication Order Number:

ESD7205/D

ESD7205

ESD Protection Diode

Low Capacitance ESD Protection Diodes

for High Speed Data Line

The ESD7205 ESD protection diode array is designed to protect

high speed data lines from ESD. Ultra−low capacitance and low ESD

clamping voltage make this device an ideal solution for protecting

voltage sensitive high speed data lines. The small form factor,

flow−through style package allows for easy PCB layout and matched

trace lengths necessary to maintain consistent impedance between

high speed differential lines such as Ethernet and LVDS present in

automotive camera modules.

Features

•Low Capacitance (0.4 pF Typical, I/O to GND)

•Diode capacitance matching

•Protection for the Following IEC Standards:

IEC 61000−4−2 Level 4 (ESD)

•Low ESD Clamping Voltage (12 V Typical, +16 A TLP, I/O to GND)

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These Devices are Pb−Free and are RoHS Compliant

Typical Applications

•100BASE−T1 / OPEN Alliance BroadR−Reach Automotive Ethernet

•10/100/1000BASE−T1 Ethernet

•LVDS

•Automotive USB 2.0/3.0

•High Speed Differential Pairs

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Operating Junction Temperature Range TJ−55 to +150 °C

Storage Temperature Range Tstg −55 to +150 °C

Lead Solder Temperature −

Maximum (10 Seconds)

TL260 °C

IEC 61000−4−2 Contact

IEC 61000−4−2 Air

ISO 10605 330 pF / 330 W Contact

ISO 10605 330 pF / 2 kW Contact

ISO 10605 150 pF / 2 kW Contact

ESD ±25

±25

±20

±30

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

MARKING

DIAGRAMS

SOT−723

CASE 631AA

PIN CONFIGURATION

AND SCHEMATIC

www.onsemi.com

Pin 1 Pin 2

Pin 3

See detailed ordering, marking and shipping information in the

package dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

EA = Specific Device Code

M = Date Code

EA M

SC−70

CASE 419

(Note: Microdot may be in either location)

ECMG

EC = Specific Device Code

M = Date Code

G= Pb−Free Package

ESD7205

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ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Uni−Directional

IPP

VRWM

VCVBR

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working

Voltage

VRWM I/O Pin to GND 5.0 V

Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.2 6.0 8.0 V

Reverse Leakage

Current

IRVRWM = 5.0 V, I/O Pin to GND 1mA

Clamping Voltage

(Note 1)

VCIEC61000−4−2, ±8 kV Contact See Figures 3 and 4

Clamping Voltage TLP

(Note 2)

VCIPP = 8 A

IPP = 16 A

IPP = −8 A

IPP = −16 A

12.5

−4.0

−8.0

Junction Capacitance

Match

DCJVR = 0 V, f = 1 MHz between I/O1 to GND and I/O

2 to GND

5 10 %

Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND

ESD7205DT5G

ESD7205WTT1G

0.34

0.47

0.55

0.85

VR = 0 V, f = 1 MHz between I/O Pins

ESD7205DT5G

ESD7205WTT1G

0.20

0.23

0.35

0.40

3dB Bandwidth fBW RL = 50 W5 GHz

1. For test procedure see Figures 5 and 6 and application note AND8307/D.

2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.

TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

ESD7205

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Figure 1. IV Characteristics Figure 2. CV Characteristics

Figure 3. IEC61000−4−2 +8 kV Contact ESD

Clamping Voltage

−20

TIME (ns)

VOLTAGE (V)

−10 20 40 60 80 100 120 140

Figure 4. IEC61000−4−2 −8 kV Contact ESD

Clamping Voltage

−20

TIME (ns)

VOLTAGE (V)

0 20 40 80 120 140

−10

−20

−30

−40

−50

−60

−70

−80

−90 10060

I (A)

V (V)

C (pF)

VBias (V)

1.E−12

1.E−10

1.E−09

1.E−08

1.E−07

1.E−06

1.E−05

1.E−04

1.E−03

1.E−02

−10 1 2 3 4 5 6 7 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0123 589

1.E−11

−2104

I/O−GND

ESD7205

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IEC 61000−4−2 Spec.

Level

Test Volt-

age (kV)

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 5. IEC61000−4−2 Spec

Figure 6. Diagram of ESD Clamping Voltage Test Setup

50 W

Cable

Device

Under

Test Oscilloscope

ESD Gun

50 W

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

ESD7205

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Figure 7. Positive TLP IV Curve Figure 8. Negative TLP IV Curve

NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.

02 1816141246810

TLP CURRENT (A)

VOLTAGE (V)

−14

TLP CURRENT (A)

VOLTAGE (V)

−12

−10

−8

−6

−4

−2

−20

−18

−16

02 1816141246810 20

EQUIVALENT VIEC (kV)

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 9. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 10 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels.

Figure 9. Simplified Schematic of a Typical TLP

System

DUT

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

ESD7205

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Figure 11. RF Insertion Loss Figure 12. Capacitance over Frequency

CAPACITANCE (pF)

FREQUENCY

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.E+00 5.E+08 1.E+09 2.E+09 2.E+09 3.E+09 3.E+09

3.3 V

0 V

FREQUENCY (Hz)

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

1.E+06 1.E+07 1.E+08 1.E+09 1.E+10

ORDERING INFORMATION

Device Package Shipping†

ESD7205DT5G SOT−723

(Pb−Free)

8000 / Tape & Reel

SZESD7205DT5G* SOT−723

(Pb−Free)

8000 / Tape & Reel

ESD7205WTT1G SOT−323

(Pb−Free)

3000 / Tape & Reel

SZESD7205WTT1G* SOT−323

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

ESD7205

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PACKAGE DIMENSIONS

SOT−723

CASE 631AA

ISSUE D

DIM MIN NOM MAX

MILLIMETERS

A0.45 0.50 0.55

b0.15 0.21 0.27

b1 0.25 0.31 0.37

C0.07 0.12 0.17

D1.15 1.20 1.25

E0.75 0.80 0.85

e0.40 BSC

H1.15 1.20 1.25

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM

THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

−Y−

−X−

X0.08 Y

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

L2 0.15 0.20 0.25

0.29 REF

TOP VIEW

BOTTOM VIEW

SIDE VIEW

RECOMMENDED

DIMENSIONS: MILLIMETERS

0.40

1.50

PACKAGE

OUTLINE

0.27

0.52

3X 0.36

ESD7205

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PACKAGE DIMENSIONS

SC−70 (SOT−323)

CASE 419−04

ISSUE N

AA2

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

0.05 (0.002)

1.9

0.075

0.65

0.025

0.65

0.025

0.9

0.035

0.7

0.028 ǒmm

inchesǓ

SCALE 10:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DIM

MIN NOM MAX MIN

MILLIMETERS

0.80 0.90 1.00 0.032

INCHES

A1 0.00 0.05 0.10 0.000

A2 0.70 REF

b0.30 0.35 0.40 0.012

c0.10 0.18 0.25 0.004

D1.80 2.10 2.20 0.071

E1.15 1.24 1.35 0.045

e1.20 1.30 1.40 0.047

0.035 0.040

0.002 0.004

0.014 0.016

0.007 0.010

0.083 0.087

0.049 0.053

0.051 0.055

NOM MAX

2.00 2.10 2.40 0.079 0.083 0.095

e1 0.65 BSC

0.38

0.028 REF

0.026 BSC

0.015

0.20 0.56 0.008 0.022

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ESD7205/D

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