UT54ACS162245S RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver Advanced Datasheet May 20, 2002 FEATURES * Voltage translation - 3.3V bus to 2.5V bus - 2.5V bus to 3.3V bus * Cold/warm sparing all pins LOGIC SYMBOL (47) EL O EV DIR2 (2) 11 (46) (24) 12 (3) (44) (5) (43) 1A4 (41) 1A5 (40) 1A6 (38) 1A7 (37) 1A8 (36) 2A1 (6) 1A3 epitaxial CMOS technology and is ideal for space applications. This high speed, low power UT54ACS162245S low voltage transceiver is designed to perform multiple functions including: asynchronous two-way communication, signal buffering, voltage translation, warm and cold sparing. With V DD equal to zero volts, the UT54ACS162245S outputs and inputs present a minimum impedance of 1M making it ideal for "cold spare" applications. Balanced outputs and low "on" output impedance make the UT54ACS162245S well suited for driving high capacitance loads and low impedance backplanes. The UT54ACS162245S enables system designers to interface 2.5 volt CMOS compatible components with 3.3 volt CMOS components. For voltage translation, the A port interfaces with the 2.5 volt bus; the B port interfaces with the 3.3 volt bus. The direction control (DIRx) controls the direction of data flow. The output enable (OEx) overrides the direction control and disables both ports. These signals can be driven from either port A or B. The direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. 2EN1 (BA) 2EN2 (AB) 1EN1 (BA) 1EN2 (AB) PM EN 1A2 The 16-bit wide UT54ACS162245S MultiPurpose low voltage transceiver is built using Aeroflex UTMC's Commercial 2A2 (8) (9) 1B2 1B3 1B4 1B5 1B6 (11) 1B7 (12) 1B8 (13) 2B1 21 22 (35) (14) (33) (16) (32) 2A4 (30) 2A5 (29) 2A6 (27) 2A7 (26) 2A8 (17) 2A3 1B1 (19) (20) 2B2 2B3 2B4 2B5 2B6 (22) 2B7 (23) 2B8 PIN DESCRIPTION Pin Names IN D G2 1A1 DESCRIPTION RadHard TM G1 T * 0.25 Commercial RadHard TM CMOS - Total dose: 300Krad(Si) and 1Mrad)Si) - Single Event Latchup immune * High speed, low power consumption * Schmitt trigger inputs to filter noisy signals * Cold and Warm Spare - all outputs * Available QML Q or V processes * Standard Microcircuit Drawing TBD * Package: - 48-lead flatpack, 25 mil pitch (.390 x .640) O E1 (48) O E2 (25) (1) DIR1 1 Description O Ex Output Enable Input (Active Low) DIRx Direction Control Inputs xAx Side A Inputs or 3-State Outputs (2.5V Port) xBx Side B Inputs or 3-State Outputs (3.3V Port) POWER TABLE DIR1 1 48 OE1 1B1 2 47 1A1 1B2 3 46 V SS 45 44 1A2 V SS 1B3 4 5 1B4 6 43 1A4 VDD1 7 42 VDD2 1B5 8 9 41 40 1A5 10 39 1A6 V SS 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 V SS 14 15 35 34 2A2 2B3 16 33 2A3 2B4 17 32 2A4 VDD1 2B5 18 19 20 21 31 30 29 28 VDD2 2A5 2A6 V SS 22 23 24 27 26 25 2A7 2A8 Voltage Translator 3.3 Volts 3.3 Volts Non Translating 2.5 Volts 2.5 Volts Non Translating ENABLE O Ex DIRECTION DIRx OPERATION L L B Data To A Bus L H A Data To B Bus H X Isolation The device will place all outputs into a high-impedance state if either VDD supply is taken to zero volts (I WS , warm spare), or if both VDD supplies are set to zero volts (I CS, cold spare). DEVICE POWER UP FUNCTION The device will place all outputs into a high-impedance during power-up. The high impedance state is maintained for a time period approximately equal to the rise time of V DD1 . EL O DIR2 2.5 Volts COLD/WARM SPARE FUNCTION O E2 EV 2B7 2B8 3.3 Volts FUNCTION TABLE D 2B6 V SS V SS OPERATION When V DD2 is at 2.5 volts, either 2.5 or 3.3 volts CMOS logic levels can be applied to all control inputs. For proper operation connect power to all V DD and ground all V SS pins (i.e., no floating V DD or VSS input pins). Tie unused inputs to VSS . Always insure V DD1 > V DD2 during operation of the part. IN 1B6 V SS 1A3 Port A T 48-Lead Flatpack Top View Port B PM EN PINOUTS 2 LOGIC DIAGRAM 2A1 2A6 (38) 2A7 (11) 1B7 (37) EL O 2A8 1B8 EV (12) D 1A8 1B6 3 2B4 (30) 1B5 (40) (9) 1A7 (17) 2A5 2B3 (32) T (41) (8) 1A6 1B4 2A4 PM EN (6) 1A5 (16) (43) 2B2 (33) 1B3 IN 2.5V PORT 1A4 (14) 2A3 2B1 (35) 1B2 (44) OE 2 (36) (13) 2A2 (5) (25) 1B1 (46) (3) 1A3 (24) O E1 (47) (2) 1A2 DIR2 2.5V PORT 1A1 (48) (19) 2B5 (29) (20) 2B6 (27) (22) 2B7 (26) (23) 2B8 3.3 V PORT (1) 3.3 V PORT DIR1 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E5 rad(Si) SEL Latchup >120 MeV-cm2 /mg Neutron Fluence (Note 2) 1.0E14 n/cm 2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Not tested, inherent of CMOS technology. ABSOLUTE MAXIMUM RATINGS 1 LIMIT (Mil only) UNITS V I/O (Note 2) Voltage any pin -.3 to V DD1 +.3 V V DD1 Supply voltage -0.3 to 4.0 V V DD2 Supply voltage -0.3 to 4.0 V TSTG Storage Temperature range -65 to +150 C Maximum junction temperature +150 C TJ (Note 3) T PARAMETER PM EN SYMBOL JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W EL O Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability and performance . 2. For Cold Spare mode (V DD1 =V SS, V DD2 =VSS ), VI/O may be -0.3V to the maximum recomended operating level of V DD1 +0.3V. 3. Maximum junction temperature may be increased to +175 oC during burn-in and life test. EV DUAL SUPPLY OPERATING CONDITIONS SYMBOL VIN TC IN V DD2 D V DD1 PARAMETER LIMIT UNITS Supply voltage 2.3 to 3.6 V Supply voltage 2.3 to 3.6 V Input voltage any pin 0 to VDD1 V Temperature range -55 to + 125 C 4 DC ELECTRICAL CHARACTERISTICS ( -55C < TC < +125C) 1 SYMBOL PARAMETER CONDITION MIN MAX UNIT V T+ Schmitt Trigger, positive going threshold2 VDD from 2.3 to 3.6 .7VDD V VT - Schmitt Trigger, negative going threshold2 VDD from 2.3 to 3.6 .3V DD V VH1 Schmitt Trigger range of hysteresis9 VDD from 3.0 to 3.6 0.4 V VH2 Schmitt Trigger range of hysteresis9 VDD from 2.3 to 2.7 0.4 V I IN Input leakage current 9 VDD from 2.7 to 3.6 -1 3 A -1 3 A -1 5 A -5 5 A -200 200 mA -100 100 mA 0.4 V VIN = VDD or VSS IOZ VDD from 2.7 to 3.6 Three-state output leakage current9 VIN = VDD or VSS VIN = 3.6 Cold sparing input leakage current 3 VDD = VSS Warm sparing input leakage current11 VIN = VSS or VDD, V DD1 = 0 PM EN IWS T I CS VDD2 = V DD or V DD1 = V DD, VDD2 = 0 I OS1 VO = V DD or V SS Short-circuit output current 5, 10 VDD from 3.0 to 3.6 I OS2 VO = V DD or V SS Short-circuit output current 5, 10 V OL1 Low-level output voltage9 EL O VDD from 2.3 to 2.7 IOL= 8mA IOL= 100A 0.2 High-level output voltage9 IN VOH1 Low-level output voltage9 D V OL2 EV VDD = 3.0 VOH2 High-level output voltage9 IOL= 8mA 0.5 IOL= 100A 0.2 VDD = 2.3 IOH = -8mA IOH = -100A VDD = 3.0 IOH = -8mA IOH = -100A VDD = 2.3 5 V VDD - 0.7 V VDD - 0.2 VDD - 0.9 VDD - 0.2 V P total1 Power dissipation CL = 50pF 4, 6, 7 TBD mW/ MHz TBD mW/ MHz A A V DD from 3.0 to 3.6 P total2 CL = 50pF Power dissipation 4, 6, 7 V DD from 2.3 to 2.7 I DD Standby Supply Current V DD1 or V DD2 V IN = VDD or VSS V DD = 3.6 Pre-Rad 25oC OE=V DD Pre-Rad -55 C to +125 C OE=V DD TBD TBD Post-Rad 25oC OE=V DD TBD A Input capacitance 8 = 1MHz @ 0V 15 pF 15 pF o CIN o V DD from 2.3 to 3.6 = 1MHz @ 0V Output capacitance8 V DD from 2.3 to 3.6 T COUT IN D EV EL O PM EN Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = V IH (min) + 20%, - 0%; V IL = VIL (max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 3. All combinations of OEx and DIRx 4. Guaranteed by characterization. 5. Not more than one output may be shorted at a time for maximum duration of one second. 6. Power does not include power contribution of any CMOS output sink current. 7. Power dissipation specified per switching output. 8.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V SS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 9.Guaranteed; tested on a sample of pins per device. 10. Supplied as a design limit, but not guaranteed or tested. 11. 0 Volts is defined as 0V +/- 0.4Volts. 6 AC ELECTRICAL CHARACTERISTICS1 (Port B = 3.3 Volt, Port A = 2.5 Volt) (V DD1 = 3.0V to 3.6V; V DD2 = 2.3V to 2.7V, -55C < T C < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT Propagation delay Data to Bus 2 10 ns tPHL Propagation delay Data to Bus 2 10 ns tPZL Output enable time OEx to Bus 2 12 ns tPZH Output enable time OEx to Bus 2 12 ns tPLZ Output disable time OEx to Bus high impedance 2 15 ns tPHZ Output disable time OEx to Bus high impedance 2 15 ns tPZL2 Output enable time DIRx to Bus 2 12 ns tPZH 2 Output enable time DIRx to Bus 2 12 ns tPLZ2 Output disable time DIRx to Bus high impedance 2 15 ns tPHZ 2 Output disable time DIRx to Bus high impedance 2 15 ns tSKEW Skew between outputs (50pF +/- 10 pF on each output) 900 ps PM EN T tPLH 50 Notes: 1. All specifications valid for radiation dose 1E5 rad (Si) per MIL-STD-883, Method 1019. Propagation Delay Input Control Input D tPZL IN 3.3V Output Normally Low 3.3V Output Normally High EV Output Enable Disable Times VOH VDD /2 VOL tPLZ VDD /2-0.2 .2V DD + .2V tPHZ tPZH VDD /2+0.2 tPZL 2.5V Output Normally Low 2.5V Output Normally High tPHL EL O tPLH VDD VDD /2 0V .8V DD - .2V tPLZ V DD/2-0.2 .2V DD + .2V tPHZ tPZH V DD/2+0.2 7 .7VDD - .2V VDD VDD /2 0V VDD /2 .2VDD .8VDD VDD /2 V DD/2 .2V DD .7V DD V DD/2 AC ELECTRICAL CHARACTERISTICS 1 (Port A = Port B, 3.3 Volt Operation) (V DD1 = 3.0 to 3.6V; V DD2 = 3.0V to 3.6V, -55C < TC < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT Propagation delay Data to Bus 2 7.5 ns tPHL Propagation delay Data to Bus 2 7.5 ns tPZL Output enable time OEx to Bus 2 10 ns tPZH Output enable time OEx to Bus 2 10 ns tPLZ Output disable time OEx to Bus high impedance 2 12 ns tPHZ Output disable time OEx to Bus high impedance 2 12 ns tPZL 2 Output enable time DIRx to Bus 2 10 ns tPZH 2 Output enable time DIRx to Bus 2 10 ns tPLZ 2 Output disable time DIRx to Bus high impedance 2 12 ns tPHZ 2 Output disable time DIRx to Bus high impedance 2 12 ns tSKEW Skew between outputs (50pF +/- 10 pF on each output) 900 ps PM EN T tPLH 50 Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested Propagation Delay Input EL O tPLH tPHL VOH VDD /2 VOL EV Output VDD VDD /2 0V Control Input IN 3.3V Output Normally Low 3.3V Output Normally High D Enable Disable Times tPZL tPLZ V DD/2-0.2 .2V DD + .2V tPHZ tPZH VDD /2+0.2 8 .8V DD - .2V VDD VDD /2 0V VDD /2 .2VDD .8VDD VDD /2 AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 2.5 Volt Operation) (V DD1 = 2.3V TO 2.7V; VDD2 = 2.3V to 2.7V, -55C < TC < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT Propagation delay Data to Bus 2 10 ns tPHL Propagation delay Data to Bus 2 10 ns tPZL Output enable time OEx to Bus 2 12 ns tPZH Output enable time OEx to Bus 2 12 ns tPLZ Output disable time OEx to Bus high impedance 2 15 ns tPHZ Output disable time OEx to Bus high impedance 2 15 ns tPZL2 Output enable time DIRx to Bus 2 12 ns tPZH 2 Output enable time DIRx to Bus 2 12 ns tPLZ2 Output disable time DIRx to Bus high impedance 2 15 ns tPHZ 2 Output disable time DIRx to Bus high impedance 2 15 ns tSKEW Skew between outputs (50pF +/- 10 pF on each output) 900 ps PM EN T tPLH 50 Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested. Propagation Delay EL O Input tPLH Control Input IN 2.5V Output Normally Low 2.5V Output Normally High D Enable Disable Times EV Output tPZL V DD V DD /2 0V tPHL V OH V DD /2 V OL tPLZ VDD /2-0.2 .2V DD + .2V tPHZ tPZH V DD /2+0.2 9 .7VDD - .2V V DD V DD /2 0V V DD /2 .2V DD .7VDD V DD /2 PACKAGE 4 EV EL O 6 PM EN T 5 D 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. IN 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003. Figure 1. 48-Lead Flatpack 10 6 ORDERING INFORMATION UT54ACS162245S: SMD 5962 R 98580 01 * * * Lead Finish: (C) = Gold Case Outline: (X) = 48 lead BB FP (Gold only) Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 16-bit MultiPurpose Low Voltage T ransceiver PM EN Total Dose: (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) (G) = 5E5 rad(Si) (H) = 1E6 rad(Si) T Drawing Number: 98580 IN D EV EL O Notes: 1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 11 UT54ACS162245S UT54 *** ****** * * * Lead Finish: (C) = Gold Screening: (C) = Mil Temp (P) = Prototype Package Type: 48-lead BB FP (Gold only) Part Number: I/O Type: (ACS)= PM EN (16245SLV ) = 16-bit MultiPurpose Low Voltage Transceiver T (U) = CMOS compatible I/O Level EL O UTMC Core Part Number IN D EV Notes: 1. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation n either tested nor guaranteed. 2. Prototype flow per UTMC Manufacturing Flows Document Tested at 25C only. Lead finish is gold only. 12