QorIQ Communications Platforms T Series QorIQ T1040/20 and T1042/22 communication processors Overview e5500 Core The QorIQ T1 family of communications The T1 family is based on the 64-bit e5500 processors combines up to four 64-bit cores, Power Architecture core, which uses a seven- built on Power Architecture(R) technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral DPAA Hardware Accelerators Frame manager (FMAN) 13 Gb/s classify, parse and distribute stage pipeline for low latency response to Buffer manager (BMAN) 64 buffer pools unpredictable code execution paths, boosting Queue manager (QMAN) Up to 224 queues single-threaded performance. Security (SEC) 5 Gb/s: 3DES, AES bus interfaces required for networking and telecommunications. This scalable, pin- e5500 Core Features compatible family also features the industry's * Supports up to 1.4 GHz core frequencies first 64-bit embedded processor with an integrated Gigabit Ethernet switch, the T1040 * Tightly coupled low latency cache hierarchy (and dual-core T1020), which simplifies * 32 KB I/D (L1), 256 KB L2 per core hardware design, reduces power and overall * Up to 256 KB of shared platform cache (L3) system cost. Target Markets and Applications The T1 family is ideally suited for use in mixed control and data plane applications such as fixed routers, switches, Internet access devices, firewall and other packet filtering applications, as well as generalpurpose embedded computing. Its high level of integration offers significant performance benefits and greatly helps to simplify board design. * Enterprise equipment: Fixed routers, Ethernet switches, UTM equipment * Service provider: Edge routers, mobile backhaul Data Path Acceleration Architecture (DPAA) The T1 family integrates the QorIQ DPAA, an innovative multicore infrastructure for scheduling work to cores (physical and virtual), hardware accelerators and network interfaces. * 3.0 DMIPS/MHz per core The FMAN, a primary element of the DPAA, * Up to 64 GB of addressable parses headers from incoming packets, then memory space classifies and selects data buffers with optional policing and congestion management. The * Hybrid 32-bit mode to support legacy FMAN passes its work to the QMAN which software and seamless transition to assigns it to cores or accelerators with a 64-bit architecture multilevel scheduling hierarchy. Virtualization Gigabit Ethernet Switch The T1 family includes support for hardware- The T1040 and T1020 processors include assisted virtualization. The e5500 core offers an integrated gigabit Ethernet switch that an extra core privilege level (hypervisor). supports wire-speed switching for all packet Virtualization software for the T1 family includes sizes. Other features include VLAN, QoS kernel-based virtual machine (KVM), Linux(R) processing and ACLs. OS containers, Freescale hypervisor and commercial virtualization software from Green Hills(R) Software and Enea(R). * Aerospace, defense and government: Ruggedized network appliances QorIQ T1040/20 andCommunications T1042/22 Processors Communications QorIQ T1040/20 and T1042/22 Processors * Industrial computing: Single board 256 KB Backside L2 Cache 32 KB D Cache 32 KB I Cache Security Fuse Processor SDXC/eMMC Security 5.4 Queue (XoR CRC) Mgr. 2x DUART 4x I2C SPI, GPIO 2x USB 2.0 w/PHY Pattern Buffer Match Mgr. Engine 2.0 DIU Core Complex (CPU, L2, L3 Cache) Parse, Classify, Distribute 1 GbE T1042/T1022 Only T1040: 2x DMA, T1042: 4x DMA 1 GbE 1 GbE 1 GbE 1 GbE 8 Port Switch 1 GbE 1 GbE 1 GbE 1 GbE 1 GbE 1 GbE 1 GbE 1 GbE T1040/ T1020 Only PAMU QUICC Engine TDM/HDLC Power Management PAMU SATA 2.0 16-bit IFC CoreNetTM Coherency Fabric PAMU PAMU TDM/HDLC Security Monitor 32/64-bit DDR3L/4 Memory Controller 256 KB Platform Cache SATA 2.0 smart grid Power Architecture(R) e5500 PCle PCle PCle PCle computers, factory automation, Peripheral Access Mgmt. Unit Real-Time Debug Watchpoint Cross Trigger Perf. Monitor Trace Aurora 8-Lane 5 GHz SerDes Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements T1 Family Comparison CPU T1020 T1022 T1040 T1042 T2081 2 e5500 2 e5500 4 e5500 4 e5500 4 e6500 (dual threaded) 1200-1400 MHz 1200-1400 MHz 1200-1400 MHz 1200-1400 MHz 1500-1800 MHz 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3/3L to 22133 MT/s 10/100/1000 Ethernet (with IEEE(R) 1588v2) 8-port GbE switch + 4x 1 GbE 5x 1 GbE 8-port GbE switch + 4x 1 GbE 5x 1 GbE 2x 1/10 GbE + 6x 1 GbE SerDes Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (10 GHz) DDR I/F Package Pin compatible System Peripherals and Networking For networking, the FMAN supports up to five 1 Gb/s MAC controllers that connect to PHYs, switches and backplanes over RGMII and SGMII. The T1040 and T1020 processors also include an integrated 8-port Gigabit Ethernet switch, which supports QSGMII or SGMII interfaces. High-speed system expansion is supported through three PCI Express(R) V2.0 controllers that support a variety of lane widths. Other peripherals include SATA, SD/MMC, I2C, UART, SPI, NOR/NAND controller, GPIO and a 1600 MT/s DDR3L/4 controller. Software and Tool Support T1 Family Feature List Two or four e5500 single-threaded cores built on Power Architecture(R) technology * Up to 1.4 GHz with 64-bit ISA support * Three levels of instructions: User, supervisor, hypervisor * Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture CoreNet platform cache * 256 KB shared platform cache Hierarchical interconnect fabric * CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints * QMAN fabric supporting packet-level queue management and quality of service 64-bit DDR3L/4 SDRAM memory controller with ECC support * Up to 1600 MT/s DPAA incorporating acceleration Freescale and our partner network deliver a for the following functions wide range of tools, run-time software, reference solutions and services to accelerate your designs. * Packet parsing, classification and distribution * Queue management for scheduling, packet sequencing and congestion management * Hardware buffer management for buffer allocation and de-allocation * Cryptography acceleration (SEC 5.x) * QorIQ reference design boards SerDes * Eight lanes at up to 5 Gb/s * Supports SGMII, QSGMII, PCI Express(R) and SATA * CodeWarrior Development Studio for Power Architecture Ethernet interfaces * Freescale Linux SDK * 8-port Gigabit Ethernet switch (available with T1040 and T1020 only) * Up to 5x 1 Gb/s Ethernet MACs QUICC Engine module * Support for legacy protocols TDM, HDLC, UART and ISDN * Reference Platforms High-speed peripheral interfaces * Four PCI Express 2.0 controllers Enterprise WLAN Access Point * VortiQa Application Software AIS-Application Identification Software Additional peripheral interfaces Enterprise Software for Networking ONS-Open Network Switch Software OND-Open Network Director Software * Professional Services & Support Commercial Services * * * * * * * Two serial ATA (SATA 2.0) controllers Two High-Speed USB 2.0 controllers with integrated PHYs Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface Two I2C controllers Four UARTS Integrated flash controller supporting NAND and NOR flash memory DMA * Dual four channel Support for hardware virtualization and partitioning enforcement * Extra privileged level for hypervisor support QorIQ trust architecture * Secure boot, secure debug, tamper detection, volatile key storage Linux SDK Support Package Reference Design Software (RDS) Support Package * Third Party Software and Tools Enea, Green Hills, Mentor Graphics and Wind River For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet and QUICC Engine are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. (c) 2012, 2013 Freescale Semiconductor, Inc. Document Number: T1FAMILYFS REV 1