IBM043616CBLBC
IBM041816CBLBC
16Mb (512K x 36 & 1M x 18) SRAM
CBLBCds.fm.00
June 3, 2002 Page 13 of 25
AC Characteristics (TA = 0 to +85°C, VDD = 2.5 V +10/− 5%)
Symbol Parameter
-22 -24 -27 -30
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max.
tKHKH Cycle Time 2.2 2.4 2.7 3.0 ns
tKHKL Clock High Pulse Width 1.0 1.0 1.3 1.4 ns
tKLKH Clock Low Pulse Width 1.0 1.0 1.3 1.4 ns
tAVKH Address Setup Time 0.25 0.25 0.3 0.3 ns 1, 8, 5, 7
tKHAX Address Hold Time 0.25 0.25 0.3 0.3 ns 1, 8, 5, 7
tBVKH Function Control (B1, B2, B3) Setup Time 0.25 0.25 0.3 0.3 ns 1, 8, 5, 7
tKHBX Function Control (B1, B2, B3) Hold Time 0.25 0.25 0.3 0.3 ns 1, 8, 5, 7
tDVKH Data In Setup Time 0.21 0.21 0.25 0.25 ns 1, 8, 5, 7
tKHDX Data In Hold Time 0.21 0.21 0.25 0.25 ns 1, 8, 5, 7
tINPW Input Pulse Width 0.8 0.8 1.0 1.0 6
tCHCL Echo Clock (CQ) High Pulse Width tKHKL-
0.1
tKHKL+
0.1
tKHKL-
0.1
tKHKL+
0.1
tKHKL-
0.1
tKHKL+
0.1
tKHKL-
0.1
tKHKL+
0.1 ns 1, 2, 5
tCLCH Echo Clock (CQ) Low Pulse Width tKLKH-
0.1
tKLKH+
0.1
tKLKH-
0.1
tKLKH+
0.1
tKLKH-
0.1
tKLKH+
0.1
tKLKH-
0.1
tKLKH+
0.1 ns 1, 2 5
tKXCV Clock (CK) crossing to Echo Clock (CQ)
Valid 0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns 1, 3, 5
tKXQV Clock (CK) crossing to Output Valid 0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns 1, 5
tKXQZ Clock (CK) crossing to Output High-Z 0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns 1, 5
tKXQLZ Clock (CK) crossing to Output Active 0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns 1, 5
tQVTRK
Echo Clock (CQ) Valid to Output Valid
Tracking (tKXCV - tKXQV)-0.15 0.15 -0.15 0.15 -0.15 0.15 -0.2 0.2 ns 1, 2, 4, 5
tQZTRK
Echo Clock (CQ) Valid to Output High-Z
Tracking (tKXCV - tKXQZ)-0.15 0.15 -0.15 0.15 -0.15 0.15 -0.2 0.2 ns 1, 2, 4, 5
tQLZTRK
Echo Clock (CQ) Valid to Output Active
Tracking (tKXCV - tKXQLZ)-0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 ns 1, 2, 4, 5
tGHQZ Output Enable (G) High to High-Z 0.3 1.7 0.3 1.7 0.3 1.7 0.3 2.0 ns 2
tGLQV Output Enable (G) Low to Output Valid 0.3 1.7 0.3 1.7 0.3 1.7 0.3 2.0 ns 2
1. See AC Test Loading on page 12.
2. These parameters may not be tested at the values shown in this table, and may only be guaranteed by design.
3. Echo Clock (CQ) Valid refers to CQ and CQ rising and falling edges.
4. The tracking between echo-clock access times and DQ access times is across all cycle boundaries for any given SRAM address
and function pattern.
5. CK and CK clocks must be used differentially in order to meet specification.
6. Inputs to switch a maximum of once per applied cycle. For example, Data equals (TKHKH)/2; Address and Controls equal TKHKH.
7. To guarantee AC characteristics; VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these conditions
are not met then:
• Setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels.
• Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
8. Guaranteed by design and tested without guardband.