IBM043616CBLBC-24 - IBM Microelectronics

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

CBLBCds.fm.00

June 3, 2002 Page 1 of 25

Features

• 512K x 36 or 1M x 18 organization

•CMOS technology

• Double-data-rate and single-data-rate synchro-

nous mode of operation

• Pipeline mode of operation

• Self-timed late write with full data coherency

• Single differential clock

• 1.8V high-speed transceiver logic (HSTL) I/O

• 2.5V power supply, 1.8V VDDQ

• Registered addresses, controls, and data-ins

• Burst mode of operation

• Common I/O

• Asynchronous output enable

• Boundary scan using a limited set of JTAG

1149.1 functions

• 9 x 17 bump ball grid array package with SRAM

JEDEC standard pinout and boundary SCAN

order

• Programmable impedance output driver

Description

The IBM043616CBLBC and IBM041816CBLBC

16Mb SRAMs are synchronous pipeline-mode, high-

performance CMOS static random-access memo-

ries that have wide I/O and achieve 2.2ns cycle

times. Single differential CK clocks are used to ini-

tialize the read/write operation, and all internal oper-

ations are self-timed. At the rising edge of the CK

clock, addresses and controls are registered inter-

nally. Data-outs are updated from output registers

on the next rising and falling edges of the CK clock,

hence the double data rate. Internal write buffers

allow write data to follow one cycle after addresses

and controls. The SRAM is operated with a single

2.5V power supply and is compatible with HSTL I/O

interfaces.

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 2 of 25

CBLBCds.fm.00

June 3, 2002

x36 BGA Bump Layout (Top View)

123456789

A VSS VDDQ SA13 SA11 ZQ SA10 SA8 VDDQ VSS

B DQ23 DQ20 SA14 VSS B1 VSS SA7 DQ15 DQ12

C VSS VDDQ SA15 SA12 G SA9 SA6 VDDQ VSS

D DQ24 DQ21 SA18 VSS VDD VSS SA5 DQ14 DQ11

E VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

F DQ25 CQ DQ18 VDD VDD VDD DQ17 CQ DQ10

G VSS VDDQ VSS VSS CK VSS VSS VDDQ VSS

H DQ26 DQ22 DQ19 VDD CK VDD DQ16 DQ13 DQ9

J VSS VDDQ VSS VDD VDD VDD VSS VDDQ VSS

K DQ27 DQ31 DQ34 VSS B2 VSS DQ1 DQ4 DQ8

L VSS VDDQ VSS LBO B3 MODE1VSS VDDQ VSS

M DQ28 CQ DQ35 VDD VDD VDD DQ0 CQ DQ7

N VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

P DQ29 DQ32 NC VSS VDD VSS SA4 DQ3 DQ6

R VSS VDDQ VDD SA17 SA1 SA2 VDD VDDQ VSS

T DQ30 DQ33 SA16 VSS SA0 VSS SA3 DQ2 DQ5

U VSS VDDQ TMS TDI TCK TDO NC2VDDQ VSS

1. Connect the Mode pin to VSS. The Mode pin has a very small pull down, less than 5µA current at VDD input.

2. ESD protection diodes reside on this NC bump.

x18 BGA Bump Layout (Top View)

123456789

A VSS VDDQ SA13 SA11 ZQ SA10 SA8 VDDQ VSS

B NC DQ10 SA14 VSS B1 VSS SA7 NC DQ5

C VSS VDDQ SA15 SA12 G SA9 SA6 VDDQ VSS

D DQ11 NC SA18 VSS VDD VSS SA5 DQ7 NC

E VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

F NC CQ NC VDD VDD VDD DQ8 NC DQ4

G VSS VDDQ VSS VSS CK VSS VSS VDDQ VSS

H DQ12 NC DQ9 VDD CK VDD NC DQ6 NC

J VSS VDDQ VSS VDD VDD VDD VSS VDDQ VSS

K NC DQ15 NC VSS B2 VSS DQ0 NC DQ3

L VSS VDDQ VSS LBO B3 MODE1VSS VDDQ VSS

M DQ13 NC DQ17 VDD VDD VDD NC CQ NC

N VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

P NC DQ16 SA19 VSS VDD VSS SA4 NC DQ2

R VSS VDDQ VDD SA17 SA1 SA2 VDD VDDQ VSS

T DQ14 NC SA16 VSS SA0 VSS SA3 DQ1 NC

U VSS VDDQ TMS TDI TCK TDO NC2VDDQ VSS

1. Connect the Mode pin to VSS. The Mode pin has a very small pull down, less than 5µA current at VDD input.

2. ESD protection diodes reside on this NC bump.

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

CBLBCds.fm.00

June 3, 2002 Page 3 of 25

Pin Description

SA0–SA19 Address Input (SA0–SA1 burst-control start-

ing addresses) TDO IEEE 1149.1 Test Output (LVTTL level)

DQ0–DQ35 Data I/O G Asynchronous Output Enable

CQ, CQ Differential Echo Clocks MODE

Mode Pin. Connect to VSS. A waiver to float Mode

may be obtained; contact your field applications

engineer (FAE).

CK, CK Differential Input Register Clocks VREF HSTL Input Reference Voltage

B1 B1 = 0 initiates a Load operation VDD Power Supply (2.5V)

B2 B2 = 0 initiates a Write operation VSS Ground

B3 B3 = 0 Double Data Rate,

B3 = 1 Single Data Rate VDDQ Output Power Supply

LBO

Linear Burst Order (LBO = 1, interleave

mode; LBO = 0, linear mode), (can be tied to

VDD or VSS)

ZQ Output Driver Impedance Control

TMS, TDI, TCK IEEE 1149.1 Test Inputs (LVTTL levels) NC No Connect

Ordering Information

Part Number Organization Cycle Time (ns) Package

IBM043616CBLBC-22 512K x 36 2.2 9 x 17 BGA

IBM043616CBLBC-24 512K x 36 2.4 9 x 17 BGA

IBM043616CBLBC-27 512K x 36 2.7 9 x 17 BGA

IBM043616CBLBC-30 512K x 36 3.0 9 x 17 BGA

IBM041816CBLBC-22 1M x 18 2.2 9 x 17 BGA

IBM041816CBLBC-24 1M x 18 2.4 9 x 17 BGA

IBM041816CBLBC-27 1M x 18 2.7 9 x 17 BGA

IBM041816CBLBC-30 1M x 18 3.0 9 x 17 BGA

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 4 of 25

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June 3, 2002

Block Diagram (x36 Double Data Rate Mode)

256K x 72

Buffer

Write

Decode

2:1 Mux

DQ0-DQ35

Read Add

Reg

Compare

CK,CK

B1-B3

SA0-SA18

Array

101

Buffer

Write

01 01

REG

Output Output

REG

36 36

REG

Output Output

REG

CQa,CQa

CQb,CQb

01 01

VDD VSS

Write

Add Reg

Burst

Logic

A2-A18

A0,A1 A0’,A1’

A0’ A0’

Control

Logic

Load

Write

Output Enable

Advance

Match

36 36

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

CBLBCds.fm.00

June 3, 2002 Page 5 of 25

SRAM Features

Double Data Rate (DDR) and Single Data Rate (SDR) Modes

The timing diagram on page 6 shows input and output data placements for both DDR and SDR modes. In

DDR read mode, two sets of data-outs are generated from the second rising and falling edges of the CK

clock, assuming the first rising edge of the CK clock samples the base address. The first of the two data-out

sets (DOUT-A) is generated from the sampled base address (Base-A). The second data-out set (DOUT-A’) is

generated from the next burst-order address, according to the burst-order definition. Similarly, a DDR write

requires data-in placement on the second rising and falling CK edges. In SDR read mode, only one set of

data-outs is generated from the second rising CK edge. In SDR write mode, one set of data-ins is sampled on

the second rising CK edge. The user may switch from DDR to SDR mode (or vice-versa) during any LOAD

(B1 = 0) operation.

Late Write

The late-write function allows write data to be registered one cycle after addresses and controls. This feature

eliminates one of two bus-turnaround cycles normally required when going from a read to a write operation.

Late write is accomplished by buffering write addresses and data. The SRAM array update occurs during the

third write cycle. Read-cycle addresses are monitored to determine if read data is to be supplied from the

SRAM array or the write buffer. Full data coherency is maintained for both DDR and SDR operations. As a

result, NOP (write buffer flush) operations are not required going from write cycles to read cycles.

Echo Clocks

Echo clocks CQ and CQ are generated from rising and falling edges of the CK clock, with access times repre-

sentative of the data-outs. Echo clocks keep running during write and NOP operations. Echo-clock operation

is identical for both double-data-rate and single-data-rate operations. The close tracking of echo clocks and

data-out timings allows the echo clocks to be used as capture clocks for the data-outs by the receiving

device.

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 6 of 25

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June 3, 2002

Programmable Impedance and Power-Up Requirements

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to

adjust its output driver impedance. The value of RQ must be five times the value of the intended line imped-

ance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of

15% is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary because

the impedance is affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock

cycles, and each evaluation may move the output driver impedance level one step at a time towards the opti-

mum level. The output driver has 64 discrete binary weighted steps. Impedance updates for zeros occur

whenever the SRAM is driving ones for the same DQs; impedance updates for ones occur whenever SRAM

is driving zeros for the same DQs. Updates of both zeros and ones occur when the SRAM is High-Z. Further-

more, to guarantee the output driver impedance, the SRAM requires 2048 clock cycles and a Read ‘0’ and

Read ‘1’ or a Read ‘1’ and a Read ‘0’ across all used outputs. The RC time constant of the loaded RQ trace

must be less than 3ns.

Power-Up and Power-Down Sequences

The power supplies need to be powered up in the following sequence: VDD, VDDQ, VREF, followed by inputs.

The power-down sequence must be the reverse. VDDQ must not exceed VDD.

Initial Writes

DQ and CQ timings will not be guaranteed until at least two write cycles are performed. These cycles can be

part of the programmable impedance initial cycles.

Timing Diagram: Double Data Rate and Single Data Rate Modes

SA/Bs

CK,CK

DOUT-A DOUT-A’ DOUT-B

DIN-A DIN-A’ DIN-B DIN-B’

DIN-A DIN-B

DOUT-B’

Base-A Base-B Base-C Base-D

CQ,CQ

DOUT-C

DQ: DDR READ

DQ: SDR READ DOUT-B

DOUT-A DOUT-C

DIN-C DIN-C’

DQ: DDR WRITE

DIN-C

DQ: SDR WRITE

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

CBLBCds.fm.00

June 3, 2002 Page 7 of 25

Function Control

The function control is dependent on the state of the three function control pins (B1, B2, and B3), captured

when CK transitions from low to high as described in the following table (“n” refers to the current cycle and

“n-1” refers to the previous SRAM cycle).

Burst Order Definition

The DC state of the LBO pin determines the burst order of the addresses, given the starting address in a

Load operation (B1 = 0). The following table defines the order of addresses for the two different states of

LBO.

B1 (n-1) B2 (n-1) B3 (n-1) B1 (n) B2 (n) B3 (n) Function (n)

X X X 0 0 0 Load New Address, Double Data Rate (DDR) Write

X X X 0 0 1 Load New Address, Single Data Rate (SDR) Write

X X X 0 1 0 Load New Address, DDR Read

X X X 0 1 1 Load New Address, SDR Read

0 0 0 1 1 X Continue Burst, DDR Write

0 0 1 1 1 X Continue Burst, SDR Write

0 1 0 1 1 X Continue Burst, DDR Read

0 1 1 1 1 X Continue Burst, SDR Read

X X X 1 0 X NOP (High-Z cycle n+1)

1 0 X 1 X X NOP (High-Z cycle n+2)

Address Sequence when LBO = VDD (Interleave Burst)

SA1 SA0 SA1 SA0 SA1 SA0 SA1 SA0

Starting address 00011011

Second address 01001110

Third address 10110001

Fourth address 11100100

Address Sequence when LBO = VSS (Linear Burst)

SA1 SA0 SA1 SA0 SA1 SA0 SA1 SA0

Starting address 0 0 0 1 1 0 1 1

Second address 0 1 1 0 1 1 0 0

Third address 1 0 1 1 0 0 0 1

Fourth address 1 1 0 0 0 1 1 0

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 8 of 25

CBLBCds.fm.00

June 3, 2002

Clock Truth Table

CK B1 (n) B2 (n) B3 (n) DQ (n) DQ (n + 1) DQ (n + 1.5) MODE

L→H LHH X

Dout 0-35 Previous Data

Held Read Cycle SDR

L→HLHL X

Dout 0-35a Dout 0-35b Read Cycle DDR

L→HLLH X

DIN 0-35 X Write Cycle SDR

L→HLLL X

DIN 0-35a DIN 0-35b Write Cycle DDR

L→H H L X X High-Z High-Z NOP (Deselect) Cycle

L→HH H X Continue Burst Operation

Output Enable Truth Table

Operation (n, n + 1) G (n) G (n + 1) DQ (n) DQ (n + 1)

Read L L X DOUT 0-35

Read H H High-Z High-Z

Write L L X High-Z

NOP L L X High-Z

Absolute Maximum Ratings

Symbol Parameter Rating Units

Notes

VDD Power Supply Voltage -0.5 to 2.825 V 1

VDDQ Power Supply Voltage -0.5 to 2.825 V 1

VIN Input Voltage -0.5 to 2.825 V 1

VOUT Output Voltage -0.5 to 2.825 V 1

TJOperating Temperature 0 to +110 °C 1

TSTG Storage Temperature -55 to +125 °C 1

IOUT Short Circuit Output Current 25 mA 1

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

IBM043616CBLBC
IBM041816CBLBC
   16Mb (512K x 36 & 1M  x 18) SRAM
CBLBCds.fm.00
June 3, 2002 Page 9 of 25
Recommended DC Operating Conditions  (TA = 0 to 85°C)
Symbol Parameter Min. Typ. Max. Units Notes
VDD Supply Voltage  2.5V - 5% 2.5 2.5V + 5% V 1
VDDQ Output Driver Supply Voltage  1.4 1.8 1.9 V  1
VIH Input High Voltage  VREF +0.1 VDDQ + 0.3  V 1, 2
VIL Input Low Voltage  -0.3  VREF - 0.1 V 1, 3
VREF  Input Reference Voltage  0.68 .9 1.0 V  1, 6
VIN - CLK Clocks Signal Voltage -0.3  VDDQ + 0.3 V 1, 4
VDIF - CLK Differential Clocks Signal Voltage 0.1  VDDQ + 0.6 V 1, 5
VCM - CLK Clocks Common Mode Voltage 0.55 1.0 V  1
1. All voltages referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.
2. VIH(Max)DC = VDDQ + 0.3V, VIH(Max) AC = VDDQ +0.85 (pulse width ≤ 2ns).
3. VIL(Min)DC = -0.3 V, VIL(Min)AC = -1.5V (pulse width ≤ 2ns).
4. VIN-CLK specifies the maximum allowable DC excursions of each differential clock (CK, CK).
5. VDIF-CLK specifies the minimum clock differential voltage required for switching.
6. Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF
.
DC Electrical Characteristics (TA = 0 to +85°C, VDD = 2.5V ± 5%)  (Page 1 of 2)
Symbol Parameter Min. Max. Units Notes 
IDD
Average Power Supply Operating Current 
(IOUT = 0, VIN = VIH or VIL)
x36
-22 800
mA 1
-24 750
-27 700
-30 640
x18
-22 625
mA 1
-24 540
-27 515
-30 470
ISB
Power Supply Standby Current 
(SS = VIH. All other inputs = VIH or VIL. 
IOUT = 0) 200 mA 1
ILI Input Leakage Current, any input
(VIN = VSS or VDDQ)  -2 +2  µA 
ILO Output Leakage Current
(VOUT = VSS or VDDQ, DQ in High-Z) -5 +5  µA 
1. IOUT = Chip Output Current. 
2. Minimum Impedance Output Driver.
3. For JTAG inputs only.
4. JTAG output current leakage is not provided since it is not driven; it is an output only.

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 10 of 25

CBLBCds.fm.00

June 3, 2002

VOH Output High Level Voltage

(IOH = -6mA) VDDQ -0.4 VDDQ V 2

VOL Output Low Level Voltage

(IOL = +6mA) VSS V

SS +0.4 V 2

ILIJTAG

JTAG Leakage Input Current

(VIN = VSS or VDD)-70 +10 µA3

ILOJTAG JTAG Leakage Output Current 4

DC Electrical Characteristics (TA = 0 to +85°C, VDD = 2.5V ± 5%) (Page 2 of 2)

Symbol Parameter Min. Max. Units Notes

1. IOUT = Chip Output Current.

2. Minimum Impedance Output Driver.

3. For JTAG inputs only.

4. JTAG output current leakage is not provided since it is not driven; it is an output only.

IBM043616CBLBC
IBM041816CBLBC
   16Mb (512K x 36 & 1M  x 18) SRAM
CBLBCds.fm.00
June 3, 2002 Page 11 of 25
Programmable Impedance Output Driver DC Electrical Characteristics 
(TA = 0 to +85°C, VDD = 2.5V ± 5%)
Symbol Parameter Min. Max. Units Notes 
VOH Output High Voltage VDDQ / 2 VDDQ V 1, 3
VOL Output Low Voltage VSS V
DDQ/2 V 2, 3
1.  IOH = (VDDQ / 2) / (RQ / 5) ± 15% @ VOH = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 350Ω). 
2.  IOL = (VDDQ / 2) / (RQ / 5) ± 15% @ VOL = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.8 V.
PBGA Thermal Characteristics 
Symbol Parameter Rating Units 
RΘJC Thermal Resistance Junction to Case  1 °C/W
Capacitance  (TA = 0 to +85°C, VDD = 2.5V ±5%, f = 1MHz)
Symbol Parameter Test Condition Max. Units
CIN Input Capacitance VIN = 0V  4 pF 
COUT Data I/O Capacitance (DQ0–DQ35)  VOUT = 0V  5 pF 
AC Input Characteristics  (TA = 0 to +85°C, VDD = 2.5V ± 5%)
Symbol Parameter Min. Max. Units Notes
VIH (ac) AC Input Logic High VREF + 400 mV 3, 4
VIL (ac) AC Input Logic Low VREF - 400 mV 3, 4
VDIF (ac) Clock Input Differential Voltage 800 mV 2, 3
VREF (ac) VREF Peak-to-Peak AC Voltage 5% VREF (dc) mV 1
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. SRAM performance is a function of clock input differential voltage (VDIF).
3. To guarantee AC characteristics; VIH, VIL, Trise, and Tfall of the inputs and clocks must be within 20% of each other. If these condi-
tions are not met then: 
• Setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels. 
• Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
4. See AC Test Loading on page 12.

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 12 of 25

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June 3, 2002

AC Input Definition

AC Test Loading

AC Test Conditions (TA = 0 to +85°C, VDD = 2.5V ± 5%, VDDQ = 1.8V)

Symbol Parameter Conditions Units Notes

VIH Input High Level 1.5 V 2

VIL Input Low Level 0.3 V 2

VREF Input Reference Voltage 0.9 V 2

VDIF-CLK Differential Clocks Voltage 1.2 V 2

VCM-CLK Clocks Common Mode Voltage 0.9 V 2

TR Input Rise Time 0.5 ns 2

TF Input Fall Time 0.5 ns 2

I/O Signals Reference Level (except CK clocks) 0.9 V 2

Clocks Reference Level Differential Cross Point V 2

Output Load Conditions 1

1. See AC Test Loading on page 12.

2. Due to tester limitations and applied guardbands, the part is tested to AC test conditions and not worst-case specification condi-

tions. For application robustness, it is recommended that at a minimum AC test conditions are applied.

VIH (ac)

VREF

VIL (ac)

VDIF

0.9V

Ω

25 Ω5pF

0.9V

Ω

5pF

0.9V

IBM043616CBLBC
IBM041816CBLBC
   16Mb (512K x 36 & 1M  x 18) SRAM
CBLBCds.fm.00
June 3, 2002 Page 13 of 25
 
AC Characteristics  (TA = 0 to +85°C, VDD = 2.5 V +10/− 5%)
Symbol Parameter 
-22 -24 -27 -30
Units Notes 
Min. Max. Min. Max. Min. Max. Min. Max. 
 tKHKH Cycle Time  2.2 2.4 2.7 3.0 ns 
 tKHKL Clock High Pulse Width  1.0 1.0 1.3 1.4 ns 
 tKLKH Clock Low Pulse Width 1.0 1.0 1.3 1.4 ns 
 tAVKH Address Setup Time  0.25 0.25 0.3 0.3 ns  1, 8, 5, 7
 tKHAX Address Hold Time  0.25 0.25 0.3 0.3 ns  1, 8, 5, 7
 tBVKH Function Control (B1, B2, B3) Setup Time  0.25 0.25 0.3 0.3 ns  1, 8, 5, 7
 tKHBX Function Control (B1, B2, B3) Hold Time  0.25 0.25 0.3 0.3 ns  1, 8, 5, 7
 tDVKH Data In Setup Time  0.21 0.21 0.25 0.25 ns  1, 8, 5, 7
 tKHDX Data In Hold Time  0.21 0.21 0.25 0.25 ns  1, 8, 5, 7
 tINPW Input Pulse Width 0.8 0.8 1.0 1.0 6
 tCHCL Echo Clock (CQ) High Pulse Width tKHKL-
0.1
tKHKL+
0.1
tKHKL-
0.1
tKHKL+
0.1
tKHKL-
0.1
tKHKL+
0.1
tKHKL-
0.1
tKHKL+
0.1 ns  1, 2, 5
 tCLCH Echo Clock (CQ) Low Pulse Width tKLKH-
0.1
tKLKH+
0.1
tKLKH-
0.1
tKLKH+
0.1
tKLKH-
0.1
tKLKH+
0.1
tKLKH-
0.1
tKLKH+
0.1 ns  1, 2 5
 tKXCV Clock (CK) crossing to Echo Clock (CQ) 
Valid  0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns  1, 3, 5
 tKXQV Clock (CK) crossing to Output Valid  0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns  1, 5
 tKXQZ Clock (CK) crossing to Output High-Z 0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns 1, 5
 tKXQLZ Clock (CK) crossing to Output Active  0.8 2.1 0.8 2.1 0.8 2.0 0.8 1.7 ns  1, 5
 tQVTRK
Echo Clock (CQ) Valid to Output Valid 
Tracking (tKXCV - tKXQV)-0.15 0.15 -0.15 0.15 -0.15 0.15 -0.2 0.2 ns 1, 2, 4, 5
 tQZTRK
Echo Clock (CQ) Valid to Output High-Z 
Tracking (tKXCV - tKXQZ)-0.15 0.15 -0.15 0.15 -0.15 0.15 -0.2 0.2 ns 1, 2, 4, 5
 tQLZTRK
Echo Clock (CQ) Valid to Output Active 
Tracking (tKXCV - tKXQLZ)-0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 ns 1, 2, 4, 5
 tGHQZ Output Enable (G) High to High-Z  0.3 1.7 0.3 1.7 0.3 1.7 0.3 2.0 ns  2
 tGLQV Output Enable (G) Low to Output Valid 0.3 1.7 0.3 1.7 0.3 1.7 0.3 2.0 ns  2
1. See AC Test Loading on page 12. 
2. These parameters may not be tested at the values shown in this table, and may only be guaranteed by design.
3. Echo Clock (CQ) Valid refers to CQ and CQ rising and falling edges.
4. The tracking between echo-clock access times and DQ access times is across all cycle boundaries for any given SRAM address 
and function pattern.
5. CK and CK clocks must be used differentially in order to meet specification. 
6. Inputs to switch a maximum of once per applied cycle. For example, Data equals (TKHKH)/2; Address and Controls equal TKHKH.
7. To guarantee AC characteristics; VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these conditions 
are not met then: 
• Setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels. 
• Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
8. Guaranteed by design and tested without guardband.

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 14 of 25

CBLBCds.fm.00

June 3, 2002

Timing Diagram (Read and NOP Cycles)

tKHKH

Q1 Q2 Q3a

tKHKL

tGHQZ

tAVKH

tKHAX

tGLQV

tKLKH

tBVKH

tKHBX

tBVKH

tKHBX

tBVKH

tKHBX

CK,CK

Q4a

Q3b

CQ,CQ

Q4b Q4c Q4d

tKXCV

tKXQV

tKXQV tKXQZ

tCHCL tCLCH

SDR READ SDR READ DDR READ DDR READ CONTINUE

BURST NOP NOP

tCLQX

tKXQV

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

CBLBCds.fm.00

June 3, 2002 Page 15 of 25

Timing Diagram (Read, Write Cycles)

tKHKH

tKHKL

tAVKH

tKHAX

tKLKH

tBVKH tKHBX

tBVKH

tKHBX

tBVKH

tKHBX

CK,CK

CQ,CQ

tKXCV

tKXQV

tDVKH

tKHDX

SDR Read SDR Write DDR Write Continue

tGHQZ

DDR Write

Burst

Continue

Burst

Continue

Burst

tINPW

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 16 of 25

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IEEE 1149.1 TAP and Boundary Scan

The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os

and printed circuit board traces or other components. There is no multiplexer in the path from the I/O pins to

the RAM core.

In conformance with IEEE standard 1149.1, the SRAM contains a TAP controller, instruction register, bound-

ary scan register, bypass register, and ID register.

The TAP controller has a standard 16-state machine that resets internally upon power up; therefore, a TRST

signal is not required.

Signal List:

• TCK: Test Clock

• TMS: Test Mode Select

• TDI: Test Data In

• TDO: Test Data Out

JTAG Recommended DC Operating Conditions (TA = 0 to 85°C)

Symbol Parameter Min. Typ. Max. Units Notes

VIH1 JTAG Input High Voltage 1.7 — 2.8 V

VIL1 JTAG Input Low Voltage -0.3 — 0.8 V

VOH1 JTAG Output High Level 2.1 — — V 2

VOL1 JTAG Output Low Level — — 0.2 V 1

1. OH1 = -2mA at 2.1V.

2. OL1 = +2mA at 0.2V.

JTAG AC Test Conditions (TA = 0 to +85°C, VDD = 2.5V ± 5%)

Symbol Parameter Conditions Units

Notes

VIH1 Input Pulse High Level 2.0 V

VIL1 Input Pulse Low Level 0.0 V

TR1 Input Rise Time 2.0 ns

TF1 Input Fall Time 2.0 ns

Input and Output Timing Reference Level 1.0 V 1

1. See AC Test Loading on page 12.

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16Mb (512K x 36 & 1M x 18) SRAM

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JTAG AC Characteristics (TA = 0 to +85°C, VDD = 2.5V ± 5%)

Symbol Parameter Min. Max. Units Notes

tTHTH TCK Cycle Time 20 ns

tTHTL TCK High Pulse Width 7 ns

tTLTH TCK Low Pulse Width 7 ns

tMVTH TMS Setup 4 ns

tTHMX TMS Hold 4 ns

tDVTH TDI Setup 4 ns

tTHDX TDI Hold 4 ns

tTLOV TCK Low to Valid Data 7 ns 1

1. See AC Test Loading on page 12.

JTAG Timing Diagram

TCK

TMS

TDI

TDO

tTHTL tTLTH tTHTH

tTHMX

tMVTH

tDVTH

tTHDX

tTLOV

IBM043616CBLBC

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16Mb (512K x 36 & 1M x 18) SRAM

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Scan Register Definition

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan1, 2 49 68

1. The boundary-scan chain consists of the following bits:

• 36 or 18 bits for data inputs depending on x36 or x18 configuration

• 19 bits for SA0–SA18 for x36; 20 bits for SA0–SA19 for x18

• 4 or 2 bits for CQ and CQ clocks depending on x36 or x18 configuration

• 9 bits for CK, CK, ZQ, LBO, B1, B2, B3, MODE and G

2. CK and CK clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value

are used for boundary-scan sampling. CQ and CQ clocks are sampled from the CK and CK boundary-scan register inputs.

ID Register Definition

Part

Field Bit Number and Description

Revision Number

(31:28)

IBM Internal Use

Device Density and

Configuration (27:19)

Vendor Definition

(18:12)

Manufacture JEDEC

Code (11:1)

Start

Bit(0)

1M x 18 XXXX 011100001 0110011 00010100100 1

512K x 36 XXXX 011011110 0110011 00010100100 1

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16Mb (512K x 36 & 1M x 18) SRAM

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June 3, 2002 Page 19 of 25

This part has not been designed to comply with the following sections of IEEE 1149.1:

• 7.2.1.b, e

• 7.7.1.a–f

• 10.1.1.b, e

• 10.7.1.a–d

Instruction Set

Code Instruction Notes

000 SAMPLE-Z 1

001 IDCODE 1

010 SAMPLE-Z 1

011 PRIVATE 4

100 SAMPLE 3

101 PRIVATE 4

110 PRIVATE 4

111 BYPASS 2

1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.

2. BYPASS register is initialized to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially-loaded

TDI when exiting the Shift DR state.

3. SAMPLE instruction does not place DQs in High-Z.

4. PRIVATE is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality.

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 20 of 25

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Boundary Scan Order (x36)

Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump #

1 SA1 5R 24 CQ 8F 47 CQ 2F

2 SA0 5T 25 DQ11 9D 48 DQ25 1F

3 SA2 6R 26 DQ17 7F 49 DQ19 3H

4 SA3 7T 27 DQ14 8D 50 DQ22 2H

5 SA4 7P 28 DQ12 9B 51 DQ26 1H

6 DQ2 8T 29 DQ15 8B 52 ZQ 5A

7 DQ5 9T 30 SA5 7D 53 B1 5B

8 DQ3 8P 31 SA6 7C 54 B2 5K

9 DQ0 7M 32 SA7 7B 55 B3 5L

10 DQ6 9P 33 SA8 7A 56 LBO 4L

11 CQ 8M 34 SA9 6C 57 DQ27 1K

12 DQ7 9M 35 SA10 6A 58 DQ31 2K

13DQ17K36SA114A59DQ343K

14 DQ4 8K 37SA124C 60DQ281M

15DQ89K38SA133A61CQ

16 MODE16L 39 SA14 3B 62 DQ29 1P

17 CK 5H 40 SA15 3C 63 DQ35 3M

18 CK 5G 41 SA18 3D 64 DQ32 2P

19 G 5C 42 DQ20 2B 65 DQ30 1T

20 DQ9 9H 43 DQ23 1B 66 DQ33 2T

21 DQ13 8H 44 DQ21 2D 67 SA16 3T

22 DQ16 7H 45 DQ18 3F 68 SA17 4R

23 DQ10 9F 46 DQ24 1D

1. Mode will scan out the value placed on the Mode pin, or if the Mode pin is floated, Mode will scan VSS.

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16Mb (512K x 36 & 1M x 18) SRAM

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Boundary Scan Order (x18)

Exit Order Signal Bump # Exit Order Signal Bump #

1 SA1 5R 26 SA11 4A

2 SA0 5T 27 SA12 4C

3 SA2 6R 28 SA13 3A

4 SA3 7T 29 SA14 3B

5 SA4 7P 30 SA15 3C

6 DQ1 8T 31 SA18 3D

7 DQ2 9P 32 DQ10 2B

8 CQ 8M 33 DQ11 1D

9 DQ0 7K 34 CQ 2F

10 DQ3 9K 35 DQ9 3H

11 MODE16L 36 DQ12 1H

12 CK 5H 37 ZQ 5A

13 CK 5G 38 B1 5B

14 G 5C 39 B2 5K

15 DQ6 8H 40 B3 5L

16 DQ4 9F 41 LBO 4L

17 DQ8 7F 42 DQ15 2K

18 DQ7 8D 43 DQ13 1M

19 DQ5 9B 44 DQ17 3M

20 SA5 7D 45 DQ16 2P

21 SA6 7C 46 DQ14 1T

22 SA7 7B 47 SA19 3P

23 SA8 7A 48 SA16 3T

24 SA9 6C 49 SA17 4R

25 SA10 6A

1. Mode will scan out the value placed on the Mode pin, or if the Mode pin is floated, Mode will scan VSS.

IBM043616CBLBC

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16Mb (512K x 36 & 1M x 18) SRAM

Page 22 of 25

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TAP Controller State Machine

Test Logic Reset

Run Test Idle Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

IBM043616CBLBC

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16Mb (512K x 36 & 1M x 18) SRAM

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June 3, 2002 Page 23 of 25

9 x 17 BGA Dimensions

Note: All dimensions are in millimeters.

1.27

Solder Ball 0.889 ± 0.04 diameter

UTRPNMLKJHFGEDCB

0.84

1.92

20.32

Plate

0.71 ± 0.05

0.701 ± 0.099

Under fill

0.0826 ± 0.0254

0.725 ± 0.2

Indicates A1

Location

81G5788 Plate

Chip

12.7

22.00

19.968

2.549 ± 0.13

0.1778

Under fill

11.968

16.764

10.16 12.294

2.618 ± 0.254

Flush to 1.4 Max

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Page 24 of 25

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June 3, 2002

Revision Log

Rev Contents of Modification

June 3, 2002 Initial release (00).



 Copyright International Business Machines Corporation 2002

Printed in the United States of America June 2002

The following are trademarks of International Business Machines Corporation in the United States, or other countries,

or both.

IBM IBM Logo

IEEE and IEEE 802 are registered trademarks in the United States of the Institute of Electrical and Electronics Engineers.

Other company, product, and service names may be trademarks or service marks of others.

All information contained in this document is subject to change without notice. The products described in this document

are NOT intended for use in implantation, life support, space, nuclear, or military applications where malfunction may

result in injury or death to persons. The information contained in this document does not affect or change IBM product

specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under

the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific

environments, and is presented as an illustration. The results obtained in other operating environments may vary.

THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be

liable for damages arising directly or indirectly from any use of the information contained in this document.

IBM Microelectronics Division

1580 Route 52, Bldg. 504

Hopewell Junction,

NY 12533-6351

The IBM home page can be found at http://www.ibm.com

The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com

June 3, 2002