HD404344R Series/HD404394 Series
Rev. 7.0
Sept. 1999
Description
The HD404344R series and HD404394 series 4-bit microcomputers are products of the HMCS400 series,
which is designed to make application systems compact while realizing higher performance and increasing
program productivity.
Each microcomputer has an A/D converter, two timers and a serial interface. The HD404344R series
includes the HD404344R with on-chip 4-kword ROM, HD404342R with 2-kword ROM, and HD404341R
with 1-kword ROM. The HD404394 series includes the HD404394 with on-chip 4-kword ROM,
HD404392 with 2-kword ROM, and HD404391 with 1-kword ROM.
The HD4074344 and HD4074394 are the PROM version ZTAT microcomputers. Programs can be
written to the PROM by a PROM writer, which can dramatically shorten system development periods and
smooth the process from debugging to mass production. (The PROM program specifications are the same
as for the 27256.)
ZTAT: Zero Turn Around Time ZTAT is a Trademark of Hitachi Ltd.
Features
• Input/output pins
HD404344R series, HD4074344: 22 pins
(10pins: Large-current I/O pins)
HD404394 series: 21 pins
(3 pins: intermediate-voltage NMOS open drain I/O; 5 pins: NMOS open drain I/O with 15-mA
high-current driver)
• Two timer/counters
One timer output
One event counter input (with programmable edge detection)
• 8-bit clock-synchronous serial interface (1 channel)
• On-chip A/D converter
HD404344R series, HD4074344: 8 bit × 4 channel
HD404394 series: 8 bit × 3 channel (with Vref pin)
• Built-in oscillator
HD404344R Series/HD404394 Series
2
HD404344R Series
Ceramic oscillator, CR oscillation, External clock drive is also possible.
HD404394 Series, HD4074344
Ceramic oscillator, External clock drive is also possible.
• Five interrupt sources
One by external source (with programmable edge detection)
Four by internal sources
• Subroutine stack
Maximum 16 levels including interrupts
• Two low-power dissipation modes
Standby mode
Stop mode
• One input signal to return from stop mode
• Instruction cycle time
1 µs (fOSC = 4 MHz)
HD404344R Series/HD404394 Series
3
Type of Products
Product Name
Type HD404344R
Series*1HD404394
Series ROM (words) RAM (digit) Package
Mask ROM HD404341RS HD404391S 1,024 256 DP-28S
HD40C4341RS
HD404342RS HD404392S 2,048
HD40C4342RS
HD404344RS HD404394S 4,096
HD40C4344RS
HD404341RFP HD404391FP 1,024 FP-28DA
HD40C4341RFP
HD404342RFP HD404392FP 2,048
HD40C4342RFP
HD404344RFP HD404394FP 4,096
HD40C4344RFP
HD404341RFT HD404391FT 1,024 FP-30D
HD40C4341RFT
HD404342RFT HD404392FT 2,048
HD40C4342RFT
HD404344RFT HD404394FT 4,096
HD40C4344RFT
HCD404344R —— 4,096 Chip*3 *4
HCD40C4344R
ZTATHD4074344S HD4074394S 4,096 DP-28S
HD4074344FP HD4074394FP FP-28DA
HD4074344FT HD4074394FT FP-30D
Note: 1. The HD404344R Series is available in a mask ROM version only.
2. ZTAT chip shipment is not supprted.
3. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
HD404344R Series/HD404394 Series
4
List of Functions
Mask ROM
item HD404341R HD404342R HD404344R HCD404344R HD40C4341R HD40C4342R HD40C4344R
Operating voltage (V) 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5
Instruction cycle time (typ.) 1 µs
(fosc = 4.0
MHz)
1 µs
(fosc = 4.0
MHz)
1 µs
(fosc = 4.0
MHz)
1 µs
(fosc = 4.0
MHz)
2 µs
(Rf = 20 kΩ)2 µs
(Rf = 20 kΩ)2 µs
(Rf = 20 kΩ)
ROM (Words) 1,024 2.048 4,096 4,096 1,024 2,048 4,096
RAM (Digits) 256 256 256 256 256 256 256
I/O 22 22 22 22 22 22 22
High-current
I/O pins (Sink
15 mA max)
10 10 10 10 10 10 10
Timer
functions Free running
timer 2222222
Reload timer 2222222
Event counter 1111111
Watchdog
timer 1111111
Serial interface 1111111
A/D converter 8bit × 4ch 8bit × 4ch 8bit × 4ch 8bit × 4ch 8bit × 4ch 8bit × 4ch 8bit × 4ch
Interrupt External 1111111
Internal 4444444
Low-power modes 2222222
Stop mode
lllllll
Standby mode
lllllll
Oscillator Ceramic
oscillation
llll
———
RC oscillation ————
lll
Package DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
Chip DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
Guaranteed operation
temperature (°C) –20 to +75 –20 to +75 –20 to +75 +75 –20 to +75 –20 to +75 –20 to +75
HD404344R Series/HD404394 Series
5
List of Functions (cont)
Mask ROM ZTAT
item HCD40C4344R HD4074344
Operating voltage (V) 2.7 to 5.5 2.7 to 5.5
Instruction cycle time (typ.) 2 µs
(Rf = 20 kΩ)1 µs
(fosc = 4.0 MHz)
ROM (Words) 4,096 4,096 PROM
RAM (Digits) 256 256
I/O 22 22
High-current
I/O pins (Sink
15 mA max)
10 10
Timer
functions Free running
timer 22
Reload timer 2 2
Event counter 1 1
Watchdog
timer 11
Serial interface 1 1
A/D converter 8bit × 4ch 8bit × 4ch
Interrupt External 1 1
Internal 4 4
Low-power modes 2 2
Stop mode
ll
Standby mode
ll
Oscillator Ceramic
oscillation —
l
RC oscillation
l
—
Package Chip DP-28S
FP-28DA
FP-30D
Guaranteed operation
temperature (°C) +75 –20 to +75
HD404344R Series/HD404394 Series
6
List of Functions (cont)
Mask ROM ZTAT
item HD404391 HD404392 HD404394 HD4074394
Operating voltage (V) 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5
Instruction cycle time (typ.) 1 µs
(fosc = 4.0
MHz)
1 µs
(fosc = 4.0
MHz)
1 µs
(fosc = 4.0
MHz)
1 µs
(fosc = 4.0
MHz)
ROM (Words) 1,024 2.048 4,096 4,096 PROM
RAM (Digits) 256 256 256 256
I/O 21 21 21 21
intermediate-
voltage NMOS
open drain I/O
3333
NMOS open
drain I/O (15
mA High
current driver)
5555
Timer
functions Free running
timer 2222
Reload timer 2222
Event counter 1111
Watchdog
timer 1111
Serial interface 1112
A/D converter 8bit × 3ch 8bit × 3ch 8bit × 3ch 8bit × 3ch
Interrupt External 1111
Internal 4444
Low-power modes 2222
Stop mode
llll
Standby mode
llll
Oscillator Ceramic
oscillation
llll
Package DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
Guaranteed operation
temperature (°C) –20 to +75 –20 to +75 –20 to +75 –20 to +75
HD404344R Series/HD404394 Series
7
Pin Arrangement
HD404344R Series, HD4074344
R10
R11
R12
R13
R20
R21
R22
R23
OSC1
OSC2
GND
R30/AN0
R31/AN1
2/AN2
D5
D4/STOPC
D3
D2
D1
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
R33/AN3
DP-28S
FP-28DA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R10
R11
R12
R13
R20
R21
R22
R23
OSC1
OSC2
GND
NC
R30/AN0
R31/AN1
2/AN2
D5
D4/STOPC
D3
D2
D1
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
NC
R33/AN3
FP-30D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Top view
R3 R3
HD404394 Series
R10
R11
R12
R13
R20
R21
R22
R23
OSC1
OSC2
Vref
R31/AN1
2/AN2
D5
D4/STOPC
D3
D2
D1
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
R33/AN3
DP-28S
FP-28DA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R10
R11
R12
R13
R20
R21
R22
R23
OSC1
OSC2
GND
NC
Vref
R31/AN1
2/AN2
D5
D4/STOPC
D3
D2
D1
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
NC
R33/AN3
FP-30D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Top view
R3
GND
R3
HD404344R Series/HD404394 Series
8
Pad Arrangement
HCD404344R, HCD40C4344R
30
Type Code
Type Code: HD404344R (HCD404344R)
HD40C4344R (HCD40C4344R)
29 28
241
23
22
21
27 26 25
10 11 12 14 15 16
13
2
3
4
5
6
7
20
19
18
17
8
9
HD404344R Series/HD404394 Series
9
Bonding Pad Coordinates
HCD404344R, HCD40C4344R
Type Code
Chip size (X × Y): 3.23 × 3.65 (mm)
Coordinates: Pad center
Home point position: Chip center
Pad size (X × Y): 90 × 90 (µm)
Chip thickness: 400 (µm)
Chip center
(X=0, Y=0)
Pad Coordinates Pad Coordinates
No. Pad Name X (µm) Y (µm) No. Pad Name X (µm) Y (µm)
1 R13 –1425 1370 16 TEST 1360 –1627
2 R20 –1425 1050 17 RESET 1418 –1456
3 R21 –1425 732 18 R00 1418 –1072
4 R22 –1425 455 19 R01 1418 –690
5 R23 –1425 165 20 R02 1418 –306
6 OSC1 –1425 –115 21 R03 1418 312
7 OSC2 –1425 –732 22 D0 1418 694
8 GND –1425 –997 23 D1 1418 1098
9 GND –1425 –1244 24 D2 1418 1501
10 R30 –1257 –1627 25 D3 1075 1627
11 R31 –891 –1627 26 D4 693 1627
12 R32 –526 –1627 27 D5 309 1627
13 R33 –162 –1627 28 R10 –329 1627
14 VCC 420 –1627 29 R11 –732 1627
15 VCC 804 –1627 30 R12 –1135 1627
HD404344R Series/HD404394 Series
10
Pin Description
HD404344R Series, HD4074344
Pin Number
Item Symbol DP-28S/
FP-28DA FP-30D Chip I/O Function
Power supply VCC 16 18 14, 15 Applies power voltage
GND 11 11 8, 9 Connects to ground
Test TEST 17 19 16 I Cannot be used in user applications.
Connect this pin to GND.
Reset RESET 18 20 17 I Resets the MCU
Oscillator OSC19 9 6 I Input/output pins for the internal
oscillator. Connect these pins to the
ceramic oscillator, or OSC1 to an external
oscillator circuit.
OSC210 10 7 O
Port D0–D523–28 25–30 22–27 I/O Input/output pins addressed individually
by bits; pins D1 and D2 can sink 15 mA
max.
R00–R03,
R10–R13,
R20–R23,
R30–R33
1–8,
12–15
19–22
1–8,
13–16,
21–24
18–21,
28–30,
1–5,
10–13
I/O Four-bit input/output pins.
Pins R10–R23 can sink 15 mA max.
Interrupt INT023 25 22 I Input pin for external interrupts
Stop clear STOPC 27 29 26 I Input pin for transition from stop mode to
active mode
Serial interface SCK 19 21 18 I/O Serial interface clock input/output pin
SI 20 22 19 I Serial interface receive data input pin
SO 21 23 20 O Serial interface transmit data output pin
Timer TOC 22 24 21 O Timer output pin
EVNB 23 25 22 I Event count input pin
A/D converter AN0–AN312–15 13–16 10–13 I Analog input pins for the A/D converter
HD404344R Series/HD404394 Series
11
HD404394 Series
Pin Number
Item Symbol DP-28S/
FP-28DA FP-30D I/O Function
Power supply VCC 16 18 Applies power voltage
GND 11 11 Connects to ground
Test TEST 17 19 I Cannot be used in user applications. Connect
this pin to GND.
Reset RESET 18 20 I Resets the MCU
Oscillator OSC19 9 I Input/output pin for the internal oscillator.
Connect these pins to the ceramic oscillator, or
OSC1 to an external oscillator circuit
OSC210 10 O
Port D0–D523–28 25–30 I/O Input/output pins addressed individually by bits;
pins D1 and D2 can sink 15 mA max.
R00–R03,
R10–R13,
R20–R23,
R31–R33
1–8,
13–15
19–22
1–8,
14–16,
21–24
I/O Four-bit input/output pins. Pins R10–R12 are
NMOS intermediate-voltage open drain pins.
Pins R13–R23 are NMOS standard-voltage open
drain pins which can sink 15 mA max.
Interrupt INT023 25 I Input pin for external interrupts
Stop clear STOPC 27 29 I Input pin for transition from stop mode to active
mode
Serial interface SCK 19 21 I/O Serial interface clock input/output pin
SI 20 22 I Serial interface receive data input pin
SO 21 23 O Serial interface transmit data output pin
Timer TOC 22 24 O Timer output pin
EVNB 23 25 I Event count input pin
A/D converter Vref 12 13 Power supply for the internal ladder resistor in
the A/D converter
AN1–AN313–15 14–16 I Analog input pins for the A/D converter
HD404344R Series/HD404394 Series
12
HD404344R Series, HD4074344 Block Diagram
D0
D1
D2
D3
D4
D5
R00
D portR0 port
ROM
(1,024 × 10 bits)
(2,048 × 10 bits)
(4,096 × 10 bits)
PC
(14 bits)
Instruction
decoder
SP
(10 bits)
B
(4 bits)
A
(4 bits)
ST
(1 bit) CA
(1 bit)
ALU
SPY
(4 bits)
Y
(4 bits)
SPX
(4 bits)
X
(4 bits)
W
(2 bits)
RAM
(256 × 4 bits)
System control
Interrupt
control
Timer B
Timer C
Serial
interface
A/D
converter
Internal data bus
Internal data bus
Internal address bus
AN0
AN1
SI
SO
SCK
TOC
EVNB
INT0
Data bus
Large-current
pin
Bidirectional
signal line
GND
VCC
OSC2
OSC1
STOPC
TEST
RESET
AN2
AN3
R01
R02
R03
R30
R3 port
R31
R32
R33
R10
R1 port
R11
R12
R13
R20
R2 port
R21
R22
R23
HD404344R Series/HD404394 Series
13
HD404394 Series Block Diagram
D0
D1
D2
D3
D4
D5
R00
D portR0 port
ROM
(1,024 × 10 bits)
(2,048 × 10 bits)
(4,096 × 10 bits)
PC
(14 bits)
Instruction
decoder
SP
(10 bits)
B
(4 bits)
A
(4 bits)
ST
(1 bit) CA
(1 bit)
ALU
SPY
(4 bits)
Y
(4 bits)
SPX
(4 bits)
X
(4 bits)
W
(2 bits)
RAM
(256 × 4 bits)
System control
Interrupt
control
Timer B
Timer C
Serial
interface
A/D
converter
Internal data bus
Internal data bus
Internal address bus
AN1
AN2
SI
SO
SCK
TOC
EVNB
INT0
Data bus
Large-current
pin
Bidirectional
signal line
GND
VCC
OSC2
OSC1
STOPC
TEST
RESET
AN3
Vref
R01
R02
R03
R3 port
R31
R32
R33
R10
R1 port
R11
R12
R13
R20
R2 port
R21
R22
R23
Intermediate-
voltage
NMOS open
drain pins
Standard-
voltage
NMOS open
drain pins
HD404344R Series/HD404394 Series
14
Memory Map
ROM Memory Map
The ROM memory map for the MCU is shown in figure 1 and explained as follows.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
JMPL instruction
(jump to RESET, STOPC routine)
JMPL instruction
(jump to INT routine)
0
Not used
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to timer C routine)
JMPL instruction
(jump to A/D converter routine)
JMPL instruction
(jump to serial routine)
Vector address
Zero-page subroutine
(64 words)
HD404341R, HD40C4341R, HD404391
program/pattern
(1,024 words)
Not used
HD404342R, HD40C4342R, HD404392
program/pattern
(2,048 words)
HD404344R, HD40C4344R, HCD404344R,
HCD40C4344R,HD404394, HD4074344, HD4074394
program/pattern
(4,096 words)
$0000
$000F
$0010
$03FF
$0400
$0FFF
$1000
$3FFF
$003F
$0040
$07FF
$0800
0
15
16
63
64
1023
1024
4095
4096
16383
2047
2048
Figure 1 ROM Memory Map
HD404344R Series/HD404394 Series
15
Vector Address Area ($0000 to $000F): When an MCU reset or an interrupt process is executed, the
program will begin executing from a vector address. The JMPL instructions which branch to the reset
routine and interrupt routine should be programmed at these top addresses.
Zero-Page Subroutine Area ($0000–$003F): This area is reserved for subroutines. The program branches
to a subroutine in this area in response to a CAL instruction.
Pattern Area:
HD404341R, HD40C4341R, HD404391—$0000 to $03FF
HD404342R, HD40C4342R, HD404392—$0000 to $07FF
HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394—
$0000 to $0FFF
This area contains ROM data which can be referenced with the P instruction.
Program Area:
HD404341R, HD40C4341R, HD404391—$0000 to $03FF
HD404342R, HD40C4342R, HD404392—$0000 to $07FF
HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394—
$0000 to $0FFF
HD404344R Series/HD404394 Series
16
RAM Memory Map
The MCU RAM contains 256 digits × 4 bits which is used for the memory registers, and the data and stack
areas. The interrupt control bits area, special register area, and the register flag area are mapped into the
RAM memory. The RAM memory area is shown in figure 2 and explained as follows.
A/D channel register (ACR)
$000 $000
$040
$050
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$033
$00A
$00B
$00E
$00F
W
W
R/W
W
W
W
W
W
W
W
W
W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
$3C0
RAM-mapped registers
Memory registers (MR)
Stack (64 digits)
Interrupt control bits area
Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register B1 (TMB1)
Timer B (TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register (MIS)
Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)
Register flag area
Port R0 DCR (DCR0)
Port R3 DCR (DCR3)
Not used
* Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
Timer read register B lower (TRBL)
Timer read register B upper (TRBU)
Timer read register C lower (TRCL)
Timer read register C upper (TRCU)
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
R: Read only
W: Write only
R/W: Read/write
Note:
$016 R
A/D data register lower (ADRL)
$017
$018
$019
$01A
$3FF A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)
R
W
W
W
Port mode register B (PMRB)
Port mode register C (PMRC)
Timer mode register B2 (TMB2)
Not used
W
W
W
$030
Data (176 digits)
Not used
Not used
*
$03F
Not used
$100
Not used
W
W
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
$031
$032
W
Port D
4
, D
5
DCR
W
Port D
0
–D
3
DCR
$020
$023
$024
$025
$026
$02D
$02C
Not used
(DCD0)
(DCD1)
Figure 2 RAM Memory Map
HD404344R Series/HD404394 Series
17
RAM Map Register Area ($000 to $03F):
• Interrupt control bits area: $000 to $003
This area is made up of bits used for interrupt control as shown in figure 3. Each bit can be accessed
only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). Some bits
however, have limitations along with certain instructions as shown in figure 4.
• Special register area: $004 to $01F, $024 to $03F
This area is made up of mode registers and data registers, such as for external interrupt, serial interface,
timers, A/D converter, and data control for the I/O ports. Its configurations are shown in figures 2 and 5.
These registers are categorized as write-only, read-only, and write/read. They can not be accessed by
RAM bit manipulation instructions.
• Register flag area: $020 to $023
This area is used for the WDON flag and other interrupt control flags. Its configuration is shown in
figure 3. Each bit can be accessed only by the SEM/SEMD, REM/REMD, and TM/TMD instructions.
Some bits however, have limitations along with certain instructions as shown in figure 4.
Data Area ($040 to $0FF): Sixteen of the 176 digits in this area, from $040 to $04F, are memory registers.
These registers can be accessed by the LAMR and XMRA instructions. Its configuration is shown in figure
6.
Stack Area ($3C0 to $3FF): This area is used to hold the program counter (PC), the status flag (ST), and
the carry flag (CA) for subroutine calls (CAL and CALL instructions) and interrupts. Since four digits are
used for each level, this area can be used for stacking up to 16 subroutines. The stacking order of saved
data and the storing of bits are shown in figure 6. The program counter is recovered by the RTN and RTNI
instructions. The status and carry flags are recovered only by the RTNI instruction.
Any area not used in the stack area is available for data storage.
HD404344R Series/HD404394 Series
18
Bit 3 Bit 2 Bit 1 Bit 0
IMTC
(IM of timer C) IFTC
(IF of timer C) IMTB
(IM of timer B) IFTB
(IF of timer B)
IMS
(IM of serial) IFS
(IF of serial) IMAD
(IM of A/D) IFAD
(IF of A/D)
$0000
$0001
$0002
$0003
Interrupt control bits area
IM0
(IM of INT0)IF0
(IF of INT0)RSP
(Reset SP bit) IE
(Interrupt
enable flag)
$020
$021
$022
$023
Register flag area
ADSF
(A/D start flag) WDON
(Watchdog
on flag)
RAME
(RAM enable
flag)
Interrupt
request flag
Interrupt
mask
Interrupt
enable flag
SP: Stack pointer
Bit 3 Bit 2 Bit 1 Bit 0
RAM Address
IAOF
(IAD off flag)
: Not used
IF:
IM:
IE:
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD
• The WDON bit can be reset by an MCU reset or by stop mode release with STOPC.
• Do not use REM/REMD for the ADSF bit during A/D conversion.
• If the TM or TMD instruction is excuted for the inhibited or non-existing bits, the value in
ST becomes invaild.
IE
IM
IAOF
IF
RAME
RSP
WDON
ADSF
Not used
REM/REMD TM/TMD
Can be used Can be used Can be used
Can be used
Can be used
Not processed
Inhibited to access
Not processed
Can be usedNot processed
Not processed
Can be used
Can be used
Not processed
Inhibited to access
Inhibited to access
Can be used
Inhibited to access
Figure 4 Limitations for RAM Bit Manipulation Instructions
HD404344R Series/HD404394 Series
19
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
PMRA
SMR
SRL
SRU
TMB1
TRBL/TWBL
TRBU/TWBU
MIS
TMC
TRCL/TWCL
TRCU/TWCU
ACR
ADRL
ADRU
AMR1
AMR2
PMRB
PMRC
TMB2
DCD0
DCD1
DCR0
DCR1
DCR2
DCR3
Bit 3
IM0
IMTC
IMS
R0
0
/SCK
Reload control
Pull-up control
Reload control
R3
3
/AN
3
RAME
D
4
/STOPC
D
3
DCR
R0
3
DCR
R1
3
DCR
R2
3
DCR
R3
3
DCR
Bit 2
IF0
IFTC
IFS
R0
3
/TOC
SO PMOS control
R3
2
/AN
2
ADSF
IAOF
D
2
DCR
R0
2
DCR
R1
2
DCR
R2
2
DCR
R3
2
DCR
Bit 1
RSP
IMTB
IMAD
R0
1
/SI
R3
1
/AN
1
WDON
SO idle level
D
1
DCR
D
5
DCR
R0
1
DCR
R1
1
DCR
R2
1
DCR
R3
1
DCR
Bit 0
IE
IFTB
IFAD
R0
2
/SO
R3
0
/AN
0
*
A/D conversion speed
D
0
/INT
0
/EVNB
Transmit clock
D
0
DCR
D
4
DCR
R0
0
DCR
R1
0
DCR
R2
0
DCR
Register name
Serial data transfer speed
Serial data register (lower)
Serial data register (upper)
Timer B clock source
Timer B register (lower)
Timer B register (upper)
Timer C clock source
Timer C register (lower)
Timer C register (upper)
A/D channel selection
A/D data register (lower)
A/D data register (upper)
EVNB edge detection
: Not used
Note: * Applies to the HD404344R series and HD4074344. Does not apply to the HD404394 series.
R3
0
DCR*
Figure 5 Special Register Area
HD404344R Series/HD404394 Series
20
Memory registers
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
$3C0
$3FF
MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
ST
PC
CA
PC
10
3
13
9
6
2
12
8
5
1
11
7
4
0
Bit 3 Bit 2 Bit 1 Bit 0
PC –PC :
ST:
CA:
Program counter
13
Stack area
0
$3FC
$3FD
$3FE
$3FF
Status flag
Carry flag
Note: Since HD404344R series, HD4074344 and HD404394 series have a 4-kword ROM, PC12 and
PC13 are ignored.
Figure 6 Configuration of Memory Registers, Stack Area, and Stack Position
HD404344R Series/HD404394 Series
21
Functional Description
Registers and Flags
The CPU has nine registers and two flags. Their configurations are shown in figure 7 and explained as
follows.
30
30
30
30
30
30
0
0
0
13
95
1
(B)
(A)
(W)
(X)
(Y)
(SPX)
(SPY)
(CA)
(ST)
(PC)
(SP)
1111
Accumulator
B register
W register
X register
Y register
SPX register
SPY register
Carry
Status
Program counter
Initial value: 0,
no R/W
Stack pointer
Initial value: $3FF, no R/W
0
0
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: 1, no R/W
Figure 7 Registers and Flags
HD404344R Series/HD404394 Series
22
Accumulator (A), B Register (B): The accumulator and B register are 4-bit registers used for storing ALU
operation results and data that is transferred between memory and I/O ports or between other registers.
W Register (W), X Register (X), Y Register (Y): The W register is a 2-bit register and the X and Y
registers are 4-bit registers.
These are used for indirect addressing to RAM. The Y register is also used for addressing the D port.
SPX Register (SPX), SPY Register (SPY): The SPX and SPY registers are 4-bit registers that supplement
the X and Y registers, respectively.
Carry Flag (CA): The carry flag latches the ALU overflow during an arithmetic instruction execution. It is
controlled by the SEC, REC, ROTL, and ROTR instructions. The carry flag is stored during interrupt
processing, then recovered from the stack by a RTNI instruction. (It is not affected by the RTN instruction.)
Status Flag (ST): The status flag latches the overflow of ALU arithmetic instructions and compara tive
instructions, and also the results of ALU non-zero and bit test instructions. It is then used for branch
conditions of the BR, BRL, CAL, and CALL instructions. The status flag remains unchanged until the next
arithmetic instruction, comparative instruction, or bit test is executed. After a BR, BRL, CAL, or CALL
instruction is executed, the status flag will be set to 1 regardless if the instruction is executed or skipped.
The contents of the status flag is stored on the stack during interrupt processing, then recovered from the
stack by a RTNI instruction.
Program Counter (PC): This 14-bit binary counter maintains ROM address information.
Stack Pointer (SP): The stack pointer is a 10-bit register which contains the address of the next stack
space to be used. It is initialized as $3FF by an MCU reset. When data is stored onto the stack, the SP is
decremented by 4, and when data is pulled from the stack, it is incremented by 4. The top four bits of the
stack pointer are fixed at 1111, so it can be used for a maximum of 16 levels. There are two ways of
initializing the stack pointer to $3FF. One is by MCU reset and the other is by resetting the RSP bit with a
REM or a REMD instruction.
Reset
An MCU reset is executed by setting RESET low. The RESET input must be more than t RC so as to keep
the oscillator steady during power on or when stop mode is cancelled. For other cases, the MCU can be
reset by a RESET input for a minimum of two instruction cycle times.
Initialized values by MCU reset are listed in table 1.
Certain bits in the interrupt control bits area and the register flag area can be set or reset by the SEM/SEMD or
REM/REMD instructions. Also these can be tested by the TM/TMD instruction. The following specifies the limitations
for each bit.
HD404344R Series/HD404394 Series
23
Table 1 Initial Values After MCU Reset
Item Abbr. Initial Value Contents
Program counter (PC) $0000 Indicates program execution
point from start address of ROM
area
Status flag (ST) 1 Enables conditional branching
Stack pointer (SP) $3FF Stack level 0
Interrupt
flags/mask Interrupt enable flag (IE) 0 Inhibits all interrupts
Interrupt request flag (IF) 0 Indicates there is no interrupt
request
Interrupt mask (IM) 1 Prevents (masks) interrupt
requests
I/O Port data register (PDR) All bits 1 Enables output at level 1
Data control register (DCD0, DCD1) All bits 0 Turns output buffer off (to high
impedance)
(DCR0,- DCR3) All bits 0
Port mode register A (PMRA) - 000 Refer to description of port mode
register A
Port mode register B (PMRB) 0 - - 0 Refer to description of port mode
register B
Port mode register C (PMRC) - - - 0 Refer to description of port mode
register C
Timer/
counters, serial
interface
Timer mode register B1 (TMB1) 0000 Refer to description of timer
mode register B1
Timer mode register B2 (TMB2) - - 00 Refer to description of timer
mode register B2
Timer mode register C (TMC) 0000 Refer to description of timer
mode register C
Serial mode register (SMR) 0000 Refer to description of serial
mode register
Prescaler S (PSS) $000 —
Timer counter B (TCB) $00 —
Timer counter C (TCC) $00 —
Timer write register B (TWBU, TWBL) $X0 —
Timer write register C (TWCU, TWCL) $X0 —
Octal counter 000 —
HD404344R Series/HD404394 Series
24
Table 1 Initial Values After MCU Reset (cont)
Item Abbr. Initial Value Contents
A/D A/D mode register 1 (AMR1) 0000 Refer to description of A/D mode
register
A/D mode register 2 (AMR2) - - - 0 Refer to description of A/D mode
register
Bit register Watchdog timer on flag (WDON) 0 Refer to description of timer C
A/D start flag (ADSF) 0 Refer to description of A/D
converter
IAD off flag (IAOF) 0 Refer to description of A/D
converter
Others Miscellaneous register (MIS) 00 - - Refer to description of I/O, and
serial interface
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist.
Table 1 Initial Values After MCU Reset (cont)
After Stop Mode
Release by STOPC
Input
After Stop Mode
Release by RESET
Input
After Other Types
of MCU Reset
Carry (CA) Program needs to initialize these registers. Program needs to
initialize these
registers.
Accumulator (A)
B register (B)
W register (W)
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
Serial data register (SRU, SRL)
A/D data register (ADRU, ADRL)
RAM Data before entering stop mode are kept.
RAM enable flag (RAME) 1 0 0
Port mode register B
bit 3 (PMRB3) Data before entering
stop mode are kept. 00
HD404344R Series/HD404394 Series
25
Interrupts
There are five kinds of interrupts: external INT0, timer B, timer C, serial interface, and A/D converter.
An interrupt request flag or an interrupt mask and vector address are used for each type of interrupt. They
are used for storing interrupt requests and interrupt controls. An interrupt enable flag is also used for total
interrupt control.
Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped from $000 to
$003 of RAM and can be accessed by RAM bit manipulation instructions. However, the interrupt request
flag (IF) cannot be set by software. An MCU reset initializes the interrupt enable flag (IE) and the interrupt
request flag (IF) to 0, and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 8. The interrupt priority order and vector
addresses are listed in a table in the figure, along with the conditions for executing the interrupt processing
of the five types of interrupt requests (table 2). An interrupt request occurs when the interrupt request flag
is set to 1 and the interrupt mask to 0. If the interrupt enable flag is 1, interrupt processing has occurred.
The vector address which corresponds to the interrupt source is generated from the priority PLA.
The interrupt processing sequence is shown in figure 9 and the interrupt processing flowchart is shown in
figure 10. After receiving an interrupt, the previous instruction is completed in the first cycle. The interrupt
enable flag (IE) is reset after two cycles. The contents of the carry flag, status flag, and program counter are
stored onto the stack at the second and third cycles. Instruction execution is restarted by jumping to the
vector address during the third cycle. The JMPL instructions, which branch to the start addresses of the
interrupt routines, should be programmed at each vector address area. The interrupt request which initiated
the interrupt processing should be reset by software instructions in the interrupt routine.
HD404344R Series/HD404394 Series
26
IE
IF0
IM0
IFTB
IMTB
IFTC
IMTC
IFAD
IMAD
$000,0
$000,2
$000,3
$002,0
$002,1
$002,2
$002,3
$003,0
$003,1
Interrupt
request
Priority Controller
IFS
IMS
$003,2
$003,3
INT0 interrupt
Timer B interrupt
Timer C interrupt
A/D interrupt
Serial interrupt
Priority Order Vector Address
1
2
3
4
5
$0000
$0002
$0008
$000A
$000C
$000E
(RESET,STOPC*)
Note: * STOPC interrupt request is enabled only when the MCU is in stop mode.
Figure 8 Interrupt Control Circuit, Vector Addresses, and Interrupt Priorities
HD404344R Series/HD404394 Series
27
Table 2 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit INT0Timer B Timer C A/D Serial
IE 11111
IF0 · IM0 10000
IFTB · IMTB *1000
IFTC · IMTC **100
IFAD · IMAD ***10
IFS · IMS ****1
Note: * Can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
123456
Instruction
execution*
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Stacking;
Vector address
generation
Stacking;
IE reset
Note: * The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even
if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
HD404344R Series/HD404394 Series
28
Power on
RESET = 0?
Reset MCU
Interrupt
request?
Execute instruction
PC ←(PC) + 1
PC ←$0002
PC ←$000A
PC ←$000C
PC ←$000E
IE = 1?
Accept interrupt
IE 0
Stack (PC)
Stack (CA)
Stack (ST)
←
INT0
interrupt?
Timer C
interrupt?
A/D
interrupt?
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
No
No
No
No
←
←
←
(serial interrupt)
PC ←$0008 Timer B
interrupt?
Yes
Figure 10 Interrupt Processing Flowchart
HD404344R Series/HD404394 Series
29
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag executes interrupt enable/disable for all
interrupt requests as listed in table 3. It is reset by interrupt processing and set by the RTNI instruction.
Table 3 Interrupt Enable Flag (IE: $000, Bit 0)
IE Interrupt Enabled/Disabled
0 Disabled
1 Enabled
External Interrupt (INT0): INT0 input should be selected by using port mode register B (PMRB: $024), so
that the external interrupt request flag (IF0) is set at the falling edge of the INT0 input.
External Interrupt Request Flag (IF0: $000, Bit 2): The external interrupt request flag is set by the INT0
input edge, as listed in table 4.
Table 4 External Interrupt Request Flag (IF0: $000, Bit 2)
IF0 Interrupt Request
0No
1 Yes
External Interrupt Mask (IM0: $000, Bit 3): IM0 is a bit which masks the interrupt request caused by an
external interrupt request flag, as listed in table 5.
Table 5 External Interrupt Mask (IM0: $000, Bit 3)
IM0 Interrupt Request
0 Enabled
1 Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the
overflow output of timer B, as listed in table 6.
Table 6 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB Interrupt Request
0No
1 Yes
HD404344R Series/HD404394 Series
30
Timer B Interrupt Mask (IMTB: $002, Bit 1): IMTB is a bit which masks the interrupt request caused by
the timer B interrupt request flag, as listed in table 7.
Table 7 Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB Interrupt Request
0 Enabled
1 Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): The timer C interrupt request flag is set by the
overflow output of timer C, as listed in table 8.
Table 8 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC Interrupt Request
0No
1 Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): IMTC is a bit which masks the interrupt request caused
by the timer C interrupt request flag, as listed in table 9.
Table 9 Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC Interrupt Request
0 Enabled
1 Disabled (masked)
Serial Interrupt Request Flag (IFS: $003, Bit 2): A serial interrupt request flag is set when the serial data
transfer is completed or when the data transfer is suspended, as listed in table 10.
Table 10 Serial Interrupt Request Flag (IFS: $003 Bit 2)
IFS Interrupt Request
0No
1 Yes
HD404344R Series/HD404394 Series
31
Serial Interrupt Mask (IMS1: $003, Bit 3): IMS1 is a bit which masks the interrupt request caused by the
serial interrupt request flag, as listed in table 11.
Table 11 Serial Interrupt Mask (IMS: $003, Bit 3)
IMS Interrupt Request
0 Enabled
1 Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 0): The A/D interrupt request flag is set after the A/D
conversion is completed, as listed in table 12.
Table 12 A/D Interrupt Request Flag (IFAD: $003, Bit 0)
IFAD Interrupt Request
0No
1 Yes
A/D Interrupt Mask (IMAD: $003, Bit 1): IMAD is a bit which masks the interrupt request caused by the
A/D interrupt request flag, as listed in table 13.
Table 13 A/D Interrupt Mask (IMAD: $003, Bit 1)
IMAD Interrupt Request
0 Enabled
1 Disabled (masked)
HD404344R Series/HD404394 Series
32
Operating Modes
The MCU has three operating modes as shown in table 14. The transitions between the operating modes are
shown in figure 11.
Table 14 Operations in Each Operating Mode
Function Active Mode Standby Mode Stop Mode
System oscillator OP OP Stopped
CPU OP Retained Reset
RAM OP Retained Retained
Timers B, C OP OP Reset
Serial OP OP Reset
A/D OP OP Reset
I/O OP Retained*Reset
Notes: OP implies in operation.
*Since input/output circuits are in operation, the current will flow in/out depending on the pin status
in standby mode. Note that this current is in addition to the standby mode dissipation current.
Active
mode
Standby
mode
MCU
reset
Stop
mode
RESET = 1
RESET = 0
RESET = 0
RESET = 0
STOP
instruction
SBY
instruction
Interrupt
request
Figure 11 MCU Status Transition
HD404344R Series/HD404394 Series
33
Active Mode: All functions operate in active mode. In active mode, the MCU is controlled by the
oscillating circuit of OSC1 and OSC2.
Standby Mode: The MCU switches to standby mode when an SBY instruction is executed.
In standby mode, the oscillator continues operating, but the clocks related to instruction execution stops
running. This causes the CPU to stop operating. However, the contents of RAM are retained. Also, the D
and R ports, which are set as output, maintain their status before entering standby mode. The peripheral
functions, such as interrupt, timers, serial interface, and A/D converter, continue operating.
Power dissipation in standby mode is less than in active mode because of the CPU not operating.
The MCU enters standby mode when the SBY instruction is executed in active mode.
To terminate standby mode, provide a RESET input or an interrupt request. If a reset input is given, the
MCU will be reset. If an interrupt request is given, the MCU will change to active mode and the next
instruction will be executed. After the instruction execution, if the interrupt enable flag is 1, the interrupt
operation is executed. If the interrupt enable flag is 0, normal instruction execution continues and the
interrupt request is left pending.
The standby mode flowchart is shown in figure 13.
Stop Mode: The MCU enters stop mode when a STOP instruction is received.
In stop mode, all MCU functions stop, except for maintaining RAM data. Power dissipation in this mode is
therefore the lowest of all operating modes.
In stop mode, the OSC1 and OSC2 oscillator is stopped.
To terminate stop mode provide either a RESET or STOPC input as shown in figure 12.
When terminating stop mode, it is important to ensure a proper oscillation stabilization period of at least tRC
for the RESET or STOPC input. (Refer to the AC characteristics tables.)
After clearing stop mode, the RAM maintains its data kept before entering stop mode. However, the
contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and the
serial data register are not maintained.
Clearing Stop Mode Using STOPC: The MCU is transition from stop mode to active mode by either a
RESET or STOPC input. The MCU starts instruction execution from the start of the program at address 0.
Then the RAM enable flag (RAME: $021, 3) is set accordingly, RAME = 0 for RESET input and RAME =
1 for STOPC input. A RESET input is effective when the MCU is in any mode. A STOPC input however,
is effective only in stop mode and is ignored in other modes.
So, when clearing stop mode with a STOPC input the program needs to identify the RAME status. (For
example, when the RAM contents before entering stop mode is used after transition to active mode.) A
TEST instruction for the RAM enable flag (RAME) should be executed at the beginning of the program.
HD404344R Series/HD404394 Series
34
Table 15 Operating Modes and Transition Conditions
Mode Conditions to Enter Mode Conditions to Exit Mode
Active mode • RESET release
• Interrupt request
• STOPC release in stop mode
• RESET input
• STOP/SBY instruction
Standby mode • SBY instruction • RESET input
• Interrupt request
Stop mode • STOP instruction • RESET input
• STOPC input in stop mode
Stop mode
Oscillator
Internal
clock
STOP instruction execution tres≥t
RC (stabilization period)
tres
RESET
or
STOPC
Figure 12 Timing of Stop Mode Cancellation
HD404344R Series/HD404394 Series
35
Standby
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes
No
Yes
RESET = 0?
IF0 • IM0 = 1?
IFTB • IMTB =
1?
IFTC • IMTC =
1?
IFAD • IMAD =
1?
IFS • IMS =
1?
Stop
Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop
RESET = 0?
STOPC = 0?
Yes
Yes
No
No
Restart
processor clocks
Execute
next instruction
IF = 1,
IM = 0, and
IE = 1?
Interrupt accept
Execute
next instruction
Reset MCU
Restart
processor clocks
RAME = 0
RAME = 1
Figure 13 MCU Process Flowchart
HD404344R Series/HD404394 Series
36
MCU Operation Sequence: The MCU operates according to the flowcharts shown in figures 14 to 16.
Since RESET is asynchronous input, the MCU will be reset in any mode that the MCU is operating in.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 0?
RAME = 0
Reset MCU
MCU
operation
cycle
No
Yes
Figure 14 MCU Operation Sequence (Power On)
HD404344R Series/HD404394 Series
37
IF = 1?
Instruction
execution
SBY/STOP
instruction?
PC Next
location PC Vector
address
Low-power mode
operation cycle
IE 0
Stack (PC),
(CA),
(ST)
IM = 0 and
IE = 1?
←
←←
Yes
No No
Yes
Yes
No
IF:
IM:
IE:
PC:
CA:
ST:
←
Interrupt request flag
Interrupt mask
Interrupt enable flag
Program counter
Carry flag
Status flag
MCU operation
cycle
Figure 15 MCU Operation Sequence (MCU Operation Cycle)
HD404344R Series/HD404394 Series
38
Low-power mode
operation cycle
IF = 1 and
IM = 0?
Hardware NOP
execution
←
PC Next
Iocation
MCU operation
cycle
Standby mode
(SBY)
IF = 1 and
IM = 0?
Hardware NOP
execution
PC Next
Iocation
←
Instruction
execution
Stop mode
No
Yes
No
Yes
Note: *For IF and IM operation, refer to figure 13.
STOPC = 0?
RAME = 1
Reset MCU
No
Yes
*
Figure 16 MCU Operation Sequence (Low Power Mode Operation)
HD404344R Series/HD404394 Series
39
Oscillator Circuit
Figure 17 shows a block diagram of the clock generation circuit. Ceramic oscillator can be connected to
OSC1 and OSC2 as listed in table 16. An external clock can also be connected. In addition, the system
oscillator of the HD404344R Series is capable of CR oscillation.
OSC2
OSC1
System
oscillator 1/4
division
circuit
Timing
generator
circuit
System
clock
generation
CPU with ROM,
RAM, registers,
flags, and I/O
Peripheral
function
interrupt
fcyc
tcyc
fOSC øCPU
øPER
Figure 17 Clock Generation Circuit
R23
OSC1
OSC2
GND
: GND
Figure 18 Typical Layout of Ceramic Oscillator
HD404344R Series/HD404394 Series
40
Table 16 Oscillator Circuit Examples
Circuit Configuration Circuit Constants
External clock operation External
oscillator OSC
Open
1
OSC2
Ceramic oscillator
(OSC1, OSC2)OSC
2
C1
2
COSC
1
Rf
Ceramic
oscillator
GND
Ceramic oscillator : CSA4.00MG (Murata)
Rf = 1 MΩ ±20%
C1 = C2 = 30 pF ±20%
Ceramic oscillator: KBR-4.0MSA (Kyocera)
Rf = 1 MΩ ±20%
C1 = C2 = 33 pF ±20%
CR oscillation
(OSC1, OSC2)
HD404344R series OSC
2
OSC
1
Rf
Rf = 20 kΩ ±1%
Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of
the board, the user should consult with the ceramic oscillator manufacturer to determine the
circuit parameters.
2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross
other wiring (see figure 18).
HD404344R Series/HD404394 Series
41
Input/Output
The HD404344R series and HD4074344 MCU has 22 input/output pins (D0–D5, R00–R33) and the
HD404394 MCU has 21 input/output pins (D0–D5, R0 0–R23, R31–R33). These input/output pins have the
following features:
• All 22 pins for the HD404344R series and HD4074344 have a CMOS output circuit. Ten pins D1, D2,
and R10–R23 are large current input/output pins.
• Three input/output pins of the 21 pins on the HD404394 series, R10–R12, have intermediate-voltage
NMOS open drain output circuits. Five other input/output pins, R13 and R20–R23, have standard-voltage
NMOS open drain output circuits. The remaining 13 input/output pins, D0–D5, R00–R03 and R31–R33,
have CMOS output circuits.
Ten pins D1, D2, and R10–R23 are high-current input/output pins.
• Some input/output pins are multiplexed with peripheral functions, such as for the timers and serial
interface. For these pins, the settings for peripheral functions are done prior to the D or R ports settings.
If these pins are set as peripheral functions, the pin functions and input/output selections automatically
switch according to the settings.
• Program control of input/output port selection, as well as peripheral function selection.
• All peripheral function output pins are CMOS output pins. However, the R02/SO pin can be
programmed to be NMOS open drain output.
• In stop mode, all peripheral function selections are cleared because of the MCU being reset. Also, the
input/output pins go into a high-impedance state.
• All input/output pins for both the HD404344R series, HD4074344 and the HD404394 series except for
pins R10–R23, have built-in pull-up MOS. Therefore they can be individually turned on or off by
software.
• When pin functions are set as peripheral functions after selecting the pins as pull-up MOS, the pins are
maintained as pull-up MOS from the time of selection. Also, pull-up MOS can be selected by software
after setting the pin functions as peripheral functions. The control of the input/output pins are shown in
table 17 and the circuit configuration of each input/output pin is shown in table 18.
Table 17 Programmable Control of Standard I/O Pins
MIS3 (bit 3 of MIS) 0 1
DCD, DCR 0 1 0 1
PDR 01010101
CMOS buffer PMOS — — — On — — — On
NMOS — — On — — — On —
Pull-up MOS — ————On—On
Note: — indicates off.
HD404344R Series/HD404394 Series
42
Table 18 Circuit Configurations of I/O Pins
Pins
I/O Pin Type Circuit
HD404344R
Series,
HD4074344
HD404394
Series
Input/output
pins Pull-up control signal
VCC VCC
Input control signal
Input data
Output data
Buffer control signal
HLT
MIS3
PDR
DCD, DCR
D0–D5,
R00, R01
R03,
R10–R33
D0–D5,
R00, R01
R03,
R31–R33
VCC VCC
Input control signal
Input data
Output data
HLT
PDR
DCR
Buffer control signal None R13,
R20–R23
(standard
voltage pins)
Pull-up control signal
VCC VCC
Input control signal
Input data
Output data
Buffer control signal
HLT
MIS3
PDR
DCR
MIS2
R02R02
Input control signal
Input data
HLT
PDR
DCR
None R10–R12
(middle
voltage pins)
HD404344R Series/HD404394 Series
43
Table 18 Circuit Configurations of I/O Pins (cont)
Pins
I/O Pin Type Circuit
HD404344R
Series,
HD4074344
HD404394
Series
Peripheral
function pins Input/
output
pins
Pull-up control signal
VCC VCC
Input data
Output data
HLT
MIS3
SCK
SCK
SCK SCK
Output
pins Pull-up control signal
VCC VCC
Output data
PMOS control signal
HLT
MIS3
SO
MIS2
SO SO
Pull-up control signal
VCC VCC
Output data
HLT
MIS3
TOC
TOC TOC
Input
pins
SI, INT0,
Input data
EVNB, STOPC
VCC
HLT
PDR
MIS3 SI, INT0,
EVNB,
STOPC
SI, INT0,
EVNB,
STOPC
VCC
HLT
PDR
MIS3
A/D input
Input control
AN0–AN3AN1–AN3
Note: In stop mode, the MCU is reset and the peripheral function selection is cancelled. Also, the HLT
signal goes low, and input/output pins enter a high-impedance state.
HD404344R Series/HD404394 Series
44
D Port
The D port consists of six input/output pins each addressed by one bit.
The D ports can be set and reset by SED/RED and SEDD/REDD instructions. Output data is stored in the
port data register (PDR) for each pin. Also, all D ports can tested by the TD/TDD instructions.
The on/off status of the output buffers is controlled by the D-port data control registers (DCD0, DCD1:
$02C and $02D), which are mapped to memory addresses (figure 19).
Pins D0 and D4 are multiplexed with peripheral function pins INT0/EVNB, and STOPC. Setting of the
peripheral functions for these pins is executed by bits 3 and 0 (PMRB3, PMRB0) of port mode register B
(PMRB: $024) (figure 20).
Bit
Initial value
Read/Write
Bit name
3
0
W
2
0
W
0
0
W
1
0
W
DCD0, DCD1
DCR0 to DCR3
Data control register
(DCD0, DCD1: $02C, $02D)
(DCR0 to DCR3: $030 to $033)
DCR00
to
DCR30
DCR01
to
DCR31
Bits 0 to 3
0
CMOS Buffer Control
CMOS buffer off
(high impedance)
CMOS buffer on
Register
DCD0
DCD1
DCR0
DCR1
DCR2
DCR3
Bit 3
D
—
R03
R13
R23
Correspondence between ports and DCR bits
Bit 2
—
R02
R12
R22
R32
Bit 1
D
R01
R11
R21
R31
Bit 0
D
R00
R10
R20
R30
1
DCD01
to
DCD11
DCD00
to
DCD10
DDD
R33*
Note: *Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
DCD03 DCD02
DCR02
to
DCR32
DCR03
to
DCR33
3210
54
Figure 19 Data Control Register (DCR)
HD404344R Series/HD404394 Series
45
Bit
Initial value
Read/Write
Bit name
3
0
W
PMRB3
2
—
—
Not used
0
0
W
PMRB0
1
—
—
Not used
PMRB0
0
1
D0/INT0/EVNB Mode Selection
D0
INT0
Port mode register B (PMRB: $024)
PMRB3
0
1
D4/STOPC Mode Selection
D4
STOPC /EVNB
Figure 20 Port Mode Register B (PMRB)
HD404344R Series/HD404394 Series
46
R Port
The R port consists of input/output pins each addressed by 4 bits. Input/output is controlled by the LAR and
LBR instructions and the LRA and LRB instructions. The output data is stored in the port data register
(PDR) of each pin. The on/off status of the output buffers is controlled by the R-port data control registers
(DCR0–DCR3: $030–$033), which are mapped to memory addresses (figure 19).
The R10–R12 ports of the HD404394 series are n-channel middle-voltage open drain input/output pins.
The R00–R03 pins are also used as peripheral function pins: SCK, SI, SO, and TOC. Setting of the
peripheral functions for these pins is executed by bit 3 (SMR3) of the serial mode register (SMR:$005) and
by bits 2 to 0 (PMRA2–PMRA0) of port mode register A (PMRA: $004), as shown in figures 21 and 22.
The R30–R33 pins of the HD404344R series and HD4074344 are also used as AN0–AN3 peripheral function
pins. Pins R31–R33 of the HD404394 series are also used as AN 1–AN3 peripheral function pins. The setting
of peripheral functions for these pins is executed by bits 3 to 0 (AMR13–AMR10) of A/D mode register 1
(AMR1: $019). For the HD404394 series, the use of AMR10 is prohibited (figure 23).
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
W
PMRA2
0
0
W
PMRA0
1
0
W
PMRA1
PMRA0
0
1
R02/SO Mode Selection
R02
SO
Port mode register A (PMRA: $004)
PMRA1
0
1
R01/SI Mode Selection
R01
SI
PMRA2
0
1
R03/TOC Mode Selection
R03
TOC
Figure 21 Port Mode Register A (PMRA)
HD404344R Series/HD404394 Series
47
Bit
Initial value
Read/Write
Bit name
3
0
W
SMR3
2
0
W
SMR2
0
0
W
SMR0
1
0
W
SMR1
Serial mode register (SMR: $005)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SMR2 SMR0SMR1
SMR3
0
1
R00/SCK
Mode Selection
R00
SCK
SCK
Output
Output
Input
Clock Source
External clock
—
—
Prescaler
Division Ratio
See table 22.
Prescaler
System clock
Figure 22 Serial Mode Register (SMR)
Bit
Initial value
Read/Write
Bit name
3
0
W
AMR13
2
0
W
AMR12
0
0
W
AMR10
1
0
W
AMR11
AMR10*
0
1AN0
A/D mode register 1 (AMR1: $019)
AMR11
0
1AN1
AMR12
0
1
R32/AN2 Mode Selection
R32
AN2
AMR13
0
1
R33/AN3 Mode Selection
R33
AN3
R30/AN0 Mode Selection
R30
R31/AN1 Mode Selection
R31
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 23 A/D Mode Register 1 (AMR1)
HD404344R Series/HD404394 Series
48
Pull-Up MOS Transistor Control
Pull-up MOS, which can be controlled by software, is built into all input/output pins except R10–R23 of the
HD404394 series.
The on/off status of all pull-up MOS pins is controlled by bit 3 (MIS3) of the miscellaneous register (MIS:
$00C) and the port data registers (PDR) of each pin. Each pin can therefore independently switch between
with or without pull-up MOS (table 17 and figure 24).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
Bit
Initial value
Read/Write
Bit name
3
0
W
MIS3
2
0
W
MIS2
0
0
W
MIS0
1
0
W
MIS1
MIS2 PMOS On/Off
Selection for Pin R02/SO
Miscellaneous register (MIS: $00C)
0
1
On
Off
MIS3
0
1
Pull-Up MOS
On/Off Selection
Pull-up MOS off
Pull-up MOS on
Programming MIS1 and MIS0 to 1 is prohibited.
Figure 24 Miscellaneous Register
How to Deal with Unused I/O Pins
When input/output pins are not being used and are left floating, it is necessary to set these pins to VCC to
reduce the possibility of LSI malfunctions due to noise. This can be done by selecting pull-up MOS for the
pins or by connecting an external pull-up resistor of about 100 kΩ at each unused pin.
HD404344R Series/HD404394 Series
49
Prescaler
The MCU has one built-in prescaler, S (PSS). This divides the system clock and outputs the divided clock
to the peripheral function modules as shown in figure 25.
Clocks for timers B and C except for external events, and clocks for serial interface except for the external
clock are all selected from the prescaler output by programming each mode register.
Prescaler S is an 11-bit counter which inputs the system clock. After an MCU reset clears the prescaler to
$000, it begins dividing the system clock. Prescaler S stops operating due to either an MCU reset or stop
mode. It cannot be stopped by any other mode.
Timer B
Timer C
Serial
System
clock Prescaler S
Figure 25 Prescaler Output Supply
HD404344R Series/HD404394 Series
50
Timers
The MCU has two built-in timers, B and C. The functions of each timer are listed in table 19.
Table 19 Timer Functions
Functions Timer B Timer C
Clock source Prescaler S Available Available
External event Available —
Timer functions Free-running Available Available
Event counter Available —
Reload Available Available
Watchdog — Available
Timer output PWM — Available
Timer B
Timer B is an 8-bit multifunction timer that includes free-running, reload, and event counter features. These
are described as follows.
• By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler
S can be selected, or timer B can be used as an external event counter.
• By setting timer mode register B2 (TMB2: $026), timer B can be incremented by each edge detector of
input signals at pin EVNB.
• By setting timer write register BL, BU (TWBL, TWBU: $00A, $00B), timer counter B (TCB) can be
written to during reload timer operation.
• By setting timer read register BL, BU (TRBL, TRBU: $00A, $00B), the contents of timer counter B can
be read out.
Timer B Operation
• Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source,
and prescaler division ratio is done by timer mode register B1 (TMB1: $009).
Timer B is initialized to the data which is written to timer write register B (TWBL: $00A, TWBU:
$00B) by software. The data is then incremented in steps of 1 by using the input clock. If the clock
input is continued after timer B is set to $FF, an overflow occurs. Timer B then begins counting again,
setting the timer to the value in timer write register B (TWBL: $00A, TWBU: $00B) when the reload
timer is selected, or reset to $00 when the free-running timer is selected.
HD404344R Series/HD404394 Series
51
The timer B interrupt request flag is set by an overflow. Resetting the timer B interrupt request flag
(IFTB: $002, bit 0) is executed by either software or by an MCU reset.
• External event counter operation: By setting the external event input as an input clock source, timer B
can operate as an external event counter. The D0/INT0/EVNB pins are set to be INT0/EVNB pins by
port mode register B (PMRB: $024).
The detection edge of the external event counter for timer B is selected as rising edge, falling edge, or
rising/falling edge by timer mode register B2 (TMB2: $026). When the rising/falling edge is selected,
the period must be set to more than 2tcyc between the falling edge and the rising edge.
Timer B is incremented by 1 using the edge selection in timer mode register B2 (TMB2: $026). Other
functions are based on the free-running/reload timer.
Timer counter B
(TCB)
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
Timer mode
register B2
(TMB2)
EVNB Selector
System
clock øPER Prescaler S (PSS)
2
Edge
detector
Edge detection control
3
Timer write
register B lower
(TWBL)
Timer mode
register B1
(TMB1)
Timer write
register B upper
(TWBU)
Clock
Free-running
timer control
Timer read
register B lower
(TRBL)
Interrupt request
flag of timer B
(IFTB)
Timer read
register BU
(TRBU)
Overflow
Internal data bus
Figure 26 Timer B Free-Running and Reload Operation Block Diagram
HD404344R Series/HD404394 Series
52
Using Timer B Registers
Timer B sets the operation and the read/write data according to the following registers.
Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $026)
Timer write register B
(TWBL: $00A, TWBU: $00B)
Timer read register B
(TRBL: $00A, TRBU: $00B)
Port mode register B (PMRB: $024)
• Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer, input clock, and prescaler division ratio, as shown in figure 27. It is reset to $0 by an MCU reset.
Data written to timer mode register B1 is valid after two instruction cycles. The initial setting of timer
B, which is set by writing to timer write register B (TWBL: $00A, TWBU: $00B), should be
programmed only after a mode change has been effective.
Bit
Initial value
Read/Write
Bit name
3
0
W
TMB13
2
0
W
TMB12
0
0
W
TMB10
1
0
W
TMB11
Timer mode register B1 (TMB1: $009)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2048tcyc
512tcyc
128tcyc
32tcyc
8tcyc
4tcyc
2tcyc
TMB12 TMB10TMB11 Input Clock Period and Input
Clock Source
D0/INT0/EVNB (external event
TMB13
0
1
Free-Running/Reload
Timer Selection
Free-running timer
Reload timer
input)
Figure 27 Timer Mode Register B1 (TMB1)
HD404344R Series/HD404394 Series
53
• Timer mode register B2 (TMB2: $026): Two-bit write-only register that sets the input edge detection of
pin EVNB, as shown in figure 28. It is reset to $0 by an MCU reset.
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
0
W
TMB20
1
0
W
TMB21
Timer mode register B2 (TMB2: $026)
TMB21
0
1
TMB20
0
1
0
1
EVNB Edge Detection Selection
No detection
Falling-edge detection
Rising-edge detection
Rising- and falling-edge detection
Figure 28 Timer Mode Register B2 (TMB2)
• Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value cannot be guaranteed. See figures 29 and 30.
Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.
Bit
Initial value
Read/Write
Bit name
3
0
W
TWBL3
2
0
W
TWBL2
0
0
W
TWBL0
1
0
W
TWBL1
Timer write register B (lower) (TWBL: $00A)
Figure 29 Timer Write Register B (lower) (TWBL)
Bit
Initial value
Read/Write
Bit name
3
Undefined
W
TWBU3
2
Undefined
W
TWBU2
0
Undefined
W
TWBU0
1
Undefined
W
TWBU1
Timer write register B (upper) (TWBU: $00B)
Figure 30 Timer Write Register B (upper) (TWBU)
HD404344R Series/HD404394 Series
54
• Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit. See figures 31 and
32.
The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is
obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by
reading TRBL, the count of timer B when TRBU is read can be obtained.
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRBL3
2
Undefined
R
TRBL2
0
Undefined
R
TRBL0
1
Undefined
R
TRBL1
Timer read register B (lower) (TRBL: $00A)
Figure 31 Timer Read Register B (lower) (TRBL)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRBU3
2
Undefined
R
TRBU2
0
Undefined
R
TRBU0
1
Undefined
R
TRBU1
Timer read register B (upper) (TRBU: $00B)
Figure 32 Timer Read Register B (upper) (TRBU)
• Port mode register B (PMRB: $024): Write-only register that selects the D0/INT0/EVNB pin as shown
in figure 20. It is reset to $0 by an MCU reset.
HD404344R Series/HD404394 Series
55
Timer C
Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features,
which are selected and described as follows.
• By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S
can be selected.
• By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output
(PWM output) is enabled.
• By setting timer write register CL, CU (TWCL, TWCU: $00E, $00F), timer counter C (TCC) can be
written to.
• By setting timer read register CL, CU (TRCL, TRCU: $00E, $00F), the contents of timer counter C can
be read out.
• An interrupt can be requested when timer counter C overflows.
• Timer counter C can be used as a watchdog timer for detecting runaway programs.
HD404344R Series/HD404394 Series
56
Timer counter C
(TCC)
÷1024
÷2048
Port mode
register A (PMRA)
Selector
÷2
÷4
÷8
÷32
÷128
÷512
System
clock øPER Prescaler S (PSS)
3
Timer write
register C lower
(TWCL)
Timer mode
register C (TMC)
Timer write
register C upper
(TWCU)
Clock
Free-running/
reload timer
control
Timer read
register C lower
(TRCL)
Interrupt request
flag of timer C
(IFTC)
Timer read register CU (TRCU)
Overflow
TOC
Timer
output
control
Timer output
controller
Watchdog timer
controller
Watchdog on
flag (WDON)
System reset signal
Internal data bus
Figure 33 Timer C Block Diagram
Timer C Operation
• Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source,
and prescaler division ratio is done by timer mode register C (TMC: $00D).
Timer C is initialized to the data, which is written to timer write register C (TWCL: $00E, TWCU:
$00F) by software. The data is then incremented in steps of 1 by using the input clock. If the clock input
is continued after timer C is set to $FF, an overflow occurs. Timer C then begins counting again, setting
the timer to the value in timer write register C (TWCL: $00E, TWCU: $00F) when the reload timer is
selected, or reset to $00 when the free-running timer is selected.
The timer C interrupt request flag is set by an overflow. Resetting the timer C interrupt request flag
(IFTC: $002, bit 2) is executed by either software or by an MCU reset.
HD404344R Series/HD404394 Series
57
• Watchdog timer operation: Timer C can be used as a watchdog timer for programs that may run out of
control. A watchdog timer is enabled when the setting on the watchdog on flag (WDON: $020, bit 1) is
1. When timer C overflows, an MCU reset occurs. This usually controls programs running out of
control by initializing timer C through software before timer C counts up to $FF (figure 34).
$FF + 1
$00
Timer C
count value
Overflow
Time
CPU
operation Normal
operation Timer C
clear Normal
operation Timer C
clear Program
runaway Normal
operation
Reset
Figure 34 Watchdog Timer Operation Flowchart
• Timer output operation: Timer C can select the timer output mode by selecting the TOC pin after setting
bit 2 (PMRA2) of port mode register A (PMRA: $004) to 1. The output of the TOC pin is initialized to
0 by an MCU reset. PWM output is a pulse output function of variable duty. The output wave differs by
the contents of timer mode register C and timer write register C, as shown in figure 35.
T (N + 1)
T 256
T
T (256 – N)
×
×
×
TMC3 = 0
(free-running
timer)
TMC3 = 1
(reload timer)
Notes: T: Input clock period supplied to counter. (The clock input source and system clock division ratio
are determined by timer mode register C.)
N: Value in timer write register C. (When N = 255 ($FF), PWM output is fixed low.)
Figure 35 PWM Output Waveform
HD404344R Series/HD404394 Series
58
Using Timer C Registers
Timer C sets the operation and the read/write data according to the following registers.
Timer mode register C (TMC: $00D)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
• Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload
timer, input clock, and prescaler division ratio, as shown in figure 36. It is reset to $0 by an MCU reset.
The data written to timer mode register C is valid after two instructions cycles. The initial setting of
timer C, which is set by writing to timer write register C (TWCL: $00E, TWCU: $00F), should be
programmed to execute only after a mode change has been effective.
Bit
Initial value
Read/Write
Bit name
3
0
W
TMC3
2
0
W
TMC2
0
0
W
TMC0
1
0
W
TMC1
Timer mode register C (TMC: $00D)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2048tcyc
512tcyc
128tcyc
32tcyc
8tcyc
4tcyc
2tcyc
TMC2 TMC0TMC1 Input Clock Period
TMC3
0
1
Free-Running/Reload
Timer Selection
Free-running timer
Reload timer 1024tcyc
Figure 36 Timer Mode Register C (TMC)
HD404344R Series/HD404394 Series
59
• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL: $00E) and an upper digit (TWCU: $00F), as shown in figures 37 and 38.
The operation of this register is the same as that of timer write register B.
Bit
Initial value
Read/Write
Bit name
3
0
W
TWCL3
2
0
W
TWCL2
0
0
W
TWCL0
1
0
W
TWCL1
Timer write register C (lower) (TWCL: $00E)
Figure 37 Timer Write Register C (lower) (TWCL)
Bit
Initial value
Read/Write
Bit name
3
Undefined
W
TWCU3
2
Undefined
W
TWCU2
0
Undefined
W
TWCU0
1
Undefined
W
TWCU1
Timer write register C (upper) (TWCU: $00F)
Figure 38 Timer Write Register C (upper) (TWCU)
• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL: $00E) and upper digit (TRCU: $00F), which allows the upper digit of timer C to be read
directly (figures 39 and 40).
The operation of this register is the same as that of timer read register B.
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRCL3
2
Undefined
R
TRCL2
0
Undefined
R
TRCL0
1
Undefined
R
TRCL1
Timer read register C (lower) (TRCL: $00E)
Figure 39 Timer Read Register C (lower) (TRCL)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRCU3
2
Undefined
R
TRCU2
0
Undefined
R
TRCU0
1
Undefined
R
TRCU1
Timer read register C (upper) (TRCU: $00F)
Figure 40 Timer Read Register C (upper) (TRCU)
HD404344R Series/HD404394 Series
60
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 20. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
Table 20 PWM Output Following Update of Timer Write Register
PWM Output
Mode Timer Write Register is Updated during High
PWM Output Timer Write Register is Updated during Low
PWM Output
Free
running Timer write
register
updated to
value N Interrupt
request
T × (255 – N) T × (N + 1)
Timer write
register
updated to
value N Interrupt
request
T × (N' + 1)
T × (255 – N) T × (N + 1)
Reload Timer write
register
updated to
value N Interrupt
request
TT × (255 – N)T
Timer write
register
updated to
value N Interrupt
request
TT × (255 – N)
T
HD404344R Series/HD404394 Series
61
Serial Interface
The MCU has a one-channel 8-bit serial interface built in with the following features.
• One of 12 different internal clocks or an external clock can be selected as the transmit clock. The
internal clocks include the six prescaler outputs divided by two and by four, and the system clock.
• During idle states, the serial output pin can be controlled as high or low output.
• Transmit clock errors can be detected.
• An interrupt request can be generated when any errors occurred or data transfer has completed.
Internal data bus
÷2
÷8
÷32
÷128
÷512
÷2048
Port mode
register C
(PMRC)
SCK
Selector
System
clock øPER Prescaler S (PSS)
Idle
controller
3Serial mode
register
(SMR)
Clock
Serial data
register (SR)
Serial interrupt
request flag
(IFS)
Selector
1/2 1/2
SI
SO Octal
counter (OC)
I/O
controller
Transfer
control
signal
Figure 41 Serial Interface Block Diagram
HD404344R Series/HD404394 Series
62
Serial Interface Operation
Selection and Changing of Serial Interface Operation Mode: The available settings for port mode
register A (PMRA: $004) and the serial mode register (SMR: $005) are shown in table 21. To change the
operating mode or to initialize the serial interface, write to the serial mode register.
The R00/SCK pin is controlled by writing data to serial mode register (SMR: $005). The R01/SI and
R02/SO pins are controlled by writing data to port mode register A (PMRA: $004).
Table 21 Serial Interface Operating Modes
SMR PMRA
Bit 3 Bit 1 Bit 0 Operating Mode
1 0 0 Continuous clock output mode
1 Transmit mode
1 0 Receive mode
1 Transmit/receive mode
Setting Serial Clock Source: The transmit clock is set by writing to the serial mode register (SMR: $005)
and port mode register C (PMRC: $025).
Serial Data Setting: Serial data is sent by writing to the serial data register (SRL: $006 and SRU: $007).
Serial data can then be obtained by reading the serial data register. Serial data is shifted by the transmit
clock.
The output of the SO pin is undefined until the first serial data is output after an MCU reset, or until the
output level control is performed during an idle state.
Transfer Control: Serial interface operation is initiated by an STS instruction. The octal counter is reset
by the STS instruction to 000 and then incremented by one by the rising edge of the transmit clock. If eight
rising edges from the transmit clock is input or the serial data transfer is cut-off, the counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the serial data transfer stops.
As for using the built-in prescaler output for the transmit clock, selection for the transmit clock frequency
can be from 4tcyc to 8192tcyc by setting bits 2 to 0 (SMR2–SMR0) of the serial mode register (SMR: $005)
and bit 0 (PMRC0) of port mode register C (PMRC: $025). Writing to these registers for the setting of the
transmit clock is shown in table 22.
HD404344R Series/HD404394 Series
63
Table 22 Transmit Clock Selection (Prescaler Output)
PMRC SMR
Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency
0000÷ 2048 4096tcyc
1÷ 512 1024tcyc
10÷ 128 256tcyc
1÷ 32 64tcyc
100÷ 8 16tcyc
1÷ 24t
cyc
1000÷ 4096 8192tcyc
1÷ 1024 2048tcyc
10÷ 256 512tcyc
1÷ 64 128tcyc
100÷ 16 32tcyc
1÷ 48t
cyc
Serial Interface Operating States: The serial interface has the following operating states shown in figure
42, both in external clock mode and internal clock mode.
STS wait state
Transmit clock wait state
Transfer state
Continuous clock output (internal clock mode only)
• STS wait state: The serial interface is put into the STS wait state by an MCU reset (00, 10 in figure 42).
While in this state, the serial interface is initialized and does not operate, even if a transmit clock is
provided. If an STS instruction is executed while in this state (01, 11), the serial interface transfers to
the transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state period starts from when an STS instruction is
executed until the first transmit clock falling edge. While in the transmit clock wait state, if the transmit
clock is input (02, 12), the octal counter is incremented by the transmit clock, the data in the serial data
register shifts, and the serial interface enters the transfer state. However, note that if continuous clock
output mode is selected in internal clock mode, the serial interface does not enter transfer state but
enters continuous clock output state (17).
By writing to the serial mode register (SMR: $005) (04, 14) while in the transmit clock wait state, the
serial interface changes to the STS wait state.
• Transfer state: The transfer state period starts from the first falling edge of the transmit clock to the
eighth rising edge of the transmit clock. While in the transfer state, if an STS instruction is executed or
eight pulses of the transmit clock is applied, the octal counter will reset to 000 and the state will change.
If an STS instruction is executed (05, 15), the state changes to the transmit clock wait state. After the
HD404344R Series/HD404394 Series
64
eight pulses of the transmit clock, the state changes to the transmit clock wait state for the external clock
mode (03). Also, the state changes to the STS wait state for the internal clock mode (13). In the internal
clock mode, the transmit clock stops after eight pulses of the transmit clock are output.
While in the transfer state, if the serial mode register (SMR: $005) (06, 16) is written to, the serial
interface is initialized and the state changes to the STS wait state.
After the transfer state has changed to another state, the octal counter is reset to 000 and the serial
interrupt request flag (IFS: $003, 2) is set.
• Continuous clock output state (internal clock mode only): Continuous clock output state is the state in
which only the transmit clock from the SCK pin is output without data transfer. This can be done only
while in internal clock mode.
When the status of the 1 and 0 bits (PMRA1, PMRA0) of port mode register A (PMRA: $004) is 00
while in transmit clock wait state, the state can be changed to continuous clock output state by enabling
the transmit clock (17). By writing to the serial mode register (SMR: $005) while in continuous clock
output state (18), the state will change to the STS wait state.
STS wait state
(Octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(Octal counter = 000) Transfer state
(Octal counter = 000)
MCU reset
SMR write STS instruction
Transmit clock
8 transmit clocks 03 or STS instruction 05 (IFS 1)
←
SMR write (IFS 1)
←
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(Octal counter = 000) Transfer state
(Octal counter = 000)
SMR write
STS instruction
Transmit clock
STS instruction 15 (IFS 1)
←
8 transmit clocks 13 or
SMR write (IFS 1) 16
Internal clock mode
Continuous clock output state
(PMRA 0, 1 = 0, 0)
SMR write
Note: Refer to the operating states section for the corresponding encircled numbers.
MCU reset
←
04
00
01 06
02
18
14
Transmit clock 17
11
12
10
Figure 42 Serial Interface State Transitions
HD404344R Series/HD404394 Series
65
Output Level Control During Idle States: The output level of the SO pin can be set during either STS
wait state or transmit clock wait state by software. During idle states, the output level is controlled by
writing to bit 1 (PMRC1) of port mode register C (PMRC: $025). An example of output level control
during idle states is shown in figure 43. During transfer state, output level control cannot be executed.
State
MCU reset
PMRA write
SMR write
PMRC write
SCK pin
STS wait state
Transmit clock
wait state
Transfer state
Transmit clock
wait state
STS wait state
Port selection
External clock selection
Output level control in
idle states
Dummy write for
state transition
Output level control in
idle states
Data write for transmission
Undefined LSB MSB
Flag reset at transfer completion
External clock mode
State
MCU reset
PMRA write
SMR write
PMRC write
STS wait state Transfer state
Transmit clock
wait state
STS wait state
Port selection
Internal clock selection
Output level control in
idle states
Data write for transmission
Output level control in
idle states
Undefined LSB MSB
Flag reset at transfer completion
Internal clock mode
(input)
instruction
write
SRL, SRU
STS
SO pin
IFS
SCK pin
(output)
instruction
write
SRL, SRU
STS
SO pin
IFS
Figure 43 Example of Serial Interface Operation Sequence
HD404344R Series/HD404394 Series
66
Transmit Clock Error Detection (External Clock Mode): Serial interface will malfunction if a spurious
pulse caused by external noise conflicts with a normal transmit clock during data transfer. A transmit clock
error of this type can be detected as shown in figure 44.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS is reset, writing to the serial mode register (SMR: $005)
changes the state from transfer to STS wait. At this time the serial interface is in the transfer state, and the
serial interrupt request flag (IFS: $003, bit 2) is set again, and therefore the error can be detected.
Transfer completion
(IFS 1)
Interrupts inhibited
IFS 0
SMR write
IFS = 1? Transmit clock
error processing
Normal
termination
←
←
Yes
No
Transmit clock error detection flowchart
Transmit clock error detection procedure
State
SCK pin (input)
Transmit clock
wait state Transfer state Transfer state
Transmit clock wait state
Noise
Transfer state has been
entered by the transmit
clock error. When SMR is
written, IFS is set.
Flag set because octal
counter reaches 000. Flag reset at
transfer completion.
SMR write
IFS
12345678
Figure 44 Transmit Clock Error Detection
HD404344R Series/HD404394 Series
67
Notes On Use:
• Initializing after writing to registers: If port mode register A (PMRA: $004) is written to in the transmit
clock wait state or transfer state, the serial interface should be reinitialized by writing to the serial mode
register (SMR: $005).
• Serial interrupt request flag (IFS: $003, bit 2) set: For the serial interface, if the state is changed from
transfer state to another by writing to serial mode register (SMR:$005) or executing the STS instruction
during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $003, bit 2) is not
set. To set the serial interrupt request flag (IFS: $003, bit 2), a serial mode register (SMR: $005) write
or STS instruction execution must be programmed to be executed after confirming that the SCK pin is
at 1, that is, after executing the input instruction to port R0.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written using the following registers:
• Serial mode register (SMR: $005)
• Port mode register C (PMRC: $025)
• Serial data registers (SRL: $006 and SRU: $007)
• Port mode register A (PMRA: $004)
• Miscellaneous register (MIS: $00C)
Serial Mode Register (SMRA: $005): This register has the following functions (figure 45):
• R00/SCK pin function selection
• Selection of transmit clock
• Selection of prescaler division ratio
• Serial interface initialization
The write-only serial mode register is reset to $0 by an MCU reset. Writing to the serial mode register
discontinues the transmit clock input to the serial data registers (SRL: $006 and SRU: $007) and the octal
counter. The octal counter is then reset to 000. If the serial mode register is written to during serial interface
operation, data transfer will be cut off and the serial interrupt request flag (IFS: $003, bit 2) will be set.
Data in the serial mode register becomes effective after two instruction execution cycles from the time the
serial mode register is written to. It is therefore necessary to program the STS instruction to be executed
two cycles after the serial mode register is written to.
HD404344R Series/HD404394 Series
68
Bit
Initial value
Read/Write
Bit name
3
0
W
SMR3
2
0
W
SMR2
0
0
W
SMR0
1
0
W
SMR1
Serial mode register (SMR: $005)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SMR2 SMR0SMR1
SMR3
0
1
R00/SCK
Mode Selection
R00
SCK
SCK
Output
Output
Input
Clock Source
External clock
—
—
Prescaler
Division Ratio
See table 22.
Prescaler
System clock
Figure 45 Serial Mode Register (SMR)
Port Mode Register C (PMRC: $025): This register has the following functions:
• Prescaler division ratio selection
• Output level control during idle states
Port mode register C is a two-bit write-only register, which cannot be changed during data transfer.
Bit 0 (PMRC0) selects the prescaler division ratio. Only this bit is reset to 0 by an MCU reset.
Bit 1 enables the output level control of the SO pin during an idle state. The output levels at the pins are
therefore changed when writing to bit 1 (PMRC1).
HD404344R Series/HD404394 Series
69
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
0
W
PMRC0
1
Undefined
W
PMRC1
Port mode register C (PMRC: $025)
PMRC1
0
1
Output Level Control in Idle States
Low level
High level
PMRC0
0
1
Transmit Clock Division Ratio
Prescaler output divided by 2
Prescaler output divided by 4
Figure 46 Port Mode Register C (PMRC)
HD404344R Series/HD404394 Series
70
Serial Data Register (SRL: $006, and SRU: $007): This register has the following functions (figures 47
and 48):
• Transmission data write and shift
• Receive data shift and read
Data written to the serial data registers is output from the SO pin, LSB first, synchronously with the falling
edge of the transmit clock.
Also, data from the SI pin (from the LSB) is input synchronously with the rising edge of the transmit clock.
Reading or writing to the serial data register should be performed after data transfer. Read/write operation
to this register during data transfer does not guarantee valid data. The input/output timing chart for the
transmit clock and the data are shown in figure 49.
Bit
Initial value
Read/Write
Bit name
3
Undefined
R/W
SR3
2
Undefined
R/W
SR2
0
Undefined
R/W
SR0
1
Undefined
R/W
SR1
Serial data register (lower) (SRL: $006)
Figure 47 Serial Data Register (SRL)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R/W
SR7
2
Undefined
R/W
SR6
0
Undefined
R/W
SR4
1
Undefined
R/W
SR5
Serial data register (upper) (SRU: $007)
Figure 48 Serial Data Register (SRU)
LSB MSB
12345678
Ttransmit clock
Serial output
data
Serial input
data latch
timing
Figure 49 Serial Interface Timing
HD404344R Series/HD404394 Series
71
Port Mode Register A (PMRA: 004): This register A has the following functions:
• R01/SI pin function selection
• R02/SO pin function selection
Port mode register A is a three-bit write-only register and reset to 0 by an MCU reset, as listed in figure 50.
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
W
PMRA2
0
0
W
PMRA0
1
0
W
PMRA1
PMRA0
0
1
R02/SO Mode Selection
R02
SO
Port mode register A (PMRA: $004)
PMRA1
0
1
R01/SI Mode Selection
R01
SI
PMRA2
0
1
R03/TOC Mode Selection
R03
TOC
Figure 50 Port Mode Register A (PMRA)
Miscellaneous Register
The miscellaneous register (MIS: $00C) has the following functions:
• Control of R02/SO pin PMOS
• Pull-up MOS on/off selection
It is a two-bit write-only register and is reset to $0 by an MCU reset, as listed in figure 51.
HD404344R Series/HD404394 Series
72
Bit
Initial value
Read/Write
Bit name
3
0
W
MIS3
2
0
W
MIS2
0
0
W
MIS0
1
0
W
MIS1
MIS2 PMOS On/Off
Selection for Pin R02/SO
Miscellaneous register (MIS: $00C)
0
1
On
Off
MIS3
0
1
Pull-Up MOS
On/Off Selection
Pull-up MOS off
Pull-up MOS on
Programming MIS1 and MIS0 to 1 is prohibited.
Figure 51 Miscellaneous Register
HD404344R Series/HD404394 Series
73
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a register ladder. It
can perform a digital conversion with 3 or 4 analog inputs at 8-bit resolution. The following describes the
features of the A/D converter.
• A/D mode register 1 (AMR1: $019) is used to select digital or analog ports (figure 53).
• A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed (figure 54).
• The A/D channel register (ACR: $016) is used to select an analog input channel (figure 55).
• A/D conversion is started by setting the A/D start flag (ADSF: $020, bit 2) to 1. After the conversion is
completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is
cleared to 0 (figure 56).
• By setting the IAD off flag (IAOF: $021, bit 2) to 1, the current flowing through the resistance ladder
can be cut off even in standby or active mode (figure 57).
• A/D data registers (ADRL: $017, ADRU: $018) are read-only registers used to store the conversion
result. (ADRL: lower 4 bits, ADRU: upper 4 bits.) These registers cannot be cleared by a reset input.
Also, data in these registers are not guaranteed during the conversion period. After the conversion is
completed, an 8-bit result is set to these registers and kept until the next conversion starts (figures 58,
59, and 60).
Notes On Use:
• Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF).
• Do not write to the A/D start flag during A/D conversion.
• Data in the A/D data register during A/D conversion is undefined.
• Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power dissipation while in a stop mode, all
current flowing through the converter’s resistance ladder is cut off.
• Output signal level from other ports should be fixed during A/D conversion.
• The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain
pulled up.
HD404344R Series/HD404394 Series
74
IAD off flag
(IAOF)
Selector
4
A/D channel
register (ACR)
A/D mode
register 2
(AMR2)
A/D mode
register 1
(AMR1)
A/D interrupt
request flag
(IFAD)
Encoder A/D data
registers
(ADRU, L)
A/D start flag
(ADSF)
D/A
VCC (Vref)*2
GND
Operating mode signal (1 in stop mode)
Internal data bus
+
–
Comp A/D
controller
R33/AN3
R32/AN2
R31/AN1
(R30/AN0)
*1
Control signal
for conversion
time
4
Notes: 1.
2. Available for the HD404344R series and HD4074344. Not available for the HD404394 series.
Connected to VCC for the HD404344R series and HD4074344. Connected to Vref for the
HD404394 series.
Figure 52 A/D Converter Block Diagram
HD404344R Series/HD404394 Series
75
Bit
Initial value
Read/Write
Bit name
3
0
W
AMR13
2
0
W
AMR12
0
0
W
AMR10
1
0
W
AMR11
AMR10*
0
1AN0
A/D mode register 1 (AMR1: $019)
AMR11
0
1AN1
AMR12
0
1
R32/AN2 Mode Selection
R32
AN2
AMR13
0
1
R33/AN3 Mode Selection
R33
AN3
R30/AN0 Mode Selection
R30
R31/AN1 Mode Selection
R31
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 53 A/D Mode Register 1 (AMR1)
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
0
W
AMR20
1
—
—
Not used
AMR20
0
167tcyc
A/D mode register 2 (AMR2: $01A)
Conversion Time
34tcyc
Figure 54 A/D Mode Register 2 (AMR2)
HD404344R Series/HD404394 Series
76
Bit
Initial value
Read/Write
Bit name
3
0
W
ACR3
2
0
W
ACR2
0
0
W
ACR0
1
0
W
ACR1
A/D channel register (ACR: $016)
000
0
1
0
1
Analog Input Selection
AN0
AN1
AN2
AN3
ACR3 ACR1ACR2 ACR0
1
Note: Available for the HD404344R series and HD4074344, but not available for the HD404394 series.*
*
Figure 55 A/D Channel Register (ACR)
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
R/W
ADSF
0
—
—
Not used
1
0
W
WDON
A/D start flag (ADSF: $020, bit 2)
Refer to the description of timers
WDON
0
1
A/D conversion completed
A/D conversion started
A/D Start Flag (ADSF)
Figure 56 A/D Start Flag (ADSF)
HD404344R Series/HD404394 Series
77
Bit
Initial value
Read/Write
Bit name
3
0
R/W
RAME
2
0
R/W
IAOF
0
—
—
Not used
1
—
—
Not used
IAD off flag (IAOF: $021, bit 2)
Refer to the description of operating
modes
RAME
0
1
IAD
IAD
current flows
IAD Off Flag (IAOF)
current is cut off
Figure 57 IAD Off Flag (IAOF)
3210 3210
MSB LSB
Bit 0Bit 7
Result
ADRU: $018 ADRL: $017
Figure 58 A/D Data Register
Bit
Initial value
Read/Write
Bit name
3
0
R
ADRL3
2
0
R
ADRL2
0
0
R
ADRL0
1
0
R
ADRL1
A/D data register lower (ADRL: $017)
Figure 59 A/D Data Register Lower (ADRL)
HD404344R Series/HD404394 Series
78
Bit
Initial value
Read/Write
Bit name
3
1
R
ADRU3
2
0
R
ADRU2
0
0
R
ADRU0
1
0
R
ADRU1
A/D data register upper (ADRU: $018)
Figure 60 A/D Data Register Upper (ADRU)
HD404344R Series/HD404394 Series
79
Pin Description in PROM Mode
The HD4074344 and the HD4074394 are PROM versions of a ZTAT microcomputer. In PROM mode,
the MCU stops operating, thus allowing the user to program the on-chip PROM.
Pin Number MCU Mode PROM Mode
DP-28S/FP-28DA FP-30D Pin I/O Pin I/O Remarks
11R1
0I/O A5I
22R1
1I/O A6I
33R1
2I/O A7I
44R1
3I/O A8I
55R2
0I/O A9I
66R2
1I/O A10 I
77R2
2I/O A11 I
88R2
3I/O A12 I
9 9 OSC1IOE I
10 10 OSC2O
11 11 GND GND
12 NC
12 13 R30/AN0 or Vref I/O or Vref 2
13 14 R31/AN1I/O M0I
14 15 R32/AN2I/O XON I
15 16 R33/AN3I/O O0I/O
17 NC
16 18 VCC VCC
17 19 TEST I VPP I
18 20 RESET IRESET I
19 21 R00/SCK I/O O1I/O
20 22 R01/SI I/O O2I/O
21 23 R02/SO I/O O3I/O
22 24 R03/TOC I/O O4I/O
23 25 D0/INT0/EVNB I/O A0I
24 26 D1I/O A1I
25 27 D2I/O A2I
26 28 D3I/O A3I
27 29 D4/STOPC I/O CE I
28 30 D5I/O A4I
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin
2. R30/AN0 is for the HD404344R series and Vref for the HD404394 series in MCU mode.
HD404344R Series/HD404394 Series
80
Programmable ROM Operation
The HD4074344 and HD4074394 on-chip PROMs are programmed in PROM mode.
In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a
standard PROM programmer and a socket adapter as shown in figure 61. Table 23 lists the recommended
PROM programmers and socket adapters.
Since instructions of the HMCS400 series consists of 10 bits, the HMCS400 series microcomputers
incorporate a conversion circuit to enable the use of a general-purpose PROM programmer. By this circuit,
an instruction is read or written to using two addresses, lower five bits and upper five bits. For example, if
4 kwords of on-chip PROM are programmed by a general-purpose PROM programmer, 8 kbytes of
addresses ($0000–$1FFF) should be specified.
Control signals
Address bus
Data bus
A14,A
13
2
A12–A0
O4–O0
28-to-28-pin socket adapter
30-to-28 pin socket adapter PROM programmer
VCC
GND
VPP
A14–A0
O7–O0
O7–O5
CE, OE
A12–A0
O4–O0
HD4074344
HD4074394
VCC
GND
VPP
XON
M0
RESET
3
Figure 61 PROM Mode Connections
HD404344R Series/HD404394 Series
81
Table 23 PROM Programmer and Socket Adapter
PROM Programmer
Maker Type Name
DATA I/O UNISITE
AVAL Corp. PKW-3100
Socket Adapter
Package Maker Type Name
DP-28S Hitachi HS4344ESS01H
FP-28DA HS4344ESP01H
FP-30D HS4344ESF01H
Programming and Verification
The HD4074344 and HD4074394 can be high-speed programmed without causing voltage stress or
affecting data reliability.
Table 24 shows how programming and verification modes are selected.
Table 24 PROM Mode Selection
Pin
Mode CE OE VPP O0–O4
Programming Low High VPP Data input
Verification High Low VPP Data output
Programming inhibited High High VPP High impedance
Precautions
1. Addresses $0000 to $1FFF should be specified if the PROM is programmed by a PROM programmer.
If address $2000 or higher is accessed, the PROM may not be programmed or verified correctly. Note
that the plastic package type devices cannot be erased and reprogrammed. Set all data in unused
addresses to $FF.
2. Be careful of not using the wrong PROM programmer or socket adapter, which may cause an
overvoltage and damage the LSI. Make sure that the LSI is firmly fixed onto the socket adapter, and
that the socket adapter is firmly fixed to the programmer.
3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to
the HD4074344 or HD4074394, the LSI may become permanently damaged. 12.5 V is Intel’s 27256
VPP.
HD404344R Series/HD404394 Series
82
Addressing Modes
RAM Addressing Modes
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as
a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 digits from
$040 to $04F, are accessed with the LAMR and XMRA instructions.
ROM Addressing Modes
Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the
JMPL, BRL, or CALL instruction.
30
30
0
0
0
9
9
1
WXY
Opcode
Register Indirect Addressing
2nd instruction
word
RAM address
Direct Addressing
Instruction
90
09
RAM address
1st instruction
word
37
30
Memory Register Addressing
09
RAM address 000100
OpcodeInstruction
Figure 62 RAM Addressing Modes
HD404344R Series/HD404394 Series
83
Current Page Addressing Mode: A program can branch to any address in the current page (256 words per
page) by executing the BR instruction.
Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page
subroutine area ($0000–$003F) by executing the CAL instruction.
Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
0
0
Direct Addressing
2nd
instruction word
Program counter
Current Page Addressing
97
0
9
Program counter
1st
instruction word 50
Zero-Page Addressing
00
Operand
09
Table Data Addressing
7
13
09
OperandOpcode
3
013
Operand
******
Opcode
Program counter
013
3
Operand
Opcode BA
0
9
Opcode
00000000Program counter
013
Figure 63 ROM Addressing Modes
HD404344R Series/HD404394 Series
84
Addressing Mode for P Instruction: By using the P instruction, the ROM data determined by table data
addressing can be referenced. The lower-order 8 bits of ROM data are written in the accumulator and the B
register when bit 8 of the ROM data is 1, and are written in the R1 and R2 port output registers when bit 9
is 1. If bit 8 and bit 9 are both 1, the ROM data is simultaneously written into the accumulator, the B
register, and the R1 and R2 port output registers. (See figure 64.)
The program counter is not affected by the P instruction.
Accumulator
Referenced ROM address
Address
B register
00
[P]
Instruction
Opcode
RO8 = 1Accumulator, B register
ROM data
Pattern Output
ROM data
RO9 = 1Output registers R1, R2
p3p2p1p0
B3B2B1B0A3A2A1A0
RA13RA12RA11RA10 RA9RA8RA7RA6RA5RA4RA3RA2RA1RA0
RO9RO8RO7RO6RO5RO4RO3RO2RO1RO0
B3B2B1B0A3A2A1A0
RO9RO8RO7RO6RO5RO4RO3RO2RO1RO0
R23R22R21R20R13R12R11R10
Figure 64 P Instruction
HD404344R Series/HD404394 Series
85
BR Branching Instruction at Page Boundary: When the BR instruction is at a page boundary (256n +
255), the address in the program counter is transferred over to point to the next page as done by the internal
hardware. Therefore, executing the BR instruction at a page boundary will cause the program to branch to
the next page. (See figure 65.)
BR AAA
AAA NOP
BR AAA
BR BBB
BBB NOP
256 (n – 1) + 255
256n
256n + 254
256n + 255
256 (n + 1)
Figure 65 BR Instruction at Page Boundary
HD404344R Series/HD404394 Series
86
Absolute Maximum Ratings
Item Symbol Value Unit Notes
Supply voltage VCC –0.3 to +7.0 V
Programming voltage VPP –0.3 to +14.0 V 1
Pin voltage VT–0.3 to VCC + 0.3 V 2
–0.3 to +15.0 V 3
Total permissible input current ∑IO100 mA 4
Total permissible output current –∑IO30 mA 5
Maximum input current IO30 mA 6, 7
4 mA 6, 8
Maximum output current –IO4mA9
Operating temperature Topr –20 to +75 °C10
Storage temperature Tstg –55 to +125 °C11
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to pin TEST (VPP) of the HD4074344 and HD4074394.
2. Applies to the following pins.
HD404344R series and HD4074344: D0–D5, R0, R1, R2, R3
HD404394 series: D0–D5, R0, R13, R2, R31–R33
3. Applies to the following pins.
HD404394 series: R10–R12
4. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
6. The maximum input current is the maximum current flowing from each I/O pin to GND.
7. Applies to D1, D2, R1, and R2.
8. Applies to the following pins.
HD404344R series and HD4074344: D0, D3–D5, R0, R3
HD404394 series: D0, D3–D5, R0, R31–R33
9. The maximum output current is the maximum current flowing out from VCC to each I/O pin.
10.The operating temperature indicates the temperature range in which power can be supplied to
the LSI (voltage Vcc shown in the electrical characteristics tables can be applied).
11.In the case of chips, the storage specification differs from that of the package products. Please
consult your Hitachi sales representative for details.
HD404344R Series/HD404394 Series
87
Electrical Characteristics
DC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, HCD404344R, HCD40C4344R:
VCC = 2.5 to 5.5 V, GND = 0 V, Ta = +75°C, HD404394, HD404392, HD404391, HD4074344,
HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item Symbol Pins Min Typ Max Unit Test Condition Notes
Input high
voltage VIH RESET, SCK,
INT0, STOPC,
EVNB
0.8VCC —V
CC + 0.3 V
SI 0.7VCC —V
CC + 0.3 V
OSC1VCC – 0.5 — VCC + 0.3 V
Input low
voltage VIL RESET, SCK,
INT0, STOPC,
EVNB
–0.3 — 0.2VCC V
SI –0.3 — 0.3VCC V
OSC1–0.3 — 0.5 V
Output high
voltage VOH SCK, SO, TOC VCC – 1.0 — — V –IOH = 0.5 mA
Output low
voltage VOL SCK, SO, TOC — — 0.4 V IOL = 0.5 mA
I/O leakage
current |IIL|RESET, SCK,
SI, SO, TOC,
OSC1, INT0,
STOPC, EVNB
——1 µAV
in = 0 V to VCC 1
Current
dissipation in
active mode
ICC1 VCC — — 3.5 mA VCC = 5 V,
fOSC = 4 MHz 2
ICC2 — — 0.4 mA VCC = 3 V, 2, 4
0.5 mA fOSC = 400 kHz 5
Current
dissipation in
standby
mode
ISBY1 VCC — — 1.5 mA VCC = 5 V,
fOSC = 4 MHz 3
ISBY2 — — 0.2 mA VCC = 3 V, 3, 4
— — 0.4 mA fOSC = 400 kHz 3, 5
ISBY3 — — 0.6 mA VCC = 5 V,
fOSC = 800 kHz 3, 5, 6
HD404344R Series/HD404394 Series
88
DC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, HCD404344R, HCD40C4344R:
VCC = 2.5 to 5.5 V, GND = 0 V, Ta = +75°C, HD404394, HD404392, HD404391, HD4074344,
HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified) (cont)
Item Symbol Pins Min Typ Max Unit Test Condition Notes
Current
dissipation in
stop mode
ISTOP VCC ——10µAV
in (RESET) =
VCC – 0.3 V to VCC,
Vin (TEST) =
0 to 0.3 V
Stop mode
retaining
voltage
VSTOP VCC 2——V
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. ICC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions: MCU: Reset
Pins: RESET, TEST at GND
D0–D5, R0–R3 at VCC
3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating.
Test conditions: MCU: I/O reset
Standby mode
Pins: RESET at VCC
TEST at GND
D0–D5, R0–R3 at VCC
4. Applies to the HD404394 series and HD4074344.
5. Applies to the HD404344R series.
6. The current in case of excluding the current through A/D converters ladder resistance (flag IAOF is
set to “1”). Circuit structure and circuit constants of oscillator circuit is the following condition.
Circuit Structure Circuit Constants
OSC1
OSC2
Rf
Rd
C1
C2
Ceramic
oscillator
Ceramic oscillator: KBR-800FTR (KYOSERA)
C1 = C2 = 100 pF
Rf = 1 MΩ
Rd = 2.2 kΩ
HD404344R Series/HD404394 Series
89
I/O Characteristics for Standard Pins (HD404344R, HD404342R, HD404341R, HD40C4344R,
HD40C4342R, HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, HCD404344R,
HCD40C4344R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = +75°C, HD404394, HD404392, HD404391,
HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise
specified)
Pins
Item Symbol HD404344R
Series,
HD4074344
HD404394
Series Min Typ Max Unit Test Condition Note
Input high
voltage VIH D0–D5,
R0–R3 D0–D5,
R0, R13, R2,
R31–R33
0.7VCC —V
CC + 0.3 V
Input low
voltage VIL D0–D5,
R0–R3 D0–D5,
R0, R13, R2,
R31–R33
–0.3 — 0.3VCC V
Output high
voltage VOH D0–D5,
R0–R3 D0–D5,
R0,
R31–R33
VCC – 1.0 — — V –IOH = 0.5 mA
—R1
3
, R2 VCC – 0.5 — — V 500 kΩ at VCC 2
Output low
voltage VOL D0–D5,
R0–R3 D0–D5,
R0, R13, R2,
R31–R33
— — 0.4 V IOL = 0.5 mA
D1, D2,
R1, R2 D1, D2,
R13, R2 — — 2.0 V IOL = 15 mA,
VCC = 4.5–5.5 V
Input
leakage
current
|IIL|D
0
–D5,
R0–R3 D0–D5,
R0, R13, R2,
R31–R33
——1 µAV
in = 0 V to VCC 1
Pull-up
MOS
current
–IPU D0–D5,
R0–R3 D0–D5,
R0,
R31–R33
30 150 300 µAV
CC = 5 V,
Vin = 0 V
Notes: 1. Output buffer current and pull-up MOS current are excluded.
2. Applies to the HD404394 series.
HD404344R Series/HD404394 Series
90
I/O Characteristics for NMOS Intermediate-Voltage Pins for HD404394 Series (VCC = 2.7 to 5.5 V,
GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item Symbol Pins Min Typ Max Unit Test Condition Notes
Input high voltage VIH R10–R120.7VCC — 12.0 V 1
Input low voltage VIL R10–R12–0.3 — 0.3VCC V1
Output high voltage VOH R10–R1211.5 — — V 500 kΩ at 12 V 1
Output low voltage VOL R10–R12— — 0.4 V IOH = 0.5 mA 1
R10–R12— — 2.0 V IOL = 15 mA,
VCC = 4.5 to 5.5 V 1
I/O leakage current |IIL|R1
0
–R12——20µAV
in = 0 V to 12 V 1, 2
Notes: 1. Applies to the HD404394 series.
2. Excludes output buffer current.
A/D Converter Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R,
HD40C4342R, HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, HCD404344R,
HCD40C4344R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = +75°C, HD404394, HD404392, HD404391,
HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise
specified)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Analog reference voltage Vref Vref 0.5VCC —V
CC V2
Analog input voltage AVin AN0–AN3GND — VCC V1
AN1–AN3GND — Vref V2
Current flowing between
Vref and GND IAD — — 200 µAV
ref = VCC = 5.0 V 2
Analog input capacitance CAin AN0–AN3—15—pF
Resolution — 8 — Bit
Number of input channels 0 — 4 Channel 1
0 — 3 Channel 2
Absolute accuracy AN0–AN3–2.0 — 2.0 LSB 1
AN0–AN3–2.5 — 2.5 LSB Ta = 25°C, 2
AN1–AN3–3.0 — 3.0 LSB Vref = VCC = 5.0 V 3
Conversion time 34 — 67 tcyc
Input impedance AN0–AN31 ——MΩf
OSC = 1 MHz,
Vin = 0 V
Notes: 1. Applies to the HD404344R series.
2. Applies to the HD4074344.
3. Applies to the HD404394 series.
HD404344R Series/HD404394 Series
91
AC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, HCD404344R, HCD40C4344R:
VCC = 2.5 to 5.5 V, GND = 0 V, Ta = +75°C, HD404394, HD404392, HD404391, HD4074344,
HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Clock oscillation frequency
(ceramic oscillator) fOSC OSC1, OSC20.4 — 4.5 MHz Division by 4
Clock oscillation frequency
(resistor oscillator) fOSC OSC1, OSC21.0 2.0 3.5 MHz Division by 4
Rf = 20 kΩ
Instruction cycle time
(external clock, ceramic
oscillator)
tcyc 0.89 — 10 µs Division by 4
Instruction cycle time
(resistor oscillator) tcyc 1.14 — 4.0 µs Division by 4
Rf = 20 kΩ
Oscillation setting time
(external clock) tRC OSC1, OSC2——2 ms 1
Oscillation setting time
(ceramic oscillator) tRC OSC1, OSC2——2 ms 1
Oscillation setting time
(resistor oscillator) tRC OSC1, OSC2— — 0.5 ms Rf = 20 kΩ1, 11
External clock high-level
width tCPH OSC192——ns 2
External clock low-level
width tCPL OSC192——ns 2
External clock rise time tCPr OSC1——20ns 2
External clock fall time tCPf OSC1——20ns 2
INT0, EVNB high-level
width tIH INT0, EVNB 2 — — tcyc 3
INT0, EVNB low-level
width tIL INT0, EVNB 2 — — tcyc 3
RESET low-level width tRSTL RESET 2 ——t
cyc 4
STOPC low-level width tSTPL STOPC 1 ——t
RC 5
RESET rise time tRSTr RESET ——20ms 4
STOPC rise time tSTPr STOPC ——20ms 5
HD404344R Series/HD404394 Series
92
AC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, HCD404344R, HCD40C4344R:
VCC = 2.5 to 5.5 V, GND = 0 V, Ta = +75°C, HD404394, HD404392, HD404391, HD4074344,
HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified) (cont)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Input capacitance Cin All input pins
except TEST,
Vref and R10–R12
— — 15 pF f = 1 MHz,
Vin = 0 V
TEST — — 15 pF f = 1 MHz,
Vin = 0 V 6
——40pF 7
V
ref ——30pF 8
R10–R12——15pF 9
——30pF 10
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After VCC reaches the minimum specification value at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of tRC.
When using a ceramic oscillator, consult with the manufacturer to determine what stabilization
time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 66.
3. Refer to figure 67.
4. Refer to figure 68.
5. Refer to figure 69.
6. Applies to the HD404341R, HD404342R, HD404344R, HD404391, HD404392, and HD404394.
7. Applies to the HD4074344 and HD4074394.
8. Applies to the HD404394 series.
9. Applies to the HD404344R series.
10.Applies to the HD404394 series and HD4074344.
11.Applies to the HD40C4344R, HD40C4342R, HD404341R
HD404344R Series/HD404394 Series
93
Serial Interface Timing Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R,
HD40C4342R, HD40C4341R: VCC = 2.5 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, HCD404344R,
HCD40C4344R: V CC = 2.5 to 5.5 V, GND = 0 V, Ta = +75°C, HD404394, HD404392, HD404391,
HD4074344, HD4074394: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise
specified)
During Transmit Clock Output
Item Symbol Pins Test Condition Min Typ Max Unit Note
Transmit clock cycle time tScyc SCK Load shown in
figure 71 1 ——t
cyc 1
Transmit clock high width tSCKH SCK Load shown in
figure 71 0.4 — — tScyc 1
Transmit clock low width tSCKL SCK Load shown in
figure 71 0.4 — — tScyc 1
Transmit clock rise time tSCKr SCK Load shown in
figure 71 ——80ns1
Transmit clock fall time tSCKf SCK Load shown in
figure 71 ——80ns1
Serial output data delay time tDSO SO Load shown in
figure 71 — — 300 ns 1
Serial input data setup time tSSI SI 100 — — ns 1
Serial input data hold time tHSI SI 200 — — ns 1
During Transmit Clock Input
Item Symbol Pins Test Condition Min Typ Max Unit Note
Transmit clock cycle time tScyc SCK 1 ——t
cyc 1
Transmit clock high width tSCKH SCK 0.4 — — tScyc 1
Transmit clock low width tSCKL SCK 0.4 — — tScyc 1
Transmit clock rise time tSCKr SCK ——80ns1
Transmit clock fall time tSCKf SCK ——80ns1
Serial output data delay time tDSO SO Load shown in
figure 71 — — 300 ns 1
Serial input data setup time tSSI SI 100 — — ns 1
Serial input data hold time tHSI SI 200 — — ns 1
Note: 1. Refer to figure 70.
HD404344R Series/HD404394 Series
94
V – 0.5 V
CC
0.5 V
OSC1
tCPH tCPL
1/fCP
tCPf
tCPr
Figure 66 External Clock Timing
0.8VCC
0.2VCC
INT0, EVNB
tIL
tIH
Figure 67 Interrupt Timing
RESET
tRSTr
tRSTL
0.2VCC
0.8VCC
Figure 68 RESET Timing
tSTPr
tSTPL
0.8VCC
0.2VCC
STOPC
Figure 69 STOPC Timing
HD404344R Series/HD404394 Series
95
0.7V
CC
0.3V
CC
tDSO
tSCKf tSCKL
tSSI tHSI
tScyc
tSCKr
0.4 V
V – 0.5 V
CC
V – 0.5 V (0.8V )*
CC 0.4 V (0.2V )*
SCK
SO
SI
Note: * VCC – 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and
0.8VCC and 0.2VCC are the threshold voltages for transmit clock input.
CC
CC tSCKH
Figure 70 Serial Interface Timing
RL = 2.6 kΩ
VCC
Hitachi
1S2074 H
or equivalent
R =
12 kΩ
Test
point C =
30 pF
Figure 71 Timing Load Circuit
HD404344R Series/HD404394 Series
96
1
0.0
0.5
1.0
1.5
2.0
Icc (mA)
Vcc (V)
23456
Ta = 25°C, fcyc = fosc/4
Sample: Typ
(a) Icc vs Vcc Characteristics
(ceramic oscillator)
fosc = 4 MHz
fosc = 2 MHz
fosc = 1 MHz
fosc = 800 kHz
fosc = 400 kHz
1
0.0
1.0
0.5
1.5
2.0
2.5
Icc (mA)
Vcc (V)
23456
(b) Icc vs Vcc Characteristics
(resistor oscillator)
Ta = 25°C, Rf = 20 kΩ
fcyc = fosc/4
Sample: Typ
1
fosc (MHz)
Vcc (V)
23456
(c) fosc vs Vcc Characteristics
(resistor oscillator)
0
0.0
2.0
1.0
3.0
4.0
5.0
1.0
2.0
1.5
2.5
3.0
3.5
fosc (MHz)
Rf (kΩ)
10 20 30 40 50
(d) fosc vs Rf Characteristics
(resistor oscillator)
Ta = 25°C, Sample: TypTa = 25°C, Rf = 20 kΩ
Sample: Typ
0
VOL (V)
IOL (mA)
10 20 30 40 50
(e) VOL vs IOL Characteristics
(D1, D2, R1, R2 pins)
0.0
1.0
0.5
1.5
2.0
2.5 Ta = 25°C
Sample: Typ
Vcc = 5 V
Vcc = 3.5 V
Vcc = 2.5 V
Vcc = 4.5 V
Vcc = 5 V
Vcc = 5.5 V
Figure 72 Characteristics curve HD404344R series (consultation value)
HD404344R Series/HD404394 Series
97
Notes On ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions
(HD404344R and HD404394). A 4-kword data size is required to change ROM data to mask
manufacturing data since the program used is for a 4-kword version.
This limitation apply to the case of using EPROM and the case of using data base.
$0000
$000F
$0010
$003F
$0040
$03FF
$0400
$0FFF
ROM 1 kwords version:
HD404341R, HD40C4341R,
HD404391
Address $0400 to $0FFF
Vector address
Zero page subroutine
(64 words)
Pattern and program
(1,024 words)
ROM 2 kwords version:
HD404342R, HD40C4342R,
HD404392
Address $0800 to $0FFF
Fill this area with all 1s
Not used
$0000
$000F
$0010
$003F
$0040
$07FF
$0800
$0FFF
Vector address
Zero page subroutine
(64 words)
Pattern and program
(2,048 words)
Not used
HD404344R Series/HD404394 Series
98
HD404341R/HD404342R/HD404344R/HCD404344R/HD40C4341R/HD40C4342R/
HD40C4344R/HCD40C4344R Option List
2. ROM code media
Date of order
Customer
Department
Name
ROM code name
LSI number
EPROM:
Ceramic oscillator
External clock
RC oscillator
HD404341R/HD404342R/HD404344R/HCD404344R HD40C4341R/HD40C4342R/HD40C4344R/HCD40C4344R
f = MHz
f = MHz
3. System oscillator (OSC1–OSC2) (Shaded areas indicate selections that are not available.)
The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
HD404341R
HD404342R
HD404344R
HCD404344R
1. ROM size
DP-28S
FP-28DA
FP-30D
Chip
5. Package type
Note: The specifications of shipped chips differ from of the package product.
Please contact our sales staff for details.
1-kword
2-kword
4-kword
4-kword
Ceramic oscillator
External clock
HD404341R
HD404342R
HD404344R
HCD40C4344R
1-kword
2-kword
4-kword
4-kword
RC oscillator
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
Please check off the appropriate applications and enter the necessary information.
Used
Not used
4. Stop mode
HD404344R Series/HD404394 Series
99
HD404391/HD404392/HD404394 Option List
Date of order
Customer
Department
Name
ROM code name
LSI number
EPROM:
Ceramic oscillator
External clock
f = MHz
f = MHz
3. System oscillator (OSC1–OSC2)
The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
2. ROM code media
HD404391
HD404392
HD404394
1. ROM size
1-kword
2-kword
4-kword
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
DP-28S
FP-28DA
FP-30D
5. Package type
Used
Not used
4. Stop mode
Please check off the appropriate applications and enter the necessary information.
HD404344R Series/HD404394 Series
100
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
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Telex: 40815 HITEC HX
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Tel: <44> (1628) 585000
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Germany
Tel: <49> (89) 9 9180-0
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For further information write to:
