TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DDirect Upgrades for the TL06x Low-Power
BiFETs
DLow Power Consumption...
6.5 mW/Channel Typ
DOn-Chip Offset-Voltage Trimming for
Improved DC Performance
(1.5 mV, TL031A)
DHigher Slew Rate and Bandwidth Without
Increased Power Consumption
DAvailable in TSSOP for Small Form-Factor
Designs
description
The TL03x series of JFET-input operational amplifiers offer improved dc and ac characteristics over the TL06x
family of low-power BiFET operational amplifiers. On-chip zener trimming of offset voltage yields precision
grades as low as 1.5 mV (TL031A) for greater accuracy in dc-coupled applications. The Texas Instruments
improved BiFET process and optimized designs also yield improved bandwidths and slew rates without
increased power consumption. The TL03x devices are pin-compatible with the TL06x and can be used to
upgrade existing circuits or for optimal performance in new designs.
BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors without
sacrificing the output drive associated with bipolar amplifiers. This higher input impedance makes the TL3x
amplifiers better suited for interfacing with high-impedance sensors or very low-level ac signals. These devices
also feature inherently better ac response than bipolar or CMOS devices having comparable power
consumption.
The TL03x family has been optimized for micropower operation, while improving on the performance of the
TL06x series. Designers requiring significantly faster ac response should consider the Excalibur™ TLE206x
family of low-power BiFET operational amplifiers.
Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to
observe common-mode input-voltage limits and output swing when operating from a single supply. DC biasing
of the input signal is required, and loads should be terminated to a virtual-ground node at midsupply. The TI
TLE2426 integrated virtual-ground generator is useful when operating BiFET amplifiers from single supplies.
The TL03x devices are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply
systems, the TI LinCMOS families of operational amplifiers (TLC prefix) are recommended. When moving from
BiFET to CMOS amplifiers, particular attention should be paid to slew rate, bandwidth requirements, and output
loading.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Excalibur is a trademark of Texas Instruments.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
8
7
6
5
OFFSET N1
IN−
IN+
VCC−
NC
VCC+
OUT
OFFSET N2
3212019
910111213
4
5
6
7
8
18
17
16
15
14
NC
VCC+
NC
OUT
NC
NC
IN−
NC
IN+
NC
NC
OFFSET N1
NC
NC
NC
NC
OFFSET N2 NC
NC
VCC−
TL031x, TL031Ax
D, JG, OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
VCC −
VCC+
2OUT
2IN−
2IN+
3212019
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN−
NC
NC
1IN−
NC
1IN+
NC
NC
1OUT
NC
NC
NC
NC
2IN+
NC
CC−
V
CC+
V
TL031M, TL031AM
FK PACKAGE
(TOP VIEW) TL032M, TL032AM
FK PACKAGE
(TOP VIEW)
TL032x, TL032Ax
D, JG, OR P PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4IN+
NC
VCC−
NC
3IN+
1IN+
NC
VCC+
NC
2IN+
1IN−
1OUT
NC
3IN−
2IN−
NC
3OUT 4OUT
4IN−
2OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VCC+
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
VCC−
3IN+
3IN−
3OUT
TL034x, TL034Ax
D, J, N, OR PW PACKAGE
(TOP VIEW)
TL034M, TL034AM
FK PACKAGE
(TOP VIEW)
NC − No internal connection
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOMAX
AT 25°CSMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
TSSOP
(PW)
0.8 mV TL031ACD
TL032ACD — — — — TL031ACP
TL032ACP —
0°C to 70°C1.5 mV
TL031CD
TL032CD
TL034ACD
— — — TL034ACN TL031CP
TL032CP —
4 mV TL034CD — — — TL034CN — TL034CPW
0.8 mV TL031AID
TL032AID — — — — TL031AIP
TL032AIP —
−40°C to 85°C1.5 mV
TL031ID
TL032ID
TL034AID
— — — TL034AIN TL031IP
TL032IP —
4 mV TL034ID — — — TL034IN — —
0.8 mV TL031AMD
TL032AMD
TL031AMFK
TL032AMFK —TL031AMJG
TL032AMJG —TL031AMP
TL032AMP —
−55°C to 125°C1.5 mV
TL031MD
TL032MD
TL034AMD
TL031MFK
TL032MFK
TL034AMFK
TL034AMJ TL031MJG
TL032MJG TL034AMN TL031MP
TL032MP —
4 mV TL034MD TL034MFK TL034MJ — TL034MN — —
The D and PW packages are available taped and reeled and are indicated by adding an R suffix to device type (e.g., TL034CDR or TL034CPWR).
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
symbol (each amplifier)
−
+OUT
IN−
IN+
equivalent schematic (each amplifier)
R2
OFFSET N2
OFFSET N1
IN−
IN+
Q2
Q3
Q5
VCC+
Q14
Q6
R4
Q8 Q10 R7
Q11
R6
Q12
R3
C1
Q9
Q7
Q4
R5R1
Q1
JF1 JF2
Q13
Q16
R8
JF3 JF4
Q15
Q17
OUT
D1
VCC−
NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL031, TL031A.
See Note A
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (see Note 1): VCC+ 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC− −18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (any input) (see Notes 1 and 3) ±15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (each input) ±1 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO (each output) ±40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VCC+ 160 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of VCC− 160 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 4) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 5): D package (8 pin) 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
D package (14 pin) 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1 /16 inch) from case for 10 seconds: D, N, P, or PW package 260°C. . . . . . . . .
Lead temperature 1,6 mm (1 /16 inch) from case for 60 seconds: J or JG package 300°C. . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
2. Differential voltages are at IN+ with respect to IN−.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
FK 1375 mW 11.0 mW/°C880 mW 715 mW 275 mW
J1375 mW 11.0 mW/°C880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C672 mW 546 mW 210 mW
recommended operating conditions
C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX UNIT
VCC±Supply voltage ±5±15 ±5±15 ±5±15 V
V
Common mode input voltage
VCC± = ±5 V −1.5 4 −1.5 4 −1.5 4
V
VIC Common-mode input voltage VCC± = ±15 V −11.5 14 −11.5 14 −11.5 14 V
TAOperating free-air temperature 0 70 −40 85 −55 125 °C
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL031C and TL031AC electrical characteristics at specified free-air temperature
TL031C, TL031AC
PARAMETER TEST CONDITIONS TAVCC±= ±5 V VCC±= ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL031C
25°C 0.54 3.5 0.5 1.5
V
Input offset voltage
VO = 0,
V 0
TL031C Full range†4.5 2.5
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL031AC
25°C 0.41 2.8 0.34 0.8 mV
R
S =
50
Ω
TL031AC Full range†3.8 1.8
TL031C
25°C to
59
a
Tem
p
erature coefficient of VO = 0,
V 0
TL031C
25 C
to
70°C7.1 5.9
V/°C
aVIO
Temperature
coefficient
of
input offset voltage VIC =0,
RS
=
50 Ω
TL031AC
25°C to
59
μV/°C
input
offset
voltage
R
S =
50
Ω
TL031AC
25 C
to
70°C7.1 5.9 25
Input offset voltage
long-term drift‡
VO = 0,
VIC =0,
RS = 50 Ω
25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100
pA
IIO Input offset current
VO
=
0
,
VIC
=
0
See Figure 5 70°C 9 200 12 200 pA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200
pA
IIB Input bias current
VO
=
0
,
VIC
=
0
See Figure 5 70°C 50 400 80 400 pA
V
Common-mode input 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
M i iti k
25°C 3 4.3 13 14
VOM+
Maximum positive peak
output voltage swing
RL = 10 kΩ0°C 3 4.2 13 14 V
VOM+
ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
70°C 3 4.3 13 14
V
Mi ti k
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum negative peak
output voltage swing
RL = 10 kΩ0°C −3 −4.1 −12.5 −13.9 V
VOM
−ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
70°C −3 −4.2 −12.5 −14
V
25°C 4 12 5 14.3
AVD Large-signal differential
voltage amplification§
RL = 10 kΩ0°C 3 11.1 4 13.5 V/mV
AVD
voltage amplification
§
RL
10
kΩ
70°C 4 13.3 5 15.2
V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 4 pF
Cd
V V i
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
VIC = VICRmin,
VO=0 R
S=50Ω
0°C 70 87 75 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
V
O =
0
,
R
S =
50
Ω
70°C 70 87 75 94
dB
Supply
-
voltage
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VO = 0, RS = 50 Ω0°C 75 96 75 96 dB
SVR
rejection
ratio
(ΔVCC±/ΔVIO)
O,S
70°C 75 96 75 96
†Full range is 0°C to 70°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL031C and TL031AC electrical characteristics at specified free-air temperature (continued)
TL031C, TL031AC
PARAMETER TEST CONDITIONS TAVCC±= ±5 V VCC±= ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
25°C 1.9 2.5 6.5 8.4
PDTotal power dissipation VO = 0, No load 0°C1.8 2.5 6.3 8.4 mW
PD
Total
power
dissipation
VO
0,
No
load
70°C 1.9 2.5 6.3 8.4
mW
25°C 192 250 217 280
ICC Supply current VO = 0, No load 0°C184 250 211 280 μA
CC
pp y
O,
70°C 189 250 210 280
μ
TL031C and TL031AC operating characteristics at specified free-air temperature
TL031C, TL031AC
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
R10 kΩC100 F
25°C 2 1.5 2.9
SR+ Positive slew rate at
unity gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
0°C 1.8 1 2.6 V/μs
unity gain
†
S
ee
Fi
gure
1
70°C 2.2 1.5 3.2
V/μs
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at
unity gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
0°C 3.7 1.5 5 V/μs
unity gain
†
S
ee
Fi
gure
1
70°C 4 1.5 5
V/μs
VI(PP)
=
±10 mV,
25°C 138 132
trRise time
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF 0°C 134 127 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 70°C 150 142
ns
VI(PP)
=
±10 mV,
25°C 138 132
tfFall time
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF 0°C 134 127 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figure 1 70°C 150 142
ns
VI(PP)
=
±10 mV,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF 0°C 10% 4%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 70°C 12% 6%
TL031C
f = 10 Hz
61 61
E
q
uivalent in
p
ut
TL031C R
S
= 20 Ωf = 1 kHz 25°C41 41
nV/√H
Vn
Equivalent
input
noise voltage
TL031AC
RS
=
20
Ω
See Figure 3 f = 10 Hz
61 61 nV/√Hz
g
TL031AC f = 1 kHz 25°C41 41 60
In
Equivalent input noise
current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV
25°C 1 1.1
B1Unity-gain bandwidth
V
I =
10
mV
RL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 70°C 1 1
MHz
VI
=
10 mV
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
RL = 10 kΩ, CL = 25 pF 0°C 61°65°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 70°C 60°64°
†For VCC±= ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL031I and TL031AI electrical characteristics at specified free-air temperature
TL031I, TL031AI
PARAMETER TEST CONDITIONS TAVCC±= ±5 V VCC±= ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL031I
25°C 0.54 3.5 0.5 1.5
V
Input offset voltage
VO = 0,
V 0
TL031I Full range†5.3 3.3
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL031AI
25°C 0.41 2.8 0.34 0.8 mV
R
S =
50
Ω
TL031AI Full range†4.6 2.6
TL031I
25°C to
62
a
Temperature coefficient
f
VO = 0,
V 0
TL031I
25 C
to
85°C6.5 6.2
V/°C
aVIO of
input offset voltage
VIC = 0,
RS
=
50 Ω
TL031AI
25°C to
62
μV/°C
i
nput o
ff
set vo
l
tage
R
S =
50
Ω
TL031AI
25 C
to
85°C6.5 6.2 25
In
p
ut offset volta
g
eVO = 0,
V 0
25°C
004
V/mo
Input
offset
voltage
long-term drift‡VIC = 0,
RS = 50 Ω
25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100 pA
IIO Input offset current
VO
=
0
,
VIC
=
0
See Figure 5 85°C 0.02 0.45 0.02 0.45 nA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200 pA
IIB Input bias current
VO
=
0
,
VIC
=
0
See Figure 5 85°C 0.2 0.9 0.2 0.9 nA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
M i iti k
25°C 3 4.3 13 14
VOM+
Maximum positive peak
output voltage swing
RL = 10 kΩ−40°C 3 4.1 13 14 V
VOM+
ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
85°C 3 4.4 13 14
V
Mi ti k
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum negative peak
output voltage swing
RL = 10 kΩ−40°C −3 −4.1 −12.5 −13.8 V
VOM
−ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
85°C −3 −4.2 −12.5 −14
V
25°C 4 12 5 14.3
AVD Large-signal differential
voltage amplification§
RL = 10 kΩ−40°C 3 8.4 4 11.6 V/mV
AVD
voltage amplification
§
RL
10
kΩ
85°C 4 13.5 5 15.3
V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 4 pF
Cd
V V i
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
VIC = VICRmin,
VO=0 R
S=50Ω
−40°C 70 87 75 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
V
O =
0
,
R
S =
50
Ω
85°C 70 87 75 94
dB
Supply
-
voltage
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VO = 0, RS = 50 Ω−40°C75 96 75 96 dB
SVR
rejection
ratio
(ΔVCC±/ΔVIO)
O,
S
85°C 75 96 75 96
†Full range is −40°C to 85°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL031I and TL031AI electrical characteristics at specified free-air temperature (continued)
TL031I, TL031AI
PARAMETER TEST CONDITIONS TAVCC±= ±5 V VCC±= ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
25°C 1.9 2.5 6.5 8.4
PDTotal power dissipation VO = 0, No load −40°C1.4 2.5 5.4 8.4 mW
PD
Total
power
dissipation
VO
0,
No
load
85°C 1.9 2.5 6.2 8.4
mW
25°C 192 250 217 280
ICC Supply current VO = 0, No load −40°C144 250 181 280 μA
CC
pp y
O,
85°C 189 250 207 280
μ
TL031I and TL031AI operating characteristics at specified free-air temperature
TL031I, TL031AI
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
R10 kΩC100 F
25°C 2 1.5 2.9
SR+ Positive slew rate at
unity gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−40°C 1.6 1 2.1 V/μs
unity gain
†
S
ee
Fi
gure
1
85°C 2.3 1.5 3.3
V/μs
N ti l ttit
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−40°C 3.3 1.5 4.8 V/μs
ga
i
n
†
S
ee
Fi
gure
1
85°C 4.1 1.5 4.9
V/μs
VI(PP)
=
±10 mV,
25°C 138 132
trRise time
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF −40°C 132 123 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 85°C 154 146
ns
VI(PP)
=
±10 mV,
25°C 138 132
tfFall time
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF −40°C 132 123 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figure 1 85°C 154 146
ns
VI(PP)
=
±10 mV,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF −40°C 12% 5%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 85°C 13% 7%
TL031I
f = 10 Hz
25°C
61 61
Equivalent
it
TL031I R
S
= 20 Ωf = 1 kHz 25°C41 41
nV/√H
Vninput
noise voltage
TL031AI
RS
=
20
Ω
See Figure 3 f = 10 Hz
25°C
61 61 nV/√Hz
no
i
se vo
lt
age TL031AI f = 1 kHz 25°C41 41 60
Equivalent input noise
f 1 kHz
25°C
pA/√H
In
Equivalent
input
noise
current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV
25°C 1 1.1
B1Unity-gain bandwidth
V
I =
10
mV
RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 85°C 0.9 1
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −40°C 60°65°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 85°C 60°64°
†For VCC±= ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL031M and TL031AM electrical characteristics at specified free-air temperature
TL031M, TL031AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL031M
25°C 0.54 3.5 0.5 1.5
V
Input offset voltage
VO = 0,
V 0
TL031M Full range†6.5 4.5
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL031AM
25°C 0.41 2.8 0.34 0.8 mV
R
S =
50
Ω
TL031AM Full range†5.8 3.8
a
Temperature coefficient of VO = 0,
V 0
TL031M 25°C to
125°C5.1 4.3
V/°C
aVIO
Temperature
coefficient
of
input offset voltage VIC = 0,
RS = 50 ΩTL031AM 25°C to
125°C5.1 4.3
μV/°C
Input offset voltage
long-term drift‡
VO = 0,
VIC = 0,
RS = 50 Ω
25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100 pA
IIO Input offset current
VO
=
0
,
VIC
=
0
See Figure 5 125°C 0.2 10 0.2 10 nA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200 pA
IIB Input bias current
VO
=
0
,
VIC
=
0
See Figure 5 125°C 7 20 8 20 nA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
M i iti k
25°C 3 4.3 13 14
VOM+
Maximum positive peak
output voltage swing
RL = 10 kΩ−55°C 3 4.1 13 14 V
VOM+
ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
125°C 3 4.4 13 14
V
Mi ti k
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum negative peak
output voltage swing
RL = 10 kΩ−55°C −3 −4 −12.5 −13.8 V
VOM
−ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
125°C −3 −4.3 −12.5 −14
V
25°C 4 12 5 14.3
AVD Large-signal differential
voltage amplification§
RL = 10 kΩ−55°C 3 7.1 4 10.4 V/mV
AVD
voltage amplification
§
RL
10
kΩ
125°C 3 12.9 4 15
V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 4 pF
Cd
V V i
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
VIC = VICRmin,
VO=0 R
S=50Ω
−55°C 70 87 70 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
V
O =
0
,
R
S =
50
Ω
125°C 70 87 70 94
dB
Supply
-
voltage
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VO = 0, RS = 50 Ω−55°C75 96 75 95 dB
kSVR
rejection
ratio
(ΔVCC±/ΔVIO)
VO
0,
RS
50
Ω
125°C 75 96 75 96
dB
25°C 1.9 2.5 6.5 8.4
PDTotal power dissipation VO = 0, No load −55°C1.1 2.5 4.7 8.4 mW
D
pp
O,
125°C 1.8 2.5 5.8 8.4
†Full range is −55°C to 125°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL031M and TL031AM electrical characteristics at specified free-air temperature (continued)
TL031M, TL031AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
25°C 192 250 217 280
ICC Supply current VO = 0, No load −55°C114 250 156 280 μA
CC
pp y
O,
125°C 178 250 197 280
μ
TL031M and TL031AM operating characteristics at specified free-air temperature
TL031M, TL031AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
R10 kΩC100 F
25°C 2 1.5 2.9
SR+ Positive slew rate at
unity gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−55°C 1.4 1 1.9 V/μs
unity gain
†
S
ee
Fi
gure
1
125°C 2.4 1 3.5
V/μs
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at
unity gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−55°C 3.2 1 4.6 V/μs
unity gain
†
S
ee
Fi
gure
1
125°C 4.1 1 4.7
V/μs
VI(PP)
=
±10 mV,
25°C 138 132
trRise time
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF −55°C 142 123 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 125°C 166 158
ns
VI(PP)
=
±10 mV,
25°C 138 132
tfFall time
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF −55°C 142 123 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figure 1 125°C 166 158
ns
VI(PP)
=
±10 mV,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
mV
,
RL = 10 kΩ, CL = 100 pF −55°C 16% 6%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 125°C 14% 8%
TL031M
f = 10 Hz
25°C
61 61
Equivalent input TL031M R
S
= 20 Ωf = 1 kHz 25°C41 41
nV/√H
Vn
Equivalent
input
noise voltage
TL031AM
RS
=
20
Ω
See Figure 3 f = 10 Hz
25°C
61 61 nV/√Hz
TL031AM f = 1 kHz 25°C41 41
Equivalent input noise
f 1 kHz
25°C
pA/√H
In
Equivalent
input
noise
current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV,
25°C 1 1.1
B1Unity-gain bandwidth
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 125°C 0.9 0.9
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −55°C 57°64°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 125°C 59°62°
†For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL032C and TL032AC electrical characteristics at specified free-air temperature
TL032C, TL032AC
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL032C
25°C 0.69 3.5 0.57 1.5
V
Input offset voltage
VO = 0,
V 0
TL032C Full range†4.5 2.5
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL032AC
25°C 0.53 2.8 0.39 0.8 mV
R
S =
50
Ω
TL032AC Full range†3.8 1.8
aV
Temperature
ffi i t f i t
VO = 0,
V 0
TL032C 25°C to
70°C11.5 10.8
V/°C
a
VIO coefficient of input
offset voltage
VIC = 0,
RS = 50 ΩTL032AC 25°C to
70°C11.5 10.8 25
μV/°C
Input offset voltage
long-term drift‡
VO = 0,
VIC = 0,
RS = 50 Ω
25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100
pA
IIO Input offset current
VO
=
0
,
See Figure 5
VIC
=
0
70°C 9 200 12 200 pA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200
pA
IIB Input bias current
VO
=
0
,
See Figure 5
VIC
=
0
70°C 50 400 80 400 pA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
Maximum positive
25°C 3 4.3 13 14
VOM+
Maximum
positive
peak output voltage RL = 10 kΩ0°C 3 4.2 13 14 V
VOM+
peak
output
voltage
swing
RL
10
kΩ
70°C 3 4.3 13 14
V
Maximum negative
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum
negative
peak output voltage RL = 10 kΩ0°C −3 −4.1 −12.5 −13.9 V
VOM
−
peak
output
voltage
swing
RL
10
kΩ
70°C −3 −4.2 −12.5 −14
V
Large
-
signal
25°C 4 12 5 14.3
AVD
L
arge-s
i
gna
l
differential voltage RL = 10 kΩ0°C 3 11.1 4 13.5 V/mV
AVD
differential
voltage
amplification§
RL
10
kΩ
70°C 4 13.3 5 15.2
V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 14 pF
Cd
V V i
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
VIC = VICRmin,
VO=0 R
S=50Ω
0°C 70 87 75 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
V
O =
0
,
R
S =
50
Ω
70°C 70 87 75 94
dB
Supply
-
voltage
V±5Vt ±15 V
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VCC± = ±5 V to ±15 V,
VO=0 R
S=50Ω
0°C 75 96 75 96 dB
SVR
rejection
ratio
(ΔVCC±/ΔVIO)
V
O =
0
,
R
S =
50
Ω
70°C 75 96 75 96
†Full range is 0°C to 70°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL032C and TL032AC electrical characteristics at specified free-air temperature (continued)
TL032C, TL032AC
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Ttl di i ti
25°C 3.8 5 13 17
PD
Total power dissipation
(two amplifiers)
VO = 0, No load 0°C3.7 5 12.7 17 mW
PD
(t
wo amp
lifi
ers
)
VO
0,
No
load
70°C 3.8 5 12.6 17
mW
I
Suppl
y
current
V 0
No load
0°C 368 500 422 560
A
ICC
Supply
current
(two amplifiers) VO = 0, No load 70°C378 500 420 560 μA
VO1/VO2 Crosstalk attenuation AVD = 100 dB 25°C 120 120 dB
TL032C and TL032AC operating characteristics at specified free-air temperature
TL032C, TL032AC
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
MIN TYP MAX MIN TYP MAX
R10 kΩC100 F
25°C 1.2 1.5 2.9
SR+ Positive slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
0°C 1.8 1 2.6 V/μs
gain
†
S
ee
Fi
gure
1
70°C 2.2 1.5 3.2
V/μs
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
0°C 3.7 1.5 5 V/μs
gain
†
S
ee
Fi
gure
1
70°C 4 1.5 5
V/μs
VI(PP)
=
±10 V,
25°C 138 132
trRise time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF 0°C 134 127 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 70°C 150 142
ns
VI(PP)
=
±10 V,
25°C 138 132
tfFall time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF 0°C 134 127 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 70°C 150 142
ns
VI(PP)
=
±10 V,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF 0°C 10% 4%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 70°C 12% 6%
TL032C
f = 10 Hz
49 49
E
q
uivalent in
p
ut
TL032C R
S
= 20 Ωf = 1 kHz 25°C41 41
nV/√Hz
Vn
Equivalent
input
noise voltage
TL032AC
RS
=
20
Ω
See Figure 3 f = 10 Hz
49 49 nV/
√
Hz
g
TL032AC f = 1 kHz 25°C41 41 60
InEquivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV,
25°C 1 1.1
B1Unity-gain bandwidth
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 70°C 1 1
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF 0°C 61°65°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 70°C 60°64°
†For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL032I and TL032AI electrical characteristics at specified free-air temperature
TL032I, TL032AI
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL032I
25°C 0.69 3.5 0.57 1.5
V
Input offset voltage
VO = 0,
V 0
TL032I Full range†5.3 3.3
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL032AI
25°C 0.53 2.8 0.39 0.8 mV
R
S =
50
Ω
TL032AI Full range†4.6 2.6
aV
Temperature
ffi i t f i t
VO = 0,
V 0
TL032I 25°C to
85°C11.4 10.8
V/°C
a
VIO coefficient of input
offset voltage
VIC = 0,
RS = 50 ΩTL032AI 25°C to
85°C11.4 10.8 25
μV/°C
Input offset voltage
long-term drift‡
VO = 0,
VIC = 0,
RS = 50 Ω
25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100 pA
IIO Input offset current
VO
=
0
,
See Figure 5
VIC
=
0
85°C 0.02 0.45 0.02 0.45 nA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200 pA
IIB Input bias current
VO
=
0
,
See Figure 5
VIC
=
0
85°C 0.2 0.9 0.3 0.9 nA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
Maximum positive
25°C 3 4.3 13 14
VOM+
Maximum
positive
peak output voltage RL = 10 kΩ−40°C 3 4.2 13 14 V
VOM+
peak
output
voltage
swing
RL
10
kΩ
85°C 3 4.4 13 14
V
Maximum negative
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum
negative
peak output voltage RL = 10 kΩ−40°C −3 −4.1 −12.5 −13.8 V
VOM
−
peak
output
voltage
swing
RL
10
kΩ
85°C −3 −4.2 −12.5 −14
V
A
Lar
g
e-si
g
nal differential
R10 kΩ
−40°C 3 8.4 4 11.6
V/mV
AVD
Large
-
signal
differential
voltage amplification§RL = 10 kΩ85°C 4 13.5 5 15.3 V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 4 pF
Cd
V V i
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
VIC = VICRmin,
VO=0 R
S=50Ω
−40°C 70 87 75 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
V
O =
0
,
R
S =
50
Ω
85°C 70 87 75 94
dB
Supply
-
voltage
V±5Vt ±15 V
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VCC± = ±5 V to ±15 V,
VO=0 R
S=50Ω
−40°C 75 96 75 96 dB
SVR
rejection
ratio
(ΔVCC±/ΔVIO)
V
O =
0
,
R
S =
50
Ω
85°C 75 96 75 96
†Full range is −40°C to 85°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL032I and TL032AI electrical characteristics at specified free-air temperature (continued)
TL032I, TL032AI
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Total power
25°C 3.8 5 13 17
PD
Total
power
dissipation VO = 0, No load −40°C2.9 5 10.9 17 mW
PD
dissipation
(two amplifiers)
VO
0,
No
load
85°C 3.7 5 12.4 17
mW
Sl t
25°C 384 500 434 560
ICC
Supply current
(two amplifiers)
VO = 0, No load −40°C288 500 362 560 μA
ICC
(t
wo amp
lifi
ers
)
VO
0,
No
load
85°C 372 500 414 560
μA
VO1/VO2
Crosstalk
attenuation AVD = 100 dB 25°C 120 120 dB
TL032I and TL032AI operating characteristics at specified free-air temperature
TL032I, TL032AI
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
25°C 2 1.5 2.9
SR+ Positive slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF −40°C 1.6 1 2.1 V/μs
SR+
gain
†
RL
10
kΩ,
CL
100
pF
85°C 2.3 1.5 3.3
V/μs
25°C 3.9 1.5 5.1
SR− Negative slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF −40°C 3.3 1.5 4.8 V/μs
SR
gain
†
RL
10
kΩ,
CL
100
pF
85°C 4.1 1.5 4.9
V/μs
VI(PP)
=
±10 V,
25°C 138 132
trRise time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −40°C 132 123 ns
tr
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 85°C 154 146
ns
VI(PP)
=
±10 V,
25°C 138 132
tfFall time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −40°C 132 123 ns
tf
Fall
time
RL
10
kΩ,
CL
100
pF
See Figure 1 85°C 154 146
ns
VI(PP)
=
±10 V,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −40°C 12% 5%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 85°C 13% 7%
TL032I
f = 10 Hz
25°C
49 49
V
E
q
uivalent in
p
ut
TL032I R
S
= 20 Ωf = 1 kHz 25°C41 41
nV/√Hz
Vn
Equivalent
input
noise voltage
TL032AI
RS
=
20
Ω
See Figure 3 f = 10 Hz
25°C
49 49 nV/
√
Hz
g
TL032AI f = 1 kHz 25°C41 41 60
In
Equivalent input noise
current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV,
25°C 1 1.1
B1Unity-gain bandwidth
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHz
B1
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 85°C 0.9 1
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −40°C 61°65°
φm
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 85°C 60°64°
†For VCC± = ±5 V, VI(PP) = ±1 V; for VCC±= ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL032M and TL032AM electrical characteristics at specified free-air temperature
TL032M, TL032AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL032M
25°C 0.69 3.5 0.57 1.5
V
Input offset voltage
VO = 0,
V 0
TL032M Full range†6.5 4.5
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL032AM
25°C 0.53 2.8 0.39 0.8 mV
R
S =
50
Ω
TL032AM Full range†5.8 3.8
a
Tem
p
erature coefficient VO = 0,
V 0
TL032M 25°C to
125°C9.7 9.7
V/°C
aVIO
Temperature
coefficient
of input offset voltage VIC = 0,
RS = 50 ΩTL032AM 25°C to
125°C9.7 9.7
μV/°C
Input offset voltage
long-term drift‡
VO = 0,
VIC = 0,
RS = 50 Ω
25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100 pA
IIO Input offset current
VO
=
0
,
See Figure 5
VIC
=
0
125°C 0.2 10 0.2 10 nA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200 pA
IIB Input bias current
VO
=
0
,
See Figure 5
VIC
=
0
125°C 7 20 8 20 nA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
M i iti k
25°C 3 4.3 13 14
VOM+
Maximum positive peak
output voltage swing
RL = 10 kΩ−55°C 3 4.1 13 14 V
VOM+
ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
125°C 3 4.4 13 14
V
Mi ti k
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum negative peak
output voltage swing
RL = 10 kΩ−55°C −3 −4 −12.5 −13.8 V
VOM
−ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
125°C −3 −4.3 −12.5 −14
V
25°C 4 12 5 14.3
AVD Large-signal differential
voltage amplification§
RL = 10 kΩ−55°C 3 7.1 4 10.4 V/mV
AVD
voltage amplification
§
RL
10
kΩ
125°C 3 12.9 4 15
V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 4 pF
Cdjti
V V i
25°C 70 87 75 94
CMRR Common-mode rejection
ratio
VIC = VICRmin,
VO=0 R
S=50Ω
−55°C 70 87 70 94 dB
CMRR
ra
ti
o
V
O =
0
,
R
S =
50
Ω
125°C 70 87 70 94
dB
Supply
-
voltage
V±5Vt ±15 V
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VCC± = ±5 V to ±15 V,
VO=0 R
S=50Ω
−55°C 75 95 75 95 dB
SVR
rejection
ratio
(ΔVCC±/ΔVIO)
V
O =
0
,
R
S =
50
Ω
125°C 75 96 75 96
†Full range is −55°C to 125°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL032M and TL032AM electrical characteristics at specified free-air temperature (continued)
TL032M, TL032AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Total power dissipation
25°C 3.8 5 13 17
PD
Total
power
dissipation
(two amplifiers) VO = 0, No load −55°C2.3 5 9.4 17 mW
PD
(two
amplifiers)
VO = 0,
VO
0,
No
load
125°C 3.6 5 11.8 17
mW
Sl t
25°C 384 500 434 560
ICC
Supply current
(two amplifiers)
VO = 0, No load −55°C228 500 312 560 μA
ICC
(t
wo amp
lifi
ers
)
VO
0,
No
load
125°C 356 500 394 560
μA
VO1/VO2 Crosstalk attenuation AVD = 100 dB 25°C 120 120 dB
TL032M and TL032AM operating characteristics at specified free-air temperature
TL032M, TL032AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
R10 kΩC100 F
25°C 2 1.5 2.9
SR+ Positive slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See and Figure 1
−55°C 1.4 1 1.9 V/μs
gain
†
S
ee an
d
Fi
gure
1
125°C 2.4 1 3.5
V/μs
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See and Figure 1
−55°C 3.2 1 4.6 V/μs
gain
†
S
ee an
d
Fi
gure
1
125°C 4.1 1 4.7
V/μs
VI(PP)
=
±10 V,
25°C 138 132
trRise time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −55°C 142 123 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 125°C 166 58
ns
VI(PP)
=
±10 V,
25°C 138 132
tfFall time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −55°C 142 123 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figure 1 125°C 166 158
ns
VI(PP)
=
±10 V,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −55°C 16% 6%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 125°C 14% 8%
TL032M
f = 10 Hz
25°C
49 49
Equivalent
input noise
TL032M R
S
= 20 Ωf = 1 kHz 25°C41 41
nV/√Hz
Vninput noise
v
o
lt
age
TL032AM
RS
=
20
Ω
See Figure 3 f = 10 Hz
25°C
49 49 nV/
√
Hz
voltage
TL032AM f = 1 kHz 25°C41 41
In
Equivalent input noise
current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV,
25°C 1 1.1
B1 Unity-gain bandwidth
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 125°C 0.9 0.9
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −55°C 57°64°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 125°C 59°62°
†For VCC± = ±5 V, VI(PP) = ±1 V; for VCC±= ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL034C and TL034AC electrical characteristics at specified free-air temperature
TL034C, TL034AC
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL034C
25°C 0.91 6 0.79 4
V
Input offset voltage
VO = 0,
V 0
TL034C Full range†8.2 6.2
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL034AC
25°C 0.7 3.5 0.58 1.5 mV
R
S =
50
Ω
TL034AC Full range†5.7 3.7
a
Tem
p
erature coefficient VO = 0,
V 0
TL034C 25°C to
70°C11.6 12
V/°C
aVIO
Temperature
coefficient
of input offset voltage VIC = 0,
RS = 50 ΩTL034AC 25°C to
70°C11.6 12 25
μV/°C
Input offset voltage
long-term drift‡
VO = 0,
VIC = 0,
RS = 50 Ω25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100
pA
IIO Input offset current
VO
=
0
,
VIC
=
0
See Figure 5 70°C 9 200 12 200 pA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200
pA
IIB Input bias current
VO
=
0
,
VIC
=
0
See Figure 5 70°C 50 400 80 400 pA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
M i iti k
25°C 3 4.3 13 14
VOM+
Maximum positive peak
output voltage swing
RL = 10 kΩ0°C 3 4.2 13 14 V
VOM+
ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
70°C 3 4.3 13 14
V
Mi ti k
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum negative peak
output voltage swing
RL = 10 kΩ0°C −3 −4.1 −12.5 −13.9 V
VOM
−ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
70°C −3 −4.2 −12.5 −14
V
25°C 4 12 5 14.3
AVD Large-signal differential
voltage amplification§
RL = 10 kΩ0°C 3 11.1 4 13.5 V/mV
AVD
voltage amplification
§
RL
10
kΩ
70°C 4 13.3 5 15.2
V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 14 pF
Cd
VIC
=
VICRmin,
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
V
IC =
V
ICR
min
,
VO = 0, 0°C 70 87 75 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
VO
0,
RS = 50 Ω70°C 70 87 75 94
dB
Supply
-
voltage
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VO = 0, RS = 50 Ω0°C 75 96 75 96 dB
SVR
rejection
ratio
(ΔVCC±/ΔVIO)
O,S
70°C 75 96 75 96
†Full range is 0°C to 70°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL034C and TL034AC electrical characteristics at specified free-air temperature (continued)
TL034C, TL034AC
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Ttl di i ti
25°C 7.7 10 26 34
PD
Total power dissipation
(two amplifiers)
VO = 0, No load 0°C 7.4 10 25.3 34 mW
PD
(t
wo amp
lifi
ers
)
VO
0,
No
load
70°C 7.6 10 25.2 34
mW
Sl t(f
25°C 0.77 1 0.87 1.12
ICC
Supply current (four
amplifiers)
VO = 0, No load 0°C 0.74 1 0.85 1.12 mA
ICC
amp
lifi
ers
)
VO
0,
No
load
70°C 0.76 1 0.84 1.12
mA
VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB
TL034C and TL034AC operating characteristics at specified free-air temperature
TL034C, TL034AC
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
R10 kΩC100 F
25°C 2 1.5 2.9
SR+ Positive slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
0°C 1.8 1 2.6 V/μs
gain
†
S
ee
Fi
gure
1
70°C 2.2 1.5 3.2
V/μs
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
0°C 3.7 1.5 5 V/μs
gain
†
S
ee
Fi
gure
1
70°C 4 1.5 5
V/μs
VI(PP)
=
±10 V,
25°C 138 132
trRise time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF 0°C 134 127 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 70°C 150 142
ns
VI(PP)
=
±10 V,
25°C 138 132
tfFall time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF 0°C 134 127 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figure 1 70°C 150 142
ns
VI(PP)
=
±10 V,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF 0°C 10% 4%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 70°C 12% 6%
TL034C
f = 10 Hz
83 83
E
q
uivalent in
p
ut
TL034C R
S
= 20 Ωf = 1 kHz 25°C43 43
nV/√Hz
Vn
Equivalent
input
noise voltage
TL034AC
RS
=
20
Ω
See Figure 3 f = 10 Hz
83 83 nV/
√
Hz
g
TL034AC f = 1 kHz 25°C43 43 60
InEquivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV
25°C 1 1.1
B1Unity-gain bandwidth
V
I =
10
mV
RL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 70°C 1 1
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF 0°C 61°65°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 70°C 60°64°
†For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL034I and TL034AI electrical characteristics at specified free-air temperature
TL034I, TL034AI
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL034I
25°C 0.91 3.6 0.79 4
V
Input offset voltage
VO = 0,
V 0
TL034I Full range†9.3 7.3
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL034AI
25°C 0.7 3.5 0.58 1.5 mV
R
S =
50
Ω
TL034AI Full range†6.8 4.8
a
Tem
p
erature coefficient VO = 0, VIC
0
TL034I 25°C to
85°C11.5 11.6
V/°C
aVIO
Temperature
coefficient
of input offset voltage = 0,
RS = 50 ΩTL034AI 25°C to
85°C11.5 11.6 25
μV/°C
Input offset voltage
long-term drift‡
VO = 0,
VIC = 0,
RS = 50 Ω25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100 pA
IIO Input offset current
VO
=
0
,
VIC
=
0
See Figure 5 85°C 0.02 0.45 0.02 0.45 nA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200 pA
IIB Input bias current
VO
=
0
,
VIC
=
0
See Figure 5 85°C 0.2 0.9 0.3 0.9 nA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
M i iti k
25°C 3 4.3 13 14
VOM+
Maximum positive peak
output voltage swing
RL = 10 kΩ−40°C 3 4.1 13 14 V
VOM+
ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
85°C 3 4.4 13 14
V
Maximum negative
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum
negative
peak RL = 10 kΩ−40°C −3 −4.1 −12.5 −13.8 V
VOM
−
peak
output voltage swing
RL
10
kΩ
85°C −3 −4.2 −12.5 −14
V
A
Lar
g
e-si
g
nal differential
R10 kΩ
−40°C 4 12 5 14.3
V/mV
AVD
Large
-
signal
differential
voltage amplification§RL = 10 kΩ85°C 3 8.4 4 11.6 V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 4 pF
Cd
VIC
=
VICRmin,
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
V
IC =
V
ICR
min
,
VO = 0, −40°C 70 87 75 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
VO
0,
RS = 50 Ω85°C 70 87 75 94
dB
Supply
-
voltage
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VO = 0, RS = 50 Ω−40°C 75 96 75 96 dB
SVR
rejection
ratio
(ΔVCC±/ ΔVIO)
O,S
85°C 75 96 75 96
†Full range is −40°C to 85°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL034I and TL034AI electrical characteristics at specified free-air temperature (continued)
TL034I, TL034AI
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Ttl di i ti
25°C 7.7 10 26 34
PD
Total power dissipation
(four amplifiers)
VO = 0, No load −40°C 5.8 10 21.7 34 mW
PD
(f
our amp
lifi
ers
)
VO
0,
No
load
85°C 7.4 10 24.8 34
mW
Sl t
25°C 0.77 1 0.87 1.12
ICC
Supply current
(four amplifiers)
VO = 0, No load −40°C 0.58 1 0.72 1.12 mA
ICC
(f
our amp
lifi
ers
)
VO
0,
No
load
85°C 0.74 1 0.83 1.12
mA
VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB
TL034I and TL034AI operating characteristics
TL034I, TL034AI
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
R10 kΩC100 F
25°C 2 1.5 2.9
SR+ Positive slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−40°C 1.6 1 2.1 V/μs
gain
†
S
ee
Fi
gure
1
85°C 2.3 1.5 3.3
V/μs
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−40°C 3.3 1.5 4.8 V/μs
gain
†
S
ee
Fi
gure
1
85°C 4.1 1.5 4.9
V/μs
VI(PP)
=
±10 V,
25°C 138 132
trRise time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −40°C 132 123 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 85°C 154 146
ns
VI(PP)
=
±10 V,
25°C 138 132
tfFall time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −40°C 132 123 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 85°C 154 146
ns
VI(PP)
=
±10 V,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −40°C 12% 5%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 85°C 13% 7%
TL034I
f = 10 Hz
25°C
83 83
E
q
uivalent in
p
ut
TL034I R
S
= 20 Ωf = 1 kHz 25°C43 43
nV/√Hz
Vn
Equivalent
input
noise voltage
TL034AI
RS
=
20
Ω
See Figure 3 f = 10 Hz
25°C
83 83 nV/
√
Hz
g
TL034AI f = 1 kHz 25°C43 43 60
In
Equivalent input noise
current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV,
25°C 1 1.1
B1Unity-gain bandwidth
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 85°C 0.9 1
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −40°C 61°65°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 85°C 60°64°
†For VCC± = ±5 V, VI(PP) = ±1 V; for VCC±= ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL034M and TL034AM electrical characteristics at specified free-air temperature
TL034M, TL034AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
TL034M
25°C 0.91 3.6 0.78 4
V
Input offset voltage
VO = 0,
V 0
TL034M Full range†11 9
mV
VIO Input offset voltage VIC = 0,
R
S
=
50
Ω
TL034AM
25°C 0.7 3.5 0.58 1.5 mV
R
S =
50
Ω
TL034AM Full range†8.5 6.5
a
Tem
p
erature coefficient of VO = 0,
V 0
TL034M 25°C to
125°C10.6 10.9
V/°C
aVIO
Temperature
coefficient
of
input offset voltage VIC = 0,
RS = 50 ΩTL034AM 25°C to
125°C10.6 10.9
μV/°C
Input offset voltage
long-term drift‡
VO = 0,
VIC = 0,
RS = 50 Ω 25°C 0.04 0.04 μV/mo
I
Input offset current
V
O
= 0, VI
C
= 0 25°C 1 100 1 100 pA
IIO Input offset current
VO
=
0
,
VIC
=
0
See Figure 5 125°C 0.2 10 0.2 10 nA
I
Input bias current
V
O
= 0, VI
C
= 0 25°C 2 200 2 200 pA
IIB Input bias current
VO
=
0
,
VIC
=
0
See Figure 5 125°C 7 20 8 20 nA
V
Common-mode in
p
ut 25°C−1.5
to 4
−3.4
to 5.4
−11.5
to 14
−13.4
to 15.4
V
VICR
Common mode
input
voltage range Full range†−1.5
to 4
−11.5
to 14
V
M i iti k
25°C 3 4.3 13 14
VOM+
Maximum positive peak
output voltage swing
RL = 10 kΩ−55°C 3 4.1 13 14 V
VOM+
ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
125°C 3 4.4 13 14
V
Mi ti k
25°C −3 −4.2 −12.5 −13.9
VOM−
Maximum negative peak
output voltage swing
RL = 10 kΩ−55°C −3 −4 −12.5 −13.8 V
VOM
−ou
t
pu
t
vo
lt
age sw
i
ng
RL
10
kΩ
125°C −3 −4.3 −12.5 −14
V
25°C 4 12 5 14.3
AVD Large-signal differential
voltage amplification§
RL = 10 kΩ−55°C 3 7.1 4 10.4 V/mV
AVD
voltage amplification
§
RL
10
kΩ
125°C 3 12.9 4 15
V/mV
riInput resistance 25°C 1012 1012 Ω
ciInput capacitance 25°C 5 4 pF
Cd
V V i
25°C 70 87 75 94
CMRR Common-mode
rejection ratio
VIC = VICRmin,
VO=0 R
S=50Ω
−55°C 70 87 70 94 dB
CMRR
re
j
ec
ti
on ra
ti
o
V
O =
0
,
R
S =
50
Ω
125°C 70 87 70 94
dB
Supply
-
voltage
25°C 75 96 75 96
kSVR
Supply
-
voltage
rejection ratio VO = 0, RS = 50 Ω−55°C 75 95 75 95 dB
SVR
rejection
ratio
(ΔVCC±/ΔVIO)
O,S
125°C 75 96 75 96
†Full range is −55°C to 125°C.
‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
§At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL034M and TL034AM electrical characteristics at specified free-air temperature (continued)
TL034M, TL034AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Ttl di i ti
25°C 7.7 10 26 34
PD
Total power dissipation
(two amplifiers)
VO = 0, No load −55°C4.6 12 18.7 45 mW
PD
(t
wo amp
lifi
ers
)
VO
0,
No
load
125°C 7.1 12 23.6 45
mW
Sl t
25°C 0.77 1 0.87 1.12
ICC
Supply current
(two amplifiers)
VO = 0, No load −55°C0.46 1.2 0.62 1.5 mA
ICC
(t
wo amp
lifi
ers
)
VO
0,
No
load
125°C 0.71 1.2 0.79 1.5
mA
VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB
TL034M and TL034AM operating characteristics at specified free-air temperature
TL034M, TL034AM
PARAMETER TEST CONDITIONS TAVCC± = ±5 V VCC± = ±15 V UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
R10 kΩC100 F
25°C 2 1.5 2.9
SR+ Positive slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−55°C 1.4 1 1.9 V/μs
gain
†
S
ee
Fi
gure
1
125°C 2.4 1 3.5
V/μs
R10 kΩC100 F
25°C 3.9 1.5 5.1
SR− Negative slew rate at unity
gain†
RL = 10 kΩ, CL = 100 pF
See Figure 1
−55°C 3.2 1 4.6 V/μs
gain
†
S
ee
Fi
gure
1
125°C 4.1 1 4.7
V/μs
VI(PP)
=
±10 V,
25°C 138 132
trRise time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −55°C 142 123 ns
Rise
time
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 125°C 166 58
ns
VI(PP)
=
±10 V,
25°C 138 132
tfFall time
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −55°C 142 123 ns
Fall
time
RL
10
kΩ,
CL
100
pF
See Figure 1 125°C 166 158
ns
VI(PP)
=
±10 V,
25°C11% 5%
Overshoot factor
V
I(PP) =
±10
V
,
RL = 10 kΩ, CL = 100 pF −55°C 16% 6%
Overshoot
factor
RL
10
kΩ,
CL
100
pF
See Figures 1 and 2 125°C 14% 8%
TL034M
f = 10 Hz
25°C
83 83
Equivalent input TL034M R
S
= 20 Ωf = 1 kHz 25°C43 43
nV/√Hz
Vn
Equivalent
input
noise voltage
TL034AM
RS
=
20
Ω
See Figure 3 f = 10 Hz
25°C
83 83 nV/
√
Hz
TL034AM f = 1 kHz 25°C43 43
In
Equivalent input noise
current f = 1 kHz 25°C 0.003 0.003 pA/√Hz
VI
=
10 mV,
25°C 1 1.1
B1 Unity-gain bandwidth
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHz
Unity gain
bandwidth
RL
10
kΩ,
CL
25
pF
See Figure 4 125°C 0.9 0.9
MHz
VI
=
10 mV,
25°C 61°65°
φmPhase margin at unity gain
V
I =
10
mV
,
RL = 10 kΩ, CL = 25 pF −55°C 57°64°
gyg
RL
10
kΩ,
CL
25
pF
See Figure 4 125°C 59°62°
†For VCC± = ±5 V, VI(PP) = ±1 V; for VCC±= ±15 V, VI(PP) = ±5 V
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 1. Slew-Rate and Overshoot Test Circuit
VI
+
−
VCC+
VCC−
VO
CL
(see Note A) RL
NOTE A: CL includes fixture capacitance.
Figure 2. Rise Time and Overshoot Waveform
Overshoot
10%
90%
tr
Figure 3. Noise-Voltage Test Circuit
VCC−
VCC+
−
VO
RSRS
10 kΩ
Figure 4. Unity-Gain Bandwidth and
Phase-Margin Test Circuit
(see Note A)
CL
VO
VCC−
VCC+
RL
VI
10 kΩ
100 Ω
NOTE A: CL includes fixture capacitance.
+
−
+
−
VCC+
VCC−
Picoammeters
Ground Shield
Figure 5. Input-Bias and Offset-Current Test Circuit
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
typical values
Typical values presented in this data sheet represent the median (50% point) of device parametric performance.
input bias and offset current
At the picoampere bias current level typical of the TL03x and TL03xA, accurate measurement of the bias current
becomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily can
exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses
a two-step process. The socket leakage is measured using picoammeters with bias voltages applied but with
no device in the socket. The device is then inserted into the socket and a second test that measures both the
socket leakage and the device input bias current is performed. The two measurements are then subtracted
algebraically to determine the bias current of the device.
noise
With the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage density
is performed at f = 1 kHz, unless otherwise noted.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Distribution of TL03x input offset voltage 6−11
Distribution of TL03x input offset-voltage temperature coefficient 12−14
Input bias current vs Common-mode input voltage 15
Input bias current and input offset current vs Free-air temperature 16
Common-mode input voltage vs Supply voltage 17
Common-mode input voltage vs Free-air temperature 18
Output voltage vs Differential input voltage 19, 20
Maximum peak output voltage vs Supply voltage 21
Maximum peak-to-peak output voltage vs Frequency 22
Maximum peak output voltage vs Output current 23, 24
Maximum peak output voltage vs Free-air temperature 25, 26
Large-signal differential voltage amplification vs Load resistance 27
Large-signal differential voltage amplification and Phase shift vs Frequency 28
Large-signal differential voltage amplification vs Free-air temperature 29
Output impedance vs Frequency 30
Common-mode rejection ratio vs Frequency 31, 32
Common-mode rejection ratio vs Free-air temperature 33
Supply-voltage rejection ratio vs Free-air temperature 34
Short-circuit output current vs Supply voltage 35
Short-circuit output current vs Time 36
Short-circuit output current vs Free-air temperature 37
Equivalent input noise voltage vs Frequency (TL031 and TL031A) 38
Equivalent input noise voltage vs Frequency (TL032 and TL032A) 39
Equivalent input noise voltage vs Frequency (TL034 and TL034A) 40
Supply current vs Supply voltage (TL031 and TL031A) 41
Supply current vs Supply voltage (TL032 and TL032A) 42
Supply current vs Supply voltage (TL034 and TL034A) 43
Supply current vs Free-air temperature (TL031 and TL031A) 44
Supply current vs Free-air temperature (TL032 and TL032A) 45
Supply current vs Free-air temperature (TL034 and TL034A) 46
Slew rate vs Load resistance 47, 48
Slew rate vs Free-air temperature 49, 50
Overshoot factor vs Load capacitance 51
Total harmonic distortion vs Frequency 52
Unity-gain bandwidth vs Supply voltage 53
Unity-gain bandwidth vs Free-air temperature 54
Phase margin vs Supply voltage 55
Phase margin vs Load capacitance 56
Phase margin vs Free-air temperature 57
Voltage-follower small-signal pulse response 58
Voltage-follower large-signal pulse response 59, 60
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
0
Percentage of Units − %
VIO − Input Offset Voltage − mV
2
4
6
8
10
12
14
−1.2 −0.6 0 0.6 1.2
DISTRIBUTION OF TL031
INPUT OFFSET VOLTAGE
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
1681 Units Tested From 1 Wafer Lot
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±15 V
ÎÎÎÎ
ÎÎÎÎ
TA = 25°C
P Package
Figure 7
0
−900
Percentage of Units − %
VIO − Input Offset Voltage − μV
2
4
6
8
10
12
14
16
−600 0 300 600 900
1433 Units Tested From 1 Wafer Lot
VCC± = ±15 V
ÎÎÎÎÎ
ÎÎÎÎÎ
P Package
DISTRIBUTION OF TL031A
INPUT OFFSET VOLTAGE
TA = 25°C
−300
Figure 8
−1.2
0
Percentage of Amplification − %
VIO − Input Offset Voltage − mV
12
−0.6 0 0.6 1.2
3
6
9
DISTRIBUTION OF TL032
INPUT OFFSET VOLTAGE
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
1681 Amplifiers Tested From 1 Wafer Lot
ÎÎÎÎ
ÎÎÎÎ
TA = 25°C
P Package
VCC± = ±15 V
Figure 9
−900
0
Percentage of Amplifiers − %
VIO − Input Offset Voltage − μV
900
15
−600 −300 0 300 600
3
6
9
12
DISTRIBUTION OF TL032A
INPUT OFFSET VOLTAGE
1321 Amplifiers Tested From 1 Wafer Lot
VCC± = ±15 V
TA = 25°C
P Package
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
−1.2
0
VIO − Input Offset Voltage − mV
12
−0.6 0 0.6 1.2
3
6
9
DISTRIBUTION OF TL034
INPUT OFFSET VOLTAGE
TA = 25°C
ÎÎÎÎ
D Package
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±15 V
ÎÎÎÎÎÎÎÎÎÎÎÎ
1681 Amplifiers Tested From 1 Wafer Lot
Percentage of Amplifiers − %
Figure 11
−1.8
0
Percentage of Amplifiers − %
VIO − Input Offset Voltage − mV
1.8
−1.2 0.6 0 0.6 1.2
3
6
9
12
DISTRIBUTION OF TL034A
INPUT OFFSET VOLTAGE
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
1716 Amplifiers Tested From 3 Wafer Lots
ÎÎÎÎÎ
N Package
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VCC± = ±15 V
TA = 25°C
15
Figure 12
0
−30
Percentage of Units − %
− Input Offset-Voltage Temperature Coefficient − μV/°C
6
12
18
24
−20 −10 0 10 20 30
DISTRIBUTION OF TL031
INPUT OFFSET-VOLTAGE
TEMPERATURE COEFFICIENT
76 Units Tested From 1 Wafer Lot
VCC± = ±15 V
TA = 25°C to 125°C
P Package
aVIO
Figure 13
−40
0
Percentage of Amplifiers − %
− Temperature Coefficient − μV/°C
40
30
5
10
15
20
25
−30 −20 −10 0 10 20 30
DISTRIBUTION OF TL032
INPUT OFFSET-VOLTAGE
TEMPERATURE COEFFICIENT
P Package
VCC± = ±15 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
160 Amplifiers Tested From 2 Wafer Lots
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
TA = 25°C to 125°C
aVIO
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
−40
0
Percentage of Amplifiers − %
− Temperature Coefficient − μV/°C
40
30
5
10
15
20
25
−30 −20 −10 0 10 20 30
DISTRIBUTION OF TL034
INPUT OFFSET-VOLTAGE
TEMPERATURE COEFFICIENT
D Package
VCC± = ±15 V
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
160 Amplifiers Tested From 2 Wafer Lots
ÎÎÎÎÎÎ
TA = 25°C to 125°C
aVIO
Figure 15
−10
−15
IIB − Input Bias Current − nA
VIC − Common-Mode Input Voltage − V
−5
0
5
10
−10 −5 0 5 10 15
TA = 25°C
VCC± = ±15 V
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
IB
I
Figure 16
0.00125
TA − Free-Air Temperature − °C
0.01
0.1
1
10
45 65 85 105 125
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT†
vs
FREE-AIR TEMPERATURE
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC± = ±15 V
VO = 0
VIC = 0
ÎÎ
ÎÎ
IIO
ÎÎÎ
ÎÎÎ
IIB
IIB and IIO − Input Bias and Input Offset Current − nA
IB
IIIO
Figure 17
−16 0
VIC − Common-Mode Input Voltage − V
|VCC±| − Supply Voltage − V
−12
−8
−4
0
4
8
12
16
2 4 6 8 10 12 14 16
TA = 25°C
ÎÎÎÎÎ
ÎÎÎÎÎ
Positive Limit
ÎÎÎÎÎ
ÎÎÎÎÎ
Negative Limit
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
ÁÁ
VIC
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
1251007550250−25−50
20
15
10
5
0
−5
−10
−15
TA − Free-Air Temperature −°C
−75
−20
VCC± = ±15 V
ÎÎÎÎÎ
Positive Limit
ÎÎÎÎÎ
ÎÎÎÎÎ
Negative Limit
COMMON-MODE INPUT VOLTAGE†
vs
FREE-AIR TEMPERATURE
VIC − Common-Mode Input Voltage − V
ÁÁÁ
ÁÁÁ
VIC
Figure 19
−1.5
−5
−1
0
0.5
1
1.5
−4−3−2−1012345
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
−0.5
ÎÎÎÎÎ
ÎÎÎÎÎ
RL = 1 kΩ
ÎÎÎÎ
RL = 2 kΩ
ÎÎÎÎ
RL = 5 kΩ
ÎÎÎÎÎ
ÎÎÎÎÎ
RL = 10 kΩ
ÎÎÎÎÎ
ÎÎÎÎÎ
RL = 20 kΩ
VCC± = ±5 V
TA = 25°C
ÎÎÎ
RL = 1 kΩ
ÎÎÎ
ÎÎÎ
RL = 2 kΩ
ÎÎÎÎ
ÎÎÎÎ
RL = 5 kΩ
ÎÎÎÎ
ÎÎÎÎ
RL = 20 kΩ
ÎÎÎÎ
RL = 10 kΩ
− Output Voltage − V
VO
VID − Differential Input Voltage − V
Figure 20
−1.5
−15
−1
−0.5
0
0.5
1
−10 −5 0 5 10
1.5
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
15
ÈÈÈÈ
ÈÈÈÈ
RL = 5 kΩ
ÈÈÈÈ
ÈÈÈÈ
RL = 10 kΩ
ÈÈÈÈ
RL = 20 kΩ
ÈÈÈÈ
ÈÈÈÈ
RL = 50 kΩ
TA = 25°C
VCC± = ±15 V
VID − Differential Input Voltage − V
− Output Voltage − V
VO
RL = 5 kΩ
RL = 10 kΩ
RL = 20 kΩ
RL = 50 kΩ
Figure 21
−16 0
VOM − Maximum Peak Output Voltage − V
|VCC±| − Supply Voltage − V
−12
−8
−4
0
4
8
12
16
2 4 6 8 10121416
TA = 25°C
RL = 10 kΩ
ÎÎÎ
ÎÎÎ
VOM−
VOM+
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
V
OM
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
0
1 k
VOPP − Maximum Peak-to-Peak Output Voltage − V
f − Frequency − Hz
5
10
15
20
25
30
10 k 100 k 1 M
TA = 125°C
VCC± = ±15 V
TA = −55°C
VCC± = ±5 V
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE†
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
VO(PP)
ÎÎÎÎÎ
ÎÎÎÎÎ
RL = 10 kΩ
Figure 23
− Maximum Peak Output Voltage − V
00
|IO| − Output Current − mA
1
2
3
4
5
5 101520
VOM+
VOM−
VCC± = ±5 V
TA = 25°C
MAXIMUM PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
|V |
OM
Figure 24
0
0
|IO| − Output Current − mA
5 1015202530
2
4
6
8
10
12
14
16
ÎÎÎ
ÎÎÎ
VOM−
ÎÎÎÎ
ÎÎÎÎ
VOM+
VCC± = ±15 V
TA = 25°C
MAXIMUM PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
− Maximum Peak Output Voltage − V|V |
OM
Figure 25
−5
−75
VOM − Maximum Peak Output Voltage − V
TA − Free-Air Temperature − °C
−4
−3
−2
−1
0
1
2
3
4
5
−50 −25 0 25 50 75 100 125
ÎÎÎÎ
VOM+
ÎÎÎ
ÎÎÎ
VOM−
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±5 V
RL = 10 kΩ
MAXIMUM PEAK OUTPUT VOLTAGE†
vs
FREE-AIR TEMPERATURE
ÁÁÁ
ÁÁÁ
V
OM
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 26
−16
TA − Free-Air Temperature −°C
−75 −50 −25 0 25 50 75 100 125
−12
−8
−4
0
4
8
12
16
VOM+
MAXIMUM PEAK OUTPUT VOLTAGE†
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±15 V
RL = 10 kΩ
VOM − Maximum Peak Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
V
OM
ÎÎÎ
ÎÎÎ
VOM−
Figure 27
0
RL − Load Resistance − Ω
5
10
15
20
25
30
35
40
10 k 100 k 1 M
VCC± = ±15 V
VCC± = ±5 V
TA = 25°C
VO = ±1 V
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
− Large-Signal Differential
AVD
Voltage Amplification − V/mV
0.110
f − Frequency − Hz
100 k
10 k
1 k
100
10
1
100 1 k 10 k 100 k 1 M 10 M
0°
30°
60°
90°
120°
150°
180°
Phase Shift
ÎÎÎ
ÎÎÎ
AVD
VCC± = ±15 V
RL = 10 kΩ
CL = 25 pF
TA = 25°C
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
ÎÎÎÎ
ÎÎÎÎ
Phase Shift
− Large-Signal Differential
AVD
Voltage Amplification
Figure 28
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 29
−75
1
TA − Free-Air Temperature − °C
125
50
−50 −25 0 25 50 75 100
10
VCC± = ±15 V
ÎÎÎÎ
ÎÎÎÎ
RL = 10 kΩ
VCC± = ±5 V
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†
vs
FREE-AIR TEMPERATURE
− Large-Signal Differential
AVD
Voltage Amplification − V/mV
Figure 30
1 k
10
zo − Output Impedence −
f − Frequency − Hz
100 k
200
10 k
20
40
60
80
100
AVD = 100
AVD = 10
AVD = 1
VCC± = ±15 V
ro (open loop) ≈ 250 Ω
OUTPUT IMPEDANCE
vs
FREQUENCY
ÁÁ
Ω
ÎÎÎÎÎ
TA = 25°C
ÁÁ
ÁÁ
zo
Figure 31
10
0
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
10 M
100
100 1 k 10 k 100 k 1 M
10
20
30
40
50
60
70
80
90
VCC± = ±5 V
ÎÎÎÎ
ÎÎÎÎ
TA = 25°C
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
Figure 32
10
0
f − Frequency − Hz
10 M
100
100 1 k 10 k 100 k 1 M
10
20
30
40
50
60
70
80
90
ÎÎÎÎ
ÎÎÎÎ
TA = 25°C
VCC± = ±15 V
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 33
−75
75
CMRR − Common-Mode Rejection Ratio − dB
TA − Free-Air Temperature − °C
125
95
−50 −25 0 25 50 75 100
80
85
90
VCC± = ±15 V
VCC± = ±5 V
COMMON-MODE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
ÎÎÎÎÎ
VIC = VICRmin
Figure 34
−75
90
− Supply Voltage Rejection Ratio − dB
TA − Free-Air Temperature − °C
125
100
−50 −25 0 25 50 75 100
92
94
96
98
VCC± = ±5 V to ±15 V
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
SVR
k
Figure 35
0
−30
IOS − Short-Circuit Output Current − mA
|VCC±| − Supply Voltage − V
16
30
246 8 10 12 14
−20
−10
0
10
20
VO = 0
TA = 25°C
VID = 100 mV
VID = −100 mV
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
OS
I
Figure 36
0
−20
t − Time − s
30
30
51015 20 25
−10
0
10
20
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VCC± = ±15 V
TA = 25°C
VID = −100 mV
VID = 100 mV
SHORT-CIRCUIT OUTPUT CURRENT
vs
TIME
IOS − Short-Circuit Output Current − mA
ÁÁ
ÁÁ
OS
I
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 37
−75
−25
− Short-Circuit Output Current − mA
TA − Free-Air Temperature − °C
125
25
−50 −25 0 25 50 75 100
−20
−15
−10
−5
0
5
10
15
20
SHORT-CIRCUIT OUTPUT CURRENT†
vs
FREE-AIR TEMPERATURE
OS
I
ÎÎÎÎÎ
ÎÎÎÎÎ
VID = 100 mV
ÎÎÎ
ÎÎÎ
VO = 0
ÎÎÎÎÎÎ
VID = −100 mV
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±5 V
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±15 V
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±15 V
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±5 V
Figure 38
10
40
Vn − Equivalent Input Noise Voltage − nVHz
f − Frequency − Hz
100 k
70
60
50
100 1 k 10 k
ÁÁ
ÁÁ
ÁÁ
ÁÁ
nV/ Hz
Vn
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC± = ±15 V
RS = 20 Ω
TA = 25°C
See Figure 3
TL031 and TL031A
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
Figure 39
10
30
Vn − Equivalent Input Noise Voltage − nVHz
f − Frequency − Hz
100 k
60
50
40
100 1 k 10 k
Vn
ÁÁ
ÁÁ
ÁÁ
nV/ Hz
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC± = ±15 V
RS = 20 Ω
TA = 25°C
See Figure 3
TL032 and TL032A
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
Figure 40
10
40
Vn − Equivalent Input Noise Voltage − nVHz
f − Frequency − Hz
11 k
90
70
50
100 1 k 10 k
Vn
ÁÁ
ÁÁ
ÁÁ
nV/ Hz
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
VCC± = ±15 V
RS = 20 Ω
TA = 25°C
See Figure 3
80
60
TL034 and TL034A
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 41
0
0
|VCC±| − Supply Voltage − V
16
250
2 4 6 8 10 12 14
50
100
150
200
TA = 25°C
TA = 125°C
TA = −55°C
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
VO = 0
No Load
ICC − Supply Current − A
ÁÁ
ÁÁ
CC
IAμ
TL031 and TL031A
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
Figure 42
0
0
ICC − Supply Current −A
|VCC±| − Supply Voltage − V
16
500
246 8 10 12 14
100
200
300
400
TA = 25°C
TA = 125°C
TA = −55°C
ÁÁ
ÁÁ
ÁÁ
CC
IAμ
ÁÁÁ
ÁÁÁ
VO = 0
No Load
TL032 and TL032A
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
Figure 43
0
0
ICC − Supply Current −A
|VCC±| − Supply Voltage − V
16
1000
2 4 6 8 10 12 14
200
400
600
800
TA = 25°C
TA = 125°C
TA = −55°C
ÁÁ
ÁÁ
ÁÁ
CC
IAμ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 0
No Load
TL034 and TL034A
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
Figure 44
−75
0
TA − Free-Air Temperature − °C
125
250
−50 −25 0 25 50 75 100
50
100
150
200
VCC± = ±15 V
VCC± = ±5 V
ÁÁÁ
ÁÁÁ
ÁÁÁ
VO = 0
No Load
ICC − Supply Current − A
ÁÁ
ÁÁ
CC
IAμ
TL031 and TL031A
SUPPLY CURRENT†
vs
FREE-AIR TEMPERATURE
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 45
−75
0
TA − Free-Air Temperature − °C
125
500
−50 −25 0 25 50 75 100
100
200
300
400
VCC± = ±15 V
VCC± = ±5 V
ICC − Supply Current −A
ÁÁ
ÁÁ
CC
IAμ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
VO = 0
No Load
TL032 and TL032A
SUPPLY CURRENT†
vs
FREE-AIR TEMPERATURE
Figure 46
−75
0
TA − Free-Air Temperature − °C
125
1000
−50 −25 02550 75 100
200
400
600
800
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±15 V
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±5 V
ICC − Supply Current −A
ÁÁ
ÁÁ
CC
IAμ
ÎÎÎÎ
ÎÎÎÎ
VO = 0
No Load
TL034 and TL034A
SUPPLY CURRENT†
vs
FREE-AIR TEMPERATURE
Figure 47
1
0
RL − Load Resistance − kΩ
100
6
1
2
3
4
5
10
SR−
SR+
SLEW RATE
vs
LOAD RESISTANCE
SR − Slew Rate − V/s sμ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±5 V
CL = 100 pF
TA = 25°C
See Figure 1
Figure 48
10
5
4
3
2
1
6
100
RL − Load Resistance − kΩ
01
ÎÎ
SR+
ÎÎÎ
SR−
SLEW RATE
vs
LOAD RESISTANCE
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VCC± = ±15 V
CL = 100 pF
TA = 25°C
See Figure 1
SR − Slew Rate − V/s sμ
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 49
−75
0
TA − Free-Air Temperature − °C
125
6
−50 −25 0 25 50 75 100
1
2
3
4
5
SR−
SR+
SLEW RATE†
vs
FREE-AIR TEMPERATURE
SR − Slew Rate − V/s sμ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±5 V
RL = 10 kΩ
CL = 100 pF
See Figure 1
Figure 50
−75
0
TA − Free-Air Temperature − °C
125
6
−50 −25 0 25 50 75 100
1
2
3
4
5
SR−
SR+
SLEW RATE†
vs
FREE-AIR TEMPERATURE
SR − Slew Rate − V/s sμ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VCC± = ±15 V
RL = 10 kΩ
CL = 100 pF
See Figure 1
Figure 51
0
0
Overshoot Factor − %
CL − Load Capacitance − pF
250
60
50 100 150 200
10
20
30
40
50
VI(PP) = ±10 mV
RL = 10 kΩ
TA = 25°C
See Figure 1
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC±= ±5 V
OVERSHOOT FACTOR
vs
LOAD CAPACITANCE
ÎÎÎÎÎÎ
VCC± = ±15 V
Figure 52
100
0.1
THD − Total Harmonic Distortion − %
f − Frequency − Hz
100 k
0.5
0.2
0.3
0.4
1 k 10 k
VCC±= ±15 V
AVD = 1
VO(rms) = 6 V
TA = 25°C
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 53
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
0
0.9
|VCC±|− Supply Voltage − V
16
1.1
246 8 10 12 14
0.95
1.0
1.05
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
VI = 10 mV
RL = 10 kΩ
CL = 25 pF
TA = 25°C
See Figure 4
B1 − Unity-Gain Bandwidth − MHz
B1
Figure 54
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
−75
0.8
TA − Free-Air Temperature − °C
125
1.3
−50 −25 0 25 50 75 100
0.9
1.0
1.1
1.2
VCC+ = ±15 V
VCC± = ±5 V
VI = 10 mV
RL = 10 kΩ
CL = 25 pF
See Figure 4
UNITY-GAIN BANDWIDTH†
vs
FREE-AIR TEMPERATURE
B1 − Unity-Gain Bandwidth − MHz
B1
Figure 55
0
57°
m − Phase Margin
|VCC±| − Supply Voltage − V
16
65°
2 4 6 8 10 12 14
59°
61°
63°
PHASE MARGIN
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
ÁÁ
φm
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VI = 10 mV
RL = 10 kΩ
CL = 25 pF
See Figure 4
m − Phase Margin
ÁÁ
ÁÁ
ÁÁ
φm
TA = 25°C
Figure 56
0
50°
CL − Load Capacitance − pF
100
70°
10 20 30 40 50 60 70 80 90
52°
54°
56°
58°
60°
62°
64°
66°
68°
PHASE MARGIN
vs
LOAD CAPACITANCE
m − Phase Margin
ÁÁ
ÁÁ
φm
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
VI = 10 mV
RL = 10 kΩ
TA = 25°C
See Figure 4
ÎÎÎÎ
ÎÎÎÎ
VCC± = ±5 V
NOTE A: Values of phase margin below a load capacitance of 25 pF
were estimated.
ÎÎÎÎ
ÎÎÎÎ
See Note A
ÎÎÎÎÎ
VCC± = ±15 V
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 57
−75
55°
TA − Free-Air Temperature −°C
125
67°
−50 −25 0 25 50 75 100
57°
59°
61°
63°
65°
VCC± = ±5 V
PHASE MARGIN†
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VI = 10 mV
RL = 10 kΩ
CL = 25 pF
See Figure 4
− Phase Margin
m
φ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC± = ±15 V
Figure 58
−16
VO − Output Voltage − mV
t − Time − μs
1.4
16
0 0.2 0.4 0.6 0.8 1.0 1.2
−12
−8
−4
0
4
8
12
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
ÁÁ
ÁÁ
VO
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC± = ±15 V
RL = 10 kΩ
CL = 100 pF
See Figure 1
TA = 25°C
Figure 59
−2
VO − Output Voltage − V
t − Time − μs
8
2
01234567
0
1
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
ÁÁ
ÁÁ
VO
VCC± = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
−1
Figure 60
t − Time − μs
0
−6
−2
2
4
6
0
−4
8
−8 16141210864218
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
See Figure 1
TA = 25°C
CL = 100 pF
RL = 10 kΩ
VCC±= ±15 V
VO − Output Voltage − V
ÁÁ
ÁÁ
VO
†Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input characteristics
The TL03x and TL03xA are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction.
Due to of the extremely high input impedance and resulting low bias-current requirements, the TL03x and
TL03xA are well suited for low-level signal processing; however, leakage currents on printed circuit boards and
sockets easily can exceed bias-current requirements and cause degradation in system performance. It is a good
practice to include guard rings around inputs (see Figure 61). These guard rings should be driven from a
low-impedance source at the same voltage level as the common-mode input.
Unused amplifiers should be connected as grounded unity-gain followers to avoid oscillation.
(c) UNITY-GAIN AMPLIFIER
(b) INVERTING AMPLIFIER(a) NONINVERTING AMPLIFIER
VO
VI
−
+
VI
VO
VO
VI
−
+
−
+
Figure 61. Use of Guard Rings
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics
All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance.
The TL03x and TL03xA drive higher capacitive loads; however, as the load capacitance increases, the resulting
response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation. The value of
the load capacitance at which oscillation occurs varies with production lots. If an application appears to be
sensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviate
the problem (see Figure 63). Capacitive loads of 1000 pF and larger can be driven if enough resistance is added
in series with the output (see Figure 62).
(a) CL = 100 pF, R = 0 (b) CL = 300 pF, R = 0 (c) CL = 350 pF, R = 0
(d) CL = 1000 pF, R = 0 (e) CL = 1000 pF, R = 50 Ω(f) CL = 1000 pF, R = 2 kΩ
Figure 62. Effect of Capacitive Loads
RVO
10 kΩ
(see Note A)
CL
− 15 V
15 V
−5 V
5 V
−
+
NOTE A: CL includes fixture capacitance.
Figure 63. Test Circuit for Output Characteristics
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
high-Q notch filter
In general, Texas Instruments enhanced-JFET operational amplifiers serve as excellent filters. The circuit in
Figure 64 provides a narrow notch at a specific frequency. Notch filters are designed to eliminate frequencies
that are interfering with the operation of an application. For this filter, the center frequency can be calculated as:
fO+1
2p R1 C1
With the resistors and capacitors shown in Figure 64, the center frequency is 1 kHz. C1 = C3 = C2 + 2 and
R1 = R3 = 2 × R2. The center frequency can be modified by varying these values. When adjusting the center
frequency, ensure that the operational amplifier has sufficient gain at the frequency required.
−
+
0.2
−8
Gain − dB
f − Frequency − kHz
2
2
0.4 0.6 0.8 1 0.2 0.4 0.6 0.8
−7
−6
−5
−4
−3
−2
0
1
R1 R3
1.5 MΩ
C2
220 pF
R3 750 kΩ
C1 C3
110 pF 110 pF
1.5 MΩ
15 V
−15 V
TL03x
VO
VI
−1
Figure 64. High-Q Notch Filter
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
transimpedance amplifier
The low-power precision TL03x allows accurate measurement of low currents. The high input impedance and
low offset voltage of the TL03xA greatly simplify the design of a transimpedance amplifier. At room temperature,
this design achieves 10-bit accuracy with an error of less than 1/2 LSB.
Assuming that R2 is much less than R1 and ignoring error terms, the output voltage can be expressed as:
VO+–IIN RFǒR1 )R2
R2 Ǔ
Using the resistor values shown in the schematic for a 1-nA input current, the output voltage equals −0.1 V. If
the VO limit for the TL03xA is measured at ±12 V, the maximum input current for these resistor values is ±120 nA.
Similarly, one LSB on a 10-bit scale corresponds to 12 mV of output voltage, or 120 pA of input current.
The following equation shows the effect of input offset voltage and input bias current on the output voltage:
VO+–ƪVIO )RFǒIIO )IIBǓƫǒR1 )R2
R2 Ǔ
If the application requires input protection for the transimpedance amplifier, do not use standard PN diodes.
Instead, use low-leakage Siliconix SN4117 JFETs (or equivalent) connected as diodes across the TL03xA
inputs (see Figure 65).
As with all precision applications, special care must be taken to eliminate external sources of leakage and
interference. Other precautions include using high-quality insulation, cleaning insulating surfaces to remove
fluxes and other residue, and enclosing the application within a protective box.
−
+
15 V
−15 V
TL03xA
RF
10 MΩ
90 kΩ
VO
10 kΩR2
SN4117
R1
Input Current
Figure 65. Transimpedance Amplifier
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
4-mA to 20-mA current loops
Often, information from an analog sensor must be sent over a distance to the receiving circuitry. For many
applications, the most feasible method involves converting voltage information to a current before transmission.
The following circuits give two variations of low-power current loops. The circuit in Figure 66 requires three wires
from the transmitting to receiving circuitry, while the second variation in Figure 67 requires only two wires, but
includes an extra integrated circuit. Both circuits benefit from the high input impedance of the TL03xA because
many inexpensive sensors do not have low output impedance.
Assuming that the voltage at the noninverting input of the TL03xA is zero, the following equation determines
the output current:
IO+VIǒR3
R1 RSǓ)5VǒR3
R2 RSǓ+0.16 VI)4mA
The circuits presently provide 4-mA to 20-mA output current for an input voltage of 0 to 100 mV. By modifying
R1, R2, and R3, the input voltage range or the output current range can be adjusted.
Including the offset voltage of the operational amplifier in the above equation clearly illustrates why the low offset
TL03xA was chosen:
IO+VIǒR3
R1 RSǓ)5VǒR3
R2 RSǓ*VIǒR3
R1 RS)R3
R2 RS)R1
RSǓ
+0.16 VI)4mA – 0.17 VI
For example, an offset voltage of 1 mV decreases the output current by 0.17 mA.
Due to the low power consumption of the TL03xA, both circuits have at least 2 mA available to drive the actual
sensor from the 5-V reference node.
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+
R5
3.3 kΩ2N3904
TL03xA
1 MΩR2
R1
5 kΩ
R3 80 kΩ
R4 5 kΩ
VI
Signal Common
1N4148
RS
100 Ω
RL50 Ω
IO
5 V Ref
VCC+ = 10 V
VEE = −5 V
100 kΩ
R7
R6
TL431
100 kΩ
Figure 66. Three-Wire 4-mA to 20-mA Current Loop
100 Ω
−
+
3
2
4
8
5
LTC1044
10 μF
10 μF
R5
3.3 kΩ2N3904
TL03xA
1 MΩR2
R1
5 kΩ
R3 80 kΩ
R4 5 kΩ
VI
Signal Common
1N4148
RS
RL50 Ω
IO
LT1019-5
GND
OUT
IN
5 V Ref
VCC+ = 10 V
Figure 67. Two-Wire 4-mA to 20-mA Current Loop
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
low-level light-detector preamplifier
Applications that need to detect small currents require high input-impedance operational amplifiers; otherwise,
the bias currents of the operational amplifier camouflage the current being monitored. Phototransistors provide
a current that is proportional to the light reaching the transistor. The TL03x allows even the small currents
resulting from low-level light to be detected.
In Figure 68, if there is no light, the phototransistor is off and the output is high. As light is detected, the
operational amplifier output begins pulling low. Adjusting R4 both compensates for offset voltage of the amplifier
and adjusts the point of light detection by the amplifier.
TL03x
−
+
R6
10 kΩ
C1
100 pF
R7
R3
R1
TIL601
R2 5 kΩ
R5
R4
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
15 V
VO
−15 V
Figure 68. Low-Level Light-Detector Preamplifier
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
audio-distribution amplifier
This audio-distribution amplifier (see Figure 69) feeds the input signal to three separate output channels. U1A
amplifies the input signal with a gain of 10, while U1B, U1C, and U1D serve as buffers to the output channels.
The gain response of this circuit is very flat from 20 Hz to 20 kHz. The TL03x allows quick response to the input
signal while maintaining low power consumption.
+
−
VCC+
R4
1 MΩ
C1
1 μF
U1B
R5
10 kΩ
R3
100 kΩ
C2
100 μF
+
−
U1C
+
−
U1D
+
−
U1A
R2
100 kΩ
R1
100 kΩ
VI
VCC+ VOA
VOB
VOC
NOTE A: U1A through U1D = TL03x; VCC+ = 5 V
Figure 69. Audio-Distribution Amplifier Circuit
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
instrumentation amplifier with linear gain adjust
The low offset voltage and low power consumption of the TL03x provide an accurate but inexpensive
instrumentation amplifier (see Figure 70). This particular configuration offers the advantage that the gain can
be linearly set by one resistor:
VO = R6
R5 × (VB − VA)
Adjusting R6 varies the gain. The value of R6 always should be greater than, or equal to, the value of R5 to
ensure stability. The disadvantage of this instrumentation amplifier topology is the high degree of CMRR
degradation resulting from mismatches between R1, R2, R3, and R4. For this reason, these four resistors
should be 0.1%-tolerance resistors.
+
−
U1C
+
−
U1A
R6
1 MΩ
VA
VCC+
VO
+
−
+
−
VB
U1B
R2
10 kΩ
0.1%
R4
10 kΩ
0.1%
R7
100 kΩ
R5
100 kΩ
R1
10 kΩ
0.1%
R3
10 kΩ
0.1%
U1D
VCC−
NOTE A: U1A through U1D = TL03x; VCC± = ±15 V
Figure 70. Instrumentation Amplifier With Linear Gain-Adjust Circuit
PACKAGING INFORMATION
Orderable Device Status (1) Package
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Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-9086102Q2A OBSOLETE LCCC FK 20 TBD Call TI Call TI
TL031ACD OBSOLETE SOIC D 8 TBD Call TI Call TI
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no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL031CDR ACTIVE SOIC D 8 2500 Green (RoHS &
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no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL031CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL031CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL031CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL031CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TL031ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL031IDE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL031IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
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TL031IP ACTIVE PDIP P 8 50 Pb-Free
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TL031IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032ACD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032ACDE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032ACDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032ACDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032ACP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032ACPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
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TL032AID ACTIVE SOIC D 8 75 Green (RoHS &
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TL032AIDE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032AIDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
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TL032AIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CDE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032CPSR ACTIVE SO PS 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CPSRE4 ACTIVE SO PS 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TL032ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032IDE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL032IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
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TL032IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL032MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TL032MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI
TL034ACD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034ACDE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034ACDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034ACDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034ACN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL034ACNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL034AID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034AIDE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034AIDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034AIDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034AIDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034AIN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL034AINE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL034CD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CDE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CN ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
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(RoHS)
TL034CNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL034CNSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CNSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CNSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
TL034CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034IDE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034IDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034IDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL034IN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL034INE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL034MD OBSOLETE SOIC D 14 TBD Call TI Call TI
TL034MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TL034MJB OBSOLETE CDIP J 14 TBD Call TI Call TI
TL034MN OBSOLETE PDIP N 14 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2008
Addendum-Page 4
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2008
Addendum-Page 5
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL031CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL032ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL032AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL032CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL032CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TL032IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL034ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL034AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL034CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL034CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TL034CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TL034IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL031CDR SOIC D 8 2500 340.5 338.1 20.6
TL032ACDR SOIC D 8 2500 340.5 338.1 20.6
TL032AIDR SOIC D 8 2500 340.5 338.1 20.6
TL032CDR SOIC D 8 2500 340.5 338.1 20.6
TL032CPSR SO PS 8 2000 367.0 367.0 38.0
TL032IDR SOIC D 8 2500 340.5 338.1 20.6
TL034ACDR SOIC D 14 2500 367.0 367.0 38.0
TL034AIDR SOIC D 14 2500 367.0 367.0 38.0
TL034CDR SOIC D 14 2500 367.0 367.0 38.0
TL034CNSR SO NS 14 2000 367.0 367.0 38.0
TL034CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TL034IDR SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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