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XE8801A – SX8801R Sensing Machine
Data Acquisition with ZoomingADC™
XE8801A – SX8801R
Sensing Machine
Data Acquisition with 16+10 bit ZoomingADC™
General Description
The XE8801A is a data acquisition ultra low-
power, low-voltage, system on a chip (SoC) with a
high efficiency embedded microcontroller unit
(MCU), allowing for 1 MIPS at 300uA and 2.4 V,
and multiplying in one clock cycle.
The XE8801A includes a high resolution
acquisition path with16+10 bits.
The XE8801A is available with on chip ROM (this
is called the SX8801R) or Multiple-Time-Program-
mable (MTP) program memory.
Applications
• Portable, battery operated instruments
• Current loop powered instruments
• Wheatstone bridge interfaces
• Pressure and chemical sensors
• HVAC control
• Metering
•Sports watches, wrist instruments
Key product Features
• Low-power, high resolution ZoomingADC
• 0.5 to 1000 gain with offset cancellation
• up to 16 bits analog to digital converter
• up to 13 inputs multiplexer
• Low-voltage low-power controller operation
• 2 MIPS with 2.4 V to 5.5 V operation
• 300 µA at 1 MIPS over voltage range
• 22 kByte (8 kInstruction) MTP or ROM
• 520 Byte RAM data memory
• RC and crystal oscillators
• 5 reset, 22 interrupt, 8 event sources
• 100 years MTP Flash retention at 55°C
Ordering Information
Item number*
XE8801AMI027LF -40°C to 85 °C MTP LQFP44
SX8801RIxxx -40°C to 85 °C ROM die
SX8801IRxxLFTRT -40°C to 85 °C* ROM LQFP44
SX8801IRxxMLTRT -40°C to 85 °C ROM MLPQ44
*xx will be replaced by ROM identifier
**MTP parts are conditioned in trays; ROM parts are conditioned in reels
The XE8801A was previously called, and is the same as the XE8801LC01A.
Temperature
range
Memory
type Package
**
Not Recommended for
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XE8801A – SX8 801R Sensing Machine
Data Acquisition with ZoomingADC™
TABLE OF CONTENTS
Chapter 1 XE8801AM - SX8801R Overview
Chapter 2 XE8801AM - SX8801R Perf ormance
Chapter 3 XE8801AM - SX8801R CPU
Chapter 4 XE8801AM - SX8801R Memory
Chapter 5 System Block
Chapter 6 Reset genera tor
Chapter 7 Clock generation
Chapter 8 Interrupt han dler
Chapter 9 Event handler
Chapter 10 Low power RAM
Chapter 11 Port A
Chapter 12 Port B
Chapter 13 Port C
Chapter 14 Universal Asynchronous Receiver/Transmitter (UART)
Chapter 15 Universal Synchronous Receiver/Transmitter (USRT)
Chapter 16 Acquisition Chain
Chapter 17 Voltage multiplier
Chapter 18 Counters/Timers/PWM
Chapter 19 The Voltage Level Detector
Chapter 20 XE8801AM - SX8801R Dimensions
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1-1
XE8801A – SX8801R
1. General Overview
CONTENTS
1.1 Top schematic 1-2
1.1.1 General description 1-2
1.1.2 XE88LC01 vs XE8 8LC01A vs XE88 01 A vs SX8801R 1-4
1.2 Pin map 1-4
1.2.1 Bare die of XE8801AM 1-4
1.2.2 Bare die of SX880 1R 1-5
1.2.3 LQFP-44 package 1-6
1.3 Pin assignment 1-7
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1-2
XE8801A – SX8801R
1.1 Top schematic
1.1.1 General description
The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the
Coolrisc81 6® CPU core. This core incl udes an 8x8 multiplier and 16 internal registers.
The bus controller generates all control signals for access to all data registers other than the CPU internal
registers.
The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained
in its control registers. Possible reset sources are the power-on-reset (POR), the external pin RESET, the
watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low
power modes are implemented.
The clock generation and power management block sets up the clock signals and generates internal supplies for
different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal
oscillator (XTAL) or an external clock source (given on the OSCIN pin).
The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8
low power data registers. If power consumption is important for the application, the variables that need to be
accessed very oft e n should be stored in these registers rather than in th e RAM.
The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows
masking of the int err upt sources and it fla gs which in te rru pt source is active.
Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e.
the program execution resumes with the instruction following the HALT instruction. The EVN handler routes the
event signals of the different peripherals to the EVN inputs of the CPU core. It allows masking of the interrupt
sources and it flags wh ich int er rup t sou rce is active.
The Port B is an 8 bit parallel IO port with analog capabilities. The URST, UART, and PWM block also make use of
this port.
The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. Flash and ROM
versions have both 8k instruction memory.
The data memory on t his pro du ct is a 51 2 by te SRAM.
The Acquisition Chain is a high resolution acquisition path with the 16+10 bits ZoomingADC™. The VMULT
(voltage mult ip lier ) pow ers a pa rt of the Acquisition C hain.
Port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input
external clocks fo r th e timer/counter/PWM block.
Port C is a general pu rpo se 8 bit parallel I /O por t.
The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to
simplify th e sof t wa re implementation of a synchronous seri al link.
The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the
asynchronous seri al lin k.
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1-3
XE8801A – SX8801R
The counters/timers/PWM can take its clocks from internal or external sources (on Port A) and can generate
interrupts or events. The PWM is ou tp ut on Port B.
The VLD (voltage level detector) de te cts the battery end of li fe with respe ct to a programmable th resh old .
INSTRUCTION M EM O RY
B
U
S
C
O
N
T
R
O
L
L
E
R
TEST CONTROLLER
RESET BLOCK
WD
CLOCK
GENERATION/
POWER
MANAGEMENT
VREG
XTAL
RC
CPU
COOLRISC816
8X8 M ULTIPLIER
16 CPU REGISTERS
IRQ HANDLING
EVN HANDLING
PORT B
8 DATA REGISTERS
PORT A
USRT
PORT C
address
control
da ta in
dataout
rese t
control
clocks
test
control
irq
evn
VPP/TEST
VBAT
VSS
RESET
OSCIN
OSCOUT
VREG
PB(7:0)
PA (7:0)
PC (7:0)
A C _R (3 :0 )
AC _ A(7:0)
VMULT
DATA
MEMORY
UART
COUNTERS
TIMERS
PWM
VLD
PB(5:4) PB(7:6) PA(3:0) PB(1:0)
POR
AC Q U ISITIO N
CHAIN
ZoomingADC
VMULT
Figure 1-1. Bloc k sc hematic of the XE8801A circuit.
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1-4
XE8801A – SX8801R
1.1.2 XE88LC01 vs XE88LC01A vs XE880 1A vs SX880 1R
The XE88LC01 was the first version of this chip that was launched in 1999. It is not sold anymore. The
XE88LC01A has a new RESET pin function. The action of the RESET pin of the XE88LC01A resets the clock
registers too and creates an addit i o nal short delay. See the RES ET chap ter for more info rmat ion.
The XE8801A is the same product as the XE88LC01A. Its name was modified when XEMICS was bought by
Semtech mid -2005. The SX8801R is the ROM version of the XE8801A.
1.2 Pin map
1.2.1 Bare die of XE8801AM
(52.6,4075.5) PA(4)
(52.6, 3795.5) PA(5)
(52.6,3515.5) VBAT
(52.6, 3235.5) PA(6)
(52.6, 2955.5) PA(7)
(52.6, 2675.5) PC(0)
(52.6, 2395.5) PC(1)
(52.6, 2115.5) PC(2)
(52.6, 1835.5) PC(3)
(52.6, 1555.5) VSS
(52.6, 1275.5) PC(4)
(52.6, 995.5) PC(5)
(52.6, 715.5) PC(6)
(52.6, 435.5) PC(7)
VSS (3958.4, 3942.4)
AC_R(0) (3958.4, 3657.4)
AC_R(1) (3958.4, 3372.4)
AC_A(0) (3958.4, 3087.4)
AC_A(1) (3958.4, 2802.4)
VSS (3958.4, 2517.4)
AC_A(2) (3958.4, 2232.4)
AC_A(3) (3958.4, 1947.4)
AC_A(4) (3958.4,1662.4)
AC_A(5) (3958.4, 1377.4)
AC_A(6) (3958.4, 1092.4)
VBAT (3958.4, 807.4)
AC_A(7) (3958.4, 522.4)
PA(3) ( 417.6, 4453.4)
PA(2) ( 682.6, 4453.4)
PA(1) ( 947.6, 4453.4)
PA(0) (1212.6, 4453.4)
OSCOUT (1477.6, 4453.4)
VSS (1742.6, 4453.4)
OSCIN (2007.6, 4453.4)
VMULT (2537.0, 4453.4)
RESET (2802.6, 4453.4)
VREG (3067.6, 4453.4)
VSS (3332.6, 4453.4)
VBAT (3597.6, 4453.4)
( 398.5, 47.6) PB(0)
( 533.5, 47.6) PB(1)
( 668.5, 47.6) PB(2)
( 798.5, 47.6) PB(3)
( 933.5, 47.6) PB(4)
(1063.5, 47.6) VBAT
(1198.5, 47.6) PB(5)
(1328.5, 47.6) PB(6)
(1463.5, 47.6) PB(7)
(1934.1, 47.6) TEST
(2394.1, 47.6) VSS
(2854.1, 47.6) AC_R(3)
(3314.1, 47.6) AC_R(2)
4100
4600
Figure 1-2. Die dimensions and pin coordinates (in µm).
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1-5
XE8801A – SX8801R
1.2.2 Bare die of SX8801R
Figure 1-3. Die dimensions and pin coordinates (in µm).
(447.4, 118) PB(1)
(724.4, 118) PB(2)
(1001.4, 118) PB(3)
(1278.4, 118) PB(4)
(1513.6, 118) VBAT
(1790.6, 118) PB(5)
(2067.6, 118) PB(6)
(2344.6, 118) PB(7)
(2735.8, 118) TEST
(2971.0, 118) VSS
(3155.6, 118) AC_R(3)
4131
3441
PA(4) (285.3, 4013)
PA(3) (470.0, 4013)
PA(2) (704.6, 4013)
PA(1) (939.2, 4013)
PA(0) 1173.8, 4013)
OSCOUT (1403.4, 4013)
VSS (1638.0, 4013)
OSCIN (1923.2, 4013)
VMULT (2157.8, 4013)
RESET (2352.8, 4013)
VREG (2537.4, 4013)
VSS (2772.0, 4013)
VBAT (3032.2, 4013)
(118, 3776.0) PA(5)
(118, 3490.8) VBAT
(118, 3256.2) PA(6)
(118, 3033.0) PA(7)
(118, 2710.9) PC(0)
(118, 2438.9) PC(1)
(118, 2166.8) PC(2)
(118, 1894.8) PC(3)
(118, 1659.6) VSS
(118, 1387.5) PC(4)
(118, 1115.5) PC(5)
(118, 843.5) PC(6)
(118, 571.4) PC(7)
(118, 285.4) PB(0)
VSS (3323, 3760.6)
AC_R(0) (3323, 3475.4)
AC_R(1) (3323, 3240.8)
AC_A(0) (3323, 3006.2)
AC_A(1) (3323, 2771.6)
VSS (3323, 2487.0)
AC_A(2) (3323, 2151.8)
AC_A(3) (3323, 1867.2)
AC_A(4) (3323, 1578.6)
AC_A(5) (3323, 1344.0)
AC_A(6) (3323, 1109.4)
VBAT (3323, 874.8)
AC_A(7) (3323, 589.6)
AC_R(2) (3323, 355.0)
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1-6
XE8801A – SX8801R
1.2.3 LQFP-44 and MLPQ-44 pin-out
Figure 1-4. LQFP-44 or MLPQ-44 pin map, top view
The XE8801A is delivered in a LQFP-44 package; the SX8801R can be delivered in LQFP-44 or MLPQ-44
package. The pin map is given below.
Package
Pin name
Package
Pin name
1
PA(5)
23
AC_A(7)
2
PA(6)
24
AC_A(6)
3
PA(7)
25
AC_A(5)
4
PC(0)
26
AC_A(4)
5
PC(1)
27
AC_A(3)
6
PC(2)
28
AC_A(2)
7
PC(3)
29
AC_A(1)
8
PC(4)
30
AC_A(0)
9
PC(5)
31
AC_R(1)
10
PC(6)
32
AC_R(0)
11
PC(7)
33
VSS
12
PB(0)
34
VBAT
13
PB(1)
35
VREG
14
PB(2)
36
RESET
15
PB(3)
37
VMULT
16
PB(4)
38
OSCIN
17
PB(5)
39
OSCOUT
18
PB(6)
40
PA(0)
19
PB(7)
41
PA(1)
20
VPP/TEST
42
PA(2)
21
AC_R(3)
43
PA(3)
22
AC_R(2)
44
PA(4)
Table 1-1. Bonding plan of the LQFP-44 and MLPQ-44 packages
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1-7
XE8801A – SX8801R
1.3 Pin assignment
The table below gives a short de scri pt ion of the diff ere nt pi n a ssi gnme nts.
Pin Assignment
VBAT Positive power supply
VSS Negative power supply
VREG Connection for the mandatory external capacit or of the voltage regulator
VPP/TEST High voltage supply for flash memory programming (NC in ROM versions)
RESET Resets the circuit when the voltage is high
OSCIN/OSCOUT Quartz crystal connections, also us ed for f lash mem ory programming
PA(7:0) Parallel input port A pins
PB(7:0) Parallel I/O port B pins
PC(7:0) Parallel I/O port C pins
AC_A(7:0) Acquisition chain input pins
AC_R(3:0) Acquisition chain referen ce pins
VMULT Connection for the external capacitor if VBAT is below 3V
Table 1-2. Pin assignment
Table 1-3 gives a more detailed pin map for the different pins. It also indicates the possible I/O configuration of
these pins. The indications in blue bold are the configuration at start-up. The pins CNTx pins are possible counter
inputs, PWM x ar e possible PWM output s.
pin function I/O configuration
lqfp-44
first
second
third
AI
AO
DI
DO
OD
PU
POWER
1 PA(5)
X X
2 PA(6)
X X
3 PA(7)
X X
4 PC(0) X
X
5 PC(1) X
X
6 PC(2) X
X
7 PC(3) X
X
8 PC(4) X
X
9 PC(5) X
X
10 PC(6) X
X
11 PC(7) X
X
12 PB(0) PWM0 X X
X X X X
13 PB(1) PWM1 X X
X X X X
14 PB(2) X X
X X X X
15 PB(3) X X
X X X X
16 PB(4) USRT_S0 X X
X X X X
17 PB(5) USRT_S1 X X
X X X X
18 PB(6) UART_Tx X X
X X X X
19 PB(7) UART_Rx X X
X X X X
20 VPP TEST
X
21 AC_R(3) X
22 AC_R(2) X
23 AC_A(7) X
24 AC_A(6) X
25 AC_A(5) X
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XE8801A – SX8801R
26 AC_A(4) X
27 AC_A(3) X
28 AC_A(2) X
29 AC_A(1) X
30 AC_A(0) X
31 AC_R(1) X
32 AC_R(0) X
33 VSS
X
34 VBAT
X
35 VREG
X
36 RESET
X
37 VMULT
X
38 OSCIN X
39 OSCOUT
X
40 PA(0) CNTA
X X
41 PA(1) CNTB
X X
42 PA(2) CNTC
X X
43 PA(3) CNTD
X X
44 PA(4)
X X
Pin map table legend:
blue bold: configuration at start up
AI: analog input
AO: analog output
DI: digital input
DO: digital output
OD: nMOS open drain output
PU: pull-up resistor
POWER: power supply
Table 1-3. Pin description table
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2-1
XE8801A – SX8801R
2 XE88LC01A – SX8801R Operation and Performances
2.1 Absolute maximum ratings 2-2
2.2 Operating range 2-2
2.3 Supply configurations 2-3
2.3.1 Flash circuit 2-3
2.3.2 ROM circuit 2-3
2.4 Current consumption 2-5
2.5 Operating speed 2-6
2.5.1 Flash version 2-6
2.5.2 ROM circuit version 2-6
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2-2
XE8801A – SX8801R
2.1 Absolute ma xi mum ratings
Table 2-1. Absolute maximal ratings
Min. Max. Note
Voltage applied to VBAT with re spect to VSS -0.3 6.0 V
Voltage applied to VP P wit h respect to VSS VBAT-0.3 12 V
Voltage applied to all pins except VPP and V BAT VSS-0.3 VBAT+0.3 V
Storage temperature (ROM device or unprogrammed
flash device ) -55 150 °C
Storage t emp erature (progra mme d flash device) -40 85 °C
Stresses beyond the absolute maximal ratings may cause permanent damage to the device. Functional operation
at the absolute maximal ratings is not implied. Exposure to conditions beyond the absolute maximal ratings may
affect the reliability of the device.
2.2 Operating range
Table 2-2. Opera ting range for the XE8801AM device
Min. Max. Note
Voltage applied to VBAT with re spect to VSS 2.4 5.5 V
Voltage applied to VBAT with respect to VSS during
the flash programming 3.3 5.5 V 1
Voltage applied to VPP with respect to VSS VBAT 11.5 V
Voltage applied to all pins except VPP and VBAT VSS VBAT V
Operating t emperature rang e -40 85 °C
Capacitor on VREG (flash version) 0.8 1.2 µF 2
Capacitor on VMULT 1.0 3.0 nF 3
1. During the programming of the device, the supply voltage should at least be equal to the supply voltage
used during normal operation.
2. The capacitor on VREG is mandatory.
3. The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The
multiplier has to be ena ble d if VBAT<3.0V .
Table 2-3. Operating range for the SX8801R device
Min. Max. Note
Voltage applied to VBAT with re spect to VSS 2.4 5.5 V
Voltage applied to all pins except VBA T VSS VBAT V
Voltage applied to VPP VSS VBAT V 3
Operating t emperature rang e -40 85 °C
Capacitor on VREG 0.1 1.2 µF 1
Capacitor on VMULT 1.0 3.0 nF 2
1. The capacitor may be omit ted when VREG is conne cte d t o VBAT.
2. The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The
multiplier has to be ena ble d if VBAT<3.0V .
3. VPP should be left open, conne ct e d to VB AT through a resistor o r conn ected directly to VBAT.
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XE8801A – SX8801R
All specificati ons in this document are valid for the complete op era tin g ra nge unless otherwise specified.
Table 2-4. Operat ing ran ge of the Flash memory
Min. Typ. Note
Retention time at 85°C 10 years 1
Retention time at 55°C 100 ye ars 1
Number of progra mmin g cycles for production 10
Number of progra mmin g cycles for development 200 2
1. Valid only if progra mmed using a pro gra mmin g to ol that is qualified
2. Circuits can be programmed more than 10 times but in that case the retention time is no longer
guaranteed.
2.3 Supply configurations
2.3.1 Flash circuit
The flash version of the circuit can be run from a supply between 2.4V and 5.5V (Figure 2-1). The capacitor on
VREG has to be connected at all times (value in Table 2-2) to guarantee proper operation of the device. The
capacitor on V M ULT is only required if t he circuit is to be operate d be low 3V.
VBAT
VREG
VMULT
VSS
2.4V – 5.5V
Cvreg
Cvmult
Figure 2-1. Supp ly configuration for the fl a sh circuit.
2.3.2 ROM circuit
For the ROM version, two possible operating modes exist: with and without voltage regulator. Using the voltage
regulator, low power consumption will be obtained even with supply voltages above 2.4V. Without the voltage
regulator (i.e. VREG short- circuit ed to VBAT), a higher speed can b e ob ta ined.
2.1.3. 1 Low power operation
In this case, the internal voltage regulator is used in order to maintain a low power consumption independent from
the supply voltage. The capacitor on VREG has to be connected at all times (value in Table 2-3) to guarantee
proper operat ion of the device. The capacitor on V MULT has to be conne cted only when V BAT<3V.
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2-4
XE8801A – SX8801R
VBAT
VREG
VMULT
VSS
2.4V – 5.5V
Cvreg
Cvmult
Figure 2-2. Supp ly voltage conn ections for low po wer o peration of the ROM v ersion.
2.1.3. 2 High speed operat ion
In this case, the internal voltage regulator is not used. The operation speed of the circuit can be increased with
increasing supply voltage but the supply current will also increase. The capacitor on VMULT has to be connected
only when VBAT<3V. In this case, the supply voltage can decrease down to 2.15V. Beware however that the
ZoomingADCTM will not run below 2.4V (see Figure 2-4). In this configuration, the circuit can not be used above
3.3V.
VBAT
VREG
VMULT
VSS
2.15V – 3.3V
Cvmult
Figure 2-3. Supp ly voltage conn ections for high spee d operation of the ROM version.
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2-5
XE8801A – SX8801R
0 2.15 2.4 3.3 VBAT (V)
CPU
parallel and serial ports
RC and cr ystal osc illator
VLD
Counters and PWM
acquisi tion chain
voltage mu ltiplie r
Figure 2-4. Operation ran ge of t he different circuit blocks
2.4 Current consumption
The tables below give the current consumption for the circuit in different configurations. The figures are indicative
only and may cha nge as a fu nction of the act ual software impl eme nt ed in th e circuit.
Table 2-5 gives the current consumption for the flash version of the circuit. The peripherals are disabled. The
parallel ports A and B are configured in input with pull up, the parallel port C is configured as an output. Their pins
are not connected externally. The pin RESET is connected to VSS and the pin VPP/TEST is connected to VBAT.
he inputs of the acquisition chain are connected to VSS.
Table 2-5. Typical curre nt consu mption of the XE8 80 1AM version
Operation mode CPU RC Xtal Consumption comments Note
High speed CPU 1 MIPS 1 MHz Off 310 µA 2.4V<>5.5V, 27°C
Low power CPU 32 kIPS Off 32 kHz 10 µA 2.4V <>5.5V, 27°C
Low power time
keeping HALT Off 32 kHz 1.0 µA 2.4V <>5.5V, 27°C
Fast wake-up
time keeping HALT Ready 32kHz 1.7 µA 2.4V <>5.5V, 27°C
Immediate wake-
up time keeping HALT 100 kHz Off 1.4 µA 2.4V <>5.5V, 27°C
VLD static curre nt 15 µA 2.4V <>5.5V, 27°C
16 bit resolution
data acquisition HALT 2 MHz Off 190 µA 3.0V, 27°C 1
12 bit , gain 100,
data acquisition HALT 2 MHz Off 460 µA 3.0V, 27°C 2
1. PGA disabled, ADC enabled, 16 bit resolution
2. PGA 1 disabled, PGA 2 and 3 enabled, ADC enabled, 12 bit resolution
For more information concerning the current consumption of the ZoomingADCTM, see the power consumption
section in the acquisition chain chapter of this document, which shows the current consumption of this block as a
function of temperature and voltage and for different configurations of the PGA and ADC.
The power consumption of the ROM version of the circuit is identical if it is configured as shown in Figure 2-2. In
the high speed configuration, the current consumption will increase proportional with VBAT.
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2-6
XE8801A – SX8801R
2.5 Operating speed
2.5.1 Flash version
The speed of the devices is not highly dependent upon the supply voltage. However, by limiting the temperature
range, the speed can be increased. The minimal guaranteed speed as a function of the supply voltage and
maximal temperature operatin g temperature is given in Fig ure 2-5.
0
1
2
3
4
2 2.5 3 3.5 4 4.5 5 5.5
supply voltage VBAT (V)
speed (MIPS)
85°C 45°C
Figure 2-5. Guaran te ed spee d as a fu nction of the supp ly voltage and max ima l t em perature.
2.5.2 ROM circuit version
2.1.5. 1 Low power supply conf ig uration
In the low power supply configuration as shown in Figure 2-2, the operating speed does not depend highly on the
supply voltage as shown in Figure 2-6.
0
0.5
1
1.5
2
2.5
3
3.5
22.533.544.555.5
supply vol tage V BAT (V)
speed (MIPS)
85°C 45°C 125°C
Figure 2-6. Guaranteed speed as a function of supply voltage and for different maximal temperatures using the
voltage regulator.
2.1.5. 2 High speed supply con fig ur ation
In the high speed supply config uration of Figu re 2-3, the guarantee d spe ed of the circuit is shown in Figur e 2-7 .
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2-7
XE8801A – SX8801R
0
1
2
3
4
2 2.2 2.4 2.6 2.8 3 3.2 3.4
supply voltage VBAT (V)
speed (MIPS)
85°C 45°C 125°C
Figure 2-7. Guaranteed speed as a function of supply voltage and for three temperature ranges when
VREG=VBAT.
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3-1
XE8801A – SX8801R
3. CPU
CONTENTS
3.1 CPU description 3-2
3.2 CPU internal registers 3-2
3.3 CPU instruction short reference 3-4
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XE8801A – SX8801R
3.1 CPU description
The CPU of the XE8000 series is a low power RISC core. It has 16 internal registers for efficient implementation of
the C compiler. Its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing
modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. The
circuit therefo re ru ns on 1 MIPS on a 1MHz clock.
The CPU hardware and software description is given in the document “Coolrisc816 Hardware and Software
Reference Manual”. A short summary is giv en in the following pa ragraphs.
The good code efficiency of the CPU core makes it possible to compute a polynomial like
YBBXYAAZ ⋅++⋅⋅+= 1010 )( in less than 300 clock cycles (software code generated by the XEMICS C-
compiler, all numbers are signed integers on 16 bits).
3.2 CPU internal registers
As shown in Figure 3-1, the CPU has 16 internal 8-bit registers. Some of these registers can be concatenated to a
16-bit word for use in some instructions. The function of these registers is defined in Table 3-1. The status register
stat (Table 3-2) is used to manage the different interrupt and event levels. An interrupt or an event can both be
used to wake up after a HALT instruction. The difference is that an interrupt jumps to a special interrupt function
whereas an event con tin ue s t he sof twa re e xe cution with the inst ru ctio n following the HALT instr uct ion.
The program counter (PC) is a 16 bit register that indicates the address of the instruction that has to be executed.
The stack (STn) is used to memorise the ret ur n add re ss when e xe cuting subroutines or in te rrupt routines.
Instruction
memory
22bit
CPU
CPU internal r egisters
a
stat
iph ipl
i3h i3l
i2h i2l
i1h i1l
i0h i0l
r3
r2
r1
r0
Data memory
data bus
instruction bus
PC
ST1
ST2
ST3
ST4
program counter stack
Figure 3-1. CPU i nt ern al re gisters
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3-3
XE8801A – SX8801R
Register name Register funct i on
r0 general purpose
r1 general purpose
r2 general purpose
r3 data memory offset
i0h MSB of the data memory index i0
i0l LBS of the data memor y index i0
i1h MSB of the data memory index i1
i1l LBS of the data memor y index i1
i2h MSB of the data memory index i2
i2l LBS of the data memor y index i2
i3h MSB of the data memory index i3
i3l LBS of the data memor y index i3
iph MSB of the program memory index ip
ipl LBS of the progra m memo ry index ip
stat status register
a accumulator
Table 3-1. CPU interna l reg ister definiti o n
bit name function
7 IE2 enables (when 1) the interrupt request of level 2
6 IE1 enables (when 1) the interrupt request of level 1
5 GIE enables (when 1) all interrupt req ue st le ve ls
4 IN2 interrupt request of level 2. The interrupts labelled “low” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
3 IN1 interrupt request of level 1. The interrupts labelled “mid” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
2 IN0 interrupt request of level 0. The interrupts labelled “hig” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
1 EV1 event request of level 1. The events labelled “low” in the event handler are routed to
this event lev el. This bit has to be cleared when the ev e nt is served.
0 EV0 event request of level 1. The events labelled “hig” in the event handler are routed to
this event lev el. This bit has to be cleared when the ev e nt is served.
Table 3-2. Stat u s regist er descrip tion
The CPU also has a number of flags that can be used fo r con dit ional jumps. These fla gs are def ine d in Table 3-3.
symbol name function
Z zero Z=1 when the accumulator a content is zero
C carry This flag is used in shift or arithmetic operations.
For a shift operation, it has the value of the bit that was shifted out (LSB for shift
right, MSB for shift left).
For an arithmetic op era tion with unsigned number s:
it is 1 at occurrence of an overf l ow du ring an additi on (o r equivalent ).
it is 0 at occurrence of an underf low du rin g a subtraction (or eq uivalent).
V overfl ow This flag is used in shift or arithmeti c operations.
For arithmetic or shift operations with signed numbers, it is 1 if an overflow or
underflow occurs.
Table 3-3. Flag description
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XE8801A – SX8801R
3.3 CPU instruction short reference
Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The notation cc in the
conditional jump instruction refers to the condition description as given in Table 3-6. The notation reg, reg1, reg2,
reg3 refers to one of the CPU internal registers of Table 3-1. The notation eaddr and DM(eaddr) refer to one of the
extended address modes as defined in Table 3-5. The notation DM(xxx) refers to the data memory location with
address xxx.
Instruction Modification Operation
Jump addr[15:0] -,-,-, - PC := addr[15:0]
Jump ip -,-,-, - PC := ip
Jcc addr[15:0] -,-,-, - if cc is true then PC := addr[15:0]
Jcc ip -,-,-, - if cc is true then PC := ip
Call addr[15:0] -,-,-, - STn+1 := STn (n>1); ST1 := PC+1; PC := addr[15:0]
Call ip -,-,-, - STn+1 := STn (n>1); ST1 := PC+1; PC := ip
Calls addr[15:0] -,-,-, - ip := PC+1; PC := addr[15:0]
Calls ip -,-,-, - ip := PC+1; PC := ip
Ret -,-,-, - PC := ST1; STn := STn+1 (n>1)
Rets -,-, -, - PC := ip
Reti -,-,-, - PC := ST1; STn := STn+1 (n>1); GIE :=1
Push -,-,-, - PC := PC+1; STn+1 := STn (n>1); ST1 := ip
Pop -,-,-, - PC := PC+1; ip := ST1; STn := STn+1 (n>1)
Move reg,#data[7:0] -,-, Z, a a := data[7:0]; reg := data[7:0]
Move reg1, reg2 -,-, Z, a a := reg2; reg1 := reg2
Move reg, eaddr -,-, Z, a a := DM(eaddr); reg := DM(eaddr)
Move eaddr, reg -,-,-, - DM(eaddr) := reg
Move addr[7:0],#data[7:0] -,-,-, - DM(addr[7:0]) := data[7:0]
Cmvd reg1, reg2 -,-, Z, a a := reg2; if C=0 then reg1 := a;
Cmvd reg, eaddr -,-, Z, a a := DM(eaddr); if C=0 then reg := a
Cmvs reg1, reg2 -,-, Z, a a := reg2; if C=1 then reg1 := a;
Cmvs reg, eaddr -,-, Z, a a := DM(eaddr); if C=1 then reg := a
Shl reg1, reg2 C, V, Z, a a := reg2<<1; a[0] := 0; C := reg2[7]; reg1 := a
Shl reg C, V, Z, a a := reg<<1; a[0] := 0; C := reg[7]; reg := a
Shl reg, eaddr C, V, Z, a a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]; reg := a
Shlc reg1, reg2 C, V, Z, a a := reg2<<1; a[0] := C; C := reg2[7]; reg1 := a
Shlc reg C, V, Z, a a := reg<<1; a[0] := C; C := reg[7]; reg := a
Shlc reg, eaddr C, V, Z, a a := DM(eaddr)<<1; a[0] := C; C := DM(eaddr)[7]; reg := a
Shr reg1, reg2 C, V, Z, a a := reg2>>1; a[7] := 0; C := reg2[0]; reg1 :=a
Shr reg C, V, Z, a a := reg>>1; a[7] := 0; C := reg[0]; reg := a
Shr reg, eaddr C, V, Z, a a := DM(eaddr)>>1; a[7] := 0; C := DM(eaddr)[0]; reg := a
Shrc reg1, reg2 C, V, Z, a a := reg2>>1; a[7] := C; C := reg2[0]; reg1 := a
Shrc reg C, V, Z, a a := reg>> 1; a[7] := C; C := reg[0]; reg := a
Shrc reg, eaddr C, V, Z, a a := DM(eaddr)>>1; a[7] := C; C := DM(eaddr)[0]; reg := a
Shra reg1, reg2 C, V, Z, a a := reg2>>1; a[7] := reg2[7]; C := reg2[0]; reg1 := a
Shra reg C, V, Z, a a := reg>>1; a[7] := reg[7]; C := reg[0]; reg := a
Shra reg, eaddr C, V, Z, a a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0]; reg := a
Cpl1 reg1, reg2 -,-, Z, a a := NOT(reg2); reg1 := a
Cpl1 reg -,-, Z, a a := NOT(reg); reg := a
Cpl1 reg, eaddr -,-, Z, a a := NOT(DM(eaddr)); reg := a
Cpl2 reg1, reg2 C, V, Z, a a := NOT(reg2)+1; if a=0 then C:=1 else C := 0; reg1 := a
Cpl2 reg C, V, Z, a a := NOT(reg)+1; if a=0 then C:=1 else C := 0; reg := a
Cpl2 reg, eaddr C, V, Z, a a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0; reg := a
Cpl2c reg1, reg2 C, V, Z, a a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0; reg1 := a
Cpl2c reg C, V, Z, a a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
Cpl2c reg, eaddr C, V, Z, a a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
Inc reg1, reg2 C, V, Z, a a := reg2+1; if a=0 then C := 1 else C := 0; reg1 := a
Inc reg C, V, Z, a a := reg+1; if a=0 then C := 1 else C := 0; reg := a
Inc reg, eaddr C, V, Z, a a := DM(eaadr)+1; if a=0 then C := 1 else C := 0; reg := a
Incc reg1, reg2 C, V, Z, a a := reg2+C; if a=0 and C=1 then C := 1 else C := 0; reg1 := a
Incc reg C, V, Z, a a := reg+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
Incc reg, eaddr C, V, Z, a a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
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XE8801A – SX8801R
Dec reg1, reg2 C, V, Z, a a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a
Dec reg C, V, Z, a a := reg-1; if a=hFF then C := 0 else C := 1; reg := a
Dec reg, eaddr C, V, Z, a a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1; reg := a
Decc reg1, reg2 C, V, Z, a a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg1 := a
Decc reg C, V, Z, a a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
Decc reg, eaddr C, V, Z, a a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
And reg,#data[7:0] -,-, Z, a a := reg and data[7:0]; reg := a
And reg1, reg2, reg3 -,-, Z, a a := reg2 and reg3; reg1 := a
And reg1, reg2 -,-, Z, a a := reg1 and reg2; reg1 := a
And reg, eaddr -,-, Z, a a := reg and DM(eaddr); reg := a
Or reg,#data[7:0] -,-, Z, a a := reg or data[7:0]; reg := a
Or reg1, reg2, reg3 -,-, Z, a a := reg2 or reg3; reg1 := a
Or reg1, reg2 -,-, Z, a a := reg1 or reg2; reg1 := a
Or reg, eaddr -,-, Z, a a := reg or DM(eaddr); reg := a
Xor reg,#data[7:0] -,-, Z, a a := reg xor data[7:0]; reg := a
Xor reg1, reg2, reg3 -,-, Z, a a := reg2 xor reg3; reg1 := a
Xor reg1, reg2 -,-, Z, a a := reg1 xor reg2; reg1 := a
Xor reg, eaddr -,-, Z, a a := reg or DM(eaddr); reg := a
Add reg,#data[7:0] C, V, Z, a a := reg+data[7:0]; if overflow then C:=1 else C := 0; reg := a
Add reg1, reg2, reg3 C, V, Z, a a := reg2+reg3; if overflow then C:=1 else C := 0; reg1 := a
Add reg1, reg2 C, V, Z, a a := reg1+reg2; if overflow then C:=1 else C := 0; reg1 := a
Add reg, eaddr C, V, Z, a a := reg+DM(eaddr); if overflow then C:=1 else C := 0; reg := a
Addc reg,#data[7:0] C, V, Z, a a := reg+data[7:0]+C; if overflow then C:=1 else C := 0; reg := a
Addc reg1, reg2, reg3 C, V, Z, a a := reg2+reg3+C; if overflow then C:=1 else C := 0; reg1 := a
Addc reg1, reg2 C, V, Z, a a := reg1+reg2+C; if overflow then C:=1 else C := 0; reg1 := a
Addc reg, eaddr C, V, Z, a a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0; reg := a
Subd reg,#data[7:0] C, V, Z, a a := data[7:0]-reg; if underflow then C := 0 else C := 1; reg := a
Subd reg1, reg2, reg3 C, V, Z, a a := reg2-reg3; if underflow then C := 0 else C := 1; reg1 := a
Subd reg1, reg2 C, V, Z, a a := reg2-reg1; if underflow then C := 0 else C := 1; reg1 := a
Subd reg, eaddr C, V, Z, a a := DM(eaddr)-reg; if underflow then C := 0 else C := 1; reg := a
Subdc reg,#data[7:0] C, V, Z, a a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
Subdc reg1, reg2, reg3 C, V, Z, a a := reg2-reg3-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subdc reg1, reg2 C, V, Z, a a := reg2-reg1-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subdc reg, eaddr C, V, Z, a a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
Subs reg,#data[7:0] C, V, Z, a a := reg-data[7:0]; if underflow then C := 0 else C := 1; reg := a
Subs reg1, reg2, reg3 C, V, Z, a a := reg3-reg2; if underflow then C := 0 else C := 1; reg1 := a
Subs reg1, reg2 C, V, Z, a a := reg1-reg2; if underflow then C := 0 else C := 1; reg1 := a
Subs reg, eaddr C, V, Z, a a := reg-DM(eaddr); if underflow then C := 0 else C := 1; reg := a
Subsc reg,#data[7:0] C, V, Z, a a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1; reg := a
Subsc reg1, reg2, reg3 C, V, Z, a a := reg3-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subsc reg1, reg2 C, V, Z, a a := reg1-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
Subsc reg, eaddr C, V, Z, a a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1; reg := a
Mul reg,#data[7:0] u, u, u, a a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
Mul reg1, reg2, reg3 u, u, u, a a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
Mul reg1, reg2 u, u, u, a a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
Mul reg, eaddr u, u, u, a a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
Mula reg,#data[7:0] u, u, u, a a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
Mula reg1, reg2, reg3 u, u, u, a a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
Mula reg1, reg2 u, u, u, a a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
Mula reg, eaddr u, u, u, a a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
Mshl reg,#shift[2:0] u, u, u, a a := (reg*2shift)[7:0]; reg := (reg*2shift)[15:8]
Mshr reg,#shift[2:0] u, u, u, a a := (reg*2(8-shift)[7:0]; reg := (reg*2(8-shift)[15:8]
Mshra reg,#shift[2:0] u, u, u, a* a := (reg*2(8-shift)[7:0]; reg := (reg*2(8-shift)[15:8]
Cmp reg,#data[7:0] C, V, Z, a a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmp reg1, reg2 C, V, Z, a a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmp reg, eaddr C, V, Z, a a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmpa reg,#data[7:0] C, V, Z, a a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmpa reg1, reg2 C, V, Z, a a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
Cmpa reg, eaddr C, V, Z, a a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Tstb reg,#bit[2:0] -, -, Z, a a[bit] := reg[bit]; other bits in a are 0
Setb reg,#bit[2:0] -, -, Z, a reg[bit] := 1; other bits unchanged; a := reg
Clrb reg,#bit[2:0] -, -, Z, a reg[bit] := 0; other bits unchanged; a := reg
Invb reg,#bit[2:0] -, -, Z, a reg[bit] := not reg[bit]; other bits unchanged; a := reg
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3-6
XE8801A – SX8801R
Sflag -,-,-, a a[7] := C; a[6] := C xor V; a[5] := ST full; a[4] := ST empty
Rflag reg C, V, Z, a a := reg << 1; ; a[0] := 0; C := reg[7]
Rflag eaddr C, V, Z, a a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]
Freq divn -,-,-, - reduces the CPU frequency (divn=nodiv, div2, div4, div8, div16)
Halt -,-,-, - halts the CPU
Nop -,-,-, - no operation
- = unchanged, u = undefined, *MSHR reg,# 1 doesn’t shift by 1
Table 3-4. Instruction short reference
The Coolrisc816 has 8 different addressing modes. These modes are described in Table 3-5. In this table, the
notation ix refers to one of the data memory index registers i0, i1, i2 or i3. Us ing eaddr in an instruction of Table 3-4
will access the data me mory at the address DM(eaddr) and will simultaneously execute the index operation.
extended address
eaddr accessed data memory
location
DM(eaddr)
index
operation
addr[7:0] DM(h00&addr[7:0]) - direct addressing
(ix) DM(ix) - indexed addressing
(ix, offset[7:0]) DM(ix+offset) - indexed addressing with immediate offset
(ix,r3) DM(ix+r3) - indexed addressing with register offset
(ix)+ DM(ix) ix := ix+1 indexed addressing with index post-increment
(ix,offset[7:0])+ DM(ix+offset) ix := ix+offset indexed addressing with index post-increment by the offset
-(ix) DM(ix-1) ix := ix-1 indexed addressing with index pre-decrement
-(ix,offset[7:0]) DM(ix-offset) ix := ix -offset indexed addressing with index pre-decrement by the offset
Table 3-5. Ext en ded add re ss mode d escrip tion
Eleven different jump conditions are implemented as shown in Table 3-6. The contents of the column CC in this
table should replace the CC notation in the instructi on description of Tab l e 3- 4.
CC condition
CS C=1
CC C=0
ZS Z=1
ZC Z=0
VS V=1
VC V=0
EV (EV1 or EV0)=1
After CMP op1,op2
EQ op1=op2
NE op1≠op2
GT op1>op2
GE op1≥op2
LT op1<op2
LE op1≤op2
Table 3-6. Jump condition description
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XE8801A – SX8801R
4 Memory Mapping
4.1 Memory organisation 4-2
4.2 Quick reference data memory register map 4-2
4.2.1 Low power data regist er s (h0000-h0007) 4-3
4.2.2 System, clock configuration and reset configuration (h0010-h001F) 4-4
4.2.3 Port A (h0020-h0027) 4-4
4.2.4 Port B (h0028-h002F) 4-4
4.2.5 Port C (h0030-h0033) 4-5
4.2.6 Flash programming (h0038-003 B) 4-5
4.2.7 Event handler (h003C-h003F) 4-5
4.2.8 Interrupt handler (h0040-h00 47 ) 4-6
4.2.9 USRT (h0048-h004F) 4-7
4.2.10 UART (h0050-h0057) 4-7
4.2.11 Counter/Timer/PWM registers (h0058-h0 05 F ) 4-7
4.2.12 Acquisitio n chain register s (h0060-h0067) 4-8
4.2.13 Voltage multiplier (h007C) 4-8
4.2.14 Voltage Level Detector registers (h007E-h007F) 4-8
4.2.15 RAM (h0080-h027F) 4-8
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XE8801A – SX8801R
4.1 Memory organisation
The XE8801AM-SX8801R CPUs are built with Harvard architecture. Harvard architecture uses separate instruction
and data memories. The instruction bus and data bus are also separated. The advantage of such a structure is that
the CPU can get a new instruction and read/write data simultaneously. The circuit configuration is shown in Figure
4-1. The CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit instructions. The
data memory spa ce has 8 low power registers, the peripher al re gister space and 512 by tes of RAM.
Figure 4-1. Memory ma pping
The CPU internal registers are described in the CPU chapter. A short reference of the low power registers and
peripheral registers is given in 4.2.
4.2 Quick ref e re nc e da t a m em o ry regist er map
The data register map is given in the tables below. A more detailed description of the different registers is given in
the detailed description of the different periph erals.
The tables give the following information:
1. The register name and register addr ess
2. The different bits in the re gist er
3. The access mode of the different bit s (see Table 4-4-1 for code description)
4. The reset source and reset value of the different bits
The reset source coding is given in Table 4-4-2. To get a full description of the reset sources, please refer to the
reset block chapter.
µF µF 0h027F
RAM
capacity:
512 bytes
0h0080
0h1FFF
Instruction
memory
capacity:
8k x 22bit
0h0000
CPU
CPU internal registers
a
stat
iph ipl
i3h i3l
i2h i2l
i1h i1l
i0h i0l
r3
r2
r1
r0
Low power
RAM
0h0000
0h007F
Peripheral
registers
0h0008
Data memor y
data bus
instruction bus
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4-3
XE8801A – SX8801R
code access mode
r bit can be read
w bit can be writte n
r0 bit always reads 0
r1 bit always reads 1
c bit is cleared by writ in g an y value
c1 bit is cleared by writin g a 1
ca bit is cleared after reading
s special function, verify the detailed description in the respective peripherals
Table 4-4-1. Access mode codes used i n th e re gist er definitions
code reset source
sys resetsystem
cold resetcold
pconf resetpconf
sleep resetsleep
Table 4-4-2. Reset source coding used in the register definitions
4.2.1 Low power data registers (h0000-h0007)
Name
Address
7
6
5
4
3
2
1
0
Reg00
h0000 Reg00[7:0]
rw, xxxxxxxx,-
Reg01
h0001 Reg01[7:0]
rw,xxxxxxxx,-
Reg02
h0002 Reg02[7:0]
rw,xxxxxxxx,-
Reg03
h0003 Reg03[7:0]
rw,xxxxxxxx,-
Reg04
h0004 Reg04[7:0]
rw,xxxxxxxx,-
Reg05
h0005 Reg05[7:0]
rw,xxxxxxxx,-
Reg06
h0006 Reg06[7:0]
rw,xxxxxxxx,-
Reg07
h0007 Reg07[/:0]
rw,xxxxxxxx,-
Table 4-4-3. Low p owe r data registers
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4-4
XE8801A – SX8801R
4.2.2 System, clock configuration and reset configuration (h0010-h001F)
Name
Address
7
6
5
4
3
2
1
0
RegSysCtrl
h0010 SleepEn
rw,0,cold EnResPConf
rw,0,cold EnBusError
rw,0,cold EnResWD
rw,0,cold
r0
r0
r0
r0
RegSysReset
h0011 Sleep
rw,0,sys ResetBusError
rc, 0, cold ResetWD
rc, 0, cold ResetfromportA
rc, 0, cold ResPad
rc,0,cold ResPadSleep
rc,0,cold
r0
RegSysClock
h0012 CpuSel
rw,0,sleep ExtClk
r,0,cold EnExtClock
rw,0,cold BiasRC
rw,1,cold ColdXtal
r,1,sleep ColdRC
r,1,sleep EnableXtal
rw,0,sleep EnableRC
rw,1,sleep
RegSysMisc
h0013
r0
r0
r0
r0 RCOnPA0
rw,0,sleep DebFast
rw,0,sleep OutputCkXtal
rw,0,sleep OutputCpuCk
rw,0,sleep
RegSysWd
h0014
r0
r0
r0
r0 WatchDog[3:0]
s,0000,cold
RegSysPre0
h0015
r0
r0
r0
r0
r0
r0
r0 ResPre
c1r0,0,-
RegSysRcTrim1
h001B
r0
r0 Reserved
rw,0,cold RcFreqRange
rw,0,cold RcFreqCoarse[3:0]
rw,0000,cold
RegSysRcTrim2
h001C
r0
r0 RcFreqFine[5:0]
rw,10000,cold
Table 4-4-4. Reset block and clock block registers
4.2.3 Port A (h0020-h0027)
Name
Address
7
6
5
4
3
2
1
0
RegPAIn
h0020 PAIn[7:0]
r
RegPADebounce
h0021 PADebounce[7:0]
rw,00000000,pconf
RegPAEdge
h0022 PAEdge[7:0]
rw,00000000,sys
RegPAPullup
h0023 PAPullup[7:0]
rw,00000000,pconf
RegPARes0
h0024 PARes0[7:0]
rw, 00000000, sy s
RegPARes1
h0025 PARes1[7:0]
rw,00000000,sys
Table 4-4-5. Port A registers
4.2.4 Port B (h0028-h002F)
Name
Address
7
6
5
4
3
2
1
0
RegPBOut
h0028 PBOut[7:0]
rw,00000000,pconf
RegPBIn
h0029 PBIn[7:0]
r
RegPBDir
h002A PBDir[7:0]
rw,00000000,pconf
RegPBOpen
h002B PBOpen[7:0]
rw,00000000,pconf
RegPBPullup
h002C PBPullup[7:0]
rw,00000000,pconf
RegPBAna
h002D
r0
r0
r0
r0 PBAna[3:0]
rw,0000,pconf
Table 4-4-6. Port B registers
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4-5
XE8801A – SX8801R
4.2.5 Port C (h0030-h0033)
Name
Address
7
6
5
4
3
2
1
0
RegPCOut
h0030 PCOut[7:0]
rw,00000000,pconf
RegPCIn
h0031 PCIn[7:0]
r,-,-
RegPCDir
h0032 PD1Dir[7:0]
rw,00000000,pconf
Table 4-4-7. Port C re gist ers
4.2.6 Flash programming (h0038-003B)
These four registers are used during flash programming only. Refer to the flash programming algorithm
documentation for more details.
4.2.7 Event handler (h003C-h003F)
Name
Address
7
6
5
4
3
2
1
0
RegEvn
h003C CntIrqA
rc1,0,sys CntIrqC
rc1,0,sys 128Hz
rc1,0,sys PAEvn[1]
rc1,0,sys CntIrqB
rc1,0,sys CntIrqD
rc1,0,sys 1Hz
rc1,0,sys PAEvn[0]
rc1,0,sys
RegEvnEn
h003D EvnEn[7:0]
rw,00000000,sys
RegEvnPriority
h003E EvnPriority[7:0]
r,11111111,sys
RegEvnEvn
h003F
r0
r0
r0
r0
r0
r0 EvnHigh
r,0,sys EvnLow
r,0,sys
Table 4-4-8. Even t h and ler registers
The origin of the different even ts is s ummarised in the table below.
Event Event source
CntIrqA Count er/ Time r A (cou nter block)
CntIrqB Counter/Timer B (count er bl ock)
CntIrqC Counter/Timer C (counter block)
CntIrqD Counter/Timer D (counter block)
128Hz Low prescaler (clock block)
1Hz Low prescaler (clock block)
PAEvn[1:0] Port A
Table 4-4-9. Event source description
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XE8801A – SX8801R
4.2.8 Interrupt handler (h0040-h0047)
Name
Address
7
6
5
4
3
2
1
0
RegIrqHig
h0040 IrqAC
rc1,0,sys 128Hz
rc1,0,sys
r0 CntIrqA
rc1,0,sys CntIrqC
rc1,0,sys
r0 UartIrqTx
rc1,0,sys UartIrqRx
rc1,0,sys
RegIrqMid
h0041 UsrtCond1
rc1,0,sys UrstCond2
rc1,0,sys PAIrq[5]
rc1,0,sys PAIrq[4]
rc1,0,sys 1Hz
rc1,0,sys VldIrq
rc1,0,sys PAIrq[1]
rc1,0,sys PAIrq[0]
rc1,0,sys
RegIrqLow
h0042 PAIrq[7]
rc1,0,sys PAIrq[6]
rc1,0,sys CntIrqB
rc1,0,sys CntIrqD
rc1,0,sys PAIrq[3]
rc1,0,sys PAIrq[2]
rc1,0,sys
r0
r0
RegIrqEnHig
h0043 IrqEnHig[7:0]
rw,0000000,sys
RegIrqEnMid
h0044 IrqEnMid[7:0]
rw,0000000,sys
RegIrqEnLow
h0045 IrqEnLow[7:0]
rw,0000000,sys
RegIrqPriority
h0046 IrqPriority[7:0]
r,11111111,sys
RegIrqIrq
h0047
r0
r0
r0
r0
r0 IrqHig
r,0,sys IrqMid
r,0,sys IrqLow
r,0,sys
Table 4-4-10. Int er rupt handler registers
The origin of the different interrupts is summarised in the table below.
Event Event source
CntIrqA Counter/Timer A (count er bl ock)
CntIrqB Counter/Timer B (count er bl ock)
CntIrqC Counter/Timer C (counter block)
CntIrqD Counter/Timer D (counter block)
128Hz Low prescaler (clock block)
1Hz Low prescaler (clock block)
PAIrq[7:0] Port A
UartIrqRx UART reception
UartIrqTx UART transmission
UrstCond1 USRT condition 1
UsrtCond2 USRT condition 2
VldIrq Voltage level detector
IrqAC Acquisition chain end of conversion interrupt
Table 4-4-11. Interrupt source description
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XE8801A – SX8801R
4.2.9 USRT (h0048-h004F)
Name
Address
7
6
5
4
3
2
1
0
RegUsrtS1
h0048
r0
r0
r0
r0
r0
r0
r0 UsrtS1
s,1,sys
RegUsrtS0
h0049
r0
r0
r0
r0
r0
r0
r0 UsrtS0
s,1,sys
RegUsrtCond1
h004A
r0
r0
r0
r0
r0
r0
r0 UsrtCond1
rc,0,sys
RegUsrtCond2
h004B
r0
r0
r0
r0
r0
r0
r0 UsrtCond2
rc,0,sys
RegUsrtCtrl
h004C
r0
r0
r0
r0 UsrtWaitS0
r,0,sys UsrtEnWaitCond1
rw,0,sys UsrtEnWaitS0
rw,0,sys UsrtEnable
rw,0,sys
RegUsrtBufferS1
h004D
r0
r0
r0
r0
r0
r0
r0 UsrtBufferS1
r,0,sys
RegUsrtEdgeS0
h004E
r0
r0
r0
r0
r0
r0
r0 UsrtEdgeS0
r,0,sys
Table 4-4-12. USRT register des cription
4.2.10 UART (h0050-h0057)
Name
Address
7
6
5
4
3
2
1
0
RegUartCtrl
h0050 UartEcho
rw,0,sys UartEnRx1
rw,0,sys UartEnTx
rw,0,sys UartXRx
rw,0,sys UartXTx
rw,0,sys UartBR[2:0]
rw,101,sys
RegUartCmd
h0051 SelXtal
rw,0,sys UartEnRx2
rw,0,sys UartRcSel[2:0]
rw,000,sys UartPM
rw,0,sys UartPE
rw,0,sys UartWL
rw,1,sys
RegUartTx
h0052 UartTx[7:0]
rw,0000000,sys
RegUartTxSta
h0053
r0
r0
r0
r0
r0
r0 UartTxBusy
r,0,sys UartTxFull
r,0,sys
RegUartRx
h0054 UartRx[7:0]
r,00000000,sys
RegUartRxSta
h0055
r0
r0 UartRxSErr
r,0,sys UartRxPErr
r,0,sys UartRxFErr
r,0,sys UartRxOerr
rc,0,sys UartRxBusy
r,0,sys UartRxFull
r,0,sys
Table 4-13. UAR T register des cription
4.2.11 Counter/Timer/PWM registers (h0058-h005F)
Name
Address
7
6
5
4
3
2
1
0
RegCntA
h0058 CounterA[7:0]
s,xxxxxxxx,-
RegCntB
h0059 CounterB[7:0]
s,xxxxxxxx,-
RegCntC
h005A CounterC[7:0]
s,xxxxxxxx,-
RegCntD
h005B CounterD[7:0]
s,xxxxxxxx,-
RegCntCtrlCk
h005C CntDCkSel[1:0]
rw,xx,- CntCCkSel[1:0]
rw,xx,- CntBCkSel[1:0]
rw,xx,- CntACkSel[1:0]
rw,xx,-
RegCntConfig1
h005D CntDDownUp
rw,x,- CntCDownUp
rw,x,- CntBDownUp
rw,x,- CntADownUp
rw,x,- CascadeCD
rw,x,- CascadeAB
rw,x,- CntPWM1
rw,0,sys CntPWM0
rw,0,sys
RegCntConfig2
h005E CapSel[1:0]
rw,00,sys CapFunc[1:0]
rw,00,sys Pwm1Size[1:0]
rw,xx,- Pwm0Size[1:0]
rw,xx,-
RegCntOn
h005F
r0
r0
r0
r0 CntDEnable
rw,0,sys CntCEnable
rw,0,sys CntBEnable
rw,0,sys CntAEnable
rw,0,sys
Table 4-14. Cou nter/timer/PWM register description.
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4-8
XE8801A – SX8801R
4.2.12 Acquisition chain registers (h0060 -h00 67)
Name
Address
7
6
5
4
3
2
1
0
RegAcOutLsb
h0060 OUT[7:0]
r,0,sys
RegAcOutMsb
h0061 OUT[15:8]
r,0,sys
RegAcCfg0
h0062 START
w r0,0,sys SET_NELCONV[1:0]
rw,01,sys SET_OSR[2:0]
rw,010,sys CONT
rw,0,sys
r0
RegAcCfg1
h0063 IB_AMP_ADC[1:0]
rw,11,sys IB_AMP_PGA[1:0]
rw,11,sys ENABLE[3:0]
rw,0000,sys
RegAcCfg2
h0064 FIN
rw,00,sys PGA2_GAIN[1:0]
rw,00,sys PGA2_OFFSET[3:0]
rw,0000,sys
RegAcCfg3
h0065 PGA1_GAIN
Rw,0,sys PGA3_GAIN[6:0]
rw,0000000,sys
RegAcCfg4
h0066
r0 PGA3_OFFSET
rw,0000000,sys
RegAcCfg5
h0067 BUSY
r,0,sys DEF
w r0 AMUX[4:0]
rw,00000,sys VMUX
rw,0,sys
Table 4-15. Acquisition chain register description.
4.2.13 Voltage multiplier (h007C)
Name
Address
7
6
5
4
3
2
1
0
RegVmultCfg0
h007C
r0
r0
r0
r0
r0 Enable
rw,0,sys Fin[1:0]
rw,00,sys
Table 4-16. VMUL T register.
4.2.14 Voltage Level Detector registers (h007E-h007F)
Name
Address
7
6
5
4
3
2
1
0
RegVldCtrl
h007E
r0
r0
r0
r0 VldRange
rw,0,sys VldTune[2:0]
rw,000,sys
RegVldStat
h007F
r0
r0
r0
r0
r0 VldResult
r,0,sys VldValid
r,0,sys VldEn
rw,0,sys
Table 4-17. Voltage level detecto r reg iste r de script ion
4.2.15 RAM (h0080-h027F)
The 512 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables
stored in the RAM sho uld be initialised before use si nce t hey can have any va lue at circuit start up.
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5-1
XE8801A – SX8801R
5 System Block
5.1 Overview 5-2
5.2 Operating mode 5-2
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5-2
XE8801A – SX8801R
5.1 Overview
The XE8000 chips have three operating modes. There are; normal, low current and very low current modes (see
Figure 5-1). The different modes are controlled by the reset and clock blocks (see the documentation of the
respective blocks).
5.2 Operating mode
Start-up
All bits are reset in the design when a POR (power-on-reset) is active.
RC is enabled, Xt a l is di sabled and the CP U is reset (pmaddr = 0000).
If the port A is used to return f rom t he sleep mode, all bits with reset cold don ’t change (see sleep mode)
Reset
All bits with resetsystem and resetpconf (if enabled) are reset. Clock configuration doesn’t change except cpuck.
The CPU is reset
Active mode
This is the mode where the CPU and all peripherals can work and execute the embedded software.
Standby mode
Executing a HALT instruction moves the XE8000 into the Standby mode. The CPU is stopped, but the clocks
remain active. Therefor, the enabled peripherals remain active e.g. for time keeping. A reset or an interrupt/event
request (if ena ble d) cancels the standby mode.
Sleep mode
This is a very low-power mode because all circuit clocks and all peripherals are stopped. Only some service blocks
remain active. No time-keeping is possible. Two instructions are necessary to move into sleep mode. First, the
SleepEn (sleep enable) bit in RegSysCtrl has to be set to 1. The sleep mode can then be activated by setting the
Sleep bi t in RegSysReset to 1.
There are three possibe ways to wake -up from the sl eep mode:
1. The por (power-on-re set caused by a power-down followed by po wer- on) . The RAM information is l ost .
2. The padreset
3. The Port A reset combination (if the Port A is present in the product). See Port A documentation for
more details.
Note: If the Port A is used to return from the sleep mode, all bits with resetcold don’t change (RegSysCtrl,
RegSysReset (except bit sleep), EnExtClock and BiasRc in RegSysClock, RegSysRcTrim1 and
RegSysRcTrim2). The SleepFlag bit in RegSysReset, reads back a 1 if the circuit was in sleep mode
since the flag was last clea red (see reset block for more details).
Note: For a lower power consumption, disable the BiasRc bit in RegSysClock before to going to sleep mode.
The start-up ti me of the oscillator wil l the n be lon ger however.
Note: It is recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode
because this instruction can be execut ed when the sleep mod e is l ef t using the resetfromportA.
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5-3
XE8801A – SX8801R
START-UP
RESET
ACTIVE STAND-BY SLEEP
Halt in struction
Interrupt/event
set bit sleep
po
r
padreset
portA reset
po
r
normal mode low current very low current
po
r
padreset
portA reset
watchdog reset
buserror reset
padreset
portA reset
watchdog reset
por
without
condition
without
condition
Figure 5-1. XE8 801 A an d SX8801R operatin g mod es.
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6-1
XE8801A – SX8801R
6 Reset Block
6.1 Features 6-2
6.2 Overview 6-2
6.3 Register map 6-2
6.4 Reset handling capabilities 6-3
6.5 Reset source description 6-4
6.5.1 Power On Reset 6-4
6.5.2 RESET pin 6-4
6.5.3 Programmable Port A input combination 6-4
6.5.4 Watchdog reset 6-4
6.5.5 BusError reset 6-4
6.5.6 Sleep mode 6-4
6.6 Control register description and operation 6-4
6.7 Watchdog 6-5
6.8 Start-up and watchdog specifications 6-5
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6-2
XE8801A – SX8801R
6.1 Features
• Power On Reset (POR)
• External reset from the RESET pin
• Programmable Watchdog timer reset
• Programmable BusError reset
• Sleep mode managemen t
• Programmable Port A inpu t comb ina t ion reset
6.2 Overview
The reset block is the reset manager. It handles the different reset sources and distributes them through the
system. It also controls the sleep mode of the circuit.
6.3 Register map
Pos. RegSysCtrl Rw Reset Function
7 SleepEn r w 0 resetco ld enables Sleep mode
0: sleep mode is disabled
1: sleep mode is enabled
6 EnResPConf r w 0 resetcold enables the resetpconf signal when the
resetglobal is active
0: resetpconf is disabled
1: resetpconf is enabled
5 EnBusError r w 0 resetcold enables reset from BusError
0: BusError reset source is disabled
1: BusError reset source is enabled
4 EnResWD r w 0 reset co ld enables reset from W atc hdog
0: Watchdog reset source is disabled
1: Watchdog reset source is enabled
this bit can not be set to 0 by SW
3 – 0 - r 0000 unused
Table 6-1. RegSysCtrl register.
Pos. RegSysReset Rw Reset Function
7 Sleep rw 0 reset system Sleep mode control (reads always 0)
6 - r 0 unused
5 ResetBusError r c 0 resetcold reset source was BusError
4 ResetWD r c 0 resetcold reset source was Watchdog
3 ResetfromportA r c 0 resetcold reset source was Port A combination
2 ResPad r c 0 resetcold reset source was reset pad
1 ResPadSleep r c 0 resetcold reset source was reset pad in sleep mode
0 - r 0 unused
Table 6-2. RegSysReset register
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6-3
XE8801A – SX8801R
Pos. RegSysWD Rw Reset Function
7 – 4 - r 0000 unused
WDKey[3] w Watchdog Key bit 3
3 WDCounter[3] r 0 resetcold Watchdog counter bit 3
WDKey[2] w Watchdog Key bit 2
2 WDCounter[2] r 0 resetcold Watchdog counter bit 2
WDKey[1] w Watchdog Key bit 1
1 WDCounter[1] r 0 resetcold Watchdog counter bit 1
WDKey[0] w Watchdog Key bit 0
0 WDCounter[0] r 0 resetcold Watchdog counter bit 0
Table 6-3. RegSysWD register
6.4 Reset handling capabilities
There are 5 reset sources:
• Power On Reset (POR)
• External reset from the RESET p in
• Programmable Port A inpu t comb ina tion
• Programmable watchdog timer reset
• Programmable BusError reset on processor access outside the allocated memory map
Another res et source is the bit Sleep in the RegSysReset register. This source is fully controlled by software and
is only used duri ng the sl eep mode.
Four internal reset signals are generated from th ese sources and distribute d through the sy stem:
• resetcold: is asserted on POR
• resetsystem: is asserted when resetcold or any other enabled reset source is active
• resetpconf: is asserted when resetsystem is active and if the EnResPConf bit in the RegSysCtrl register
is set. This reset is generally used in the different ports. It allows to maintain the port
configuration unchanged while the rest of the circuit is reset.
• resetsleep: is asserted when the circuit is in sleep mo de
For the circuits XE8801AM/XE88LC01AM/SX8801R and XE8805AM/XE88LC05AM
(2) For the circuits XE88LC01 and XE88LC05
Table 6-4 shows a summary of the dependency of the internal reset signals on the various reset sources. In all the
tables describing the different registers, the reset source is indicated.
Internal reset signals
resetpconf
Asserted
reset source resetsystem when
EnResPConf=0 when
EnResPConf=1 resetsleep resetcold
POR Asserted Asserted Asserted Asserted Asserted
RESET pin (1) Asserte d Asserted Asserted Asserted Asserted
RESET pin (2) Asserted - Asserted - -
PortA input Asserted - Asserted - -
Watchdog Asserted - Asserted - -
BusError Asserted - Asserted - -
Sleep - - - Asserted -
(1) For the circuits XE8801AM/XE88LC01AM/SX8801R and XE8805AM/XE88LC05AM
(2) For the circuits XE88LC01 and XE88L C05
Table 6-4 Inter na l reset assertion as a function of the re set source.
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6-4
XE8801A – SX8801R
6.5 Reset source desc ription
6.5.1 Power On Reset
The power on reset (POR) monitors the external supply voltage. It activates a reset on a rising edge of this supply
voltage. The reset is inactivated only if the internal voltage regulator has started up. No precise voltage level
detection is perfor med by the POR block.
6.5.2 RESET pin
The reset can be activ a te d by applying a high input state on the RESET pin.
6.5.3 Programmable Port A input combination
A reset signal can be ge ne rated by Port A. See the descrip tion of the P ort A for furthe r information.
6.5.4 Watchdog reset
The Watchdog will generate a reset if the EnResetWD bit in the RegSysCtrl register has been set and if the
watchdog is not cleared in time by the processor. See chapter 6.7 de scri bin g the watchdog fo r fu rther information.
6.5.5 BusError reset
The address space is assigned as shown in the register map of the product. If the EnBusError bit in the
RegSysCtrl register is set and a non- existant addre ss i s accessed b y the software, a reset is generated .
6.5.6 Sleep mode
Entering the sleep mode will reset a part of the circuit. The reset is used to configure the circuit for correct wake-up
after the sleep mode. If the SleepEn bit in the RegSysCtrl register has been set, the sleep mode can be entered
by setting the bit Sleep in RegSysReset. During the sleep mode, the resetsleep signal is active. For detailed
information on the sleep mode, see the system documentation.
6.6 Control register description and operation
Two registers are dedicated for reset status and control, RegSysReset and RegSysCtrl. The bits Sleep, and
SleepEn are also located in those registers and are described in the chapter dedicated to the different operating
modes of the circuit (sys tem block).
The RegSysReset register gives information on the source which generated the last reset. It can be read at the
beginning of the application program to detect if the circuit is recovering from an error or exception condition, or if
the circuit is star ting up normally.
• when ResBusError is 1, a forbidden add ress access ge nerated the rese t.
• when ResWD is 1, the watchdog generated the reset.
• when ResPortA is 1, a PortA combination gene rated the reset.
• when ResPad is 1, a reset pin gene rated the reset.
• when ResPadSleep is 1, a reset pin in sleep mode gene rated the reset.
Note: If no bit is set to 1, the reset source was the internal POR.
Note: Several bits might be set or not, if the register was not cleared in between 2 reset occurrences. Write
any value in RegSysReset to clear it.
Note: When a reset pin wakes up the chip from the sleep mode, ResPad and ResPadSleep bits are equal
at 1.
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XE8801A – SX8801R
The last bit conc erns the sleep mode control (see syst em documentation for the sleep mode description).
• when Sleep is set to 1, and SleepEn is 1, the sleep mode is entered. The bit always reads back a 0.
The RegSysCtrl register enab les t he different available reset sources and the slee p mod e.
• EnResWD enab les the reset due to the watchdog (can not be disabled once ena bled).
• EnBusError enables the reset due to a bus error condi tio n.
• EnResPConf enables the reset of the port configurations when reset by Port A, a Bus Error or the
watchdog.
• SleepEn unlocks the Sleep bit. As long as SleepEn is 0, the Sleep bit has no effect.
6.7 Watchdog
The watchdog is a timer which has to be cleared at least every 2 seconds by the software to prevent a reset being
generated by the timeout condition.
The watchdog can be enabled by software by setting the EnResWD bit in the RegSysCtrl register to 1. It can then
only be disabled by a power on reset.
The watchdog timer can be cleared by writing consecutively the values Hx0A and Hx03 to the RegSysWD register.
The sequence must str i ctly be respected to clea r th e watchdog.
In assembler code, the sequence to clear the watchdog is:
move AddrRegSysWD, #0x0A
move AddrRegSysWD, #0x03
Only writing Hx0A followed by Hx03 resets the WD. If some other write instruction is done to the RegSysWD
between the writing of th e Hx 0A and Hx03 valu es, the watchdog timer will not be clear ed.
It is possible to read the status of the watchdog in the RegSysWD register. The watchdog is a 4 bit counter with a
count range between 0 and 7. The system reset is generated when the cou nter is reaching the value 8.
6.8 Start-up and watchdog specifications
At start-up of the circuit, the POR (power-on-reset) block generates a reset signal during tPOR. The circuit starts
software execution after this period (see system chapter). The POR is intended to force the circuit in a correct state
at start-up. For precise monitor ing of t he supply volta ge , t he voltage level detector (V LD) has to be used.
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XE8801A – SX8801R
Symbol Parameter Min Typ Max Unit Comments
TPOR POR reset duration 5 20 ms
TRESET RESET pin reset duration 20 200 µs 3
TRESET RESET pin reset duration 5 20 ms 4
Vbat_sl_M Supply ramp up of MTP version 20 V/ms 1
Vbat_sl_R Supply ramp up of RO M ve rsio n 0.25 V/ms 1
WDtime Watchdog timeout period 2 s 2
Table 6-5. Electrical a nd t i min g specifications
Note: 1) The Vbat_sl defines the minimum slop e req uir ed on VB AT. Correct start-u p of th e circu i t is no t g uar anteed
if this slope is too slow. In such a case, a delay ha s to b e bu ilt using t he RESET pin.
Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. The watchdog
takes its clock from the low prescaler. In case an external clock source is used, the RC oscillator must be enabled
also (EnRC=1 in RegSysClock). Othe rwise , the watchdog is stopped (see the clock block documentatio n).
Note: 3) For the circuit versions XE88LC01 and XE88LC05. Gives the time the reset is active after the falling edge
of the RESET pin.
Note: 4) For the circuit versions XE88LC01A and XE88LC05A. Gives the time the reset is active after the falling
edge of the RES ET pin .
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XE8801A – SX8801R
7 Clock Generator
7.1 Features 7-2
7.2 Overview 7-2
7.3 Register map 7-2
7.4 Interrupts and events m ap 7-4
7.5 Clock sources 7-4
7.5.1 RC oscillator 7-4
7.5.2 Xtal oscillator 7-6
7.5.3 External clock 7-7
7.6 Clock source selecti on 7-8
7.7 RegSysMisc Description 7-8
7.8 Prescalers 7-9
7.9 32 kHz frequenc y selector 7-9
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XE8801A – SX8801R
7.1 Features
• 3 available clock sources (RC oscillator, quartz oscillator and external clock).
• 2 divider chains : high-prescaler (8 bits) and low-prescaler (15 bits).
• CPU clock disabling in halt m ode .
7.2 Overview
The XE8801AM – SX8801R chips can work on different clock sources (RC oscillator, quartz oscillator and external
clock). The clock generator block is in charge of distributin g the necessary clock fre quencies to the circuit .
Figure 7-1 represents the fu nctionality of the clock block.
The internal RC oscillator drives the high prescaler. This prescaler generates frequency divisions down to 1/256 of
its input frequency. A 32 kHz clock is generated by enabling the quartz oscillator (if present in the product) or by
selecting the appropriate tap on the high prescaler. The low prescaler generates clock signals from 32 kHz down to
1Hz. The clock source for the CPU can be selected from the RC oscillator, the external clock or the 32 kHz clock.
7.3 Register map
pos. RegSysClock rw Reset function
7 CpuSel rw 0 resetsleep Select speed for cpuck, 0=RC, 1=xtal or
external clock
6 Extclk r 0 resetcold External clock detected, 1=availab l e
5 EnExtClock rw 0 resetcold Enabl e fo r external clock, 1=en abled
4 BiasRc rw 1 resetcold Enable Rcbias (red uces start-up time of RC).
3 ColdXtal r 1 resetsleep Xtal in start phase
2 ColdRC r 1 resetsleep RC in start phase
1 EnableXtal rw 0 resetsleep Enable Xtal oscillator, 0=disabl ed , 1=en ab led
0 EnableRc rw 1 resetsleep Enable RC oscillator, 0=disabled, 1=enabled
Table 7-1: RegSysClock register
pos. RegSysMisc rw Reset Function
7-4 -- r 0000 Unused
3 RCOnPA0 rw 0 resetsleep Start RC on PA[0], 0=disabled, 1=enabled
2 DebFast rw 0 resetsleep Debouncer clock speed, 0=256Hz, 1=8kHz
1 OutputCkXtal rw 0 resetsleep Output Xtal Clock on PB[3], 0=disabled,
1=enabled if EnXtal=1 else PB[ 3 ]=0
0 OutputCpuCk rw 0 resetsleep Output CPU clock on PB[2], 0=disabled,
1=enabled
Table 7-2: RegSysMisc reg ister
pos. RegSysPre0 rw reset Function
7-1 -- r 0000000 Unused
0 ResPre w1
r0 0 Write 1 to reset low prescaler, but always
reads 0
Table 7-3: RegSysPre0 register
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XE8801A – SX8801R
pos. RegSysRcTrim1 rw reset Function
7-4 -- r 00 Unused
5 Reserved rw 0 resetcold Reserved
4 RcFreqRange rw 0 resetcold Low/high freq . range (low=0 )
3 Rc FreqCoars e[3] rw 0 rese tcold RC coarse trim bit 3
2 Rc FreqCoars e[2] rw 0 rese tcold RC coarse trim bit 2
1 Rc FreqCoars e[1] rw 0 rese tcold RC coarse trim bit 1
0 Rc FreqCoars e[0] rw 0 rese tcold RC coarse trim bit 0
Table 7-4: RegSysRCTrim1 register
pos. RegSysRcTrim2 Rw reset function
7-6 -- r 00 Unused
5 RcFreqFine[5] rw 1 resetcold RC fine trim bit 5
4 RcFreqFine[4] rw 0 resetcold RC fine trim bit 4
3 RcFreqFine[3] rw 0 resetcold RC fine trim bit 3
2 RcFreqFine[2] rw 0 resetcold RC fine trim bit 2
1 RcFreqFine[1] rw 0 resetcold RC fine trim bit 1
0 RcFreqFine[0] rw 0 resetcold RC fine trim bit 0
Table 7-5: RegSysRCTrim2 register
OSCIN
RC
Xtal
High prescaler
CpuCk
CpuSel
0
1
RegSysRcTrim1
RegSysRcTrim2
0
1
CkRc
CkXtal
EnXtal and
not(ExtClk or EnExtClk)
Low prescaler 32kHz
to
1Hz
CkRc
to
CkRc/256
External
Clock 0
1
Figure 7-1. Clock block structure
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XE8801A – SX8801R
7.4 Interrupts and eve nts ma p
Interrupt Interrupt source Mapping in the interrupt manager Mapping in the event manager
IrqPre1 Ck128Hz RegIrqHig(6) RegEvn(5)
IrqPre2 Ck1Hz RegIrqMid(3) RegEvn(1)
Table 7-6: Interrupts and events map
7.5 Clock sources
7.5.1 RC oscillator
7.5.1.1 Configuration
The RC oscillator is always turned on and selected for CPU and system operation at power-on reset and when
exiting sleep mode. It can be turned off after the Xtal (quartz oscillator) has been started, after selection of the
external clock or by entering sleep mod e.
The RC oscillator has two frequency ranges: sub-MHz (100 kHz to 1 MHz) and above-MHz (1 MHz to 10 MHz).
Inside a range, the frequency can be tuned by software for coarse and fine adjustment. See registers
RegSysRcTrim1 and RegSysRcTrim2.
Bit EnableRC in register RegSysClock controls the propagation of the RC clock signal and the operation of the
oscillator. The user can stop the RC oscillator by resetting the bit EnableRC. Entering the sleep mode disables the
RC oscillator.
Note: Before turning off the RC oscillator, the cpusel bit in RegSysClock must be set to one.
Note: The RC oscillator bias can be maintained while the oscillator is switched off by setting the bit BiasRc in
RegSysClock. This allows a faster restart of the RC oscillator at the cost of increased power consumption when
the oscillator is disabled (see section 7.5.1.3).
7.5.1.2 RC oscillator frequency tuning
The RC oscillator frequency can be set using the bits in the RegSysRcTrim1 and RegSysRcTrim2 registers.
Figure 7-2 shows the nominal frequency of the RC oscillator as a function of these bits. The absolute value of the
frequency for a given register content may change by ±50% from chip to chip due to the tolerances on the
integrated capacitors and resistors. However, the modification of the frequency as a function of a modification of
the register content is fairly precise for frequencies below 2MHz. This means that the curves in Figure 7-2 can shift
up and down but that the slope remains unchanged.
The bit RcFreqRange modifies the oscillator frequency by a factor of 10. The upper curve in the figure
corresponds to RcFreqRange=1.
The RcFreqCoarse modifies the frequency of the oscillator by a factor (RcFreqCoarse+1). The figure represents
the frequen cy for 5 diffe ren t v alues of the bi ts RcFreqCoarse: for each v alue the frequency i s mult iplie d by 2.
Incrementing the RcFreqFine code increases the frequency by about 1.4%.
The frequency of the oscillator is therefor given by:
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XE8801A – SX8801R
f
RC=fRcmin⋅(1+9⋅RcFreqRange)⋅(1+RcFreqCoarse)⋅(1.014)RcFreqFine
with fRcmin the RC oscillator frequency if the registers are all 0. At higher frequencies, the frequency may deviate
from the v alu e pre dicted by the equ ation.
000000
010000
100000
110000
111111
010000
100000
110000
111111
010000
100000
110000
111111
010000
100000
110000
111111
010000
100000
110000
111111
000000
010000
100000
110000
111111
010000
100000
110000
111111
010000
100000
110000
111111
010000
100000
110000
111111
010000
100000
110000
111111
0000 0001 0011 0111 1111
1E+04
1E+05
1E+06
1E+07
1E+08
RcFreqCoarse(3:0)
Nominal RC oscillator frequency [Hz]
RcFreqRange='1'
RcFreqRange='0'
RcFreqFine(5:0)
RcFreqFine(5:0)
Figure 7-2. RC oscillator nominal frequency tuning.
7.5.1.3 RC oscillator specifications
symbol description min typ max unit Comments
fRCmin Lowest RC freque ncy 40 80 120 kHz Note 1
RcFreqFine fine tuning step 1.4 2.0 %
RC_su startup time 30 50 us
BiasRc=0
3 5 us
BiasRc=1
PSRR @ DC Supply voltage TBD %/V Note 2
dependence TBD %/V Note 3
∆f/∆T Temperature
dependence 0.1
%/°C
Table 7-7. RC oscillator specifications
Note 1: this is the freque ncy tolerance when all tr immin g code s are 0.
Note 2: frequency shift as a function of VBAT with normal regula to r fu nction.
Note 3: frequency shift as a function of VBAT while the regu lator is short-circuited t o VBAT.
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XE8801A – SX8801R
The tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the
software DFLL (digital frequency locked loop) which uses the crystal oscillator as a reference frequency.
7.5.2 Xtal oscillator
7.5.2.1 Xtal configuration
The Xtal operat es wit h an ex ternal crystal of 32’768 Hz.
During Xtal oscillator start-up, the first 32768 cycles are masked. The two bits EnableXtal and ColdXtal in register
RegSysClock control the oscillator.
At power-on reset or during sleep mode, EnableXtal is reset and ColdXtal is set (Xtal oscillator is not selected at
start-up). The user can start Xtal oscillator by setting EnableXtal. When the Xtal oscillator starts, bit ColdXtal is
reset after 32768 cycles. Before ColdXtal is reset by the system, the Xtal frequency precision is not guaranteed.
The Xtal oscillat or can be stop ped by the user by rese tt ing bit EnableXtal.
When the user enter s int o slee p mod e, the Xtal is stopped.
When an external clock is detect ed (ExtClk = 1) or the EnExtClock is set 1, the EnableXtal bit can not be set to 1.
7.5.2.2 Xtal oscillator specifications
The crystal oscillator has been designed for a crystal with the specifications given in Table 7-8. The oscillator
precision can only be guarant eed for this crysta l.
Symbol Description Min Typ Max Unit Comments
Fs Resonance frequency 32768 Hz
CL CL for nominal
frequency 8.2 15 pF
Rm Motional resistance 40 100
kΩ
Cm Motional capacitance 1.8 2.5 3.2 fF
C0 Shunt capacitance 0.7 1.1 2.0 pF
Rmp Motional resistance of
6th overtone (parasitic) 4 8
kΩ
Q Quality factor 30k 50k 400k -
Table 7-8. Crystal specifications.
For safe operation, low power consum pt ion and to meet the specified precision, caref ul board layout is requ ire d:
Keep lines OSCIN and OSCOUT short and insert a VSS line in betwee n th em.
Connect the crystal package to V SS.
No noisy or digital lines near OSCIN or OSCOUT.
Insert guards where needed.
Respect the board specifications of Table 7-9.
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XE8801A – SX8801R
Symbol Description Min Typ Max Unit Comments
Rh_oscin Resistance OSCIN-VSS 10
MΩ
Rh_oscout Resistance O SCO U T -VS S 10
MΩ
Rh_oscin_oscout Resistance OS CIN-OSCOUT 50
MΩ
Cp_oscin Capacitance OSCIN-VSS 0.5 3.0 pF
Cp_oscout Capacitance OSCOUT-VSS 0.5 3.0 pF
Cp_oscin_oscout Capacitance OSCIN-OSCOUT 0.2 1.0 pF
Table 7-9. Board layout specifications.
The oscillator characteristics are given in Table 7-10. The characteristics are valid only if the crystal and board
layout meet the specifications above.
Symbol Description Min Typ Max Unit Comments
fXtal Nominal frequency 32768 Hz
St_xtal Start-up time 1 2 s
Fstab Frequency deviation -100 300 ppm Note 1
Table 7-10. Crystal oscillator charac teristics.
Note 1. This gives the relative frequency deviation from nominal for a crystal with CL=8.2pF and within the
temperature range -40°C to 85°C. The crystal tolerance, crystal aging and crystal temperature drift are not included
in this figure.
7.5.3 External clock
7.5.3.1 External clock configuration
The user can provide an external clock instead of the internal oscillators. Only the CPU can use the external clock.
The external clo ck inpu t pi n is OSCIN.
The system is configured for external clock by bit EnExtClock in re gister RegSysClock.
When EnExtClock is set to 1, the external clock is detected after 4 pulses on pin OSCIN. The ExtClk bit shows
when the external clock is available.
Note: when using the ext e rnal clock, the Xtal is not avai lab le.
7.5.3.2 External clock specification
The external clock has to satisfy the specifications in the table below. Correct behavior of the circuit can not be
guaranteed if t he e xternal clock signal doe s not resp ect the specificatio ns be low.
Symbol Description Min Typ Max Unit Comments
FEXT External clock
frequency 2 MHz
PW_1 Pulse 1 width 0.2 µs
PW_0 Pulse 0 width 0.2 µs
Table 7-11. External clock specific ati ons.
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XE8801A – SX8801R
7.6 Clock source selection
There are three possible clock sources available for the CPU clock. The RC clock is always selected after power-
up or after Sleep mode. The CPU clock selection is done with the bit CpuSel in RegSysClock (0= RC clock, 1= 32
kHz from Xtal if EnableXtal =1, ExtClk = 0 and EnExtClk = 0 else external clock).
Switching from on e clock sou rce to another is glit ch fr ee.
The next table summarizes the diff e ren t clock con figurations of t he circuit :
Clock Sources Clock targets
Cpuck Note 1
Mode
name
EnExtClk
EnableRc
EnableXtal
CpuSel=0 CpuSel=1
High
Prescaler
Clock
input
Low
Prescaler
Clock
input
Sleep 0 0 0 Off Off Off Off
Xtal 0 0 1 Off Xtal Off Xtal
RC 0 1 0 RC RC RC High presc.
RC + Xtal 0 1 1 RC Xtal RC Xtal
External 1 0 X Off External Off Off
RC +
External 1 1 X RC External RC High presc.
Table 7-12: Table of clocking modes.
Note 1: The CPU clock can be divided by using the freq instruction (see coolrisc instruction set)
Switching from one clock source to another and stopping the unused clock source must be performed using 3
MOVE instructions to RegSysClock. First select the new clock source, secondly change the CpuSel bit and finally
stop the unused one.
7.7 RegSysMisc Description
The RCOnPA0 bit in RegSysMisc can be used to enable the RC oscillator on an event external to the circuit. If
RCOnPA0 is 1, the RC osc illator is enabled (EnableRC bit is set to 1) as soon as the va lue on port A pin PA[0] is
equal to 1. The Port A pin can be debounced (see Po rt A do cumen tation).
Bit DebFast in the RegSysMisc register allows to chose the debouncer clock between 256Hz and 8kHz (DebFast
= 0 and DebFast = 1 respectively). The Debouncer clock is used to debounce PA inputs (see Port A
documentation).
Bit OutputCkXtal allows to show the Xtal clock on PB[3]. The EnableXtal bit must be set to 1 else PB[3] equals 0
(see port B documen tation to set up the Port B).
Bit OutputCpuCk allows to show the CpuClock on PB[2] (see Port B documentation).
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XE8801A – SX8801R
7.8 Prescalers
The clock generator bl ock emb ed s two divider chain s: t he high prescaler and t he low prescaler.
The high prescaler is mad e of an 8 stage dividi ng chain and the low prescaler of a 15 stage dividi ng chain.
Features:
• High pre scale r can on ly be dr iv en with RC clock (bit EnableRc have to be set, see Table 7-12).
• Low prescaler can be driven from the high prescaler or directly with the Xtal clock when bit EnableXtal is set to
1, bit EnExtClock is set to 0 and ExtClk is equal at 0.
• Bit ResPre in the RegSysPre0 register allows to reset synchronously the low prescaler, the low prescaler is
also automatically cleared when bit EnableXtal is set. Both dividing chains are reset asynchronously by the
resetsleep signal.
• Bit ColdXtal=1 indicates the Xtal is in its start up phase. It is active for 37268 Xtal cycles after setting
EnableXtal.
7.9 32 kHz frequency selector
A decoder is used to select from the high prescaler the frequency tap that is the closest to 32 kHz to operate the
low prescaler when the Xtal is not running. In this case, the RC oscillator frequency of ±50% will also be valid for
the low prescaler fr eq uency outputs.
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XE8801A – SX8801R
8 IRQ - Interrupt Handler
8.1 Features 8-2
8.2 Overview 8-2
8.3 Register map 8-2
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XE8801A – SX8801R
8.1 Features
The XE8000 chi ps supp or t 24 interrupt sou rces, divided in to 3 l ev els of priority .
8.2 Overview
A CPU interruption is generated and memorized when an interrupt becomes active. The 24 interrupt sources are
divided into 3 levels of priority: High (8 interrupt sources), Mid (8 interrupt sources), and Low (8 interrupt sources).
Those 3 levels of priority are directly mapped to those supported by the CoolRisc (IN0, IN1 and IN2; see CoolRisc
documentation for more informat io n).
RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags
are set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or
RegIrqEnLow is set) and a rising edge is det ected on the correspo nd ing interrupt source.
Once memoriz ed, an interru pt flag can be cleared by writing a ‘1’ in th e corresponding bit of RegIrqHig, RegIrqMid
or RegIrqLow. Writing a ‘0’ does not modify the flag. To definitively clear the interrupt, one has to clear the
CoolRisc interrupt in the CoolRisc status regi ste r. All interrupts are automatically clear ed aft er a rese t.
Two registers are provided to facilitate the writing of interrupt s ervice software. RegIrqPriority contains the number
of the highest priority interrupt set (its value is 0xFF when no interrupt is set). RegIrqIrq indicates the priority level
of the current interrupts. RegIrqIrq and RegIrqPriority ‘s values are dependent upon the memorized state of the
interrupts (as reflected in fl a gs in RegIrqHig, RegIrqMid and RegIrqLow).
8.3 Register map
pos. RegIrqHig rw reset function
7 RegIrqHig[7] r
c1 0 resetsystem interrupt #23 (high priority)
clear inter rupt #23 whe n 1 is written
6 RegIrqHig[6] r
c1 0 resetsystem interrupt #22 (high priority )
clear inter rupt #22 whe n 1 is written
5 RegIrqHig[5] r
c1 0 resetsystem interrupt #21 (high priority )
clear inter rupt #21 whe n 1 is written
4 RegIrqHig[4] r
c1 0 resetsystem interrupt #20 (high priority )
clear inter rupt #20 whe n 1 is written
3 RegIrqHig[3] r
c1 0 resetsystem interrupt #19 (high priority )
clear inter rupt #19 whe n 1 is written
2 RegIrqHig[2] r
c1 0 resetsystem interrupt #18 (high priority )
clear inter rupt #18 whe n 1 is written
1 RegIrqHig[1] r
c1 0 resetsystem interrupt #17 (high priority )
clear inter rupt #17 whe n 1 is written
0 RegIrqHig[0] r
c1 0 resetsystem interrupt #16 (high priority )
clear inter rupt #16 whe n 1 is written
Table 8-1: RegIrqHig
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XE8801A – SX8801R
pos. RegIrqMid rw reset function
7 RegIrqMid[7] r
c1 0 resetsystem interrupt #15 (mid priority)
clear inter rupt #15 whe n 1 is written
6 RegIrqMid[6] r
c1 0 resetsystem interrupt #14 (mid priority)
clear inter rupt #14 whe n 1 is written
5 RegIrqMid[5] r
c1 0 resetsystem interrupt #13 (mid priority)
clear inter rupt #13 whe n 1 is written
4 RegIrqMid[4] r
c1 0 resetsystem interrupt #12 (mid priority)
clear inter rupt #12 whe n 1 is written
3 RegIrqMid[3] r
c1 0 resetsystem interrupt #11 (mid priority)
clear inter rupt #11 whe n 1 is written
2 RegIrqMid[2] r
c1 0 resetsystem interrupt #10 (mid priority)
clear interr upt #10 when 1 is written
1 RegIrqMid[1] r
c1 0 resetsystem interrupt #9 (mid priority)
clear interrupt #9 when 1 is written
0 RegIrqMid[0] r
c1 0 resetsystem interrupt #8 (mid priority)
clear interrupt #8 when 1 is written
Table 8-2: RegIrqMid
pos. RegIrqLow rw reset function
7 RegIrqLow[7] r
c1 0 resetsystem interrupt #7 (low priority)
clear interrupt #7 when 1 is written
6 RegIrqLow[6] r
c1 0 resetsystem interrupt #6 (low priority)
clear interrupt #6 when 1 is written
5 RegIrqLow[5] r
c1 0 resetsystem interrupt #5 (low priority)
clear interrupt #5 when 1 is written
4 RegIrqLow[4] r
c1 0 resetsystem interrupt #4 (low priority)
clear interrupt #4 when 1 is written
3 RegIrqLow[3] r
c1 0 resetsystem interrupt #3 (low priority)
clear interrupt #3 when 1 is written
2 RegIrqLow[2] r
c1 0 resetsystem interrupt #2 (low priority)
clear interrupt #2 when 1 is written
1 RegIrqLow[1] r
c1 0 resetsystem interrupt #1 (low priority)
clear interrupt #1 when 1 is written
0 RegIrqLow[0] r
c1 0 resetsystem interrupt #0 (low priority)
clear interrupt #0 when 1 is written
Table 8-3: RegIrqLow
pos. RegIrqEnHig rw reset function
7 RegIrqEnHig[7] rw 0 resetsystem 1= enable interrupt #23
6 RegIrqEnHig[6] rw 0 resetsystem 1= enable interrupt #22
5 RegIrqEnHig[5] rw 0 resetsystem 1= enable interrupt #21
4 RegIrqEnHig[4] rw 0 resetsystem 1= enable interrupt #20
3 RegIrqEnHig[3] rw 0 resetsystem 1= enable interrupt #19
2 RegIrqEnHig[2] rw 0 resetsystem 1= enable interrupt #18
1 RegIrqEnHig[1] rw 0 resetsystem 1= enable interrupt #17
0 RegIrqEnHig[0] rw 0 resetsystem 1= enable interrupt #16
Table 8-4: RegIrqEnHig
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XE8801A – SX8801R
pos. RegIrqEnMid rw reset function
7 RegIrqEnMid[7] rw 0 resetsystem 1= enable interrupt #15
6 RegIrqEnMid[6] rw 0 resetsystem 1= enable interrupt #14
5 RegIrqEnMid[5] rw 0 resetsystem 1= enable interrupt #13
4 RegIrqEnMid[4] rw 0 resetsystem 1= enable interrupt #12
3 RegIrqEnMid[3] rw 0 resetsystem 1= enable interrupt #11
2 RegIrqEnMid[2] rw 0 resetsystem 1= enable interrupt #10
1 RegIrqEnMid[1] rw 0 resetsystem 1= enable interrupt #9
0 RegIrqEnMid[0] rw 0 resetsystem 1= enable interrupt #8
Table 8-5: RegIrqEnMid
pos. RegIrqEnLow rw reset function
7 RegIrqEnLow[7] rw 0 resetsystem 1= enable interrupt #7
6 RegIrqEnLow[6] rw 0 resetsystem 1= enable interrupt #6
5 RegIrqEnLow[5] rw 0 resetsystem 1= enable interrupt #5
4 RegIrqEnLow[4] rw 0 resetsystem 1= enable interrupt #4
3 RegIrqEnLow[3] rw 0 resetsystem 1= enable interrupt #3
2 RegIrqEnLow[2] rw 0 resetsystem 1= enable interrupt #2
1 RegIrqEnLow[1] rw 0 resetsystem 1= enable interrupt #1
0 RegIrqEnLow[0] rw 0 resetsystem 1= enable interrupt #0
Table 8-6: RegIrqEnLow
pos. RegIrqPriority rw reset function
7-0 RegIrqPriority r 11111111
resetsystem code of highest priority set
Table 8-7: RegIrqPriority
pos. RegIrqIrq rw Reset function
7-3 - r 00000 unused
2 IrqHig r 0 resetsystem one or more high priority interrupt is
set
1 IrqMid r 0 resetsystem one or more mid priority interrupt is
set
0 IrqLow r 0 resetsystem one or more low priority interrupt is
set
Table 8-8: RegIrqIrq
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XE8801A – SX8801R
9 Event Handler
9.1 Features 9-2
9.2 Overview 9-2
9.3 Register map 9-2
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9-2
XE8801A – SX8801R
9.1 Features
The XE8801AM and SX8801R chips supp ort 8 event sources, divided int o 2 le ve ls of priority.
9.2 Overview
A CPU event is generated and memorized when an event source becomes active. The 8 event sources are divided
into 2 levels of priority: High (4 event sources) and Low (4 event sources). Those 2 levels of priority are directly
mapped to tho se supported by th e CoolRisc (EV0 and EV 1; see CoolRisc documentation for more information).
RegEvn is an 8-bit register containing flags for the event sources. Those flags are set when the event is enabled
(i.e. if the corresponding bit in the registers RegEvnEn is set) and a rising edge is detected on the corresponding
event source.
Once memorized, writing a ‘1’ in the corresponding bit of RegEvn clears an event flag. Writing a ‘0’ does not
modify the flag. All interrupts are aut o m atically cleared after a reset.
Two registers are provided to facilitate the writing of event service software. RegEvnPriority contains the number
of the highest priority event set (its value is 0xFF when no event is set). RegEvnEvn indicates the priority level of
the curre nt interrupts. RegEvnEvn and RegEvnPriority ‘s values are dependent upon the memorized state of the
events (as reflected in fla gs in RegEvn).
9.3 Register map
pos. RegEvn rw reset function
7 RegEvn[7] r
c1 0 resetsystem event #7 (high priority)
clear event #7 when written 1
6 RegEvn[6] r
c1 0 resetsystem event #6 (high priority)
clear event #6 when written 1
5 RegEvn[5] r
c1 0 resetsystem event #5 (high priority)
clear event #5 when written 1
4 RegEvn[4] r
c1 0 resetsystem event #4 (high priority)
clear event #4 when written 1
3 RegEvn[3] r
c1 0 resetsystem event #3 (low priority)
clear event #3 when written 1
2 RegEvn[2] r
c1 0 resetsystem event #2 (low priority)
clear event #2 when written 1
1 RegEvn[1] r
c1 0 resetsystem event #1 (low priority)
clear event #1 when written 1
0 RegEvn[0] r
c1 0 resetsystem event #0 (low priority)
clear event #0 when written 1
Table 9-1: RegEvn
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XE8801A – SX8801R
pos. RegEvnEn rw reset function
7 RegEvnEn [7 ] rw 0 resetsystem 1= enable ev en t #7
6 RegEvnEn [6 ] rw 0 resetsystem 1= enable ev en t #6
5 RegEvnEn [5 ] rw 0 resetsystem 1= enable ev en t #5
4 RegEvnEn [4 ] rw 0 resetsystem 1= enable ev en t #4
3 RegEvnEn [3 ] rw 0 resetsystem 1= enable ev en t #3
2 RegEvnEn [2 ] rw 0 resetsystem 1= enable ev en t #2
1 RegEvnEn [1 ] rw 0 resetsystem 1= enable ev en t #1
0 RegEvnEn [0 ] rw 0 resetsystem 1= enable ev en t #0
Table 9-2: RegEvnEn
pos. RegEvnPriority rw reset function
7-0 RegEvnPriority r 11111111
resetsystem code of highest event set
Table 9-3: RegEvnPriority
pos. RegEvnEvn rw reset function
7-2 - r 00000 unused
1 EvnHig r 0 resetsyst em on e or mo re high priority ev ent is set
0 EvnLow r 0 resetsystem one or more low priority event is set
Table 9-4: RegEvnEvn
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XE8801A – SX8801R
10 Low Power RAM
10.1 Features 10-2
10.2 Overview 10-2
10.3 Register map 10-2
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XE8801A – SX8801R
10.1 Features
• Low power RAM locations.
10.2 Overview
In order to save power consumption, 8 8-bit registers are provided in page 0. These memory locations should be
reserved for often-updated variables. Accessing these register locations requires much less power than the other
general purpose RAM loca ti ons.
10.3 Register map
pos. Reg00 rw reset function
7-0 Reg00 rw XXXXXXXX low-power data memory
Table 10-1: Reg00
pos. Reg01 rw reset function
7-0 Reg01 rw XXXXXXXX low-power data memory
Table 10-2: Reg01
pos. Reg02 rw reset function
7-0 Reg02 rw XXXXXXXX low-power data memory
Table 10-3: Reg02
pos. Reg03 rw reset function
7-0 Reg03 rw XXXXXXXX low-power data memory
Table 10-4: Reg03
pos. Reg04 rw reset function
7-0 Reg04 rw XXXXXXXX low-power data memory
Table 10-5: Reg04
pos. Reg05 rw reset function
7-0 Reg05 rw XXXXXXXX low-power data memory
Table 10-6: Reg05
pos. Reg06 rw ¨reset function
7-0 Reg06 rw XXXXXXXX low-power data memory
Table 10-7: Reg06
pos. Reg07 rw reset function
7-0 Reg07 rw XXXXXXXX low-power data memory
Table 10-8: Reg07
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XE8801A – SX8801R
11 Port A
11.1 Features 11-2
11.2 Overview 11-2
11.3 Register map 11-3
11.4 Interrupts and events map 11-4
11.5 Port A (PA) Operation 11-4
11.6 Port A electrical specification 11-5
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11-2
XE8801A – SX8801R
11.1 Features
• Input port, 8 bits wid e
• Each bit can be set individually for debou nce d or direct input
• Each bit can be set individ ua lly for pull-up or not
• Each bit is an interrupt request source on the rising or falling edge
• A system reset can be generated on an input pattern
• PA[0] and PA[1] can generate two events for the CPU, individually maskable
• PA[0] to PA[3] ca n be used as clock inp uts for the co unters/timers/PW M (product depende nt)
• PA[0] can be used t o en able the RC oscillat or
11.2 Overview
Port A is a general p urp ose 8 bit wid e dig i t al in put port, with in te rru pt capability. Figure 11-1 shows its structure.
Figure 11-1:stru ctu re of Port A
VBat
1
0
resetfromporta
8x
RegPAPullup
RegPADebounce
RegPAIn
RegPACtrl
RegPAEdge
RegPARes1
RegPARes0
0
1
8x
1
00
01
11
10
0
interrupts
events
cntclocks
8
8
8
88
debounce
10
DebFast
(RegSysMisc(2)) 256 Hz
8 kHz
8
8
8
Port A
8x
PAReset[x]
RC
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XE8801A – SX8801R
11.3 Register map
There are six registers in the Port A (PA), namely RegPAIn, RegPADebounce, RegPAEdge, RegPAPullup,
RegPARes0 and RegPARes1. Table 11-1 to Tab le 11-6 show the mapping of control bit s and functionality.
pos. RegPAIn rw reset description
7:0 PAIn[7:0] r pad PA[7] to PA[0] input va lue
Table 11-1: RegPAIn
pos. RegPADebounce rw reset description
7:0 PADebounce[7:0] r w 00000000
resetpconf
PA[7] to PA[0]
1: debounce enabled
0: debounce disabled
Table 11-2: RegPADebounce
pos. RegPAEdge rw reset description
7:0 PAEdge[7:0] r w
00000000
resetsystem
PA[7] to PA[0] edge configuration
0: positive edge
1: negative edge
Table 11-3: RegPAEdge
pos. RegPAPullup rw reset description
7:0 PAPullup[7:0] r w
00000000
resetpconf
PA[7] to PA[0] pullup enable
0: pullup disabled
1: pullup enabled
Table 11-4: RegPAPullup
pos. RegPARes0 rw Reset description
7:0 PARes0[7:0] r w
00000000
resetsystem PA[7] to PA[0] reset configuration
Table 11-5: RegPARes0
pos. RegPARes1 rw reset Description
7:0 PARes1[7:0] r w 00000000
resetsystem PA[7] to PA[0] reset configuration
Table 11-6: RegPARes
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11-4
XE8801A – SX8801R
11.4 Interrupts and events map
Interrupt source Default mapping in
the interrupt manager Default mapping in the
event manager
pa_irqbus[5] RegIrqMid[5]
pa_irqbus[4] RegIrqMid[4]
pa_irqbus[1] RegIrqMid[1] RegEvn[4]
pa_irqbus[0] RegIrqMid[0] RegEvn[0]
pa_irqbus[7] RegIrqLow[7]
pa_irqbus[6] RegIrqLow[6]
pa_irqbus[3] RegIrqLow[3]
pa_irqbus[2] RegIrqLow[2]
11.5 Port A (PA) Operat ion
The Port A inp ut st at us (debounced or not ) can be read from RegPAin.
Debounce mode:
Each bit in Port A can be individually debounced by setting the corresponding bit in RegPADebounce. After reset,
the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if
the input value is identical at two consecutive sampling on the rising edge of the selected clock. Selection of the
clock is done by the bit DebFast in Register RegSysMisc (see clock block documentation for more precision on
the frequen cy) .
DebFast Clock filter
0 256 Hz
1 8 kHz
Table 11-7: debounce frequency selection
Figure 11-2: digital debouncer
Pull-ups:
When the corresponding bit in RegPAPullup is set to 0, the inputs are floating (pull-up resistors are disconnected).
When the corresponding bit in RegPAPullup is set to 1, a pull-up resistor is connected to the input pin. Port A
starts up with th e pull-up resistors di sconn ected.
Port A as an inter rup t sou rce:
Each Port A input is an interrupt request source and can be set on rising or falling edge with the corresponding bit
in RegPAEdge. After reset, the rising edge is selected for interrupt generation by default. The interrupt source can
be debounced by setting register RegPADebounce.
Note: care must be taken when modifying RegPAEdge because this register performs an edge selection. The
change of this register may result in a transiti on wh ich may be interpreted as a valid int err uption.
Input
CkDebounce
Debounced 112112
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XE8801A – SX8801R
Port A as an event source:
The interrupt signals of the pins PA[0] and PA[1] are also available as events on the event controller.
PortA as a clock source (product dependent):
Images of the PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the
counter/timer/PWM periphera l (see t he coun te r blo ck docume nt ation for more inf or mation).
Port A as a reset sour ce:
Port A can be used to generate a system reset by placing a predetermined word on Port A externally. The reset is
built using a logical and of the 8 PARes[x] signals:
resetfromportA = PAReset[7] AND PAReset[6] AND P A Re set [5 ] AND ... AND PAReset[0]
PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected
for each pin by writing into two re gisters RegPARes0 and RegPARes1 as shown in Table 11-8 .
PARes1[x] PARes0[x] PAReset[x]
0 0 0
0 1 PA[x]
1 0 not(PA[x])
1 1 1
Table 11-8: Selection bits for reset signal
A reset from Port A can be inhibited by placing a 0 on both PARes1[x] and PARes0[x] for at least 1 pin. Setting
both PARes1[x] and PARes0[x] to 1, makes the reset independent of the value on the corresponding pin. Setting
both registers to hFF, will reset the circuit independent from the Port A input value. This makes it possible to do a
reset by software.
Note: depending of the value of PA[0] to PA[7], the change of RegPARes0 and RegPARes1 can cause a reset.
Therefore it is saf e to hav e always one (RegPARes0 [x], RegPARe s1[x]) equal to ‘00’ during the setting operations.
Port A as a RC enable:
PA[0] can be used to enable the RC oscillator. When RCOnPA0 bit in RegSysMisc is set to 1 and the value of
PA[0] (debounced or not) is equal to 1, the EnRc bit in RegSysClock is automatically set to 1.
11.6 Port A electrical specification
Sym description min typ max unit Comments
VINH Input high voltage 0.7*VBAT VBAT V VBAT≥2.4V
VINL Input low voltage VSS 0.2*VBAT V VBAT≥2.4V
RPU Pull-up resistance 20 50 80 kΩ
Cin Input capacitance 3.5 pF Note 1
Note 1: this value is indicative only since it depends on the package.
Table 11-9. Port A electrical specification.
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XE8801A – SX8801R
12 Port B
12.1 Features 12-2
12.2 Overview 12-2
12.3 Register map 12-2
12.4 Port B capabilities 12-3
12.5 Port B analog capability 12-3
12.5.1 Port B analog configuration 12-3
12.5.2 Por t B an alog function spec ification 12-4
12.6 Port B function capability 12-5
12.7 Port B digital capabilities 12-5
12.7.1 Por t B dig ital con fig uration 12-5
12.7.2 Port B digital function specification 12-6
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XE8801A – SX8801R
12.1 Features
• Input / output / analog port, 8 bits wide
• Each bit can be set individually for input or output
• Each bit can be set individually for open-drain or push-pull
• Each bit can be set individually for pull-up or not (for input or open-drain mode)
• In open-drain mode, pull-up is not active when corresponding pad is set to zero
• The 8 pads can be connected by pairs to four internal analog lines (4 line analog bus)
• Two internal f re q. (cpuck and 32 kHz) can be out put on PB[2] an d PB[3]
Product dep en dant:
• Two PWM signals can be out putted on the pads PB[0] and PB[ 1]
• The synchronous ser i al in te rface (USRT) uses pads PB[5], PB[ 4]
• The UART interface uses pad s P B[6] and PB[7 ] for Tx and Rx
12.2 Overview
Port B is a multi-purpose 8 bit Input/output port. In addition to digital functions, all pins can be used for analog
signals. All port terminals can be selected by pairs as digital input or output or as analog sharing one of four
possible analog lines.
12.3 Register map
Pos. RegPBOut rw reset descripti on in digital mode description in analog mode
7 – 0 PBOut[7-0] r w 0 resetpconf Pad PB[7-0] output value Analog bus selection for pad PB[7-0]
Table 12-1: RegPBOut
Pos. RegPBIn rw reset description in digital mo de description in analog mode
7 – 0 PBIn[7-0] r w Pad PB[7-0] input status Unused
Table 12-2: RegPBIn
Pos. RegPBDir rw reset description in digital mode description in analog mode
7 – 0 PBDir [7-0] r w 0 resetpconf Pad PB[7-0] direction (0=input) Analog bus selection for pad PB[7-0]
Table 12-3: RegPBDir
Pos. RegPBOpen rw reset description in digital mode description in analog mode
7 – 0 PBOpen[7-0] r w 0 resetpconf Pad PB[7-0] open drain (1 = open
drain) Unused
Table 12-4: RegP BOpe n
Pos. RegPBPullup rw reset description in dig i tal mo de description in analog mode
7 –0 PBPullup[7] r w 0 resetpconf Pull-up for pad PB[7-0] (1=active) Connect pad PB[7-0] on selected ana
bus
Table 12-5: RegPBP ullup
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XE8801A – SX8801R
Pos. RegPBAna rw reset description in dig ital mode description in analog mode
7 – 4 -- r 0000 Unused Unused
3 PBAna [3] r w 0 resetpconf Set PB[7:6] in analog mode Set PB[7:6] in analog mode
2 PBAna [2] r w 0 resetpconf Set PB[5:4] in analog mode Set PB[5:4] in analog mode
1 PBAna [1] r w 0 resetpconf Set PB[3:2] in analog mode Set PB[3:2] in analog mode
0 PBAna [0] r w 0 resetpconf Set PB[1:0] in analog mode Set PB[1:0] in analog mode
Table 12-6: RegPBAna
Note: Depending on the status of the EnResPConf bit in RegSysCtrl, the reset conditions of the registers are
differen t . See the reset bl o ck docume ntation for more details on the re setpconf signal.
12.4 Port B capabilities
Port B usage (priority )
name analog
(high) functions
(medium) digital
(low) (default)
PB[7] uart Rx I/O
PB[6] analog uart Tx I/O
PB[5] usrt S1 I/O
PB[4] analog usrt S0 I/O
PB[3] 32 kHz I/O
PB[2] analog clock CPU I/O
PB[1] PWM1 Counter C (C+D) I/O
PB[0] analog PWM0 Counter A (A+B) I/O
Table 12-7: Different Port B functionality
Table 12-7 shows the different usage that can be made of Port B with the order of priority. If a pair of pins is
selected to be analog, it overwrites the function and digital set-up. If the pin is not selected as analog, but a
function is enabled, it overwrites the digital set-up. If neither the analog nor function are selected for a pin, it is used
as an ordinary digital I/O. This is the default configuration at start-up.
12.5 Port B analog capabilit y
12.5.1 Port B analog configuration
Port B terminals can be attached to a 4 line analog bus by setting the PBAna[x] bits to 1 in the RegPBAna
register.
The other registers then define the connection of these 4 analog lines to the different pads of Port B. This can be
used to implement a simple LCD driver or A/D converter. Analog switching is available only when the circuit is
powered with sufficient voltage (see specification below). Below the specified supply voltage, only voltages that are
close to VSS or V BAT can be switched.
When PBAna[x] is set to 1, a pair of Port B terminals is switched from digital I/O mode to analog mode. The usage
of the registers RegPBPullup, RegPBOut and RegPBDir define the analog configura t io n (se e Tab l e 12 -8) .
When PBAna[x] = 1, then PBPullup[x] connects the pin to the analog bus. PBDir[x] and PBPOut[x] select which
of the 4 analog lines is used. For odd values of x, the selection bits are in the register RegPBOut (see Table 12-8).
For even value s of x , the selection bit s are i n th e re gister RegPBDir (see Table 12-9).
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XE8801A – SX8801R
if x is odd, PBOut[x, x-1] PBPullup[x] PB[x] selection on
00 1 analog line 0
01 1 analog line 1
10 1 analog line 2
11 1 analog line 3
XX 0 High impedance
Table 12-8: Select io n of th e analog lines for PB[x] when x is odd and PBAna[x] = 1
if x is even, PBDir[x+1, x] PBPullup[x] PB[x] selection on
00 1 analog line 0
01 1 analog line 1
10 1 analog line 2
11 1 analog line 3
XX 0 High impedance
Table 12-9: Selection of the ana l og li nes f or PB[x] whe n x is even and PBAna[x] = 1
Example:
Set the pads PB[2] and PB[3] on the analog line 3. (the values X depend on the configuration of others
pads)
- apply high impedance in the analog mode (move RegPBPullup,#0bXXXX00XX)
- go to analog mode (move RegP BAna,#0bXXX XXX1X)
- select the analog line3 (mov e RegPBDir,#0bXXXX11XX and move RegPBOut,#0b XXXX11XX)
- connect the analog line t o the pins (move RegP BP ullup,#0bX XXX11XX)
12.5.2 Port B analog function specification
The table below defines the on-resistance of the switches between the pin and the analog bus for different
conditions. The series resistance between 2 pins of Port B connected to the same analog line is twice the
resistance given i n th e table.
sym description min typ max unit Comments
Ron switch resistance 11 kΩ Note 1
Ron switch resistance 15 kΩ Note 2
Cin input capacitance (off) 3.5 pF Note 3
Cin input capacitance (on) 4.5 pF Note 4
Table 12-10. Analo g input specif ica tio ns.
Note 1: This is the series re sista nce b et ween the pad and th e analog line in 2 cases
1. VBAT ≥ 2.4V and the VMULT peripheral is present on the ci rcuit and enabled.
2. VBAT ≥ 3.0V and the VMULT peripheral is not presen t on the circuit.
Note 2: This is the series resistance in case VBAT ≥ 2.8V and the peripheral VMULT is not present on the circuit.
Note 3: This is the input capacitance seen on the pin when the pin is not connected to an analog line. This value is
indicati v e only since it is product a nd package depende nt .
Note 4: This is the input capacitance seen on the pin when the pin is connected to an analog line and no other pin
is connected to the same analog line. This v alu e is ind i cat i v e on ly si nce it is prod uct and packag e de pe nd ent .
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XE8801A – SX8801R
12.6 Port B function capability
The Port B can be used for different functions implemented by other peripherals. The description below is
applicable only i n so fa r the circuit cont ain s the se peripherals.
When the counters are used to implement a PWM function (see the do cumentation of the cou nters) , the PB[0] and
PB[1] terminals are used as outputs (PB[0] is used if CntPWM0 in RegCntConfig1 is set to 1, PB[1] is used if
CntPWM1 in RegCntConfig1 is set to 1) and the PWM generated values overwrite the values written in
RegPBout. However, PBDir(0) and PBDir(1) are not automatically overwrit te n and have to be set to 1.
If OutputCkXtal is set in RegSysMisc, the Xtal clock is output on PB[3] (EnableXtal in RegSysClock must be set
to 1). This overrides the value contained in PBOut(3). However, PBDir(3) must be set to 1. The duty cycle of the
clock signal is about 50 %.
Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value
contained in PBOut(2). However, PBDir(2) must be set to 1.
The frequency of the CPU clock depends on the selection of the CpuSel bit in the RegSysClock register (see
clock_gen_ff).
Pins PB[5] and PB[4] can be used for S1 and S0 of the USRT (see USRT documentation) when the UsrtEnable bit
is set in RegUsrtCtrl. The PB[5] and PB[4] then become open-drain. This overrides the values contained in
PBOpen(5:4), PBOut(5:4) and PBDir(5:4). If there is no external pull-up resistor on these pins, internal pull-ups
should be selected by setting PBPullup(5:4). When S0 is an output, the pin PB[4] takes the value of UsrtS0 in
RegUrstS0. When S1 is an output, the pin PB[5] takes the value of UsrtS1 in RegUrstS1.
Pins PB[6] and PB[7] can be used by the UART (see UART documentation). When UartEnTx in RegUartCtrl is set
to 1, PB[6] is used as output signal Tx. When UartEnRx in RegUartCtrl is set to 1, PB[7] is used as input signal
Rx. This overrides the values cont ained in PBOut(7:6) and PBDir(7:6).
12.7 Port B digital capabilities
12.7.1 Port B digital configuration
The direction of each bit within Port B (input only or input/output) can be individually set using the RegPBDir
register. If PBDir[x] = 1, both the input and output buffer are active on the corresponding Port B. If PBDir[x] = 0,
the corresponding Port B pin is an input only and the output buffer is in high impedance. After reset (resetpconf)
Port B is in input only mode (PBDir[x] are reset to 0).
The input values of Port B are available in RegPBIn (read only). Reading is always direct - there is no debounce
function in Port B. In case of possible noise on input signals, a software debouncer with polling or an external
hardware filter have to be realized. The input buffer is also active when the port is defined as output and allows to
read back the effective valu e on the pin.
Data stored in RegPBOut are output at Port B if PBDir[x] is 1. The default value after reset is low (0).
When a pin is in output mode (PBDir[x] is set to 1), the output can be a conventional CMOS (Push-Pull) or a N-
channel Open-drain, driving the output only low. By default, after reset (resetpconf) the PBOpen[x] in RegPBOpen
is cleared to 0 (push-pull). If PBOpen[x] in RegPBOpen is set to 1 then the int er nal P transistor in the output buffer
is electrically removed and the output can only be driven low (PBOut[x]=0). When PBOut[x]=1, the pin is high
Impedance. The internal pull-up or an external pull- up resist or can be use d to driv e t he pin high .
Note: Because the P transistor actually exists (this is not a real Open-drain output) the pull-up range is limited to
VDD + 0.2V (avoid fo rwar d bia s t he P tr ansistor / diode).
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XE8801A – SX8801R
Each bit can be set individually for pull-up or not using register RegPBPullup. Input is pulled up when its
corresponding bit in this register is set to 1. Default status after (resetpconf) is 0, which means without pull up. To
limit power consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an N-
channel open-drain output with the pad set to 1. In the other cases (push-pull output or open-drain output driven
low), the pull up resistors are disabled indep end en t of the value in RegPBPullup.
After powe r-o n reset, the P ort B is configured as an inpu t port without pull-up.
The input buffer is always active, except in analog mode. This means that the Port B input should be a valid digital
value at all times unle ss th e pin is set in an alo g mo de. Violating th is rule may lea d to hig h power consumption.
12.7.2 Port B digital function specification
Sym description min typ max unit Comments
VINH Input high voltage 0.7*VBAT VBAT V VBAT≥2.4V
VINL Input low voltage VSS 0.2*VBAT V VBAT≥2.4V
VOH Output high voltage VBAT-0.4
VBAT V VBAT=1.2V, IOH =0.3mA
VBAT=2.4V, IOH =5.0mA
VBAT=4.5V, IOH =8.0mA
VOL Output low voltage VSS
VSS+0.4 V VBAT=1.2V, IOL =0.3mA
VBAT=2.4V, IOL
=12.0mA
VBAT=4.5V, IOL
=15.0mA
RPU Pull-up resistance 20 50 80 kΩ
Cin Input capacitance 3.5 pF Note 1
Note 1: this value is indicative only since it depends on the package.
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13-1
XE8801A – SX8801R
13 Port C
13.1 Features 13-2
13.2 Overview 13-2
13.3 Port C (PC) Operation 13-2
13.4 Register map 13-3
13.5 Port C electrical specification 13-3
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13-2
XE8801A – SX8801R
13.1 Features
• Input / outpu t port, 8 bits wide
• Each bit can be set individually for inp ut or output
13.2 Overview
Port C (PC) is a gene ra l pur pose 8 bit input/o ut pu t digital port.
Figure 13-1 shows its structure.
Figure 13-1 : structure of Port C
13.3 Port C (PC) Operat ion
The direction of each bit within Port C (input or output) can be individually set by using the RegPCDir register. If
PCDir[x] = 1, the corresponding Port C pin becomes an output. After reset, Port C is in input mode (PCDir[x] are
reset to 0).
Output mode:
Data is stored in RegPCOut prior t o ou tput at Port C.
Input mode:
The status of Port C is available in RegPCIn (read only). Reading is always direct - there is no digital debounce
function associated with Port C. In case of possible noise on input signals, a software debouncer or an external
filter must be realized.
By default after reset, Port C is configured as an input port.
RegPCIn
RegPCOut
RegPCDir
8
8
8
Port C
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XE8801A – SX8801R
13.4 Register map
There are three registers in the Port C (PC), namely RegPCIn, RegPCOut and RegPCDir. Table 13-1 to Table
13-3 show the mapp ing of con trol bits and f unct i o nality of these registers.
Pos. RegPCIn Rw Reset Description
7-0 PCIn r - pad PC input value
Table 13-1 RegPCIn
Pos. RegPCOut Rw Reset Description
7-0 PCOut r w 0 resetpconf pad PC output value
Table 13-2 RegPCOut
Pos. RegPCDir Rw Reset Description
7-0 PCDir r w 0 resetpconf p ad PC direction (0=input)
Table 13-3 RegPCDir
13.5 Port C electrical specification
Sym description min typ max unit Comments
VINH Input high voltage 0.7*VBAT VBAT V VBAT≥2.4V
VINL Input low voltag e VSS 0.2*VBAT V VBAT≥2.4V
VOH Output high voltage VBAT-0.4
VBAT V VBAT=1.2V, IOH =0.3mA
VBAT=2.4V, IOH =5.0mA
VBAT=4.5V, IOH =8.0mA
VOL Output low voltage VSS
VSS+0.4 V VBAT=1.2V, IOL =0.3mA
VBAT=2.4V, IOL
=12.0mA
VBAT=4.5V, IOL
=15.0mA
Cin Input capacitance 3.0 pF Note 1
Note 1: this value is indicative only since it depends on the package.
Table 13-4. Port C electrical specif icat ion
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14-1
XE8801A – SX8801R
14 UART
14.1 Features 14-2
14.2 Overview 14-2
14.3 Registers map 14-2
14.4 Interrupts map 14-3
14.5 Uart baud rate sele ction 14-3
14.5.1 Uart on the RC oscillator 14-3
14.5.2 Uart on the crystal oscillator 14-4
14.6 Function description 14-4
14.6.1 Configuration bits 14-4
14.6.2 Transmission 14-5
14.6.3 Reception 14-6
14.7 Interrupt or polling 14-6
14.8 Software hints 14-7
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XE8801A – SX8801R
14.1 Features
• Full duplex operation with buffered receiver and transmitter.
• Internal baud rate generator with 12 programmable baud rates (300 - 11 5200).
• 7 or 8 bits word length.
• Even, odd, or no-parity bit generation and det ection
• 1 stop bit
• Error receive detection: Start, Pa rity, Frame an d Ov errun
• Receiver echo mode
• 2 interrupts (receive full and transmit empty)
• Enable receive and/or transmit
• Invert pad Rx and/or Tx
14.2 Overview
The UART pins are PB[7], which is used as Rx - receive and PB[6] as Tx - transmit.
14.3 Registers map
pos. RegUartCmd rw Reset Description
7 SelXtal rw 0 resetsystem Select input clock: 0 = RC/external, 1 = xtal
6 UartEnRx2 rw 0 resetsystem Enable Uart Reception
5-3 UartRcSel(2:0) rw 000 resetsyst em RC prescaler selection
2 UartPM rw 0 resetsystem Select pa rit y mode: 0 = odd, 1 = even
1 UartPE rw 0 resetsystem Enable parity: 1 = with parity, 0 = no parity
0 UartWL rw 1 resetsystem Select word length: 1 = 8 bits, 0 = 7 bits
Table 14-1: RegUartCmd
Pos. RegUartCtrl rw reset Description
7 UartEcho rw 0 resetsystem Enable echo mode:
1 = echo Rx->Tx, 0 = no echo
6 UartEnRx1 rw 0 resetsystem Enable uart reception
5 UartEnTx rw 0 resetsystem Enable uart tran smission
4 UartXRx rw 0 resetsystem Invert pad Rx
3 UartXTx rw 0 resetsystem Invert pad Tx
2-0 Uart BR( 2: 0) rw 101 resetsystem Select baud rate
Table 14-2: Re gUartCtrl
pos. RegUartTx rw reset Description
7-0 UartTx rw 00000000
resetsystem Data to be sent
Table 14-3: RegUartTx
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XE8801A – SX8801R
pos. RegUartTxSta rw reset description
7-2 - r 000000 Unused
1 UartTxBusy r 0 resetsystem Uart busy transmitt ing
0 UartTxFull r 0 resetsystem RegUartTx full
Set by writing to RegUartTx
Cleared when tran sferring RegUartTx into
internal shift register
Table 14-4: RegUartTxSta
pos. RegUartRx rw reset description
7-0 UartRx r 00000000
resetsystem Received data
Table 14-5: RegUartRx
pos. RegUartRxSta rw Reset description
7-6 - r 00 Unused
5 UartRxSErr r 0 resetsystem Start error
4 UartRxPErr r 0 resetsystem Parity error
3 UartRxFErr r 0 resetsystem Frame error
2 UartRxOErr rc 0 resetsystem Overrun error
Cleared by writin g RegUartRxSta
1 UartRxBusy r 0 resetsystem Uart busy receiving
0 UartRxFull r 0 resetsystem RegUartRx full
Cleared by reading RegUartRx
Table 14-6: RegUartRxSta
14.4 Interrupts map
interrupt source default mapping in the interrupt manager
Irq_uart_Tx IrqHig(1)
Irq_uart_Rx IrqHig(0)
Table 14-7: Interrupts map
14.5 Uart baud rate selection
In order to have correct baud rates, the Uart interface has to be fed with a stable and trimmed clock source. The
clock source can be the RC oscillator or the crystal oscillator. The precision of the baud rate will depend on the
precision of the selected cloc k source.
14.5.1 Uart on the RC oscillator
To select the RC oscillator for the Uart, the bit SelXtal in RegUartCmd has to be 0.
In order to obtain a correct baud rate, the RC oscillator frequency has to be set to one of the frequencies given in
the table below. The precision of the obtained baud rate is directly proportional to the frequency deviation with
respect to the values in the table.
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XE8801A – SX8801R
Frequency selection for correct Uart
baud rate with RC oscill ator (Hz)
2’457’600
1’843’200
1’228’800
614’400
For each of these frequencies, the baud rate can be selected with the bits UartBR(2:0) in RegUartCtrl and
UartRcSel(2:0) in RegUartCmd as shown in Table 14-8
RC frequency (Hz) 2’457’600 1’228’800 614’400 1’843’200
UartRcSel 010 001 000 000
111 38400 115200
110 19200 57600
101 9600 28800
UartBR
100 Not possible 4800 14400
Table 14-8: Uart baud rate with RC clock
Note: The precision of the baud rate is directly proportional to the frequency deviation of the used clock from the
ideal frequency given in the table. In order to increase the precision and stability of the RC oscillator, the DFLL
(digital frequency locked loop) can be used with the crystal oscillator as a reference.
14.5.2 Uart on the crystal oscillator
In order to use the crystal oscillator as the clock source for the Uart, the bit SelXtal in RegUartCmd has to be set.
The crystal oscillator has to be enabled by setting the EnableXtal bit in RegSysClock. The baud rate selection is
done using the UartBR and UartRcSel bits as shown in Table 14-9.
Xtal freq. (Hz) UartRcSel UartBR Baud rate
011 2400
010 1200
001 600
32768 001
000 300
Table 14-9: Uart baud rate with Xtal clock
Due to the odd ratio between the crystal oscillator frequency and the baud rate, the generated baud rate has a
systematic error of –2.48%.
14.6 Function description
14.6.1 Configuration bits
The configuration bits of the Uart serial interface can be found in the registers RegUartCmd and RegUartCtrl.
The bit SelXtal is used to select the clock source (see chapter 14.5). The bits UartSelRc and UartBR select the
baud rate (see chapter 14.5).
The bit UartEnTx is used to enable or disable the transmission.
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XE8801A – SX8801R
The bits UartEnRx1 and UartEnRx2 are used to enable or disable the reception. When one is set to 1, the
reception is enabled.
The word length (7 or 8 data bits) can be chosen with UartWL. A par ity bit is added during transmission or checked
during recept io n if UartPE is set. The parity mode (o dd or even) can be chosen wit h UartPM.
Setting the bi ts UartXRx and UartXTx inverts the Rx respectively Tx signals.
The bit UartEcho is used to send the received data automatically back. The transmission function becomes then:
Tx = Rx XOR UartXTx.
14.6.2 Transmission
In order to send data, the transmitter has to be enabled by setting the bit UartEnTx. Data to be sent has to be
written to the register RegUartTx. The bit UartTxFull in RegUartTxSta then goe s to 1, indi ca ting to the tr ans mitter
that a new word is available. As soon as the transmitter has finished sending the previous word, it then loads the
contents of the register RegUartTx to an internal shift register and clears the UartTxFull bit. An interrupt is
generated on Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows
that the tran smitter is bus y transmittin g a word.
A timing diagram is shown in Figure 14-1. Data are sent LSB first.
New data shoul d be written to the reg iste r RegUartTx only while UartTxFull is 0, otherwise data will be lost.
Asynchronous Transmission
write to RegUartTx
Re
g
UartTx word 1
reg ua rt tx _shift w o rd 1
shift clock
Tx start b0 b1 b6/7 parity stop
UartTxBus
y
UartTxFull
Irq_uart_Tx
Asynchronous Transmission (back to back)
word 1 word 2
write to RegUartTx
Re
g
UartTx word 1 word 2
reguarttx_shift word 1 word 2
shift clock
Tx start b0 b6/7 stop start
UartTxBus
y
UartTxFull
Irq_uart_Tx
Figure 14-1. Uart tr an sm ission timing diagram.
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14-6
XE8801A – SX8801R
14.6.3 Reception
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are
transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set
and an interrupt is generated on Irq_uart_Rx. This indicates that new data is available in RegUartRx. The timing
diagram is shown in Figure 14- 2.
The UartRxFull bit is clear ed when RegUartRx is read. If the register was not read before the receiver transfers a
new word to it, the bit UartRxOErr (overflow error) is set and the previous contents of the register is lost.
UartRxOErr is cleared by writing any dat a to RegUartRxSta.
The bit UartRxSErr is set if a start err or has been detecte d. The bit is updated at data tra nsfer to RegUartRx.
The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the
calculated parity of the received data. The bit is updated at data transfer to RegUartRx.
The bit UartRxFErr in RegUartRxSta shows that a frame error has be en detected. No stop bit has been detected.
Asynchronous Reception
read o f R egUartRx (software)
reguartrx_shift word 1
RegUartRx word 1
shift clock
Rx start b0 b6/7 parity stop
UartRxBusy
UartRxFull
Irq_uart_Rx
Figure 14-2. Uart rece pt ion timing diagram.
14.7 Interrupt or polling
The transmission and recep tion software can be driven by interruption or by polling the status bits.
Interrupt driven reception: each time an Irq_uart_Rx interrupt is generated, a new word is available in RegUartRx.
The register has to be read before a new wo rd is rece ived.
Interrupt driven transmission: each time the contents of RegUartTx is transferred to the transmission shift register,
an Irq_uart_Tx interrupt is generat ed. A new word can t hen be written to RegUartTx.
Reception driven by polling: the UartRxFull bit is to be read and checked. When it is 1, the RegUartRx register
contains new data and has to be read before a new word is received.
Transmission driven by polling: the UartTxFull bit is to read and checked. When it is 0, the RegUartTx register is
empty and a new word can be written to it.
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XE8801A – SX8801R
14.8 Software hints
Example of pro gra m fo r a transmission with polling :
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart transmission).
2. Write a byte to RegUartTx.
3. Wait until the UartTxFull bit in RegUartTxSta register equals 0.
4. Jump to 2 to write the next byte if the message is not finished.
5. End of transmission.
Example of program for a tran smission wi th interrupt:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart transmission).
2. Write a byte to RegUartTx.
3. After an interrupt and if the message is not fi nish ed , ju mp to 2
4. End of transmission.
Example of program for a reception with polling:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart recep tio n).
2. Wait until the UartRxFull bit in the RegUartRxSta register equals 1.
3. Read the RegUartRxSta and check if there is no error.
4. Read data in RegUartRx.
5. If data is not equal to End-Of-Line, then jump to 2.
6. End of reception.
Example of program for a recept io n with interrupt:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart recep tio n).
2. When there is an interrupt, jump to 3
3. Read RegUartRxSta and check i f there is no error.
4. Read data in RegUartRx.
5. If data is not equal to End-Of-Line, then jump to 2.
6. End of reception.
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15-1
XE8801A – SX8801R
15 USRT
15.1 Features 15-2
15.2 Overview 15-2
15.3 Register map 15-2
15.4 Interrupts map 15-3
15.5 Conditional edge detection 1 15-4
15.6 Conditional edge detection 2 15-4
15.7 Interrupts or polling 15-4
15.8 Function description 15-5
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XE8801A – SX8801R
15.1 Features
The USRT implements a hardware support for software implemented serial protocols:
• Control of two external lines S0 and S1 (re ad /wr i te ).
• Conditional edge de te ctio n ge ne rates interrupts.
• S0 rising edge detection.
• S1 value is stored on S 0 risi ng edge.
• S0 signal can be forced to 0 after a falling edge on S0 for clock stretching in the low state.
• S0 signal can be stret ched i n th e low state after a falling edge on S0 an d after a S1 conditional detect ion .
15.2 Overview
The USRT block supports software universal synchronous receiv er and t ra nsmit t er mo de interfaces.
External lines S0 and S1 respectively correspond to clock line and data line. S0 is mapped to PB[4] and S1 to
PB[5] when the USRT block is enabled. It is independent from RegPBdir (Port B can be input or output). When
USRT is enabled, the configurations in port B for PB[4] and PB[5] are overwritten by the USRT configuration.
Interna l pull-ups can be used by setting th e PBPullup[5:4] bits.
Conditional edge detections are prov id ed .
RegUsrtS1 can be used to read the S1 data line from PB[5] in receive mode or to drive the output S1 line PB[5] by
writing it when in transmit mode. It is advised to read S1 data when in receive mode from the RegUsrtBufferS1
register, which is th e S1 va lue sample d on a risin g edg e of S0.
15.3 Register map
Block configuration registers:
pos. RegUsrtS1 rw reset function
7-1 - r 0000000 Unused
0 UsrtS1 rw 1 resetsystem Write: data S1 written to pad PB[5]),
Read: value on PB[5] (not UsrtS1 value).
Table 15-1: RegUsrtS1
pos. RegUsrtS0 rw Reset function
7-1 - r 0000000 Unused
0 UsrtS0 rw 1 resetsystem Write: clock S0 writte n t o pa d PB[4],
Read: value on PB[4] (not UsrtS0 value).
Table 15-2: RegUsrtS0
The values that are read in the registers RegUsrtS1 and RegUsrtS0 are not necessarily the same as the values
that were written in the register. The read value is read back on the circuit pins, not in the registers. Since the
outputs are o pen drain, a value different fr om the register value may be forced by an external circu it on the circuit
pins.
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XE8801A – SX8801R
pos. RegUsrtCtrl rw reset function
7-4 - r “0000” Unused
3 UsrtWaitS0 r 0 resetsyst em Clock stretching flag (0=no stretching),
cleared by writing RegUsrtBufferS1
2 UsrtEnWaitCond1 rw 0 resetsystem Enable stretching on UsrtCond1 detection
(0=disable)
1 UsrtEnWaitS0 rw 0 resetsystem Enable stretching operatio n (0=disable)
0 UsrtEnable rw 0 resetsystem Enable USRT operation (0=disable)
Table 15-3: RegUsrtCtrl
pos. RegUsrtCond1 rw reset function
7-1 - r 0000000 Unused
0 UsrtCond1 r/c 0 resetsystem State of condition 1 detection (1 =detected),
cleared when written.
Table 15-4: RegUsrtCond1
pos. RegUsrtCond2 rw reset function
7-1 - r 0000000 Unused
0 UsrtCond2 r/c 0 resetsystem State of condition 2 detection (1 =detected),
cleared when written.
Table 15-5: RegUsrtCond2
pos. RegUsrtBufferS1 rw reset function
7-1 - r 0000000 Unused
r Value on S1 at last S0 rising edg e.
Clear RegUsrtEdgeS0 bit in RegUsrtEdgeS0
0 UsrtBufferS1 w x Clear UsrtWaitS0 bit in RegUsrtCtrl with any
value
Table 15-6: RegUsrtBufferS1
pos. RegUsrtEdgeS0 rw reset function
7-1 - r 0000000 Unused
0 UsrtEdgeS0 r 0 resetsystem State of rising edge detection on S0
(1=detected). Cleared by reading
RegUsrtBufferS1
Table 15-7: RegUsrtEdgeS0
15.4 Interrupts map
interrupt
source default mapping in the interrupt manager
Irq_cond1 RegIrqMid(7)
Irq_cond2 RegIrqMid(6)
Table 15-8: I nt err up ts map
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XE8801A – SX8801R
15.5 Conditional edge detection 1
S1
S0
Figure 15-1: Condition 1
Condition 1 is satisfied when S0=1 at the falling edge of S1. The bit UsrtCond1 in RegUsrtCond1 is set when the
condition 1 is detected and the USRT interface is enabled (UsrtEnable=1). Condition 1 is asserted for both modes
(receiver and transmitter). The UsrtCond1 bit is r ead only and is c leared by all r eset conditions an d by writing a ny
data to its address.
Condition 1 occurr ence also generates an interrupt on Irq_cond1.
15.6 Conditional edge detection 2
S1
S0
Figure 15-2: Condition 2
Condition 2 is satisfied when S0=1 at the rising edge of S1. The bit UsrtCond2 in RegUsrtCond2 is set when the
condition 2 is detected and the USRT interface is enabled. Condition 2 is asserted for both modes (receiver and
transmitter). The UsrtCond2 bit is read only and is cleared by all reset conditions and by writing any data to its
address.
Condition 2 occurre nce al so ge nerates an interr upt on Irq_cond2 .
15.7 Interrupts or polling
In receive mode, there are two possibilities to detect condition 1 or 2: the detection of the condition can generate
an interrupt or the registers can be polled (reading and checking the RegUsrtCond1 and RegUsrtCond2 registers
for the status of USRT communication).
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XE8801A – SX8801R
15.8 Function description
The bit UsrtEnable in RegUsrtCtrl is used to enable the USRT interface and controls the PB[4] and PB[5] pins.
This bit puts th ese t wo port B lines in the open drain config ura tion request ed t o use t he USRT int erface.
If no external pull-ups are added on PB[4] and PB[5], the user can activate internal pull-ups by setting PBPullup[4]
and PBPullup[5] in RegPBPullup.
The bits UsrtEnWaitS0, UsrtEnWaitCond1, UsrtWaitS0 in RegUsrtCtrl are used for transmitter/receiver control
of USRT interf ace.
Figure 15-3 shows the unco nd i tional clock stretching function which is enabled by setting UsrtEnWaitS0.
S0
UsrtWaitS0
write RegUsrtBufferS1
Figure 15-3: S0 St retching (UsrtE nWa i t S 0 =1)
When UsrtEnWaitS0 is 1, the S0 line will be maintained at 0 after its falling edge (clock stretching). UsrtWaitS0 is
then set to 1, indicating that the S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1
register.
The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4
shows the conditional clock stretching function which is enable d by setting UsrtEnWaitCond1.
S0
UsrtWaitS0
write RegUsrtBufferS1
S1
Figure 15-4: Condit ional stretching (UsrtEnWaitCond1=1)
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XE8801A – SX8801R
When UsrtEnWaitCond1 is 1, the S0 signal will be stretched in its low state after its falling edge if the condition 1
has been detected before (UsrtCond1=1). UsrtWaitS0 is then set to 1, indicating that the S0 line is forced low.
One can release S0 by writing to the RegUsrtBufferS1 register.
Figure 15-5 shows the sampling function implemented by the UsrtBufferS1 bit. The bit UsrtBufferS1 in
RegUsrtBufferS1 is the value of S1 sampled on PB[4] at the last rising edge of S0. The bit UsrtEdgeS0 in
RegUsrtEdgeS0 is set to one on the same S0 rising edge and is cleared by a read operation of the
RegUsrtBufferS1 register. The bit therefor indicates that a new value is present in the RegUsrtBufferS1 which
was not yet read.
S0
UsrtBufferS1
read RegUsrtBufferS1
S1
UsrtEdgeS0
Figure 15-5: S1 sampling
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16-1
XE8801A – SX8801R
16. Acquisition Chain
16.1 ZoomingADC™ Features .......................................... ....................... ...................... ....................... ......16-2
16.2 Overview..............................................................................................................................................16-2
16.3 Register map .......................................................................................................................................16-3
16.4 ZoomingADC™ Description.......................................... ....................... .............................................. .16-4
16.4.1 Acquisition Chain ................................................................................................................... ...............16-4
16.4.2 Peripheral Registers..............................................................................................................................16-6
16.4.3 Continuous-Time vs. On-Request.........................................................................................................16-7
16.5 Input Multiplexers ...............................................................................................................................16-8
16.6 Programmable Gain Amplifiers ..........................................................................................................16-9
16.6.1 PGA & ADC Enabling..........................................................................................................................16-10
16.6.2 PGA1..................................................................................................................................................16-10
16.6.3 PGA2..................................................................................................................................................16-11
16.6.4 PGA3..................................................................................................................................................16-11
16.7 ADC Characteristics .........................................................................................................................16-12
16.7.1 Conversion Sequence.........................................................................................................................16-12
16.7.2 Sampling Frequency...........................................................................................................................16-12
16.7.3 Over-Sampling Ratio...........................................................................................................................16-13
16.7.4 Elementary Conversions.....................................................................................................................16-13
16.7.5 Resolution...........................................................................................................................................16-14
16.7.6 Conversion Time & Throughput ................................................................................................. .........16-15
16.7.7 Output Code Format ...........................................................................................................................16-15
16.7.8 Power Saving Modes..........................................................................................................................16-17
16.8 Specifications and Measured Curves..............................................................................................16-17
16.8.1 Default Settings...................................................................................................................................16-17
16.8.2 Specifications......................................................................................................................................16-18
16.8.3 Linearity ............................................................................................................................. .................16-20
16.8.3.1 Integral non-linearity............................................................................................................................16-20
16.8.3.2 Differential non-linearity ............................................................................................................. .........16-23
16.8.4 Noise...................................................................................................................................................16-24
16.8.5 Gain Error and Offset Error.................................................................................................................16-25
16.8.6 Power Consumption................................................................................................................... .........16-26
16.8.7 Power Supply Rejection Ratio......................................................................................................... ....16-28
16.9 Application Hints...............................................................................................................................16-29
16.9.1 Input Impedance.................................................................................................................................16-29
16.9.2 PGA Settling or Input Channel Modifications.......................................................................................16-29
16.9.3 PGA Gain & Offset, Linearity and Noise........ ..... .... ..... .... ......... ..... ..... .... ......... ..... .... ..... ......... .............16-29
16.9.4 Frequency Response..........................................................................................................................16-30
16.9.5 Power Reduction............................................................................................................................. ....16-31
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XE8801A – SX8801R
16.1 ZoomingADC™ Features
The ZoomingADC™ is a complete and versatile low-power analog front-end interface typically intended for sensing
applications. The key features of the ZoomingADC™ are:
Programmable 6 to 16-bit dynamic range oversampled ADC
• Flexible gain programming between 0.5 and 1000
• Flexible and large range offset compensation
• 4-c ha nnel differential or 8-channel single-ended input multiplexer
• 2-c ha nnel differential ref erence inputs
• Power saving modes
• Direct interfacing to CoolRisc™ microcon t r ol l er
16.2 Overview
PGA1 PGA2 PGA3
ADC
MUX
MUX
GD1 GD2 GD3
OFF2 OFF3
0
1
2
3
4
5
6
7
0
1
2
3
Analog
Inputs
16
V
IN
f
S
V
REF
V
IN,ADC
Gain1 Gain2 Gain3
Offset3Offset2
Reference
Selection
Input
Selection
ZOOM
Reference
Inputs
V
D1
V
D2
f
S
Figure 16-1. ZoomingADC™ general functional block diagram
The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an
oversampled A/D converter. The reference voltage can be selected on two different channels. Two offset
compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset allow one to
zoom in on a small portion of the reference voltage defined input range.
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16.3 Register map
There are eight registers in the acquisition chain (AC), namely RegAcOutLsb, RegAcOutMsb, RegAcCfg0,
RegAcCfg1, RegAcCfg2, RegAcCfg3, RegAcCfg4 and RegAcCfg5. Table 16-2 to Table 16-9 show the mapping
of control bits and functionality of these registers while Table 16-1 gives an overview of these eight.
The register map only gives a short description of the different configuration bits. More detailed information is found
in subsequent sections.
register name
RegAcOutLsb
RegAcOutMsb
RegAcCfg0
RegAcCfg1
RegAcCfg2
RegAcCfg3
RegAcCfg4
RegAcCfg5
Table 16-1: AC registers
pos. RegAcOutLsb rw reset description
7:0 Out[7:0] r
00000000
resetsystem LSB of the output code
Table 16-2: RegAcOutLsb
pos. RegAcOutMsb rw reset description
7:0 Out[15:8] r
00000000
resetsystem MSB of the output code
Table 16-3: RegAcOutMsb
pos. RegAcCfg0 rw reset description
7 Start w r0 0 resetsystem starts a conversion
6:5 SET_NELCONV[1:0] r w 01 resetsystem sets the number of elementary conversions
4:2 SET_OSR[2:0] r w 010 resetsystem
sets the oversampling rate of an elementary
conversion
1 CONT r w 0 resetsystem continuous conversion mode
0 reserved r w 0 resetsystem
Table 16-4: RegAcCfg0
pos. RegAcCfg1 rw reset description
7:6 IB_AMP_ADC[1:0] r w 11 resetsystem Bias current selection of the ADC converter
5:4 IB_AMP_PGA[1:0] r w 11 resetsystem Bias current selection of the PGA stages
3:0 ENABLE[3:0] r w
0000
resetsystem Enables the different PGA stages and the ADC
Table 16-5: RegAcCfg1
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pos. RegAcCfg2 rw reset description
7:6 FIN[1:0] r w 00 resetsystem Sampling frequency selection
5:4 PGA2_GAIN[1:0] r w 00 resetsystem PGA2 stage gain selection
3:0 PGA2_OFFSET[3:0] r w
0000
resetsystem PGA2 stage offset selection
Table 16-6: RegAcCfg2
pos. RegAcCfg3 rw reset description
7 PGA1_GAIN r w 0 resetsystem PGA1 stage gain selection
6:0 PGA3_GAIN[6:0] r w 0000000
resetsystem PGA3 stage gain selection
Table 16-7: RegAcCfg3
pos. RegAcCfg4 rw reset description
7 reserved r 0 Unused
6:0 PGA3_OFFSET[6:0] r w 0000000
resetsystem PGA3 stage offset selection
Table 16-8: RegAcCfg4
pos. RegAcCfg5 rw reset description
7 BUSY r 0 resetsystem Activity flag
6 DEF w r0 0 Selects default configuration
5:1 AMUX[4:0] r w 00000
resetsystem Input channel confi gu rat i on sele c tor
0 VMUX r w 0 resetsystem Reference channel selector
Table 16-9: RegAcCfg5
16.4 ZoomingADC™ Description
Figure 16-2 gives a more detailed description of the acquisition chain.
16.4.1 Acquisition Chain
Figure 16-1 shows the general block diagram of the acquisition chain (AC). A control block (not shown in Figure
16-1) manages all communications with the CoolRisc™ microcontroller.
Analog inputs can be selected among eight input channels, while reference input is selected between two differential
channels.
The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of a
combination of input and reference signals VIN and VREF, the input voltage is modulated and amplified through stages
1 to 3. Fine gain programming up to 1'000V/V is possible. In addition, the last two stages provide programmable
offset. Each amplifier can be bypassed if needed.
The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal
VIN,ADC into digital.
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Like most ADCs intended for instrumentation or sensing applications, the ZoomingADC™ is an over-sampled
converter (See Note1). The ADC is a so-called incremental converter, with bipolar operation (the ADC accepts both
positive and negative input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers
the qu a ntit y:
2/2/
,
REF
ADCIN
ADC V
V
FS
OUT ≅ (Eq. 1)
in two's complement (see Sections 16.4 and 16.7 for details). The output code OUTADC is -FS/2 to +FS/2 for VIN,ADC ≅
-VREF/2 to +VREF/2 respectively. As will be shown in section 16.6, VIN,ADC is related to input voltage VIN by the
relationship:
REFTOTINTOTADCIN VGDoffVGDV ⋅−⋅=
, (V) (Eq. 2)
where GDTOT is the total PGA gain, and GDoffTOT is the total PGA offset.
PGA1 PGA2 PGA3
ADC
MUX
Register Bank
Acquisition Chain
GD1 GD2 GD3
OFF2 OFF3
0
1
2
3
4
5
6
7
0
1
2
3
AC_A
AC_R
RegACOutLSB
RegACOutMSB
8
8
Sampling Frequency f
S
ADC Busy Flag
Default Settings
Conversion Start
Nbr of Elementary Cycles
Over-Sampling Ratio
Continuous vs. On-Request
Power Saving Modes
PGA Enabling
RegACCfg5
RegACCfg4
RegACCfg3
RegACCfg2
RegACCfg1
RegACCfg0
5 2 4 7 7
Inputs
V
IN
f
S
V
REF
V
IN,ADC
f
S
MUX
Figu r e 16-2. Zo om ingAD C ™ detailed functional block diagram
1 Note: Over-sampled converters are operated with a sampling frequency fS much higher than the input signal's Nyquist rate (typically fS is 20-
1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital
decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications.
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16.4.2 Peripheral Registers
Figure 16-2 shows a detailed functional diagram of the ZoomingADC™. In
Table 16-10 the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit registers:
six registers are used to configure the acquisition chain (RegAcCfg0 to 5), and t wo reg is ter s a re u sed to s t ore t he
output code of the analog-to-digital conversion (RegAcOutMsb & Lsb). The regist er coding of the ADC parameters
and performance characteristics are detailed in Section 16.7.
Table 16-10. Peripheral registers to configure the acquisition chain (AC)
and to store the analog-to-digital conversion (ADC) result
Bit Position
Register
Name 7 6 5 4 3 2 1 0
RegAcOutLsb OUT[7:0]
RegAcOutMsb OUT[15:8]
RegAcCfg0
Default
values:
STAR
T
0
SET_NELC[1:0]
01 SET_OSR[2:0]
010 CONT
0 TEST
0
RegAcCfg1
Default
values:
IB_AMP_ADC[
1:0]
11
IB_AMP_PGA[1:
0]
11
ENABLE[3:0]
0001
RegAcCfg2
Default
values:
FIN[1:0]
00 PGA2_GAIN[1:0]
00 PGA2_OFFSET[3:0]
0000
RegAcCfg3
Default
values:
PGA1
_G
0
PGA3_GAIN[6:0]
0000000
RegAcCfg4
Default
values:
0 PGA3_OFFSET[6:0]
0000000
RegAcCfg5
Default
values:
BUSY
0 DEF
0 AMUX[4:0]
00000 VMUX
0
With:
• OUT: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
• START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads
back 0.
• SET_NELC: (rw) sets the number of elementary conversions to 2SET_NELC[1:0] . To compensate for offsets, the
input signal is chopped between elementary conversions (1,2,4,8).
• SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]) . OSR = 8, 16,
32, ..., 512, 1024.
• CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit
remains at 1.
• TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten.
• IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation
current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
• IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the norm al operation
current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
• ENABLE: (rw) enables the ADC modulator (bit 0) and the dif ferent stages of the PGAs (PGAi by bit i=1,2,3). PGA stag es that
are disabled are bypassed.
• FIN: (rw) These bits set the sampling frequenc y of the acq uisition chain. Express ed as a fraction of the oscill ator frequenc y,
the sampling frequency is given as: 00 Æ 1/4 fRC, 01 Æ 1/8 fRC, 10 Æ 1/32 fRC, 11Æ ~8kHz.
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• PGA1_GAIN: (rw) sets the gain of the first stage: 0 Æ 1, 1 Æ 10.
• PGA2_GAIN: (rw) sets the gain o f the second stage: 00 Æ 1, 01 Æ 2, 10 Æ 5, 11 Æ 10.
• PGA3_GAIN: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]⋅1/12.
• PGA2_OFFSET: (rw) sets the offse t of the second stage between –1 and +1, with incre ments of 0.2. The MSB gives the sign
(0 → positive, 1 → negative) ; ampli t ude is cod ed with the bits PGA2_OFFSET[5:0].
• PGA3_OFFSET: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the
sign (0 → positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0].
• BUSY: (r) set to 1 if a conversion is running. Note that the flag is set at the effective start of the conversion. Since the ADC is
generally synchronized on a lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC
sampling frequency) between the writing of the START or CONT bits and the appearance of BUSY flag.
• DEF: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary
conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one.
• AMUX(4:0): (rw) AMUX[4] sets the mode (0 Æ 4 dif ferent ial inputs, 1 Æ 7 inputs with A(0) = common reference) AMUX(3)
sets the sign (0 Æ straight, 1Æ cross) AMUX[2:0] sets the channel.
• VMUX: (rw) sets the differential reference channel (0 Æ R(1) and R(0), 1 Æ R(3) and R(2)).
(r = read; w = writ e; rw = re ad & writ e)
16.4.3 Continuous-Time vs. On-Request
The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit
CONT).
In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new
one is automatically initiated. The new value is then written in the result register, and the corresponding internal
trigger pulse is generated. This operation is sketched in Figure 16-3. The convers ion time in this case is defined as
TCONV.
Internal Trig
Ouput Code
RegACOut[15:0]
T
CONV
BUSY
IRQ
Figure 16-3. ADC "continuous-time" operation
Figure 16-4. ADC "on-request" operation
In the "on-request" mode, the internal behaviour of t he converter is the same as in the " continuous-time" mode, but
the conversion is initiated on user request ( with the START bit). As shown in Figure 16-4, the conversion time is also
TCONV. Note that the flag is set at the effective start of the conversion. Since the ADC is generally synchronized on a
lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC sampling frequency)
between the writing of the START or CONT bits and the appearance of BUSY flag.
Intern al Trig
Ouput Code
RegACOut[15:0]
TCONV
Request
START
BUSY
IRQ
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16.5 Input Multiplexers
The ZoomingADC™ has eight analog inputs AC_A(0) to AC_A(7) and four r efer ence in puts AC_R(0) to AC_R(3).
Let us first define the differential input voltage VIN and reference voltage VREF respectively as:
INNINPIN VVV −= (V) (Eq. 3)
and:
REFNREFPREF VVV −= (V) (Eq. 4)
As shown in Table 16-11 the inputs can be configured in two ways: either as 4 differential channels (VIN1 = AC_A(1)
- AC_A(0),..., VIN4 = AC_A(7) - AC_A(6)), or AC_A(0) can be used as a common reference, providing 7 signal
paths all referred to AC_A(0). The control word for the analog input selection is AMUX[4:0]. Notice that the bit
AMUX[3] controls the sign of the input voltage.
AMUX[4:0]
(RegAcCfg5[5:1]) VINP V
INN AMUX[4:0]
(RegAcCfg5[5:1]) VINP V
INN
00x00
00x01
00x10
00x11
AC_A(1)
AC_A(3)
AC_A(5)
AC_A(7)
AC_A(0)
AC_A(2)
AC_A(4)
AC_A(6)
01x00
01x01
01x10
01x11
AC_A(0)
AC_A(2)
AC_A(4)
AC_A(6)
AC_A(1)
AC_A(3)
AC_A(5)
AC_A(7)
10000
10001
10010
10011
10100
10101
10110
10111
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_A(0)
11000
11001
11010
11011
11100
11101
11110
11111
AC_A(0)
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
Table 16-11. Analog input selection
Similarly, the reference voltage is chosen among two differential channels (VREF1 = AC_R(1)-AC_R(0) or VREF2 =
AC_R(3)-AC_R(2)) as shown in Table 16-12. The selection bit is VMUX. The reference inputs VREFP and VREFN
(common-mode) can be up to the power supply range.
VMUX
(RegAcCfg5[0]) VREFP V
REFN
0 AC_R(1) AC_R(0)
1 AC_R(3) AC_R(2)
Table 16-12. Analog Reference input selection
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16.6 Programmable Gain Amplifiers
As seen in Figure 16-1, the zooming function is implemented with t hree programmable gain amplifiers (PGA). These
are:
• PGA1: coarse gain tuning
• PGA2: medium gain and offset tuning
• PGA3: fine gain and offset tuning
All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and
gain, as well as the offset of stages 2 and 3. These functions are examined hereafter.
ENABLE[3:0] Block
xxx0
xxx1 ADC dis abl ed
ADC enabled
xx0x
xx1x PGA1 disabled
PGA1 enabled
x0xx
x1xx PGA2 disabled
PGA2 enabled
0xxx
1xxx PGA3 disabled
PGA3 enabled
Table 16-13 ADC & PGA enabling
PGA1_GAIN PGA1 Gain
GD1 (V/V)
0 1
1 10
Table 16-14 PGA1 Gain Settings
PGA2_GAIN[1:0] PGA2 Gain
GD2 (V/V)
00 1
01 2
10 5
11 10
Table 16-15 PGA2 gain settings
PGA2_OFFSET[3:0] PGA2 Offset
GDoff2 (V/V)
0000 0
0001 +0.2
0010 +0.4
0011 +0.6
0100 +0.8
0101 +1
1001 -0.2
1010 -0.4
1011 -0.6
1100 -0.8
1101 -1
Table 16-16 PGA2 offset settings
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PGA3_GAIN[6:0] PGA3 Gain
GD3 (V/V)
0000000 0
0000001 1/12(=0.083)
... ...
0000110 6/12
... ...
0001100 12/12
0010000 16/12
...
0100000 32/12
...
1000000 64/12
...
1111111 127/12(=10.58)
Table 16-17 PGA3 gain settings
PGA3_OFFSET[6:0] PGA3 Offset
GDoff3 (V/V)
0000000 0
0000001 +1/12(=+0.083)
0000010 +2/12
... ...
0010000 +16/12
... ...
0100000 +32/12
... ...
0111111 +63/12(=+5.25)
1000000 0
1000001 -1/12(=-0.083)
1000010 -2/12
... ...
1010000 -16/12
... ...
1100000 -32/12
... ...
1111111 -63/12(=-5.25)
Table 16-18 PGA3 offset settings
16.6.1 PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to
the word ENABLE and the coding given in Table 16-13. To reduce power dissipation, the ADC can also be inactivated
while idle.
16.6.2 PGA1
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 16-14). The voltage VD1 at
the output of PGA1 is:
IND VGDV ⋅= 11 (V) (Eq. 5)
where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN.
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16.6.3 PGA2
The second PGA has a finer gain and offset tuning capability, as shown in Table 16-15 and Table 16-16. The voltage
VD2 at the output of PGA2 is given by:
REFDD VGDoffVGDV ⋅−⋅= 2122 (V) (Eq. 6)
where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words
PGA2_GAIN[1:0] and PGA2_OFFSET[3:0].
As shown in equation 6, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
16.6.4 PGA3
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table
16-17 and Table 16-18. The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the
voltage entering the ADC is given by:
REFDADCIN VGDoffVGDV ⋅−⋅= 323, (V) (Eq. 7)
where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are
PGA3_GAIN[6:0] and PGA3_OFFSET[6:0] . To remain within the signal compliance of the PGA stages, the
condition:
DDDD VVV <
21 , (V) (Eq. 8)
must be verified.
As shown in equation 7, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
Finally, combining equations Eq. 5 to Eq. 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related
to VIN by:
REFTOTINTOTADCIN VGDoffVGDV ⋅−⋅=
, (V) (Eq. 9)
where the total PGA gain is defined as:
123 GDGDGDGDTOT ⋅⋅= (V/V) (Eq. 10)
and the total PGA offset is:
233 GDoffGDGDoffGDoffTOT ⋅+= (V/V) (Eq. 11)
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16.7 ADC Characteristics
The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three
programmable parameters. The setting of these parameters and the resulting performances are described later.
• sampling frequency fS,
• over-sampling ratio OSR, and
• number of elementary conversions NELCONV.
16.7.1 Conversion Sequence
A conversion is started each time the bit START or the bit DEF is se t. As de pict ed in Figu re 16- 5, a compl ete an alo g-
to-digital conversion sequence is made of a set of NELCONV elementary incremental conversions and a final
quantization step. Each elementary conversion is made of (OSR+1) sampling periods TS=1/fS, i.e.:
SELCONV fOSRT /)1( += (s) (Eq. 12)
The result is the mean of the elementary conversion results. An important feature is that the elementary conversions
are al ternativ ely performed with the offset of the int ernal amplifiers contributing in one direction and the ot her to the
output code. Thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.e. if
NELCONV ≥ 2). A few additional clock cycles are also required to initiate and end the conversion properly.
Conversion index
Offset
TELCONV= (OSR+1)/fS
Elementary
Conversion
1
+
Elementary
Conversion
2
-
Elementary
Conversion
NELCONV
- 1
+
Elementary
Conversion
NELCONV
-
Init End
TCONV
Conversion
Result
Figure 16-5 Analog-to-digital conversion sequence
16.7.2 Sampling Frequency
The word FIN[1:0] is used to select the sampling frequency fS (Table 16-19). Three sub-multiples of the internal
RC-based frequency fRCEXT can be chosen. For FIN = "11", sampling freq uency is about 8k Hz. Additional information
on oscillators and their control can be found in the clock block documentation.
Sampling Frequency fS (Hz)
FIN[1:0] XE8801A, SX8801
and XE8805A XE8802
00 1/4⋅fRC 1/8⋅fRCEXT
01 1/8⋅fRC 1/16⋅fRCEXT
10 1/32⋅fRC 1/64⋅fRCEXT
11 ∼8kHz ∼4kHz
Table 16-19 Sampling frequency settings (fRC or fRCEXT i s the RC oscillator frequency)
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16.7.3 Over-Sampling Ratio
The over-sampling ratio (OSR) defines the number of integration cycles per elementary conversion. Its value is set
with the word SET_OSR[2:0] in power of 2 steps (see Table 16-20) given by:
0]:SET_OSR[23
2+
=OSR (-) (Eq. 13)
SET_OSR[2:0]
(RegAcCfg0[4:2])
Over-Sampling Ratio
OSR (-)
000 8
001 16
010 32
011 64
100 128
101 256
110 512
111 1024
Table 16-20 Over-sampling ratio settings
16.7.4 Elementary Conversions
As mentioned previously, the whole conversion sequence is made of a set of NELCONV elementary incremental
conversions. This number is set with the word SET_NELC[1:0] in power of 2 steps (see Table 16-21) given by:
0]:SET_NELC[1
2=
ELCONV
N (-) (Eq. 14)
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SET_NELC[1:0]
(RegAcCfg0[6:5])
# of Elementary
Conversions
NELCONV (-)
00 1
01 2
10 4
11 8
Table 16-21 Number of elementary conversion settings
As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier offsets.
16.7.5 Resolution
The theoretical resolution of the ADC, without considering thermal noise, is given by:
)(log)(log2 22 ELCONV
NOSRn +⋅= (Bits) (Eq. 15)
5
7
9
11
13
15
17
000 001 010 011 100 101 110 111
SET
_
OSR
Resolution - n [Bits]
11
10
01
00
SET
_
NELC=
Figure 16-6 Resolution vs. SET_OSR[2:0] and SET_NELC[2:0]
SET_NELC
SET_OS
R
[2:0] 00 01 10 11
000 6 7 8 9
001 8 9 10 11
010 10 11 12 13
011 12 13 14 15
100 14 15 16 16
101 16 16 16 16
110 16 16 16 16
111 16 16 16 16
(shaded area: resolution truncated to 16 bits
due to output register size RegAcOut[15:0])
Table 16-22 Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] settings
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Using look-up Table 16-22 or the graph plotted in Figure 16-6, resolution can be set between 6 and 16 bits. Notice
that , beca use o f 16-bit r e gister us e f o r t he ADC output , pr actical resolution is limited to 16 bits, i.e. n ≤ 16. Even if
the resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and NELCONV to higher
values in order to reduce the influence of the thermal noise in the PGA (see section 16.8.4).
16.7.6 Conversion Time & Throughput
As ex plai ned using Figure 16-5, conv ersion time is given by:
SELCONVCONV fOSRNT /)1)1(( ++⋅= (s) (Eq. 16)
and throughput is then simply 1/TCONV. For example, consider an over-sampling ratio of 256, 2 elementary
conversions, and a sampling frequency of 500kHz (SET_OSR = "101", SET_NELC = "01", fRC = 2MHz, and FIN =
"00"). In this case, using Table 16-23, the conversion time is 515 sampling periods, or 1.03ms. This corresponds to a
throughput of 971Hz in continuous-time mode. The plot of Figure 16-7 illustrates the classic trade-off between
resolution and co nversion tim e.
SET_NELC[1:0] SET_OSR
[2:0] 00 01 10 11
000 10 19 37 73
001 18 35 69 137
010 34 67 133 265
011 66 131 261 521
100 130 259 517 1033
101 258 515 1029 2057
110 514 1027 2053 4105
111 1026 2051 4101 8201
Table 16-23 Normalized conversion time (TCONV
⋅
fS) vs. SET_OSR[2:0] and SET_NELC[1:0](normalized
to sampling period 1/fS)
4.0
6.0
8.0
10.0
12.0
14.0
16.0
10.0 100.0 1000.0 10000.0
Normalized Conversion Time - T
CONV
*f
S
[-]
Resolution - n [Bits]
00
SET_NELC
01 10 11
Figure 16-7 Resolution vs. normalized conversion time for different SET_NELC[1:0]
16.7.7 Output Code Format
The ADC output code is a 16-bit word in two's complement format (see Table 16-24). For input voltages outside the
range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller
than 16 bits, the non-significant bits are forced to the values shown in Table 16-25. The output code, expressed in
LSBs, corresponds to:
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XE8801A – SX8801R
OSR
OSR
V
V
OUT
REF
ADCIN
ADC 1
2,
16 +
⋅⋅= (LSB) (Eq.17)
Recalling equation Eq. 9, this can be rewritten as:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛⋅−⋅⋅=
IN
REF
TOTTOT
REF
IN
ADC V
V
GDoffGD
V
V
OUT 16
2 OSR
OSR 1
+
⋅ (LSB) (Eq. 18)
where, from Eq. 10 and Eq. 11, the total PGA gain and offset are respectively:
123 GDGDGDGDTOT ⋅⋅= (V/V)
and:
233 GDoffGDGDoffGDoffTOT ⋅+= (V/V)
ADC In put
Voltage
VIN,ADC
% of
Full
Scale
(FS)
Output in
LSBs
Output
Code
in Hex
+2.49505V +0.5⋅FS +215-1
=+32'767 7FFF
+2.49497V ... +215-2
=+32'766 7FFE
... ... ... ...
+76.145µV ... +1 0001
0V 0 0 0000
-76.145µV ... -1 FFFF
... ... ... ...
-2.49505V ... -215-1
=-32'767 8001
-2.49513V -0.5⋅FS -215
=-32'768 8000
Table 16-24. Basic ADC Relationships (example for: VREF = 5V, OSR = 512, n = 16 bits)
SET_OS
R
[2:0] SET_NELC = 00 SET_NELC = 01 SET_NELC = 10 SET_NELC = 11
000 1000000000 100000000 10000000 1000000
001 10000000 1000000 100000 10000
010 100000 10000 1000 100
011 1000 100 10 1
100 10 1 - -
101 - - - -
110 - - - -
111 - - - -
Table 16-25. Last forced LSBs in conversion output registers for resolution settings smaller than 16
bits (n < 16) (RegAcOutMsb[7:0] & RegAcOutLsb[7:0])
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The equivalent LSB size at the input of the PGA chain is:
1
2
1
+
⋅⋅= OSR
OSR
GD
V
LSB
TOT
REF
n (V) (Eq. 19)
Notice that the input voltage VIN,ADC of the ADC must satisfy the condition:
1
)(
2
1
,+
⋅−⋅≤ OSR
OSR
VVV REFNREFPADCIN (V) (Eq. 20)
to remain within the ADC input range.
16.7.8 Power Saving Modes
During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the
control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0] (see Table 16-26). If the system is idle, the PGAs and
ADC can even be disabled, thus, reducing power consumption to its minimum. This can considerably improve
battery lifetime.
IB_AMP_ADC
[1:0]
IB_AMP_PGA
[1:0] ADC
Bias
Current
PGA
Bias
Current
Max. fS
[kHz]
00
01
10
11
x
1/4⋅IADC
1/2⋅IADC
3/4⋅IADC
IADC
x
62.5
125
250
500
x
00
01
10
11
x
1/4⋅IPGA
1/2⋅IPGA
3/4⋅IPGA
IPGA
62.5
125
250
500
Table 16-26. ADC & PGA power saving modes and maximum sampling frequency
16.8 Specifications and Measured Curves
This section presents measurement results for the acquisition chain. A summary table with circuit specifications and
meas u red cur ves ar e gi v e n .
16.8.1 Default Settings
Unless other wise specified, the meas urement conditions are the following:
• Temperature TA = + 25°C
• VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V
• RC frequency fRC = 2MHz, sampling frequency fS = 500kHz
• Offsets GDOff2 = GDOff3 = 0
• Power oper ation: nor m al (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '11')
• Resolut ion: for n = 12 bits: OSR = 32 and NELCONV = 4
for n = 16 bits: OSR = 512 and NELCONV = 2
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16.8.2 Specifications
Unless otherwise specified: Temperature TA = +25°C, VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V, RC frequency fRC = 2MHz, sampling frequency
fS = 500kHz , Overall PGA gain GDTOT = 1, offsets GDOff2 = GDOff3 = 0. Power operation : normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] =
'11'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2.
VALUE
PARAMETER MIN TYP MAX
UNITS COMMENTS/CONDITIONS
ANALOG INPUT
CHARACTERISTICS
Differential Input Voltage Ranges
VIN = (VINP - VINN)
Reference Voltage Range
V
REF = (VREFP – VREFN)
-2.42
-24.2
-2.42
+2.42
+24.2
+2.42
VDD
V
mV
mV
V
Gain = 1, OSR = 32 (Note 1)
Gain = 100, OSR = 32
Gain = 1000, OSR = 32
PROGRAMMABLE GAIN
AMPLIFIERS (PGA)
Total PGA Gain, GDTOT
PGA1 Gain, GD1
PGA2 Gain, GD2
PGA3 Gain, GD3
Gain Setting Precision (each stage)
Gain Temp erature Dependence
Offset
PGA2 Offset, GDoff2
PGA3 Offset, GDoff3
Offset Setting Precision (PGA2 or 3)
Offset Temperature Dependence
Input Impedance
PGA1
PGA2, PGA3
Output RMS Noise
PGA1
PGA2
PGA3
0.5
1
1
0
-3
-1
-127/12
-3
1500
150
150
±0.5
±5
±0.5
±5
205
340
365
1000
10
10
127/12
+3
+1
+127/12
+3
V/V
V/V
V/V
V/V
%
ppm/°C
V/V
V/V
%
ppm/°C
kΩ
kΩ
kΩ
µV
µV
µV
See Table 16-14
See Table 16-15
Step=1/12 V/V, See Table 16-17
Step=0.2 V/V, See Table 16-16
Step=1/12 V/V, See Table 16-18
(Note 2)
PGA1 Gain = 1 (Note 3)
PGA1 Gain = 10 (Note 3)
Maximal g ain (Note 3)
(Note 4)
(Note 5)
(Note 6)
ADC STATIC PERFORMANCE
Resolution, n
No Missing Codes
Gain Error
Offset Error
Integral Non-Linearity, INL
Resolution n = 16 Bits
Differential Non-Linearity, DNL
Resolution n = 16 Bits
Power Suppl y Rejection Ratio, PSRR
6
±0.15
±1
±1.0
±0.5
78
72
16
Bits
% of FS
LSB
LSB
LSB
dB
dB
(Note 7)
(Note 8)
(Note 9)
n = 16 bits (Note 10)
(Note 11)
(Note 12)
VDD = 5V ± 0.3V (Note 13)
VDD = 3V ± 0.3V (Note 13)
DYNAMIC PER FORMANCE
Sampling Frequency, fS
Conversion Time, TCONV
Throughput Rate (Continuous Mode),
1/TCONV
Nbr of Initialization Cycles, NINIT
Nbr of End Conversion Cycles, NEND
PGA Stabilization Delay
3
0
0
133
1027
3.76
0.49
OSR
2
5
kHz
cycles/fS
cycles/fS
kSps
kSps
cycles
cycles
cycles
n = 12 bits (Note 14)
n = 16 bits (Note 14)
n = 12 bits, fS = 500kHz
n = 16 bits, fS = 500kHz
(Note 15)
DIGIT AL OUTPUT
ADC Output Data Coding
Binary Two’s Complement
See Table 16-24 and Table
16-25
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XE8801A – SX8801R
Specifications (Cont’d)
VALUE
PARAMETER MIN TYP MAX
UNITS COMMENTS/CONDITIONS
POWER SUPPLY
Voltage Supply Range, VDD
Analog Quiescent Current
Consumption, Total (IQ)
ADC Only
PGA1
PGA2
PGA3
Analog Power Dissipation
Normal Power Mode
3/4 Power Reduction Mode
1/2 Power Reduction Mode
1/4 Power Reduction Mode
+2.4
+5
720/620
250/190
165/150
130/120
175/160
3.6/1.9
2.7/1.4
1.8/0.9
0.9/0.5
+5.5
V
µA
µA
µA
µA
µA
mW
mW
mW
mW
Only Acquisition Chain
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
All PGAs & ADC Active
VDD = 5V/3V (Note 16)
VDD = 5V/3V (Note 17)
VDD = 5V/3V (Note 18)
VDD = 5V/3V (Note 19)
TEMPERATURE
Specified Range
Operating Range
-40
-40
+85
+125
°C
°C
Notes:
(1) Gain defined as overall PGA gain GDTOT = GD1⋅GD2⋅GD3. Maximum input voltage is given by:
VIN,MAX = ±(VREF/2)⋅(OSR/OSR+1).
(2) Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
(3) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS =
512kHz. This figure must be multiplied by 2 for fS = 256kHz, 4 for fS = 128kHz. Input impedance is proportional to 1/fS.
(4) Figure independent from PGA1 gain and sampling frequency fS. See model of Figure 16-18(a).
See equation Eq. 21 to calculate equivalent input noise.
(5) Figure independent on PGA2 gain and sampling frequency fS. See model of Figure 16-18(a). See equation Eq. 21 to calculate
equivalent input noise.
(6) Figure independent on PGA3 gain and sampling frequency fS. See model of Figure 16-18(a) and equation Eq. 21 to calculate
equivalent input noise.
(7) Resolution is given by n = 2⋅log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1,
2, 4 or 8.
(8) If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
(9) Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function
(with the offset error removed). (See Figure 16-19)
(10) Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For ± 1 LSB offset, NELCONV must be ≥2.
(11) INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds
over the full scale.
(12) DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
(13) Figures for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage
changes.
(14) Conversion time is given by: TCONV = (NELCONV ⋅ (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can
be set to 1, 2, 4 or 8.
(15) PGAs are reset after each writing operation to registers RegAcCfg1-5. The ADC must be started after a PGA or inputs common-mode
stabilisation delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching. Delay between
PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This delay
does not apply to conversions made without the PGAs.
(16) Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = ‘11’ and IB_AMP_ADC[1:0] = ‘11’.
(17) Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘10’, IB_AMP_ADC[1:0] = ‘10’.
(18) Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘01’, IB_AMP_ADC[1:0] = ‘01’.
(19) Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘00’, IB_AMP_ADC[1:0] = ‘00’.
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16.8.3 Linearity
16.8.3.1 Integral non-linearity
The integral non-linearity depends on the selected gain configuration. First of all, the non-linearity of the ADC (all
PGA s tages bypas sed ) is s hown in Figu re 16-8.
Figure 16-8 Integral non-linearity of the ADC (PGA disabled, reference voltage of 4.8V)
The different PGA stages have been designed to find the best compromise between the noise performance, the
integral non-linearity and the power consumption. To obtain t his, the first stage has the best noise performance and
the thir d stage the best li nearity perfo rmance. F or l arge input signals (small P GA gains, i.e. up to about 50), th e noise
added by the PGA is very small with respec t t o the input signal and the second a nd third stage of the PGA should be
used to get the best linearity. For small input signals (large gains, i.e. above 50), the noise level in the PGA is
important and the first stage of the PGA should be used.
The following figures give the non-linearity for different gain settings of the PGA, selecting the appropriate stage to
get the best noise and linearity performance. Figure 16-9 shows the non-linearity when the third stage is used with a
gain of 1. It is of course not very useful to use the PGA with a gain of 1 unless it is used to compensate offset. By
increasing the gain, the integral non-linearity becomes even smaller since the signal in the amplifiers reduces.
Figure 16-10 shows the non-linearity for a gain of 2. Figure 16-11 shows the non-linearity for a gain of 5. Figure
16-12 shows the non-linearity for a gain of 10. By comparing these figures to Figure 16-8, it can be seen that the
third stage of the PGA does not add significant integral non-linearity.
Figure 16-13 shows the non-linearity for a gain of 20 and Figure 16-14 shows the non-linearity for a gain of 50. In
both cases the PGA2 is used at a gain of 10 and the remaining gain is realized by the third stage. It can be seen
again that the second stage of the PGA does not add significant non-linearity.
For gains above 50, the first stage PGA1 should be selected in stead of PGA2. Although the non-linearity in the first
stage of the PGA is larger than in stage 2 and 3, the gain in stage 3 is now sufficiently high so that the non-linearity
of the first stage does become negligible as is shown in Figure 16-15 for a gain of 100. Therefor, the first stage is
preferred over the second stage since it has less noise.
Increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the
first two stages. The signal is full scale at the output of stage 3 and as shown in Figure 16-9 to Figure 16-12, this
stage has very good linearity.
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Figure 16-9 Integral non-linearity of the ADC and with gain of 1 (PGA1 and PGA2 disabled, PGA3=1,
reference voltage of 5V)
Figure 16-10 Integral non-linearity of the ADC and gain of 2 (PGA1 and PGA2 disabled, PGA3=2
reference voltage of 5V)
Figure 16-11 Integral non-linearity of the ADC and gain of 5 (PGA1 and PGA2 disabled, PGA3=5,
reference voltage of 5V)
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Figure 16-12 Integral non-linearity of the ADC and gain of 10 (PGA1 and PGA2 disabled, PGA3=10,
reference voltage of 5V)
Figure 16-13 Integral non-linearity of the ADC and gain of 20 (PGA1 and PGA2=10, PGA3=2, reference
voltage of 5V)
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Figure 16-14 Integral non-linearity of the ADC and gain of 50 (PGA1 disabled, PGA2=10, PGA3=5,
reference voltage of 5V)
Figure 16-15 Integral non-linearity of the ADC and gain of 100 (PGA1=10 and PGA3=10, PGA2 disabled,
reference voltage of 5V)
16.8.3.2 Differential non-linearity
The differential non-li nearity is generated by the ADC. The PGA does not add differential non-linearity. Figure 16-16
shows the differential non-linearity.
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Figure 16-16 Differential non-linearity of the ADC converter.
16.8.4 Noise
Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the
output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions for
a constant input voltage was performed to derive the equivalent noise levels of PGA1, PGA2, and PGA3. The
extracted rms output noise of PGA1, 2, and 3 are given in Table 16-27: standard output deviation and output rms
noise voltage. Figure 16-17 shows the distribution for the ADC alone (PG A1, 2, and 3 b ypassed). Quantizat ion noise
is dominant in this case, and, thus, the ADC thermal noise is below 16 bits.
The simple noise model of Figure 16-18(a) is used to estimate the equivalent input referred rms noise VN,IN of the
acquisition chain in the model of Figure 16-18(b). This is given by the relationship:
)(
))/(())/(()/( 2
3213
2
212
2
11
2
,ELCONV
NNN
INN NOSR
GDGDGDVGDGDVGDV
V⋅
⋅⋅+⋅+
= (V2rms) (Eq. 21)
where VN1, VN2, and VN3 are the output rms noise figures of Table 16-27, GD1, GD2, and GD3 are the PGA gains of
stages 1 to 3 respectively. As shown in this equation, noise can be reduced by increasing OSR and NELCONV
(increases the ADC averaging effect, but reduces noise).
Parameter PGA1 PGA2 PGA3
Standard deviation at
ADC output (LSB) 0.85 1.4 1.5
Output rms noise (µV) 1 205 (VN1) 340 (VN2) 365 (VN3)
Note: see noise model of Figure 16-18 and equation Eq. 21.
Table 16-27 PGA noise measurements (n = 16 bits, OSR = 512, NELCONV = 2, VREF = 5V)
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0
20
40
60
80
-5 -4 -3 -2 -1 0 1 2 3 4 5
Output Code Deviation From Mean Value [LSB]
Occurences
[% of total samples]
Figure 16-17 ADC noise (PGA1, 2 & 3 bypassed, OSR=512,NELCONV=2)
PGA1 PGA2 PGA3
ADC
GD1 GD2 GD3
V
N1
f
S
V
N2
V
N3
(a)
PGA1 PGA2 PGA3
ADC
GD1 GD2 GD3
V
N,IN
f
S
(b)
Figure 16-18 (a) Simple noise model for PGAs and ADC
and (b) total input referred noise
As an example, consider the system where: GD2 = 10 (GD1 = 1; PGA3 bypassed), OSR = 512, NELCONV = 2, VREF =
5V. In this case, the nois e contribution VN1 of PGA1 is dominant over that of PGA2. Using equation Eq. 21, we get:
VN,IN = 6.4µV (rms) at the input of the acquisition chain, or, equivalently, 0.85 LSB at the output of the ADC.
Considering a 0.2V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB.
Noise can also be reduced by implementing a software filter. By making an average on a number of subsequent
measurements, the apparent noise is reduced the square root of the number of measurement used to make the
average.
16.8.5 Gain Error and Offset Error
Gain error is defined as the amount of deviation between the ideal transfer function (theoretical equation Eq. 18) and
the measured transfer function (with the offset error removed).
The actual gain of the different stages can vary depending on the fabrication tolerances of the different elements.
Although these tolerances are specified to a maximum of ±3%, they will be most of the time around ±0.5%.
Moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error
in the same direction in all stages is very low. Finally, these gain errors can be calibrated by the software at the same
time with the gain errors of the sensor for instance.
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Figure 16-19 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of Full-
Scale Range (FSR) norma lized to 25°C.
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC
and the PGA1 stage are completely suppressed if NELCONV > 1.
The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 16-20. The output
offset error, expressed in LSB for 16-bit setting, is normalized to 25°C. Notice that if the ADC is used alone, the
output offs e t erro r is be lo w ±1 LSB and has no drift.
NORMALIZED TO 25°C
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
-50 -25 0 25 50 75 100
Temperature [°C]
Ga in Error [% of FSR]
1
5
20
100
Figure 16-19 Gain error vs. tem perature f or dif fere nt PGA gains
NORMALIZED TO 25°C
-40
-20
0
20
40
60
80
100
-50 -25 0 25 50 75 100
Temperat u re [°C ]
Output Offset Error [LSB ]
1
5
20
100
Figure 16-20 Offset error vs. temperature for different PGA gains
16.8.6 Power Consumption
Figu re 16- 21 plo ts t he vari ati on of quies cent c urre nt co nsumpt ion with supply volt age V DD, as wel l as the distr ibutio n
between the 3 PGA stages and the ADC (see Table 16-28). As shown in Figure 16-22, if lower sampling frequency is
used, the quiescent current consumption can be lowered by reducing the bias currents of the PGAs and the ADC
with registers IB_AMP_PGA [1:0] and IB_AMP_ADC [1:0]. (In Figure 16-22, IB_AMP_PGA/ADC[1:0] = '11',
'10', '00' for fS = 500, 250, 62.5kHz respectively.)
Quiescent current consumption vs. temperature is depicted in Figure 16-23, showing a relative increase of nearly
40% between -45 and +85°C. Figure 16-24 shows the variation of quiescent current consumption for different
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16-27
XE8801A – SX8801R
frequency settings of the internal RC oscillator. It can be seen that the quiescent current varies by about 20%
between 100kHz and 2MHz.
100
200
300
400
500
600
700
800
2.53.03.54.04.55.05.5
Supply Voltage - V
DDA
[V]
Quiescen t Current - I
Q
[µA]
No PGAs, ADC o nly
PGA1 + ADC
PGA1 & 2 + ADC
PG A1, 2 & 3 + ADC
Figure 16-21 Quiescent current consumption vs. supply voltage
100
200
300
400
500
600
700
800
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage - V
DDA
[V]
Quiescent Current - I
Q
[µA]
500kHz
Sampl ing Frequency f
S
:
250kHz
62.5kHz
Figure 16-22 Quiescent current consumption vs. supply voltage for different sampling frequencies
500
550
600
650
700
750
800
850
900
-50 -25 0 25 50 75 100 125
Temperatu re [ °C]
Quiescent Cu rrent - I
Q
[µA]
-25
-20
-15
-10
-5
0
5
10
15
20
-50 -25 0 25 50 75 100 125
Temperature [°C]
Relative Quiescent Current Change
I
Q
/ I
Q,25°C
[%]
(a) (b)
Figure 16-23 (a) Absolute and (b) relative change inquiescent current consumption vs. temperature
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XE8801A – SX8801R
Supply ADC PGA1
PGA2 PGA3 TOTAL Unit
VDD = 5V 250 165 130 175 720 µA
VDD = 3V 190 150 120 160 620 µA
Table 16-28 Typical quiescent current distributions in acquisition chain (n = 16 bits, fS = 500kHz)
-20
-15
-10
-5
0
5
10
15
0 500 1000 1500 2000 2500 3000 3500
Fr e quency - fRC [kHz]
Relative Quiescent C urrent C hange
∆IQ / IQ,2MHz [%]
500
550
600
650
700
750
800
850
0 500 1000 1500 2000 2500 3000 3500
Fr equency - f
RC
[kHz]
Quiescent Current - I
Q
[µA]
(a) (b)
Figure 16-24 (a) Absolute and (b) relative change in quiescent curent consumption vs. RC oscillator
frequency (all PGAs active, VDD = 5V)
16.8.7 Power Supply Rejection Ratio
Figure 16-25 shows power supply rejection ratio (PSRR) at 3V and 5V supply voltage, and for various PGA gains.
PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the change in the converter output (in V).
PSRR depends on both PGA gain and supply voltage VDD.
60
65
70
75
80
85
90
95
100
105
1 5 10 20 100
PGA Gain [V/V]
PSRR [dB]
VDD=3V
V
DD=5V
Figure 16-25 Power supply rejection ratio (PSRR)
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XE8801A – SX8801R
Supply GAIN = 1 GAIN =5 GAIN = 10 GAIN = 20 GAIN =100 Unit
VDD = 5V 79 78 100 99 97 dB
VDD = 3V 72 79 90 90 86 dB
Table 16-29 PSRR (n = 16 bits, VIN = VREF = 2.5V, fS = 500kHz)
16.9 Application Hints
16.9.1 Input Impedance
The PGAs of the acquisition chain employ switched-capacitor techniques. For this reason, while a conversion is
done, the input impedance on the selec ted channel of the P GAs is inversely proportional to the sampling frequency
fS and to stage gain as given in equation 22.
gainf Hz
Z
s
in ⋅
Ω⋅
≥9
10768 (Eq. 22)
The input impedance observed is the input impedance of the first PGA stage that is enabled or the input impedance
of t he ADC if all three stages are disabled.
PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input
impedance of 150kΩ at fS = 512kHz (see Specification Table). Larger input impedance c an be obtained by reducing
the gain and/or by reducing the sampling frequency. Therefor, with a gain of 1 and a sampling frequency of 100kHz,
Zin > 7.6MΩ.
The input impedance on channels that are not selected is very high (>100MΩ).
16.9.2 PGA Settling or Input Channel Modifications
PGAs are reset after each writing operation to registers RegAcCfg1-5. Similarly, input channels are switched after
modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA or inputs
common-mode stabilization delay. This is done by writing bit START several cycles after PGA settings modification or
channel switching. Delay between PGA start or input channel switching and ADC s tart should be equivalent to OSR
(between 8 and 1024) number of cycles. This delay does not apply to conversions made without the PGAs.
If the ADC is not settled within the specified period, there is most probably an input impedance problem (see
previous section).
16.9.3 PGA Gain & Offset, Linearity and Noise
Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC™:
1) Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but degrades
nois e perform ance.
2) Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset.
Bypass unnecessary PGAs.
3) For high gains (>50), use PGA stage 1. For low gains (<50) use stages 2 and 3.
4) For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For
example, in an application where a gain of 20 is needed, set the gain of PGA2 to 10, set the gain of PGA3
to 2.
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XE8801A – SX8801R
4) For highest linearity and lowest noise performance, bypass all PGAs and use the ADC alone (applications
where no "zooming" is needed); i.e. set ENABLE[3:0] = '0001'.
5) For low-noise applications where power consumption is not a primary concern, maintain the largest bias
currents in the PGAs and in the ADC; i.e. set IB_AMP_PGA[1:0] = IB_AMP_ADC[1:0] = '11'.
6) F or lo west outp ut of fset error at t he out put o f the A DC, bypas s PGA 2 and PG A3. I ndeed, PGA 2 and P GA3
typically introduce an offset of about 5 to 10 LSB (16 bit) at their output. Note, however, that the ADC
output offset is easily calibrated out by software.
16.9.4 Frequency Response
The incremental ADC is an over-sampled converter with two main blocks: an analog modulator and a low-pass
digital filter. The main function of the digital filter is to remove the quant iza tion noi se int rod uced by the modul at or. A s
shown in Figure 16-26, this filter determines the frequency response of the transfer function between the output of
the ADC and the analog input VIN. Notice that the frequency axes are normalized to one elementary conversion
period OSR/fS. The plots of Figure 16-26 also show that the frequency response changes with the number of
elementary conversions NELCONV performed. In particular, notches appear for NELCONV ≥ 2. These notches occur at:
ELCONV
S
NOTCH NOSR fi
if ⋅
⋅
=)( (Hz) for )1(,...,2,1
−
=
ELCONV
Ni (Eq. 23)
and are repeated every fS/OSR.
Information on the location of these notches is particularly useful when specific frequencies must be filtered out by
the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection is
needed. Using the above equation and the plots below, we set the 4th notch for NELCONV = 4 to 50Hz, i.e. 1.25⋅fS/OSR
= 50Hz. The sampling frequency is then calculated as fS = 20.48kHz for OSR = 512. Notice that this choice yields
also good attenuation of 50Hz harmonics.
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XE8801A – SX8801R
0
0.2
0.4
0.6
0.8
1
1.2
01234
Normalized Frequency - f *(OSR/f
S
) [-]
Norma lized M agn itud e [-]
N
ELCONV
= 1
0
0.2
0.4
0.6
0.8
1
1.2
01234
Normalized Frequency - f *(OSR/f
S
) [-]
Nor mal ize d Magn itu d e [-]
N
ELCONV
= 2
0
0.2
0.4
0.6
0.8
1
1.2
01234
Normalized Frequency - f *(OSR/fS) [-]
Nor m al i ze d Magn i tu d e [-]
N
ELCONV
= 4
0
0.2
0.4
0.6
0.8
1
1.2
01234
Norma l i z ed Frequency - f *(OSR/f
S
) [-]
Nor malized M agnitude [-]
N
ELCONV
= 8
Figure 16-26 Frequency response: normalized magnitude vs. frequency for different NELCONV
16.9.5 Power Reduction
The ZoominADC™ is particularly well suited for low-power applications. When very low power consumption is of
primary concern, such as in battery operated systems, several parameters can be used to reduce power
consumption as follows:
1) Operate the acquisition chain with a reduced supply voltage VDD.
2) Disable the PGAs which are not used during analog-to-digital conversion with ENABLE[3:0].
3) Disable all PGAs and the ADC when the system is idle and no conversion is performed.
4) Use lower bias currents in the PGAs and the ADC using the control words IB_AMP_PGA[1:0] and
IB_AMP_ADC[1:0]. (This reduces the maximum sampling frequency according to Table 16-26.)
5) Reduce internal RC oscillator frequency and/or sampling frequency.
Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower
maximum sampling speed.
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XE8801A – SX8801R
17. Vmult (Voltage Multiplier)
17.1 Features 17-2
17.2 Overview 17-2
17.3 Control register 17-2
17.4 External component 17-2
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XE8801A – SX8801R
17.1 Features
• Generates a volt ag e that is higher or equ al to the supply v oltage.
• Can be easily enabled or disabled
17.2 Overview
The Vmult block generates a voltage (called “Vmult”) that is higher or equal to the supply voltage. This output
voltage is used in the acquisition chain.
The voltage multiplier should be on (bit ENABLE in RegVmultCfg0) when using the acquisition chain or analog
properties of the Port B while VBAT is below 3V. If the multiplier is enabled, the external capacitor on the pin
VMULT is mandatory.
The source clock of Vmult is selected by FIN[1:0] in RegVmultCfg0. It is strongly recommended to use the same
settings as in the ADC.
17.3 Control register
There is only one reg i st er in the Vmult. Table 17-1 describes the bits in the register.
Pos. RegVmultCfg0 rw Reset Function
2 Enable rw 0
resetsystem enable of the vmult
‘1’ : enabled
‘0’ : disabled
1-0 Fin rw 0
resetsystem system clock division f act or
‘00’ : 1/2,
‘01’ : 1/4,
‘10’ : 1/16,
‘11’ : 1/64
Table 17-1. RegVmultCfg0
17.4 External component
When the multiplier is enabled, a capacitor has to be connected to the VMULT pin. If the multiplier is disabled, the
pin may remain floating.
Min. Max. Note
Capacitor on VMULT 1.0 3.0 nF
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XE8801A – SX8801R
18 Counters/Timers/PWM
18.1 Features 18-2
18.2 Overview 18-2
18.3 Register map 18-2
18.4 Interrupts and events map 18-4
18.5 Block sc hematic 18-4
18.6 General counter registers operation 18-5
18.7 Clock selection 18-5
18.8 Counter mode selection 18-6
18.9 Counter / Timer mode 18-7
18.10 PWM mode 18-8
18.11 Capture function 18-9
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XE8801A – SX8801R
18.1 Features
• 4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules
• Each with 4 possible clock sources
• Up/down counter modes
• Interrupt and event generation
• Capture functi on (internal or ext ern al source)
• Rising, falling or both edge of capture signal
• PA[3:0] can be used as clock inputs (deb ou nced or direct)
• 2 x 8 bits PWM or 2 x 16 bits PWM
• PWM resolution of 8, 10, 12, 14 or 16 bits
• Complex mode combinations are possib l e be tween counter, capture and PWM mode s
18.2 Overview
CounterA and CounterB are 8-bit counters and can be combined to form a 16-bit counter. CounterC and CounterD
exhibit the same features.
The counters can also be used to generate two PWM outputs on PB[0] and PB[1]. In PWM mode one can generate
PWM functions with 8, 10, 12, 14 or 16 bit wide counters.
The counters A and B can be captured by events on an internal or an external signal. The capture can be
performed on both 8-bit counters running individually on two different clock sources or on both counters chained to
form a 16-bit counter. In any case, the same captur e signal is used for both counters.
When the counters A and B are not chained, they can be used in several configurations: A and B as counters, A
and B as captured counters, A as PWM and B as coun ter, A as PWM and B as captured counter .
When the counters C and D are not chained, they can be used either both as counters or counter C as PWM and
counter D as counter.
18.3 Register map
Bit RegCntA rw reset function
7-0 CounterA r xxxxxxxx 8-bits counter value
7-0 CounterA w xxxxxxxx 8-bits comparison value
Table 18-1. RegCntA
bit RegCntB rw reset function
7-0 CounterB r xxxxxxxx 8-bits counter value
7-0 CounterB w xxxxxxxx 8-bits comparison value
Table 18-2. RegCntB
Note: When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading
these locations, the processor reads back either the actual counter value or the last captured value if the capture
mode is active.
bit RegCntC rw reset function
7-0 CounterC r xxxxxxxx 8-bits counter value
7-0 CounterC w xxxxxxxx 8-bits comparison value
Table 18-3. RegCntC
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XE8801A – SX8801R
bit RegCntD rw reset function
7-0 CounterD r xxxxxxxx 8-bits counter value
7-0 CounterD w xxxxxxxx 8-bits comparison value
Table 18-4. RegCntD
Note: When writing RegCntC or RegCntD, the processor writes the counter comparison values. When reading
these locati ons, the processor reads back t he actu al counter value.
bit RegCntCtrlCk rw reset function
7-6 CntDCkSel(1:0) rw xx Counter d clock selecti on
5-4 CntCCkSel(1:0) rw xx Counter c clock selection
3-2 CntBCkSel(1:0) rw xx Counter b clock selection
1-0 CntACkSel(1:0) rw xx Counter a clock selection
Table 18-5. RegCntCtrlCk
bit RegCntConfig1 rw Reset function
7 CntDDownUp rw x Counter d up or down count i ng (0=do wn)
6 CntCDownUp rw x Counter c up or down coun ting (0=down)
5 CntBDownUp rw x Counter b up or down counting (0=do w n)
4 CntADownUp rw x Counter a up or down counting (0=do w n)
3 CascadeCD rw x Cascade counter c & d (1=cascade)
2 CascadeAB rw x Cascade counter a & b (1=ca sca de )
1 CntPWM1 rw 0 resetsystem Activ a te pwm1 on counter c or c+d (PB(1))
0 CntPWM0 rw 0 resetsystem Activate pwm0 on counter a or a+b (PB(0))
Table 18-6. RegCntConfig1
bit RegCntConfig2 rw Reset function
7-6 CapSel(1:0) rw 00 resetsystem Capture source
selection
5-4 CapFunc(1:0) rw 00 resetsystem Capture function
3-2 Pwm1Size(1:0) rw xx Pwm1 size
selection
1-0 Pwm0Size(1:0) rw xx Pwm0 size
selection
Table 18-7. RegCntConfig2
bit RegCntOn rw Reset Function
7-4 -- r 0000 Reserved
3 CntDEnable rw 0 resetsyst em Enable counter d
2 CntCEnable rw 0 resetsyst em Enable counter c
1 CntBEnable rw 0 resetsystem Enable counter b
0 CntAEnable rw 0 resetsystem Enable counter a
Table 18-8. RegCntOn
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18-4
XE8801A – SX8801R
18.4 Interrupts and events map
Interrupt source Mapping in the
interrupt manager Mapping in the event
manager
IrqA RegIrqHigh(4) RegEvn(7)
IrqB RegIrqLow(5) RegEvn(3)
IrqC RegIrqHigh(3) RegEvn(6)
IrqD RegIrqLow(4) RegEvn(2)
Table 18-9. Inter rup t a nd event mapping .
18.5 Block schematic
PB(0)
Capture
ck32k
ck1k
PA(0)
RegCntA (write)
Co unt er A
PA(2)
RegCntC (write)
Co unt er C
RegCntD (write)
Co unt er D
RegCntB (write)
Co unt er B
PA(1)
PA(3)
ck128
ckrcext/4
ckrcext
ck1k
ck32k
PWM PB(1)
RegCntA (read)
RegCntB (read)
RegCntC (read)
RegCntD (read)
Figure 18-1: Counters/timers block schematic
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XE8801A – SX8801R
18.6 General counter registers operation
Counters are ena ble d by CntAEnable, CntBEnable, CntCEnable, and CntDEna ble in RegCntOn.
To stop the counter X, CntXEnable must be reset. To start the counter X, CntXEnable must be set. When
counters are cascaded, CntAEnable and CntCEnable also control respectively the counters B and D.
In the control registers, all registers must be written in this order: RegCntCtrlCk, RegCntConfig1, RegCntConfig2
and all RegCntX because several bits have no default values at reset.
All counters have a corresponding 8-bit read/write register: RegCntA, RegCntB, RegCntC, and RegCntD. When
read, these registers contain the counter value (or the captured counter value). When written, they modify the
counter comparison values.
For a correct acquisition of the counter value, use one of the three fol l owin g methods:
1) Stop the concerned counter, perform the read operation and restart the counter. While stopped, the
counter content is frozen and the counter does not take into account the clock edges delivered on the
external pin.
2) For slow operating counters (typically at least 8 times slower than the CPU clock), oversample the counter
content and perform a majority operation on the consecutive read results to select the correct actual
content of the counter.
3) Use the capture mechanism.
When a value is written into the counter register while the counter is in counter mode, both the comparison value is
updated and the counter value is modified. In upcount mode, the register value is reset to zero. In downcount
mode, the comparison value is loaded into the counter. Due to the synchronization mechanism between the
processor clock domain and the external clock source domain, this modification of the counter value can be
postponed unt il t he coun te r is ena ble d an d it receives it’s first v alid clock edge.
In the PWM mode, the counter value is not modified by the write operation in the counter register. Changing the
counter mode, do es not update the counter valu e (no load in downcount mode).
18.7 Clock selection
The clock source for each counter can be individually selected by writing the appropriate value in the register
RegCntCtrlCk.
Table 18-10 gives the correspondence between the binary codes used for the configuration bits CntACkSel(1:0),
CntBCkSel(1:0), CntCCkSel(1:0) or CntDCkSel(1:0) and the clock source selected respectively for the counters
A, B, C or D.
Clock source for
CntXCkSel(1:0) CounterA CounterB CounterC CounterD
11 Ck128
10 CkRc/4 Ck1k
01 CkRc Ck32k
00 PA(0) PA(1) PA(2) PA(3)
Table 18-10: Clock sources for counters A, B, C and D
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XE8801A – SX8801R
The CkRc clock is the RC oscillator. The clocks below 32kHz can be derived from the RC oscillator or the crystal
oscillator (see the documentation of the clock block). A separate external clock source can be delivered on Port A
for each individual counter.
The external clock sources can be debounced or not by settin g the Port A conf ig ur ation registers.
The clock source can be change d on ly when the counter is stopped.
18.8 Counter mode selection
Each counter can work in one of the following modes:
1) C ounter, downcount & upcount
2) Captured counter, downcount & upcount (only counters A&B)
3) PWM, downcount
The counters A and B or C and D can be cascaded or not. In cascaded mode, A and C are the LSB counters while
B and D are the MSB counters.
Table 18-11 shows the different operation modes of the counters A and B as a function of the mode control bits.
For all counte r modes, the s ource of the d own or upcoun t selection is given (eith er the bit CntADownUp or the bit
CntBDownUp). Also, the mapping of the interrupt sources IrqA and IrqB and the PWM output on PB(0) in these
different modes is shown.
CascadeAB
CountPWM0
CapFunc(1:0)
Counter A
mode Counter B
mode IrqA
source IrqB
source PB(0)
function
0 0 00
Counter 8b
Downup: A Counte r 8b
Downup: B Counter
A Counter
B PB(0)
1 0 00 Counter 16b AB
Downup: A Counter
AB - PB(0)
0 1 00
PWM 8b
Down Counter 8b
Down - Counter
B PWM A
1 1 00 PWM 10 – 16b AB
Down - - PWM AB
0 0
1x
or
x1
Captured
counter 8b
Downup: A
Captured
counter 8b
Downup: B
Capture
A Capture
B PB(0)
1 0
1x
or
x1
Captured counte r 16b AB
Downup: A Capture
AB Capture
AB PB(0)
0 1
1x
or
x1
PWM 8b
Down
Captured
counter 8b
Downup: B
Must not
be used Capture
B PWM A
Table 18-11: Operating modes of the counters A and B
Table 18-12 shows th e different ope ration modes of th e cou nt ers C an d D as a function of the m ode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntCDownUp or the bit
CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these
different modes is also shown.
The switching between different modes must be done while the concerned counters are stopped. While switching
capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode
change.
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18-7
XE8801A – SX8801R
CascadeCD CountPWM1 Counter C
mode Counter D
mode IrqC
Source IrqD
source PB(1)
function
0 0
Counter 8b
Downup: C Counter 8b
Downup: D Counter
C Counter
D PB(1)
1 0 Counter 16b CD
Downup: C Counter
CD - PB(1)
0 1
PWM 8b
Down Counter 8b
Down - Counter
D PWM C
1 1
PWM 10 – 16b CD
Down - - PWM CD
Table 18-12: Operating modes of the counters C and D
18.9 Counter / Timer mode
The counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock
periods appli ed o n the counter clock inpu t.
Each counter can be set individually either in upcount mode by setting CntXDownUp in the register
RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave as a 16
bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting
CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the
up/down count modes set for t he counters A and C.
When in upcount mode, the counter will start incrementing from zero up to the target value which has been written
in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is
generated at the next falling edge of counter clock. Then the counter is loaded again with the zero value at the next
rising edge of coun ter clock (Figure 18-2).
When in downcount mode, the counter will start decrementing from the initial load value which has been written in
the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an
interrupt is generated at the next falling edge of counter clock. Then the counter is loaded again with the load value
at the next rising edge of counter clock (Figure 18-2).
Be careful to select the counter mode (no capture, not PWM, specify cascaded or not and up or down counting
mode) before writing any target or load value to the RegCntX register(s). This ensures that the counter will start
from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that
both cascaded counters will start from the correct initial values.
The stopping and consecutive starting of a counter in counte r mode without a targ et or load value write opera tion in
between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it’s target
value (upcount). This interrupt is additional to the interrupt which has already been generated when the counter
reached the zero or the target value.
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18-8
XE8801A – SX8801R
d
ow n coun
ti
ng
clock counter X
RegcntX
_
rXX 321032103210
RegCntX
_
wXX 3
write RegCntX
CntXDownUp
IrqX
CntXEnable
up coun
ti
ng
clock counter X
RegCntX
_
rXX0 12301230123
RegCntX
_
wXX 3
write RegCntX
CntXDownUp
IrqX
CntXEnable
Figure 18-2. Up and d own cou nt interrupt generation.
18.10 PWM mode
The counters can gen era te PWM signals (Pulse Widt h Modulation) on the Port B out puts PB(0) and PB (1 ).
The PWM mode is selected by setting CntPWM1 and CntPWM0 in the RegCntConfig1 register. See Table 18-11
and Table 18-12 for an exact description of how the setting of CntPWM1 and CntPWM0 affects the operating
mode of the counters A, B, C and D according to the ot he r configurati on set tings.
When CntPWM0 is enabled, the PWMA or PWMAB output value overrides the value set in bit 0 of RegPBOut in
the Port B peripheral. When CntPWM1 is enabled, the PWMC or PWMCD output value o verrides the value se t in
bit 1 of RegPBOut. The corresponding ports (0 and/or 1) of Port B must be set in digital mode and as output and
either open dra i n o r not and pull up or not th ro ugh a proper settin g of the control regist ers of the Port B.
Counters in PWM mode always count down, the CntXDow nUp bit setting must be reset. No interrupts and events
are generated by the counters which are in PWM mode. Counters do count circularly: they restart at the maximal
value (either 0xFF when not cascaded or 0xFFFF when cascaded) when respectively an underflow condition
occurs in the counting.
The internal PWM signals are low as long as the counter contents are higher than the PWM code values written in
the RegCntX register s. They are high whe n the counter contents are smaller or equal to thes e PWM code values.
The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded.
PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the
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18-9
XE8801A – SX8801R
counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in
cascaded mode are shown in Table 18-13. Choosing a 16 bit PWM code higher than the maximum value that can
be represente d by the number of bits chosen for the resolution, results in a PWM outp ut which is alwa ys tied to 1.
Pw mXsize(1:0) Resolution
11 16 bits
10 14 bits
01 12 bits
00 10 bits
Table 18-13: Resolution selection in cascaded PWM mode
Sm a ll PWM co de
Lar ge PW M code
Tper
Thlarge Tllarge
Thsmall Tlsmall
Figure 18-3: PWM modulation ex amp l es
The period of th e PWM sig nal is given by t he f or m ula :
ckcnt
resolution
f
Tper 2
=
The duty cycle rat i o DCR of t he PWM sign al is de fined as:
Tper
Th
DCR =
DCR can be selected between 0 % and 100*
212 resolution
resolution − %.
DCR in % in functio n of the RegCntX content(s) is given by the relati o n:
resolution
DCR 2RegCntX*100
=
18.11 Capture function
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the ex t ernal PA(2) or PA(3) ports. Bo th counters use the same capture condit ion.
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XE8801A – SX8801R
When the capture function is active, the A and B counters must be written with the value 0xFF and can either
upcount or downcount. They do count circularly: they restart at zero or at the maximal value (either 0xFF when not
cascaded or 0xFFFF when cascaded) when respectively an overflow or an underflow condition occurs in the
counting.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 18-14 shows the capture condition as a function of the setting of these
configuratio n bit s.
CapSel(1:0) Selected capture signal CapFunc Selected condition Capture condition
11 1 K
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
1 K rising edge
1 K falling edge
1 K both edges
10 32 K
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
32 K rising edge
32 K falling edge
32 K both edges
01 PA3
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
PA3 rising edg e
PA3 falling edge
PA3 both edges
00 PA2
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
PA2 rising edg e
PA2 falling edge
PA2 both edges
Table 18-14: Capture condition selection
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the
effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the
same clock, the interruptions on IrqA and IrqB which inform that the capture condition was met, may appear at
different moments. In this case, the processor should read the shadow register associated to a counter only if the
interrupt io n related to t his cou nter has been det ected.
It must be noted that when counters A and B are cascaded, the capture might happen at different cycles for the A
and B registers. This is due to the asynchronous relationship between counter and capture clock and to the fact
that the capture condition det ection is independent for A and B cou nters.
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19-1
XE8801A – SX8801R
19 VLD (Voltage Level Detector)
19.1 Features 19-2
19.2 Overview 19-2
19.3 Register map 19-2
19.4 Interrupt map 19-2
19.5 VLD operation 19-2
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19-2
XE8801A – SX8801R
19.1 Features
• Can be switched off, on or simultaneously with CPU activities
• Generates an inter rup t if powe r sup ply is below a pre-determi ned level
19.2 Overview
The Voltage Level Detector (VLD) monitors the state of the system battery. It returns a logical high value (an
interrupt) in the status register if the supplied voltage drops below the user defined level (Vsb).
The VLD must be calibra te d by setting VldTune bits du rin g pr odu ct manufacturing to cancel technol og y variation.
19.3 Register map
There are tw o regis ters in the VLD, namely RegVldCtrl and RegVldStat. Table 19-1 shows the mapping of control
bits and functionality of RegVldCtrl while Table 19-2 describ es th at for RegVldStat.
pos. RegVldCtrl rw reset function
7-4 -- r 0000 reserved
3 VldRange r w 0 resetsystem VLD detection volta ge ran ge f or VldTune = “011”:
0 : 1.3V (not use d in XE 8801A and SX88 01R)
1 : 2.55V
2-0 VldTune[2:0] r w 000
resetsystem VLD tuning:
000 : +19 %
111 : -18 %
Table 19-1: RegVldCtrl
pos. RegVldStat rw reset function
7-3 -- r 00000 reserved
2 VldResult r 0 resetsystem is 1 when battery voltage is below the detection
voltage
1 VldValid r 0 resetsystem Indicates when V ldRe sult can be read
0 VldEn r w 0 resetsystem VLD enable
Table 19-2: RegVldStat
19.4 Interrupt map
interrupt source mapping in the interrupt manager
IrqVld RegIrqMid(2)
Table 19-3: Interrupt map
19.5 VLD operation
The VLD is controlled by VldRange, VldTune and VldEn. VldRange selects the voltage range to be detected,
while VldTune is used to fine-tune this voltage level in 8 steps. VldEn is used to enable (disable) the VLD with a
1(0) value respectively.
When disabled, the block dissipates no power.
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19-3
XE8801A – SX8801R
symbol description min typ max unit comments
trimming values:
VldRange VldTune
not used 0 xxx
2.60 3.20 1 000
2.50 3.00 1 001
2.38 2.83 1 010
2.24 2.69 1 011
2.10 2.56 1 100
2.00 2.45 1 101
1.95 2.34 1 110
Vth Threshold voltage
Note 1
1.90 2.23
V
1 111
TEOM duration of measurement 2.0 2.5 ms Note 2
TPW Minimum pulse width
detected 875 1350 us Note 2
Vthd Variation of threshold
voltage with temperature +/-150 ppm/°C Note 3
Table 19-4: Voltage level det ect or operation
Note 1: measured at 20°C.
Note 2: this timing is respe cte d whe n t he in ternal RC or crystal oscillator is enabled
Note 3: between 0°C and 60°C
To start the voltage level detection, the user sets bit VldEn. The measurement is started.
After 2ms, the bit VldValid is set to indicate that the measurement results are valid. From that time on, as long as
the VLD is enabled, a maskable interrupt request is sent if the voltage level falls below the threshold. One can also
poll the VLD and monitor the actual measurement result by reading the VldResult bit of the RegVldStat. This
result is only v alid as long as the VldValid bit is ‘1’.
An interru pt i s gene rated on each risi ng edge of VldResult.
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20-1
XE8801A – SX8801R
20 Physical Dimensions
CONTENTS
20.1 LQFP typ e package 20-2
20.2 Die XE8801AM 20-2
20.3 Die SX8801R 20-3
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20-2
XE8801A – SX8801R
20.1 LQFP type package
The QFP package dimensions are given in Figure 20-1 and Table 20-1. The dimensions conform to JEDEC MS-
026 Rev. C.
Figure 20-1. QFP type package
package A
mm
B
mm
C
mm
D
mm
E
mm
F
mm
G
mm
LQFP-44 10.0 12.0 1.4 0.10 0.37 0.8
Table 20-1. QFP package dimensions
20.2 Die XE8801AM
The XE8801AM die is 4100 x 4600 um2 large plus 20-30 um due to the saw channel. Zero coordinate is at bottom
left corner of p ad ring. Pad op ening is 85x85 um2. Pad surface is xxx.
pin name pin X
[um] pin Y
[um] pin name pin X
[um] pin Y
[um]
left pads top pads
PA(4) 52 4075 PA(3) 417 4453
PA(5) 52 3795 PA(2) 682 4453
VBat 52 3515 PA(1) 947 4453
PA(6) 52 3235 PA(0) 1212 4453
PA(7) 52 2955 OSCOUT 1477 4453
PC(0) 52 2675 VSS 1742 4453
PC(1) 52 2395 OSCIN 2007 4453
PC(2) 52 2115 VMULT 2537 4453
PC(3) 52 1835 RESET 2802 4453
VSS 52 1555 VREG 3067 4453
PC(4) 52 1275 VSS 3332 4453
PC(5) 52 995 VBAT 3597 4453
PC(6) 52 715
PC(7) 52 435
bottom pads right pads
PB(0) 398 47 VSS 3958 3942
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20-3
XE8801A – SX8801R
pin name pin X
[um] pin Y
[um] pin name pin X
[um] pin Y
[um]
PB(1) 533 47 AC_R(0) 3958 3657
PB(2) 668 47 AC_R(1) 3958 3372
PB(3) 798 47 AC_A(0) 3958 3087
PB(4) 933 47 AC_A(1) 3958 2802
VBAT 1063 47 VSS 3958 2517
PB(5) 1198 47 AC_A(2) 3958 2232
PB(6) 1328 47 AC_A(3) 3958 1947
PB(7) 1463 47 AC_A(4) 3958 1662
TEST 1934 47 AC_A(5) 3958 1377
VSS 2394 47 AC_A(6) 3958 1092
AC_R(3) 2854 47 VBAT 3958 807
AC_R(2) 3314 47 AC_A(7) 3958 522
20.3 Die SX8801R
The SX8801R die is 3441 x 4131 um2 large plus 20-30 um due to the saw channel. Zero coordinate is at bottom
left corner of p ad ring. Pad op ening is 85x85 um2. Pad surface is xxx.
pin name pin X
[um] pin Y
[um] pin name pin X
[um] pin Y
[um]
left pads top pads
PA(5) 118 3776 PA(4) 285 4013
VBAT 118 3490 PA(3) 470 4013
PA(6) 118 3256 PA(2) 704 4013
PA(7) 118 3033 PA(1) 939 4013
PC(0) 118 2710 PA(0) 1173 4013
PC(1) 118 2438 OSCOUT 1403 4013
PC(2) 118 2166 VSS 1638 4013
PC(3) 118 1894 OSCIN 1923 4013
VSS 118 1659 VMULT 2157 4013
PC(4) 118 1387 RESET 2352 4013
PC(5) 118 1115 VREG 2573 4013
PC(6) 118 843 VSS 2772 4013
PC(7) 118 571 VBAT 3032 4013
PB(0) 118 285
bottom pads right pads
PB(1) 447 118 VSS 3323 3760
PB(2) 724 118 AC_R(0) 3323 3475
PB(3) 1001 118 AC_R(1) 3323 3240
PB(4) 1278 118 AC_A(0) 3323 3006
VBAT 1513 118 AC_A(1) 3323 2771
PB(5) 1790 118 VSS 3323 2487
PB(6) 2067 118 AC_A(2) 3323 2151
PB(7) 2344 118 AC_A(3) 3323 1867
TEST 2735 118 AC_A(4) 3323 1578
VSS 2971 118 AC_A(5) 3323 1344
AC_R(3) 3155 118 AC_A(6) 3323 1109
VBAT 3323 874
AC_A(7) 3323 589
AC_R(2) 3323 355
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XE8801A – SX8801R Sensing Machine
Data Acquisition with ZoomingADC™
Contact Information
© Semtech 2009
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