© Semiconductor Components Industries, LLC, 2017
June, 2020 − Rev. 10
1Publication Order Number:
NCP1342/D
Quasi-Resonant Flyback
Controller, High Frequency
NCP1342
The NCP1342 is a highly integrated quasi−resonant flyback
controller suitable for designing high−performance off−line power
converters. With an integrated active X2 capacitor discharge feature,
the NCP1342 can enable no−load power consumption below 30 mW.
The NCP1342 features a proprietary valley−lockout circuitry,
ensuring stable valley switching. This system works down to the 6th
valley and transitions to frequency foldback mode to reduce switching
losses. As the load decreases further, the NCP1342 enters quiet−skip
mode to manage the power delivery while minimizing acoustic noise.
To ensure light load performance with high frequency designs, the
NCP1342 incorporates Rapid Frequency Foldback with Minimum
Peak Current Modulation to reduce the switching frequency quickly.
To help ensure converter ruggedness, the NCP1342 implements
several key protective features such as internal brownout detection, a
non−dissipative Over Power Protection (OPP) for constant maximum
output power regardless of input voltage, a latched overvoltage and
NTC−ready overtemperature protection through a dedicated pin, and
line removal detection to safely discharge the X2 capacitors when the
ac line is removed.
Features
•Integrated High−Voltage Startup Circuit with Brownout Detection
•Integrated X2 Capacitor Discharge Capability
•Wide VCC Range from 9 V to 28 V
•28 V VCC Overvoltage Protection
•Abnormal Overcurrent Fault Protection for Winding Short Circuit or
Saturation Detection
•Internal Temperature Shutdown
•Valley Switching Operation with Valley−Lockout for Noise−Free
Operation
•Frequency Foldback with 25 kHz Minimum Frequency Clamp for
Increased Efficiency at Light Loads
•Rapid Frequency Foldback for Fast Reduction of Switching
Frequency at Light Loads
•Skip Mode with Quiet−Skip Technology for Highest Performance
During Light Loads
•Minimized Current Consumption for No Load Power Below 30 mW
•Frequency Jittering for Reduced EMI Signature
•Latching or Auto−Recovery Timer−Based Overload Protection
•Adjustable Overpower Protection (OPP)
•Adjustable Maximum Frequency Clamp
•Fault Pin for Severe Fault Conditions, NTC Compatible for OTP
•4 ms Soft−Start Timer
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
PIN CONNECTIONS
(Top Views)
SOIC−9 NB
D SUFFIX
CASE 751BP
www.onsemi.com
See detailed ordering and shipping information on page 3 of
this data sheet.
ORDERING INFORMATION
1
9
1342abcde = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
f = Additional Options Code
G= Pb−Free Package
MARKING DIAGRAMS
1342abcde
ALYWf
G
1
9
GND
DRV
VCC
HV
FMAX
FB
ZCD/OPP
CS
Fault
1
FB
ZCD/OPP
CS
Fault
GND
DRV
VCC
HV
1
SOIC−8 NB
D SUFFIX
CASE 751
1
8
1342abcde
ALYWf
G
1
8
NCP1342
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Table 1. PART NUMBER DECODE − NCP1342ABCDEF
NCP1342 A B C D E F*
Device
OTP/Overload Jitter Frequency/Amplitude Quiet−Skip CS Min CS Min Shift Additional
A − AR/AR A − 1.55 kHz/75 mV A − 800 Hz A − 200 mV A − 400 mV −
B − Latch/AR B − 1.55 kHz/92 mV B − 1.2 kHz B − 150 mV B − 350 mV A
C − AR/Latch C − 1.55 kHz/55 mV C − 1.56 kHz C − 100 mV C − 300 mV C
D − Latch/Latch D − 1.55 kHz/61 mV D − Disabled D − 250 mV D − 250 mV D
E − 1.3 kHz/75 mV E − Disabled E
F − 1.3 kHz/92 mV
G − 1.3 kHz/55 mV
H − 1.3 kHz/61 mV
J − 3.9 kHz/75 mV
K − 3.9 kHz/92 mV
L − 3.9 kHz/55 mV
M − 3.9 kHz/61 mV
N − Disabled
*Not present in all parts. See Table 2 for details.
Table 2. ADDITIONAL PART OPTIONS
F Description
−Default Configuration
AX2 Discharge Disabled, VBO(stop) = 84 V, VBO(start) = 94 V
COverload Disabled
DX2 Discharge Disabled, VBO(stop) = 84 V, VBO(start) = 94 V, Resettable Overload Timer
EX2 Discharge Disabled, Brownout Disabled
Table 3. ORDERING INFORMATION
Part Number Device Marking Package Shipping
NCP1342AMDCCDR2G 1342AMDCC SOIC−8 NB (Pb−Free)
2500 / Tape & Reel
NCP1342ANDAAD1R2G 1342ANDAA
SOIC−9 NB (Pb−Free)
NCP1342DADBDD1R2G 1342DADBD
NCP1342AMDCDAD1R2G 1342AMDCDA
NCP1342AMAACD1R2G 1342AMAAC
NCP1342ANACED1R2G 1342ANACE
NCP1342ANACECD1R2G 1342ANACEC
NCP1342ANDBDD1R2G 1342ANDBD
NCP1342BMDCDAD1R2G 1342BMDCDA
NCP1342BMDCDDD1R2G 1342BMDCDD
NCP1342BMDCDED1R2G
(In Development)
1342BMDCDE
NCP1342AMDCDD1R2G 1342AMDCD
NCP1342ANACCED1R2G 1342ANACCE
NCP1342
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4
FUNCTIONAL BLOCK DIAGRAM
Figure 3. NCP1342 Block Diagram
FB
CS
R
Q
S
RFB
tLEB1
OPP
ZCD/OPP
÷
KFB
ICS
VDD
Clamp
VCC
DRV
GND
VCC
X2/BO Detect
+
VCC
Management
HV
X2
FMAX
Control
Fault
VFB(open)
On−Time
Control
ILIM1
Detect
tLEB2 ILIM2
Detect
Jitter Ramp
Count 4 Abnormal OCP
OPP
Control
OPP
Off−Time
Control
Dead−Time
Control
Valley/FF
Control
FB
QR_FMAX ttout
Quiet−Skip
Control
FB
Fault
Management
BO
VCC(OVP)
TSD
OVLD
tOVLD
Abnormal OCP
OVLD
Fault
QR_FMAX
MPCM
Control
FB
OVP/OTP
Detect
OVP
OTP
OVP
OTP
VFault(clamp)
Fault
IOTP
VDD
RFault(clamp)
FMAX
IFMAX
VDD
8−Pin 9−Pin
Table 4. PIN FUNCTIONAL DESCRIPTION
8−Pin 9−Pin Pin Name Function
1 1 Fault The controller enters fault mode if the voltage on this pin is pulled above or below the fault
thresholds. A precise pull up current source allows direct interface with an NTC thermistor.
−2 FMAX A resistor to ground sets the value for the maximum switching frequency clamp. If this pin is
pulled above 4 V, the maximum frequency clamp is disabled.
2 3 FB Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
3 4 ZCD/OPP A resistor divider from the auxiliary winding to this pin provides input to the demagnetization de-
tection comparator and sets the OPP compensation level.
4 5 CS Input to the cycle−by−cycle current limit comparator.
5 6 GND Ground reference.
6 7 DRV This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suit-
able to effectively drive high gate charge power MOSFETs.
7 8 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17 V and
turns off when VCC goes below 9 V (typical values). After start−up, the operating range is 9 V up
to 28 V.
−9 N/C Removed for creepage distance.
8 10 HV This pin is the input for the high voltage startup and brownout detection circuits. It also contains
the line removal detection circuit to safely discharge the X2 capacitors when the line is removed.
NCP1342
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Table 5. MAXIMUM RATINGS
Rating Symbol Value Unit
High Voltage Startup Circuit Input Voltage VHV(MAX) −0.3 to 700 V
High Voltage Startup Circuit Input Current IHV(MAX) 20 mA
Supply Input Voltage VCC(MAX) −0.3 to 30 V
Supply Input Current ICC(MAX) 30 mA
Supply Input Voltage Slew Rate dVCC/dt 1 V/ms
Fault Input Voltage VFault(MAX) −0.3 to VCC + 0.7 V V
Fault Input Current IFault(MAX) 10 mA
Zero Current Detection and OPP Input Voltage VZCD(MAX) −0.3 to VCC + 0.7 V V
Zero Current Detection and OPP Input Current IZCD(MAX) −2/+5 mA
Maximum Input Voltage (Other Pins) VMAX −0.3 to 5.5 V
Maximum Input Current (Other Pins) IMAX 10 mA
Driver Maximum Voltage (Note 1) VDRV −0.3 to VDRV(high) V
Driver Maximum Current IDRV(SRC)
IDRV(SNK)
500
800
mA
Operating Junction Temperature TJ−40 to 125 °C
Maximum Junction Temperature TJ(MAX) 150 °C
Storage Temperature Range TSTG –60 to 150 °C
Power Dissipation (TA = 25°C, 1 oz. Cu, 42 mm
2
Copper Clad Printed Circuit)
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
PD(MAX) 450
330
mW
Thermal Resistance (TA = 25°C, 1 oz. Cu, 42 mm
2
Copper Clad Printed Circuit)
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
RqJA 225
300
°C/W
ESD Capability
Human Body Model per JEDEC Standard JESD22−A114F (All pins except HV)
Human Body Model per JEDEC Standard JESD22−A114F (HV Pin)
Charge Device Model per JEDEC Standard JESD22−C101F
Latch−Up Protection per JEDEC Standard JESD78E
2000
800
1000
±100
V
V
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
NCP1342
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Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics Conditions Symbol Min Typ Max Unit
START−UP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Discharge Voltage During Line Removal
Minimum Operating Voltage
Operating Hysteresis
Internal Latch / Logic Reset Level
Transition from Istart1 to Istart2
dV/dt = 0.1 V/ms
VCC increasing
VCC decreasing
VCC decreasing
VCC(on) − VCC(off)
VCC decreasing
VCC increasing, IHV = 650 mA
VCC(on)
VCC(X2_reg)
VCC(off)
VCC(HYS)
VCC(reset)
VCC(inhibit)
16.0
17.0
8.5
7.5
4.5
0.30
17.0
18.0
9.0
–
6.5
0.70
18.0
19.0
9.5
–
7.5
1.05
V
VCC(off) Delay VCC decreasing tdelay(VCC_off) 25 32 40 ms
Startup Delay Delay from VCC(on) to DRV Enable tdelay(start) – – 500 ms
Minimum Voltage for Start−Up Current
Source
VHV(MIN) – – 40 V
Inhibit Current Sourced from VCC Pin Vcc = 0 V Istart1 0.2 0.5 0.65 mA
Start−Up Current Sourced from VCC Pin Vcc = Vcc(on) – 0.5 V Istart2 2.4 3.75 5.0 mA
Start−Up Circuit Off−State Leakage Current VHV = 162.5 V
VHV = 325 V
VHV = 700 V
IHV(off1)
IHV(off2)
IHV(off3)
–
–
–
–
–
–
15
20
50
mA
Supply Current
Fault or Latch
Skip Mode (excluding FB current)
Operating Current
VCC = VCC(on) – 0.5 V
VFB = 0 V
fsw = 50 kHz, CDRV = open
ICC1
ICC2
ICC3
−
−
−
0.115
0.230
1.0
0.250
0.400
1.5
mA
VCC Overvoltage Protection Threshold VCC(OVP) 27 28 29 V
VCC Overvoltage Protection Delay tdelay(VCC_OVP) 25 32 40 ms
X2 CAPACITOR DISCHARGE (ALL VERSIONS EXCEPT xxxxxA, xxxxxD, xxxxxE)
Line Voltage Removal Detection Timer tline(removal) 65 100 135 ms
Discharge Timer Duration tline(discharge) 21 32 43 ms
Line Detection Timer Duration tline(detect) 21 32 43 ms
VCC Discharge Current VCC = 20 V ICC(discharge) 13 18 23 mA
HV Discharge Level VHV(discharge) – – 30 V
BROWNOUT DETECTION (ALL VERSIONS EXCEPT xxxxxE)
System Start−Up Threshold
Other Versions
Versions xxxxxA, xxxxxD
VHV increasing VBO(start)
107
89
112
94
116
99
V
Brownout Threshold
Other Versions
Versions xxxxxA, xxxxxD
VHV decreasing VBO(stop)
93
79
98
84
102
89
V
Hysteresis
Other Versions
Versions xxxxxA, xxxxxD
VHV increasing VBO(HYS)
9.0
6.0
14
10
–
–
V
Brownout Detection Blanking Time VHV decreasing tBO(stop) 40 70 100 ms
GATE DRIVE
Rise Time VDRV from 10% to 90% tDRV(rise) – 20 40 ns
Fall Time VDRV from 90% to 10% tDRV(fall) – 5 30 ns
2. NTC with R110 = 8.8 kW
NCP1342
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Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics UnitMaxTypMinSymbolConditions
GATE DRIVE
Current Capability
Source
Sink
IDRV(SRC)
IDRV(SNK)
–
–
500
800
–
–
mA
High State Voltage VCC = VCC(off) + 0.2 V, RDRV = 10 kW
VCC = 30 V, RDRV = 10 kW
VDRV(high1)
VDRV(high2)
8.0
10
–
12
–
14
V
Low Stage Voltage VFault = 0 V VDRV(low) – – 0.25 V
FEEDBACK
Open Pin Voltage VFB(open) 4.8 5.0 5.1 V
VFB to Internal Current Setpoint Division
Ratio
KFB −4−–
Internal Pull−Up Resistor VFB = 0.4 V RFB 17 20 23 kW
Valley Thresholds
Transition from 1st to 2nd valley
Transition from 2nd to 3rd valley
Transition from 3rd to 4th valley
Transition from 4th to 5th valley
Transition from 5th to 6th valley
Transition from 6th to 5th valley
Transition from 5th to 4th valley
Transition from 4th to 3rd valley
Transition from 3rd to 2nd valley
Transition from 2nd to 1st valley
VFB decreasing
VFB decreasing
VFB decreasing
VFB decreasing
VFB decreasing
VFB increasing
VFB increasing
VFB increasing
VFB increasing
VFB increasing
V1to2
V2to3
V3to4
V4to5
V5to6
V6to5
V5to4
V4to3
V3to2
V2to1
1.316
1.128
1.034
0.940
0.846
1.410
1.504
1.598
1.692
1.880
1.400
1.200
1.100
1.000
0.900
1.500
1.600
1.700
1.800
2.000
1.484
1.272
1.166
1.060
0.954
1.590
1.696
1.802
1.908
2.120
V
Maximum Frequency Clamp
(9−Pin Versions Only) VFMAX = 0.5 V
VFMAX = 3.5 V
fMAX1
fMAX2
440
61
500
70
560
79
kHz
FMAX Disable Threshold
(9−Pin Versions Only)
VFMAX(disable) 3.85 4.00 4.15 V
FMAX Pin Source Current
(9−Pin Versions Only)
IFMAX 9.0 10 11 mA
Maximum On Time ton(MAX) 28 32 40 ms
DEMAGNETIZATION INPUT
ZCD threshold voltage VZCD decreasing VZCD(trig) 35 60 90 mV
ZCD hysteresis VZCD increasing VZCD(HYS) 15 25 55 mV
Demagnetization Propagation Delay VZCD step from 4.0 V to −0.3 V tdemag – 80 250 ns
ZCD Clamp Voltage
Positive Clamp
Negative Clamp
IQZCD = 5.0 mA
IQZCD = −2.0 mA
VZCD(MAX)
VZCD(MIN)
12.4
−0.9
12.7
−0.7
13
0
V
Blanking Delay After Turn−Off tZCD(blank) 600 700 800 ns
Timeout After Last Demagnetization
Detection
While in soft−start
After soft−start complete
t(tout1)
t(tout2)
80
5.1
100
6.0
120
6.9
ms
CURRENT SENSE
Current Limit Threshold Voltage VCS increasing VILIM1 0.760 0.800 0.840 V
Leading Edge Blanking Duration DRV minimum width minus
tdelay(ILIM1)
tLEB1 220 265 330 ns
Current Limit Threshold Propagation Delay Step VCS 0 V to VILIM1 + 0.5 V,
VFB = 4 V
tdelay(ILIM1) – 95 175 ns
2. NTC with R110 = 8.8 kW
NCP1342
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Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics UnitMaxTypMinSymbolConditions
CURRENT SENSE
PWM Comparator Propagation Delay Step VCS 0 V to 0.7 V, VFB = 2.4 tdelay(PWM) – 125 175 ns
Minimum Peak Current
Versions xxxAx
Versions xxxBx
Versions xxxCx
Versions xxxDx
VCS(MIN)
170
115
70
215
200
150
100
250
230
185
130
285
mV
Abnormal Overcurrent Fault Threshold VCS increasing, VFB = 4 V VILIM2 1.125 1.200 1.275 V
Abnormal Overcurrent Fault Blanking
Duration
DRV minimum width minus
tdelay(ILIM2)
tLEB2 80 110 140 ns
Abnormal Overcurrent Fault Propagation
Delay
Step VCS 0 V to VILIM2 + 0.5 V,
VFB = 4 V
tdelay(ILIM2) – 80 175 ns
Number of Consecutive Abnormal Overcur-
rent Faults to Enter Latch Mode
nILIM2 – 4 –
Overpower Protection Delay VCS dv/dt = 1 V/ms, measured from
VOPP(MAX) to DRV falling edge
tOPP(delay) – 95 175 ns
Overpower Signal Blanking Delay tOPP(blank) 220 280 330 ns
Pull−Up Current Source VCS = VILIM2 − 10 mV ICS 0.7 1.0 1.5 mA
JITTERING
Jitter Frequency
Versions xJxxx, xKxxx, xLxxx, xMxxx
Versions xAxxx, xBxxx, xCxxx, xDxxx
Versions xExxx, xFxxx, xGxxx, xHxxx
Versions xNxxx
fjitter
3.5
1.43
1.2
−
3.9
1.55
1.3
−
4.2
1.68
1.4
−
kHz
Peak Jitter Voltage
Versions xBxxx, xFxxx, xKxxx
Versions xAxxx, xExxx, xJxxx
Versions xDxxx, xHxxx, xMxxx
Versions xCxxx, xGxxx, xLxxx
Versions xNxxx
Vjitter 82
65
52
45
−
92
75
61
55
−
102
85
70
65
−
mV
FAULT PROTECTION
Soft−Start Period Measured from
1st DRV pulse to VCS = VILIM1
tSSTART 2.8 4.0 5.0 ms
Flyback Overload Fault Timer
Other versions
Version xxxxxC
VCS = VILIM1 tOVLD 120
−
160
−
200
−
ms
Overvoltage Protection (OVP) Threshold VFault increasing VFault(OVP) 2.79 3.00 3.21 V
OVP Detection Delay VFault increasing tdelay(OVP) 22.5 30 37.5 ms
Overtemperature Protection (OTP) Thresh-
old (Note 2)
VFault decreasing VFault(OTP_in) 380 400 420 mV
Overtemperature Protection (OTP) Exiting
Threshold (Note 2)
VFault increasing VFault(OTP_out) 874 910 966 mV
OTP Detection Delay VFault decreasing tdelay(OTP) 22.5 30 37.5 ms
OTP Pull−Up Current Source VFault = VFault(OTP_in) + 0.2 V
TJ = 25°C to 125°C
IOTP 43.75 45.00 46.25 mA
Fault Input Clamp Voltage VFault(clamp) 1.15 1.7 2.25 V
Fault Input Clamp Series Resistor RFault(clamp) 1.32 1.55 1.78 kW
Autorecovery Timer trestart 1.8 2.0 2.2 s
2. NTC with R110 = 8.8 kW
NCP1342
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Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics UnitMaxTypMinSymbolConditions
LIGHT/NO LOAD MANAGEMENT
Minimum Frequency Clamp fMIN 21.5 25 27.0 kHz
Dead−Time Added During Frequency
Foldback
VFB = 400 mV tDT(MAX) 32 − − ms
Quiet−Skip Timer
Versions xxAxx
Versions xxBxx
Versions xxCxx
Versions xxDxx
tquiet 1.18
0.770
0.590
−
1.25
0.833
0.640
−
1.40
0.900
0.690
−
ms
Skip Threshold VFB decreasing Vskip 350 400 450 mV
Skip Hysteresis VFB increasing Vskip(HYS) 20 50 70 mV
RAPID FREQUENCY FOLDBACK
Minimum Peak Current Shift
Versions xxxxA
Versions xxxxB
Versions xxxxC
Versions xxxxD
Versions xxxxE
VMPCM(delta) 340
300
250
200
−
400
350
300
250
−
460
400
350
300
−
mV
Entry Threshold
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
VMPCM(entry) 780
−
800
−
820
−
mV
Exit Threshold
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
VMPCM(exit) 730
−
750
−
770
−
mV
Transition Timer
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
tMPCM
0.85
−
1.00
−
1.05
−
ms
THERMAL PROTECTION
Thermal Shutdown Temperature increasing TSHDN – 140 – °C
Thermal Shutdown Hysteresis Temperature decreasing TSHDN(HYS) – 40 – °C
2. NTC with R110 = 8.8 kW
NCP1342
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INTRODUCTION
The NCP1342 implements a quasi−resonant flyback
converter utilizing current−mode architecture where the
switch−off event is dictated by the peak current. This IC is
an ideal candidate where low parts count and cost
effectiveness are the key parameters, particularly in ac−dc
adapters, open−frame power supplies, etc. The NCP1342
incorporates all the necessary components normally needed
in modern power supply designs, bringing several
enhancements such as non−dissipative overpower
protection (OPP), brownout protection, and frequency
reduction management for optimized efficiency over the
entire power range. Accounting for the needs of extremely
low standby power requirements, the controller features
minimized current consumption and includes an automatic
X2 capacitor discharge circuit that eliminates the need to
install power−consuming resistors across the X2 input
capacitors.
•High−Voltage Start−Up Circuit: Low standby power
consumption cannot be obtained with the classic
resistive start−up circuit. The NCP1342 incorporates a
high−voltage current source to provide the necessary
current during start−up and then turns off during normal
operation.
•Internal Brownout Protection: The ac input voltage is
sensed via the high−voltage pin. When this voltage is
too low, the NCP1342 stops switching. No restart
attempt is made until the ac input voltage is back within
its normal range.
•X2−Capacitor Discharge Circuitry: Per the
IEC60950 standard, the time constant of the X2 input
capacitors and their associated discharge resistors must
be less than 1 s in order to avoid electrical shock when
the user unplugs the power supply and inadvertently
touches the ac input cord terminals. By providing an
automatic means to discharge the X2 capacitors, the
NCP1342 eliminates the need to install X2 discharge
resistors, thus reducing power consumption.
•Quasi−Resonant, Current−Mode Operation:
Quasi−Resonant (QR) mode is a highly efficient mode
of operation where the MOSFET turn−on is
synchronized with the point where its drain−source
voltage is at the minimum (valley). A drawback of this
mode of operation is that the operating frequency is
inversely proportional to the system load. The
NCP1342 incorporates a valley lockout (VLO) and
frequency foldback technique to eliminate this
drawback, thus maximizing the efficiency over the
entire power range.
•Valley Lockout: In order to limit the maximum
frequency while remaining in QR mode, one would
traditionally use a frequency clamp. Unfortunately, this
can cause the controller to jump back and forth between
two different valleys, which is often undesirable. The
NCP1342 patented VLO circuitry solves this issue by
determining the operating valley based on the system
load, and locking out other valleys unless a significant
change in load occurs.
•Rapid Frequency Foldback: As the load continues to
decrease, it becomes beneficial to reduce the switching
frequency. When the load is light enough, the NCP1342
enters rapid frequency foldback mode. During this
mode, the minimum peak current is limited and
dead−time is added to the switching cycle, thus
reducing the frequency and switching operation to
discontinuous conduction mode (DCM). Dead−time
continues to be added until skip mode is reached, or the
switching frequency reaches its minimum level of 25
kHz.
•Minimum Peak Current Modulation (MPCM): In
order to reduce the switching frequency even faster (for
high frequency designs), the NCP1342 uses MPCM to
increase the minimum peak current during frequency
foldback. It also reduces the minimum peak current
gradually as the load decreases to ensure optimum skip
mode entry.
•Skip Mode: To further improve light or no−load power
consumption while avoiding audible noise, the
NCP1342 enters skip mode when the operating
frequency reaches its minimum value. To avoid
acoustic noise, the circuit prevents the switching
frequency from decaying below 25 kHz. This allows
regulation via bursts of pulses at 25 kHz or greater
instead of operating in the audible range.
•Quiet−Skip: To further reduce acoustic noise, the
NCP1342 incorporates a novel circuit to prevent the
skip mode burst period from entering the audible range
as well.
•Internal OPP: In order to limit power delivery at high
line, a scaled version of the negative voltage present on
the auxiliary winding during the on−time is routed to
the ZCD/OPP pin. This provides the designer with a
simple and non−dissipative means to reduce the
maximum power capability as the bulk voltage
increases.
•Frequency Jittering: In order to reduce the EMI
signature, a low frequency triangular voltage waveform
is added to the input of the PWM comparator. This
helps by spreading out the energy peaks during noise
analysis.
•Internal Soft−Start: The NCP1342 includes a 4 ms
soft−start to prevent the main power switch from being
overly stressed during start−up. Soft−start is activated
each time a new startup sequence occurs or during
auto−recovery mode.
NCP1342
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11
•Dedicated Fault Input: The NCP1342 includes a
dedicated fault input. It can be used to sense an
overvoltage condition and latch off the controller by
pulling the pin above the overvoltage protection (OVP)
threshold. The controller is also disabled if the Fault pin
is pulled below the overtemperature protection (OTP)
threshold. The OTP threshold is configured for use with
a NTC thermistor.
•Overload/Short−Circuit Protection: The NCP1342
implements overload protection by limiting the
maximum time duration for operation during overload
conditions. The overload timer operates whenever the
maximum peak current is reached. In addition to this,
special circuitry is included to prevent operation in
CCM during extreme overloads, such as an output
short−circuit.
•Maximum Frequency Clamp: The 9−pin version of
NCP1342 includes a maximum frequency clamp. The
clamp can be adjusted via an external resistor from the
FMAX Pin to ground. It can also be disabled by pulling
the FMAX pin above 4 V.
HIGH VOLTAGE START−UP
The NCP1342 contains a multi−functional high voltage
(HV) pin. While the primary purpose of this pin is to reduce
standby power while maintaining a fast start−up time, it also
incorporates brownout detection and line removal detection.
The HV pin must be connected directly to the ac line in
order for the X2 discharge circuit to function correctly. Line
and neutral should be diode “ORed” before connecting to the
HV pin as shown in Figure 4. The diodes prevent the pin
voltage from going below ground. A resistor in series with
the pin should be used to protect the pin during EMC or surge
testing. A low value resistor should be used (<5 kW) to
reduce the voltage offset during start−up.
Figure 4. High−Voltage Input Connection
EMI
AC
CON
HV
Controller
Start−up and VCC Management
During start−up, the current source turns on and charges
the VCC capacitor with Istart2 (typically 6 mA). When Vcc
reaches VCC(on) (typically 16.0 V), the current source turns
off. If the input voltage is not high enough to ensure a proper
start−up (i.e. VHV has not reached VBO(start)), the controller
will not start. VCC then begins to fall because the controller
bias current is at ICC2 (typically 1 mA) and the auxiliary
supply voltage is not present. When VCC falls to VCC(off)
(typically 10.5 V), the current source turns back on and
charges VCC. This cycle repeats indefinitely until VHV
reaches VBO(start). Once this occurs, the current source
immediately turns on and charges VCC to VCC(on), at which
point the controller starts (see Figure 6).
When VCC is brought below VCC(inhibit), the start−up
current is reduced to Istart1 (typically 0.5 mA). This limits
power dissipation on the device in the event that the VCC pin
is shorted to ground. Once VCC rises back above VCC(inhibit),
the start−up current returns to Istart2.
Once VCC reaches VCC(on), the controller is enabled and
the controller bias current increases to ICC3 (typically
2.0 mA). However, the total bias current is greater than this
due to the gate charge of the external switching MOSFET.
The increase in ICC due to the MOSFET is calculated using
Equation 1.
DICC +fsw @QG@10−3(eq. 1)
where DICC is the increase in milliamps, fsw is the switching
frequency in kilohertz and QG is the gate charge of the
external MOSFET in nanocoulombs.
CVCC must be sized such that a VCC voltage greater than
VCC(off) is maintained while the auxiliary supply voltage
increases during start−up. If CVCC is too small, VCC will fall
below VCC(off) and the controller will turn off before the
auxiliary winding supplies the IC. The total ICC current after
the controller is enabled (ICC3 plus DICC) must be
considered to correctly size CVCC.
NCP1342
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13
DRIVER
The NCP1342 maximum supply voltage, VCC(MAX), is
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp to limit the gate voltage on the external
MOSFETs. The DRV voltage clamp, VDRV(high) is typically
12 V with a maximum limit of 14 V.
REGULATION CONTROL
Peak Current Control
The NCP1342 is a peak current−mode controller, thus the
FB voltage sets the peak current flowing in the transformer
and the MOSFET. This is achieved by sensing the MOSFET
current across a resistor and applying the resulting voltage
ramp to the non−inverting input of the PWM comparator
through the CS pin. The current limit threshold is set by
applying the FB voltage divided by KFB (typically 4) to the
inverting input of the PWM comparator. When the current
sense voltage ramp exceeds this threshold, the output driver
is turned off, however, the peak current is affected by several
functions (see Figure 7):
The peak current level is clamped during the soft−start
phase. The setpoint is actually limited by a clamp level
ramping from 0 to 0.8 V within 4 ms.
In addition to the PWM comparator, a dedicated
comparator monitors the current sense voltage, and if it
reaches the maximum value, VILIM (typically 800 mV), the
gate driver is turned off and the overload timer is enabled.
This occurs even if the limit imposed by the feedback
voltage is higher than VILIM1. Due to the parasitic
capacitances of the MOSFET, a large voltage spike often
appears on the CS Pin at turn−on. To prevent this spike from
falsely triggering the current sense circuit, the current sense
signal is blanked for a short period of time, tLEB1 (typically
275 ns), by a leading edge blanking (LEB) circuit. Figure 7
shows the schematic of the current sense circuit.
The peak current is also limitied to a minimum level,
VCS(MIN) (0.2 V, typically). This results in higher efficiency
at light loads by increasing the minimum energy delivered
per switching cycle, while reducing the overall number of
switching cycles during light load.
Figure 7. Current Sense Logic
*
+
*
+
*
+
*
+
*
+
FB
CS
ZCD/OPP
VILIM1 VCS(MIN)
VILIM2
VFB(open)
OCP
PWM
Minimum Peak
Current
AOCP
Soft−Start
Ramp
DRV Off
Overload Timer
Abnormal OCP Counter
KFB
OPP
tLEB1
tLEB2
RFB
ROPP
Rsense
NCP1342
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14
Zero Current Detection
The NCP1342 is a quasi−resonant (QR) flyback
controller. While the power switch turn−off is determined by
the peak current set by the feedback loop, the switch turn−on
is determined by the transformer demagnetization. The
demagnetization is detected by monitoring the transformer
auxiliary winding voltage.
Turning on the power switch once the transformer is
demagnetized has the benefit of reduced switching losses.
Once the transformer is demagnetized, the drain voltage
starts ringing at a frequency determined by the transformer
magnetizing inductance and the drain lump capacitance,
eventually settling at the input voltage. A QR flyback
controller takes advantage of the drain voltage ringing and
turns on the power switch at the drain voltage minimum or
“valley” to reduce switching losses and electromagnetic
interference (EMI).
As shown by Figure 13, a valley is detected once the ZCD
pin voltage falls below the demagnetization threshold,
VZCD(trig), typically 55 mV. The controller will either switch
once the valley is detected or increment the valley counter,
depending on the FB voltage.
Overpower Protection
The average bulk capacitor voltage of the QR flyback
varies with the RMS line voltage. Thus, the maximum
power capability at high line can be much higher than
desired. An integrated overpower protection (OPP) circuit
provides a relatively constant output power limit across the
input voltage on the bulk capacitor, Vbulk. Since it is a
high−voltage rail, directly measuring Vbulk will contribute
losses in the sensing network that will greatly impact the
standby power consumption. The NCP1342 OPP circuit
achieves this without the need for a high−voltage sensing
network, and is essentially lossless.
Figure 8. OPP Circuit Schematic
FB
CS
ZCD/OPP
VFB(open)
RFB
tLEB1
KFB
VOPP
VILIM1
PWM
OCP
DRV Off
NCP1342
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15
AUX
BULK
P
NV
N
⎛
−⎢
⎝
VAUX (V)
Figure 9. Auxiliary Winding Voltage
⎛
⎢
⎝
.
Since the auxiliary winding voltage during the power
switch on time is a reflection of the input voltage scaled by
the primary to auxiliary winding turns ratio, NP:AUX (see
Figure 9), OPP is achieved by scaling down reflected
voltage during the on−time and applying it to the ZCD pin
as a negative voltage, VOPP
. The voltage is scaled down by
a resistor divider comprised of ROPPU and ROPPL. The
maximum internal current setpoint (VCS(OPP)) is simply the
sum of VOPP and the peak current sense threshold, VILIM1.
Figure 8 shows the schematic for the OPP circuit.
The adjusted peak current limit is calculated using
Equation 2. For example, a VOPP of −150 mV results in a
peak current limit of 650 mV in NCP1342.
VCS(OPP) +VOPP )VILIM1 (eq. 2)
To ensure optimal zero−crossing detection, a diode is
needed to bypass ROPPU during the off−time. Equation 3 is
used to calculate ROPPU and ROPPL.
RZCD )ROPPU
ROPPL +*NP:AUX @Vbulk *VOPP
VOPP
(eq. 3)
ROPPU is selected once a value is chosen for ROPPL.
ROPPL is selected large enough such that enough voltage is
available for the zero−crossing detection during the
off−time. It is recommended to have at least 8 V applied on
the ZCD pin for good detection. The maximum voltage is
internally clamped to VCC. The off−time voltage on the ZCD
Pin is given by Equation 4.
VZCD +ROPPL
RZCD )ROPPL @ǒVAUX *VFǓ(eq. 4)
Where VAUX is the voltage across the auxiliary winding
and VF is the DOPP forward voltage drop.
The ratio between RZCD and ROPPL is given by
Equation 5. It is obtained by combining Equations 3 and 4.
RZCD
ROPPL +VAUX *VF*VZCD
VZCD
(eq. 5)
A design example is shown below:
System Parameters:
VAUX +18 V
VF+0.6 V
NP:AUX +0.18
The ratio between RZCD and ROPPL is calculated using
Equation 5 for a minimum VZCD of 8 V.
RZCD
ROPPL +18 V *0.6 V *8V
8V +1.2 kW
RZCD is arbitrarily set to 1 kW. ROPPL is also set to 1 kW
because the ratio between the resistors is close to 1.
The NCP1342 maximum overpower compensation or
peak current setpoint reduction is 31.25% for a VOPP of
−250 mV. We will use this value for the following example:
Substituting values in Equation 3 and solving for ROPPU
we obtain:
ROPPU +271 @ROPPL *RZCD
ROPPU +271 @1kW*1kW+270 kW
RZCD )ROPPU
ROPPL +0.18 @370 V *(−0.25 V)
−0.25 V +271
For optimum performance over temperature, it is
recommended to keep ROPPL below 3 kW.
NCP1342
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16
Soft−Start
Soft−start is achieved by ramping up an internal reference,
VSSTART, and comparing it to the current sense signal.
VSSTART ramps up from 0 V once the controller initially
powers up. The peak current setpoint is then limited by the
VSSTART ramp resulting in a gradual increase of the switch
current during start−up. The soft−start duration, tSSTART, is
typically 4 ms.
During startup, demagnetization phases are long and
difficult to detect since the auxiliary winding voltage is very
small. In this condition, the 6 ms steady−state timeout is
generally shorter than the inductor demagnetization period.
If it is used to restart a switching cycle, it can cause operation
in CCM for several cycles until the voltage on the ZCD pin
is high enough to prevent the timer from running. Therefore,
a longer timeout period, ttout1 (typically 100 ms), is used
during soft−start to prevent CCM operation.
Frequency Jittering
In order to help meet stringent EMI requirements, the
NCP1342 features frequency jittering to average the energy
peaks over the EMI frequency range. As shown in Figure 10,
the function consists of summing a triangular wave of
amplitude Vjitter and frequency fjitter with the CS signal
immediately before the PWM comparator. This current acts
to modulate the on−time and hence the operation frequency.
Figure 10. Jitter Implementation
FB
VILIM1
CS LEB
KFB
Vjitter
RFB
VDD
VCS(MIN)
DRV Off
VOPP
Since the jittering function modulates the peak current
level, the FB signal will attempt to compensate for this effect
in order to limit the output voltage ripple. Therefore, the
bandwidth of the feedback loop must be well below the jitter
frequency, or the jitter function will be filtered by the loop.
Due to the minimum peak current, the effect of the
jittering circuit will not be seen during frequency foldback
mode.
Maximum Frequency Clamp
All 9−pin versions of the NCP1342 include an adjustable
maximum frequency clamp via an external resistor from the
FMAX Pin to ground. It can also be disabled by pulling the
FMAX pin above 4 V. The maximum frequency can be
programmed using Equation 6, and is shown in Figure 11.
FSW(MAX) +
261 kHz * 1 V
RFMAX *10mA
(eq. 6)
Figure 11. FSW(MAX) vs. RFMAX
1000
900
800
700
600
500
400
300
200
100
0
0 50 100 150 200 250 250300 350
RFMAX (kW)
FSW(MAX) (kHz)
NCP1342
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LIGHT LOAD MANAGEMENT
Valley Lockout Operation
The operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. In
other words, a load reduction increases the operating
frequency. A maximum frequency clamp can be useful to
limit the operating frequency range. However, when used by
itself, such an approach often causes instabilities since when
this clamp is active, the controller tends to jump (or hesitate)
between two valleys, thus generating audible noise.
Instead, the NCP1342 also incorporates a patented valley
lockout (VLO) circuitry to eliminate valley jumping. Once
a valley is selected, the controller stays locked in this valley
until the output power changes significantly. This technique
extends the QR mode operation over a wider output power
range while maintaining good efficiency and limiting the
maximum operating frequency.
The operating valley (1st, 2nd, 3rd, 4
th, 5th or 6th) is
determined by the FB voltage. An internal counter
increments each time a valley is detected by the ZCD/OPP
Pin. Figure 12 shows a typical frequency characteristic
obtainable at low line in a 65 W application.
0 20 40 60
0
210
4
x
410
4
x
610
4
x
810
4
x
110
5
x
Pout (W)
Fsw (Hz)
1st
2nd
3rd
4th
5th
6th
VCO
mode
1st
2nd
3rd
4th
5th
6th
VCO
mode
Figure 12. Valley Lockout Frequency vs. Output Power
When an “n” valley is asserted by the valley selection
circuitry, the controller is locked in this valley until the FB
voltage decreases to the lower threshold (“n+1” valley
activates) or increases to the “n valley threshold” + 600 mV
(“n−1” valley activates). The regulation loop adjusts the
peak current to deliver the necessary output power. Each
valley selection comparator features a 600 mV hysteresis
that helps stabilize operation despite the FB voltage swing
produced by the regulation loop.
Table 7. VALLEY FB THRESHOLDS (typical values)
FB Falling FB Rising
1s
t
to 2n
d
valley 1.400 V 2n
d
to 1s
t
valley 2.000 V
2n
d
to 3r
d
valley 1.200 V 3r
d
to 2n
d
valley 1.800 V
3r
d
to 4
th
valley 1.100 V 4
th
to 3r
d
valley 1.700 V
4
th
to 5
th
valley 1.000 V 5
th
to 4
th
valley 1.600 V
5
th
to 6
th
valley 0.900 V 6
th
to 5
th
valley 1.500 V
Valley Timeout
In case of extremely damped oscillations, the ZCD
comparator may not be able to detect the valleys. In this
condition, drive pulses will stop while the controller waits
for the next valley or ZCD event. The NCP1342 ensures
continued operation by incorporating a maximum timeout
period after the last demagnetization detection. The timeout
signal acts as a substitute for the ZCD signal to the valley
counter. Figure 13 shows the valley timeout circuit
schematic. The steady state timeout period, ttout2, is set at 6
ms (typical) to limit the frequency step.
During startup, the voltage offset added by the OPP diode,
DOPP
, prevents the ZCD Comparator from accurately
detecting the valleys. In this condition, the steady state
NCP1342
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18
timeout period will be shorter than the inductor
demagnetization period causing CCM operation. CCM
operation lasts for a few cycles until the voltage on the ZCD
pin is high enough to detect the valleys. A longer timeout
period, ttout1, (typically 100 ms) is set during soft−start to
limit CCM operation.
In VLO operation, the number of timeout periods are
counted instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For example, if
the FB voltage sets VLO mode to turn on at the fifth valley,
and the ZCD ringing is damped such that the ZCD circuit is
only able to detect:
•Valleys 1 to 4: the circuit generates a DRV pulse 6 ms
(steady−state timeout delay) after the 4th valley
detection.
•Valleys 1 to 3: the timeout delay must run twice, and
the circuit generates a DRV pulse 12 ms after the 3rd
valley detection.
Figure 13. Valley Timeout Circuitry
Rapid Frequency Foldback with Minimum Peak
Current Modulation (MPCM)
As the output load decreases (FB voltage decreases), the
valleys are incremented from 1 to 6. When the sixth valley
is reached and the FB voltage further decreases to
VMPCM(entry) (800 mV typical), the controller enters MPCM
and begins frequency foldback (FF). At this point, the
minimum peak current is increased by VMPCM(delta)
(400 mV typical). The increase in peak current serves to
force the switching frequency to a much lower value, thus
improving the efficiency at light loads. During this mode,
the controller regulates the power delivery by modulating
the switching frequency.
Once in frequency foldback mode, the controller reduces
the switching frequency by adding dead−time after the 6th
valley is detected. This dead−time increases as the FB
voltage decreases.
The dead−time circuit is designed to add 0 ms dead−time
when VFB = 0.4 V and linearly increases the total dead−time
to tDT(MAX) (36 ms typical) as VFB falls down to 0.4 V. The
minimum frequency clamp prevents the switching
frequency from dropping below 25 kHz to eliminate the risk
of audible noise. Note that the dead−time is not added (it is
blanked) until MPCM is engaged to ensure valley switching
prior to entering MPCM mode.
In addition to dead−time, the peak current setpoint is
linearly reduced as VFB falls down to 0.4 V. This ensures that
the peak current is not too high during the lightest loads, and
has the effect of reducing the skip entry power level.
Figure 14 shows the MPCM with respect to the feedback
voltage, while Figure 15 shows the VLO to FF operation.
To reduce the output power hysteresis between entering
and exiting MPCM, the exit threshold (VMPCM(exit)) is set
slightly below the entry threshold (750 mV typical). A 1 ms
timer, tMPCM, is engaged every time MPCM is entered or
exited to prevent oscillations during the operating point
transition. If at any time FB falls to skip mode, or rises to 5th
valley, MPCM will be immediately exited regardless of
tMPCM.
NCP1342
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19
Figure 14. Minimum Peak Current Modulation
VFB
Minimum Peak Current
Vskip
VCS(MIN)
VCS(MIN) + VMPCM(delta)
VMPCM(delta)
VMPCM(entry)
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
Valley 1
3.2
1.61.51.41.11.00.90.8 1.2 VFB (V)
Fault !
Operating Mode
Valley 3
Valley 4
Valley 5
Valley 6
FF
Valley 2
2.01.81.7
VFB decreases
VFB increases
Figure 15. Valley Lockout Thresholds
NCP1342
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Minimum Frequency Clamp and Skip Mode
As mentioned previously, the circuit prevents the
switching frequency from dropping below fMIN (25 kHz
typical). When the switching cycle would be longer than
40 ms, the circuit forces a new switching cycle. However, the
fMIN clamp cannot generate a DRV pulse until the
demagnetization is completed. In other words, it will not
cause operation in CCM.
Since the NCP1342 forces a minimum peak current and a
minimum frequency, the power delivery cannot be
continuously controlled down to zero. Instead, the circuit
starts skipping pulses when the FB voltage drops below the
skip level, Vskip, and recovers operation when VFB exceeds
Vskip + Vskip(HYS). This skip−mode method provides an
efficient method of control during light loads.
Quiet−Skip
To further avoid acoustic noise, the circuit prevents the
burst frequency during skip mode from entering the audible
range by limiting it to a maximum of 800 Hz. This is
achieved via a timer (tquiet) that is activated during
Quiet−Skip. The start of the next burst cycle is prevented
until this timer has expired.
As the output power decreases, the switching frequency
decreases. Once it hits 25 kHz, the skip−in threshold is
reached and burst mode is entered − switching stops as soon
as the current drive pulses ends – it does not stop
immediately.
Once switching stops, FB will rise. As soon as FB crosses
the skip−exit threshold, drive pulses will resume, but the
controller remains in burst mode. At this point, a 1.25 ms
timer, tquiet, is started together with a count−to−3 counter.
The next time the FB voltage drops below the skip−in
threshold, drive pulses stop at the end of the current pulse as
long as 3 drive pulses have been counted (if not, they do not
stop until the end of the 3rd pulse). They are not allowed to
start again until the timer expires, even if the skip−exit
threshold is reached first. It is important to note that the
timer will not force the next cycle to begin – i.e. if the natural
skip frequency is such that skip−exit is reached after the
timer expires, the drive pulses will wait for the skip−exit
threshold.
This means that during no−load, there will be a minimum
of 3 drive pulses, and the burst−cycle period will likely be
much longer than 1.25 ms. This operation helps to improve
efficiency at no−load conditions.
In order to exit burst mode, the FB voltage must rise higher
than 1 V. If this occurs before tquiet expires, the drive pulses
will resume immediately – i.e. the controller won’t wait for
the timer to expire. Figure 16 provides an example of how
Quiet−Skip works.
NCP1342
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22
FAULT MANAGEMENT
The NCP1342 contains three separate fault modes.
Depending on the type of fault, the device will either latch
off, restart when the fault is removed, or resume operation
after the auto−recovery timer expires.
Latching Faults
Some faults will cause the NCP1342 to latch off. These
include the abnormal OCP (AOCP), VCC OVP, and the
external latch input. When the NCP1342 detects a latching
fault, the driver is immediately disabled. The operation
during a latching fault is identical to that of a non−latching
fault except the controller will not attempt to restart at the
next VCC(on), even if the fault is removed. In order to clear
the latch and resume normal operation, VCC must first be
allowed to drop below VCC(reset) or a line removal event
must be detected. This operation is shown in Figure 17.
time
Fault
time
VCC
time
FDRV
VCC(on)
VCC(off)
Fault
Applied
time
IHV
Istart 2
Istart(off)
Fault
Removed
Figure 17. Operation During Latching Fault
NCP1342
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23
Non−Latching Faults
When the NCP1342 detects a non−latching fault
(brownout or thermal shutdown), the drivers are disabled,
and VCC falls towards VCC(off) due to the IC internal current
consumption. Once VCC reaches VCC(off), the HV current
source turns on and CVCC begins to charge towards VCC(on).
When VCC, reaches VCC(on), the cycle repeats until the fault
is removed. Once the fault is removed, the NCP1342 is
re−enabled when VCC reaches VCC(on) according to the
initial power−on sequence, provided VHV is above
VBO(start). This operation is shown in Figure 18. When VHV
is reaches VBO(start), VCC immediately charges to VCC(on).
If VCC is already above VCC(on) when the fault is removed,
the controller will start immediately as long as VHV is above
VBO(start).
time
Fault
time
VCC
time
FDRV
VCC (on )
VCC (off )
Waits for next
VCC(on) before
starting
Fault
Applied
time
IHV
Istart 2
Istart (off)
Fault
Removed
Figure 18. Operation During Non−Latching Fault
NCP1342
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24
Auto−recovery Timer Faults
Some faults faults cause the NCP1342 auto−recovery
timer to run. If an auto−recovery fault is detected, the gate
drive is disabled and the auto−recovery timer, tautorec
(typically 1.2 s), starts. While the auto−recovery timer is
running, the HV current source turns on and off to maintain
Vcc between Vcc(off) and Vcc(on). Once the auto−recovery
timer expires, the controller will attempt to start normally at
the next VCC(on) provided VHV is above VBO(start). This
operation is shown in Figure 19.
Figure 19. Operation During Auto−Recovery Fault
time
Fault
time
VCC
time
DRV
VCC(on)
VCC(off)
Fault
Applied
time
Autorecovery
Timer
1.2 s
Controller
stops
Fault
Removed
trestart
Restarts
At VCC(on)
(new burst
cycle if Fault
still present)
NCP1342
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25
PROTECTION FEATURES
Brownout Protection
A timer is enabled once VHV drops below its disable
threshold, VBO(stop) (typically 99 V). The controller is
disabled if VHV doesn’t exceed VBO(stop) before the
brownout timer, tBO (typically 54 ms), expires. The timer is
set long enough to ignore a two cycle dropout. The timer
starts counting once VHV drops below VBO(stop).
Figure 20 shows the brownout detector waveforms during
a brownout.
When a brownout is detected, the controller stops
switching and enters non−latching fault mode (see
Figure 18). The HV current source alternatively turns on and
off to maintain VCC between VCC(on) and VCC(off) until the
input voltage is back above VBO(start).
VCC(on)
VCC (off )
DRV
VCC
Brownout
Timer
VHV
VBO(stop )
VBO(start )
time
time
time
time
tdelay (start )
Starts
Charging
Immediately
Brownout
detected
Restarts at
next V CC(on)
Fault
Cleared
Figure 20. Operation During Brownout
Line Removal Detection and X2 Capacitor Discharge
Safety agency standards require the input filter capacitors
to be discharged once the ac line voltage is removed. A
resistor network is the most common method to meet this
requirement. Unfortunately, the resistor network consumes
power across all operating modes and it is a major
contributor of input power losses during light−load and
no−load conditions.
The NCP1342 eliminates the need for external discharge
resistors by integrating active input filter capacitor
discharge circuitry. A novel approach is used to reconfigure
the high voltage startup circuit to discharge the input filter
capacitors upon removal of the ac line voltage. The line
removal detection circuitry is always active to ensure safety
compliance.
The line removal is detected by digitally sampling the
voltage present at the HV pin, and monitoring the slope.
A timer, tline(removal) (typically 100 ms), is used to detect
when the slope of the input signal is negative or below the
resolution level. The timer is reset any time a positive slope
NCP1342
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26
is detected. Once the timer expires, a line removal condition
is acknowledged initiating an X2 capacitor discharge cycle,
and the controller is disabled.
If VCC is above VCC(on), it is first discharged to VCC(on).
A second timer, tline(discharge) (typically 32 ms), is used for
the time limiting of the discharge phase to protect the device
against overheating. Once the discharge phase is complete,
tline(discharge) is reused while the device checks to see if the
line voltage is reapplied. During the discharge phase, if VCC
drops to VCC(on), it is quickly recharged to VCC(X2_reg). The
discharging process is cyclic and continues until the ac line
is detected again or the voltage across the X2 capacitor is
lower than VHV(discharge) (30 V maximum). This feature
allows the device to discharge large X2 capacitors in the
input line filter to a safe level.
It is important to note that the HV pin cannot be
connected to any dc voltage due to this feature, i.e.
directly to the bulk capacitor.
VBO(start)
VBO(stop)
tline(detect )
VHV(discharge )
tline(removal ) tline(discharge )
tline(discharge )
VCC(X2_reg)
VCC(on)
tline(removal )
tline(discharge /detect )
0
ICC(discharge )
ICC3
Istart2
Istart2
X2 Discharge
Current
VCC
VHV
Timer
DRV
ICC
time
time
X2 Discharge
X2 Capacitor
Discharge
X2 Capacitor
Discharge
Device is stopped
X2 Discharge
No AC Detection
AC Line Unplug
AC
Timer
Starts
AC
Timer
Restarts
AC
Timer
Expires
Figure 21. Line Removal Timing
NCP1342
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27
VBO(start )
VBO(stop )
VHV(discharge )
VCC(X2_reg)
VCC(on)
tline(removal ) tline (discharge )
tline(removal )
tline(discharge /detect )
Istart 2
0
ICC(discharge )
ICC3
Istart 2
time
time
time
time
time
VHV
DRV
VCC
X2 Discharge
Current
Timer
ICC
tdelay (start )
X2 Capacitor
Discharge
AC Line Unplug
Device is stopped X2 Discharge
AC
Timer
Starts
AC
Timer
Restarts
AC
Timer
Expires
AC Detected
Figure 22. Line Removal Timing with AC Reapplied
An over temperature protection block monitors the
junction temperature during the discharge process to avoid
thermal runaway, in particular during open/short pins safety
tests. Please note that the X2 discharge capability is also
active at all times, including off−mode and before the
controller actually starts to pulse (e.g. if the user unplugs the
converter during the start−up sequence).
Dedicated Fault Input
The NCP1342 includes a dedicated fault input accessible
via the Fault pin (8−pin and 9−pin versions only). The
controller can be latched by pulling up the pin above the
upper fault threshold, VFault(OVP) (typically 3.0 V). The
controller is disabled if the Fault pin voltage is pulled below
the lower fault threshold, VFault(OTP_in) (typically 0.4 V).
The lower threshold is normally used for detecting an
overtemperature fault. The controller operates normally
while the Fault pin voltage is maintained within the upper
and lower fault thresholds. Figure 23 shows the architecture
of the Fault input.
The Fault input signal is filtered to prevent noise from
triggering the fault detectors. Upper and lower fault detector
blanking delays, tdelay(OVP) and tdelay(OTP),are both
typically 30 ms. A fault is detected if the fault condition is
asserted for a period longer than the blanking delay.
NCP1342
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28
OVP
An active clamp prevents the Fault pin voltage from
reaching the upper latch threshold if the pin is open. To reach
the upper threshold, the external pull−up current has to be
higher than the pull−down capability of the clamp (set by
RFault(clamp) at VFault(clamp)), i.e., approximately 1 mA.
The upper fault threshold is intended to be used for an
overvoltage fault using a zener diode and a resistor in series
from the auxiliary winding voltage. The controller is latched
once VFault exceeds VFault(OVP).
Once the controller is latched, it follows the behavior of
a latching fault according to Figure 17 and is only reset if
VCC is reduced to VCC(reset), or X2 discharge is activated. In
the typical application these conditions occur only if the ac
voltage is removed from the system.
OTP
The lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor. A pull up
current source, IFault(OTP) (typically 45.0 mA), generates a
voltage drop across the thermistor. The resistance of the
NTC thermistor decreases at higher temperatures resulting
in a lower voltage across the thermistor. The controller
detects a fault once the thermistor voltage drops below
VFault(OTP_in).
The controller bias current is reduced during power up by
disabling most of the circuit blocks including IFault(OTP).
This current source is enabled once VCC reaches VCC(on). A
filter capacitor is typically connected between the Fault and
GND pins. This will result in a delay before VFault reaches
its steady state value once IFault(OTP) is enabled. Therefore,
the lower fault comparator (i.e. overtemperature detection)
is ignored during soft−start.
Version A latches off the controller after an
overtemperature fault is detected according to Figure 17. In
Version B, the controller is re−enabled once the fault is
removed such that VFault increases above VFault(OTP_out),
the auto−recovery timer expires, and VCC reaches VCC(on)
as shown in Figure 19.
Figure 23. Fault Pin Internal Schematic
NCP1342
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29
Overload Protection
The overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault is
present and reduces its count once it is removed. The
overload timer duration, tOVLD, is typically 160 ms. When
the overload timer expires, the controller detects an overload
condition does one of the following:
•The controller latches off (version A) or
•Enters a safe, low duty−ratio auto−recovery mode
(version B).
Figure 24 shows the overload circuit schematic, while
Figure 25 and Figure 26 show operating waveforms for
latched and auto−recovery overload conditions.
Figure 24. Overload Circuitry
FB
CS
ZCD/OPP
VILIM2
VFB(open)
RFB
tLEB1
tLEB2
KFB
VOPP
VILIM1
tOVLD
Count Up
Count Down
Count 4
Abnormal OCP
DRV Off
PWM
OCP + OPP
AOCP
NCP1342
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31
Figure 26. Auto−Recovery Overload Operation
time
Fault Flag
time
VCC
time
DRV
VCC(on)
VCC(off)
Overcurrent
applied
time
Output Load
Max Load
time
Fault timer
160 ms
Fault
timer
starts
Controller
stops
Fault
disappears
tOVLD trestart
Restarts
At VCC(on)
(new burst
cycle if Fault
still present)
tdelay(start)
NCP1342
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32
Abnormal Overcurrent Protection (AOCP)
Under some severe fault conditions, like a winding
short−circuit, the switch current can increase very rapidly
during the on−time. The current sense signal significantly
exceeds VILIM1, but because the current sense signal is
blanked by the LEB circuit during the switch turn−on, the
power switch current can become huge and cause severe
system damage.
The NCP1342 protects against this fault by adding an
additional comparator for Abnormal Overcurrent Fault
detection. The current sense signal is blanked with a shorter
LEB duration, tLEB2, typically 125 ns, before applying it to
the Abnormal Overcurrent Fault Comparator. The voltage
threshold of the comparator, VILIM2, typically 1.2 V, is set
50% higher than VILIM1, to avoid interference with normal
operation. Four consecutive Abnormal Overcurrent faults
cause the controller to enter latch mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
Fault Overcurrent Comparator.
Current Sense Pin Failure Protection
A 1 mA (typically) pull−up current source, ICS, pulls up the
CS pin to disable the controller if the pin is left open.
Additionally, the maximum on−time, ton(MAX) (32 ms
typically), prevents the MOSFET from staying on
permanently if the CS Pin is shorted to GND.
Output Short Circuit Protection
During an output short−circuit, there is not enough
voltage across the secondary winding to demagnetize the
core. Due to the valley timeout feature of the controller, the
flux level will quickly walk up until the core saturates. This
can cause excessive stress on the primary MOSFET and
secondary diode. This is not a problem for the NCP1342,
however, because the valley timeout timer is disabled while
the ZCD Pin voltage is above the arming threshold. Since the
leakage energy is high enough to arm the ZCD trigger, the
timeout timer is disabled and the next drive pulse is delayed
until demagnetization occurs.
VCC Overvoltage Protection
An additional comparator on the VCC pin monitors the
VCC voltage. If VCC exceeds VCC(OVP), the gate drive is
disabled and the NCP1342 follows the operation of a
latching fault (see Figure 17).
Thermal Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of the controller. The controller is
disabled if the junction temperature exceeds the thermal
shutdown threshold, TSHDN (typically 140°C). When a
thermal shutdown fault is detected, the controller enters a
non−latching fault mode as depicted in Figure 18. The
controller restarts at the next VCC(on) once the junction
temperature drops below below TSHDN by the thermal
shutdown hysteresis, TSHDN(HYS), typically 40°C.
The thermal shutdown is also cleared if VCC drops below
VCC(reset), or a line removal fault is detected. A new power
up sequence commences at the next VCC(on) once all the
faults are removed.
NCP1342
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33
TYPICAL CHARACTERISTICS
17.14
17.12
17.1
17.08
17.06
17.04
17.02
17
16.98
16.96
16.94
−40 12010080−20 0 20 6040
VCC(on) (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. VCC(on) vs. Temperature
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 28. VCC(off) vs. Temperature
9
VCC(off) (V)
8.99
8.98
8.97
8.96
8.95
8.94
8.93
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. Istart1 vs. Temperature
0.6
Istart1 (mA)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 30. Istart2 vs. Temperature
5
Istart2 (mA)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. IHV(off1) vs. Temperature
7
IHV(off1) (mA)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 32. IHV(off2) vs. Temperature
9
IHV(off2) (mA)
8
7
6
5
4
3
2
1
0
0.5
0.4
0.3
0.2
0.1
0
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
6
5
4
3
2
1
0
NCP1342
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34
TYPICAL CHARACTERISTICS
0.126
−40 12010080−20 0 20 6040
ICC1 (mA)
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. ICC1 vs. Temperature
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 34. ICC2 vs. Temperature
0.255
ICC2 (mA)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. ICC3 vs. Temperature
1.075
ICC3 (mA)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 36. VCC(OVP) vs. Temperature
28.35
VCC(OVP) (V)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 37. ICC(discharge) vs. Temperature
19.8
ICC(discharge) (mA)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 38. VBO(start) vs. Temperature
112.6
VBO(start) (V)
0.124
0.122
0.120
0.118
0.116
0.114
0.112
0.110
0.108
0.106
0.250
0.245
0.240
0.235
0.230
0.225
0.220
1.070
1.065
1.060
1.055
1.050
1.045
1.040
1.035
1.030
28.3
28.25
28.2
28.15
28.1
19.6
19.4
19.2
19
18.8
18.6
18.4
18.2
18
17.8
17.6
112.4
112.2
112
111.8
111.6
111.4
111.2
110
110.8
NCP1342
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35
TYPICAL CHARACTERISTICS
98.2
−40 12010080−20 0 20 6040
VBO(stop) (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 39. VBO(stop) vs. Temperature
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 40. tDRV(rise) vs. Temperature
90
tDRV(rise) (ns)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 41. tDRV(fall) vs. Temperature
45
tDRV(fall) (ns)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 42. fMAX1 vs. Temperature
111.8
fMAX1 (kHz)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 43. fMAX2 vs. Temperature
367
fMAX2 (kHz)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 44. fMAX3 vs. Temperature
73.45
fMAX3 (kHz)
98
97.8
97.6
97.4
97.2
97
111.6
111.4
111.2
111
110.8
110.6
110.4
110.2
366.5
366
365.5
365
364.5
364
363.5
363
362.5
73.4
73.35
73.3
73.25
73.2
73.15
73.1
73.05
73
80
70
60
50
40
30
20
10
0
CDRV = 100 pF
CDRV = 1 nF
40
35
30
25
20
15
10
5
0
CDRV = 100 pF
CDRV = 1 nF
NCP1342
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36
TYPICAL CHARACTERISTICS
32.5
−40 12010080−20 0 20 6040
ton(MAX) (ms)
TJ, JUNCTION TEMPERATURE (°C)
Figure 45. ton(MAX) vs. Temperature
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 46. VZCD(trig) vs. Temperature
63.6
VZCD(trig) (mV)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 47. VZCD(HYS) vs. Temperature
25.65
VZCD(HYS) (mV)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 48. VZCD(MAX) vs. Temperature
12.95
VZCD(MAX) (V)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 49. VZCD(MIN) vs. Temperature
0
VZCD(MIN) (V)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 50. Vfreeze vs. Temperature
198.8
Vfreeze (mV)
32.4
32.3
32.2
32.1
32
31.9
31.8
31.7
63.5
63.4
63.3
63.2
63.1
63
25.6
25.55
25.5
25.45
25.4
25.35
12.9
12.85
12.8
12.75
12.7
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
198.6
198.4
198.2
198
197.8
197.6
NCP1342
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37
TYPICAL CHARACTERISTICS
1.31
−40 12010080−20 0 20 6040
fjitter (kHz)
TJ, JUNCTION TEMPERATURE (°C)
Figure 51. fjitter vs. Temperature
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 52. Vjitter vs. Temperature
104.2
Vjitter (mV)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 53. VFault(OVP) vs. Temperature
3.1
VFault(OVP) (V)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 54. VFault(OTP_in) vs. Temperature
402.5
VFault(OTP_in) (mV)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 55. VFault(OTP_out) vs. Temperature
920
VFault(OTP_out) (mV)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 56. IOTP vs. Temperature
45.1
IOTP (mA)
1.308
1.306
1.304
1.302
1.3
1.298
1.296
1.294
3.09
3.08
3.07
3.06
3.05
3.04
3.03
45
44.9
44.8
44.7
44.6
44.5
44.4
44.3
402
401.5
401
400.5
400
399.5
399
918
916
914
912
910
908
906
104
103.8
103.6
103.4
103.2
103
102.8
NCP1342
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38
TYPICAL CHARACTERISTICS
1.731
−40 12010080−20 0 20 6040
VFault(clamp) (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 57. VFault(clamp) vs. Temperature
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 58. RFault(clamp) vs. Temperature
1.55
RFault(clamp) (kW)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 59. fMIN vs. Temperature
24.5
fMIN (kHz)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 60. tquiet vs. Temperature
1.39
tquiet (ms)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 61. tZCD(blank) vs. Temperature
840
tZCD(blank) (ns)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 62. VILIM1 vs. Temperature
0.8
VILIM1 (V)
1.73
1.729
1.728
1.727
1.726
1.545
1.54
1.535
1.53
1.525
1.52
1.515
1.51
1.505
1.5
1.495
24.45
24.4
24.35
24.3
24.25
24.2
24.15
24.1
24.05
24
0.799
0.798
0.797
0.796
0.795
0.794
0.793
1.385
1.38
1.375
1.37
1.365
830
820
810
800
790
780
NCP1342
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39
TYPICAL CHARACTERISTICS
1.202
−40 12010080−20 0 20 6040
VILIM2 (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 63. VILIM2 vs. Temperature
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
40
tDT(MAX) (ms)
−40 12010080−20 0 20 6040
TJ, JUNCTION TEMPERATURE (°C)
Figure 64. tDT(MAX) vs. Temperature
399
Vskip (mV)
1.201
1.2
1.199
1.198
1.197
1.196
1.195
1.194
1.193
398.5
398
397.5
397
396.5
396
Figure 65. Vskip vs. Temperature
39.9
39.8
39.7
39.6
39.5
39.4
39.3
39.2
39.1
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(Pb−Free)
XXXXX
ALYWX
G
1
8
IC
(Pb−Free)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−9 NB
CASE 751BP
ISSUE A
DATE 21 NOV 2011
SEATING
PLANE
1
5
610
h
X 45 _
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DE-
TERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERM-
INED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
D
E
H
A1
A
SCALE 1:1
DIM
D
MIN MAX
4.80 5.00
MILLIMETERS
E3.80 4.00
A1.25 1.75
b0.31 0.51
e1.00 BSC
A1 0.10 0.25
A3 0.17 0.25
L0.40 1.27
M0 8
H5.80 6.20
C
M
0.25
M
__
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
9
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
XXXXX
ALYWX
G
1
9
h0.37 REF
L2 0.25 BSC
A
C0.20
4 TIPS
TOP VIEW
C0.20
5 TIPS A-B D
C0.10 A-B
2X
C0.10 A-B
2X
e
C0.10
b9X
B
C
C0.10
9X
SIDE VIEW END VIEW
DETAIL A
6.50
9X 1.18
9X 0.58 1.00
PITCH
RECOMMENDED
1
L
F
SEATING
PLANE
C
L2 A3
DETAIL A
D
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON52301E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC−9 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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