SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ’ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide
true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding
10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The output-enable input does not affect the internal operation of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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2
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5
6
7
8
9
10
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12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
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53
52
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49
48
47
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45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
SN54ABT16841 . . . WD PACKAGE
SN74ABT16841 . . . DL PACKAGE
(TOP VIEW)
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16841 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16841 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit latch)
INPUTS OUTPUT
OE LE DQ
L H H H
LHL L
LLX Q
0
H X X Z
logic symbol†
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1Q1
2
1Q2
3
1Q3
5
1Q4
6
1Q5
8
1D
55
1D1 54
1D2 52
1D3 51
1D4 49
1D5 48
1D6 47
1D7 45
1D8 44
1D9 43
1D10
1Q6
9
1Q7
10
1Q8
12
1Q9
13
1Q10
14
3D
42
2D1 41
2D2 40
2D3 38
2D4 37
2D5
2Q1
15
2Q2
16
2Q3
17
2Q4
19
2Q5
20
36
2D6 34
2D7 33
2D8 31
2D9 30
2D10
2Q6
21
2Q7
23
2Q8
24
2Q9
26
2Q10
27
EN2
1
C1
56
1LE
EN4
28
C3
29
2LE
1OE
2OE
2
4
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
To Nine Other Channels
1
56
55 2
1LE
1D1
C1
1D 1Q1
2OE
To Nine Other Channels
28
29
42 15
2LE
2D1
C1
1D 2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16841 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16841 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16841 SN74ABT16841
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT16841 SN74ABT16841
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VOH
VCC = 5 V, IOH = –3 mA 3 3 3
V
V
OH
VCC =45V
IOH = –24 mA 2 2
V
V
CC =
4
.
5
V
IOH = –32 mA 2* 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55* 0.55
V
Vhys 100 mV
II
VCC = 0 to 5.5 V, VI = VCC or GND ±1±1
µA
I
IVCC = 5 V, VI = VCC or GND ±5µ
A
IOZPU‡VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
IOZPD‡VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
IOZH VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE ≥ 2 V 10 10 10 µA
IOZL VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
ICEX Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
IO§VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
Outputs high
V55VI0
0.5 0.5
ICC Outputs low VCC = 5.5 V, IO = 0,
VI=V
CC or GND
89 89 89 mA
Outputs disabled
VI
=
VCC
or
GND
0.5 0.5 0.5
∆ICCVCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1.5 1.5 1.5 mA
CiVI = 2.5 V or 0.5 V 3.5 pF
CoVO = 2.5 V or 0.5 V 7.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†All typical values are at VCC = 5 V.
‡This parameter is characterized, but not production tested.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT16841
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
twPulse duration, LE high or low 4 4 ns
tsu Setup time, data before LE↓3 3 ns
thHold time, data after LE↓2.6 2.6 ns
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT16841
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
twPulse duration, LE high or low 4 4 ns
tsu Setup time, data before LE↓1 1 ns
thHold time, data after LE↓2 2 ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT16841
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
D
Q
1.1 3.2 4.3 1.1 5.7
ns
tPHL
D
Q
1.6 3.5 4.5 1.6 5.3
ns
tPLH
LE
Q
1.1 3.2 4.4 1.1 5.6
ns
tPHL
LE
Q
1.6 3.4 5 1.6 5.5
ns
tPZH
OE
Q
1.2 3.2 4.7 1.2 5.8
ns
tPZL
OE
Q
1.7 3.6 5 1.7 5.7
ns
tPHZ
OE
Q
2.2 4.1 6.6 2.2 7.7
ns
tPLZ
OE
Q
1.9 4.4 5.8 1.2 8.4
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT16841
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
D
Q
1.1 3.2 4.3 1.1 5
ns
tPHL
D
Q
1.6 3.5 4.5 1.6 5.1
ns
tPLH
LE
Q
1.1 3.2 4.4 1.1 5
ns
tPHL
LE
Q
1.6 3.4 4.6 1.6 5
ns
tPZH
OE
Q
1.2 3.2 4.7 1.2 5.7
ns
tPZL
OE
Q
1.7 3.6 5 1.7 5.6
ns
tPHZ
OE
Q
2.2 4.1 5.7 2.2 6.5
ns
tPLZ
OE
Q
1.9 4.4 5.8 1.9 7.1
ns
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2. 5 ns , t f≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9564601QXA ACTIVE CFP WD 56 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9564601QX
A
SNJ54ABT16841W
D
SN74ABT16841DL ACTIVE SSOP DL 56 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841
SN74ABT16841DLG4 ACTIVE SSOP DL 56 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841
SN74ABT16841DLR ACTIVE SSOP DL 56 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841
SN74ABT16841DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841
SNJ54ABT16841WD ACTIVE CFP WD 56 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9564601QX
A
SNJ54ABT16841W
D
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT16841, SN74ABT16841 :
•Catalog: SN74ABT16841
•Military: SN54ABT16841
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ABT16841DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ABT16841DLR SSOP DL 56 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WD (R-GDFP-F**) CERAMIC DUAL FLATPACK
4040176/D 10/97
48 LEADS SHOWN
48
48
25
56
0.610
(18,80)
0.710
(18,03)
0.7400.640
0.390 (9,91)
0.370 (9,40)
0.870 (22,10)
1.130 (28,70)
1
A
0.120 (3,05)
0.075 (1,91)
LEADS**
24
NO. OF
A MIN
A MAX (16,26)
(15,49)
0.025 (0,635)
0.009 (0,23)
0.004 (0,10)
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
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