SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS222C - SEPTEMBER 1992 - REVISED MAY 1997 D D D D D D D D D D SN54ABT16841 . . . WD PACKAGE SN74ABT16841 . . . DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (-32-mA IOH, 64-mA IOL) Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 1Q7 GND 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2Q10 2OE description These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 1D7 GND 1D8 1D9 1D10 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2D10 2LE The 'ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The output-enable input does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS222C - SEPTEMBER 1992 - REVISED MAY 1997 description (continued) When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16841 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT16841 is characterized for operation from -40C to 85C. FUNCTION TABLE (each 10-bit latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol 1 1OE 1LE 56 28 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2D10 29 55 EN2 C1 EN4 C3 1D 54 2 2 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 3D 4 15 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 3 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 2Q10 SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS222C - SEPTEMBER 1992 - REVISED MAY 1997 logic diagram (positive logic) 1 1OE 2OE 56 1LE 2LE C1 55 1D1 2 1D 28 29 C1 1Q1 2D1 42 To Nine Other Channels 15 1D 2Q1 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16841 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16841 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABT16841 SN74ABT16841 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC -24 Low-level output current 48 64 mA t/v Input transition rise or fall rate 10 10 ns/V t/VCC TA Power-up ramp rate 200 Operating free-air temperature -55 High-level input voltage 2 2 0.8 Input voltage 0 Outputs enabled 0 V 0.8 V VCC -32 V -40 mA s/V 200 125 V 85 C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS222C - SEPTEMBER 1992 - REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = -18 mA IOH = -3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN TA = 25C TYP MAX SN54ABT16841 MIN SN74ABT16841 MAX -1.2 MIN -1.2 -1.2 2.5 2.5 2.5 IOH = -3 mA IOH = -24 mA 3 3 3 2 2 IOH = -32 mA IOL = 48 mA 2* UNIT V V 2 0.55 IOL = 64 mA Vhys MAX 0.55 0.55* 0.55 1 1 100 V mV II VCC = 0 to 5.5 V, VI = VCC or GND VCC = 5 V, VI = VCC or GND IOZPU VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X 50 50 50 A IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X 50 50 50 A IOZH VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE 2 V 10 10 10 A IOZL VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE 2 V -10 -10 -10 A 100 A Ioff ICEX IO Outputs high VCC = 0, VCC = 5.5 V, VI or VO 4.5 V VO = 5.5 V VCC = 5.5 V, VO = 2.5 V 5 100 50 -50 -100 Outputs high ICC Outputs low Outputs disabled 50 -50 -180 0.5 5 5 V, V IO = 0, 0 VCC = 5.5 VI = VCC or GND ICC VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Co -180 -50 A 50 A -180 mA mA 0.5 89 89 89 0.5 0.5 0.5 1.5 1.5 1.5 mA 3.5 pF 7.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. This parameter is characterized, but not production tested. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT16841 VCC = 5 V, TA = 25C MIN 4 MIN MAX UNIT MAX tw tsu Pulse duration, LE high or low 4 4 ns Setup time, data before LE 3 3 ns th Hold time, data after LE 2.6 2.6 ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS222C - SEPTEMBER 1992 - REVISED MAY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN74ABT16841 VCC = 5 V, TA = 25C MIN MIN MAX UNIT MAX tw tsu Pulse duration, LE high or low 4 4 ns Setup time, data before LE 1 1 ns th Hold time, data after LE 2 2 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT16841 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, TA = 25C MIN MAX MIN TYP MAX 1.1 3.2 4.3 1.1 5.7 1.6 3.5 4.5 1.6 5.3 1.1 3.2 4.4 1.1 5.6 1.6 3.4 5 1.6 5.5 1.2 3.2 4.7 1.2 5.8 1.7 3.6 5 1.7 5.7 2.2 4.1 6.6 2.2 7.7 1.9 4.4 5.8 1.2 8.4 UNIT ns ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT16841 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VCC = 5 V, TA = 25C MIN MAX MIN TYP MAX 1.1 3.2 4.3 1.1 5 1.6 3.5 4.5 1.6 5.1 1.1 3.2 4.4 1.1 5 1.6 3.4 4.6 1.6 5 1.2 3.2 4.7 1.2 5.7 1.7 3.6 5 1.7 5.6 2.2 4.1 5.7 2.2 6.5 1.9 4.4 5.8 1.9 7.1 UNIT ns ns ns ns 5 SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS222C - SEPTEMBER 1992 - REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) 5962-9564601QXA ACTIVE CFP WD 56 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9564601QX A SNJ54ABT16841W D SN74ABT16841DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841 SN74ABT16841DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841 SN74ABT16841DLR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841 SN74ABT16841DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16841 SNJ54ABT16841WD ACTIVE CFP WD 56 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9564601QX A SNJ54ABT16841W D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT16841, SN74ABT16841 : * Catalog: SN74ABT16841 * Military: SN54ABT16841 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT16841DLR Package Package Pins Type Drawing SSOP DL 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 11.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.67 3.1 16.0 32.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT16841DLR SSOP DL 56 1000 367.0 367.0 55.0 Pack Materials-Page 2 MECHANICAL DATA MCFP010B - JANUARY 1995 - REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91) 0.009 (0,23) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 0.390 (9,91) 0.370 (9,40) 0.370 (9,40) 0.250 (6,35) 48 1 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 25 24 NO. OF LEADS** 48 56 A MAX 0.640 (16,26) 0.740 (18,80) A MIN 0.610 (15,49) 0.710 (18,03) 4040176 / D 10/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA GDFP1-F56 and JEDEC MO -146AB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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