A29L320ATV-70F - AMIC TECHNOLOGY

A29L320A Series

4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only,

Boot Sector Flash Memory

(November, 2012, Version 1.7) AMIC Technology, Corp.

Document Title

4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue April 12, 2006 Preliminary

0.1 Error correction: Top/Bottom device ID code and pin configurations May 25, 2006

0.2 Change Table1 & Program/Erasure time July 3, 2006

1.0 Final version release January 5, 2007 Final

1.1 Modify symbol “L” outline dim ensions in TSOP 48L package November 15, 2007

1.2 Modify Figure 2-1 and Figure 2-2 August 18, 2008

Modify tWHWH1 and tWHWH2

Modify VHH and VID

1.3 Modify A29L320A top block sector 34 address December 12, 2008

1.4 Update VCC supply voltages for extended range devices (-I/-U) April 3, 2009

Modify the WP /ACC operation of write in Table 1

1.5 Remove non Pb-free package type February 8, 2010

1.6 Page 1: Change from typical 100,000 cycles to minimum 100,000 cycles November 25, 2010

1.7 Page 19: CFI query data change from 0001h to 0004h at address 8Eh November 23, 2012

CFI query data change from 0085 h to 00B5h at address 9Ah

CFI query data change from 0095 h to 00C5h at address 9Ch

A29L320A Series

4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only,

Boot Sector Flash Memory

(November, 2012, Version 1.7) 1 AMIC Technology, Corp.

Features

 Single power suppl y operation

- Regulated voltage range of commercial devices: 2.7 to

3.6 volt read and write operations for compatibility with

high performance 3 volt microprocess ors

- Regulated voltage rang e of extended range devices: 3.0

to 3.6 volt read and write operations for compatibility

with high performance 3 volt microprocessors

 Access times:

- 70/80/90/120 (max.)

 Current:

- 2mA active read current at 1M Hz

- 10mA active read curre nt at 5MHz

- 20 mA typical program/erase current

- 500 nA typical CMOS standby or Automatic Sleep Mode

current

 Flexible sector architecture

- Eight 8 Kbyte sectors

- Sixty-three 64 kbyte sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

 Unlock Bypass Program Command

- Reduces overall programming time when issuing

multiple program command sequence

 Top or bottom boot block configurations available

 Embedded Algorithms

- Embedded Erase algorithm will automatically erase the

entire chip or any combination of designated sectors an d

verify the erased sectors

- Embedded Program algorithm automatically writes and

verifies data at specified addresses

 Minimum 100,000 pr ogram/erase cycles per sector

 20-year data retention at 125°C

- Reliable operation for the life of the system

 CFI (Common Flash Interface) compliant

- Provides device-specific information to the system,

allowing host software to easily reconfigure for different

Flash devices

 Compatible with JEDEC-standards

- Pinout and software compatible with single-p ower-supply

Flash memory standard

- Superior in advertent write protection

 Data Polling and toggle bits

- Provides a software method of detecting completion of

program or erase operations

 Ready / BUSY pin (RY / BY)

- Provides a hardware method of detecting completion of

program or erase operations

 Erase Suspend/Erase Resume

- Suspends a sector erase operation to read d ata from, or

program data to, a non-erasing sector, then resumes the

erase operation

 Hardware reset pin (RESET)

- Hardware method to reset the device to reading array

data

 WP /ACC input pin

- Write protect ( WP ) function allows protection of two

outermost boot sectors, regardless of sector protect

status

- Acceleration (ACC) function provides accelerated

program times

 Hardware/Software temporary sector bl ock unprotect

command allows code chang es in previously locked

sectors

 Hardware/Software sector protect/unprotect command

 Package options

- 48-pin TSOP (I) or 48-ball TFBGA

- All Pb-free (Le ad-free) products are RoHS compliant

General Description

The A29L320A is a 32Mbit, 3.3 volt-only Flash memory

organized as 2,097,152 words of 16 bits or 4,194,304 bytes

of 8 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16

bits of data appear on I/O0~I/O15. The A29L320A is offered in

48-ball TFBGA and 48-Pin TSOP packages. This device is

designed to be programmed in-system with the standard

system 3.3 volt VCC supply. Additional 12.0 volt VPP is not

required for in-system write or erase operations. However,

the A29L320A can also be pr ogrammed in standard EPROM

programmers.

The A29L320A has the first toggle bit, I/O6, which indicates

whether an Embedded Progr am or Erase is in progress, or it

is in the Erase Suspend. Besides the I/O6 toggle bit, the

A29L320A has a second toggle bit, I/O2, to indicate whether

the addressed sector is being selected for erase. The

A29L320A also offers the ability to program in the Erase

Suspend mode. T he standard A29L320A offers access time s

of 70,80,90 and 120ns, allo wing high-speed microprocessors

to operate without wait states. To eliminate bus contention

the device has separate chip enable ( CE ), write enable

(WE ) and output enable (OE) controls.

The device requires only a single 3.3 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The A29L320A is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

A29L320A Series

(November, 2012, Version 1.7) 2 AMIC Technology, Corp.

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and

erase operations. Reading da ta out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper pro gram margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm - an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin. The Unlock Bypass mode

facilitates faster programming times by requiring only two

write cycles to program data instead of four.

The host system can detect whether a program or erase

operation is complete by observing the RY / BY pin, or by

reading the I/O7 (Data Polling) and I/O6 (toggle) status bits.

After a program or erase cycle has been completed, the

device is ready to read array data or accept another

command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data

contents of other sectors. The A29L320A is fully erased

when shipped from the factory.

The hardware sector protection feature disables operati ons

for both program and erase in an y combination of the

sectors of memory. This can be achieved via programmin g

equipment.

The Erase Suspend/Erase R esume feature enables the user

to put erase on hold for any period of time to read data from,

or program data to, any other sector that is not selected for

erasure. True backgroun d erase can thus be achieved.

The hardware RESET pin terminates any operation in

progress and resets the internal state machine to reading

array data. The RESET pin may be tied to the system reset

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read the boot-up

firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of time,

the device enters the automatic sleep m ode. T he system can

also place the device into the standby mode. Power

consumption is greatly reduced in both th ese modes.

Pin Configurations

 TSOP (I)

A29L320AV

A14

A13

A12

A11

A10

A20

RESET

WP/ACC

RY/BY

A18

33 I/O2

I/O10

I/O3

I/O11

VCC

I/O4

I/O12

I/O5

I/O13

I/O6

I/O14

I/O7

I/O15(A-1)

VSS

BYTE

A16A15

A19

24 25

32 I/O9

I/O1

I/O8

I/O0

VSS

A17

A29L320A Series

(November, 2012, Version 1.7) 3 AMIC Technology, Corp.

Pin Configurations (continued)

 TFBGA

A6 B6 C6 D6 E6 F6 G6 H6

TFBGA

Top View, Bal l s Fac ing D own

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

A3 B3 C3 D3 E3 F3 G3 H3

A2 B2 C2 D2 E2 F2 G2 H2

A1 B1 C1 D1 E1 F1 G1 H1

A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS

A9 A8 A10 A11 I/O7I/O14 I/O13 I/O6

WE RESET NC A19 I/O5I/O12 VCC I/O4

RY/BY A18 A20 I/O2I/O10 I/O11 I/O3

A7 A17 A6 A5 I/O0I/O8I/O9I/O1

A3 A4 A2 A1 A0 CE OE VSS

WP/ACC

A29L320A Series

(November, 2012, Version 1.7) 4 AMIC Technology, Corp.

Block Diagram

Pin Descriptions

Pin No. Description

A0 - A20 Address Inputs

I/O0 - I/O14 Data Inputs/Outputs

I/O15 Data Input/Output, Word Mode

I/O15 (A-1) A-1 LSB Address Input, Byte Mode

CE Chip Enable

WE Write Enable

OE Output Enabl e

RESET Hardware Reset

BYTE Selects Byte Mode or Word Mode

RY/BY Ready/BUSY- Output

VSS Ground

VCC Power Supply

NC Pin not connected internally

WP /ACC Hardware Write Protect / Acceleration Pin

State

Control

Command

Address Latch

X-decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Cell Matrix

Y-Gating

VCC Detector

PGM Voltage

Generator

Data Latch

Input/Output

Buffers

Erase Voltage

Generator

VCC

VSS

A0-A20

I/O0 - I/O15 (A-1)

Timer

STB

RESET

Sector Switches

BYTE

RY/BY

WP/ACC

A29L320A Series

(November, 2012, Version 1.7) 5 AMIC Technology, Corp.

Absolute Maximum Ratings*

Storage Temperature Plastic Packages. . . -65°C to + 150°C

Ambient Temperature with Power Applied. -55°C to + 125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V

A9, OE & RESET (Note 2) . . . . . . . . . . . . . -0.5V to +12.5V

WP /ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +12.5V

All other pins (Note 1) . . . . . . . . . . . . . . -0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During

voltage transitions, input or I/O pins may undershoot VSS

to -2.0V for periods of up to 20ns. Maximum DC voltage

on input and I/O pins is VCC +0.5V. During voltage

transitions, input or I/O pins may overshoot to VCC +2.0V

for periods up to 20ns.

2. Minimum DC input voltage on A9,OEand RESET is -

0.5V. During voltage transitions, A9, OE and RESET

may overshoot VSS to -2.0V for periods of up to 20ns.

Maximum DC input voltage on A9 is +12.5V which may

overshoot to 14.0V for periods up to 20ns.

3. No more than one out put is shorted at a time. Duration of

the short circuit should not be greater than one second.

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above

those indicated in the operational sections of these

specification is not implied or intended. Exposure to

the absolute maximum rating conditi ons for extended p eriods

may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . . . 0°C to +70°C

Extended Range Devices

Ambient Temperature (TA)

For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

For –I series . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C

VCC Supply Voltages

VCC for commercial devices . . . . . . . . . . . . +2.7V to +3.6V

VCC for extended range devices . . . . . . . . . +3.0V to +3.6V

Operating ranges define those limits between which the

functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. T he command register itself does

not occupy any addressable memor y location. The register is

composed of latches that store the commands, along with

the address and data information needed to execute the

command. The contents of the register serve as inputs to th e

internal state machine. The state machine output s dictate the

function of the device. The appropriate devic e bus operati ons

table lists the inputs and control levels required, and the

resulting output. The following subsections describe each of

these operations in further detail.

Table 1. A29L320A Device Bus Operations

I/O8 - I/O15 Operation CE OE WE RESET

WP/

ACC A0 - A20

(Note 1) I/O0 - I/O7

BYTE =VIH BYTE =VIL

Read L L H H L/H AIN DOUT DOUT

Write L H L H L/H

(Note 3) AIN (Note 4) (Note 4) I/O8~I/O14=High-Z

I/O15=A-1

Accelerated

Program L H L H VHH AIN (Note 4) (Note 4) High-Z

Standby VCC ±

0.3 V X X

VCC ±

0.3 V H X High-Z High-Z High-Z

Output Disable L H H H L/H X High-Z High-Z High-Z

Reset X X X L L/H X

High-Z High-Z High-Z

Sector Protect

(Note 2) L H L VID L/H Sector Address,

A6=L, A1=H, A0=L (Note 4) X X

Sector Unprotect

(Note 2) L H L VID L/H

Sector Address,

A6=H, A1=H, A0=L (Note 4) X X

Temporary Sector

Unprotect X X X VID L/H AIN (Note 4) (Note 4) High-Z

Legend:

L = Logic Low = VIL, H = Logi c High = VIH, VID = 11.5V-12 .5V, VHH = 11.5V-12.5V, X = Don't Care, DIN = Data In, DOUT = Data Ou t, AIN = Address In

Notes:

1. Addresses are A20:A0 in word mode (BYT

=VIH), A20: A-1 in byte mode (BYTE=VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector

Block Protection and Unprotection”.

3. If WP /ACC=VIL, the two outermost boot sectors remain protected. If WP /ACC=VIH, the two outermost boot sector

protection depends on whether they were last protected or unprotected using the method described in

“Sector/Sector Block Protection and Unprotection. If WP/ACC = VHH, all sectors are unprotected.

4. DIN or DOUT as required by command sequence, data polling, or sector protection algo rithm.

A29L320A Series

(November, 2012, Version 1.7) 6 AMIC Technology, Corp.

Word/Byte Configuration

The BYTE pin determines whether the I/O pins I/O15-I/O0

operate in the byte or word configuration. If the BYTE pin is

set at logic ”1”, the device is in word configuration, I/O15-I/O0

are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte

configuration, and only I/O0-I/O7 are active and controlled by

CE and OE. I/O8-I/O14 are tri-stated, and I/O15 pin is used

as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the CE and OE pins to VIL. CE is the power control and

selects the device. OE is the output control and gates array

data to the output pins. WE should remain at VIH all the time

during read operation. The BYTE pin determines whether

the device outputs array data in words and bytes. The

internal state machine is set for reading array data upon

device power-up, or after a hardware reset. This ensures that

no spurious alteration of the memory content occurs during

the power transition. No command is necessary in this mode

to obtain array data. Standard microprocessor read cycles

that assert valid addresses on the device address inputs

produce valid data on the device data outputs. The device

remains enabled for read access until the command register

contents are altered.

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to the

Read Operations Timings diagram for the timing waveforms,

lCC1 in the DC Characteristics table represents the active

current specification for reading arra y data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of

memory), the system must drive WE and CE to VIL, and

OE to VIH. For program operations, the BYTE pin

determines whether the device accepts program data in

bytes or words, Refer to “Word/Byte Configuration” for more

information. The device features an Unlock Bypass mode to

facilitate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required to

program a word or byte, instead of four. The “

Word / Byte Program Command Sequence” section has

details on programming data to the device using both

standard and Unlock Bypass command sequence. An erase

operation can erase one sector, multiple sectors, or the

entire device. The Sector Address Tables indicate the

address range that each s ector occupies. A "sector address"

consists of the address inputs required to uniquely select a

sector. See the "Command Definiti ons" section for details on

erasing a sector or the entire chip, or suspending/resuming

the erase operation.

After the system writes the autoselect command sequence,

the device enters the autoselec t mode. The system can then

read autoselect codes from the internal register (which is

separate from the memory array) on I/O7 - I/O0. Standard

read cycle timings apply in this mode. Refer to the

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

ICC2 in the DC Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O7 - I/O0. Standard read cycle timings and ICC read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Ch aracteristics section for

timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the OE

input.

The device enters the CMOS standb y mode when the CE &

RESET pins are both held at VCC ± 0.3V. (Note that this is a

more restricted voltage range than VIH.) If CEand RESET

are held at VIH, but not within VCC ± 0.3V, the device will be

in the standby mode, but the standby current will be greater.

The device requires the standard access time (tCE) before it

is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

ICC3 and ICC4 in the DC Characteristics tables represent the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy

consumption. The device automatically enables this mode

when addresses remain stable for t ACC +30n s. The automatic

sleep mode is independent of the CE,WE and OE control

signals. Standard address access timings provide new data

when addresses are changed. While in sleep mode, output

data is latched and al ways available to the system. ICC4 in th e

DC Characteristics table represents the automatic sleep

mode current specification.

Output Disable Mode

When the OE input is at VIH, output from the device is

disabled. The output pins are placed in the high impedance

state.

RESET : Hardware Reset Pin

The RESET pin provides a hardware method of resetting

the device to reading array data. When the system drives the

RESET pin low for at least a period of tRP, the device

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

the duration of the RESET pulse. The device also resets the

internal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is

ready to accept another com mand sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET pulse.

When RESET is held at VSS ± 0.3V, the device draws

CMOS standby current (ICC4 ). If RESETis held at VIL but not

within VSS ± 0.3V, the standby current will be greater.

A29L320A Series

(November, 2012, Version 1.7) 7 AMIC Technology, Corp.

The RESET pin may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

If RESET is asserted during a program or erase operation,

the RY/BYpin remains a “0” (busy) until the internal reset

operation is complete, which requires a time tREADY (during

Embedded Algorithms). The system can thus monitor

RY/ BY to determine whether the reset operation is

complete. If RESET is asserted when a program or erase

operation is not executing (RY/ BY pin is “1”), the reset

operation is completed within a time of tREADY (not during

Embedded Algorithms). The system can read data tRH after

the RESET pin return to VIH.

Refer to the AC Characteristics tables for RESET

parameters and diagram.

Table 2. A29L320A Top Boot Block Sector Address Table

Address Range (in h exadecimal)

Sector A20-A12 Sector Size

(Kbytes/ Kwords) Byte Mode (x8) Word Mode (x16)

SA0 000000XXX 64/32 000000 - 00FFFF 000000 - 007FFF

SA1 000001XXX 64/32 010000 - 01FFFF 008000 - 00FFFF

SA2 000010XXX 64/32 020000 - 02FFFF 010000 - 017FFF

SA3 000011XXX 64/32 030000 - 03FFFF 018000 - 01FFFF

SA4 000100XXX 64/32 040000 - 04FFFF 020000 - 027FFF

SA5 000101XXX 64/32 050000 - 05FFFF 028000 - 02FFFF

SA6 000110XXX 64/32 060000 - 06FFFF 030000 - 037FFF

SA7 000111XXX 64/32 070000 - 07FFFF 038000 - 03FFFF

SA8 001000XXX 64/32 080000 - 08FFFF 040000 - 047FFF

SA9 001001XXX 64/32 090000 - 09FFFF 048000 - 04FFFF

SA10 001010XXX 64/32 0A0000 - 0AFFFF 050000 - 057FFF

SA11 001011XXX 64/32 0B0000 - 0BFFFF 058000 - 05FFFF

SA12 001100XXX 64/32 0C0000 - 0CFFFF 060000 - 067FFF

SA13 001101XXX 64/32 0D0000 - 0DFFFF 068000 - 06FFFF

SA14 001110XXX 64/32 0E0000 - 0EFFFF 070000 - 077FFF

SA15 001111XXX 64/32 0F0000 - 0FFFFF 078000 - 07FFFF

SA16 010000XXX 64/32 100000 - 10FFFF 080000 - 087FFF

SA17 010001XXX 64/32 110000 - 11FFFF 088000 - 08FFFF

SA18 010010XXX 64/32 120000 - 12FFFF 090000 - 097FFF

SA19 010011XXX 64/32 130000 - 13FFFF 098000 - 09FFFF

SA20 010100XXX 64/32 140000 - 14FFFF 0A0000 - 0A7FFF

SA21 010101XXX 64/32 150000 - 15FFFF 0A8000 - 0AFFFF

SA22 010110XXX 64/32 160000 - 16FFFF 0B0000 - 0B7FFF

SA23 010111XXX 64/32 170000 - 17FFFF 0B8000 - 0BFFFF

SA24 011000XXX 64/32 180000 - 18FFFF 0C0000 - 0C7FFF

SA25 011001XXX 64/32 190000 - 19FFFF 0C8000 - 0CFFFF

SA26 011010XXX 64/32 1A0000 - 1AFFFF 0D0000 - 0D7FFF

SA27 011011XXX 64/32 1B0000 - 1BFFFF 0D8000 - 0DFFFF

SA28 011100XXX 64/32 1C0000 - 1CFFFF 0E0000 - 0E7FFF

SA29 011101XXX 64/32 1D0000 - 1DFFFF 0E8000 - 0EFFFF

SA30 011110XXX 64/32 1E0000 - 1EFFFF 0F0000 - 0F7FFF

SA31 011111XXX 64/32 1F0000 - 1FFFFF 0F8000 - 0FBFFF

SA32 100000XXX 64/32 200000 - 20FFFF 100000 - 107FFF

SA33 100001XXX 64/32 210000 - 21FFFF 108000 - 10FFFF

SA34 100010XXX 64/32 220000 - 22FFFF 110000 - 117FFF

A29L320A Series

(November, 2012, Version 1.7) 8 AMIC Technology, Corp.

Table 2. A29L320A Top Boot Block Sector Address Table

Address Range (in h exadecimal)

Sector A20-A12 Sector Size

(Kbytes/ Kwords) Byte Mode (x8) Word Mode (x16)

SA35 100011XXX 64/32 230000 - 23FFFF 118000 - 11FFFF

SA36 100100XXX 64/32 240000 - 24FFFF 120000 - 127FFF

SA37 100101XXX 64/32 250000 - 25FFFF 128000 - 12FFFF

SA38 100110XXX 64/32 260000 - 26FFFF 130000 - 137FFF

SA39 100111XXX 64/32 270000 - 27FFFF 138000 - 13FFFF

SA40 101000XXX 64/32 280000 - 28FFFF 140000 - 147FFF

SA41 101001XXX 64/32 290000 - 29FFFF 148000 - 14FFFF

SA42 101010XXX 64/32 2A0000 - 2AFFFF 150000 - 157FFF

SA43 101011XXX 64/32 2B0000 - 2BFFFF 158000 - 15FFFF

SA44 101100XXX 64/32 2C0000 - 2CFFFF 160000 - 167FFF

SA45 101101XXX 64/32 2D0000 - 2DFFFF 168000 - 16FFFF

SA46 101110XXX 64/32 2E0000 - 2EFFFF 170000 - 177FFF

SA47 101111XXX 64/32 2F0000 - 2FFFFF 178000 - 17FFFF

SA48 110000XXX 64/32 300000 - 30FFFF 180000 - 187FFF

SA49 110001XXX 64/32 310000 - 31FFFF 188000 - 18FFFF

SA50 110010XXX 64/32 320000 - 32FFFF 190000 - 197FFF

SA51 110011XXX 64/32 330000 - 33FFFF 198000 - 19FFFF

SA52 110100XXX 64/32 340000 - 34FFFF 1A0000 - 1A7FFF

SA53 110101XXX 64/32 350000 - 35FFFF 1A8000 - 1AFFFF

SA54 110110XXX 64/32 360000 - 36FFFF 1B0000 - 1B7FFF

SA55 110111XXX 64/32 370000 - 37FFFF 1B8000 - 1BFFFF

SA56 111000XXX 64/32 380000 - 38FFFF 1C0000 - 1C7FFF

SA57 111001XXX 64/32 390000 - 39FFFF 1C8000 - 1CFFFF

SA58 111010XXX 64/32 3A0000 - 3AFFFF 1D0000 - 1D7FFF

SA59 111011XXX 64/32 3B0000 - 3BFFFF 1D8000 - 1DFFFF

SA60 111100XXX 64/32 3C0000 - 3CFFFF 1E0000 - 1E7FFF

SA61 111101XXX 64/32 3D0000 - 3DFFFF 1E8000 - 1EFFFF

SA62 111110XXX 64/32 3E0000 - 3EFFFF 1F0000 - 1F7FFF

SA63 111111000 8/4 3F0000 - 3FFFFF 1F8000 - 1F8FFF

SA64 111111001 8/4 3F2000 - 3F3FFF 1F9000 - 1F9FFF

SA65 111111010 8/4 3F4000 - 3F5FFF 1FA000 - 1FAFFF

SA66 111111011 8/4 3F6000 - 3F7FFF 1FB000 - 1FBFFF

SA67 111111100 8/4 3F8000 - 3F9FFF 1FC000 - 1FCFFF

SA68 111111101 8/4 3FA000 - 3FBFFF 1FD000 - 1FDFFF

SA69 111111110 8/4 3FC000 - 3FDFFF 1FE000 - 1FEFFF

SA70 111111111 8/4 3FE000 - 3FFFFF 1FF000 - 1FFFFF

Note:

Address range is A20 : A-1 in byte mode and A20 : A0 in word mode. See “Word/Byte Configuration” section.

A29L320A Series

(November, 2012, Version 1.7) 9 AMIC Technology, Corp.

Table 3. A29L320A Bottom Boot Block Sector Address Table

Address Range (in h exadecimal) Sector A20 -A12 Sector Size

(Kbytes/ Kwords) Byte Mode (x8) Word Mode (x16)

SA0 000000000 8/4 000000 - 001FFF 000000 - 000FFF

SA1 000000001 8/4 002000 - 003FFF 001000 - 001FFF

SA2 000000010 8/4 004000 - 005FFF 002000 - 002FFF

SA3 000000011 8/4 006000 - 007FFF 003000 - 003FFF

SA4 000000100 8/4 008000 - 009FFF 004000 - 004FFF

SA5 000000101 8/4 00A000 - 00BFFF 005000 - 0 05FFF

SA6 000000110 8/4 00C000 - 00DFFF 006000 - 006FFF

SA7 000000111 8/4 00E000 - 00FFFF 007000 - 007FFF

SA8 000001XXX 64/32 010000 - 01FFFF 008000 - 00FFFF

SA9 000010XXX 64/32 020000 - 02FFFF 010000 - 017FFF

SA10 000011XXX 64/32 030000 - 03FFFF 018000 - 01FFFF

SA11 000100XXX 64/32 040000 - 04FFFF 020000 - 027FFF

SA12 000101XXX 64/32 050000 - 05FFFF 028000 - 02FFFF

SA13 000110XXX 64/32 060000 - 06FFFF 030000 - 037FFF

SA14 000111XXX 64/32 070000 - 07FFFF 038000 - 03FFFF

SA15 001000XXX 64/32 080000 - 08FFFF 040000 - 047FFF

SA16 001001XXX 64/32 090000 - 09FFFF 048000 - 04FFFF

SA17 001010XXX 64/32 0A0000 - 0AFFFF 050000 - 057FFF

SA18 001011XXX 64/32 0B0000 - 0BFFFF 058000 - 05FFFF

SA19 001100XXX 64/32 0C0000 - 0CFFFF 060000 - 067FFF

SA20 001101XXX 64/32 0D0000 - 0DFFFF 068000 - 06FFFF

SA21 001110XXX 64/32 0E0000 - 0EFFFF 070000 - 077FFF

SA22 001111XXX 64/32 0F0000 - 0FFFFF 078000 - 07FFFF

SA23 010000XXX 64/32 100000 - 10FFFF 080000 - 087FFF

SA24 010001XXX 64/32 110000 - 11FFFF 088000 - 08FFFF

SA25 010010XXX 64/32 120000 - 12FFFF 090000 - 097FFF

SA26 010011XXX 64/32 130000 - 13FFFF 098000 - 09FFFF

SA27 010100XXX 64/32 140000 - 14FFFF 0A0000 - 0A7FFF

SA28 010101XXX 64/32 140000 - 14FFFF 0A8000 - 0AFFFF

SA29 010110XXX 64/32 160000 - 16FFFF 0B0000 - 0B7FFF

SA30 010111XXX 64/32 170000 - 17FFFF 0B8000 - 0BFFFF

SA31 011000XXX 64/32 180000 - 18FFFF 0C0000 - 0C7FFF

SA32 011001XXX 64/32 190000 - 19FFFF 0C8000 - 0CFFFF

SA33 011010XXX 64/32 1A0000 - 1AFFFF 0D0000 - 0D7FFF

SA34 011011XXX 64/32 1B0000 - 1BFFFF 0D8000 - 0DFFFF

A29L320A Series

(November, 2012, Version 1.7) 10 AMIC Technology, Corp.

Table 3. A29L320A Bottom Boot Block Sector Address Table

Address Range (in h exadecimal)

Sector A20 -A12 Sector Size

(Kbytes/ Kwords) Byte Mode (x8) Word Mode (x16)

SA35 011100XXX 64/32 1C0000 - 1CFFFF 0E0000 - 0E7FFF

SA36 011101XXX 64/32 1D0000 - 1DFFFF 0E8000 - 0EFFFF

SA37 011110XXX 64/32 1E0000 - 1EFFFF 0F0000 - 0F7FFF

SA38 011111XXX 64/32 1F0000 - 1FFFFF 0F8000 - 0FFFFF

SA39 100000XXX 64/32 200000 - 20FFFF 100000 - 107FFF

SA40 100001XXX 64/32 210000 - 21FFFF 108000 - 10FFFF

SA41 100010XXX 64/32 220000 - 22FFFF 110000 - 117FFF

SA42 100011XXX 64/32 230000 - 23FFFF 118000 - 11FFFF

SA43 100100XXX 64/32 240000 - 24FFFF 120000 - 127FFF

SA44 100101XXX 64/32 250000 - 25FFFF 128000 - 12FFFF

SA45 100110XXX 64/32 260000 - 26FFFF 130000 - 137FFF

SA46 100111XXX 64/32 270000 - 27FFFF 138000 - 13FFFF

SA47 101000XXX 64/32 280000 - 28FFFF 140000 - 147FFF

SA48 101001XXX 64/32 290000 - 29FFFF 148000 - 14FFFF

SA49 101010XXX 64/32 2A0000 - 2AFFFF 150000 - 157FFF

SA50 101011XXX 64/32 2B0000 - 2BFFFF 158000 - 15FFFF

SA51 101100XXX 64/32 2C0000 - 2CFFFF 160000 - 167FFF

SA52 101101XXX 64/32 2D0000 - 2DFFFF 168000 - 16FFFF

SA53 101110XXX 64/32 2E0000 - 2EFFFF 170000 - 177FFF

SA54 101111XXX 64/32 2F0000 - 2FFFFF 178000 - 17FFFF

SA55 110000XXX 64/32 300000 - 30FFFF 180000 - 187FFF

SA56 110001XXX 64/32 310000 - 31FFFF 188000 - 18FFFF

SA57 110010XXX 64/32 320000 - 32FFFF 190000 - 197FFF

SA58 110011XXX 64/32 330000 - 33FFFF 198000 - 19FFFF

SA59 110100XXX 64/32 340000 - 34FFFF 1A0000 - 1A7FFF

SA60 110101XXX 64/32 350000 - 35FFFF 1A8000 - 1AFFFF

SA61 110110XXX 64/32 360000 - 36FFFF 1B0000 - 1B7FFF

SA62 110111XXX 64/32 370000 - 37FFFF 1B8000 - 1BFFFF

SA63 111000XXX 64/32 380000 - 38FFFF 1C0000 - 1C7FFF

SA64 111001XXX 64/32 390000 - 39FFFF 1C8000 - 1CFFFF

SA65 111010XXX 64/32 3A0000 - 3AFFFF 1D0000 - 1D7FFF

SA66 111011XXX 64/32 3B0000 - 3BFFFF 1D8000 - 1DFFFF

SA67 111100XXX 64/32 3C0000 - 3CFFFF 1E0000 - 1E7FFF

SA68 111101XXX 64/32 3D0000 - 3DFFFF 1E8000 - 1EFFFF

SA69 111110XXX 64/32 3E0000 - 3EFFFF 1F0000 - 1F7FFF

SA70 111111XXX 64/32 3F0000 - 3FFFFF 1F8000 - 1FFFFF

Note:

Address range is A20 : A-1 in byte mode and A20 : A0 in word mode. See “Word/Byte Configuration” section.

A29L320A Series

(November, 2010, Version 1.7) 11 AMIC Technology, Corp.

Autoselect Mode

The autoselect mode provides manufacturer and device

identification, and sector protection verification, through

identifier codes output on I/O7 - I/O0. This mode is primarily

intended for programming equipment to automatically match

a device to be programmed with its corresponding

programming algorithm. However, the autoselect codes can

also be accessed in-system throug h the command register.

When using programming equipment, the autoselect mode

requires VID (11.5V to 12.5V) on address pin A9. Address

pins A6, A1, and A0 must be as shown in Autoselect Codes

(High Voltage Method) table. In addition, when verifying

sector protection, the sector address must appear on the

appropriate highest order address bits. Refer to the

corresponding Sector Address Tables. The Command

Definitions table shows the remaining address bits that are

don't care. When all necessary bits have been set as

required, the programming equipment may then read the

corresponding identifier code on I/O7 - I/O0.To access the

autoselect codes in-system, the host system can issue the

autoselect command via the command register, as shown in

the Command Definitions table. This method does not

require VID. See "Command Definitions" for details on using

the autoselect mode.

Table 4. A29L320A Autoselect Codes (High Voltage Metho d)

Description Mode CE

A20

A12

A11

A10

A9 A8

A6 A5

A1 A0 I/O8

I/O15

I/O7

I/O0

Manufacturer ID: AMIC L L H X X VID X L X L L X 37h

Word 22h F6h

Device ID:

A29L320A

(Top Boot Block) Byte L L H X X VID XLXLH X F6h

Word 22h F9h

Device ID:

A29L320A

(Bottom Boot Block) Byte L L H X X VID XLXLH X F9h

Continuation ID L L H X X VID X L X H H X 7Fh

X 01h

(protected)

Sector Protection Verification L L H SA X VID XLXHL X 00h

(unprotected)

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Do n’t Care.

Note: The autoselect codes may also be accessed in-s ystem via command sequences.

A29L320A Series

(November, 2010, Version 1.7) 12 AMIC Technology, Corp.

Sector/Sector Block Protection and Unprotection

(Note: For the following discussion, the term “sector” applies

to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or

unprotected at the same time (see Tables 5 and 6).

Table 5. Top Boot Sector/Sector Block Addresses for

Protection/Unprotection

Sector /

Sector Block A20–A12 Sector / Sector Block Size

SA0 000000XXX 64 Kbytes

SA1-SA3 000001XXX

000010XXX

000011XXX 192 (3x64) Kbytes

SA4-SA7 0001XXXXX 256 (4x64) Kbytes

SA8-SA11 0010XXXXX 256 (4x64) Kbytes

SA12-SA15 0011XXXXX 256 (4x64) Kbytes

SA16-SA19 0100XXXXX 256 (4x64) Kbytes

SA20-SA23 0101XXXXX 256 (4x64) Kbytes

SA24-SA27 0110XXXXX 256 (4x64) Kbytes

SA28-SA31 0111XXXXX 256 (4x64) Kbytes

SA32-SA35 1000XXXXX 256 (4x64) Kbytes

SA36-SA39 1001XXXXX 256 (4x64) Kbytes

SA40-SA43 1010XXXXX 256 (4x64) Kbytes

SA44-SA47 1011XXXXX 256 (4x64) Kbytes

SA48-SA51 1100XXXXX 256 (4x64) Kbytes

SA52-SA55 1101XXXXX 256 (4x64) Kbytes

SA56-SA59 1110XXXXX 256 (4x64) Kbytes

SA60-SA62 111100XXX

111101XXX

111110XXX 192 (3x64) Kbytes

SA63 111111000 8 Kbytes

SA64 111111001 8 Kbytes

SA65 111111010 8 Kbytes

SA66 111111011 8 Kbytes

SA67 111111100 8 Kbytes

SA68 111111101 8 Kbytes

SA69 111111110 8 Kbytes

SA70 111111111 8 Kbytes

Table 6. Bottom Boot Sector/Sector Block Addresses for

Protection/Unprotection

Sector /

Sector Block A20–A12 Sector / Sector Block Size

SA70 111111XXX 64 Kbytes

SA69- SA67 111110XXX

111101XXX

111100XXX 192 (3x64) Kbytes

SA66- SA63 1110XXXXX 256 (4x64) Kbytes

SA62- SA59 1101XXXXX 256 (4x64) Kbytes

SA58- SA55 1100XXXXX 256 (4x64) Kbytes

SA54- SA51 1011XXXXX 256 (4x64) Kbytes

SA50- SA47 1010XXXXX 256 (4x64) Kbytes

SA46-SA43 1001XXXXX 256 (4x64) Kbytes

SA42-SA39 1000XXXXX 256 (4x64) Kbytes

SA38-SA35 0111XXXXX 256 (4x64) Kbytes

SA34-SA31 0110XXXXX 256 (4x64) Kbytes

SA30-SA27 0101XXXXX 256 (4x64) Kbytes

SA26-SA23 0100XXXXX 256 (4x64) Kbytes

SA22-SA19 0011XXXXX 256 (4x64) Kbytes

SA18-SA15 0010XXXXX 256 (4x64) Kbytes

SA14-SA11 0001XXXXX 256 (4x64) Kbytes

SA10-SA8 000001XXX

000010XXX

000011XXX 192 (3x64) Kbytes

SA7 000000111 8 Kbytes

SA6 000000110 8 Kbytes

SA5 000000101 8 Kbytes

SA4 000000100 8 Kbytes

SA3 000000011 8 Kbytes

SA2 000000010 8 Kbytes

SA1 000000001 8 Kbytes

SA0 000000000 8 Kbytes

A29L320A Series

(November, 2012, Version 1.7) 13 AMIC Technology, Corp.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hardware

sector unprotection feature re-enables both program and

erase operations in previous ly protected sectors.

It is possible to determine whether a sector is protected or

unprotected. See “Autoselect Mode” for details.

Sector protection / unprotection can be implemented via two

methods. The primary method requires VID on the

RESETpin only, and can be implemented either in-system or

via programming equipment. Figure 2 shows the algorithm

and the Sector Protect / Unprotect Timing Diagram il lustrates

the timing waveforms for this feature. This method uses

standard microprocessor bus cycle timing. For sector

unprotect, all unprotected sectors must first be protected

prior to the first sector unprotect write cycle. The alternate

method for protection and unprotection is by software sector

block protect/unprotect command. See Figure 2 for

Command Flow.

The device is shipped with all sectors unprotected.

It is possible to determine whether a sector is protected or

unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for

programming or erasing provides data protection against

inadvertent writes (refer to the Command Definitions table).

In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might

otherwise be caused by spur ious system level signals during

VCC power-up transitions, or from system noise. The device

is powered up to read array data to avoid accident ally writing

data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE , CE or WE

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE =VIL,

CE = VIH or WE = VIH. To initiate a write cycle, CE and

WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

If WE = CE = VIL and OE = VIH during power up, the

device does not accept commands on the rising edge of

WE . The internal state machine is automatically reset to

reading array data on the initia l power-up.

Temporary Sector Unprotect

This feature allows temporary unprotection of previous

protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the RESET pin to VID.

During this mode, formerly protected sectors can be

programmed or erased by selecting the sector addresses.

Once VID is removed from the RESET pin, all the previously

protected sectors are protected again. Figure 1 shows the

algorithm, and the Temporary Sector Unprotect diagram

shows the timing waveforms, for this feature.

A29L320A Series

(November, 2012, Version 1.7) 14 AMIC Technology, Corp.

START

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotect

Comple ted (Note 2)

Notes:

1. All protected sectors unprotected (If WP/ACC=VIL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once again.

Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode

Figure 1-2. Temporary Sector Unprotect Operation by Software Mode

START

555/AA + 2AA/55 + 555/77

(Note 1 )

Perform Erase or

Program Opera tions

XXX/F0

(Reset Co m m a nd )

Soft-ware Temporary

Sector Un pro tect

Completed

(Note 2 )

Notes:

1. All protected sectors unprotected (If WP/ACC=VIL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once again.

A29L320A Series

(November, 2012, Version 1.7) 15 AMIC Technology, Corp.

START

PLSCNT=1

RESET=VID

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protec:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 15 0 u s

Verify Sector

Protect: Write 40h

to sect or address

with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Data=01h?

Protect another

sector?

Remove VID

from RESET

Write reset

command

Sector Protect

complete

Sector Protect

Algorithm

Temporary Sector

Unprotect Mode

Increment

PLSCNT

=25?

Device fai led

Yes

Reset

PLSCNT=1

Yes

Prote ct all secto r s:

The indi ca t e d po rt i o n of

the sector protect

algorithm mu st be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

START

PLSCNT=1

RESET=VID

Wait 1 us

First Write

Cycle=60h? No Temporar y Se ct or

Unprotect Mode

Yes

All secto rs

protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 100 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from sector

address with A6=1,

A1=1, A0=0

Data=00h?

Last sector

verified?

Remove VID

from RESET

Write reset

Command

Sector Unprotect

complete

Yes

Set up

next sector

address

Yes

Sector Unprotect

Algorithm

Increment

PLSCNT

PLSCNT=

10?

Device fai led

Yes

Figure 2-1. In-System Sector Protect/Unprotect Algorithms

PLSCNT=

10? No

Yes

Increment

PLSCNT

A29L320A Series

(November, 2010, Version 1.7) 16 AMIC Technology, Corp.

START

PLSCNT=1

555/AA + 2AA/55 +

555/77

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address

with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Data=01h?**

Protect another

sector?

Write reset

command

Sector Protect

complete

Sector Protect

Algorithm

Temporary Sector

Unprotect Mode

Increment

PLSCNT

=25?

Device failed

Yes

Reset

PLSCNT=1

Yes

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

START

PLSCNT=1

Wait 1 us

First Write

Cycle=60h? No Temporary Sector

Unprotect Mode

Yes

All se ctors

protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 100 ms

Verify Sector

Unprot ect : W rite

40h to sector

address with A6=1,

A1=1, A0=0

Read from sector

address with A6=1,

A1=1, A0=0

Data=00h?**

Last sector

verified?

Write reset

Command

Sector Unprotect

complete

Yes

Set up

next sector

address

Yes

Sector Unprotect

Algorithm

Increment

PLSCNT

PLSCNT=

10?

Device failed

Yes

Figure 2-2. Softwa re S ector/ Se cto r B lock Protection and Unprotection Algorithms

Note: The term “sector” in the figure applies to both sectors and sector blocks

* No other command is allowed during this process

** Access time is 200ns-300ns

555/AA + 2AA/55 +

555/77

PLSCNT=

10? No

Yes

Increment

PLSCNT

A29L320A Series

(November, 2010, Version 1.7) 17 AMIC Technology, Corp.

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines

device and host system software interrogation handshake,

which allows specific vendor-specified soft ware algorithms to

be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and

forward- and backward-compatible for the specified flash

device families. Flash vendors can standardize their existing

interface for long-term compatibilit y.

This device enters the CFI Query mode when the system

writes the CFI Query command, 98h, to address 55h in word

mode (or address AAh in byte mode), any time the device is

ready to read array data. The system can read CFI

information at the addresses given in Table 5-8. In word

mode, the upper address bits (A7-MSB) must be all zeros.

To terminate reading CFI data, the system must write the

reset command.

The system can also write the CFI quer y command when the

device is in the autoselect mode. The device enters the CFI

query mode, and the system can read CFI data at the

addresses given in Table 5-8. The system must write the

reset command to return the device to the autoselect mode.

Table 7. CFI Query Identification String

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 26h

28h 0002h

0000h Primary OEM Command Set

15h

16h 2Ah

2Ch 0040h

0000h Address for Primary Extended T able

17h

18h 2Eh

30h 0000h

0000h Alternate OEM Command Set (00h = none e xists)

19h

1Ah 32h

34h 0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

Table 8. System Interface String

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

1Bh 36h 0027h VCC Min. (write/erase)

I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase)

I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt

1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)

1Eh 3Ch 000 0h Vpp Max. voltage (00h = no Vpp pin present)

1Fh 3Eh 0004h

Typical timeout per single b yte/word write 2N μs

20h 40h 0000h

Typical timeout for Min. size buffer write 2N μs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0005h Max. timeout for b yte/word write 2N times typical

24h 48h 0000h Max. timeout for buffer write 2N times typical

25h 4Ah 0004h Max. timeout per individual block erase 2N times typical

26h 4Ch 000 0h Max. timeout for full chip erase 2N times typical (00h = not supported)

A29L320A Series

(November, 2012, Version 1.7) 18 AMIC Technology, Corp.

Table 9. Device Geometry Definition

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

27h 4Eh 0016h Device Size = 2N byte

28h

29h 50h

52h 0002h

0000h Flash Device Interface descri ption

2Ah

2Bh 54h

56h 0000h

0000h Max. number of byte in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0002h Number of Erase Block Regions within devic e

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification)

31h

32h

33h

34h

62h

64h

66h

68h

003Eh

0000h

0001h

Erase Block Region 2 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Erase Block Region 3 Information

39h

3Ah

3BH

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

A29L320A Series

(November, 2012, Version 1.7) 19 AMIC Technology, Corp.

Table 10. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h Query-unique ASCII string “PRI”

43h 86h 0031h Major version number, ASCII

44h 88h 0031h Minor version number, ASCII

45h 8Ah 0000h Address Sensitive Unlock

0 = Required, 1 = Not Required

46h 8Ch 0002h Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 8Eh 0004h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 90h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 92h 0004h Sector Protect/Unprot ect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29L160 mode

4Ah 94h 0000h Simultaneous Operation

00 = Not Supported, 01 = Supported

4Bh 96h 0000h Burst Mode T ype

00 = Not Supported, 01 = Supported

4Ch 98h 0000h Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 W ord Page

4Dh 9Ah 00B5h ACC (Acceleration) Supply Minimum

00 = Not Supported, D7-D4: Volt, D3-D0: 100mV

4Eh 9Ch 00C5h ACC (Acceleration) Supply Maximum

00 = Not Supported, D7-D4: Volt, D3-D0: 100mV

4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag

02 = Bottom Boot Device, 03h = Top Boot Device

A29L320A Series

(November, 2012, Version 1.7) 20 AMIC Technology, Corp.

Command Definitions

Writing specific address and data commands or sequences

into the command register initiates device operations. The

Command Definitions table defines the valid register

command sequences. Writing incorrect address and data

values or writing them in the improper sequence resets the

device to reading array data.

All addresses are latched on the falling edge of WE or CE,

whichever happens later. All data is latched on the rising

edge of WE or CE, whichever happens first. Refer to the

appropriate timing diagrams in the "AC Characteristics"

section.

Reading Array Data

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve

data. The device is also ready to read array data after

completing an Embedded Program or Embedded Erase

algorithm. After the device accepts an Erase Suspend

command, the device enters the Erase Suspend mode. The

system can read array data using the standard read timings,

except that if it reads at an address within erase-suspended

sectors, the device outputs status data. After completing a

programming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See "Erase Suspend/Erase Resume Commands"

for more information on this mode.

The system must issue the reset command to re-enable the

device for reading arr ay data if I/O5 goes hig h, or while in the

autoselect mode. See the "Reset Command" section, next.

See also "Requirements for Reading Array Data" in the

"Device Bus Operations" section for more information. The

Read Operations table provides the read parameters, and

Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to

reading array data. Address bits are don't care for this

command. The reset command may be written between the

sequence cycles in an erase command sequence before

erasing begins. This resets the device to reading array data.

Once erasure begins, however, the device ignores reset

commands until the operation is complete.

The reset command may be written between the sequence

cycles in a program command sequence before

programming begins. This resets the device to reading array

data (also applies to programming in Erase Suspend mode).

Once programming begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to

return to reading array data (also applies to autoselect during

Erase Suspend).

If I/O5 goes high during a program or erase operation, writing

the reset command returns the device to reading array data

(also applies during Erase Su spend).

Autoselect Command Sequence

The autoselect command seq uence allo ws the host system to

access the manufacturer and devices codes, and determine

whether or not a sector is protected. The Command

Definitions table shows the address and data requirements.

This method is an alternative to that shown in the Autoselect

Codes (High Voltage Method) table, which is intended for

PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two

unlock cycles, followed by the autoselect command. The

device then enters the autoselect mode, and the system may

read at any address any number of times, without initiating

another command sequence.

A read cycle at address XX00h retrieves the manufacturer

code and another read cycle at XX11h retrieves the

continuation code. A read cycl e at address XX01h returns the

device code. A read cycle containing a sector address (SA)

and the address 02h in ret urns 01h if that sector is protected,

or 00h if it is unprotected. Refer to the Sector Address tables

for valid sector addresses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE pin. Programming is a

four-bus-cycle operation. The program c ommand sequenc e is

initiated by writing two unlock write cycles, followed by the

program set-up command. The program address and data are

written next, which in turn initiate the Embedded Program

algorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verify the

programmed cell margin. T able 9 shows the address and data

requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses are

longer latched. The system can determine the status of the

program operation by using I/O7, I/O6, or RY/ BY. See “White

Operation Status” for information on these status bits.

Any commands written to the device during the Embedded

Program Algorithm are ignored. Note that a hardware reset

immediately terminates the programming operation. The Byte

Program command sequence should be reinitiated once the

device has reset to reading array data, to ensure data

integrity.

Programming is allowed in any sequence and across sector

boundaries. A bit cannot be programme d from a “0” back to a

“1”. Attempting to do so may halt the operation and set I/O5 to

“1”, or cause the Data Polling algorithm to indicate the

operation was successful. However, a succeeding read will

show that the data is still “0”. Only erase operations can

convert a “0” to a “1”.

A29L320A Series

(November, 2012, Version 1.7) 21 AMIC Technology, Corp.

START

Write Program

Command

Sequence

Data Poll

from System

Verify Data ?

Last Address ?

Programming

Completed

Yes

Increment Address

Embedded

Program

algorithm in

progress

Note : See the appropriate Command Definitions table for

program command sequence.

Figure 3. Program Operation

Unlock Bypass Command Sequenc e

The unlock bypass feature allows the system to program

bytes or words to the device faster than using the standard

program command sequence. The unlock bypass command

sequence is initiated by first writing two unloc k cycles. This is

followed by a third write cycle containing the unlock bypass

command, 20h. The device then enters the unlock bypass

mode. A two-cycle unlock bypass program command

sequence is all that is require d to program in this mode. The

first cycle in this sequence contains the unlock bypass

program command, A0h; the second cycle contains the

program address and data. Additio nal data is programmed in

the same manner. This mode dispenses with the initial two

unlock cycles required in the standard program command

sequence, resulting in faster total programm ing time. Table 9

shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass

Program and Unlock Bypass Reset commands are valid. To

exit the unlock bypass mode, the system must issue the two-

cycle unlock bypass reset command sequence. The first

cycle must contain the data 90h; the second cycle the data

00h. Addresses are don’t care for both cycle. The device

returns to reading array data.

Figure 3 illustrates the algorithm for the program operation.

See the Erase/Program Operations in “AC Characteristics” for

parameters, and to Program Operation Timings for timing

diagrams.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern pri or to

electrical erase. The system is not required to provide any

controls or timings during these operations. The Command

Definitions table shows the address and data requirements

for the chip erase command sequence.

Any commands written to the chip during the Embedded

Erase algorithm are ignored. The system can determine the

status of the erase operation by using I/O7, I/O6, or I/O2. See

"Write Operation Status" for information on these status bits.

When the Embedded Eras e algorithm is c omplete, the device

returns to reading array data and addresses are no longer

latched.

Figure 4 illustrates the algorithm for the erase operation. See

the Erase/Program Operations tables in "AC Characteristics"

for parameters, and to the Chip/Sector Erase Operation

Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the address of the sector to be

erased, and the sector erase command. The Command

Definitions table shows the address and data requirements

for the sector erase command sequence.

The device does not require the system to preprogram the

memory prior to erase. The Embedded Erase algorithm

automatically programs and verifies the sector for an all zero

data pattern prior to electrical erase. The system is not

required to provide any controls or timings during these

operations.

After the command sequence is written, a sector erase time-

out of 50μs begins. During the time-out period, additional

sector addresses and sector erase commands may be

written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector

to all sectors. The time between these additional cycles must

be less than 50μs, otherwise the last address and command

might not be accepted, and erasure may begin. It is

recommended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional sector

erase commands can be assumed to be less than 50μs, the

system need not monitor I/O3. Any command other than

Sector Erase or Erase Suspend during the time-out period

resets the device to reading array data. The system must

rewrite the command sequence and any additional sector

addresses and commands.

A29L320A Series

(November, 2012, Version 1.7) 22 AMIC Technology, Corp.

START

Write Erase

Command

Sequence

Data Poll

from System

Data = FFh ?

Erasure Completed

Yes

Embedded

Erase

algorithm in

progress

Note :

1. See the appropriate Command Definitions table for erase

command sequences.

2. See "I/O

: Sector Erase Timer" for more information.

Figure 4. Erase Operation

The system can monitor I/O3 to determine if the sector erase

timer has timed out. (See the " I/O3: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

WE pulse in the command sequence.

Once the sector erase operation has begun, only the Erase

Suspend command is valid. All other commands are ignored.

When the Embedded Erase algorit hm is com plete, the dev ice

returns to reading array data and addresses are no longer

latched. The system can determine the status of the erase

operation by using I/O7, I/O6, or I/O2. Refer to "Write

Operation Status" for information on these status bits.

4 illustrates the algorithm for the erase operation. Refer to

the Erase/Program Operations tables in the "AC

Characteristics" section for parameters, and to the Sector

Erase Operations Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allo ws the system to interrupt

a sector erase operation and then read data from, or

program data to, any sector not selected for erasure. This

command is valid only during the sector erase operation,

including the 50μs time-out period during the sector erase

command sequence. The Erase Suspend command is

ignored if written during the chip erase operation or

Embedded Program algorithm. Writing the Erase Suspend

command during the Sector Erase time-out immediately

terminates the time-out period and suspends the erase

operation. Addresses are "don't cares" when writing the

Erase Suspend command.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum of

20μs to suspend the erase operation. However, when the

Erase Suspend command is written during the sector erase

time-out, the device immediately terminates the time-out

period and suspends the erase operation.

After the erase operation has been suspended, the system

can read array data from or program data to any sector not

selected for erasure. (The device "erase suspends" all

sectors selected for erasure.) Normal read and write timings

and command definitions apply. Reading at any address

within erase-suspended sector s produces status data on I/O7

- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to

determine if a sector is actively erasing or is erase-

suspended. See "Write Operation Status" for information on

these status bits.

After an erase-suspended program operation is complete,

the system can once again read array data within non-

suspended sectors. The system can determine the status of

the program operation using the I/O7 or I/O6 status bits, just

as in the standard program operation. See "Write Operation

Status" for more information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend mode.

The device allows reading autoselect codes even at

addresses within erasing sectors, since the codes are not

stored in the memory array. When the device exits the

autoselect mode, the device reverts to the Erase Suspend

mode, and is ready for another valid operation. See

"Autoselect Command Sequence" for more information.

The system must write the Erase Resume command

(address bits are "don't care") to exit the erase suspend

mode and continue the sector erase oper ation. Further writes

of the Resume command are ignored. Another Erase

Suspend command can be written after the device has

resumed erasing.

A29L320A Series

(November, 2012, Version 1.7) 23 AMIC Technology, Corp.

Table 11. A29L320A Com m and Definitions

Bus Cycles (Notes 2 - 5)

First Second Third Fourth Fifth Sixth

Command

Sequence

(Note 1)

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 6) 1 RA RD

Reset (Note 7) 1 XXX F0

Word 555 2AA 555

Manufacturer ID Byte 4 AAA AA 555 55 AAA 90 X00 37

Word 555 2AA 555 X01 22F6Device ID,

Top Boot Block Byte 4 AAA AA 555 55 AAA 90 X02 F6

Word 555 2AA 555 X01 22F9Device ID,

Bottom Boot Block Byte 4 AAA AA 555 55 AAA 90 X02 F9

Word 555 2AA 555 X03

Continuation ID Byte 4 AAA AA 555 55 AAA 90 X06 7F

XX00

Word 555 2AA 555 (SA)

X02 XX01

Autoselect (Note 8)

Sector Protect Verify

(Note 9)

Byte 4 AAA AA 555 55 AAA 90 (SA)

X04 01

Word 55

CFI Query (Note 10) Byte 1 AA 98

Word 555 2AA 555

Command Temporary

Sector Unprotect (Note9) Byte 3 AAA AA 555 55 AAA 77

Byte 555 2AA 555

Program Byte 4 AAA AA 555 55 AAA A0 PA PD

Word 555 2AA 555

Unlock Bypass Byte 3 AAA AA 555 55 AAA 20

Unlock Bypass Program (Note

11) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 12) 2 XXX 90 XXX 00

Word 555 2AA 555 555 2AA 555

Chip Erase Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Word 555 2AA 555 555 2AA

Sector Erase Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

Erase Suspend (Note 13) 1 XXX B0

Erase Resume (Note 14) 1 XXX 30

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,

whichever happens later.

PD = Data to be programmed a t loca tion PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20- A12 select a unique sector.

A29L320A Series

(November, 2012, Version 1.7) 24 AMIC Technology, Corp.

Note:

1. See Table 1 for description of bus operations.

2. All values are in he xadecimal.

3. Except when reading array or autoselect data, all bus c ycl es are write operation.

4. Address bits A20 - A11 are don't cares for unlock a nd command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading array data.

6. The Reset command is required to return t o reading array data when device is in the autoselect mode, or if I/O5 goes high

(while the device is providing status data).

7. The fourth cycle of the autose lect command sequence is a read cycle.

8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more

information.

9. Once a reset command is applied, software temporary unprotect is exit to return to read array data. But under erase

suspend condition, this command is sti ll effective even a reset command has been appli ed. The reset command which can

deactivate the software temporary unprotect command is useful only after the erase command is complete.

10. Command is valid when device is ready to read array data or when device is in autoselect mode.

11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass

mode.

13. The system may read and program in non -erasing sectors, o r en ter the auto sele ct mode, w hen in the Era se Suspend mode .

14. The Erase Resume command is valid onl y during the Erase Suspend mode.

A29L320A Series

(November, 2010, Version 1.7) 25 AMIC Technology, Corp.

Write Operation Status

Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/BY are provided in

the A29L320A to determine the status of a write operation.

Table 10 and the following subsections describe the

functions of these status bits. I/O7, I/O6 and RY/BY each

offer a method for determining whether a program or erase

operation is complete or in progress. These three bits are

discussed first.

I/O7: Data Polling

The Data Polling bit, I/O7, indicates to the host system

whether an Embedded Algorithm is in progre ss or completed,

or whether the device is in Erase Suspend. Data Polling is

valid after the rising edge of the final WE pulse in the

program or erase command sequence.

During the Embedded Program algorithm, the device out puts

on I/O7 the complement of the datum programmed to I/O7.

This I/O7 status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to I/O7.

The system must provide the program address to read valid

status information on I/O7. If a program address falls within a

protected sector, Data Polling on I/O7 is active for

approximately 2μs, then the device returns to reading array

data.

During the Embedded Erase algorithm, Data Polling

produces a "0" on I/O7. When the Embe dded Erase al gorit h m

is complete, or if the device enters the Eras e Suspend mo de,

Data Polling produces a "1" on I/O7.This is analo gous to the

complement/true datum output described for the Embedded

Program algorithm: the erase function changes all the bits in

a sector to "1"; prior to this, the device outputs the

"complement," or "0." The system must provide an address

within any of the sectors selected for erasure to read valid

status information on I/O7.

After an erase command sequence is written, if all sectors

selected for erasing are protected, Data Polling on I/O7 is

active for approximately 100μs, then the device returns to

reading array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

When the system detects I/O7 has changed from the

complement to true data, it can read valid data at I/O7 - I/O0

on the following read cycles. This is because I/O7 may

change asynchronously with I/O0 - I/O6 while Output Enable

(OE ) is asserted low. The Data Polling Timings (During

Embedded Algorithms) figure in the "AC Characteristics"

section illustrates this. Table 10 shows the outputs for Data

Polling on I/O7. Figure 5 shows the Data Polling algorithm.

START

Read I/O

-I/O

Address = VA

I/O

= Data ?

FAIL

Note :

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. I/O

should be rechecked even if I/O

= "1" because

I/O

may change simultaneously with I/O

Read I/O

- I/O

Address = VA

I/O

= 1?

I/O

= Data ?

Yes

PASS

Yes

Figure 5. Data Polling Algorithm

A29L320A Series

(November, 2010, Version 1.7) 26 AMIC Technology, Corp.

RY/BY : Read/Busy

The RY/ BY is a dedicated, open-drain output pin that

indicates whether an Embedded algorithm is in progress or

complete. The RY/ BY status is valid after the rising edge of

the final WE pulse in the command sequence. Since RY/BY

is an open-drain output, several RY/ BY pins can be tied

together in parallel with a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing or

programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device is

ready to read array data (including during the Erase Suspend

mode), or is in the standby mode.

Table 10 shows the outputs for RY/BY. Refer to “RESET

Timings”, “Timing Waveforms for Program Operation” and

“Timing Waveforms for Chip/Sector Erase Operation” for

more information.

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded Pro gram

or Erase algorithm is in progress or complete, or whether the

device has entered the Erase Suspend mode. Toggle Bit I

may be read at any address, and is valid after the risin g edge

of the final WE pulse in the command sequ ence (prior to the

program or erase operation), and during the sector erase

time-out.

During an Embedded Program or Erase algorithm operation,

successive read cycles to any address cause I/O6 to toggle.

(The system may use either OE or CE to control the read

cycles.) When the operation is complete, I/O6 stops toggling.

After an erase command sequence is written, if all sectors

selected for erasing are protected, I/O6 toggles for

approximately 100μs, then returns to reading array data. If not

all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use I/O6 and I/O2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progr ess), I/O6 toggles . When the device

enters the Erase Suspend mode, I/O6 stops toggling.

However, the system must also use I/O2 to determine which

sectors are erasing or erase-suspended. Alternatively, the

system can use I/O7 (see the subsection on " I/O7 : Data

Polling").

If a program address falls within a protected sector, I/O6

toggles for approximately 2μs after the program command

sequence is written, then returns to reading a rray data.

I/O6 also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is

complete.

The Write Operation Status table shows the outputs for

Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the "AC

Characteristics" section for the timing diagram. The I/O2 vs.

I/O6 figure shows the differences between I/O2 and I/O6 in

graphical form. See also the subsection on " I/O2: Toggle Bit

II".

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates

whether a particular sector is actively erasing (that is, the

Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final WE pulse in the command sequence.

I/O2 toggles when the system reads at addr esses within those

sectors that have been selected for eras ure. (The system may

use either OE or CE to control the read cycles.) But I/O2

cannot distinguish whether the sector is actively erasing or is

erase-suspended. I/O6, by comparison, indicates whether the

device is actively erasin g, or is in Erase Suspend, but can not

distinguish which sectors ar e selected for erasure. Thus, b oth

status bits are required for sector and mode information.

Refer to Table 10 to compare outputs for I/O2 and I/O6.

Figure 6 shows the toggle bit algor ithm in flowchart form, and

the section " I/O2: Toggle Bit II" explains the algorithm. See

also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle

Bit Timings figure for the toggle bit timing diagram. The I/O2

vs. I/O6 figure shows the differences between I/O2 and I/O6 in

graphical form.

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever the

system initially begins reading toggle bit status, it must read

I/O7 - I/O0 at least twice in a row to determine whether a

toggle bit is toggling. Typically, a system would note and sto re

the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle

bit with the first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system can

read array data on I/O7 - I/O0 on the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system also

should note whether the value of I/O 5 is high (see the section

on I/O5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as I/O5 went high. If the toggle bit

is no longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the device

did not complete the operation successfully, and the system

must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines

that the toggle bit is toggling and I/O 5 has not gone high. The

system may continue to monitor the toggle bit and I/O5

through successive read cycles, determining the status as

described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the

system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Figu re

6).

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions I/O5 produces a "1." T his is a failure condition that

indicates the program or erase cycle was not successfully

completed.

A29L320A Series

(November, 2012, Version 1.7) 27 AMIC Technology, Corp.

The I/O5 failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed to

"0." Only an erase operation can change a "0" back to a "1."

Under this condition, the device halts the operation, and

when the operation has exceeded the timing limits, I/O5

produces a "1."

Under both these conditions, the system must issue the reset

command to return the device to reading array data.

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the system

may read I/O3 to determine whether or not an erase

operation has begun. (T he sector erase timer does not apply

to the chip erase command.) If additional sectors are

selected for erasure, the entire time-out also applies after

each additional sector erase command. Whe n the time-out is

complete, I/O3 switches from "0" to "1." The system may

ignore I/O3 if the system can guarantee that the time

between additional sector erase commands will always be

less than 50μs. See also the "Sector Erase Command

Sequence" section.

After the sector erase command sequence is written, the

system should read the status on I/O7 ( Data Polling) or I/O6

(Toggle Bit 1) to ensure the device has accepted the

command sequence, and then read I/O3. If I/O3 is "1", the

internally controlled erase cycle has begun; all further

commands (other than Erase Suspend) are ignored until the

erase operation is complete. If I/O3 is "0", the device will

accept additional sector erase commands. To ensure the

command has been accepted, the system software should

check the status of I/O3 prior to and following each

subsequent sector erase command. If I/O3 is high on the

second status check, the last command might not have been

accepted. Table 10 shows the outputs for I/O3.

START

Read I/O

-I/O

Toggle Bit

= Toggle ?

Program/Erase

Operation Not

Commplete, Write

Reset Command

Yes

Notes :

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as I/O

changes to "1". See text.

Read I/O

- I/O

Twice

I/O

= 1?

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Complete

Read I/O

-I/O

(Notes 1,2)

Figure 6. Toggle Bit Algorithm

(Note 1)

A29L320A Series

(November, 2012, Version 1.7) 28 AMIC Technology, Corp.

Table 12. Write Operation Status

I/O7 I/O6 I/O5 I/O3 I/O2 RY/BY

Operation (Note 1) (Note 2) (Note 1)

Embedded Program Algorithm 7I/O Toggle 0 N/A No toggle 0

Standard

Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspend Sector Data Data Data Data Data 1

Erase

Suspend

Mode

Erase-Suspend-Program 7I/O Toggle 0 N/A N/A 0

Notes:

1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “I/O5: Exceeded Timing Limits” for more information.

Maximum Negative Input Overshoot

20ns 20ns

20ns

+0.8V

-0.5V

-2.0V

Maximum Positive Input Overshoot

20ns20ns

20ns

VCC+0.5V

2.0V

VCC+2.0V

A29L320A Series

(November, 2012, Version 1.7) 29 AMIC Technology, Corp.

DC Characteristics

CMOS Compatible

Parameter

Symbol Parameter Description Test Description Min. Typ. Max. Unit

ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max

±1.0 μA

ILIT A9 Input Load Current VCC = VCC Max, A9 =12.5V 35 μA

ILO Output Leakage Current VOUT = VSS to VCC. VCC = VCC Max

±1.0 μA

5 MHz 10 16

CE = VIL, OE = VIH

Byte Mode 1 MHz 2 4

5 MHz 10 16

ICC1 VCC Active Read Current

(Notes 1, 2) CE = VIL, OE = VIH

Word Mode 1 MHz 2 4

ICC2 VCC Active Write (Program/Erase)

Current (Notes 2, 3, 4) CE= VIL, OE =VIH 20 30 mA

ICC3 VCC Standby Current (Note 2) CE= RESET= VCC ± 0.3V 0.5 5 μA

ICC4 VCC Standby Current During Reset

(Note 2) RESET= VSS ± 0.3V 0.5 5 μA

ICC5 Automatic Sleep Mode

(Note 2, 4, 5) VIH = VCC ± 0.3V; VIL = VSS ± 0.3V 0.5 5 μA

VIL Input Low Level -0.5 0.8 V

VIH Input High Level 0.7 x VCC VCC + 0.3 V

VHH Voltage for WP/ACC Sector Protect/

Unprotect and Program Acceleration VCC=3.0V ± 10% 11.5 12.5 V

VID Voltage for Autoselect and

Temporary Unprotect Sector VCC = 3.0 V ± 10% 11.5 12.5 V

VOL Output Lo w Voltage IOL = 4.0mA, VCC = VCC Min

0.45 V

VOH1 IOH = -2.0 mA, VCC = VCC Min 0.85 x VCC

VOH2 Output High Voltage IOH = -100 μA, VCC = VCC Min VCC - 0.4

Notes:

1. The ICC current listed is typical ly less than 2 mA/MHz, withOEat VIH. Typical VCC is 3.3V.

2. Maximum ICC specifications are tested with VCC = VCC max.

3. ICC active while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses rema in stable for tACC + 30ns. Typical sleep mode current

is 500nA.

5. Not 100% tested.

A29L320A Series

(November, 2012, Version 1.7) 30 AMIC Technology, Corp.

DC Characteristics (continued)

Zero Power Flash

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Supply Current in mA

Note: Addresses are switching at 1MHz

CC1

Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequency in MHz

Supply Current in mA

C25T :Note °=

Typical ICC1 vs. Frequency

3.6V

3.0V

A29L320A Series

(November, 2010, Version 1.7) 31 AMIC Technology, Corp.

AC Characteristics

Read Only Operations

Parameter

Symbols Speed Unit

JEDEC Std

Description Test Setup

-70 -80 -90 -120

tAVAV tRC Read Cycle T ime (Note 1) Min. 70 80 90 120 ns

tAVQV tACC Address to Output Delay CE = VIL

OE = VIL

Max. 70 80 90 120 ns

tELQV tCE Chip Enable to Output Delay OE = VIL Max. 70 80 90 120 ns

tGLQV tOE Output Enable to Output Delay Max. 30 30 40 50 ns

tOEH Output Enable Hold

Time (Note 1) Toggle and

Data Polling

10 10 10 10 10 ns

tEHQZ tHZ Chip Enable to Output High Z

(Notes 1) Max. 16 16 16 16 ns

tGHQZ tDF Output Enable to Output High Z

(Notes 1) 16 16 16 16 ns

tAXQX tOH Output Hold Time from Addresses,

CEor OE, Whichever Occurs First

(Note 1)

Min. 0 0 0 0 ns

Notes:

1. Not 100% tested.

2. See Test Conditions and Test Setup for test specifications.

Timing Waveforms for Read Only Operation

Addresses Addresses Stable

Output Valid High-Z

Output

OEH

High-Z

ACC

RESET

RY/BY

A29L320A Series

(November, 2012, Version 1.7) 32 AMIC Technology, Corp.

AC Characteristics

Hardware Reset (RESET)

Parameter

JEDEC Std Description Test Setup All Speed Options Unit

tREADY RESET Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 μs

tREADY RESET Pin Low (Not During Embed ded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET Pulse Width Min 500 ns

tRH RESET High Time Before Read (See Note) Min 50 ns

tRB RY/BY Recovery Time Min 0 ns

tRPD RESET Low to Standby Mode Min 20 μs

Note: Not 100% tested.

RESET Timings

CE, OE

RESET t

Ready

Reset Timings NOT during Embedded Algorithms

RESET

Reset Timings during Embedded Algorithms

RY/BY

Ready

CE, OE

RY/BY

A29L320A Series

(November, 2012, Version 1.7) 33 AMIC Technology, Corp.

Temporary Sector Unprotect

Parameter

JEDEC Std Description All Speed Options Unit

tVIDR VID Rise an d F all Time (See Note) Min 500 ns

tRSP RESET Setup Time for Temporary Sector

Unprotect Min 4 μs

tVHH VHH Rise and Fall Time (See Note) Min 250 ns

tRRB RESET Hold Time from RY/BY High for

Temporary Sector/Sector Block Unprotect Min 4 μs

Note: Not 100% tested.

Temporary Sector Unprotect Timing Diagram

Program or Erase Command Sequence

RESET

VID

VSS, VIL,

or VIH

tVIDR tVIDR

tRSP

RY/BY

VID

VSS, VIL,

or VIH

tRRB

Accelerated Program Timing Diagram

VHH

VIL or VIH VIL or VIH

VCC

WP/ACC tVHH tVHH

AC Characteristics

Word/Byte Configuration (BYTE)

Parameter All Speed Options Unit

JEDEC Std Description

-70 -80 -90 -120

tELFL/tELFH CE to BYTE Switching Low or High Max 5 ns

tFLQZ BYTE Switching Low to Output High-Z Max 25 25 30 30 ns

tHQV BYTE Switching High to Output Active Min 70 80 90 120 ns

A29L320A Series

(November, 2012, Version 1.7) 34 AMIC Technology, Corp.

Data Output

(I/O

-I/O

)Data Output

(I/O

-I/O

)

I/O

Output Address Input

Data Output

(I/O

-I/O

)

Data Output

(I/O

-I/O

)

I/O

Output

Address Input

FHQV

FLQZ

ELFH

ELFL

BYTE

I/O

-I/O

I/O

(A-1)

BYTE

I/O

-I/O

I/O

(A-1)

BYTE

Switching

from word to

byte mode

BYTE

Switching

from byte to

word mode

BYTE Timings for Read Operations

BYTE Timings for Write Operations

Note:

Refer to the Erase/Program Operations table for tAS and tAH specifications.

The falling edge of the last WE signal

HOLD

)

SET

)

BYTE

A29L320A Series

(November, 2012, Version 1.7) 35 AMIC Technology, Corp.

AC Characteristics

Erase and Program Operations

Parameter Speed

JEDEC Std

Description

-70 -80 -90

-120

Unit

tAVAV tWC Write Cycle Time (Note 1) Min. 70 80 90

120 ns

tAVWL tAS Address Setup Time Min. 0 0 0 0

tWLAX tAH Address Hold Time Min. 40 45 45 50 ns

tDVWH tDS Data Setup Time Min. 40 45 45 50 ns

tWHDX tDH Data Hold Time Min. 0 ns

tOES Output Enable Setup Time Min. 0 ns

tGHWL tGHWL Read Recover Time Before Write

(OE high to WE low) Min. 0 ns

tELWL tCS CE Setup Time Min. 0 ns

tWHEH tCH CE Hold Time Min. 0 ns

tWLWH tWP Write Pulse Width Min. 30 35 35 50 ns

tWHWL tWPH Write Pulse Width High Min. 30 ns

Byte Typ. 20

tWHWH1 tWHWH1 Byte Programming Operation

(Note 2) Word Typ. 40 μs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec

tvcs VCC Set Up Time (Note 1) Min. 50 μs

tRB Recovery Time from RY/BY (Note 1) Min 0 ns

tBUSY Program/Erase Valid to RY/BY Delay (Note 1) Min 90 ns

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

A29L320A Series

(November, 2012, Version 1.7) 36 AMIC Technology, Corp.

Timing Waveforms for Program Operation

Addresses

Data

VCC

A0h PD

Program Command Sequence (last two cycles)

OUT

Status

VCS

Read Status Data (last two cycles)

555h

WHWH1

WPH

Note :

1. PA = program addrss, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

BUSY

RY/BY

A29L320A Series

(November, 2012, Version 1.7) 37 AMIC Technology, Corp.

Addresses

Data

VCC

55h 30h

Erase Command Sequence (last two cycles)

Complete

Progress

VCS

Read Status Data

2AAh

WHWH2

WPH

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustratin shows device in word mode.

555h for chip erase

10h for chip erase

BUSY

RY/BY

Timing Waveforms for Chip/Sector Erase Operation

A29L320A Series

(November, 2012, Version 1.7) 38 AMIC Technology, Corp.

Timing Waveforms for Data Polling (During Embedded Algorithms)

Addresses

I/O7

tRC

VAVA VA

Complement

Complement True Valid Data High-Z

Status Data

Status Data True Valid Data High-Z

I/O0 - I/O6

tACC

tCE

tCH tOE

tOEH tDF

tOH

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

tBUSY

RY/BY

High-Z

A29L320A Series

(November, 2012, Version 1.7) 39 AMIC Technology, Corp.

Timing Waveforms for Toggle Bit (During Embedded Algorith m s)

Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Addresses

I/O

VAVA VA

Valid Status

ACC

OEH

Valid Status Valid Status Valid Data

(first read) (second read) (stop togging)

RY/BY

BUSY

High-Z

A29L320A Series

(November, 2012, Version 1.7) 40 AMIC Technology, Corp.

Timing Waveforms for Sector Protec t/Unpr otect

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

RESET

SA, A6,

A1, A0

Data

Valid* Valid* Valid*

60h 60h 40h Status

Sector Protect/Unprotect Verify

1us Sector Protect:150us

Sector Unprotect:15ms

Timing Waveforms for I/O2 vs. I/O6

Enter

Embedded

Erasing

Erase

Suspend Enter Erase

Suspend Program Erase

Resume

I/O

Erase Erase Suspend

Read Erase Suspend

Read Erase Erase

Complete

I/O

and I/O

toggle with OE and CE

Note : Both I/O

and I/O

toggle with OE or CE. See the text on I/O

and I/O

in the section "Write Operation Status" for

more information.

Erase

Suspend

Program

A29L320A Series

(November, 2012, Version 1.7) 41 AMIC Technology, Corp.

Timing Waveforms for A l ternate CE Controlled Write Operation

Addresses

Data

555 for program

2AA for erase

OUT

I/O

Data Polling

Note :

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

= Complement of Data Input, D

OUT

= Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

PD for program

30 for sector erase

10 for chip erase

BUSY

WHWH1 or 2

CPH

PA for program

SA for sector erase

555 for chip erase

A0 for program

55 for erase

RESET

RY/BY

Erase and Programming Performance

Parameter Typ. (Note 1) Unit Comments

Sector Erase Time 1.0 sec

Chip Erase Time 45 sec

Excludes 00h programming prior to erasure

Byte Programming Time 20 μs

Word Programming Time 40 μs

Byte Mode 32 sec Chip Programming Time

(Note 2) Word Mode 20 sec

Excludes system-level overhead (Note 4)

Notes:

1. Typical program and erase times assume the follo wing conditions: 25 °C, 3.0V VCC, 10, 000 cycles. Addition ally, progr amming

typically assumes checkerboard pattern.

2. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed . If the maximum byte program time given is exceeded, only then

does the device set I/O5 = 1. See the section on I/O5 for further information.

3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programm ed to 00h before erasure.

4. System-level overhead is the time requ ired to execute the four-bus-cycle command se quence for programming. See Table 9

for further information on command definiti ons.

5. The device has a guaranteed minimum erase an d program cycle endurance of 100, 000 cycles.

A29L320A Series

(November, 2012, Version 1.7) 42 AMIC Technology, Corp.

Latch-up Characteristics

Description Min. Max.

Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V

VCC Current -100 mA +100 mA

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE and RESET) -1.0V 12.5V

Includes all pins except VCC. T est conditio ns: VCC = 5.0V, one pin at time.

TSOP/TFBGA Pin Capacitance

Parameter Symbol Paramete r Description Test Setup Typ. Max. Unit

TSOP 6 7.5 pF

CIN Input Capacitance VIN=0 TFBGA 4.2 5 pF

TSOP 8.5 12 pF

COUT Output Capacitance VOUT=0 TFBGA 5.4 6.5 pF

TSOP 7.5 9 pF

CIN2 Control Pin Capacitance VIN=0 TFBGA 3.9 4.7 pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0MHz

Data Retention

Parameter Test Conditions Min Unit

150°C 10 Years

Minimum Pattern Data Retention Time 125°C 20 Years

A29L320A Series

(November, 2012, Version 1.7) 43 AMIC Technology, Corp.

Test Conditions

Test Specifications

Test Condition -70 -80 -90 -120 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL(including jig capacitance) 30 100 100 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0 – VCC V

Input timing measurement referenc e levels 0.5VCC V

Output timing measurement reference levels 0.5VCC V

Test Setup

Input Waveforms and Measuremen t Levels

Measurement Level

Input 0.5VCC 0.5VCC Output

VCC

0.0V

6.2 KW

Device

Under

Test

CLDiodes = I N3064 or Equi valent

2.7 KW

3.0V

A29L320A Series

(November, 2012, Version 1.7) 44 AMIC Technology, Corp.

Ordering Information

Top Boot Sector Flash

Part No. Access Time

(ns)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (μA) Package

A29L320ATV-70F 48 Pin Pb-Free TSOP

A29L320ATV-70UF 48 Pin Pb-Free TSOP

A29L320ATV-70IF 48 Pin Pb-Free TSOP

A29L320ATG-70F 48 ball Pb-Free TFBGA

A29L320ATG-70UF 48 ball Pb-Free TFBGA

A29L320ATG-70IF

70 10 20 0.5

48 ball Pb-Free TFBGA

A29L320ATV-80F 48 Pin Pb-Free TSOP

A29L320ATV-80UF 48 Pin Pb-Free TSOP

A29L320ATV-80IF 48 Pin Pb-Free TSOP

A29L320ATG-80F 48 ball Pb-Free TFBGA

A29L320ATG-80UF 48 ball Pb-Free TFBGA

A29L320ATG-80IF

80 10 20 0.5

48 ball Pb-Free TFBGA

A29L320ATV-90F 48 Pin Pb-Free TSOP

A29L320ATV-90UF 48 Pin Pb-Free TSOP

A29L320ATV-90IF 48 Pin Pb-Free TSOP

A29L320ATG-90F 48 ball Pb-Free TFBGA

A29L320ATG-90UF 48 ball Pb-Free TFBGA

A29L320ATG-90IF

90 10 20 0.5

48 ball Pb-Free TFBGA

A29L320ATV-120F 48 Pin Pb-Free TSOP

A29L320ATV-120UF 48 Pin Pb-Free TSOP

A29L320ATV-120IF 48 Pin Pb-Free TSOP

A29L320ATG-120F 48 ball Pb-Free TFBGA

A29L320ATG-120UF 48 ball Pb-Free TFBGA

A29L320ATG-120IF

120 10 20 0.5

48 ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

A29L320A Series

(November, 2012, Version 1.7) 45 AMIC Technology, Corp.

Ordering Information (continued)

Bottom Boot Sector Flash

Part No. Access Time

(ns)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (μA) Package

A29L320AUV-70F 48 Pin Pb-Free TSOP

A29L320AUV-70UF 48 Pin Pb-Free TSOP

A29L320AUV-70IF 48 Pin Pb-Free TSOP

A29L320AUG-70F 48 ball Pb-Free TFBGA

A29L320AUG-70UF 48 ball Pb-Free TFBGA

A29L320AUG-70IF

70 10 20 0.5

48 ball Pb-Free TFBGA

A29L320AUV-80F 48 Pin Pb-Free TSOP

A29L320AUV-80UF 48 Pin Pb-Free TSOP

A29L320AUV-80IF 48 Pin Pb-Free TSOP

A29L320AUG-80F 48 ball Pb-Free TFBGA

A29L320AUG-80UF 48 ball Pb-Free TFBGA

A29L320AUG-80IF

80 10 20 0.5

48 ball Pb-Free TFBGA

A29L320AUV-90F 48 Pin Pb-Free TSOP

A29L320AUV-90UF 48 Pin Pb-Free TSOP

A29L320AUV-90IF 48 Pin Pb-Free TSOP

A29L320AUG-90F 48 ball Pb-Free TFBGA

A29L320AUG-90UF 48 ball Pb-Free TFBGA

A29L320AUG-90IF

90 10 20 0.5

48 ball Pb-Free TFBGA

A29L320AUV-120F 48 Pin Pb-Free TSOP

A29L320AUV-120UF 48 Pin Pb-Free TSOP

A29L320AUV-120IF 48 Pin Pb-Free TSOP

A29L320AUG-120F 48 ball Pb-Free TFBGA

A29L320AUG-120UF 48 ball Pb-Free TFBGA

A29L320AUG-120IF

120 10 20 0.5

48 ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

A29L320A Series

(November, 2012, Version 1.7) 46 AMIC Technology, Corp.

Package Information

TSOP 48L (Type I) Outline Dimensions unit: inches/mm

Detail "A"

0.25

24 25

SA1

A2A

Detail "A"

Dimensions in inches Dimensio ns in mm

Symbol Min Nom Max Min Nom Max

A - - 0.047 - - 1.20

A1 0.002 - 0.006 0.05 - 0.15

A2 0.037 0.039 0.042 0.94 1.00 1.06

b 0.007 0.009 0.011 0.18 0.22 0.27

c 0.004 - 0.008 0.12 - 0.20

D 0.779 0.787 0.795 19.80 20.00 20.20

D1 0.720 0.724 0.728 18.30 18.40 18.50

E - 0.472 0.476 - 12.00 12.10

e 0.020 BASIC 0.50 BASIC

L 0.020 0.024 0.0275 0.50 0.60 0.70

S 0.011 Typ. 0.28 Typ.

y - - 0.004 - - 0.10

θ 0° - 8° 0° - 8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flas h.

A29L320A Series

(November, 2012, Version 1.7) 47 AMIC Technology, Corp.

Package Information

48LD CSP (6 x 8 mm) Outline Dimensions unit: mm

(48TFBGA)

TOP VIEW

SIDE VIEW

C SEATING PLANE

654321

BOTTOM VIEW

Ball*A1 CORNER

0.10 C

123456

Dimensions in mm

Symbol Min. Nom. Max.

A - - 1.20

A1 0.20 0.25 0.30

b 0.30 - 0.40

D 5.90 6.00 6.10

D1 4.00 BSC

e - 0.80 -

E 7.90 8.00 8.10

E1 5.60 BSC