19-2231; Rev 3; 8/10 KIT ATION EVALU E L B AVAILA 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs Features The MAX1286-MAX1289 are low-cost, micropower, serial output 12-bit analog-to-digital converters (ADCs) available in a tiny 8-pin SOT23 and an 8-pin TDFN. The MAX1286/MAX1288 operate with a single +5V supply. The MAX1287/MAX1289 operate with a single +3V supply. The devices feature a successive-approximation ADC, automatic shutdown, fast wakeup (1.4s), and a high-speed 3-wire interface. Power consumption is only 0.5mW (VDD = +2.7V) at the maximum sampling rate of 150ksps. AutoShutdownTM (0.2A) between conversions results in reduced power consumption at slower throughput rates. The MAX1286/MAX1287 provide 2-channel, single-ended operations and accept input signals from 0 to VREF. The MAX1288/MAX1289 accept true-differential inputs ranging from 0 to VREF. Data is accessed using an external clock through the 3-wire SPITM-/QSPITM-/MICROWIRETM-compatible serial interface. Excellent dynamic performance, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low power consumption and minimal space. o Single-Supply Operation +3V (MAX1287/MAX1289) +5V (MAX1286/MAX1288) o Autoshutdown Between Conversions o Low Power 245A at 150ksps 150A at 100ksps 15A at 10ksps 2A at 1ksps 0.2A in Shutdown o True-Differential Track/Hold, 150kHz Sampling Rate o Software-Configurable Unipolar/Bipolar Conversion (MAX1288/MAX1289 Only) o SPI-/QSPI-/MICROWIRE-Compatible Interface for DSPs and Processors o Internal Conversion Clock o 8-Pin SOT23 and 8-Pin TDFN Packages Ordering Information Applications Low-Power Data Acquisition PART Portable Temperature Monitors PIN-PACKAGE TOP MARK MAX1286EKA-T 8 SOT23 AAFA Flowmeters MAX1286ETA+T 8 TDFN-EP* +AFR Touch Screens MAX1287EKA-T 8 SOT23 AAEW MAX1287ETA+T 8 TDFN-EP* +AFN MAX1288EKA-T 8 SOT23 AAFC MAX1288ETA+T 8 TDFN-EP* +AFT MAX1289EKA-T 8 SOT23 AAEY MAX1289ETA+T 8 TDFN-EP* +AFP VDD 1 AIN1 (AIN+) 2 AIN2 (AIN-) 3 MAX1286- MAX1289 8 SCLK 7 DOUT 6 CNVST 5 REF DOUT CNVST REF TOP VIEW SCLK Pin Configurations 8 7 6 5 MAX1286- MAX1289 ( ) ARE FOR THE MAX1288/MAX1289 2 3 4 AIN2 (AIN-) GND VDD SOT23 + 1 AIN1 (AIN+) EP GND 4 Note: All devices specified over the -40C to +85C operating range. +Denotes a lead(Pb)-free/RoHS-compliant package. -Denotes a package containing lead(Pb). *EP = Exposed pad. TDFN AutoShutdown is a trademark of Maxim Integrated Products, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX1286-MAX1289 General Description MAX1286-MAX1289 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CNVST, SCLK, DOUT to GND....................-0.3V to (VDD + 0.3V) REF, AIN1 (AIN+), AIN2 (AIN-) to GND......-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin SOT23 (derate 9.70mW/C above TA = +70C) ...696mW 8-Pin TDFN (derate 18.5mW/C above TA = +70C) ...1481mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) Lead(Pb)-Free Packages...............................................+260C Packages Containing Lead(Pb).....................................+240C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1286/MAX1288, 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.0 LSB DC ACCURACY (Note 1) Resolution 12 Relative Accuracy (Note 2) INL Differential Nonlinearity DNL Bits 1.0 LSB Offset Error 2 4 LSB Gain Error (Note 3) 2 4 LSB No missing codes over temperature Gain Temperature Coefficient 0.4 ppm/C Offset Temperature Coefficient 0.4 ppm/C Channel-to-Channel Offset Matching 0.1 LSB 0.1 LSB 0.1 mV Channel-to-Channel Gain Matching Input Common-Mode Rejection CMR VCM = 0V to VDD; zero scale input DYNAMIC SPECIFICATIONS: (fIN (sine-wave) = 10kHz, VIN = 4.096Vp-p for MAX1286/MAX1288 or VIN = 2.5Vp-p for MAX1287/MAX1289, 150ksps, fSCLK = 8MHz, (50% duty cycle) AIN- = GND for MAX1288/MAX1289) Signal to Noise Plus Distortion SINAD 70 dB Total Harmonic Distortion (up to the 5th harmonic) THD -82 dB Spurious-Free Dynamic Range SFDR Full-Power Bandwidth -3dB point Full-Linear Bandwidth SINAD > 68dB 86 dB 1 MHz 100 kHz CONVERSION RATE Conversion Time T/H Acquisition Time tCONV Does not include tACQ 3.7 tACQ 1.4 s s Aperture Delay 30 ns Aperture Jitter <50 ps Maximum Serial Clock Frequency fSCLK 8 Duty Cycle 30 MHz 70 % ANALOG INPUT Input Voltage Range (Note 4) 2 Unipolar Bipolar 0 VREF -VREF /2 VREF/2 _______________________________________________________________________________________ V 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs (VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1286/MAX1288, 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C.) PARAMETER SYMBOL Input Leakage Current CONDITIONS MIN Channel not selected or conversion stopped Input Capacitance TYP MAX UNITS 0.01 1 A 34 pF EXTERNAL REFERENCE INPUT Input Voltage Range VREF Input Current IREF VDD +50mV 1.0 VREF = +2.5V at 150ksps 16 30 VREF = +4.096V at 150ksps 26 45 0.01 1 Acquisition/Between conversions V A DIGITAL INPUTS/OUTPUTS (SCLK, CNVST, DOUT) Input Low Voltage VIL Input High Voltage VIH Input Leakage Current Input Capacitance CIN 15 Output Low Voltage VOL Output High Voltage VOH COUT 1.0 A V 0.01 Three-State Output Capacitance V VDD -1 IL Three-State Leakage Current 0.8 pF ISINK = 2mA 0.4 V ISINK = 4mA 0.8 V VDD -0.5 ISOURCE = 1.5mA V CNVST = GND 0.05 CNVST = GND 15 10 A pF POWER REQUIREMENTS Positive Supply Voltage VDD MAX1286/MAX1288 4.75 5.0 5.25 MAX1287/MAX1289 2.7 3.0 3.6 fSAMPLE =150ksps 245 350 fSAMPLE =100ksps 150 fSAMPLE =10ksps 15 VDD = +3V fSAMPLE =1ksps Positive Supply Current IDD VDD = +5V Positive Supply Rejection PSR V 2 fSAMPLE =150ksps 320 fSAMPLE =100ksps 215 fSAMPLE =10ksps 22 fSAMPLE =1ksps 2.5 400 Shutdown 0.2 5 VDD = 5V 5%; full-scale input 0.3 1.0 VDD = +2.7V to +3.6V; full-scale input 0.4 1.2 A mV _______________________________________________________________________________________ 3 MAX1286-MAX1289 ELECTRICAL CHARACTERISTICS (continued) MAX1286-MAX1289 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs TIMING CHARACTERISTICS (Figures 1, 2, and 5) (VDD = +2.7V to +3.6V, VREF = +2.5V, 0.1F capacitor at REF, or VDD = +4.75V to +5.25V for MAX1286/MAX1288, VREF = +4.096V, 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C.) PARAMETERS SYMBOL CONDITIONS MIN SCLK Pulse Width High tCH 38 SCLK Pulse Width Low tCL 38 TYP MAX UNITS ns ns SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 60 SCLK Rise to DOUT Disable tDOD CLOAD = 30pF 500 ns CNVST Rise to DOUT Enable tDOE CLOAD = 30pF 80 ns CNVST Fall to MSB Valid tCONV CLOAD = 30pF 3.7 s CNVST Pulse Width tCSW 100 30 ns ns Note 1: Unipolar mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset nulled. Note 4: The absolute input voltage range for the analog inputs is from GND to VDD. *** CNVST tCH tCL SCLK *** tDOT tDOE DOUT HIGH-Z tDOD HIGH-Z *** Figure 1. Detailed Serial-Interface Timing Sequence VDD 6k DOUT DOUT 6k CL GND a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z CL GND b) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z Figure 2. Load Circuits for Enable/Disable Times 4 tCSW _______________________________________________________________________________________ 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs INTEGRAL NONLINEARITY vs. OUTPUT CODE 0.6 0.4 0.2 0.2 0.2 0 -0.2 DNL (LSB) 0.4 0 -0.2 0 -0.2 -0.4 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 500 1000 1500 2000 2500 3000 3500 4000 4500 OUTPUT CODE OUTPUT CODE OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE SUPPLY CURRENT vs. SAMPLING RATE SUPPLY CURRENT vs. SAMPLING RATE MAX1287/MAX1289 SUPPLY CURRENT (A) 0.6 1000 0.4 0.2 0 -0.2 -0.4 100 1000 10 1 MAX1286-9 toc06 MAX1286/MAX1288 MAX1286/MAX1288 SUPPLY CURRENT (A) MAX1286-9 toc04 1.0 0.8 -1.0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 MAX1286-9 toc05 0 DNL (LSB) 0.6 MAX1287/MAX1289 0.8 0.4 INL (LSB) INL (LSB) 0.6 MAX1286/MAX1288 0.8 1.0 MAX1286-9 toc02 MAX1287/MAX1289 0.8 1.0 MAX1286-9 toc01 1.0 DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX1286-9 toc03 INTEGRAL NONLINEARITY vs. OUTPUT CODE 100 10 1 -0.6 -0.8 0.1 0 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 1 0.1 320 300 280 260 240 220 1 0.1 100 10 SAMPLING RATE (ksps) SHUTDOWN CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 300 250 200 150 100 1000 430 MAX1286 380 SUPPLY CURRENT (A) SUPPLY CURRENT (A) 340 0 1000 MAX1286-9 toc08 360 SHUTDOWN CURRENT (nA) MAX1286-9 toc07 380 100 SAMPLING RATE (ksps) OUTPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE 10 MAX1286-9 toc09 -1.0 330 280 230 50 200 180 180 0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 -40 -20 0 20 40 60 80 TEMPERATURE (C) _______________________________________________________________________________________ 5 MAX1286-MAX1289 Typical Operating Characteristics (VDD = +3V, VREF = +2.5V for MAX1287/MAX1289. VDD = +5V, VREF = +4.096V for MAX1286/MAX1288; 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.5V for MAX1287/MAX1284. VDD = +5V, VREF = +4.096V for MAX1286/MAX1288; 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, TA = +25C, unless otherwise noted.) SHUTDOWN CURRENT vs. TEMPERATURE OFFSET ERROR vs. TEMPERATURE 100 0 0.40 0.20 0.00 -0.20 -0.40 0.8 0.6 0 20 40 60 -1.0 -40 -20 0 20 40 60 TEMPERATURE (C) GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. SUPPLY VOLTAGE 0 -0.4 -0.8 0.4 0 -0.4 -0.8 -1.6 -1.6 -2.0 -20 0 20 40 TEMPERATURE (C) 60 80 4.7 0 -40 -60 -80 -100 -120 -2.0 -40 4.2 -20 0.8 -1.2 3.7 -140 2.7 3.2 3.7 4.2 VDD (V) 5.2 FFT PLOT (SINAD) 1.2 -1.2 3.2 20 AMPLITUDE (dB) 0.4 2.7 VDD (V) 1.6 GAIN ERROR (LSB) 0.8 80 2.0 MAX1286-9 toc13 1.2 -0.4 -0.8 TEMPERATURE (C) 1.6 0 -0.2 -0.6 80 2.0 0.2 -0.80 MAX1286-9 toc14 -20 0.4 -0.60 -1.00 -40 MAX1286-9 toc12 MAX1286-9 toc11 0.60 MAX1286-9 toc15 150 1.0 OFFSET ERROR (LSB) 200 50 6 0.80 OFFSET ERROR (LSB) SHUTDOWN CURRENT (nA) 250 OFFSET ERROR vs. SUPPLY VOLTAGE 1.00 MAX1286-9 toc10 300 GAIN ERROR (LSB) MAX1286-MAX1289 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs 4.7 5.2 0 15k 30k 45k FREQUENCY (Hz) _______________________________________________________________________________________ 60k 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs NAME PIN MAX1286 MAX1287 MAX1288 MAX1289 FUNCTION 1 VDD VDD Positive Supply Voltage. +2.7V to +3.6V (MAX1287/MAX1289); +4.75V to +5.25V (MAX1286/MAX1288). Bypass with a 0.1F capacitor to GND. 2 AIN1 AIN+ Analog Input Channel 1 (MAX1286/MAX1287) or Positive Analog Input (MAX1288/MAX1289) 3 AIN2 AIN- Analog Input Channel 2 (MAX1286/MAX1287) or Negative Analog Input (MAX1288/MAX1289) 4 GND GND Ground 5 REF REF External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1F capacitor to GND. 6 CNVST CNVST Conversion Start. A rising edge powers up the IC and places it in track mode. At the falling edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the input channel (MAX1286/MAX1287) or input polarity (MAX1288/MAX1289). 7 DOUT DOUT Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a conversion and presents the MSB at the completion of a conversion. DOUT goes high impedance once data has been fully clocked out. 8 SCLK SCLK -- EP EP Serial Clock Input. Clocks out data at DOUT MSB first. Exposed Pad. Connect the exposed pad to ground or leave unconnected. Detailed Description The MAX1286-MAX1289 ADCs use a successiveapproximation conversion (SAR) technique and an onchip track-and-hold (T/H) structure to convert an analog signal into a 12-bit digital result. The serial interface provides easy interfacing to microprocessors (Ps). Figure 3 shows the simplified internal structure for the MAX1286/MAX1287 (2 channels, single ended) and the MAX1288/MAX1289 (1 channel, true differential). True-Differential Analog Input T/H MAX1286-MAX1289 CNVST SCLK OSCILLATOR INPUT SHIFT REGISTER CONTROL AIN1 (AIN+) AIN2 (AIN-) T/H 12-BIT SAR ADC REF ( ) ARE FOR MAX1288/MAX1289 Figure 3. Simplified Functional Diagram DOUT The equivalent circuit of Figure 4 shows the MAX1286-MAX1289s' input architecture, which is composed of a T/H, input multiplexer, comparator, and switched-capacitor DAC. The T/H enters its tracking mode on the rising edge of CNVST. The positive input capacitor is connected to AIN1 or AIN2 (MAX1286/ MAX1287) or AIN+ (MAX1288/MAX1289). The negative input capacitor is connected to GND (MAX1286/ MAX1287) or AIN- (MAX1288/MAX1289). The T/H enters its hold mode on the falling edge of CNVST and the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and CNVST must be held high for a longer period of time. The acquisition time, tACQ, is the maximum time needed for the signal to be acquired, plus the power-up time. It is calculated by the following equation: tACQ = 9 x (RS + RIN) x 24pF + tPWR _______________________________________________________________________________________ 7 MAX1286-MAX1289 Pin Description MAX1286-MAX1289 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is selected for the next conversion. REF GND AIN2 AIN1 (AIN+) DAC Selecting Unipolar or Bipolar Conversions (MAX1288/MAX1289) CIN+ COMPARATOR + HOLD CINRIN- GND (AIN-) RIN+ HOLD ( ) ARE FOR MAX1288/MAX1289 VDD/2 HOLD TRACK Figure 4. Equivalent Input Circuit where RIN = 1.5k, RS is the source impedance of the input signal, and tPWR = 1s is the power-up time of the device. Note: tACQ is never less than 1.4s and any source impedance below 300 does not significantly affect the ADC's AC performance. A high-impedance source can be accommodated either by lengthening tACQ or by placing a 1F capacitor between the positive and negative analog inputs. Selecting AIN1 or AIN2 (MAX1286/MAX1287) Select one of the MAX1286/MAX1287s' two positive input channels using the CNVST pin. If AIN1 is desired (Figure 5a), drive CNVST high to power up the ADC and place the T/H in track mode with AIN1 connected to the positive input capacitor. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC then performs a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Clock out all 12 bits of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is selected for the next conversion. If AIN2 is desired (Figure 5b), drive CNVST high for at least 30ns. Next, drive it low for at least 30ns, and then high again. This powers up the ADC and places the T/H in track mode with AIN2 connected to the positive input capacitor. Now hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC then performs a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. 8 Initiate true-differential conversions with the MAX1288/MAX1289s' unipolar and bipolar modes, using the CNVST pin. AIN+ and AIN- are sampled at the falling edge of CNVST. In unipolar mode, AIN+ can exceed AIN- by up to V REF . The output format is straight binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format is two's complement. Note: In both modes, AIN+ and AIN- must not exceed VDD by more than 50mV or be lower than GND by more than 50mV. If unipolar mode is desired (Figure 5a), drive CNVST high to power up the ADC and place the T/H in track mode with AIN+ and AIN- connected to the input capacitors. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC then performs a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Clock out all 12 bits of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode is selected for the next conversion. If bipolar mode is desired (Figure 5b), drive CNVST high for at least 30ns. Next, drive it low for at least 30ns and then high again. This places the T/H in track mode with AIN+ and AIN- connected to the input capacitors. Now hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC then performs a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode is selected for the next conversion. Input Bandwidth The ADC's input tracking circuitry has a 1MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. _______________________________________________________________________________________ 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs MAX1286-MAX1289 tCONV tACQ CNVST 1 SCLK B11 MSB DOUT HIGH-Z 4 B10 B9 B8 8 B7 B6 B5 B4 12 B3 B2 B1 B0 LSB HIGH-Z SAMPLING INSTANT Figure 5a. Single Conversion AIN1 vs. GND (MAX1286/MAX1287), Unipolar Mode AIN+ vs. AIN- (MAX1288/MAX1289) tCONV tACQ CNVST SCLK DOUT HIGH-Z 1 B11 MSB 4 B10 B9 B8 8 B7 B6 B5 B4 12 B3 B2 B1 B0 LSB HIGH-Z SAMPLING INSTANT Figure 5b. Single Conversion AIN2 vs. GND (MAX1286/MAX1287), Bipolar Mode AIN+ vs. AIN- (MAX1288/MAX1289) Analog Input Protection Internal Clock Internal protection diodes that clamp the analog input to VDD and GND allow the analog input pins to swing from GND - 0.3V to VDD + 0.3V without damage. Both inputs must not exceed VDD by more than 50mV or be lower than GND by more than 50mV for accurate conversions. If an off-channel analog input voltage exceeds the supplies, limit the input current to 2mA. The MAX1286-MAX1289 operate from an internal oscillator, which is accurate within 10% of the 4MHz specified clock rate. This results in a worst-case conversion time of 3.7s. The internal clock releases the system microprocessor from running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate from 0 to 8MHz. _______________________________________________________________________________________ 9 MAX1286-MAX1289 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs Output Data Format External Reference Figures 5a and 5b illustrate the conversion timing for the MAX1286-MAX1289. The 12-bit conversion result is output in MSB-first format. Data on DOUT transitions on the falling edge of SCLK. All 12 bits must be clocked out before CNVST transitions again. For the MAX1288/ MAX1289, data is straight binary for unipolar mode and two's complement for bipolar mode. For the MAX1286/ MAX1287, data is always straight binary. An external reference is required for the MAX1286- MAX1289. Use a 0.1F bypass capacitor for best performance. The reference input structure allows a voltage range of +1V to VDD + 50mV. Transfer Function Figure 6 shows the unipolar transfer function for the MAX1286-MAX1289. Figure 7 shows the bipolar transfer function for the MAX1288/MAX1289. Code transitions occur halfway between successive-integer LSB values. Applications Information Automatic Shutdown Mode With CNVST low, the MAX1286-MAX1289 default to an AutoShutdown state (< 0.2A) after power-up and between conversions. After detecting a rising edge on CNVST, the part powers up, sets DOUT low, and enters track mode. After detecting a falling edge on CNVST, the device enters hold mode and begins the conversion. A maximum of 3.7s later, the device completes conversion, enters shutdown, and MSB is available at DOUT. Connection to Standard Interfaces The MAX1286-MAX1289 feature a serial interface that is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is available, establish the CPU's serial interface as a master, so that the CPU generates the serial clock for the ADCs. Select a clock frequency up to 8MHz. How to Perform a Conversion 1) 2) 3) 4) Use a general-purpose I/O line on the CPU to hold CNVST low between conversions. Drive CNVST high to acquire AIN1(MAX1286/ MAX1287) or unipolar mode (MAX1288/MAX1289). To acquire AIN2 (MAX1286/MAX1287) or bipolar mode (MAX1288/MAX1289), drive CNVST low and high again. Hold CNVST high for 1.4s. Drive CNVST low and wait approximately 3.7s for conversion to complete. After 3.7s, the MSB is available at DOUT. OUTPUT CODE MAX1288/MAX1289 OUTPUT CODE FULL-SCALE TRANSITION 11 . . . 111 MAX1286- MAX1289 011 . . . 111 FS = VREF 2 011 . . . 110 ZS = 0 11 . . . 110 11 . . . 101 000 . . . 010 000 . . . 001 -VREF 2 V 1 LSB = REF 4096 -FS = 000 . . . 000 FS = VREF 00 . . . 011 111 . . . 111 ZS = GND 111 . . . 110 V 1 LSB = REF 4096 111 . . . 101 00 . . . 010 100 . . . 001 00 . . . 001 100 . . . 000 00 . . . 000 0 1 2 3 INPUT VOLTAGE (LSB) Figure 6. Unipolar Transfer Function 10 FS FS - 3/2 LSB 0 - FS INPUT VOLTAGE (LSB) *VCOM VREF / 2 *VIN = (AIN+) - (AIN-) Figure 7. Bipolar Transfer Function ______________________________________________________________________________________ +FS - 1 LSB 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs Activate SCLK for a minimum of 12 rising clock edges. DOUT transitions on SCLK's falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the P on SCLK's rising edge. SPI and MICROWIRE Interface When using an SPI (Figure 8a) or MICROWIRE interface (Figures 8a and 8b), set CPOL = CPHA = 0. Two 8-bit readings are necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the P on SCLK's rising edge. The first 8-bit data stream contains the first 8-bits of DOUT starting with the MSB. The second 8-bit data stream contains the remaining four result bits. DOUT then goes high impedance. QSPI Interface Using the high-speed QSPI interface (Figure 9a) with CPOL = 0 and CPHA = 0, the MAX1286-MAX1289 support a maximum fSCLK of 8MHz. One 12- to 16-bit reading is necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the P on I/O CNVST SCK SCLK MISO SCLK's rising edge. The first 12 bits are the data. DOUT then goes high impedance (Figure 9b). PIC16 and SSP Module and PIC17 Interface The MAX1286-MAX1289 are compatible with a PIC16/PIC17 C, using the synchronous serial port (SSP) module To establish SPI communication, connect the controller as shown in Figure 10a and configure the PIC16/PIC17 as system master. This is done by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 1 and 2. In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (Figure 10b) are necessary to obtain the entire 12-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the C on SCLK's rising edge. The first 8-bit data stream contains the first 8 data bits starting with the MSB. The second data stream contains the remaining bits, D3 through D0. DOUT VDD SPI I/O CNVST SK SCLK SI DOUT MICROWIRE MAX1286- MAX1289 SS MAX1286- MAX1289 Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections Table 1. Detailed SSPCON Register Content MAX1286-MAX1289 SETTINGS CONTROL BIT SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON) WCOL Bit 7 X Write Collision Detection Bit SSPOV Bit 6 X Receive Overflow Detect Bit SSPEN Bit 5 1 Synchronous Serial Port Enable Bit: 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master mode selection. CKP Bit 4 0 SSPM3 Bit 3 0 SSPM2 Bit 2 0 SSPM1 Bit 1 0 SSPM0 Bit 0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects FCLK = fOSC / 16. ______________________________________________________________________________________ 11 MAX1286-MAX1289 5) MAX1286-MAX1289 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs CNVST 1ST BYTE READ 1 2ND BYTE READ 4 12 8 16 SCLK B11 MSB DOUT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LSB HIGH-Z SAMPLING INSTANT Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0) Layout, Grounding, and Bypassing For best performance, use printed circuit (PC) boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only CS CNVST SCK SCLK MISO QSPI DOUT VDD one starpoint (Figure 11), connecting the two ground systems (analog and digital). For lowest-noise operation, ensure the ground return to the star ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) may degrade the performance of the ADC's fast comparator. Bypass VDD to the star ground with a 0.1F capacitor, located as close as possible to the MAX1286-MAX1289s' power-supply pin. Minimize capacitor lead length for best supply-noise rejection. Add an attenuation resistor (5) if the power supply is extremely noisy. MAX1286- MAX1289 SS Figure 9a. QSPI Connections Table 2. Detailed SSPSTAT Register Content CONTROL BIT 12 MAX1286-MAX1289 SETTINGS SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT) SMP Bit 7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. CKE Bit 6 1 SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock. D/A Bit 5 X Data Address Bit P Bit 4 X Stop Bit S Bit 3 X Start Bit R/W Bit 2 X Read/Write Bit Information UA Bit 1 X Update Address BF Bit 0 X Buffer Full Status Bit ______________________________________________________________________________________ 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs 1 4 16 12 8 SCLK B11 MSB DOUT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 HIGH-Z B0 LSB SAMPLING INSTANT Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0) Definitions VDD VDD SCLK SCK DOUT SDI CNVST I/O Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1286-MAX1289 are measured using the end-point method. PIC16/PIC17 MAX1286- MAX1289 Differential Nonlinearity GND GND Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller CNVST 1ST BYTE READ 1 2ND BYTE READ 4 12 8 16 SCLK DOUT B11 MSB B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LSB HIGH-Z SAMPLING INSTANT Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001) ______________________________________________________________________________________ 13 MAX1286-MAX1289 CNVST 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs MAX1286-MAX1289 Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 log (SignalRMS / NoiseRMS) SUPPLIES +5V OR +3V VLOGIC = +5V OR +3V GND R* = 5 0.1F VDD GND MAX1286- MAX1289 +5V OR +3V DGND DIGITAL CIRCUITRY *OPTIONAL Figure 11. Power-Supply and Grounding Connections Aperture Definitions Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture delay (tAD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-todigital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR = (6.02 N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. 14 Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V42 + V52 THD = 20 x log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Chip Information TRANSISTOR COUNT: 6922 PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 8 SOT23 PACKAGE CODE K8F-4 8 TDFN T833+2 21-0078 LAND PATTERN NO. 90-0176 21-0137 90-0059 OUTLINE NO. ______________________________________________________________________________________ 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs REVISION REVISION 3 8/10 DESCRIPTION Added exposed pad to TDFN package and soldering temperature PAGES CHANGED 1, 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX1286-MAX1289 Revision History