2008 Microchip Technology Inc. DS22105A-page 1
24AA02H/24LC02BH
Device Selection Table
Features:
• Single Supply with Operation down to 1.7V for
24AA02H Devices, 2.5V for 24LC02BH Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1 A, max. (I-temp)
• 2-Wire Serial Inte rfac e, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slop e Control t o El im ina te Gro und Bounc e
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 8-Byte P age Write Buffer
• Hardware Write-Protect for Half-Array (80h-FFh)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
TDFN, MSOP, 5-lead SOT- 23 and SC-70
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA02H/24LC02BH
(24XX02H*) is a 2 Kbit Electrically Erasable PROM.
The device is organized as one block of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 A and 1 mA, respec-
tively. T he 24XX02H also has a p age write cap ability for
up to 8 by t es o f data. T h e 24 XX 02 H i s av ai l ab l e i n t he
standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3
TDFN and MSOP packages, and is also available in
the 5-lead SOT-23 and SC-70 packages.
Package Types
Block Diagram
Part
Number VCC
Range Max. Clock
Frequency Temp.
Ranges
24AA02H 1.7-5.5 400 kHz(1) I
24LC02BH 2.5-5.5 400 kHz I, E
Note 1: 100 kHz for VCC <2.5V
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP, MSOP SOIC, TSSOP
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
TDFN
A0
A1
A2
VSS
WP
SCL
SDA
VCC
SOT-23/SC-70
15
4
3
SCL
Vss
SDA
WP
Vcc
2
Note: Pins A0, A1 and A2 are not used by the 24XX02H
(no internal connections).
8
7
6
5
1
2
3
4
HV
EEPROM
Array
Page
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
VCC
VSS R/W Control
Latches
Generator
2K I2C™ Serial EEPROM with Half-Array Write-Protect
24AA02H/24LC02BH
DS22105A-page 2 2008 Microchip Technology Inc.
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a s tres s rati ng only a nd fun ct ion al operat ion of the device at th ose or any o ther cond iti ons a bove th ose
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS Electrical Characteristics:
Industri al (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
D1 — A0, A1, A2, SCL, SDA
and WP pins: ————
D2 VIH High-level input voltage 0.7 VCC —V—
D3 VIL Low-level input voltage — 0.3 VCC V—
D4 VHYS Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC —V(Note)
D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
D6 ILI Input leakage current — ±1 AVIN = VSS or VCC, WP = VSS
D7 ILO Output leaka ge curre nt — ±1 AVOUT = VSS or VCC
D8 CIN,
COUT Pin capacitance
(all inputs/ou tpu t s) —10pFVCC = 5.0V (Note)
TA = 25°C, f = 1 MHz
D9 ICC Read Operating current — 1 mA VCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
D10 ICCS Standby current — 1 AVCC = 5.5V, SCL = SDA = VCC
WP = VSS, A0, A1, A2 = VSS
Note: This parameter is periodically sampled and not 100% tested.
2008 Microchip Technology Inc. DS22105A-page 3
24AA02H/24LC02BH
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—100
400 kHz 1.7V VCC < 2.5V
2.5V VCC 5.5V
2THIGH Clock high time 4000
600 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
3TLOW Clock low time 4700
1300 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
4T
RSDA and SCL rise time
(Note 1) —
—1000
300 ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
5TFSDA and SCL fall time
(Note 1) —
—1000
300 ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
6T
HD:STA Start condition hold time 4000
600 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
7T
SU:STA Start condition setup time 4700
600 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
8THD:DAT Data input hold time 0 — ns (Note 2)
9T
SU:DAT Data input setup time 250
100 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
10 TSU:STO Stop condition set up time 4 000
600 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
11 TSU:WP WP setup time 4000
600 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
12 THD:WP WP hold time 4700
600 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
13 TAA Output valid from clock
(Note 2) —
—3500
900 ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
1300
4700 —
—ns 1.7V VCC < 2.5V
2.5V VCC 5.5V
16 TSP Input filter spike suppression
(SDA and SCL pins) —50ns(Note 1 and Note 3)
17 TWC Write cycle time (byte or
page) —5ms—
18 — Enduran c e 1M — cycl es 25°C , VCC = 5.5V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combi ned TSP and VHYS spec ifi cat ion s are due to new Sc hm itt Trigger inputs, wh ic h p r ovide impro ve d
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance es timates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
24AA02H/24LC02BH
DS22105A-page 4 2008 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
In
SDA
Out
WP
5
7
6
16
3
2
89
13
D4 4
10
11 12
14
2008 Microchip Technology Inc. DS22105A-page 5
24AA02H/24LC02BH
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1, A2
The A0, A1 and A 2 pins are not used by the 24XX02H .
They may be left floating or tied to either VSS or VCC.
2.2 Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the de vice . Sinc e it i s an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3 Serial Clock (SCL)
The SCL in pu t is u se d to s ynchro ni ze th e da t a transfer
to and from the device.
2.4 Wr it e-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/wri te the ent ire mem ory 00-FF).
If tied to VCC, writ e ope rati ons are inhi bited. Half of th e
memory will be write-protected (80h-FFh). Read
operations are not af fec ted.
Name PDIP SOIC TSSOP DFN MSOP SOT23 SC-70 Description
A011111——Not Connected
A122222——Not Connected
A233333——Not Connected
VSS 4444422Ground
SDA5555533Serial Address/Data I/O
SCL6666611Serial Clock
WP7777755Write-Protect Input
VCC 8888844+1.7V to 5.5V Power
Supply
24AA02H/24LC02BH
DS22105A-page 6 2008 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The 24XX02H supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XX02H
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figu re 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 S top Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. Th e mast er device mus t ge nera te a n ex tra c lock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line d uring th e ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to t he sla ve by not ge nerati ng an Ac knowl edge b it
on the las t by te that has be en c loc ke d ou t of th e sl av e.
In this case, the slave (24XX02H) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 4-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX02H does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
2008 Microchip Technology Inc. DS22105A-page 7
24AA02H/24LC02BH
4.6 Device Addressing
A control byte is the first byte received following the
S tar t condition from the m aster device . The co ntrol byte
consists of a four-bit control code. For the 24XX02H,
this is set as ‘1010’ binary for read and write opera-
tions. The next three bits of the control byte are “don’t
cares” for the 24XX02H.
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
select ed. W hen set to ‘0’ , a write operati on is se lecte d.
Following the Start condition, the 24XX02H monitors
the SDA bus, checking the device type identifier being
transmi tted and , up on a ‘1010’ code, the s la ve dev ic e
outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24XX02H
will select a read or write operation.
FIGU RE 4-2 : CO NTROL BYTE
ALLOCATION
Operation Control
Code Block Select R/W
Read 1010 Block Addre ss 1
Write 1010 Block Address 0
1010xxx
R/W ACK
Start Bit
Read/Write Bit
x = “don’t care”
S
Slave Address
Acknowledge Bit
Control Code
Block
Select
Bits
24AA02H/24LC02BH
DS22105A-page 8 2008 Microchip Technology Inc.
5.0 WRITE OPERATION
5.1 Byte Write
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits, “don’t
cares”) and the R/W bit which is a logic low, is placed
onto the bus by the master transmitter . This indicates to
the addressed slave receiver that a byte with a word
address will follow once it has generated an Acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word address
and will be written into the Address Pointer of the
24XX02H. After receiving another Acknowledge signal
from the 24XX02H, the master device will transmit the
data word to be written into the addressed memory
location. The 24XX02H acknowledges again and the
master generates a Stop condition. This initiates the
internal write cycle and, during this time, the 24XX02H
will not generate Acknowledge signals (Figure 5-1).
5.2 Page Write
The write-con trol byte, word address and the first data
byte are transmitted to the 24XX0 2H in the same way
as in a byte write. However , instead of generating a Stop
condition, the master transmits up to 8 data bytes to the
24XX02H, which are temporarily stored in the on-chip
page buffer and will be written into memory once the
master has transmitted a Stop condition. Upon receipt
of each word, the four lower-order Address Pointer bits
are internally incremented by ‘1’. The higher-order 7
bits of the w ord a ddr ess remai n co nstant. If t he ma ster
should transmit more than 8 words prior to generating
the S top condition, the address counter will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received an internal write cycle will begin (Figure 5-2).
FIGURE 5-1: BYTE WRITE
FIGURE 5-2: PAG E WRITE
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page siz e’ ) an d end at ad dres s es that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritten to the next page, as migh t be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
Bus Acti vity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
x = “don’t care”
1010xxx0
Block
Select
Bits
S P
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
A
R
T
Control
Byte Word
Address (n) Data (n) Data (n + 7)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
x = don’t care
Block
Select
Bits
10 10xxx0
2008 Microchip Technology Inc. DS22105A-page 9
24AA02H/24LC02BH
6.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiate s the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a S tart c ondition fo llowed by t he contro l
byte for a W rite command (R/W = 0). If the device is still
busy wi th the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 6-1 for a flow diagram of
this operation.
FIGURE 6-1: ACKNOWLEDGE
POLLING FLOW
7.0 WRITE PROTECTION
The WP pin allows the user to write-protect half of the
array (80h-FFh) when the pin is tied to VCC. If tied to
VSS, the write protection is disabled.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA02H/24LC02BH
DS22105A-page 10 2008 Microchip Technology Inc.
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operat ions: current add ress read , rand om rea d
and sequential read.
8.1 Current Address Read
The 24XX02H contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous access
(either a re ad or write opera tion) was to ad dre ss n, the
next curren t addre ss read operation woul d access data
from address n + 1. Upon rece ipt of the s lave add ress
with R/W bit set to ‘1’, the 24X X02H issues an acknowl-
edge and tran smits the 8-bit dat a word. The maste r will
not acknowledge the transfer , but does gene rate a Stop
conditi on, an d t he 24XX0 2H dis conti nues t ransm issio n
(Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX0 2H as part of a wr ite operati on.
Once the w ord ad dress is sent , t he master gen erate s
a Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then
issues the cont ro l byt e aga in, but with th e R /W bi t set
to a ‘1’. The 24XX02H will then issue an acknowledge
and transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition, and the 24XX02H will discontinue
transmission (Figure 8-2).
8.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random read, exc ep t tha t once the 2 4XX0 2H tran sm its
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX02H to transmit the next sequentially-
addressed 8-bit word (Figure 8-3).
To provide sequen tia l rea ds , the 24 XX02H c ontains a n
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4 Noise Protection
The 24XX02H employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 8-1: CURRENT ADDRESS READ
SP
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte Data (n)
A
C
K
N
o
A
C
K
S
T
A
R
T
1010xxx1
Block
Select
Bits
x = “don’t care”
2008 Microchip Technology Inc. DS22105A-page 11
24AA02H/24LC02BH
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTI AL READ
S P
S
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
A
R
T
S
T
O
P
Control
Byte
A
C
K
Word
Address (n) Control
Byte
S
T
A
R
TData (n)
A
C
K
A
C
K
N
o
A
C
K
1010xxx01010xxx1
Block
Select
Bits
x = “don’t care”
Block
Select
Bits
P
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
O
P
Control
Byte
A
C
K
N
o
A
C
K
Data (n) Data (n + 1) Data (n + 2) Data (n + x)
A
C
K
A
C
K
A
C
K
1
24AA02H/24LC02BH
DS22105A-page 12 2008 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP Example:
24LC02BH
I/P 13F
0527
24LC02BHI
SN 0527
13F
XXXX
TYWW
NNN
4L2H
I527
13F
5-Lead SO T-23 Example:
XXNN 2Q3F
3
e
3
e
8-Lead MSOP Example:
XXXXXT
YWWNNN 4L2BHI
52713F
2008 Microchip Technology Inc. DS22105A-page 13
24AA02H/24LC02BH
Part Number
1st Line Marking Codes
TSSOP MSOP SOT-23 TDFN SC-70
I Temp. E Temp. I Temp. E Temp. I Temp. E Temp.
24AA02 4A2H 4A02HT 2MNN — AD1 — C5NN —
24LC02B 4L2H 4L2BHT 2QNN 2RNN AD4 AD5 C4NN C6NN
Note: T = Temperature grade (I, E)
NN = Alphanumeric traceability code
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week c ode (w eek of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Mi croch ip pa rt numbe r canno t be ma rked on one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
8-Lead 2x3 TDFN
XXX
YWW
NN
AD4
527
13
Example:
5-Lead SC-70 Example:
XXNN C43F
24AA02H/24LC02BH
DS22105A-page 14 2008 Microchip Technology Inc.
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NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
* ,<1
2008 Microchip Technology Inc. DS22105A-page 15
24AA02H/24LC02BH
! ""#$%& !'
!"#$%&"' ()"&'"!&)&#*&&&#
+%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
'!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
: 8& = =
##44!! = =
&#%%+ =
: >#& . ?1,
##4>#& . -1,
: 9& 1,
,'%@&A =
3&9& 9 =
3&& 9 .3
3& IB = <B
9#4!! =
9#>#& ) - =
#%& DB = B
#%&1&&' EB = B
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
* ,1
24AA02H/24LC02BH
DS22105A-page 16 2008 Microchip Technology Inc.
! ""#$%& !'
3&'!&"&4#*!(!!&4%&&#&
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2008 Microchip Technology Inc. DS22105A-page 17
24AA02H/24LC02BH
() )"* ! (+%+( !
!"#$%&"' ()"&'"!&)&#*&&&#
'!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
- '!#&.0
1,2 1!'!&$& "!**&"&&!
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3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& ?1,
: 8& = =
##44!! <
&#%% =
: >#& . ?1,
##4>#& . -
##49& - -
3&9& 9 ?
3&& 9 .3
3& IB = <B
9#4!! =
9#>#& ) = -
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
* ,<?1
24AA02H/24LC02BH
DS22105A-page 18 2008 Microchip Technology Inc.
," !*-, , !
!"#$%&"' ()"&'"!&)&#*&&&#
'!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
- '!#&.0
1,2 1!'!&$& "!**&"&&!
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3&'!&"&4#*!(!!&4%&&#&
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6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& ?1,
: 8& = =
##44!! <
&#%% =
: >#& . 1,
##4>#& . -1,
: 9& -1,
3&9& 9 ? <
3&& 9 .3
3& B = <B
9#4!! < = -
9#>#& ) =
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2
c
L1 L
φ
* ,1
2008 Microchip Technology Inc. DS22105A-page 19
24AA02H/24LC02BH
. !(""!( !(/
'!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
'!#&.0
1,2 1!'!&$& "!**&"&&!
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6&! 99..
'!9'&! 7 7: ;
7"')%! 7
9#& 1,
:"&!#9#& 1,
: 8& =
##44!! < = -
&#%% =
: >#& . = -
##4>#& . - = <
: 9& = -
3&9& 9 = ?
3&& 9 - = <
3& B = -B
9#4!! < = ?
9#>#& ) =
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
* ,1
24AA02H/24LC02BH
DS22105A-page 20 2008 Microchip Technology Inc.
. !(""( '0
'!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
'!#&.0
1,2 1!'!&$& "!**&"&&!
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7
& ?1,
: 8& < =
##44!! < =
&#%% =
: >#& . <
##4>#& . -
: 9& <
3&9& 9 ?
9#4!! < = ?
9#>#& ) =
D
b
1
23
E1
E
45
ee
c
L
A1
AA2
* ,?1
2008 Microchip Technology Inc. DS22105A-page 21
24AA02H/24LC02BH
3&'!&"&4#*!(!!&4%&&#&
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DS22105A-page 22 2008 Microchip Technology Inc.
1$*-,/22%0.(1
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2008 Microchip Technology Inc. DS22105A-page 23
24AA02H/24LC02BH
1$*-,/22%0.(1
3&'!&"&4#*!(!!&4%&&#&
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24AA02H/24LC02BH
DS22105A-page 24 2008 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision A
Original release of this document.
2008 Microchip Technology Inc. DS22105A-page 25
24AA02H/24LC02BH
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchi p.c om . Thi s web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip con sultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical s upport is a vailable through the web si te
at: http://support.microchip.com
24AA02H/24LC02BH
DS22105A-page 26 2008 Microchip Technology Inc.
READER RESP ONSE
It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-
uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response Total Pages Sent ________
From: Name
Company
Address
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Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS22105A24AA02H/24LC02BH
1. What are the best featu res of this document ?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2008 Microchip Technology Inc. DS22105A-page27
24AA02H/24LC02BH
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24AA02H = 1. 7V, 2 Kbit I2C Serial EEPROM
24AA02HT = 1. 7V, 2 Kbit I2C Serial EEPROM
(Tape and Reel)
24LC02BH = 2.5V, 2 Kbit I2C Serial EEPROM
24LC02BH = 2.5V, 2 Kbit I2C Serial EEPROM
(Tape and Reel)
Temperature
Range: I = -40°C to +85°C
E = -40°C to +125°C
Package: P = 8-Lead Plastic Dual In-Line (300 mil body)
SN = 8-Lead Plastic Small Outline (3.90 mm body)
ST = 8-Lead Plastic Thin Shrink Small Outline
(4.4 mm)
MS = 8-Lead Plastic Micro Small Outline
MNY(1) = 8-Lead Plastic Dual Flat, No Lead
OT = 5-Lead Plastic Small Outline Transistor
(Tape and Reel only)
LT = 5-Lead Plas tic Sm all Outline Transistor
(Tape and Reel only)
Examples:
a) 24AA02H-I/P: Industrial Temperatur e,
1.7V, PDIP package
b) 24AA02H-I/SN: Industrial Temperature,
1.7V, SOIC package
c) 24AA02HT-I/OT: Industrial Temperature,
1.7V, SOT-23 package, tape and reel
d) 24LC02BH-I/P: Industrial Temperature,
2.5V, PDIP package
e) 24LC02BH-E/SN: Extended Tempera-
ture , 2 .5 V, SOIC pac ka g e
f) 24LC02BHT-I/LT: Industrial Tempera-
ture, 2.5V, SC-70 package, tape and reel
Note 1: ’Y’ indicates a Nickel Palladium Gold (NiPdAu) finish.
24AA02H/24LC02BH
DS22105A-page 28 2008 Microchip Technology Inc.
NOTES:
2008 Microchip Technology Inc. DS22105A-page 29
Information contained in this publication regarding device
applications and the like is provided only for your con ve nience
and may be superseded by u pdates. It is y our respo ns ibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTA RT, rfPI C, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Inc orporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Prog ra m ming, IC S P, ICE PI C , M i n di , MiWi, MPASM , MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology In corporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on t he market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contai ned in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code ho pping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22105A-page 30 2008 Microchip Technology Inc.
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