Make sure the next Card you purchase has... BU-64703 SIMPLE SYSTEM RT MARK3 (SSRT MARK3) (R) FEATURES * Complete Integrated Remote Terminal Including: *Dual Low-Power 3.3V or 5.0V Transceivers *Complete RT Protocol Logic * Supports MIL-STD-1553A/B Notice 2, STANAG-3838 RT, and MIL-STD-1760 Stores Management * World's Smallest CQFP SSRT * 80-Pin Ceramic Flat Pack or Gull Wing Package * 3.3V Logic Power DESCRIPTION The BU-64703 Simple System RT Mark3 (SSRT Mark3) MILSTD-1553 terminal provides a complete interface between a simple system and a MIL-STD-1553 bus. The SSRT Mark3 can be powered entirely by 3.3 volts, thus eliminating the need for a 5V power supply. This terminal integrates dual transceiver, protocol logic, and a FIFO memory for received messages in an extremely small, 0.88 inch square 0.130" max height ceramic package. The gull wing package with a "toe-to-toe" maximum dimension of 1.110 inches enables its use in applications where PC board space is at a premium. The SSRT Mark3 provides multi-protocol support of MIL-STD-1553A/B, MIL-STD-1760, McAir, and STANAG-3838. The SSRT Mark3's transceivers are completely monolithic, require only a +3.3V supply (+5.0V available), and consume low power. The internal architecture is identical to that of the original BU-61703/61705 Simple System RT (SSRT). There are versions of the Simple System RT Mark3 available with transceivers trimmed for MIL-STD-1760 compliance, or compatible to McAir standards. The SSRT Mark3 can operate with a choice of clock frequencies at 10, 12, 16, or 20 MHz. * Meets 1553A/McAir Response Time Requirements * Internal FIFO for Burst Mode Capability on Receive Data * 16-bit DMA Interface * Auto Configuration Capability * Comprehensive Built-In Self-Test * Direct Interface to Simple (Processorless) Systems * Available with Full Military Temperature Range and Screening * Selectable Input Clock: 10, 12, 16, or 20 MHz The SSRT Mark3 incorporates a Built-In-Test (BIT). This BIT, which is processed following power turn-on or after receipt of an Initiate SelfTest Mode command, provides a comprehensive test of the SSRT Mark3's encoders, decoders, protocol, transmitter watchdog timer, and protocol section. The SSRT Mark3 also includes an auto-configuration feature. The SSRT Mark3 is ideal for stores and other simple systems that do not require a microprocessor. To streamline the interface to simple systems, the SSRT Mark3 includes an internal 32-word FIFO for received data words. This serves to ensure that only complete, consistent blocks of validated data words are transferred to a system. FOR MORE INFORMATION CONTACT: Technical Support: 1-800-DDC-5757 ext. 7771 Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com (c) 2003 Data Device Corporation Data Device Corporation www.ddc-web.com 2 BU-64703 H-06/11-0 CLOCK FREQUENCY SELECTION RT ADDRESS CONTROL INPUTS TX_INH CLK_SEL0 CLK_SEL1 CLK_IN RT_AD_ERR RT_AD_LAT RTADP RTAD4-RTAD0 BRO_ENA AUTO_CFG MSTCLR TX/RX B TX/RX B TX/RX A TX/RX A DUAL ENCODER DECODER AND RT STATE LOGIC DMA HANDSHAKE AND TRANSFER CONTROL LOGIC DATA BUFFERS L_BRO, T/R, SA4-SA0 WC/MC/CWC4-0 FIGURE 1. SSRT Mark3 BLOCK DIAGRAM TRANSCEIVER B TRANSCEIVER A +Vcc RTFAIL MSG_ERR GBR INCMD RTACTIVE BUSY SSFLAG SRV_RQST ILLEGAL MEMWR MEMOE HS FAIL DTACK DTGRT DTREQ D15-D0 RT MESSAGE STATUS RT WORD INPUTS COMMAND ADDRESS BUS DATA TRANSFER CONTROL DMA HANDSHAKE CONTROL SYSTEM DATA TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont'd) TABLE 1. SSRT Mark3 SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage * Logic +3.3V * Transceivers +3.3V (Note 10) (not during transmit) * Transceiver +3.3V (during transmit) (Note 10) * Transceiver +5.0V * +3.3V Logic Input Range RECEIVER Differential Input Resistance (Notes 1-6) Differential Input Capacitance (Notes 1-6) Threshold Voltage, Transformer Coupled, Measured on Stub Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage (Note 8) * Direct Coupled Across 35 , Measured on Bus * Transformer Coupled Across 70 , Measured on Bus BU-64703XX-XX0 BU-64703X8/3-XX2 (Note 9) Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across 70 ohms Rise/Fall Time BU-64703X8/3 BU-64703X9/4 LOGIC VIH All signals except CLOCK_IN CLOCK_IN VIL All signals except CLOCK_IN CLOCK_IN Schmidt Hysteresis All signals except CLOCK_IN CLOCK_IN IIH, IIL All signals except CLOCK_IN IIH (Vcc=3.6V, VIN=Vcc) IIH (Vcc=3.6V, VIH=2.7V) IIL (Vcc=3.6V, VIH=0.4V) CLOCK_IN IIH IIL VOH (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOH=max) VOL (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOL=max) IOL (Vcc = 3.0V) IOH (Vcc = 3.0V) CI (Input Capacitance) CIO (Bi-directional signal input capacitance) Data Device Corporation www.ddc-web.com MIN TYP MAX -0.3 -0.3 6.0 6.0 V V -0.3 4.5 V -0.3 -0.3 7.0 6.0 V V 2.5 POWER SUPPLY REQUIREMENTS Voltages/Tolerances * +3.3V Logic * +3.3V Transceivers (Note 10) * +5.0V Transceivers Current Drain(Total Hybrid)(Notes 8,14) * BU-64703X8/9-XX0,(1553 & McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X8-XX2, (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle Current Drain(Total Hybrid)(Notes 8,14) * BU-64703X3/4-X00,(1553 & McAir) +5V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * 3.3V Logic * BU-64703X3-X02,(1760) +5V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * 3.3V Logic k 0.200 5 pF 0.860 Vp-p 10 Vpeak 6 7 9 Vp-p 18 20 20 21.5 27 27 10 Vp-p Vp-p mVp-p 250 mVpeak 300 300 nsec nsec -250 100 200 PARAMETER UNITS 150 250 2.1 0.8*Vcc POWER DISSIPATION Total Hybrid (Notes 8, 11 and 14) * BU-64703X8/9-XX0, (1553 & McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X8-XX2, (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X3/4-X00, (1553 & McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X3-X02, (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle Hottest Die * BU-64703X8/9-XX0 (1553 &McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X8-XX2 (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle V V 0.7 0.2*Vcc 0.4 1.0 V V V V -10 -350 -350 10 -33 -33 A A A -10 -10 10 10 A A 2.4 V 0.4 2.2 -2.2 50 50 V mA mA pF pF 3 MIN TYP MAX UNITS 3.00 3.14 4.75 3.3 3.3 5.0 3.60 3.46 5.25 V V V 95 300 500 900 mA mA mA mA 95 315 535 975 mA mA mA mA 100 205 310 520 40 mA mA mA mA mA 100 216 332 565 40 mA mA mA mA mA 0.31 0.69 1.04 1.74 W W W W 0.31 0.71 1.08 1.83 W W W W 0.63 0.85 1.07 1.51 W W W W 0.63 0.86 1.09 1.56 W W W W 0.09 0.47 0.82 1.52 W W W W 0.09 0.49 0.85 1.61 W W W W BU-64703 H-06/11-0 TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont'd) PARAMETER MIN TYP POWER DISSIPATION (CONT'D) * BU-64703X3/4-X00 (1553 &McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X3-X02 (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle CLOCK INPUT Frequency * Nominal Value * Default * Option * Option * Option MAX TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont'd) UNITS 0.25 0.47 0.69 1.13 W W W W 0.25 0.48 0.71 1.18 W W W W 16.0 12.0 10.0 20.0 PARAMETER 1553 MESSAGE TIMING RT-to-RT Response Timeout (Note 12) RT Response Time (mid-parity to mid-sync) (Note 12) Transmitter Watchdog Timeout THERMAL Thermal Resistance (Notes 8, 13) Ceramic Flatpack / Gull Lead Junction-to-Case, Hottest Die (JC) Operating Case Temperature -1XX, -4XX -2XX, -5XX -3XX, -8XX MHz MHz MHz MHz Operating Junction Temperature Storage Temperature Lead Temperature (soldering, 10 sec.) PHYSICAL CHARACTERISTICS Size 80-pin Ceramic Flatpack / Gull Lead * Long Term Tolerance * 1553A Compliance * 1553B Compliance 0.01 0.10 -0.01 -0.10 % % -0.001 -0.01 0.001 0.01 % % * Duty Cycle 40 60 % TYP MAX UNITS 17.5 18.5 19.5 s 7 s s 11 C/W -55 -40 0 +125 +85 +70 C C C -55 -65 150 150 +300 C C C 4 660.5 9 0.88 X 0.88 X 0.13 (22.3 x 22.3 x 3.3) in. (mm) 1.110 (28.194) in. (mm) 0.353 (10) oz (g) Lead Toe-to-Toe Distance 80-pin Gull Wing * Short Term Tolerance, 1 second * 1553A Compliance * 1553B Compliance MIN Weight 80-pin Ceramic Flatpack/Gull Wing Package reference is applicable to all available product options. NOTES: (9) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub con- Notes 1 through 6 are applicable to the Receiver Differential Resistance nection. and Differential Capacitance Specifications: (10) External 10 F tantalum and 0.1 F capacitors to ground should be (1) Specifications include both transmitter and receiver (tied together located as close as possible to +3.3 Vdc input pins. internally). (11) Power dissipation is the input power minus the power delivered to (2) Impedance parameters are specified directly between pins the 1553 fault isolation resistors, the power delivered to the bus ter- TX/RX A(B) and TX/RX A(B) of the SSRT Mark3 hybrid. mination resistors, and the copper losses in the transceiver isolation (3) It is assumed that all power and ground inputs to the hybrid are con- transformer and the bus coupling transformer. An illustration of exter- nected. nal power dissipation for transformer coupled configuration (while (4) The specifications are applicable for both unpowered and powered transmitting) is: 0.14 watts for the active isolation transformer, 0.08 conditions. watts for the active bus coupling transformer, 0.45 watts for each of (5) The specifications assume a 2 volt rms balanced, differential, sinu- the two bus isolation resistors and 0.15 watts for each of the two bus soidal input. The applicable frequency range is 75 kHz to 1 MHz. termination resistors. (6) Minimum resistance and maximum capacitance parameters are (12) Measured from mid-parity crossing of command word to mid-sync guaranteed over the operating range, but are not tested. crossing of RT's status word. (7) Assumes a common mode voltage within the frequency range of dc (13) JC is measured to bottom of ceramic case. to 2 MHz, applied to the pins of the isolation transformer on the stub (14) Current drain and power dissipation specifications are based on a side (either direct or transformer coupled), and referenced to hybrid- small sample size and subject to change. ground. Transformer must be a DDC recommended transformer or other transformer that provides an equivalent minimum CMRR. (8) An "X" in one or more of the product type fields indicates that the Data Device Corporation www.ddc-web.com 4 BU-64703 H-06/11-0 INTRODUCTION The SSRT Mark3 may be operated from a 10, 12, 16, or 20 MHz clock input. For any clock frequency, the decoder samples incoming data on both edges of the clock input. This oversampling, in effect, provides for a sampling rate of twice the input clocks' frequency. Benefits of the higher sampling rate include a wider tolerance for zero-crossing distortion and improved bit error rate performance. GENERAL The BU-64703 Simple System RT Mark3 (SSRT Mark3) is a complete MIL-STD-1553 Remote Terminal (RT) bus interface unit. Contained in this hybrid are a dual transceiver and Manchester II encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) protocol logic. Also included are built-in self-test capability and a parallel subsystem interface. The subsystem interface includes a 12-bit address bus and a 16-bit data bus that operates in a 16-bit DMA handshake transfer configuration. The local bus and associated control signals are optimized for +3.3 volt logic but are +5 volt tolerant. The SSRT Mark3 includes a hardwired RT address input. This includes 5 address lines, an address parity input, and an address parity error output. The RT address can also be latched by means of a latching input signal. The SSRT Mark3 supports command illegalization. Commands may be illegalized by asserting the input signal ILLEGAL active low within approximately 2 s after the mid-parity bit zero-crossing of the received command word. Command words may be illegalized as a function of broadcast, T/R bit, subaddress, word count, and/or mode code. The transceiver front end of the SSRT Mark3 is implemented by means of low-power monolithic technology. The transceiver requires only a single +3.3V voltage source (+5.0V available). The voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. In addition, the monolithic transceivers can provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making the SSRT Mark3 suitable for MIL-STD-1760 applications. To provide compatibility to McAir specs, the SSRT Mark3 is available with an option for transmitters with increased rise and fall times. An internal Built-in-Test (BIT) Word register is updated at the end of each message. The contents of the BIT Word Register are transmitted in response to a Transmit BIT Word Mode Command. The SSRT Mark3 provides a number of real-time output signals. These various signals provide indications of message in progress, valid received message, message error, handshake fail, loop-test fail or transmitter timeout. Besides eliminating the demand for an additional power supply, the use of a +3.3V only transceiver requires the use of a step-up, rather than a step-down, isolation transformer. This provides the advantage of a higher terminal input impedance than is possible for a 15V, 12V or 5V transmitter. As a result, there is a greater margin for the input impedance test, mandated for the 1553 validation test. This allows for longer cable lengths between a system connector and the isolation transformers of an embedded 1553 terminal. The SSRT Mark3 includes standard DMA handshake signals (Request, Grant, and Acknowledge) as well as transfer control outputs (MEMOE and MEMWR). The DMA interface operates in a 16-bit mode, supporting word-wide transfers. The SSRT Mark3's system interface allows the SSRT Mark3 to be interfaced directly to a simple system that doesn't include a microprocessor. This provides a low-cost 1553 interface for A/D and D/A converters, switch closures, actuators, and other discrete I/O signals. The receiver sections of the SSRT Mark3 are fully compliant with MIL-STD-1553B in terms of front-end overvoltage protection, threshold, and bit-error rate. The SSRT Mark3 has an internal FIFO for received data words. This 32-word deep FIFO may be used to allow the SSRT Mark3 to transfer its data words to the local system in burst mode. Burst mode utilizes the FIFO by transferring data to the local bus at a rate of one data word every three clock cycles. Burst mode negotiates only once for use of the subsystem bus. Negotiation is performed only after all 1553 data words have been received and validated. In non-burst mode, the SSRT Mark3 will negotiate for the local bus after every received data word. The data word transfer period is three clock cycles for each received 1553 data word. The SSRT Mark3 implements all MIL-STD-1553 message formats, including all 13 MIL-STD-1553 dual redundant mode codes. Any subset of the possible 1553 commands (broadcast, T/R bit, subaddress, word count/mode code) may be optionally illegalized by means of an external PROM, PLD, or RAM. An extensive amount of message validation is performed for each message received. Each word received is validated for correct sync type and sync encoding, Manchester II encoding, parity, and bit count. All messages are verified to contain a legal, defined command word and correct word count. If the SSRT Mark3 is the receiving RT in an RT-to-RT transfer, it verifies that the T/R bit of the transmit command word is logic "1" and that the transmitting RT responds in time and contains the correct RT address in its Status Word. Data Device Corporation www.ddc-web.com The SSRT Mark3 may also be used in a shared RAM interface configuration. By means of tri-state buffers and a small amount of "glue" logic, the SSRT Mark3 will store Command Words and access Data Words to/from dedicated "mailbox" areas in a shared RAM for each broadcast / T/R bit / subaddress / mode code. 5 BU-64703 H-06/11-0 BU-64703E8 SSRT MARK3 (+3.3V) TRANSFORMER EVALUATION BOARD (SEE FIGURE 2) signals. The address bus L_BRO, T/R, SA4-SA0, and WC/MC/ CWC4-0; along with the data transfer control signals MEMOE and MEMWR are two-state output signals. The BU-64703E8 board is intended to support customers who are interested in electrically connecting and evaluating the performance of the +3.3V SSRT Mark3. The user will be able to quickly perform functional tests and run their system software utilizing this relatively small (2.0" x 2.5") evaluation board. The control signals include the standard DMA handshake signals DTREQ, DTGRT, DTACK, as well as the transfer control outputs MEMOE and MEMWR. HS_FAIL provides an indication to the subsystem of a handshake failure condition. The BU-64703E8 consists of a PC board incorporating a +3.3V SSRT Mark3 (BU-64703G8), necessary decoupling capacitors, and associated isolation transformers. The MIL-STD-1553 outputs have been factory configured for Stub (transformer) coupling. The board supports the signal fan-out of the +3.3V SSRT Mark3 to 96 pins subdivided into (4) dual inline, berg type pin rows. These pins (0.025" square max) and their row placement adhere to standard 0.100" vector board spacing. Data transfers between the subsystem and the SSRT Mark3 are performed by means of a DMA handshake, initiated by the SSRT Mark3. A data read operation is defined to be the transfer of data from the subsystem to the SSRT Mark3. Conversely, a data write operation transfers data from the SSRT Mark3 to the subsystem. Data is transferred as a single 16-bit word. DMA READ OPERATION In response to a transmit command, the SSRT Mark3 needs to read data words from the external subsystem. To initiate a data word read transfer, the SSRT Mark3 asserts the signal DTREQ low. Assuming that the subsystem asserts DTGRT in time, the SSRT Mark3 will then assert the appropriate values of L_BRO (logic "0"), T/R (high), SA4-0, and MC/CWC4-0; MEMWR high, along with DTACK low and MEMOE low to enable data to be read from the subsystem. ADDRESS MAPPING A typical addressing scheme for the SSRT Mark3 12-bit address bus could be as follows: A11: BROADCAST/OWNADDRESS A10: TRANSMIT/RECEIVE A9-A5: SUBADDRESS 4-0 A4-A0: WORD COUNT/MODE CODE 4-0 After the transfer of each Data Word has been completed, the value of the address bus outputs CWC4 through CWC0 is incremented. DMA WRITE OPERATION This method of address mapping provides for a "mailbox" allocation scheme for the storage of data words. The 12 address outputs may be used to map into 4K words of processor address space. The SSRT Mark3's addressing scheme maps messages in terms of broadcast/ownaddress, transmit/receive, subaddress, and word/count mode code. A 32-word message block is allocated for each T/R-subaddress. In response to a receive command, the SSRT Mark3 will need to transfer data to the subsystem. There are two options for doing this, the burst mode and the non-burst mode. In burst mode, all received data words are transferred from the SSRT Mark3 to the subsystem in a contiguous burst, only following the reception of the correct number of valid data words. In the non-burst mode, single data words are written to the external subsystem immediately following the reception of each individual data word. For non-mode code messages, the Data Words to be transmitted or received are accessed from (to) relative locations 0 through 31 within the respective message block. For the MIL-STD-1553B Synchronize with data, Selected transmitter shutdown, Override selected transmitter shutdown, and Transmit vector word mode commands which involve a single data word transfer, the address for the data word is offset from location 0 of the message block for subaddresses 0 and 31 by the value of the mode code field of the received command word. To initiate a DMA write cycle, the SSRT Mark3 asserts DTREQ low. The subsystem must then respond with DTGRT low. Assuming that DTGRT was asserted in time, the SSRT Mark3 will then assert DTACK low. The SSRT Mark3 will then assert the appropriate value of L_BRO, T/R, SA4-0, and MC/CWC4-0, MEMOE high, and MEMWR low. MEMWR will be asserted low for one clock cycle. The subsystem may then use either the falling or rising edge of MEMWR to latch the data. Similar to the DMA read operation, the address outputs CWC4 through CWC0 are incremented after the completion of a DMA write operation. The data words transmitted in response to the Transmit last command or Transmit BIT word mode commands are accessed from a pair of internal registers. HANDSHAKE FAIL DMA INTERFACE Following the assertion of DTREQ low by the SSRT Mark3, the external subsystem has 10 s to respond by asserting DTACK to logic "0". A 16-bit data bus, a 12-bit address bus, and six control signals are provided to facilitate communication with the parallel subsystem. The data bus D15-D0 consists of bi-directional tri-state Data Device Corporation www.ddc-web.com 6 BU-64703 H-06/11-0 Data Device Corporation www.ddc-web.com 7 BU-64703 H-06/11-0 2 X 0.300 [7.62] 0.150 [3.81] 0.100 [2.54] 112 X 0.025 .001 [0.64] 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 P2 31 32 P1 22 21 22 21 20 19 20 19 16 15 16 15 14 13 14 13 12 11 U1 12 11 10 9 10 9 8 7 8 7 6 5 T1 6 5 2.000 [50.80] 1.700 [43.18] 1.600 [40.64] 2 X 11 EQUAL SPACES @ 0.100 [2.54] = 1.100 [27.94] (TOL NON-CUM) 18 17 T2 18 17 4 3 4 3 2 1 2 1 P4 P3 11 9 7 5 3 1 12 10 8 6 4 2 19 20 13 21 22 14 23 24 15 25 26 16 27 28 17 29 30 18 31 32 2X 0.600 [15.24] 2X 15 EQUAL SP @ 0.100 [2.54]= 1.500 [38.10] (TOL-NONCUM) 2.500 [63.50] (MAX) Dimensions are in inches [mm] 0.100 [2.54] 2.300 [58.42] 0.100 [2.54] 2.200 [55.88] FIGURE 2. BU-64703E8 SSRT Mark3 (+3.3V) TRANSFORMER EVALUATION BOARD 24 23 24 23 S/N DC 4X 0.090 [2.30] 0.300 [7.62] (MAX) 4X 0.230 [5.84] 0.062 (1.57) If the SSRT Mark3 asserts DTREQ and the subsystem does not respond with DTGRT in time for the SSRT Mark3 to complete a data word transfer, the HSFAIL output will be asserted low to inform the subsystem of the handshake failure, and bit 12 in the internal Built-In-Test (BIT) word will be set to logic "1". If the handshake failure occurs on a data word read transfer (for a transmit command), the SSRT Mark3 will abort the current message transmission. In the case of a handshake failure on a write transfer (received command) the SSRT Mark3 will set the handshake failure output and BIT word bit, and abort processing the current message. ues presented at the time of a low-to-high transition of RT_AD_ LAT. RT address and RT Address Parity must be presented valid before the mid-parity crossing of the 1553 command and held, at least, until following the first received data word. COMMAND ILLEGALIZATION The SSRT Mark3 includes a provision for command illegalization. If a command is illegalized, the SSRT Mark3 will set the Message error bit and transmit its status word to the Bus Controller. No data words will be transmitted in response to an illegalized transmit command. However, data words associated with an illegalized receive command will be written to the external subsystem (although these transfers may be blocked using external logic). MESSAGE PROCESSING OPERATION Following the receipt and transfer of a valid Command Word, the SSRT Mark3 will attempt to perform one of the following operations: (1) transfer received 1553 data to the subsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status (and possibly the last command word or RT BIT word) on the 1553 bus, and/or (4) set status word conditions. ILLEGAL is sampled approximately 2 s following the mid-parity bit zero crossing of the received command word. A low on ILLEGAL will illegalize a particular command word and cause the SSRT Mark3 to respond with its Message error bit set in its status word. Command illegalization based on broadcast, T/R bit, subaddress, and/or word count/mode code may be implemented by means of an external PROM, PLD, or RAM device, as shown in Figure 3. The SSRT Mark3 responds to all non-broadcast messages to its RT address with a 1553 Status Word. RT ADDRESS RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity (RT_AD_P) should be programmed for a unique RT address and reflect an odd parity sum. The SSRT Mark3 will not respond to any MIL-STD-1553 commands or transfer received data from any non-broadcast messages if an odd parity sum is not presented by RT_AD_4-0 and RT_AD_P. An address parity error will be indicated by a low output on the RT_AD_ERR pin. The input signal RT_AD_LAT operates a transparent latch for RTAD4RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch tracks the value presented on the input pins. If RT_AD_LAT is high, the output of the internal latch becomes latched to the val- The external device may be used to define the legality of specific commands. Any subset of the possible 1553 commands may be illegalized as a function of broadcast, T/R bit, subaddress, word count, and/or mode code. The output of the illegalization device should be tied directly to the SSRT Mark3's ILLEGAL signal input. The maximum access time of the external illegalizing device is 400 ns. If illegalization is not used, ILLEGAL should be hardwired to logic "1". L-BRO A 11 T/R A 10 SA4 A9 SA3 A8 SA2 A7 SA1 A6 SA0 A5 WC/MC/CWC4 A4 WC/MC/CWC3 A3 WC/MC/CWC2 A2 WC/MC/CWC1 A1 WC/MC/CWC0 A0 PROM / RAM / PLD (4Kx1) (400ns max) BU - 64703 "SSRT Mark3" D0 IL L E G A L FIGURE 3. SSRT Mark3 ILLEGALIZATION Data Device Corporation www.ddc-web.com 8 BU-64703 H-06/11-0 BUSY cessfully transferred to the subsystem, a negative pulse will be asserted on the output Good Block Received (GBR). The width of this pulse is two clock cycles. The external subsystem may control the SSRT Mark3's Busy RT status word bit by means of the BUSY input signal. The SSRT Mark3 samples BUSY approximately 2 s following the midparity bit zero crossing of the received Command Word. If BUSY is sampled low for a particular message, the value of the busy bit transmitted in the SSRT Mark3's status word will be logic "1". If BUSY is sampled high for a particular message, the value of the busy bit transmitted in the SSRT Mark3's status word will be logic "0". RT-TO-RT TRANSFER ERRORS For the case where the SSRT Mark3 is the receiving RT of an RT-to-RT transfer, if the transmitting RT does not respond within the specified time period, the SSRT Mark3 will determine that a timeout condition has occurred. The value of the SSRT Mark3's RT-to-RT timeout timer is in the range from 17.5 to 18.5 s, and is specified from the mid-parity bit crossing of the transmit command word to the mid-sync crossing of the transmitting RT's status word. In the case of an RT-to-RT timeout, the SSRT Mark3 will not respond and the RT-to-RT NO TRANSFER TIMEOUT bit (bit 2) of the SSRT Mark3's BIT Word will be set to logic "1". If the RT responds to a transmit command with a busy bit of logic "1", the status word will be transmitted, but no data words will be transmitted by the SSRT Mark3. If the SSRT Mark3 responds to a receive command with a busy bit of logic "1", data words will be transferred to the external subsystem (although these may be blocked by means of external logic). Also, if the SSRT Mark3 is the receiving RT for an RT-to-RT transfer, and the T/R bit of the second command word is logic "0", or the RT address field for the transmit command is the same as for the receive command, or the subaddress for the transmit command is 00000 or 11111, the SSRT Mark3 will not respond, and will set the RT-to-RT SECOND COMMAND ERROR bit (bit 1) of the RT BIT word to logic "1". Similar to ILLEGAL, it is possible to cause the SSRT Mark3 to respond with Busy for specific command words (only), by means of an external PROM, RAM, or PLD device. TRANSMIT COMMAND (RT-TO-BC TRANSFER) If the SSRT Mark3 receives a valid Transmit command word that the subsystem determines is legal (input signal ILLEGAL is high) and the subsystem is not BUSY (input signal BUSY is high), the SSRT Mark3 will initiate a transmit data response following transmission of its status word. This entails a handshake/read cycle for each data word transmitted, with the number of data words to be transmitted specified by the word count field of the transmit command word. RT STATUS, ERROR HANDLING, AND MESSAGE TIMING SIGNALS Message transfers and transfer errors are indicated by means of the INCMD, HS_FAIL, MSG_ERR, and RTFAIL error indication outputs. Additional error detection and indication mechanisms include updating of the internal command, RT status and BIT word registers. If ILLEGAL is sampled low, the Message Error bit will be set in the SSRT Mark3's status word. No data words will be transmitted following transmission of the status word to an illegalized transmit command. A low on the BUSY input will set the busy bit in the Status Word; in this instance, only the status word will be transmitted, with no data words. The SSRT Mark3 provides a number of timing signals during the processing of 1553 messages. INCMD is asserted low when a new command is received. At the end of a message (either valid or invalid), INCMD transitions from low to high. RECEIVE COMMAND (BC-TO-RT TRANSFER) As discussed above, HS_FAIL will be asserted low if the subsystem fails to respond to DTREQ within the maximum amount of time (10 s). In non-burst mode, a DMA handshake will be initiated for each data word received from the 1553 data bus. If successful, the respective handshake will be followed by a corresponding write cycle. A handshake timeout will not terminate transfer attempts for the remaining data words, error flagging or Status Word transmission. After the reception of a valid non-mode code receive Command Word followed by the correct number of valid Data Words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the Good Block Received (GBR) output. The width of this pulse is two clock cycles. Following the last data word transfer for a valid non-mode code receive message (for either non-burst mode or burst mode), GBR will be asserted low for two clock cycles. MSG_ERR is asserted as a low output level following any detected error in a received message, except for an error in the command word. If an error is detected in a received command word, the rest of the message will be ignored. In burst mode, a DMA handshake will not be initiated until after all data words have been received over the 1553 data bus and stored into the SSRT Mark3's internal FIFO. After the handshake has been negotiated, the SSRT Mark3 will burst the contents of the FIFO to the local bus (D0-D15). After the reception of a valid non-mode code receive command word followed by the correct number of valid data words and assuming that all words are suc- Data Device Corporation www.ddc-web.com If MSG_ERR and/or HS_FAIL have been asserted (low), they will be cleared to logic "1" following receipt of a subsequent valid command word. 9 BU-64703 H-06/11-0 TABLE 2. AUTO-CONFIGURATION PARAMETERS BIT FUNCTION DESCRIPTION 5 RT GOES ONLINE IF SELF-TEST FAILS If logic "0", the RT will become enabled only if the self-test passes. If auto-config is not used, or if this bit is logic "1", or if the power-up self-test passes, then the RT will go online following self-test. 4 RTFAIL-to-TERMINAL If the loop test fails for a particular message, the Terminal flag bit will be set in the SSRT Mark3's status response for the subsequent non-broadcast message. FLAG AUTO-WRAP 3 MIL-STD-1553A/B (-B is logic "1", or the default). In MIL-STD-1553B mode, subaddress 31 is a mode code subaddress, and mode codes are implemented in full accordance with MIL-STD-1553B. In MILSTD-1553A mode, subaddress 31 is a non-mode code subaddress, and no data words are transmitted or anticipated to be received for mode code messages. 2 SUBADDRESS 30 WRAPAROUND Subaddress 30 wraparound is enabled. That is, the data words for a receive message to subaddress 30 are stored in the internal FIFO, and not transferred to the external system. For a subsequent transmit message to subaddress 30, the transmitted data words are read from the internal FIFO, rather than from the external system. 1 BURST MODE Enables burst mode (using the internal FIFO) for received data words. In burst mode, for a receive message, all data words are transferred to the external system in a contiguous burst following reception of the last data word. 0 POWER-UP SELFTEST ENABLE If enabled, the SSRT Mark3 will perform self-test following the rising edge of MSTCLR. LOOPBACK TEST STATUS WORD The SSRT Mark3 performs a loopback self-test at the end of each non-broadcast message processed. The loopback test consists of the following verifications: (1) The received version of every transmitted word is verified for validity (encoding, bit count, parity) and correct sync type; and (2) The received version of the last transmitted word is verified by means of a bit-by-bit comparison to the transmitted version of this word. If there is a transmitter timeout (660.5 s) and/or if the loopback test fails for one or more transmitted words, the Terminal flag status word bit will be set in response to the next non-broadcast message. The Broadcast Command Received bit is formulated internally by the SSRT Mark3. The Message Error Status bit will be set if the current command is a Transmit Status Word or Transmit Last Command mode command if there was an error in the data portion of the previous receive message. Message Error will also be set if ILLEGAL has been sampled low by the SSRT Mark3 for the current message. ILLEGAL, SRV_RQST, BUSY, and SSFLAG (Subsystem Flag) will be sampled from their respective Status input pins approximately 2 s following the mid-parity bit zero crossing of the received Command Word. This time is 400 ns maximum following after the L_BRO, T/R, SA4-0, and WC/MC/ CWC4-0 outputs have been presented valid. Note that the setting of the Terminal flag status bit following a loop test failure may be disabled by means of the Auto-Config feature; i.e., by setting Auto-Config bit 4 to logic "0". PROTOCOL SELF-TEST The SSRT Mark3 includes a comprehensive, autonomous offline self-test of its internal protocol logic. The test includes a comprehensive test of all registers, Manchester encoder and Data Device Corporation www.ddc-web.com 10 BU-64703 H-06/11-0 TABLE 3. CLOCK FREQUENCY SELECTION CLK_SEL_1 CLK_SEL_0 CLOCK FREQUENCY 0 0 10 MHz 0 1 20 MHz 1 0 12 MHz 1 1 16 MHz Note that the default condition for each configuration parameter is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default). decoders, transmitter failsafe timer, protocol logic, and the internal FIFO. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT Mark3 is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus. If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 by means of a DMA read data transfer. The transfer occurs during the time that the RTACTIVE and DTACK outputs are logic "0", following MSTCLR transitioning from logic "0" to logic "1" and a successful DT_REQ-to-DTGRT handshake. Unless disabled by means of the SSRT Mark3's Auto-Config feature, the protocol self-test will be performed following the SSRT Mark3's power turn-on (i.e., when MSTCLR is released high). If the Auto-Config feature is used and Auto-Config bit 5 is set to logic "0", then a failure of the protocol self-test following power turn-on will result in the SSRT Mark3 not going online. If bit 5 is set to logic "0" and the protocol self-test passes following power turn-on, the SSRT Mark3 will go online. Note that if DTGRT is hardwired to logic "0", the handshake process is not necessary (i.e., DTACK and RTACTIVE will both be asserted to logic "0" one clock cycle following DT_REQ). Each of the configuration parameters is enabled if the SSRT Mark3 reads a value of logic "1" for the respective data bit. The auto-configuration parameters are defined in TABLE 2. The protocol self-test will also be performed following receipt of an Initiate self-test mode command from the 1553 bus. If an Initiate self-test mode command is received by the SSRT Mark3, and Auto-Config bit 5 is set to logic "0", then a failure of the protocol self-test following will result in the SSRT Mark3 going offline. The timing signals pertaining to Auto-Configuration mode are illustrated in Figure 13. CLOCK INPUT The SSRT Mark3 may be operated from one of four clock frequencies: 10, 12, 16, or 20 MHz. The selected clock frequency must be designated by means of the input signals CLK_SEL_1 and CLK_ SEL_0, as shown in TABLE 3. If the protocol self-test fails: (1) the Terminal Flag bit will be set to logic "1" in the SSRT Mark3 status word; (2) bit 8 in the SSRT Mark3's BIT word, BIT Test Fail, will be set to logic "1"; (3) the SSRT Mark3's RTFAIL output will be asserted to logic "0". AUTO-CONFIGURATION The SSRT Mark3 includes an auto-configuration feature, which allows various optional features to be enabled or disabled. Autoconfiguration may be enabled or disabled by means of the input signal AUTO_CFG. If AUTO_CFG is connected to logic "1", then the auto-configure option is disabled, and the six configuration parameters revert to their default values. Data Device Corporation www.ddc-web.com 11 BU-64703 H-06/11-0 TABLE FOR FIGURE 4. RT RECEIVE COMMAND TIMING (BURST MODE) REF t1 t2 t3 t4 Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid MIN TYP MAX UNITS ALL 1.5 s ALL 2 s ALL 1.5 s 400 ALL ns t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ALL 500 ns t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t7 Mid-parity crossing of first data word to WC/CWC valid data of 1Fh ALL 1 s t8 Duration of WC/CWC data value of 1Fh ALL 200 ns t9 RT Response time. ALL t10 t11 CWC transition to next word following mid-parity of subsequent received data words. Mid-parity crossing of last data word to DTREQ falling edge (requesting data word burst write transfer) ALL t13 CWC valid following falling edge of DTREQ ALL 20 16 12 10 GBR pulse width (see Note 1) t15 Mid-parity crossing of status word to INCMD rising 7 1 ALL Mid-Sync crossing of Status response to RT_FAIL rising t14 6.5 4 ALL t12 (1) RESPONSE TIME CLOCK FREQUENCY DESCRIPTION 4.5 4 s 5.25 1.5 s s 30 MHz MHz MHz MHz s ns 100 125 167 200 ns ns ns ns 3 s ALL If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR. MID-PARITY 1553 BUS MID-PARITY MID-PARITY MID-PARITY MID-SYNC t9 RX COMMAND DATA #1 STATUS DATA #2 t1 L-BRO, T/R, SA4-SA0 t10 t7 WC/MC/CWC WC / MC PREVIOUS MSG CWC = 0 t8 t4 ILLEGAL, SRV_RQST SSFLAG, BUSY 1F CWC = 1 cwc t13 WC / MC VALID t5 INCMD t6 t15 NOTE 1 t2 t14 GBR t11 DTREQ DTGRT DTACK BURST DATA WRITE TRANSFER D15-D0 (Refer to FIGURE 10) MEMWR MEMOE t12 RT_FAIL t3 MSG_ERR HS_FAIL RT RECEIVE COMMAND (BURST MODE) NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR. FIGURE 4. RT RECEIVE COMMAND (BURST MODE) TIMING Data Device Corporation www.ddc-web.com 12 BU-64703 H-06/11-0 TABLE FOR FIGURE 5. RT RECEIVE COMMAND TIMING (NON-BURST MODE) REF RESPONSE TIME CLOCK FREQUENCY DESCRIPTION MIN TYP MAX UNITS Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ALL 1.5 s ALL 2 s ALL 1.5 s t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL t5 RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL 500 ns t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge of INCMD ALL 300 ns t7 Mid-parity crossing to WC/CWC value of 1Fh t1 t2 t3 t8 Mid-parity crossing of first data word to DTREQ falling edge t9 WC/CWC data value of 1Fh held t10 CWC valid following falling edge of DTREQ t11 RT Response time. t12 t13 GBR pulse width t15 CWC transition to WC prior to Mid-Sync crossing of Status response. ns ALL 1 s 20 MHz 16 MHz 12 MHz 10 MHz 20 MHz 16 MHz 12 MHz 10 MHz ALL 1.2 1.25 1.33 1.4 200 250 333 400 30 s s s s ns ns ns ns ns 7 s Delay from following mid-parity of last received data word to GBR low. (see Notes 1, 2) Mid-parity crossing of all data words, except first data word, to DTREQ falling edge t14 400 ALL 4 ALL 4 ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz 6.5 s 1 s 100 125 167 200 75 94 125 150 ns ns ns ns ns ns ns ns t16 Mid-Sync crossing of status response to RT_FAIL rising ALL 1.5 s t17 Mid-parity crossing of status word to INCMD rising ALL 3.0 s (1) Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low will increase by the amount of the DTGRT (low) - to - DTGRT (low) delay. (2) The transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter. MID-PARITY 1553 BUS RX COMMAND MID-PARITY DATA #1 MID-PARITY MID-PARITY MID-SYNC t11 DATA #2 STATUS t1 L-BRO, T/R, SA4-SA0 t15 t7 WC/MC/CWC WC / MC PREVIOUS MSG CWC = 0 CWC = 1 WC / MC t9 t4 ILLEGAL, SRV_RQST SSFLAG, BUSY 1F VALID t6 t5 INCMD t17 t10 t2 GBR t12 t8 t14 t13 DTREQ DTGRT DTACK SINGLE WORD WRITE SINGLE WORD WRITE D15-D0 DATA WORD #1 DATA WORD #2 MEMWR (Refer to FIGURE 11) MEMOE RT_FAIL t16 t3 MSG_ERR HS_FAIL FIGURE 5. RT RECEIVE COMMAND (NON-BURST MODE) TIMING RT RECEIVE COMMAND (NON-BURST MODE) Data Device Corporation www.ddc-web.com 13 BU-64703 H-06/11-0 TABLE FOR FIGURE 6. RT TRANSMIT COMMAND TIMING REF DESCRIPTION TYP MAX ALL 4 6.5 7 Mid-parity crossing of received command word delay to L-BRO, T/R Bit, SA4-SA0, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R Bit, and CWC/MC valid t2 t3 t4 t5 UNITS s ALL 1.5 s ALL 2 s ALL 1.5 s 400 ALL ns t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ALL 500 ns t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh ALL 20 16 12 10 t9 Mid-Sync crossing of status word to DTREQ falling edge t10 Mid-Sync crossing of Status response to RT_FAIL rising (see Note 1) Duration of WC/CWC value of 1Fh t12 CWC valid following falling edge of DTREQ MHz MHz MHz MHz ALL 20 16 12 10 t11 MHz MHz MHz MHz 6.5 s 6.75 6.81 6.92 7 s s s s 1.5 s 200 250 333 400 ns ns ns ns 30 ALL t13 Mid-Sync crossing of received data word to DTREQ falling edge t14 Mid-Sync crossing of last received data word for CWC to transition to WC t15 Mid-Parity crossing of status word to INCMD rising (1) MIN RT Response time. t1 VALUE CLOCK FREQUENCY 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz ALL ns 1.75 1.81 1.92 2 1.55 1.56 1.59 1.6 s s s s s s s s 3 s Assuming that RTFAIL was previously low. MID-PARITY 1553 BUS MID-SYNC t1 TX COMMAND MID-SYNC STATUS MID-SYNC DATA #1 MID-PARITY DATA #2 t2 L-BRO, T/R, SA4-SA0 t8 WC/MC/CWC ILLEGAL, SRV_RQST SSFLAG, BUSY CWC = 0 t14 cwc = 1 WC t11 t5 VALID t7 t6 INCMD 1F WC PREVIOUS MSG t15 t12 t3 GBR DTREQ t13 t9 DTGRT DTACK D15-D0 MEMWR MEMOE SINGLE WORD READ SINGLE WORD READ DATA WORD #1 DATA WORD #2 (Refer to FIGURE 12) t10 RT_FAIL MSG_ERR t4 HS_FAIL FIGURE 6. RT TRANSMIT COMMAND TIMING Data Device Corporation www.ddc-web.com RT TRANSMIT COMMAND 14 BU-64703 H-06/11-0 TABLE FOR FIGURE 7. RT-RT TRANSMIT COMMAND TIMING REF t1 t2 t3 t4 t5 DESCRIPTION VALUE CLOCK FREQUENCY MIN TYP MAX ALL 17.5 18.5 19.5 RT - RT response timeout for transmitting RT. Mid-parity crossing of received command word delay to L-BRO, T/R Bit, SA4-SA0, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-Parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid UNITS s ALL 1.5 s ALL 2 s ALL 1.5 s 400 ALL ns t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ALL 500 ns t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh ALL t9 Mid-Sync crossing of status word to DTREQ falling edge t10 Mid-Sync crossing of Status response to RT_FAIL rising 20 16 12 10 ALL 20 16 12 10 t11 Duration of WC/CWC value of 1Fh t12 CWC valid following falling edge of DTREQ Mid-Sync crossing of received data word to DTREQ falling edge t14 Mid-Sync crossing of last received data word for CWC to transition to WC t15 Mid-Parity crossing of status word to INCMD rising 6.75 6.81 6.92 7 s s s s 1.5 s 200 250 333 400 ns ns ns ns 30 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz ALL MID-SYNC MID-PARITY RX COMMAND MHz MHz MHz MHz s ALL t13 1553 BUS MHz MHz MHz MHz 6.5 MID-SYNC MID-SYNC ns 1.75 1.81 1.92 2 1.55 1.56 1.59 1.6 s s s s s s s s 3 s MID-PARITY t1 TX COMMAND DATA #1 STATUS DATA #2 STATUS t2 L-BRO, T/R, SA4-SA0 t8 WC/MC/CWC ILLEGAL, SRV_RQST SSFLAG, BUSY CWC = 0 t14 cwc = 1 WC t11 t5 VALID t7 t6 INCMD 1F WC PREVIOUS MSG t15 t12 t3 GBR DTREQ t13 t9 DTGRT DTACK D15-D0 MEMWR SINGLE WORD READ SINGLE WORD READ MEMOE DATA WORD #1 DATA WORD #2 (Refer to FIGURE 12) t10 RT_FAIL MSG_ERR t4 HS_FAIL FIGURE 7. RT - RT TRANSMIT TIMING RT - RT TRANSMIT COMMAND Data Device Corporation www.ddc-web.com 15 BU-64703 H-06/11-0 TABLE FOR FIGURE 8. RT-RT RECEIVE COMMAND TIMING (BURST MODE) REF t1 t2 t3 t4 Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid MIN TYP MAX UNITS ALL 1.5 s ALL 2 s ALL 1.5 s 400 ALL ns t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ALL 500 ns t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t7 RT - RT response timeout for transmitting RT. ALL 17.5 t8 Mid-parity crossing of first data word to WC/CWC valid data of 1Fh ALL 1 s t9 Duration of WC/CWC data value of 1Fh ALL 200 ns t10 RT Response time. ALL t11 t12 (1) RESPONSE TIME CLOCK FREQUENCY DESCRIPTION CWC transition to next word following mid-parity of subsequent received data words. Mid-parity crossing of last data word to DTREQ falling edge (requesting data word burst write transfer) ALL t14 CWC valid following falling edge of DTREQ ALL 20 16 12 10 GBR pulse width (see Note 1) t16 Mid-parity crossing of status word to INCMD rising 7 1 ALL Mid-Sync crossing of Status response to RT_FAIL rising 19.5 6.5 4 ALL t13 t15 18.5 5.25 1.5 ALL s s 30 MHz MHz MHz MHz s s 4.5 4 s ns 100 125 167 200 ns ns ns ns 3 s If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR. MID-SYNC MID-PARITY MID-PARITY MID-PARITY RX COMMAND TX COMMAND STATUS DATA #1 MID-SYNC MID-PARITY t7 1553 BUS DATA #2 t10 MID-PARITY STATUS t1 L-BRO, T/R, SA4-SA0 WC/MC/CWC t11 t8 1F WC / MC PREVIOUS MSG t9 t4 ILLEGAL, SRV_RQST SSFLAG, BUSY CWC = 0 CWC = 1 cwc t14 WC / MC VALID t5 INCMD t6 t16 NOTE 1 t2 t15 GBR t12 DTREQ DTGRT DTACK BURST DATA WRITE TRANSFER D15-D0 MEMWR (Refer to FIGURE 10) MEMOE t13 RT_FAIL t3 MSG_ERR HS_FAIL RT - RT RECEIVE COMMAND (BURST MODE) NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR. FIGURE 8. RT - RT RECEIVE (BURST-MODE) TIMING Data Device Corporation www.ddc-web.com 16 BU-64703 H-06/11-0 TABLE FOR FIGURE 9. RT-RT RECEIVE COMMAND TIMING (NON-BURST MODE) REF t1 t2 t3 t4 t5 RESPONSE TIME CLOCK FREQUENCY DESCRIPTION Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising MIN UNITS 1.5 s ALL 2 s ALL 1.5 s ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL ALL 500 ns ALL 300 ns ALL 17.5 400 t7 t8 Mid-parity crossing to WC/CWC value of 1Fh t9 Mid-parity crossing of first data word to DTREQ falling edge t10 WC/CWC data value of 1Fh held t11 CWC valid following falling edge of DTREQ ALL t12 RT Response time. ALL 4 t13 Delay from following mid-parity of last received data word to GBR low. (see Notes 1, 2) Mid-parity crossing of all data words, except first data word, to DTREQ falling edge ALL 4 t14 MAX ALL ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge of INCMD RT - RT response timeout for transmitting RT. t6 TYP 18.5 6.5 s s s s s s ns ns ns ns 30 ns 7 s s ALL 20 16 12 10 20 16 12 10 19.5 1 1.2 1.25 1.33 1.4 200 250 333 400 ALL 20 MHz 16 MHz 12 MHz 10 MHz 20 MHz 16 MHz 12 MHz 10 MHz ns MHz MHz MHz MHz MHz MHz MHz MHz 1 s 100 125 167 200 75 94 125 150 ns ns ns ns ns ns ns ns t15 GBR pulse width t16 CWC transition to WC prior to Mid-Sync crossing of Status response. t17 Mid-Sync crossing of status response to RT_FAIL rising ALL 1.5 s t18 Mid-parity crossing of status word to INCMD rising ALL 3.0 s (1) Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low will increase by the amount of the DTGRT (low) - to - DTGRT (low) delay. (2) The transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter. MID-SYNC MID-PARITY MID-PARITY MID-PARITY MID-SYNC MID-PARITY t7 1553 BUS RX COMMAND TX COMMAND STATUS DATA #1 MID-PARITY t12 DATA #2 STATUS t1 L-BRO, T/R, SA4-SA0 WC/MC/CWC t16 t8 WC / MC PREVIOUS MSG ILLEGAL, SRV_RQST SSFLAG, BUSY 1F CWC = 0 CWC = 1 WC / MC t10 t4 VALID t6 t5 INCMD t18 t11 t2 t13 t15 GBR t9 t14 DTREQ DTGRT DTACK SINGLE WORD WRITE SINGLE WORD WRITE D15-D0 DATA WORD #1 DATA WORD #2 MEMWR (Refer to FIGURE 11) MEMOE RT_FAIL t17 t3 MSG_ERR HS_FAIL FIGURE 9. RT - RT RECEIVE (NON-BURST-MODE) TIMING RT - RT RECEIVE COMMAND (NON-BURST MODE) Data Device Corporation www.ddc-web.com 17 BU-64703 H-06/11-0 TABLE FOR FIGURE 10. SSRT Mark3 DMA WRITE (BURST MODE) TIMING REF CLOCK FREQUENCY DESCRIPTION t1 CLOCK IN rising to DTREQ low t2 DTREQ falling to DTGRT low t3 CWC setup time prior to MEMWR falling for first word of burst transfer (see Note 1) t4 DTGRT low setup prior to CLOCK IN rising edge t5 DTGRT falling to DTACK low t6 CLOCK IN rising to DTACK low t7 Data output valid following CLOCK IN t8 DTGRT hold time following DTACK falling t9 DTACK low pulse width (based on a two data word transfer) (see Note 2) t10 Data output setup time prior to MEMWR low t11 CLOCK IN rising to MEMWR low t12 MEMWR low pulse width t13 CLOCK IN rising to MEMWR high t14 Data output and CWC hold time following MEMWR high t15 Data output hold time following CLOCK IN rising t16 CWC (all but first data word) setup time prior to MEMWR low t17 CLOCK IN rising to DTREQ and DTACK high t18 Data output signal Tri-State following CLOCK IN rising t19 CLOCK IN rising to GBR falling edge t20 GBR low pulse width t21 INCMD rising following CLOCK IN rising (see Note 3) VALUE @3.3 VOLTS MIN TYP MAX UNITS ALL 40 ns ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 10 105 118 138 155 40 s ns ns ns ns ns ns ns ns ns ns ALL 40 ns ALL 20 MHz 16 MHz 12 MHz 10 MHz 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 30 60 85 127 160 15 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ALL 40 ns ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 40 ns ns ns ns ns ns 290 365 490 590 10 22 43 60 300 375 500 600 40 52.5 73.3 90 50 62.5 83.3 100 40 40 10 23 43 60 15 10 23 43 60 90 115 157 190 100 125 167 200 40 (1) Assumes DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of the DTREQ (low) - to - DTGRT (low) delay. (2) DTACK pulse width is 3 clock cycles per data word transfer. (3) Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising edge of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock cycles: 9.6 s at 10 MHz, 8 s at 12 MHz, 6.0 s at 16 MHz, or 4.8 s at 20 MHz. Data Device Corporation www.ddc-web.com 18 BU-64703 H-06/11-0 CLOCK IN t1 t2 DTREQ DTGRT t17 t4 t8 t6 t9 DTACK t5 t11 MEMWR t12 t13 t11 t12 t13 MEMOE L-BRO, T/R, SA4-SA0 VALID t3 t7 t15 WC/MC/CWC CWC = 0 CWC = 1 t14 t7 t16 DATA VALID D15-D0 WC t14 DATA VALID t10 t10 t18 t21 t19 t20 GBR 1 INCMD DMA WRITE - BURST MODE (SHOWN FOR TWO DATA WORDS) 1 INCMD rising edge is shown for the case of a RX Broadcast command message. For the non-Broadcast case, INCMD rising edge is after the Mid-Parity crossing of the RT STATUS response. FIGURE 10. DMA WRITE TRANSFER (BURST-MODE) TIMING Data Device Corporation www.ddc-web.com 19 BU-64703 H-06/11-0 TABLE FOR FIGURE 11. SSRT Mark3 DMA WRITE TIMING (NON-BURST) REF VALUE @3.3 VOLTS CLOCK FREQUENCY DESCRIPTION MIN TYP MAX UNITS t1 CLOCK IN rising to DTREQ low ALL 40 ns t2 DTREQ (low) - to - DTGRT (low) delay time ALL 10 s 105 118 138 155 40 ns ns ns ns ns ns ns ns ns ns ALL 40 ns ALL 20 MHz 16 MHz 12 MHz 10 MHz 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t3 CWC setup time prior to MEMWR falling (see Note) t4 DTGRT low setup prior to CLOCK IN rising t5 DTGRT falling to DTACK low t6 CLOCK IN rising to DTACK low t7 Data output valid following CLOCK IN rising t8 t9 DTGRT hold time following DTACK falling DTACK low pulse width t10 Data output setup time prior to MEMWR low t11 CLOCK IN rising to MEMWR low t12 MEMWR low pulse width t13 CLOCK IN rising to MEMWR high 110 148 210 260 15 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL t14 Data output hold time following MEMWR high t15 CLOCK IN rising to DTREQ and DTACK high t16 Data output hold time following CLOCK IN rising ALL t17 Data output signal Tri-State following CLOCK IN rising ALL 200 250 333 400 60 85 127 160 40 50 62.5 83.3 100 40 52.5 73.3 90 40 10 23 43 60 40 15 ns 40 ns (1) Assumes that DTGRT is low at the time DTREQ is asserted low. If not, these values can increase by the delay time from DTREQ (low) - to DTGRT (low). CLOCK IN t1 t2 DTREQ t15 t4 DTGRT t8 t6 t9 DTACK t5 t11 t12 MEMWR t13 MEMOE L-BRO, T/R, SA4-SA0 VALID t16 t3 WC/MC/CWC t17 CWC = 0 t14 t7 DATA D15-D0 VALID t10 NON-BURST DMA WRITE NOTE: With the DTGRT pin tied to GND, the time from DTREQ to DTACK is 1 clock cycle. FIGURE 11. DMA WRITE TRANSFER (NON-BURST-MODE) TIMING Data Device Corporation www.ddc-web.com 20 BU-64703 H-06/11-0 TABLE FOR FIGURE 12. SSRT Mark3 DMA READ TIMING REF MIN TYP MAX UNITS t1 CLOCK IN rising to DTREQ low ALL 40 ns t2 DTREQ (low) - to - DTGRT delay time ALL 10 s 20 16 12 10 t3 CWC setup time prior to MEMOE falling t4 DTGRT low setup prior to CLOCK IN rising DTGRT falling to DTACK low t6 CLOCK IN rising to DTACK low t7 DTGRT hold time following DTACK falling DTACK low pulse width t9 CLOCK IN rising to MEMOE low ns ns ns ns MHz MHz MHz MHz ALL ALL 20 16 12 10 t8 60 85 127 160 MHz MHz MHz MHz ALL 20 16 12 10 t5 t10 (1) VALUE @3.3 VOLTS CLOCK FREQUENCY DESCRIPTION MEMOE low pulse width Time for input data to become valid following falling edge of MEMOE t12 Data input hold time following CLOCK IN rising (see Note) ALL t13 CLOCK IN rising to DTREQ, DTACK, and MEMOE high ALL ns ns ns ns 40 ns 30 ns ns ns ns ns 40 ns 70 95 136 170 ns ns ns ns ns ns ns ns 150 188 250 300 MHz MHz MHz MHz MHz MHz MHz MHz t11 ns 200 250 333 400 MHz MHz MHz MHz ALL 20 16 12 10 20 16 12 10 10 105 118 138 155 30 ns 40 ns The SSRT Mark3's data sampling time occurs one clock cycle prior to the rising edge of MEMOE. CLOCK IN t1 t13 t2 DTREQ t4 DTGRT DTACK t7 t6 t8 t5 MEMWR t9 t10 MEMOE L-BRO, T/R, SA4-SA0 WC/CWC VALID t3 CWC = 0 t12 t11 DATA VALID D15-D0 DMA SINGLE WORD READ FIGURE 12. DMA READ TRANSFER TIMING Data Device Corporation www.ddc-web.com 21 BU-64703 H-06/11-0 TABLE FOR FIGURE 13. AUTO-CONFIGURATION - DMA READ TIMING REF t1 MSTCLR high delay to DTREQ low 20 16 12 10 MHz MHz MHz MHz MIN TYP MAX 35 47.5 68.3 85 50 62.5 83.3 100 65 77.5 98.3 115 UNITS ns ns ns ns t2 CLOCK IN rising to DTREQ low ALL 40 ns t3 DTREQ (low) - to - DTGRT delay time ALL 10 s t4 DTGRT low setup prior to CLOCK IN rising ALL 20 16 12 10 MHz MHz MHz MHz 10 ns 105 118 138 155 ns ns ns ns t5 DTGRT falling to DTACK low t6 CLOCK IN rising to DTACK low ALL 40 ns t7 DTGRT hold time following DTACK falling ALL 30 ns 215 265 348 415 120 157 220 270 ns ns ns ns ns ns ns ns t8 DTACK low pulse width t9 Time for input data to become valid following falling edge of DTACK t10 Data input hold time following sampling time (see Note 1) t11 CLOCK IN rising to DTREQ, DTACK, and MEMOE high t12 RTACTIVE high delayed from DTACK high (see Note 2) t13 CLOCK IN rising to RTACTIVE high (1) (2) VALUE @3.3 VOLTS CLOCK FREQUENCY DESCRIPTION 20 16 12 10 20 16 12 10 200 250 333 400 185 235 318 385 MHz MHz MHz MHz MHz MHz MHz MHz 30 ALL ns 40 ALL 20 16 12 10 MHz MHz MHz MHz ns ms ms ms ms 1.6 2.0 2.7 3.2 40 ALL ns During Auto-Configuration the SSRT Mark3 samples data three clock cycles following the falling edge of DTACK. If self-test mode is not enabled, then RTACTIVE will go active high 1 clock cycle following the rising edge of DTACK. If self-test is enabled then RTACTIVE will be delayed from going active high in accordance with `t12'. CLOCK IN MSTCLR t2 t11 t3 DTREQ DTGRT DTACK t1 t4 t7 t6 t8 t13 t12 t5 RTACTIVE note1 MEMWR MEMOE t9 D15-D0 t10 DATA VALID AUTO-CONFIGURATION - DMA SINGLE WORD READ Note1: RTACTIVE asserted high 1 clock following DTACK high assuming self-test is not enabled. When self-test is enabled RTACTIVE is delayed in the amount of 't12'. See the table reference for details. FIGURE 13. AUTO-CONFIGURATION - DMA READ TRANSFER TIMING Data Device Corporation www.ddc-web.com 22 BU-64703 H-06/11-0 CLOCK IN t1 SIGNAL IN t2 SIGNAL OUT HIGH TO LOW t3 SIGNAL OUT LOW TO HIGH CLOCK EDGE TO SIGNAL IN / OUT TIMING FIGURE 14. CLOCK EDGE SIGNAL TIMING TABLE FOR FIGURE 14. SSRT Mark3 CLOCK EDGE TO SIGNAL IN / OUT VALID TIMING REF (1) VALUE @3.3 VOLTS DESCRIPTION MIN TYP MAX UNITS t1 SIGNAL INPUT setup time prior to CLOCK IN rising edge t2 CLOCK IN rising edge to SIGNAL OUTPUT driven low (see Note) 40 ns t3 CLOCK IN rising edge to SIGNAL OUTPUT driven high (see Note) 40 ns 15 ns Assumes a 50 pf external load. For loading above 50pf, the validity of output signals is delayed by an additional 0.14 ns/pf typ, 0.28ns/pf max. Data Device Corporation www.ddc-web.com 23 BU-64703 H-06/11-0 +3.3V INTERFACE TO MIL-STD-1553 BUS (BU-64703X8/9) The SSRT Mark3 is the world's first MIL-STD-1553 terminal powered entirely by 3.3 volts. Unique isolation transformer turns ratios, single output winding transformers and new interconnection methods are required in order to meet mandated MILSTD-1553 differential voltage levels. The center tap of the primary winding (the side of the transformer that connects to the SSRT Mark3) must be directly connected to the +3.3 volt plane. Additionally a 10f, low inductance tantalum capacitor and a 0.01f ceramic capacitor must be mounted as close as possible and with the shortest leads to the center tap of the transformer(s) and the ground plane. FIGURE 15 illustrates the two possible interface methods between the SSRT Mark3 series and a MIL-STD-1553 bus. Connections for both direct (short stub, 1:3.75) and transformer (long stub, 1:2.7) coupling, as well as nominal peak-to-peak voltage levels at various points (when transmitting), are indicated in the diagram. 3.3V 10F + .01F (1:3.75) (7.4 Vpp) SSRT Mark3 BU-64703X8/9 SHORT STUB (DIRECT COUPLED) 1 FT MAX 55 TX/RX DATA BUS Z0 7 Vpp 28 Vpp TX/RX 55 DIRECT-COUPLED ISOLATION TRANSFORMER 3.3V 10F + OR .01F TX/RX (1:2.7) LONG STUB (TRANSFORMER COUPLED) 0.75 Z0 20 FT MAX 28 Vpp 20 Vpp (7.4 Vpp) SSRT Mark3 BU-64703X8/9 (1:1.41) TX/RX 7 Vpp 0.75 Z0 TRANSFORMER-COUPLED ISOLATION TRANSFORMER COUPLING TRANSFORMER Z0 NOTES: 1. Transformer center tap capacitors: use a 10F tantalum for low inductance, and a 0.01F ceramic. Both must be mounted as close as possible, and with the shortest leads to the center tap of the transformer(s) and ground. 2. Connect the SSRT Mark3 hybrid grounds as directly as possible to the 3.3V ground plane. 3. Z0 = 70 to 85 Ohms. FIGURE 15. BU-64703X8/9 +3.3V INTERFACE TO MIL-STD-1553 BUS Data Device Corporation www.ddc-web.com 24 BU-64703 H-06/11-0 +3.3 VOLT INTERFACE TO MIL-STD-1553 BUS (BU-64703XC/D) Additionally, during transmission, large currents flow from the transceiver power supply through the TX/RX pins into the transformer primaries and then out the center tap into the ground plane. The traces in this path should be sized accordingly and the connections to the ground plane should be as short as possible. FIGURE 16 illustrates the two possible interface methods between the SSRT Mark3 series and a MIL-STD-1553 bus. Connections for both direct (short stub, 1:2.65) and transformer (long stub, 1:2.038) coupling, as well as nominal peak-to-peak voltage levels at various points (when transmitting), are indicated in the diagram. A 10f, low inductance tantalum capacitor and a 0.01f ceramic capacitor must be mounted as close as possible and with the shortest leads to the transceiver power input of the Mini-ACE Mark 3. The center tap of the primary winding (the side of the transformer that connects to the Mark3) must be directly connected to ground. 10F DATA BUS Z0 3.3V + .01F (1:2.65) SHORT STUB (DIRECT COUPLED) 1 FT MAX 55 TX/RX 7 Vpp 28 Vpp SSRT MARK3 BU-64703XC/D 55 TX/RX DIRECT-COUPLED ISOLATION TRANSFORMER OR 10F 3.3V + .01F (1:2.038) LONG STUB (TRANSFORMER COUPLED) (1:1.41) 0.75 Z0 20 FT MAX TX/RX 28 Vpp 20 Vpp SSRT MARK3 BU-64703XC/D TX/RX 7 Vpp 0.75 Z0 TRANSFORMER-COUPLED ISOLATION TRANSFORMER COUPLING TRANSFORMER NOTES: 1. Connect the SSRT Mark3 hybrid grounds as directly as possible to the 3.3V ground plane. 2. Zo = 70 to 85 Ohms. Z0 FIGURE 16. BU-64703XC/D +3.3 VOLT INTERFACE TO MIL-STD-1553 BUS Data Device Corporation www.ddc-web.com 25 BU-64703 H-06/11-0 +5.0V INTERFACE TO MIL-STD-1553 BUS FIGURE 17 illustrates the interface between the SSRT Mark3 +5.0V (BU-64703X3/4) and a MIL-STD-1553 bus. Connections for both direct (short stub) and transformer (long stub) coupling, 10F as well as the nominal peak-to-peak voltage levels at various points (when transmitting), are indicated in the diagram. DATA BUS Z0 5V + .01F (1:2.5) 1 FT MAX 55 TX/RX SSRT MARK3 BU-64703X3/4 SHORT STUB (DIRECT COUPLED) 11.2 Vpp 7 Vpp 28 Vpp 55 TX/RX ISOLATION TRANSFORMER OR 10F 5V + .01F (1:1.79) LONG STUB (TRANSFORMER COUPLED) (1:1.41) 0.75 Z0 20 FT MAX 28 Vpp 20 Vpp 11.2 Vpp SSRT MARK3 BU-64703X3/4 7 Vpp 0.75 Z0 COUPLING TRANSFORMER ISOLATION TRANSFORMER Z0 NOTES: 1. Z 0 = 70 TO 85 OHMS 2. NOMINAL VOLTAGE LEVELS SHOWN FIGURE 17. SSRT MARK3 +5.0V INTERFACE TO MIL-STD-1553 BUS Data Device Corporation www.ddc-web.com 26 BU-64703 H-06/11-0 +3.3V PULSE TRANSFORMERS In selecting isolation transformers to be used with the SSRT Mark3 , there is a limitation on the maximum amount of leakage inductance. If this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by MIL-STD-1553. In addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. across the "secondary" (stub side) winding must also be less than 5.0 H (Transformer Coupled) and 10.0 H (Direct Coupled). The difference between these two measurements is the "differential" leakage inductance. This value must be less than 1.0 H (Transformer Coupled) and 2.0 H (Direct Coupled). Beta Transformer Technology Corporation (BTTC), a subsidiary of DDC, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:3.75 direct coupled, and 1:2.7 transformer coupled for BU-64703X8/9 Models and the required turns ratios of 1:2.65 direct coupled, and 1:2.038 transformer coupled for BU-64703XC/D Models. TABLE 4 provides a listing of these transformers with the corresponding model numbers. The maximum allowable leakage inductance is a function of the coupling method. For Transformer Coupled applications, it is a maximum of 5.0 H. For Direct it is a maximum of 10.0 H, and is measured as follows: The side of the transformer that connects to the SSRT Mark3 is defined as the "primary" winding. If one side of the primary is shorted to the primary center-tap, the inductance should be measured across the "secondary" (stub side) winding. This inductance must be less than 5.0 H (Transformer Coupled) and 10.0 H (Direct Coupled). Similarly, if the other side of the primary is shorted to the primary center-tap, the inductance measured For further information, contact BTTC at 631-244-7393 or at www.bttc-beta.com. TABLE 4. BTTC TRANSFORMERS FOR USE WITH SSRT Mark3 BU-64703X8/9 BTTC PART NUMBER # OF CHANNELS, CONFIGURATION COUPLING RATIO DESCRIPTION COUPLING RATIO (1:X) MOUNTING MAX HEIGHT WIDTH (INCLUDING LEADS) LENGTH (INCLUDING LEADS) BU-64703X8/9 MLP-2033 Single Direct (1:3.75) SMT 0.185" 0.4" 0.52" BU-64703XC/D MLP-2030 Single Direct (1:2.65) SMT 0.185" 0.4" 0.52" BU-64703X8/9 MLP-3033 Single Direct (1:3.75) Through Hole 0.185" 0.4" 0.4" BU-64703X8/9 MLP-2233 Single Transformer (1:2.7) SMT 0.185" 0.4" 0.52" BU-64703XC/D MLP-2230 Single Transformer (1:2.038) SMT 0.185" 0.4" 0.52" BU-64703X8/9 MLP-3233 Single Transformer (1:2.7) Through Hole 0.185" 0.4" 0.4" BU-64703X8/9 MLP-3333 Single Direct & Transformer (1:3.75) & (1:2.7) Through Hole 0.185" 0.4" 0.4" BU-64703XC/D DSS-3330 Dual (Side-by-Side) Direct & Transformer (1:2.65) & (1:2.038) SMT 0.185" 0.52" 0.675" BU-64703X8/9 DSS-2033 Dual (Side-by-Side) Direct (1:3.75) SMT 0.13" 0.72" 0.96" BU-64703X8/9 DSS-2233 Dual (Side-by-Side) Transformer (1:2.7) SMT 0.13" 0.72" 0.96" BU-64703X8/9 DSS-1003 Dual (Side-by-Side) Direct & Transformer (1:3.75) & (1:2.7) SMT 0.165" 0.72" 0.96" BU-64703X8/9 TSM-2033 Dual (Stacked) Direct (1:3.75) SMT 0.32" 0.4" 0.52" BU-64703X8/9 TSM-2233 Dual (Stacked) Transformer (1:2.7) SMT 0.32" 0.4" 0.52" BU-64703XC/D TSM-2230 Dual (Stacked) Transformer (1:2.038) SMT 0.32" 0.4" 0.52" MODEL NUMBER Data Device Corporation www.ddc-web.com 27 BU-64703 H-06/11-0 +5.0V PULSE TRANSFORMERS Similarly, if the other side of the primary is shorted to the primary center-tap, the inductance measured across the "secondary" (stub side) winding must also be less than 6.0 H. In selecting isolation transformers to be used with the SSRT Mark3 +5.0V (BU-64703X3/4), there is a limitation on the maximum amount of leakage inductance. If this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by MILSTD-1553. In addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. The difference between these two measurements is the "differential" leakage inductance. This value must be less than 1.0 H. Beta Transformer Technology Corporation (BTTC), a subsidiary of DDC, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:2.5 direct coupled, and 1:1.79 transformer coupled. TABLE 4A provides a listing of many of these transformers. The maximum allowable leakage inductance is 6.0 H, and is measured as follows: The side of the transformer that connects to the SSRT Mark3 +5.0V (BU-64703X3/4) is defined as the "primary" winding. If one side of the primary is shorted to the primary center-tap, the inductance should be measured across the "secondary" (stub side) winding. This inductance must be less than 6.0 H. For further information, contact BTTC at 631-244-7393 or at www.bttc-beta.com. TABLE 4A. BTTC TRANSFORMERS FOR USE WITH SSRT MARK3 +5.0V (BU-64703X3/4) BTTC PART NUMBER # OF CHANNELS, CONFIGURATION COUPLING RATIO DESCRIPTION COUPLING RATIO (1:X) MOUNTING MAX HEIGHT WIDTH (INCLUDING LEADS) LENGTH (INCLUDING LEADS) MLP-2005 Single Direct (1:2.5) SMT 0.185" 0.4" 0.52" MLP-3005 Single Direct (1:2.5) Through Hole 0.185" 0.4" 0.4" B-3230 (-30) # Single Direct (1:2.5) Through Hole 0.25" 0.35" 0.5" MLP-2205 Single Transformer (1:1.79) SMT 0.185" 0.4" 0.52" MLP-3205 Single Transformer (1:1.79) Through Hole 0.185" 0.4" 0.4" B-3229 (-29) # Single Transformer (1:1.79) Through Hole 0.25" 0.35" 0.5" SMT 0.19" 0.63" 1.13" HLP-6015 # Single Direct & Transformer (1:2.5) & (1:1.79) B-3227 (-27) # Single Direct & Transformer (1:2.5) & (1:1.79) SMT 0.29" 0.63" 1.13" MLP-3305 Single Direct & Transformer (1:2.5) & (1:1.79) Through Hole 0.185" 0.4" 0.4" B-3226 (-26) # Single Direct & Transformer (1:2.5) & (1:1.79) Through Hole 0.25" 0.625" 0.625" HLP-6014 # Single Direct & Transformer (1:2.5) & (1:1.79) Flat Pack 0.19" 0.63" 1.13" B-3231 (-31) # Single Direct & Transformer (1:2.5) & (1:1.79) Flat Pack 0.29" 0.63" 1.13" DSS-2005 Dual (Side-by-Side) Direct (1:2.5) SMT 0.13" 0.72" 0.96" DSS-2205 Dual (Side-by-Side) Transformer (1:1.79) SMT 0.13" 0.72" 0.96" SMT 0.165" 0.72" 0.96" DSS-1005 Dual (Side-by-Side) Direct & Transformer (1:2.5) & (1:1.79) TSM-2005 Dual (Stacked) Direct (1:2.5) SMT 0.32" 0.4" 0.52" TSM-2205 Dual (Stacked) Transformer (1:1.79) SMT 0.32" 0.4" 0.52" SMT 0.335" 1.125" 1.125" TST-9117 # Dual (Stacked) Direct & Transformer (1:2.5) & (1:1.79) TST-9107 # Dual (Stacked) Direct & Transformer (1:2.5) & (1:1.79) Through Hole 0.335" 0.625" 0.625" TST-9127 # Dual (Stacked) Direct & Transformer (1:2.5) & (1:1.79) Flat Pack 0.335" 0.625" 0.625" Notes: 1. All Transformers in the table above can be used with BU-6XXXXX3/6 (1553B transceivers). 2. Transformers identified with "#" in the table above are not recommended for use with the BU-6XXXXX4 (McAir-Compatable transceivers) Data Device Corporation www.ddc-web.com 28 BU-64703 H-06/11-0 1553 BUS CONNECTIONS The isolation transformers should be placed as physically close as possible to the respective TX/RX pins on the SSRT Mark3. Also, the distance from the isolation transformers to any connectors or cables leaving the board should be as short as possible. In addition to limiting the voltage drops in the analog signal traces when transmitting, reducing the hybrid-to-transformer and transformer-to-connector spacing serves to minimize crosstalk from other signals on the board. The effect of a relatively long stub cable will be to reduce the measured impedance (looking in from the bus). In order to keep the impedance above the required level of 1000 ohms (for transformer-coupled stubs), the length of any cable between the 1553 RT and the system connector should be minimized. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS The general practice in connecting the stub side of a transformer (or direct) coupled terminal to an external system connector is to make use of 78 ohm twisted-pair shielded cable. This minimizes impedance discontinuities. The decision of whether to isolate or make connections between the center tap of the isolation transformer's secondary, the stub shield, the bus shield, and/or chassis ground must be made on a system basis, as determined by an analysis of EMI/RFI and lightning considerations. For purposes of software development and system integration, it is generally not necessary to integrate the required couplers, terminators, etc., that comprise a complete MIL-STD-1553B bus. In most instances, a simplified electrical configuration will suffice. The three connection methods illustrated in FIGURE 18 allow the SSRT Mark3 to be interfaced over a "simulated bus" to simulation and test equipment. It is important to note that the termination resistors indicated are necessary in order to ensure reliable communications between the SSRT Mark3 and the simulation/ test equipment. In most systems, it is specified that the 1553 terminal's input impedance must be measured at the system connector. This is despite the fact that the MIL-STD-1553B requirement is for it to be measured looking directly in from the bus side of the isolation transformer. ISOLATION TRANSFORMER STUB COUPLING STUB COUPLING SSRT Mark3 TEST/ SIMULATION EQUIPMENT 78 1.5W HYBRID (A) ISOLATION TRANSFORMER DIRECT COUPLING DIRECT COUPLING 55 1W SSRT Mark3 HYBRID 55 1W 55 TEST/ SIMULATION EQUIPMENT 39 0.5W 55 (B) ISOLATION TRANSFORMER DIRECT COUPLING SSRT Mark3 HYBRID 20 0.5W 55 1W 55 1W STUB COUPLING TEST/ SIMULATION EQUIPMENT 39 0.5W 20 0.5W (C) (A) TRANSFORMER COUPLED TO TRANSFORMER COUPLED (B) DIRECT COUPLED TO DIRECT COUPLED (C) DIRECT COUPLED TO TRANSFORMER COUPLED FIGURE 18. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS Data Device Corporation www.ddc-web.com 29 BU-64703 H-06/11-0 SIMPLE SYSTEM INTERFACE FIGURE 19 illustrates the capability of the SSRT Mark3 to interface to a system with no host processor in burst mode. In this example, only one set of external latches is needed to buffer the data words written by the SSRT Mark3 to the external system. In burst mode, all received data words are stored in the internal FIFO until the last word is received. At this point, the SSRT Mark3 will transfer the entire contents of the FIFO to the system if the message is validated. In this case, GBR will be driven low for two clock cycles following the burst transfer cycle. If the received message is not valid, the FIFO data will not be transferred to the external system and GBR will remain high. BUS A D15-D0 Write Address Decoder LATCH DISCRETE DIGITAL OUTPUTS LATCH BUS B EN MEMWR TRI-STATE BUFFER BU-64703 SSRT Mark3 RT ADDRESS RTAD4-0, RTADP EN L-BRO, T/R, SA4-0, WC/CWC4-0 Read Address Decoder Clock Oscillator EN CLK-IN MEMOE TRI-STATE BUFFER EN +3.3V +3.3V DISCRETE DIGITAL INPUTS +V AUTO_CFG TRI-STATE BUFFER MSTCLR EN DTGRT AUTOCONFIGURATION (OPTIONAL) RTACTIVE DTACK FIGURE 19. SSRT Mark3-TO-SIMPLE SYSTEM INTERFACE (FOR BURST MODE) Data Device Corporation www.ddc-web.com 30 BU-64703 H-06/11-0 BIT WORD The SSRT Mark3 provides an internally formulated Built-In-Test word (BIT word). This word is transmitted to the BC in response to a Transmit BIT Word Mode Code Command. The BIT word bit functions and descriptions are provided in TABLE 5. TABLE 5. INTERNAL BUILT-IN-TEST (BIT) WORD DEFINITION BIT 15 (MSB) FUNCTION TRANSMITTER TIMEOUT 14 13 CH. B LOOP TEST FAILURE CH. A LOOP TEST FAILURE 12 HANDSHAKE FAILURE 11 10 DESCRIPTION Set if the SSRT Mark3's failsafe timer detected a fault condition. The transmitter timeout circuit will automatically shut down the CH. A or CH. B transmitter if it transmits for longer than 660.5 s. A loopback test is performed on the transmitted portion of every non-broadcast message. A validity check is performed on the received version of every word transmitted by the SSRT Mark3. In addition, a bit-by-bit comparison is performed on the last word transmitted by the RT for each message. If either the received version of the last word does not match the transmitted version and/or the received version of any transmitted word is determined to be invalid (sync, encoding, bit count, parity), or a failsafe timeout occurs on the respective channel, the LOOP TEST FAILURE bit for the respective bus channel will be set. If this bit is set, it indicates that the subsystem had failed to respond with the DMA handshake input DTGRT asserted within 10 s after the SSRT Mark3 has asserted DTREQ. TRANSMITTER SHUTDOWN B If either of these bits are logic "1", this indicates that the respective 1553 transmitter has been shut TRANSMITTER SHUTDOWN A down by means of a Transmitter shutdown mode command. 9 TERMINAL FLAG INHIBITED Set to logic "1" if the SSRT Mark3's Terminal flag RT status bit has been disabled by an Inhibit terminal flag mode code command. Will revert to logic "0" if an Override inhibit terminal flag mode code command is received. 8 BIT TEST FAIL Set to logic "1" to denote that the SSRT Mark3 has failed its off-line protocol self-test. This bit will be logic "0" if the self-test passed or had not been performed. 7 HIGH WORD COUNT Set to logic "1" if the previous message had a high word count error. Set to logic "1" if the previous message had a low word count error. 6 LOW WORD COUNT 5 INCORRECT SYNC TYPE RECEIVED 4 INVALID WORD MANCHESTER/PARITY ERROR RECEIVED 3 If set, indicates that the SSRT Mark3 detected a Command sync in a received Data Word. Indicates that the SSRT Mark3 received one or more words containing one or more of the following error types: sync field error, Manchester encoding error, parity error, and/or bit count error. RT-RT TRANSFER RESPONSE This bit is set if the SSRT Mark3 is the receiving RT for an RT-to-RT transfer and one or more of the ERROR (no gap, data, sync, following errors occurs: (1) If the transmitting RT responds with a response time of less than 4 s, per address mismatch) MIL-STD-1553B (mid-parity bit to mid-sync); i.e., less than 2 s dead time; and/or (2) There is an incorrect sync type or format error (encoding, bit count, and/or parity error) in the transmitting RT Status Word; and/or (3) The RT address field of the transmitting RT Status Word does not match the RT address in the transmit Command Word. 2 RT-RT TRANSFER NO RESPONSE TIMEOUT If set, indicates that, for the previous message, the SSRT Mark3 was the receiving RT for an RT-to-RT transfer and that the transmitting RT either did not respond or responded later than the SSRT Mark3 RT-to-RT timeout time. The SSRT Mark3's RT-to-RT response timeout time is defined as the time from the mid-bit crossing of the parity bit of the transmit Command Word to the mid-sync crossing of the transmitting RT status word. The value of the SSRT Mark3's RT-to-RT response timeout time is in the range from 17.5 to 19.5 s. 1 RT-RT TRANSFER T/R ERROR ON SECOND COMMAND OR INVALID ADDRESS If the SSRT Mark3 is the receiving RT for an RT-to-RT transfer, if this bit is set, it indicates one or more of the following error conditions in the transmit Command Word: (1) T/R bit = logic "0"; (2) subaddress = 00000 or 11111; (3) same RT Address field as the receive Command Word. 0 (LSB) COMMAND WORD CONTENTS ERROR Indicates that a received command word is not defined in accordance with MIL-STD-1553B. This includes the following undefined Command Words: (1) The Command Word is a non-mode code, broadcast, transmit command; (2) a message with a T/R bit of "0", a subaddress/mode field of 00000 or 11111, and a mode code field with a value between 00000 and 01111; (3) a mode code command that is not permitted to be broadcast (e.g., Transmit Status) is sent to the broadcast address 11111. Note: Bits 15 through 9 are cleared only following a RESET input or receipt of a Reset Remote Terminal mode command. Bits 8 through 0 are updated as a result of every message processed. Data Device Corporation www.ddc-web.com 31 BU-64703 H-06/11-0 MODE CODES The SSRT Mark3 fully implements all 13 of the dual redundant MIL-STD-1553B mode codes. Four of the mode codes, Transmit vector word, Synchronize (with data), Selected transmitter shutdown, and Override transmitter shutdown, involve data transfers with the subsystem. For the Transmit last command mode command, the data word transmitted is from the SSRT Mark3's last command internal register. For the Transmit BIT word mode command, the SSRT Mark3's internally formulated BIT Word is trans- mitted. TABLE 6 provides a summary of the 1553B mode codes supported by the SSRT Mark3. SUMMARY OF RESPONSES TO MODE CODE MESSAGES The SSRT Mark3's responses to mode codes, including responses to various error conditions, are summarized in TABLE 6. TABLE 6. MODE CODE SUMMARY T/R BIT MODE CODE FUNCTION DATA WORD BROADCAST ALLOWED 0 00000-01111 Undefined No No 1 00000 Dynamic Bus Control No No 1 00001 Synchronize No Yes 1 00010 Transmit Status Word No No 1 00011 Initiate Self Test No Yes 1 00100 Transmitter Shutdown No Yes 1 00101 Override Transmitter Shutdown No Yes 1 00110 Inhibit Terminal Flag No Yes 1 00111 Override Inhibit Terminal Flag No Yes 1 01000 Reset Remote Terminal No Yes 1 01001-01111 RESERVED No TBD 1 10000 Transmit Vector Word From Subsystem No 0 10001 Synchronize with Data To Subsystem Yes 1 10010 Transmit Last Command From Internal Register No 1 10011 Transmit BIT Word From Internal Register No 0 10100 Selected Transmitter Shutdown (see Note) To Subsystem Yes 0 10101 Override Selected Transmitter Shutdown (see Note) To Subsystem Yes 1 10110-11111 RESERVED From Subsystem TBD 0 10110-11111 RESERVED To Subsystem TBD Note: For the Selected transmitter shutdown and Override transmitter shutdown mode commands, the SSRT Mark3 responds with Clear Status but no action is taken. Data Device Corporation www.ddc-web.com 32 BU-64703 H-06/11-0 DETAILED MODE CODES FUNCTIONAL DESCRIPTION The applicable Mode Codes for the SSRT Mark3 are described below: DYNAMIC BUS CONTROL ( T/R = 1; 00000) MESSAGE SEQUENCE = DBC + STATUS The SSRT Mark3 responds with Status showing non-acceptance of the mode code command. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). 5. Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). SYNCHRONIZE WITHOUT DATA WORD ( T/R = 1; 00001) MESSAGE SEQUENCE = SYNC + STATUS The SSRT Mark3 responds with Status. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). TRANSMIT STATUS WORD ( T/R = 1; 00010) MESSAGE SEQUENCE = TRANSMIT STATUS + STATUS The Status register is not updated before it is transmitted and contains the resulting status from the previous command (assuming that it was not a Transmit status or Transmit last command mode command). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word) 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). 5. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Contents Error (BIT Word). INITIATE SELF-TEST ( T/R = 1; 00011) MESSAGE SEQUENCE = SELF TEST + STATUS If the command was non-broadcast, the SSRT Mark3 responds with Status. If the command was either non-broadcast or broadcast, the SSRT Mark3 will go offline and perform its internal off-line protocol self-test. The self-test exercises the SSRT Mark3's encoder and decoders, registers, transmitter watchdog timer, and protocol logic. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT Mark3 is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus. The bus controller may determine the result of the self-test by means of a Transmit BIT word mode command. If the self-test passes, bit 8 of the SSRT Mark3's BIT word (BIT Test Fail) will be logic "0"; if the self-test fails, this bit will be logic "1". In addition, if self-test fails, the terminal flag status word bit will be set to logic "1" in response to the next non-broadcast message. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). 5. Loopback Test Failure. Set Terminal Flag bit in internal Status register (Status Word for next non-broadcast command), Current Channel (A or B) Loop Test Failure and CH A/B Loop Test Failure (BIT Word), assert RTFAIL output. Data Device Corporation www.ddc-web.com 33 BU-64703 H-06/11-0 TRANSMITTER SHUTDOWN ( T/R = 1; 00100) MESSAGE SEQUENCE =SHUTDOWN + STATUS This command is only used with dual redundant bus systems. The SSRT Mark3 responds with Status. Following the Status transmission, the SSRT Mark3 inhibits any further transmission from the alternate redundant channel. Once shutdown, the transmitter can only be reactivated by an Override Transmitter Shutdown or Reset RT mode command, or Hardware Reset (MSTRCLR input). Note that the receivers on both channels are always active, even when the transmitters are inhibited. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). OVERRIDE TRANSMITTER SHUTDOWN ( T/R = 1; 00101) MESSAGE SEQUENCE = OVERRIDE SHUTDOWN + STATUS This command is only used with dual redundant bus systems. The SSRT Mark3 responds with Status. At the end of the Status transmission, the SSRT Mark3 reactivates the transmitter of the alternate redundant bus. If the command was broadcast, the Broadcast Command Received Status Word bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00110) MESSAGE SEQUENCE = INHIBIT TERMINAL FLAG + STATUS The SSRT Mark3 responds with Status and inhibits further setting of the Terminal Flag bit in its internal Status Word register. Once the Terminal Flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT mode code commands, or by Reset. If the command was broadcast, the Broadcast Received bit is set, the state of the Terminal Flag bit in the internal Status Word register remains unchanged and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). OVERRIDE INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00111) MESSAGE SEQUENCE = OVERRIDE INHIBIT TERMINAL FLAG + STATUS The SSRT Mark3 responds with Status and re-enables the Terminal Flag bit in its internal Status register. If the command was a broadcast, the Broadcast Command Received bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). Data Device Corporation www.ddc-web.com 34 BU-64703 H-06/11-0 RESET REMOTE TERMINAL ( T/R = 1; 01000) MESSAGE SEQUENCE = RESET REMOTE TERMINAL + STATUS The SSRT Mark3 responds with Status and internally resets. The Message Error and Broadcast Command Received bits of the internal Status register are reset to 0. The internal BIT Word Register is reset to 0. If either of the 1553 transmitters has been shut down, the shutdown condition is overridden. If the Terminal Flag bit has been inhibited, the inhibit is overridden. If the command is received as a broadcast, the Broadcast Command Received bit is set and the Status Word is suppressed. Also, if the command is received as a broadcast and the Terminal Flag bit had been set as a result of the Loopback test of the previous message, the Terminal Flag bit is not reset to zero. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). RESERVED MODE CODES ( T/R = 1; 01001 - 01111) MESSAGE SEQUENCE = RESERVED MODE COMMAND + STATUS The SSRT Mark3 responds with status. If the command has been illegalized by means of the illegalization table, the Message Error Status Word bit will be set. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). TRANSMIT VECTOR WORD ( T/R = 1; 10000) MESSAGE SEQUENCE = TRANSMIT VECTOR WORD + STATUS VECTOR WORD The SSRT Mark3 transmits a Status Word followed by a vector word. The vector word is read from the external subsystem. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 4. T/R bit Set to Zero plus one Data Word. The SSRT Mark3 will respond with Status 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Low Word Count (BIT word). 6. Zero T/R bit and Broadcast Address, plus one Data Word. No Status response. Set Broadcast Command Received bits (Status Word) 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word Contents Error (BIT word). SYNCHRONIZE WITH DATA WORD ( T/R = 0; 10001) MESSAGE SEQUENCE = SYNCHRONIZE COMMAND/DATA WORD + STATUS The SSRT Mark3 will write the received 16 bit data word to the external subsystem. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Correct Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word) 3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), High Word Count (BIT word). 4. Command T/R bit set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read from the subsystem (or single-word data block for subaddress 0000 or 1111). 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word); Set Command Word Contents Error (BIT word). Data Device Corporation www.ddc-web.com 35 BU-64703 H-06/11-0 TRANSMIT LAST COMMAND ( T/R = 1; 10010) MESSAGE SEQUENCE = TRANSMIT LAST COMMAND + STATUS/LAST COMMAND The Status register is not updated before transmission. It contains the Status from the previous command. The Data Word transmitted contains the previous valid command (providing it was not another TRANSMIT LAST COMMAND or TRANSMIT STATUS WORD mode command). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word). 3. T/R bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word). 4. T/R bit Set to Zero, plus one Data Word. The SSRT Mark3 will respond with Status. The Data Word is transferred to the internal register. 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word), Low Word Count Error(BIT Word). 6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is transferred to the internal register. 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word Contents Error (BIT Word). TRANSMIT BIT WORD ( T/R = 1; 10011) MESSAGE SEQUENCE = TRANSMIT BIT WORD + STATUS/BIT WORD The SSRT Mark3 responds with Status followed by the Built-in Test (BIT) word. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word). 3. T/R bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word). 4. T/R bit Set to Zero, plus one Data Word. The SSRT Mark3 will respond with Status. The Data Word is transferred to internal registers. 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word), Low Word Count Error (BIT Word). 6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is transferred to internal registers. 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command received bits (Status Word), Command Word contents Error (BIT Word). SELECTED TRANSMITTER SHUTDOWN ( T/R = 0; 10100) MESSAGE SEQUENCE = TRANSMITTER SHUTDOWN/DATA + STATUS The Data Word received is transferred to the subsystem and Status is transmitted. No other action is taken by the SSRT Mark3. No transmitters are shut down as a result of this mode command. This command is intended for use with RTs with more than one dual redundant channel. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count Bit (BIT Word). No status response. Bits Set: message error (SW), High Word Count, Illegal Mode Code (BIT Word) 3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count Bit (BIT Word). 4. Command T/R bit Set to One followed by one Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit Set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read from the subsystem. 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Command Contents Error (BIT Word). Data Device Corporation www.ddc-web.com 36 BU-64703 H-06/11-0 OVERRIDE SELECTED TRANSMITTER SHUTDOWN ( T/R = 0; 10101) MESSAGE SEQUENCE = TRANSMITTER SHUTDOWN/DATA + STATUS The Data Word received is transferred to the subsystem. No transmitters that have been previously shut down are reactivated as a result of this command. No other action is taken by the SSRT Mark3. This command is intended for use with RTs with more than one dual redundant channel. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count bit (BIT Word). 4. Command T/R bit Set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit Set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read from the subsystem. 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Command Contents Error (BIT Word). RESERVED MODE CODES ( T/R = 1; 11111) MESSAGE SEQUENCE (when T/R = 1) = RESERVED MODE CODE STATUS/DATA (when T/R = 0) = RESERVED MODE CODE DATA + STATUS For a RESERVED receive Command, the SSRT Mark3 stores the Data Word to the subsystem. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. For a RESERVED transmit Command Word, the SSRT Mark3 responds with Status plus a single Data Word. The Data Word is read from the subsystem. ERROR CONDITIONS (T/R = 1) 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. Broadcast Command. No Status response. Set Message Error bit (status word), and Command Word Contents Error (BIT Word). ERROR CONDITIONS (T/R = 0) 1. Invalid Command. No response, command ignored. 2. Command not followed by Contiguous Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 3. Command followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT word). Data Device Corporation www.ddc-web.com 37 BU-64703 H-06/11-0 SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS TABLE 7. BU-64703X8/9 POWER AND GROUND SIGNAL NAME +3.3V_Xcvr PIN 10 DESCRIPTION Transceiver power. 30 +3.3V_Logic 51 Logic power. 69 Gnd_Xcvr 22 79 Transceiver Ground. 14 31 Gnd_Logic 50 Logic Ground. 70 77 TABLE 7A. BU-64703X3/4 POWER AND GROUND SIGNAL NAME PIN +5.0V_Xcvr 10 +3.3V_Logic 51 DESCRIPTION Transceiver power. 30 Logic power. 69 Gnd_Xcvr 22 79 Transceiver Ground. 14 31 Gnd_Logic 50 Logic Ground. 70 77 TABLE 8. MIL-STD-1553 ISOLATION TRANSFORMER INTERFACE SIGNAL NAME 3 TX/RX-A (I/O 5 TX/RX-B (I/O 15 TX/RX-B (I/O DESCRIPTION PIN TX/RX-A (I/O) Analog transmit/receive input/output signals. Connect directly to 1553 isolation transformers. 17 Data Device Corporation www.ddc-web.com 38 BU-64703 H-06/11-0 TABLE 9. DATA BUS (16) SIGNAL NAME PIN D15 (I/O) (MSB) 59 D14 (I/O) 56 D13 (I/O) 54 D12 (I/O) 55 D11 (I/O) 58 D10 (I/O) 60 D09 (I/O) 57 D08 (I/O) 52 D07 (I/O) 53 D06 (I/O) 41 D05 (I/O) 49 D04 (I/O) 43 D03 (I/O) 48 D02 (I/O) 47 D01 (I/O) 42 D00 (I/O) (LSB) 46 DESCRIPTION 16-bit bi-directional data bus. When the SSRT Mark3 is writing data to the external system, these signals are active outputs. At all other times, these signals are high impedance inputs. TABLE 10. COMMAND / ADDRESS BUS SIGNAL PIN DESCRIPTION L_BRO (O) 1 Latched Broadcast. This two-state output signal is latched following receipt of a new command word. For a broadcast command, this signal outputs a value of logic "1". For a non-broadcast message, this signal will output logic "0". T/R 2 Transmit/Receive. This two-state output signal is latched following receipt of a new command word. For a transmit message, this signal will output a value of logic "1". For a receive message, this signal will output logic "0". SA4 (O) 75 SA3 (O) 7 Subaddress. These five two-state output signals are latched following receipt of a new command word. They provide the subaddress field of the received command word. SA2 (O) 12 SA1 (O) 27 SA0 (O) 74 WC / MC / CWC4 (O) (MSB) 78 WC / MC / CWC3 (O) 13 WC / MC / CWC2 (O) 19 WC / MC / CWC1 (O) 33 WC / MC / CWC0 (O) (LSB) 18 Data Device Corporation www.ddc-web.com Word Count/Mode Code/Current Word Count. Following receipt of a new command word, these five two-state output signals provide the contents of the command word's Word Count/Mode Code field. For a non-mode code receive message, the contents of WC/CWC are updated and incremented to reflect the value of the current data word being transferred to the system (in non-burst mode), or to the internal FIFO (in burst mode). CWC increments from 0 to the value of the Word Count field - 1 during the message. At the end of a non-mode code receive message in burst mode, the contents of CWC will then increment from 0 to the value of the word count field -1, as each word is transferred from the internal FIFO to the external system over D15D0. In burst mode, it takes three clock cycles to transfer each word to the external system. For a non-mode code transmit command, the value of CWC starts from 0 and increments to the value of Word Count 1, as each word is read from the external system and transferred to the SSRT Mark3. For a mode code command, the WC/CWC outputs the command word mode code field, which remains latched through the end of the message (until receipt of a subsequent command word). 39 BU-64703 H-06/11-0 TABLE 11. DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS SIGNAL PIN DTREQ (O) 29 Data Transfer Request. Active low level output signal used to request use of the external system data bus (D15-D0). DTGRT (I) 72 Data Transfer Grant. Input from the external subsystem that must be asserted low in response to the SSRT Mark3 asserting DTREQ low in order to enable the SSRT Mark3 to read data from or write data to the external subsystem. DESCRIPTION The maximum allowable time from DTREQ to DTGRT is 10 s. If the SSRT Mark3's DMA handshake isn't required, DTGRT may be hardwired to logic "0". DTACK (O) 35 Data Transfer Acknowledge. Active low output signal used to indicate the SSRT Mark3's acceptance of the system data bus (D15-D0), in response to a data transfer grant (DTGRT). The SSRT Mark3's data transfers over D15-D0 will be framed by the time that DTACK is asserted low. If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of MSTCLR, following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted low to enable configuration data to be read from an external tri-state buffer. For transmit messages, or receive messages in non-burst mode, or for receive messages to subaddress 30 assuming that Subaddress 30 Autowrap is disabled, DTACK will be asserted low to indicate the transfer of individual words between the external system and the SSRT Mark3. For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the DTREQto-DTGRT handshake following the receipt of the last received data word. It will remain low for the duration of the DMA burst write transfer from the SSRT Mark3 to the external system. The total time for a burst write transfer is three clock cycles times the number of data words. HS_FAIL (O) 63 Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition. That is, the system did not respond with a DTGRT in time, following the SSRT Mark3's assertion of DTREQ. MEMOE (O) 20 Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external system to be enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the external system. The SSRT Mark3 latches the data one clock cycle prior to the rising edge of MEMOE. MEMWR (O) 28 Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT Mark3 write cycles. Used to transfer data from the SSRT Mark3 to the external system. The external system may latch data on either the falling or rising edge of MEMWR. TABLE 12. RT ADDRESS DESCRIPTION SIGNAL PIN RTAD4 (I) (MSB) 40 RTAD3 (I) 39 RTAD2 (I) 24 RTAD1 (I) 45 RTAD0 (I) (LSB) 38 RTADP (I) 44 Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD4RTAD0 and RTADP. RT_AD_LAT (I) 36 RT Address Latch. If RT_AD_LAT is connected to logic "0", then the SSRT Mark3 is configured to accept a hardwired RT address from RTAD4-RTAD0 and RTADP. RT Address inputs. If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP will be latched internally by the SSRT Mark3 on the rising edge of RT_AD_LAT. RT_AD_ERR (O) 6 Data Device Corporation www.ddc-web.com Remote Terminal Address Error. Output Signal that reflects the parity combination of the RTAD[4:0] inputs and RTADP input. A high level indicates odd (correct) parity. A low level indicates even (incorrect) parity. Note, if RT_AD_ERR is low, then the SSRT Mark3 will not recognize any valid Command Word received to its own RT address. 40 BU-64703 H-06/11-0 TABLE 13. RT STATUS WORD INPUTS SIGNAL PIN DESCRIPTION ILLEGAL (I) 68 Illegal. Input to the SSRT Mark3 that is sampled after the Command Word transfer. A logic "0" will cause the Message Error bit in the status response to be set (logic "1"), while a logic "1" on this input will have no effect on the Message Error bit. SRV_RQST (I) 66 Service Request. When this input is logic "0", the Service request bit in the SSRT Mark3's status word will be logic "1". When this input is logic "1", the Service request bit in the SSRT Mark3's status word will be logic "0". SSFLAG (I) 37 Subsystem Flag. If this input is asserted low, the Subsystem Flag bit will be set in the SSRT Mark3's Status Word. BUSY (I) 61 Busy. If this input is asserted low, the Busy bit will be set to logic "1" in the SSRT Mark3's Status Word. If the Busy bit in the status word is logic "1", the SSRT Mark3 will not transmit any data words, except for a Transmit last command or Transmit BIT word mode command. For a receive command, if the SSRT Mark3 is Busy, it will still transfer data words to the external system (although these transfers may be blocked by means of external logic). TABLE 14. RT ACTIVITY AND MESSAGE STATUS INDICATORS SIGNAL PIN DESCRIPTION RTACTIVE (O) 62 RT Active. This signal will be low (logic "0") following power turn-on, and when the SSRT Mark3 is reading its Autoconfigure word or is performing its internal self-test. After the self-test passes, or if the Auto-configure option is not used, or if Auto-configure is used but bit 5 of the Auto-configure word is logic "1" (meaning for the RT to always go online), RTACTIVE will then transition to logic "1". When this occurs, the SSRT Mark3 will begin processing messages over the 1553 bus. If Auto-configure is enabled, and bit 5 of the Auto-configure word is logic "0" and the self-test fails, then RTACTIVE will remain at logic "0". In this case, the SSRT Mark3 will remain offline and not process any 1553 messages. A failed self test will cause RTFAIL_L to be asserted low (logic "0"). If the auto-configure option is used, the external system should enable the configuration bits on D5-D0 when RTACTIVE and DTACK are both outputting logic "0". INCMD 32 In-command. This two-state output is asserted low whenever a message is being processed by the SSRT Mark3. GBR (O) 67 Good Block Received. Low level two-state output pulse (2 clock cycles wide) that is used to indicate to the external system that a valid, legal, non-mode receive command with the correct number of valid data words has been received and transferred to the external system. For non-burst mode, this pulse will occur after the last data word is transferred. Assuming a DTREQ-to-DTGRT time of 0, this will be approximately 4 s following the mid-parity bit crossing of the last received data word. For burst mode, the GBR pulse will begin synchronous with the rising edge of DTACK at the end of the burst write transfer. MSG_ERR (O) 34 Message Error. Active low level two-state output signal used to flag to the external system that there was a message error on the 1553 bus communication (word, gap, or word count error) for a particular message. This output goes low upon detecting the error and is reset following the receipt of the next valid command word (to the RT) from the 1553 bus, or if MSTCLR is asserted low. If this output goes low, all further servicing of the current message is aborted. RTFAIL (O) 64 Remote Terminal Fail. This two-state output signal will be asserted low following a failure of the built-in self-test performed following power turn-on or as the result of the receipt of an Initiate self-test mode command. The built-in off-line self-test includes tests of the Manchester encoder and decoders, transmitter failsafe timer, and RT protocol logic. In addition, RTFAIL will be asserted low following a failure of the on-line loop test for any non-broadcast message. The on-line loop test verifies the validity of the received version of all transmitted words (sync, Manchester encoding, bit count, parity), and includes a bit-by-bit comparison and verification of the last transmitted word. If asserted to logic "0", RTFAIL will clear to logic "1" when the SSRT Mark3 begins transmission of its status word in response to a subsequent valid non-broadcast message. Data Device Corporation www.ddc-web.com 41 BU-64703 H-06/11-0 TABLE 15. CONTROL INPUTS SIGNAL PIN DESCRIPTION MSTCLR (I) 25 Master Clear. Negative true Reset input, asserted low following power turn-on. When coming out of a "reset" condition, note that the risetime of MSTCLR must be less than 10 s. AUTO_CFG (I) 76 Auto-configure input. If connected to logic "1", then the auto-configure option is disabled, and the six configuration parameters revert to their default values as listed in TABLE 2. Note that the default condition for each configuration parameter is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default). If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 during a DMA read data transfer, when RTACTIVE and DTACK are logic "0", following MSTCLR transitioning from logic "0" to logic "1". Each of the configuration parameters is enabled if the SSRT Mark3 reads a value of logic "1" for the respective data bit. BRO_ENA (I) 71 Broadcast Enable. If this input is logic "1", the SSRT Mark3 will recognize RT address 31 as the broadcast address. If this input is logic "0", the SSRT Mark3 will not recognize RT address 31 as the broadcast address; however, in this configuration, RT address 31 may be used as a standard RT address. TX_INH (I) 65 Transmitter inhibit input for the MIL-STD-1553 transmitters. For normal operation, this input should be connected to logic "0". To force a shutdown of the Channel A and Channel B transmitters, a value of logic "1" should be applied to this input. TABLE 16. CLOCK INPUT SIGNAL DESCRIPTION PIN CLK_IN (I) 26 Clock Input. The clock frequency must be designated by means of the CLK_SEL_1 and CLK_SEL_0 inputs. CLK_SEL_1 (I) 73 These two inputs are used to designate the SSRT Mark3's clock frequency, as follows: CLK_SEL_1 CLK_SEL_0 (I) 80 CLK_SEL_0 Clock Frequency 0 0 10 MHz 0 1 20 MHz 1 0 12 MHz 1 1 16 MHz TABLE 17. FACTORY TEST (NO USER CONNECTIONS) SIGNAL NC PIN 4 DESCRIPTION For factory test only. Do not connect for normal operation. 8 9 11 16 21 23 Data Device Corporation www.ddc-web.com 42 BU-64703 H-06/11-0 PIN FUNCTIONS TABLE 18. BU-64703X8/9 "GULL WING" AND FLAT PACKAGE PIN FUNCTIONS PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION 1 L_BRO 21 N/C 41 D6 61 2 T/R 22 GROUND_XCVR 42 D1 62 BUSY RTACTIVE 3 TX/RX_A 23 N/C 43 D4 63 HS_FAIL 4 N/C 24 RTAD2 44 RTADP 64 5 TX/RX_A 25 45 RTAD1 65 RT_FAIL TX_INH 6 26 46 D0 66 SRV_RQST 7 RT_AD_ERR SA3 MSTCLR CLOCK_IN 27 SA1 47 D2 67 GBR 8 N/C 28 MEMWR 48 D3 68 9 N/C 29 DTREQ 49 D5 69 ILLEGAL +3.3V_LOGIC 10 11 +3.3 V_XCVR N/C 30 +3.3V_LOGIC GROUND_LOGIC 50 70 GROUND_LOGIC 51 GROUND_LOGIC +3.3V_LOGIC 71 BRO_ENA 12 SA2 32 D8 72 13 WC3 33 INCMD WC1 52 53 D7 73 DTGRT CLK_SEL_1 14 GROUND_LOGIC 34 MSG_ERR 54 D13 74 SA0 TX/RX_B N/C 35 DTACK RT_AD_LAT 55 D12 75 SA4 56 D14 76 D9 77 AUTO_CFG GROUND_LOGIC 38 SSFLAG RTAD0 57 18 TX/RX_B WC0 37 58 D11 78 WC4 19 WC2 39 RTAD3 59 D15 79 GROUND_XCVR 20 MEMOE 40 RTAD4 60 D10 80 CLK_SEL_0 15 16 17 31 36 TABLE 18A. BU-64703X3/4 "GULL WING" AND FLAT PACKAGE PIN FUNCTIONS PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION 1 L_BRO 21 N/C 41 D6 61 2 22 GROUND_XCVR 42 D1 62 BUSY RTACTIVE 3 T/R TX/RX_A 23 N/C 43 D4 63 HS_FAIL 4 N/C 24 RTAD2 44 RTADP 64 5 TX/RX_A 25 MSTCLR 45 RTAD1 65 RT_FAIL TX_INH 6 RT_AD_ERR SA3 26 D0 66 SRV_RQST 27 CLOCK_IN SA1 46 7 47 D2 67 GBR 8 N/C 28 MEMWR 48 D3 68 9 N/C 29 49 D5 69 10 +5.0 V_XCVR 30 DTREQ +3.3V_LOGIC ILLEGAL +3.3V_LOGIC 50 GROUND_LOGIC 70 GROUND_LOGIC 11 N/C 31 GROUND_LOGIC 51 +3.3V_LOGIC 71 BRO_ENA 12 SA2 32 52 D8 72 13 WC3 33 INCMD WC1 53 D7 73 DTGRT CLK_SEL_1 14 GROUND_LOGIC 34 MSG_ERR 54 D13 74 SA0 15 TX/RX_B 35 D12 75 SA4 16 N/C 36 DTACK RT_AD_LAT 55 56 D14 76 17 TX/RX_B WC0 37 57 D9 77 AUTO_CFG GROUND_LOGIC 38 SSFLAG RTAD0 58 D11 78 WC4 19 WC2 39 RTAD3 59 D15 79 GROUND_XCVR 20 MEMOE 40 RTAD4 60 D10 80 CLK_SEL_0 18 Data Device Corporation www.ddc-web.com 43 BU-64703 H-06/11-0 TABLE 19. BU-64703E8 SSRT-MARK3 (+3.3V) & TRANSFORMER EVALUATION BOARD PINOUTS MADE FROM 80-PIN, SSRT MARK3 BU-64703G8 P1 PIN # 80-PIN DEVICE PIN # SSRT MARK3 FUNCTION P2 PIN # 80-PIN DEVICE PIN # SSRT MARK3 FUNCTION 1 2 T/R 1 - - 2 1 BRO 2 - - 3 6 3 - STUB_TX/RX_B 4 7 RT_AD_ERR SA3 4 - 5 18 WC/MC/CWC0 5 22,31,50,70,79 STUB_TX/RX_B GND 6 13 WC/MC/CWC3 6 22,31,50,70,79 GND 7 19 WC/MC/CWC2 7 - STUB_TX/RX_B 8 12 SA2 8 - STUB_TX/RX_B 9 80 CLK_SEL_0 9 - - 10 22,31,50,70,79 GND 10 - - 11 22,31,50,70,79 GND 11 - +3.3V_XFMR_CT 12 22,31,50,70,79 GND 12 - +3.3V_XFMR_CT 13 77 GND_LOGIC 13 10 +3.3V_XCVR 14 78 WC/MC/CWC4 14 10 +3.3V_XCVR 15 75 SA4 15 - - 16 76 AUTO_CFG 16 - - 17 73 17 - STUB_TX/RX_A 18 74 CLK_SEL_1 SA0 18 - 19 71 BRO_ENA 19 22,31,50,70,79 STUB_TX/RX_A GND 20 72 22,31,50,70,79 GND 30,51,69 DTGRT +3.3V_Logic 20 21 21 - STUB_TX/RX_A +3.3V_Logic 22 - STUB_TX/RX_A 23 - - 24 - - 22 30,51,69 23 68 24 - ILLEGAL - 25 66 SRV_RQST 26 67 GBR 27 64 28 65 RTFAIL TX_INH 29 62 RTACTIVE 30 63 31 - HS_FAIL - 32 61 BUSY Data Device Corporation www.ddc-web.com 44 BU-64703 H-06/11-0 TABLE 19A. BU-64703E8 SSRT-MARK3 (+3.3V) & TRANSFORMER EVALUATION BOARD PINOUTS MADE FROM 80-PIN, SSRT MARK3 BU-64703G8 (CONT.) P3 PIN # 80-PIN DEVICE PIN # SSRT MARK3 FUNCTION P4 PIN # 80-PIN DEVICE PIN # SSRT MARK3 FUNCTION 1 14 GND_LOGIC 1 41 D06 2 20 - - 3 22,31,50,70,79 MEMOE GND 2 3 43 D04 4 - - 4 42 D01 5 30,51,69 +3.3V_LOGIC 5 45 RTAD1 6 30,51,69 +3.3V_LOGIC 6 44 RTADP 7 22,31,50,70,79 GND 7 47 D02 8 22,31,50,70,79 GND 8 46 D00 9 22,31,50,70,79 GND 9 49 D05 10 - - 10 48 D03 11 24 RTAD2 11 22,31,50,70,79 GND 12 22,31,50,70,79 GND 12 22,31,50,70,79 GND 13 25 30,51,69 +3.3V_LOGIC 14 26 MSTCLR CLOCK_IN 13 14 30,51,69 +3.3V_LOGIC 15 22,31,50,70,79 GND 15 52 D08 16 27 SA1 16 53 D07 17 28 MEMWR 17 54 D13 18 29 55 D12 19 30,51,69 DTREQ +3.3V_LOGIC 18 19 56 D14 20 30,51,69 +3.3V_LOGIC 20 57 D09 21 - - 21 58 D11 22 - - 22 59 D15 23 32 60 D10 24 33 INCMD WC/MC/CWC1 23 24 - - 25 34 MSG_ERR 26 35 27 36 DTACK RT_AD_LAT 28 37 29 38 SSFLAG RTAD0 30 39 RTAD3 31 - - 32 40 RTAD4 Data Device Corporation www.ddc-web.com 45 BU-64703 H-06/11-0 2 X 2.36 (59.94) REF. 2 X 1.88 (47.75) 0.02 4 X 0.890 (22.606) MAX. 4 X 0.060 (1.524) #60 #41 #40 #61 0.015 (0.381) TYP. 4 X 19 EQUAL SP @ 0.040 (1.016) = 0.760 (19.304) (TOL. NON-CUM.) TOP VIEW #21 #80 #1 #20 PIN NUMBERS FOR REFERENCE ONLY 0.500 (12.7) REF 4 X 0.200 (5.08) 0.008 (0.2032) 0.002 0.025 (0.635) PIN #1 DENOTED BY INDEX MARK 0.910 (23.114) MAX. 0.130 (3.302) MAX. 0.050 (1.27) SIDE VIEW Notes: 1) Dimensions are in inches (mm). 2) Tolerances = 0.005 inches unless otherwise specified. FIGURE 20. BU-64703FX FLAT PACKAGE MECHANICAL OUTLINE Data Device Corporation www.ddc-web.com 46 BU-64703 H-06/11-0 4 X 0.880 (22.35) REF #60 #41 #61 #40 0.015 (0.381) TYP. 4 X 19 EQUAL SP @ 0.040 (1.016) = 0.760 (19.304) (TOL. NON-CUM.) TOP VIEW #80 PIN #1 DENOTED BY INDEX MARK 4 X 0.060 (1.524) #21 #20 #1 PIN NUMBERS FOR REFERENCE ONLY 0.130 (3.302) MAX. PIN #1 DENOTED BY INDEX MARK 0.010 (0.254) MAX. 0.004 (0.102) 0.006 (0.152) +0.010 (+0.254) - 0.004 (- 0.102) 1.110 (28.194) 0.060 (1.524) MAX. 0.015 SIDE VIEW Notes: 1) Dimensions are in inches (mm). 2) Tolerances = 0.005 inches unless otherwise specified. FIGURE 21. BU-64703GX GULL WING PACKAGE MECHANICAL OUTLINE Data Device Corporation www.ddc-web.com 47 BU-64703 H-06/11-0 ORDERING INFORMATION BU-64703XX-XXXX Supplemental Process Requirements: Test Criteria: S = Pre-Cap Source Inspection L = 100% Pull Test Q = 100% Pull Test and Pre-Cap Source Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Inspection Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source Inspection and 100% Pull Test Blank = None of the Above 0 = Standard Testing 2 = MIL-STD-1760 Amplitude Compliant (Not available with Voltage/Transceiver Option 4, 9, & D) Process Requirements: Temperature Range(Note 2)/Data Requirements: Voltage/Transceiver Option: Package Type: Logic Voltage Product Type: 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 = = = = = = = = = = = = = = = = = = Standard DDC practices, no Burn-In (See Standard DDC Processing Table) MIL-PRF-38534 Compliant (Note 4) B (Note 1) MIL-PRF-38534 Compliant with PIND Testing (Note 4) MIL-PRF-38534 Compliant with Solder Dip (Note 4) MIL-PRF-38534 Compliant with PIND Testing and Solder Dip (Note 4) B (Note 1) with PIND Testing B (Note 1) with Solder Dip B (Note 1) with PIND Testing and Solder Dip Standard DDC Processing with Solder Dip, no Burn-In -55C to +125C -40C to +85C 0C to +70C -55C to +125C with Variables Test Data -40C to +85C with Variables Test Data Custom Part (Reserved) Custom Part (Reserved) 0C to +70C with Variables Test Data 3 = +5.0 Volts rise/fall times = 100 to 300 ns (-1553B) 4 = +5.0 Volts rise/fall times = 200 to 300 ns (-1553B & McAir Compatible)(Not available with test criteria option 2 "MIL-STD-1760 Amplitude Compliant") 8 = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B) (note 5) 9 = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible) (Not available with Test Criteria Option 2 "MIL-STD-1760 Amplitude Compliant") (note 5) C = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B) (note 6) D = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible. Note: Not available with Test Criteria Option 2 "MIL-STD-1760 Amplitude Compliant") (note 6) F = Flat Pack G = "Gull Wing" (Formed Lead) B = BGA Package (Consult factory) 3 = 3.3 Volt (+5.0V Tolerant I/O) BU-6470 = RT only with simple (non-processor) interface BU-64703E8-300 (Ordering information for SSRT-Mark3 (+3.3V) Transceiver Evaluation Board) Evaluation board intended to support customers who are interested in electrically connecting and evaluating the performance of the +3.3V SSRT Mark3 Notes: 1. Standard DDC Processing with burn-in and full temperature test--see STANDARD DDC PROCESSING TABLE. 2. Temperature range refers to "Case Temperature". 3. The above products contain tin-lead solder finish as applicable to solder dip requirements. Data Device Corporation www.ddc-web.com 4. MIL-PRF-38534 product grading is designated with the following dash numbers: Class H is a -11X, 13X, 14X, 15X, 41X, 43X, 44X, 45X Class G is a -21X, 23X, 24X, 25X, 51X, 53X, 54X, 55X Class D is a -31X, 33X, 34X, 35X, 81X, 83X, 84X, 85X 5. Transformer center-tap connected to +3.3V_XCVR, see FIGURE 15 (Obsolete) 6. Transformer center-tap connected to GND, see FIGURE 16 48 BU-64703 H-06/11-0 STANDARD DDC PROCESSING FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS MIL-STD-883 TEST METHOD(S) CONDITION(S) INSPECTION 2009, 2010, 2017, and 2032 -- SEAL 1014 A and C TEMPERATURE CYCLE 1010 C CONSTANT ACCELERATION 2001 1015 (note 1), 1030 (note 2) TABLE 1 BURN-IN 3000g Notes: 1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with MILSTD-883, Test Method 1015, Paragraph 3.2. Contact factory for details. 2. When applicable. The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our web site at www.ddc-web.com for the latest information. 105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2426 For Technical Support - 1-800-DDC-5757 ext. 7771 (R) I FI REG U ST RM Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com ERED DATA DEVICE CORPORATION REGISTERED TO ISO 9001:2000 FILE NO. A5976 H-06/11-0 49 PRINTED IN THE U.S.A. RECORD OF CHANGE For BU-64703 Data Sheet Revision F G H Date 6/2009 6/2010 6/2011 Pages 26 & 27 24, 26, & 44 25, 26, 28, 29, & 47 Description Replaced Tables 4 and 4a. Updated Figure 15 and Tables 4 & 19A Added new page 25 and Figure 16. Incremented all subsequent figure numbers. Updated Figure 17. Updated Table 4. Updated Figures 18 and 19. Added Transceiver Options "C" & "D" to ordering information.