1
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
AUGUST 2003
2003 Integrated Device Technology, Inc. DSC-6194/14c
IDT74SSTVF16859
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
13-BIT TO 26-BIT REGISTERED
BUFFER WITH SSTL I/O
DESCRIPTION:
The SSTVF16859 is a 13-bit to 26-bit registered buffer designed for
2.3V-2.7V VDD for PC1600 - PC2700 and 2.5V-2.7V VDD for PC3200, and
supports low standby operation. All data inputs and outputs are SSTL_2
level compatible with JEDEC standard for SSTL_2.
RESET is an LVCMOS input since it must operate predictably during the
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of RESET.
APPLICATIONS:
• Along with CSPT857C, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
FEATURES:
• 1:2 register buffer
• Meets or exceeds JEDEC standard SSTVF16859
• 2.3V to 2.7V Operation for PC1600, PC2100, and PC2700
• 2.5V to 2.7V Operation for PC3200
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
•RESET control compatible with LVCMOS levels
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in 56 pin VFQFPN and 64 pin TSSOP packages
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
51
48
49
45
35
R
1D
C1
16 Q1A
RESET
CLK
CLK
VREF
D1
TO 12 OTHER CHANNELS
32 Q1B
2
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
PIN CONFIGURATIONS
TSSOP
TOP VIEW
FUNCTION TABLE (1)
Input
RESET CLK CLK D Q Outputs
H↑↓ LL
H↑↓ HH
H L or H L or H X Qo(2)
LXX X L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2. Qo = Output level before the indicated steady-state conditions were established.
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Description Max. Unit
VDD or VDDQ Supply Voltage Range –0.5 to 3.6 V
VI(2) Input Voltage Range –0.5 to VDD +0.5 V
VO(3) Output Voltage Range –0.5 to VDDQ +0.5 V
IIK Input Clamp Current, VI < 0 –50 mA
IOK Output Clamp Current, ±50 mA
VO < 0 or VO > VDDQ
IOContinuous Output Current, ±50 mA
VO = 0 to VDDQ
VDD Continuous Current through each ±100 mA
VDD, VDDQ or GND
TSTG Storage Temperature Range –65 to +150 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. The output current will flow if the following conditions are observed:
a) Output in HIGH state
b) VO = VDDQ
VFQFPN
TOP VIEW
Q
12A
V
DD
Q
Q
8A
Q
11A
Q
10A
Q
9A
Q
13
A
GND
V
DDQ
V
DDQ
D
11
D
12
V
DD
D
13
56
43
Q6A
Q7A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13
B
VDD
Q
Q12B
Q11B
Q10B
Q9B
Q8B
1
14 D4
D5
D6
D7
RESET
D8
D9
D10
GND
CLK
CLK
VDDQ
VDD
VREF
42
29
V
DD
Q
D
1
Q
6B
Q
7B
V
DD
Q
Q
5B
Q
4B
Q
3B
Q
2B
Q
1B
D
2
V
DD
V
DD
Q
D
3
15
28
GND
Q13A
D1
Q12A
D2
GND
GND
VDDQ
VDDQ
D3
D4
D5
D6
D7
Q6A
Q7A
VDDQ
Q8A
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q11A
Q10A
Q9A
Q5A
Q4A
Q3A
Q2A
Q1A
GND
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q6B
Q7B
Q8B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
GND
GND
CLK
CLK
VDDQ
VDD
VREF
GND
GND
VDDQ
VDD
GND
VDDQ
3
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
PIN DESCRIPTION
Pin Names Description
Q1 - Q13 Data Output
GND Ground
VDDQ Output-stage drain power voltage
VDD Logic power voltage
RESET Asynchronous reset input - resets registers and disables data and clock differential input recievers
VREF Input reference voltage
CLK Positive master clock input
CLK Negative master clock input
D1 - D13 Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK
Center PAD Ground (MLF package only)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIK Control Inputs VDD = 2.3V, II= −18mA — — –1.2 V
VOH VDD = 2.3V to 2.7V, IOH = -100μAVDD – 0.2 — — V
VDD = 2.3V, IOH = -8mA 1.95 — —
VOL VDD = 2.3V to 2.7V, IOL = 100μA — — 0.2 V
VDD = 2.3V, IOL = 8mA — — 0.35
IIAll Inputs VDD = 2.7V,VI = VDD or GND — — ±5μA
IDD Static Standby IO = 0, VDD = 2.7V, RESET = GN D — — 0.01 m A
Static Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) ——20
Dynamic Operating (Clock Only) IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),—6—μA/Clock
CLK and CLK Switching 50% Duty Cycle. MHz
IDDD Dynamic Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),—43—μA/Clock
(Per Each Data Input)(1) CLK and CLK Switching 50% Duty Cycle. One Data Input MHz/Data
Switching at Half Clock Frequency, 50% Duty Cycle. Input
Data Inputs VDD = 2.5V, VI = VREF ± 310mV 2 — 3
CICLK and CLK VICR = 1.25V, VI (PP) = 360mV 2 — 3 p F
RESET VI = VDD or GND 2 — 3
NOTE:
1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC1600 -
PC2700
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V
4
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIK Control Inputs VDD = 2.5V, II= −18mA — — –1.2 V
VOH VDD = 2.5V to 2.7V, IOH = -100μAVDD – 0.2 — — V
VDD = 2.5V, IOH = -8mA 1.95 — —
VOL VDD = 2.5V to 2.7V, IOL = 100μA — — 0.2 V
VDD = 2.5V, IOL = 8mA — — 0.35
IIAll Inputs VDD = 2.7V,VI = VDD or GND — — ±5μA
IDD Static Standby IO = 0, VDD = 2.7V, RESET = GN D — — 0.01 m A
Static Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) ——20
Dynamic Operating (Clock Only) IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),—6—μA/Clock
CLK and CLK Switching 50% Duty Cycle. MHz
IDDD Dynamic Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = V IH (AC) or VIL (AC),—43—μA/Clock
(Per Each Data Input)(1) CLK and CLK Switching 50% Duty Cycle. One Data Input MHz/Data
Switching at Half Clock Frequency, 50% Duty Cycle. Input
Data Inputs VDD = 2.6V, VI = VREF ± 310mV 2 — 3
CICLK and CLK VICR = 1.3V, VI (PP) = 360mV 2 — 3 p F
RESET VI = VDD or GND 2 — 3
NOTE:
1. Power dissipation levels will allow operation at DDR400 speeds without excessive die temperature.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 2.6V ±0.1V, VDDQ = 2.6V ±0.1V
OPERATING CHARACTERISTICS, TA = 25ºC (1)
Symbol Parameter Min. Typ.(1) Max. Unit
VDD Supply Voltage VDDQ — 2.7 V
VDDQ Output Supply Voltage PC1600-PC2700 2.3 2.5 2.7 V
PC3200 2.5 2.6 2.7
VREF Reference Voltage (VREF= VDDQ/2) PC1600-PC2700 1.15 1.25 1.35 V
PC3200 1.25 1.3 1.35
VTT Termination Voltage VREF– 40mV VREF VREF+ 40mV V
VIInput Voltage 0 — VDD V
VIH AC High-Level Input Voltage Data Inputs VREF+ 310mV — — V
VIL AC Low-Level Input Voltage Data Inputs — — VREF– 310mV V
VIH DC High-Level Input Voltage Data Inputs VREF+ 150mV — — V
VIL DC Low-Level Input Voltage Data Inputs — — VREF– 150mV V
VIH High-Level Input Voltage RESET 1.7 — — V
VIL Low-Level Input Voltage RESET — — 0.7 V
VICR Common-Mode Input Range CLK, CLK 0.97 — 1.53 V
VI (PP) Peak-to-Peak Input Voltage CLK, CLK 360 — — mV
IOH High-Level Output Current — — – 16 mA
IOL Low-Level Output Current — — 16
TAOperating Free-Air Temperature 0 — +70 °C
NOTE:
1. The RESET input of the device must be held at VDD or GND to ensure proper device operation.
5
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE PC1600 - PC2700 PC3200
Symbol Parameter Min. Max. Min. Max. Unit
CLOCK Clock Frequency — 2 0 0 — 2 2 0 MHz
tw Pulse Duration, CLK, CLK HIGH or LOW 2.5 — 2.5 — ns
tACT Differential Inputs Active Time(1) —22—22ns
tINACT Differential Inputs Inactive Time(2) —22—22ns
tSU Setup Time, Fast Slew Rate(3, 5) Data Before CLK↑, CLK↓0.65 — 0.65 — ns
Setup Time, Slow Slew Rate(4, 5) 0.75 — 0.75 — ns
tHHold Time, Fast Slew Rate(3,5) Data Before CLK↑, CLK ↓0.75 — 0.65 — ns
Hold Time, Slow Slew Rate(2,5) 0.9 — 0.8 — ns
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
PC1600 - PC2700 PC3200
Symbol Parameter Min. Max. Min. Max. Unit
fMAX 200 — 220 — MHz
tPDM CLK and CLK to Q 1.1 2.6 1.1 2.4 ns
tPDMSS CLK and CLK to Q (simultaneous switching) — 2.9 — 2.68 ns
tPHL RESET to Q — 5 — 5 ns
NOTES:
1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH.
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW.
3. For data signal input slew rate is ≥1V/ns.
4. For data signal input slew rate is ≥0.5V/ns and <1V/ns.
5. CLK, CLK signal input slew rates are ≥1V/ns.
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COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
TEST CIRCUITS AND WAVEFORMS
FOR PC1600 - PC2700, VDD = 2.5V ± 0.2V
FOR PC3200, VDD = 2.6V ± 0.1V
Voltage Waveforms - Pulse Duration
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPDM is tPD with one output switching. tPDMSS is tPD with all outputs switching.
Load Circuit
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
Voltage and Current Waveforms
Inputs Active and Inactive Times
Timing
Input VICR VI(PP)
tPLH tPHL
Output
VOH
VOL
VICR
VTT VTT
VOH
VOL
VIH
VIL
tPHL
VDD/2
VTT
LVCMOS
RESET
Input
Output
VREF
VIH
VIL
VREF
Input
tW
VREF
VIH
VIL
VREF
Input
VICR VI(PP)
tSU tH
Timing
Input
From output
under test Test Point
LVCMOS
RESET
Input VDD/2
VDD
tINACT tACT
IDD
VDD/2
90%
0V
(see note 2)
10%
VTT
CL=30pF
(see note 1)
RL=50Ω
7
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
ORDERING INFORMATION
IDT74SSTVF XXX XX
Package
Device Type
PA
PAG
NL
NLG
Thin Shrink Small Outline Package
TSSOP - Green
Thermally Enhanced Plastic Very Fine Pitch
Quad Flat No Lead Package
VFQFPN - Green
13-Bit to 26-Bit Registered Buffer with SSTL I/O
0°C to +70°C (Commercial)
859
16
XX
Family
Double-Density
XX
Process
Blank
CORPORATE HEADQUARTERS for SALES:
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
