CFR-E3-U1 - Lattice Semiconductor Corporation

LatticeECP3 Family Handbook

HB1009 Version 05.2, July 2013

May 2013

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Section I. LatticeECP3 Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU Blocks ........................................................................................................................................................ 2-2

Slice .......................................................................................................................................................... 2-3

Modes of Operation................................................................................................................................... 2-5

Routing............................................................................................................................................................... 2-6

sysCLOCK PLLs and DLLs................................................................................................................................ 2-6

General Purpose PLL................................................................................................................................ 2-6

Delay Locked Loops (DLL)........................................................................................................................ 2-7

PLL/DLL Cascading ................................................................................................................................ 2-10

PLL/DLL PIO Input Pin Connections....................................................................................................... 2-10

Clock Dividers .................................................................................................................................................. 2-10

Clock Distribution Network ............................................................................................................................... 2-11

Primary Clock Sources............................................................................................................................ 2-11

Primary Clock Routing ............................................................................................................................ 2-13

Dynamic Clock Control (DCC) ................................................................................................................ 2-13

Dynamic Clock Select (DCS) .................................................................................................................. 2-13

Secondary Clock/Control Sources .......................................................................................................... 2-14

Secondary Clock/Control Routing ........................................................................................................... 2-14

Slice Clock Selection............................................................................................................................... 2-16

Edge Clock Sources................................................................................................................................ 2-17

Edge Clock Routing ................................................................................................................................ 2-17

sysMEM Memory ............................................................................................................................................. 2-19

sysMEM Memory Block........................................................................................................................... 2-19

Bus Size Matching .................................................................................................................................. 2-19

RAM Initialization and ROM Operation ................................................................................................... 2-19

Memory Cascading ................................................................................................................................. 2-19

Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-20

Memory Core Reset................................................................................................................................ 2-20

sysDSP™ Slice ................................................................................................................................................ 2-20

sysDSP Slice Approach Compared to General DSP .............................................................................. 2-20

LatticeECP3 sysDSP Slice Architecture Features ........................................................................................... 2-21

MULT DSP Element................................................................................................................................ 2-24

MAC DSP Element.................................................................................................................................. 2-25

MMAC DSP Element............................................................................................................................... 2-26

MULTADDSUB DSP Element................................................................................................................. 2-27

MULTADDSUBSUM DSP Element......................................................................................................... 2-28

Advanced sysDSP Slice Features ................................................................................................................... 2-29

Cascading ............................................................................................................................................... 2-29

Addition ................................................................................................................................................... 2-29

Rounding................................................................................................................................................. 2-29

ALU Flags ............................................................................................................................................... 2-30

Clock, Clock Enable and Reset Resources ............................................................................................ 2-30

Resources Available in the LatticeECP3 Family ..................................................................................... 2-30

LatticeECP3 Family Handbook

Table of Contents

LatticeECP3 Family Handbook

Programmable I/O Cells (PIC) ......................................................................................................................... 2-31

PIO ................................................................................................................................................................... 2-32

Input Register Block................................................................................................................................ 2-32

Output Register Block ............................................................................................................................. 2-34

Tristate Register Block............................................................................................................................ 2-35

ISI Calibration.......................................................................................................................................... 2-35

Control Logic Block ................................................................................................................................. 2-36

DDR Memory Support...................................................................................................................................... 2-36

Left and Right Edges............................................................................................................................... 2-36

Bottom Edge ........................................................................................................................................... 2-36

Top Edge................................................................................................................................................. 2-36

DLL Calibrated DQS Delay Block ........................................................................................................... 2-36

Polarity Control Logic .............................................................................................................................. 2-39

DDR3 Memory Support........................................................................................................................... 2-39

sysI/O Buffer .................................................................................................................................................... 2-40

sysI/O Buffer Banks ................................................................................................................................ 2-40

Typical sysI/O I/O Behavior During Power-up......................................................................................... 2-42

Supported sysI/O Standards ................................................................................................................... 2-42

On-Chip Programmable Termination ...................................................................................................... 2-43

Equalization Filter.................................................................................................................................... 2-44

Hot Socketing.......................................................................................................................................... 2-44

SERDES and PCS (Physical Coding Sublayer)............................................................................................... 2-44

SERDES Block........................................................................................................................................ 2-46

PCS......................................................................................................................................................... 2-46

SCI (SERDES Client Interface) Bus........................................................................................................ 2-46

Flexible Quad SERDES Architecture ............................................................................................................... 2-47

IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-48

Device Configuration........................................................................................................................................ 2-48

Soft Error Detect (SED) Support ............................................................................................................. 2-49

External Resistor..................................................................................................................................... 2-49

On-Chip Oscillator................................................................................................................................... 2-49

Density Shifting ................................................................................................................................................ 2-50

DC and Switching Characteristics

Absolute Maximum Ratings, , ............................................................................................................................. 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

Hot Socketing Specifications.............................................................................................................................. 3-2

Hot Socketing Requirements ............................................................................................................................. 3-2

ESD Performance .............................................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-3

LatticeECP3 Supply Current (Standby).............................................................................................................. 3-4

SERDES Power Supply Requirements.............................................................................................................. 3-5

sysI/O Recommended Operating Conditions..................................................................................................... 3-6

sysI/O Single-Ended DC Electrical Characteristics............................................................................................ 3-7

sysI/O Differential Electrical Characteristics ...................................................................................................... 3-8

LVDS25..................................................................................................................................................... 3-8

Differential HSTL and SSTL...................................................................................................................... 3-8

LVDS25E .................................................................................................................................................. 3-9

LVCMOS33D ............................................................................................................................................ 3-9

BLVDS25 ................................................................................................................................................ 3-10

LVPECL33 .............................................................................................................................................. 3-11

RSDS25E................................................................................................................................................ 3-12

MLVDS25................................................................................................................................................ 3-13

Typical Building Block Function Performance.................................................................................................. 3-14

Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-14

Table of Contents

LatticeECP3 Family Handbook

Derating Timing Tables .................................................................................................................................... 3-15

LatticeECP3 External Switching Characteristics ............................................................................................. 3-16

LatticeECP3 Internal Switching Characteristics .............................................................................................. 3-25

Timing Diagrams .............................................................................................................................................. 3-27

LatticeECP3 Family Timing Adders ................................................................................................................. 3-29

LatticeECP3 Maximum I/O Buffer Speed ........................................................................................................ 3-32

sysCLOCK PLL Timing .................................................................................................................................... 3-34

DLL Timing....................................................................................................................................................... 3-35

SERDES High-Speed Data Transmitter........................................................................................................... 3-36

SERDES/PCS Block Latency........................................................................................................................... 3-38

SERDES High Speed Data Receiver............................................................................................................... 3-39

Input Data Jitter Tolerance...................................................................................................................... 3-39

SERDES External Reference Clock........................................................................................................ 3-41

PCI Express Electrical and Timing Characteristics .......................................................................................... 3-44

AC and DC Characteristics ..................................................................................................................... 3-44

XAUI/Serial Rapid I/O Type 3/CPRI LV E.30 Electrical and Timing 

Characteristics ............................................................................................................................................ 3-45

AC and DC Characteristics ..................................................................................................................... 3-45

Serial Rapid I/O Type 2/CPRI LV E.24 Electrical and Timing Characteristics ................................................. 3-47

AC and DC Characteristics ..................................................................................................................... 3-47

Gigabit Ethernet/Serial Rapid I/O Type 1/SGMII/CPRI LV E.12 Electrical and Timing Characteristics ........... 3-48

AC and DC Characteristics ..................................................................................................................... 3-48

SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics........................... 3-49

AC and DC Characteristics ..................................................................................................................... 3-49

HDMI (High-Definition Multimedia Interface) Electrical and Timing 

Characteristics ............................................................................................................................................ 3-50

AC and DC Characteristics ..................................................................................................................... 3-50

LatticeECP3 sysCONFIG Port Timing Specifications ...................................................................................... 3-52

JTAG Port Timing Specifications ..................................................................................................................... 3-58

Switching Test Conditions................................................................................................................................ 3-59

sysI/O Differential Electrical Characteristics .................................................................................................... 3-60

Transition Reduced LVDS (TRLVDS DC Specification) ......................................................................... 3-60

Mini LVDS ............................................................................................................................................... 3-60

Point-to-Point LVDS (PPLVDS) .............................................................................................................. 3-61

RSDS ...................................................................................................................................................... 3-61

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-4

Pin Information Summary (Cont.)....................................................................................................................... 4-6

Pin Information Summary (Cont.)....................................................................................................................... 4-7

Pin Information Summary (Cont.)....................................................................................................................... 4-9

Package Pinout Information ............................................................................................................................. 4-10

Thermal Management ...................................................................................................................................... 4-10

For Further Information ........................................................................................................................... 4-10

Ordering Information

LatticeECP3 Part Number Description............................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

LatticeECP3 Devices, Green and Lead-Free Packaging .......................................................................... 5-2

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

Revision History

Table of Contents

LatticeECP3 Family Handbook

Section II. LatticeECP3 Family Technical Notes

LatticeECP3 SERDES/PCS Usage Guide

Introduction ........................................................................................................................................................ 8-1

Features ............................................................................................................................................................. 8-1

New Features Over LatticeECP2M™ SERDES/PCS ............................................................................... 8-1

Using This Technical Note ................................................................................................................................. 8-2

Standards Supported ......................................................................................................................................... 8-2

Architecture Overview ........................................................................................................................................ 8-3

PCS Quads and Channels........................................................................................................................ 8-4

Per Channel SERDES/PCS and FPGA Interface Ports............................................................................ 8-4

Detailed Channel Block Diagram .............................................................................................................. 8-5

Clocks and Resets .................................................................................................................................... 8-6

Transmit Data Bus .................................................................................................................................... 8-6

Receive Data Bus ..................................................................................................................................... 8-7

Mode-Specific Control/Status Signal Descriptions.................................................................................... 8-8

SERDES/PCS ........................................................................................................................................... 8-9

I/O Descriptions....................................................................................................................................... 8-10

SERDES/PCS Functional Description ............................................................................................................. 8-13

SERDES .......................................................................................................................................................... 8-13

Equalizer ................................................................................................................................................. 8-13

Pre-Emphasis.......................................................................................................................................... 8-13

Reference Clocks.................................................................................................................................... 8-14

SERDES Clock Architecture ................................................................................................................... 8-14

Rate Modes............................................................................................................................................. 8-15

Reference Clock from an FPGA Core..................................................................................................... 8-16

Full Data, Div 2 and Div 11 Data Rates .................................................................................................. 8-17

Dynamic Switching Between Full Rate and Half Rate (DIV2) ................................................................. 8-18

Reference Clock Sources ....................................................................................................................... 8-18

Spread Spectrum Clocking (SSC) Support ............................................................................................. 8-18

Loss of Signal.......................................................................................................................................... 8-19

Loss Of Lock ........................................................................................................................................... 8-19

TX Lane-to-Lane Skew ........................................................................................................................... 8-19

SERDES PCS Configuration Setup ........................................................................................................ 8-20

Auto-Configuration File ........................................................................................................................... 8-20

Transmit Data.......................................................................................................................................... 8-20

Receive Data........................................................................................................................................... 8-20

8b10b Decoder........................................................................................................................................ 8-21

External Link State Machine Option........................................................................................................ 8-21

Idle Insert for Gigabit Ethernet Mode ...................................................................................................... 8-22

Clock Tolerance Compensation .............................................................................................................. 8-22

Calculating Minimum Interpacket Gap .................................................................................................... 8-26

PCS Module Generation in IPexpress .................................................................................................... 8-28

8-Bit and 10-Bit SERDES-Only Modes ................................................................................................... 8-40

Generic 8b10b Mode............................................................................................................................... 8-40

LatticeECP3 PCS in Gigabit Ethernet and SGMII Modes ....................................................................... 8-42

XAUI Mode.............................................................................................................................................. 8-43

LatticeECP3 PCS in PCI Express Revision 1.1 (2.5Gpbs) Mode ........................................................... 8-44

PCI Express Beacon Support ................................................................................................................. 8-48

SDI (SMPTE) Mode ................................................................................................................................ 8-49

Serial RapidIO (SRIO) Mode................................................................................................................... 8-50

Serial Digital Video and Out-Of-Band Low Speed SERDES Operation.................................................. 8-51

Open Base Station Architecture Initiative (OBSAI) ................................................................................. 8-52

Common Public Radio Interface (CPRI) ................................................................................................. 8-53

SONET/SDH ........................................................................................................................................... 8-55

Table of Contents

LatticeECP3 Family Handbook

FPGA Interface Clocks............................................................................................................................ 8-56

Case I_a: 8/10-Bit, CTC FIFO and RX/TX FIFOs Not Bypassed............................................................ 8-59

Case I_b: 8/10-Bit, CTC FIFO Bypassed ................................................................................................ 8-60

Case I_c: 8/10-Bit, RX/TX FIFO Bypassed ............................................................................................. 8-61

Case I_d: 8/10-Bit, CTC FIFO and RX/TX FIFOs Bypassed .................................................................. 8-62

Case II_a: 16/20-bit, CTC FIFO and RX/TX FIFOs NOT Bypassed ....................................................... 8-63

Case II_b: 16/20-bit, CTC FIFO Bypassed ............................................................................................. 8-64

SERDES/PCS Block Latency........................................................................................................................... 8-65

SERDES Client Interface ........................................................................................................................ 8-66

Interrupts and Status............................................................................................................................... 8-68

SERDES Debug Capabilities ........................................................................................................................... 8-69

PCS Loopback Modes ............................................................................................................................ 8-69

ORCAstra................................................................................................................................................ 8-71

Other Design Considerations .................................................................................................................. 8-74

16/20-Bit Word Alignment ....................................................................................................................... 8-74

SERDES/PCS RESET ..................................................................................................................................... 8-79

Reset Sequence and Reset State Diagram ............................................................................................ 8-79

Reset Sequence Generation................................................................................................................... 8-79

Lock Status Signals Definitions............................................................................................................... 8-79

TX Reset Sequence ................................................................................................................................ 8-79

RX Reset Sequence................................................................................................................................ 8-79

References....................................................................................................................................................... 8-82

Technical Support Assistance.......................................................................................................................... 8-82

Revision History ............................................................................................................................................... 8-82

Appendix A. Configuration Registers ............................................................................................................... 8-85

Quad Registers Overview ....................................................................................................................... 8-85

Per Quad PCS Control Registers Details................................................................................................ 8-85

Per Quad PCS Control Registers Details................................................................................................ 8-87

Per Quad Reset and Clock Control Registers Details............................................................................. 8-89

Per Quad PCS Status Registers Details ................................................................................................. 8-89

Per Quad SERDES Status Registers Details.......................................................................................... 8-91

Channel Registers Overview................................................................................................................... 8-92

Per Channel PCS Control Registers Details........................................................................................... 8-93

Per Channel SERDES Control Registers Details....................................................................................8-97

Per Channel Reset and Clock Control Registers Details ...................................................................... 8-100

Per Channel PCS Status Registers Details .......................................................................................... 8-101

Per Channel SERDES Status Registers Details ................................................................................... 8-102

Appendix B. Register Settings for Various Standards.................................................................................... 8-104

Per Channel Register Settings for Various Standards .......................................................................... 8-104

Per Quad Register Settings for Various Standards............................................................................... 8-104

Appendix C. Attribute Cross Reference Table ............................................................................................... 8-105

Appendix D. Lattice Diamond Overview......................................................................................................... 8-110

Converting an ispLEVER Project to Lattice Diamond ........................................................................... 8-110

Importing an ispLEVER Design Project ................................................................................................ 8-110

Adjusting PCS Modules ........................................................................................................................ 8-110

Regenerate PCS Modules .................................................................................................................... 8-110

Using IPexpress with Lattice Diamond.................................................................................................. 8-111

Creating a New Simulation Project Using Simulation Wizard ............................................................... 8-112

LatticeECP3 sysIO Usage Guide

Introduction ........................................................................................................................................................ 9-1

sysIO Buffer Overview ....................................................................................................................................... 9-1

Supported sysIO Standards ............................................................................................................................... 9-1

sysIO Banking Scheme...................................................................................................................................... 9-3

VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 9-4

Table of Contents

LatticeECP3 Family Handbook

VCCAUX (3.3V) ........................................................................................................................................... 9-5

VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 9-5

Input Reference Voltage (VREF1, VREF2) .................................................................................................. 9-5

VREF1 for DDR Memory Interface............................................................................................................ 9-5

VTT Termination Voltage .......................................................................................................................... 9-5

Hot Socketing Support .............................................................................................................................. 9-5

Mixed Voltage Support in a Bank.............................................................................................................. 9-6

sysIO Standards Supported Per Bank ...................................................................................................... 9-7

sysIO Buffer Configurations ............................................................................................................................... 9-8

Bus Maintenance Circuit ........................................................................................................................... 9-8

Programmable Drive ................................................................................................................................. 9-8

Programmable Slew Rate ......................................................................................................................... 9-8

Open Drain Control ................................................................................................................................... 9-8

Differential SSTL and HSTL Support ........................................................................................................ 9-9

PCI Support with Programmable PCICLAMP ........................................................................................... 9-9

Differential I/O Support.............................................................................................................................. 9-9

Differential SSTL and HSTL...................................................................................................................... 9-9

Differential LVCMOS33............................................................................................................................. 9-9

GTL+ Input Support .................................................................................................................................. 9-9

On-Chip Termination............................................................................................................................... 9-10

Equalization Setting ................................................................................................................................ 9-10

Software sysIO Attributes................................................................................................................................. 9-10

IO_TYPE ................................................................................................................................................. 9-10

OPENDRAIN........................................................................................................................................... 9-11

DRIVE ..................................................................................................................................................... 9-12

DIFFDRIVE ............................................................................................................................................. 9-12

MULTDRIVE ........................................................................................................................................... 9-12

TERMINATEVTT..................................................................................................................................... 9-13

DIFFRESISTOR...................................................................................................................................... 9-13

EQ_CAL .................................................................................................................................................. 9-13

PULLMODE ............................................................................................................................................ 9-13

PCICLAMP.............................................................................................................................................. 9-13

SLEWRATE ............................................................................................................................................ 9-14

INBUF ..................................................................................................................................................... 9-14

FIXEDDELAY.......................................................................................................................................... 9-14

DIN/DOUT............................................................................................................................................... 9-14

LOC......................................................................................................................................................... 9-14

Design Considerations and Usage................................................................................................................... 9-14

Banking Rules ......................................................................................................................................... 9-14

Differential I/O Rules ............................................................................................................................... 9-15

Technical Support Assistance.......................................................................................................................... 9-15

Revision History ............................................................................................................................................... 9-16

Appendix A. HDL Attributes ............................................................................................................................. 9-17

VHDL Synplify Pro .................................................................................................................................. 9-17

Verilog Synplicity..................................................................................................................................... 9-20

Appendix B. sysIO Attributes Using the ispLEVER Design Planner User Interface......................................... 9-22

Appendix C. sysIO Attributes Using the Diamond Spreadsheet View User Interface...................................... 9-24

LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide

Introduction ...................................................................................................................................................... 10-1

Clock/Control Distribution Network .................................................................................................................. 10-1

LatticeECP3 Top-Level View ........................................................................................................................... 10-1

Primary Clocks ................................................................................................................................................. 10-2

Secondary Clocks ............................................................................................................................................ 10-2

Edge Clocks ..................................................................................................................................................... 10-2

Table of Contents

LatticeECP3 Family Handbook

General Routing for Clocks .............................................................................................................................. 10-4

Additional Connectivity for Dedicated Clock Resources ......................................................................... 10-4

Very Small Clock Domains...................................................................................................................... 10-5

Static Timing Analysis of General Routing Clocks .................................................................................. 10-5

Specifying Clocks in the Design Tools ............................................................................................................. 10-5

Global Primary Clock and Quadrant Primary Clock ......................................................................................... 10-6

Global Primary Clock .............................................................................................................................. 10-6

Primary-Pure and Primary-DCS.............................................................................................................. 10-6

Quadrant Primary Clock.......................................................................................................................... 10-6

Global Secondary Clock and Regional Secondary Clocks .............................................................................. 10-7

Global Secondary Clocks........................................................................................................................ 10-7

Regional Secondary Clocks .................................................................................................................... 10-7

Secondary Region Clock Preferencing ................................................................................................... 10-7

sysCLOCK™ PLL ............................................................................................................................................ 10-8

Functional Description...................................................................................................................................... 10-9

PLL Divider and Delay Blocks................................................................................................................. 10-9

PLL Inputs and Outputs ................................................................................................................................. 10-10

CLKI Input ............................................................................................................................................. 10-10

RST Input .............................................................................................................................................. 10-10

RSTK Input............................................................................................................................................ 10-11

CLKFB Input.......................................................................................................................................... 10-11

CLKOP Output ...................................................................................................................................... 10-11

CLKOS Output with Phase and Duty Cycle Select ............................................................................... 10-11

CLKOK Output with Lower Frequency .................................................................................................. 10-11

CLKOK2 Output .................................................................................................................................... 10-11

LOCK Output......................................................................................................................................... 10-12

Dynamic Phase and Dynamic Duty Cycle Adjustment.......................................................................... 10-12

Dynamic Phase Adjustment/Duty Cycle Select.............................................................................................. 10-12

Fine Delay Ports............................................................................................................................................. 10-13

LatticeECP3 PLL Modules ............................................................................................................................. 10-13

LatticeECP3 PLL Library Definition................................................................................................................ 10-14

EPLLD Design Migration from LatticeECP2 to LatticeECP3................................................................. 10-14

Dynamic Phase/Duty Mode................................................................................................................... 10-14

PLL Usage in IPexpress................................................................................................................................. 10-15

Configuration Tab.................................................................................................................................. 10-16

PLL Modes of Operation ................................................................................................................................ 10-18

PLL Clock Injection Removal ................................................................................................................ 10-18

PLL Clock Phase Adjustment................................................................................................................ 10-19

IPexpress Output ........................................................................................................................................... 10-19

Notes on PLL Usage ...................................................................................................................................... 10-20

sysCLOCK DLL.............................................................................................................................................. 10-20

DLL Overview........................................................................................................................................ 10-20

DLL Inputs and Outputs ........................................................................................................................ 10-20

DLL Attributes ....................................................................................................................................... 10-22

DLL Library Definitions.......................................................................................................................... 10-22

DLL Library Element I/Os...................................................................................................................... 10-23

DLL Modes of Operation....................................................................................................................... 10-23

DLL Usage in IPexpress ....................................................................................................................... 10-24

DLLDEL (Slave Delay Line) .................................................................................................................. 10-27

DQSDLL and DQSDEL .................................................................................................................................. 10-29

Clock Dividers (CLKDIV)................................................................................................................................ 10-29

CLKDIV Library Definition ..................................................................................................................... 10-29

CLKDIV Declaration in VHDL Source Code..........................................................................................10-30

CLKDIV Usage with Verilog - Example ................................................................................................. 10-31

Table of Contents

LatticeECP3 Family Handbook

CLKDIV Example Circuits ..................................................................................................................... 10-31

Reset Behavior...................................................................................................................................... 10-32

Release Behavior.................................................................................................................................. 10-32

CLKDIV Inputs-to-Outputs Delay Matching........................................................................................... 10-33

DCS (Dynamic Clock Select) ......................................................................................................................... 10-33

DCS Library Definition........................................................................................................................... 10-33

DCS Timing Diagrams .......................................................................................................................... 10-34

DCS Usage with VHDL - Example ........................................................................................................ 10-35

DCS Usage with Verilog - Example ...................................................................................................... 10-36

Oscillator (OSCF).................................................................................................................................. 10-36

OSC Library Symbol (OSCF) ................................................................................................................ 10-37

OSC Usage with VHDL - Example........................................................................................................ 10-37

OSC Usage with Verilog - Example ...................................................................................................... 10-37

Setting Clock Preferences..................................................................................................................... 10-37

Power Supplies .............................................................................................................................................. 10-37

PLL/DLL Names and Preferred Pads............................................................................................................. 10-37

Technical Support Assistance........................................................................................................................ 10-38

Revision History ............................................................................................................................................. 10-39

Appendix A. Primary Clock Sources and Distribution .................................................................................... 10-40

Appendix B. PLL, CLKIDV and ECLK Locations and Connectivity ................................................................ 10-41

Appendix C. Lattice Diamond Usage Overview ............................................................................................. 10-42

Converting an ispLEVER Project to Lattice Diamond ........................................................................... 10-42

Importing an ispLEVER Design Project ................................................................................................ 10-42

Adjusting PCS Modules ........................................................................................................................ 10-42

Regenerate PCS Modules .................................................................................................................... 10-42

Using IPexpress with Lattice Diamond.................................................................................................. 10-43

Creating a New Simulation Project Using Simulation Wizard ............................................................... 10-44

LatticeECP3 Memory Usage Guide

Introduction ...................................................................................................................................................... 11-1

Utilizing IPexpress............................................................................................................................................ 11-1

IPexpress Flow........................................................................................................................................ 11-2

Utilizing the PMI ............................................................................................................................................... 11-4

Memory Modules.............................................................................................................................................. 11-5

Single-Port RAM (RAM_DQ) – EBR Based ............................................................................................11-5

True Dual-Port RAM (RAM_DP_TRUE) – EBR Based......................................................................... 11-11

Pseudo Dual-Port RAM (RAM_DP) – EBR Based................................................................................ 11-19

Read Only Memory (ROM) – EBR Based............................................................................................. 11-22

First In First Out (FIFO) Memory.................................................................................................................... 11-26

Dual Clock First-In-First-Out (FIFO_DC) Memory.......................................................................................... 11-32

FIFO_DC Flags ..................................................................................................................................... 11-32

Distributed Single-Port RAM (Distributed_SPRAM) – PFU-Based ................................................................ 11-41

Distributed Dual-Port RAM (Distributed_DPRAM) – PFU-Based................................................................... 11-43

Distributed ROM (Distributed_ROM) – PFU-Based ....................................................................................... 11-45

Initializing Memory ......................................................................................................................................... 11-47

Initialization File Formats ...................................................................................................................... 11-47

Technical Support Assistance........................................................................................................................ 11-49

Revision History ............................................................................................................................................. 11-49

Appendix A. Attribute Definitions.................................................................................................................... 11-50

DATA_WIDTH....................................................................................................................................... 11-50

REGMODE............................................................................................................................................ 11-50

CSDECODE.......................................................................................................................................... 11-50

WRITEMODE........................................................................................................................................ 11-50

Table of Contents

LatticeECP3 Family Handbook

LatticeECP3 High-Speed I/O Interface

Introduction ...................................................................................................................................................... 12-1

External Interface Description .......................................................................................................................... 12-2

High-Speed I/O Interface Building Blocks ........................................................................................................ 12-3

ECLK....................................................................................................................................................... 12-4

SCLK....................................................................................................................................................... 12-4

DQS Lane ............................................................................................................................................... 12-4

PLL.......................................................................................................................................................... 12-5

DLL.......................................................................................................................................................... 12-5

DQSDLL.................................................................................................................................................. 12-5

Input DDR (IDDR) ................................................................................................................................... 12-5

Output DDR (ODDR)............................................................................................................................... 12-5

CLKDIV ................................................................................................................................................... 12-5

DELAY .................................................................................................................................................... 12-5

ECLK/SCLK vs. DQS Lanes ................................................................................................................... 12-5

Building Generic High-Speed Interfaces .......................................................................................................... 12-6

Types of High-Speed DDR Interfaces..................................................................................................... 12-6

Using IPexpress to Build High-Speed DDR Interfaces .................................................................................. 12-10

Building SDR Modules .......................................................................................................................... 12-11

Building DDR Generic Modules ............................................................................................................ 12-13

High-Speed DDR Interface Details ................................................................................................................ 12-17

GIREG_RX.SCLK ................................................................................................................................. 12-18

GDDRX1_RX.ECLK.Aligned................................................................................................................. 12-19

GDDRX1_RX.ECLK.Centered .............................................................................................................. 12-19

GDDRX1_RX.SCLK.Aligned................................................................................................................. 12-20

GDDRX1_RX.SCLK.PLL.Aligned ......................................................................................................... 12-21

GDDRX1_RX.SCLK.Centered .............................................................................................................. 12-22

GDDRX1_RX.DQS.Aligned .................................................................................................................. 12-22

GDDRX1_RX.DQS.Centered................................................................................................................ 12-23

GDDRX2_RX.ECLK.Aligned................................................................................................................. 12-24

GDDRX2_RX.ECLK.Aligned (No CLKDIV)........................................................................................... 12-26

GDDRX2_RX.ECLK.Centered .............................................................................................................. 12-27

GDDRX2_RX.DQS.Aligned .................................................................................................................. 12-28

GDDRX2_RX.DQS.Centered................................................................................................................ 12-29

GDDRX2_RX.ECLK.Dynamic............................................................................................................... 12-30

GDDRX2_RX.DQS.Dynamic ................................................................................................................ 12-31

GDDRX2_RX.PLL.Dynamic.................................................................................................................. 12-32

GOREG_TX.SCLK................................................................................................................................ 12-33

GDDRX1_TX.SCLK.Centered .............................................................................................................. 12-34

GDDRX1_TX.SCLK.Aligned ................................................................................................................. 12-36

GDDRX1_TX.DQS.Centered ................................................................................................................ 12-39

GDDRX2_TX.Aligned............................................................................................................................ 12-40

GDDRX2_TX.DQSDLL.Centered ......................................................................................................... 12-40

GDDRX2_TX.PLL.Centered ................................................................................................................. 12-42

7:1 LVDS Implementation ..................................................................................................................... 12-43

Generic DDR Design Guidelines.................................................................................................................... 12-43

Placement Guidelines for High-Speed DDR Interfaces ........................................................................ 12-43

High-Speed Clock Bridge (“EA” Devices) ............................................................................................. 12-44

DQ-DQS Grouping Rules...................................................................................................................... 12-44

I/O Logic (IOL) Site Types/Names ........................................................................................................ 12-45

Design Rules for Fitting Multiple Interfaces into One Device ................................................................ 12-47

Clocking Guidelines for Generic DDR Interfaces ..................................................................................12-48

Common Software Errors and Solutions............................................................................................... 12-49

Timing Analysis for High-Speed DDR Interfaces .................................................................................. 12-50

Table of Contents

LatticeECP3 Family Handbook

DDR/DDR2/DDR3 SDRAM Interfaces Overview ........................................................................................... 12-58

Implementing DDR/DDR2/DDR3 Memory Interfaces ....................................................................................12-60

DQS Grouping....................................................................................................................................... 12-61

Memory Read Implementation .............................................................................................................. 12-62

Memory Write Implementation .............................................................................................................. 12-65

DDR3 Clock Synchronization Module ................................................................................................... 12-74

DDR Memory Interface Generation Using IPexpress .................................................................................... 12-77

DDR Memory DQ/DQS Design Rules and Guidelines...................................................................................12-81

DDR/DDR2 Pinout Guidelines ....................................................................................................................... 12-82

DDR3 Termination Guidelines ....................................................................................................................... 12-83

Termination for DQ, DQS and DM ........................................................................................................ 12-83

Termination for CK ................................................................................................................................ 12-83

Termination for Address, Commands and Controls .............................................................................. 12-83

Termination for DDR3 DIMM................................................................................................................. 12-84

DDR3 Interface without Termination .............................................................................................................. 12-84

DQ, DQS and DM without Parallel VTT Termination ............................................................................ 12-84

Address, Command and Control Signals without Parallel VTT Termination......................................... 12-84

Layout Considerations for DDR3 ................................................................................................................... 12-84

DDR3 Pinout Guidelines ................................................................................................................................ 12-85

Pin Placement Considerations for Improved Noise Immunity ........................................................................12-86

DDR Software Primitives and Attributes ........................................................................................................ 12-88

DQSDLLB ............................................................................................................................................. 12-89

DQSBUFE............................................................................................................................................. 12-92

DQSBUFG ............................................................................................................................................ 12-92

DQSBUFE1........................................................................................................................................... 12-93

DQSBUF Logic Primitives for DDR Memory Interfaces ........................................................................ 12-93

DQSBUFD............................................................................................................................................. 12-95

DQSBUFF............................................................................................................................................. 12-96

Input DDR Primitives............................................................................................................................. 12-97

Output DDR Primitives ........................................................................................................................ 12-110

Interface ID Attribute ........................................................................................................................... 12-121

ISI Calibration...................................................................................................................................... 12-122

Migrating Designs from LatticeECP3 “E” to “EA” ......................................................................................... 12-123

Migrating Designs from ispLEVER 7.2 SP2 to ispLEVER 8.0...................................................................... 12-125

Technical Support Assistance...................................................................................................................... 12-126

Revision History ........................................................................................................................................... 12-127

Appendix A. Building DDR Interfaces Using IPexpress in ispLEVER 7.2 SP2 ............................................ 12-128

DDR Generic....................................................................................................................................... 12-129

Configuration Tab................................................................................................................................ 12-130

DDR_MEM .......................................................................................................................................... 12-131

Configuration Tab................................................................................................................................ 12-132

Appendix B. Building SDR/DDR Interfaces Using IPexpress in Diamond ................................................... 12-134

Building SDR Modules ........................................................................................................................ 12-134

Building DDR Generic Modules .......................................................................................................... 12-136

Building DDR Memory Interfaces........................................................................................................ 12-140

Power Consumption and Management for LatticeECP3 Devices

Introduction ...................................................................................................................................................... 13-1

Power Supply Sequencing and Hot Socketing................................................................................................. 13-1

Recommended Power-up Sequence ............................................................................................................... 13-1

Power Calculator Hardware Assumptions........................................................................................................ 13-1

Power Calculator.............................................................................................................................................. 13-1

Power Calculator and Power Equations.................................................................................................. 13-2

Typical and Worst Case Process Power/ICC.......................................................................................... 13-3

Junction Temperature ............................................................................................................................. 13-3

Table of Contents

LatticeECP3 Family Handbook

Maximum Safe Ambient Temperature .................................................................................................... 13-3

Operating Temperature Range ............................................................................................................... 13-3

Dynamic Power Multiplier (DPM) ............................................................................................................ 13-4

Power Budgeting..................................................................................................................................... 13-4

Activity Factor Calculation................................................................................................................................ 13-4

Thermal Impedance and Airflow ............................................................................................................. 13-5

Reducing Power Consumption......................................................................................................................... 13-5

Power Calculator Assumptions ........................................................................................................................ 13-6

Technical Support Assistance.......................................................................................................................... 13-6

Revision History ............................................................................................................................................... 13-6

LatticeECP3 sysDSP Usage Guide

Introduction ...................................................................................................................................................... 14-1

sysDSP Slice Hardware ................................................................................................................................... 14-1

sysDSP Slice Software .................................................................................................................................... 14-2

Overview ................................................................................................................................................. 14-2

Targeting sysDSP Slices Using IPexpress ............................................................................................. 14-2

Targeting the sysDSP Slice by Inference.............................................................................................. 14-12

Targeting the sysDSP Slice Using ispLeverDSP with Simulink ............................................................ 14-13

Targeting the sysDSP Slice by Instantiating Primitives......................................................................... 14-14

sysDSP in the Report Files ............................................................................................................................ 14-15

Map Report ........................................................................................................................................... 14-15

PAR Report ........................................................................................................................................... 14-16

Trace Report ......................................................................................................................................... 14-17

sysDSP in the ispLEVER Design Planner...................................................................................................... 14-18

Pre-Mapped View.................................................................................................................................. 14-18

Floorplan View ...................................................................................................................................... 14-18

Advanced Features of the sysDSP Slice ....................................................................................................... 14-19

IPexpress Slice Module.................................................................................................................................. 14-23

Rounding........................................................................................................................................................ 14-26

Example 1: Rounding Toward Zero ...................................................................................................... 14-27

Example 2: Rounding to Positive Infinity............................................................................................... 14-27

Example 3: Rounding to Negative Infinity ............................................................................................. 14-28

Example 4: Rounding Away from Zero ................................................................................................. 14-28

Example 5: Rounding Toward Even...................................................................................................... 14-29

Example 6: Rounding Toward Odd ....................................................................................................... 14-29

sysDSP Slice Control Signal and Data Signal Descriptions........................................................................... 14-30

Technical Support Assistance........................................................................................................................ 14-30

Revision History ............................................................................................................................................. 14-30

Appendix A. DSP Primitives........................................................................................................................... 14-31

Appendix B. Using IPexpress for Diamond .................................................................................................... 14-36

Invoking IPexpress for Diamond ........................................................................................................... 14-36

sysDSP in Diamond .............................................................................................................................. 14-47

LatticeECP3 sysCONFIG Usage Guide

Introduction ...................................................................................................................................................... 15-1

General Configuration Flow ............................................................................................................................. 15-2

Configuration Pins............................................................................................................................................ 15-2

Configuration Process and Flow ...................................................................................................................... 15-4

Power-up Sequence................................................................................................................................ 15-4

Initialization ............................................................................................................................................. 15-5

Loading the Configuration Memory ......................................................................................................... 15-5

Wake-up.................................................................................................................................................. 15-6

Clearing the Configuration Memory and Re-initialization ........................................................................ 15-6

Reconfiguration Priority........................................................................................................................... 15-6

Table of Contents

LatticeECP3 Family Handbook

FPGA Configuration Control Pin Definitions .................................................................................................... 15-7

Configuration Pin Management............................................................................................................... 15-7

Dedicated Control Pins ........................................................................................................................... 15-7

JTAG Pins ............................................................................................................................................... 15-7

Dual-Purpose sysCONFIG Pins............................................................................................................ 15-11

Configuration Modes ...................................................................................................................................... 15-14

SPI Interface ......................................................................................................................................... 15-14

SPI Master Multiboot (SPIm) Mode....................................................................................................... 15-16

Slave SPI (SSPI)................................................................................................................................... 15-18

Slave Serial Configuration Mode (SCM) ............................................................................................... 15-20

Slave Parallel Mode (SPCM) ................................................................................................................ 15-20

JTAG Mode (IEEE 1149.1 and IEEE 1532) .......................................................................................... 15-22

Bitstream Generation Software Usage........................................................................................................... 15-23

Configuration Options ........................................................................................................................... 15-23

Device Wake-Up ............................................................................................................................................ 15-25

Synchronizing Wake-Up........................................................................................................................ 15-26

Bitstream Generation Property Options ......................................................................................................... 15-28

Run DRC (T/F)...................................................................................................................................... 15-28

Create Bitfile (T/F)................................................................................................................................. 15-28

Bitstream File Formats .......................................................................................................................... 15-28

No Header (T/F) .................................................................................................................................... 15-28

Bitstream Encryption/Decryption Flow ........................................................................................................... 15-28

Encrypting the Bitstream ....................................................................................................................... 15-28

Programming the 128-bit Key ............................................................................................................... 15-30

Verifying a Configuration....................................................................................................................... 15-32

File Formats ................................................................................................................................................... 15-33

Decryption Flow .................................................................................................................................... 15-37

Combining Configuration Modes.................................................................................................................... 15-38

Multiple FPGAs, One SPI Flash............................................................................................................ 15-38

Chain Mode Options ...................................................................................................................................... 15-39

References..................................................................................................................................................... 15-40

Technical Support Assistance........................................................................................................................ 15-40

Revision History ............................................................................................................................................. 15-41

Appendix A. Configuration Memory Requirements ........................................................................................ 15-42

Appendix B. Lattice Diamond Usage Overview ............................................................................................. 15-44

Converting an ispLEVER Project to Lattice Diamond ........................................................................... 15-44

Importing an ispLEVER Design Project ................................................................................................ 15-44

Adjusting PCS Modules ........................................................................................................................ 15-44

Regenerate PCS Modules .................................................................................................................... 15-44

Using IPexpress with Lattice Diamond.................................................................................................. 15-45

Creating a New Simulation Project Using Simulation Wizard ............................................................... 15-46

Setting Global Preferences in Diamond................................................................................................ 15-46

Setting Bitstream Generation Options in Diamond ............................................................................... 15-48

Setting Security Options in Diamond .................................................................................................... 15-50

LatticeECP3 Soft Error Detection (SED) Usage Guide

Introduction ...................................................................................................................................................... 16-1

SED Overview.................................................................................................................................................. 16-1

Hardware Description....................................................................................................................................... 16-2

Signal Descriptions .......................................................................................................................................... 16-2

SEDCLK.................................................................................................................................................. 16-2

SEDENABLE........................................................................................................................................... 16-3

SEDCLKOUT .......................................................................................................................................... 16-3

SEDSTART ............................................................................................................................................. 16-4

SEDFRCERR.......................................................................................................................................... 16-4

Table of Contents

LatticeECP3 Family Handbook

SEDINPROG........................................................................................................................................... 16-4

SEDDONE .............................................................................................................................................. 16-4

SEDERR ................................................................................................................................................. 16-4

AUTODONE............................................................................................................................................ 16-4

MCCLK_freq Attribute ............................................................................................................................. 16-4

SED Flow ......................................................................................................................................................... 16-5

SED Run Time ................................................................................................................................................. 16-6

Sample Code ................................................................................................................................................... 16-7

VHDL Example........................................................................................................................................ 16-7

Verilog Example ...................................................................................................................................... 16-8

Technical Support Assistance.......................................................................................................................... 16-9

Revision History ............................................................................................................................................... 16-9

LatticeECP3 and LatticeECP2M High-Speed Backplane Measurements

Introduction ...................................................................................................................................................... 17-1

Eye Diagram Experiment ................................................................................................................................. 17-1

Backplane Specifications ........................................................................................................................ 17-2

Test Setup Parameters ........................................................................................................................... 17-2

Eye Diagram Measurements................................................................................................................... 17-2

Results and Conclusion .......................................................................................................................... 17-5

Data Rate Experiment...................................................................................................................................... 17-5

Backplane Specifications ........................................................................................................................ 17-5

Test Setup Parameters ........................................................................................................................... 17-5

Data Rate Measurements ....................................................................................................................... 17-6

Results and Conclusions......................................................................................................................... 17-6

Conclusions and Design Guidelines ................................................................................................................ 17-6

References....................................................................................................................................................... 17-7

Technical Support Assistance.......................................................................................................................... 17-7

Revision History ............................................................................................................................................... 17-7

Introduction ...................................................................................................................................................... 18-1

LatticeECP3 Hardware Checklist

Power Supplies ................................................................................................................................................ 18-2

LatticeECP3 SERDES/PCS Power Supplies ................................................................................................... 18-2

Power Estimation ............................................................................................................................................. 18-3

Configuration Considerations........................................................................................................................... 18-3

I/O Pin Assignments......................................................................................................................................... 18-4

Dedicated FPGA Inputs (Non-configuration).................................................................................................... 18-4

Pinout Considerations ...................................................................................................................................... 18-4

LVDS Pin Assignments .................................................................................................................................... 18-5

HSTL and SSTL Pin Assignments ................................................................................................................... 18-5

XRES Pin ......................................................................................................................................................... 18-5

SERDES Pin Considerations ........................................................................................................................... 18-5

Technical Support Assistance.......................................................................................................................... 18-8

Revision History ............................................................................................................................................... 18-8

Section III. LatticeECP3 Family Handbook Revision History

Revision History ............................................................................................................................................... 19-1

Section I. LatticeECP3 Family Data Sheet

DS1021 Version 02.3EA, June 2013

www.latticesemi.com 1-1 DS1021 Introduction_01.6

February 2012 Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

Higher Logic Density for Increased System

Integration

• 17K to 149K LUTs

• 116 to 586 I/Os

Embedded SERDES

• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit

SERDES, and 8-bit SERDES modes

• Data Rates 230 Mbps to 3.2 Gbps per channel

for all other protocols

• Up to 16 channels per device: PCI Express,

SONET/SDH, Ethernet (1GbE, SGMII, XAUI),

CPRI, SMPTE 3G and Serial RapidIO

sysDSP™

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply

and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

– Half 36x36, two 18x18 or four 9x9 multipliers

– Advanced 18x36 MAC and 18x18 Multiply-

Multiply-Accumulate (MMAC) operations

Flexible Memory Resources

• Up to 6.85Mbits sysMEM™ Embedded Block

RAM (EBR)

• 36K to 303K bits distributed RAM

sysCLOCK Analog PLLs and DLLs

• Two DLLs and up to ten PLLs per device

Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated read/write levelling functionality

• Dedicated gearing logic

• Source synchronous standards support

– ADC/DAC, 7:1 LVDS, XGMII

– High Speed ADC/DAC devices

• Dedicated DDR/DDR2/DDR3 memory with DQS

support

• Optional Inter-Symbol Interference (ISI) 

correction on outputs

Programmable sysI/O™ Buffer Supports

Wide Range of Interfaces

• On-chip termination

• Optional equalization filter on inputs

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 33/25/18/15 I, II

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL

• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

Flexible Device Configuration

• Dedicated bank for configuration I/Os

• SPI boot flash interface

• Dual-boot images supported

• Slave SPI

• TransFR™ I/O for simple field updates

• Soft Error Detect embedded macro

System Level Support

• IEEE 1149.1 and IEEE 1532 compliant

• Reveal Logic Analyzer

• ORCAstra FPGA configuration utility

• On-chip oscillator for initialization & general use

• 1.2V core power supply

Table 1-1. LatticeECP3™ Family Selection Guide

Device ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150

LUTs (K) 17336792149

sysMEM Blocks (18Kbits) 38 72 240 240 372

Embedded Memory (Kbits) 700 1327 4420 4420 6850

Distributed RAM Bits (Kbits) 36 68 145 188 303

18X18 Multipliers 24 64 128 128 320

SERDES (Quad) 11334

PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2

Packages and SERDES Channels/ I/O Combinations

328 csBGA (10x10 mm) 2 / 116

256 ftBGA (17x17 mm) 4 / 133 4 / 133

484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295

672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380

1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586

LatticeECP3 Family Data Sheet

Introduction

1-2

Introduction

LatticeECP3 Family Data Sheet

Introduction

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor-

mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous

interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture

and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to

586 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel

I/O standards.

The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices

utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-

uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source

synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and

dual-boot capabilities.

The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad

range of interface standards, including DDR3, XGMII and 7:1 LVDS.

The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-

ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular

data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-

sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various

forms of media.

The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-

bility, bit-stream encryption, and TransFR field upgrade features.

The Lattice Diamond™ and ispLEVER® design software allows large complex designs to be efficiently imple-

mented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic

synthesis tools. Diamond and ispLEVER tools use the synthesis tool output along with the constraints from its floor

planning tools to place and route the design in the LatticeECP3 device. The tools extract the timing from the routing

and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP3 family. By using these

configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their

design, increasing their productivity.

www.latticesemi.com 2-1 DS1021 Architecture_02.1

June 2013 Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Architecture Overview

Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-

DSP™ Digital Signal Processing slices, as shown in Figure 2-1. The LatticeECP3-150 has four rows of DSP slices;

all other LatticeECP3 devices have two rows of DSP slices. In addition, the LatticeECP3 family contains SERDES

Quads on the bottom of the device.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF

block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for

flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-

dimensional array. Only one type of block is used per row.

The LatticeECP3 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated

18Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or

ROM. In addition, LatticeECP3 devices contain up to two rows of DSP slices. Each DSP slice has multipliers and

adder/accumulators, which are the building blocks for complex signal processing capabilities.

The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES (Serializer / Deserializer) channels. Each

SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each

group of four SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a quad. The func-

tionality of the SERDES/PCS quads can be controlled by memory cells set during device configuration or by regis-

ters that are addressable during device operation. The registers in every quad can be programmed via the

SERDES Client Interface (SCI). These quads (up to four) are located at the bottom of the devices.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the

LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of I/O standards.

In addition, a separate I/O bank is provided for the programming interfaces. 50% of the PIO pairs on the left and

right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engi-

neered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1

LVDS, along with memory interfaces including DDR3.

The LatticeECP3 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the

device is configured, it enters into user mode with these registers SET/RESET according to the configuration set-

ting, allowing the device entering to a known state for predictable system function.

Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two

Delay Locked Loops (DLLs) and up to ten Phase Locked Loops (PLLs). The PLL and DLL blocks are located at the

end of the EBR/DSP rows.

The configuration block that supports features such as configuration bit-stream decryption, transparent updates

and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family sup-

ports a sysCONFIG™ port located in the corner between banks one and two, which allows for serial or parallel

device configuration.

In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error

detect capability. The LatticeECP3 devices use 1.2V as their core voltage.

LatticeECP3 Family Data Sheet

Architecture

2-2

Architecture

LatticeECP3 Family Data Sheet

Figure 2-1. Simplified Block Diagram, LatticeECP3-35 Device (Top Level)

PFU Blocks

The core of the LatticeECP3 device consists of PFU blocks, which are provided in two forms, the PFU and PFF.

The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF

blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-

der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2-2. Each slice contains

two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs

associated with each PFU block.

SERDES/PCS

CH 3

SERDES/PCS

CH 2

SERDES/PCS

CH 1

SERDES/PCS

CH 0

sysIO

Bank

sysIO

Bank

sysIO

Bank 0

sysIO

Bank 1

sysIO Bank 3 sysIO Bank 6

Configuration Logic:

Dual-boot, Encryption

and Transparent Updates

On-chip Oscillator

Pre-engineered Source

Synchronous Support:

DDR3 - 800Mbps

Generic - Up to 1Gbps

Flexible Routing:

Optimized for speed

and routability

Flexible sysIO:

LVCMOS, HSTL,

SSTL, LVDS

Up to 486 I/Os

Programmable

Function Units:

Up to 149K LUTs

sysCLOCK

PLLs & DLLs:

Frequency Synthesis

and Clock Alignment

Enhanced DSP

Slices: Multiply,

Accumulate and ALU

JTAG

sysMEM Block

RAM: 18Kbit

3.2Gbps SERDES

Note: There is no Bank 4 or Bank 5 in LatticeECP3 devices.

2-3

Architecture

LatticeECP3 Family Data Sheet

Figure 2-2. PFU Diagram

Slice

Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For

PFUs, Slice 0 through Slice 2 can be configured as distributed memory, a capability not available in the PFF.

Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they

enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as

LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/

asynchronous), clock select, chip-select and wider RAM/ROM functions.

Table 2-1. Resources and Modes Available per Slice

Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-

tive/negative and edge triggered or level sensitive clocks.

Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent

slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 10

input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.

Slice

PFU BLock PFF Block

Resources Modes Resources Modes

Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 1 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 3 2 LUT4s Logic, ROM 2 LUT4s Logic, ROM

Slice 0

LUT4 &

CARRY

LUT4 &

CARRY

D D

Slice 1

LUT4 &

CARRY

LUT4 &

CARRY

Slice 2

LUT4 &

CARRY

LUT4 &

CARRY

From

Routing

Slice 3

LUT4 LUT4

D D D D

FF FF FF FF FF FF

2-4

Architecture

LatticeECP3 Family Data Sheet

Figure 2-3. Slice Diagram

Table 2-2. Slice Signal Descriptions

Function Type Signal Names Description

Input Data signal A0, B0, C0, D0 Inputs to LUT4

Input Data signal A1, B1, C1, D1 Inputs to LUT4

Input Multi-purpose M0 Multipurpose Input

Input Multi-purpose M1 Multipurpose Input

Input Control signal CE Clock Enable

Input Control signal LSR Local Set/Reset

Input Control signal CLK System Clock

Input Inter-PFU signal FC Fast Carry-in1

Input Inter-slice signal FXA Intermediate signal to generate LUT6 and LUT7

Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7

Output Data signals F0, F1 LUT4 output register bypass signals

Output Data signals Q0, Q1 Register outputs

Output Data signals OFX0 Output of a LUT5 MUX

Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice

Output Inter-PFU signal FCO Slice 2 of each PFU is the fast carry chain output1

1. See Figure 2-3 for connection details.

2. Requires two PFUs.

LUT4 &

CARRY*

SLICE

FF*

OFX0

LUT4 &

CARRY*

FF*

OFX1

F/SUM

F/SUM D

FCI From Different Slice/PFU

FCO To Different Slice/PFU

LUT5

Mux

From

Routing

For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:

WCK is CLK

WRE is from LSR

DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2

WAD [A:D] is a 4-bit address from slice 2 LUT input

* Not in Slice 3

CLK

LSR

FXB

FXA

2-5

Architecture

LatticeECP3 Family Data Sheet

Modes of Operation

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.

Logic Mode

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16

possible input combinations. Any four input logic functions can be generated by programming this lookup table.

Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as

LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four

slices.

Ripple Mode

Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following func-

tions can be implemented by each slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/Subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Up/Down counter with asynchronous clear

• Up/Down counter with preload (sync)

• Ripple mode multiplier building block

• Multiplier support

• Comparator functions of A and B inputs

– A greater-than-or-equal-to B

– A not-equal-to B

– A less-than-or-equal-to B

Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-

figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-

ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.

RAM Mode

In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and

Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. A 16x2-bit pseudo

dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice

as the read-only port.

LatticeECP3 devices support distributed memory initialization.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of slices required to implement different distributed RAM primitives. For more information about

using RAM in LatticeECP3 devices, please see TN1179, LatticeECP3 Memory Usage Guide.

Table 2-3. Number of Slices Required to Implement Distributed RAM

SPR 16X4 PDPR 16X4

Number of slices 3 3

Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

2-6

Architecture

LatticeECP3 Family Data Sheet

ROM Mode

ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished

through the programming interface during PFU configuration.

For more information, please refer to TN1179, LatticeECP3 Memory Usage Guide.

Routing

There are many resources provided in the LatticeECP3 devices to route signals individually or as busses with

related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)

segments.

The LatticeECP3 family has an enhanced routing architecture that produces a compact design. The Diamond and

ispLEVER design software tool suites take the output of the synthesis tool and places and routes the design.

sysCLOCK PLLs and DLLs

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The devices in the LatticeECP3 family

support two to ten full-featured General Purpose PLLs.

General Purpose PLL

The architecture of the PLL is shown in Figure 2-4. A description of the PLL functionality follows.

CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the

Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP, CLKOS or from a user clock

pin/logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre-

quency.

Both the input path and feedback signals enter the Phase Frequency Detect Block (PFD) which detects first for the

frequency, and then the phase, of the CLKI and CLKFB are the same which then drives the Voltage Controlled

Oscillator (VCO) block. In this block the difference between the input path and feedback signals is used to control

the frequency and phase of the oscillator. A LOCK signal is generated by the VCO to indicate that the VCO has

locked onto the input clock signal. In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and

not relock until the tLOCK parameter has been satisfied.

The output of the VCO then enters the CLKOP divider. The CLKOP divider allows the VCO to operate at higher fre-

quencies than the clock output (CLKOP), thereby increasing the frequency range. The Phase/Duty Cycle/Duty Trim

block adjusts the phase and duty cycle of the CLKOS signal. The phase/duty cycle setting can be pre-programmed

or dynamically adjusted. A secondary divider takes the CLKOP or CLKOS signal and uses it to derive lower fre-

quency outputs (CLKOK).

The primary output from the CLKOP divider (CLKOP) along with the outputs from the secondary dividers (CLKOK

and CLKOK2) and Phase/Duty select (CLKOS) are fed to the clock distribution network.

The PLL allows two methods for adjusting the phase of signal. The first is referred to as Fine Delay Adjustment.

This inserts up to 16 nominal 125ps delays to be applied to the secondary PLL output. The number of steps may

be set statically or from the FPGA logic. The second method is referred to as Coarse Phase Adjustment. This

allows the phase of the rising and falling edge of the secondary PLL output to be adjusted in 22.5 degree steps.

The number of steps may be set statically or from the FPGA logic.

2-7

Architecture

LatticeECP3 Family Data Sheet

Figure 2-4. General Purpose PLL Diagram

Table 2-4 provides a description of the signals in the PLL blocks.

Table 2-4. PLL Blocks Signal Descriptions

Delay Locked Loops (DLL)

In addition to PLLs, the LatticeECP3 family of devices has two DLLs per device.

CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes

block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference

input of the Phase Detector (PD) input mux. The reference signal for the PD can also be generated from the Delay

Chain signals. The feedback input to the PD is generated from the CLKFB pin or from a tapped signal from the

Delay chain.

The PD produces a binary number proportional to the phase and frequency difference between the reference and

feedback signals. Based on these inputs, the ALU determines the correct digital control codes to send to the delay

Signal I/O Description

CLKI I Clock input from external pin or routing

CLKFB I PLL feedback input from CLKOP, CLKOS, or from a user clock (pin or logic)

RST I “1” to reset PLL counters, VCO, charge pumps and M-dividers

RSTK I “1” to reset K-divider

WRDEL I DPA Fine Delay Adjust input

CLKOS O PLL output to clock tree (phase shifted/duty cycle changed)

CLKOP O PLL output to clock tree (no phase shift)

CLKOK O PLL output to clock tree through secondary clock divider

CLKOK2 O PLL output to clock tree (CLKOP divided by 3)

LOCK O “1” indicates PLL LOCK to CLKI

FDA [3:0] I Dynamic fine delay adjustment on CLKOS output

DRPAI[3:0] I Dynamic coarse phase shift, rising edge setting

DFPAI[3:0] I Dynamic coarse phase shift, falling edge setting

CLKFB

Divider

RST

CLKFB

CLKI

LOCK

CLKOP

CLKOS

RSTK

WRDEL

FDA[3:0]

CLKOK2

CLKOK

CLKI

Divider

PFD VCO/

Loop Filter

CLKOP

Divider

Phase/

Duty Cycle/

Duty Trim

CLKOK

Divider

Lock

Detect

DRPAI[3:0]

DFPAI[3:0]

2-8

Architecture

LatticeECP3 Family Data Sheet

chain in order to better match the reference and feedback signals. This digital code from the ALU is also transmit-

ted via the Digital Control bus (DCNTL) bus to its associated Slave Delay lines (two per DLL). The ALUHOLD input

allows the user to suspend the ALU output at its current value. The UDDCNTL signal allows the user to latch the

current value on the DCNTL bus.

The DLL has two clock outputs, CLKOP and CLKOS. These outputs can individually select one of the outputs from

the tapped delay line. The CLKOS has optional fine delay shift and divider blocks to allow this output to be further

modified, if required. The fine delay shift block allows the CLKOS output to phase shifted a further 45, 22.5 or 11.25

degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with optional duty cycle

correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK output signal is

asserted when the DLL is locked. Figure 2-5 shows the DLL block diagram and Table 2-5 provides a description of

the DLL inputs and outputs.

The user can configure the DLL for many common functions such as time reference delay mode and clock injection

removal mode. Lattice provides primitives in its design tools for these functions.

Figure 2-5. Delay Locked Loop Diagram (DLL)

CLKOP

CLKOS

LOCK

CLKFB

CLKI

ALUHOLD

DCNTL[5:0]*

GRAYO[5:0]

INCO

UDDCNTL

Phase

Detector

Delay3

Delay2

Delay1

Delay0

Delay4

Reference

Feedback

÷4

÷2

÷4

÷2

RSTN

(from routing

or external pin)

from CLKOP (DLL

internal), from clock net

(CLKOP) or from a user

clock (pin or logic)

Arithmetic

Logic Unit

Lock

Detect

Digital

Control

Output

Delay Chain

Output

Muxes

Duty

Cycle

50%

Duty

Cycle

50%

INCI

GRAYI[5:0]

DIFF

* This signal is not user accessible. This can only be used to feed the slave delay line.

2-9

Architecture

LatticeECP3 Family Data Sheet

Table 2-5. DLL Signals

LatticeECP3 devices have two general DLLs and four Slave Delay lines, two per DLL. The DLLs are in the lowest

EBR row and located adjacent to the EBR. Each DLL replaces one EBR block. One Slave Delay line is placed adja-

cent to the DLL and the duplicate Slave Delay line (in Figure 2-6) for the DLL is placed in the I/O ring between

Banks 6 and 7 and Banks 2 and 3.

The outputs from the DLL and Slave Delay lines are fed to the clock distribution network.

For more information, please see TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide.

Figure 2-6. Top-Level Block Diagram, High-Speed DLL and Slave Delay Line

Signal I/O Description

CLKI I Clock input from external pin or routing

CLKFB I DLL feed input from DLL output, clock net, routing or external pin

RSTN I Active low synchronous reset

ALUHOLD I Active high freezes the ALU

UDDCNTL I Synchronous enable signal (hold high for two cycles) from routing

CLKOP O The primary clock output

CLKOS O The secondary clock output with fine delay shift and/or division by 2 or by 4

LOCK O Active high phase lock indicator

INCI I Incremental indicator from another DLL via CIB.

GRAYI[5:0] I Gray-coded digital control bus from another DLL in time reference mode.

DIFF O Difference indicator when DCNTL is difference than the internal setting and update is needed.

INCO O Incremental indicator to other DLLs via CIB.

GRAYO[5:0] O Gray-coded digital control bus to other DLLs via CIB

CLKOP

CLKOS

LOCK

GRAY_OUT[5:0]

INC_OUT

DIFF

DCNTL[5:0]*

CLKO (to edge clock

muxes as CLKINDEL)

Slave Delay Line

LatticeECP3

High-Speed DLL

DCNTL[5:0]

CLKI

HOLD

GRAY_IN[5:0]

INC_IN

RSTN

GSRN

UDDCNTL

DCPS[5:0]

TPIO0 (L) OR TPIO1 (R)

GPLL_PIO

CIB (DATA)

CIB (CLK)

GDLL_PIO

Top ECLK1 (L) OR Top ECLK2 (R)

FB CIB (CLK)

Internal from CLKOP

GDLLFB_PIO

ECLK1

CLKFB

CLKI

* This signal is not user accessible. It can only be used to feed the slave delay line.

2-10

Architecture

LatticeECP3 Family Data Sheet

PLL/DLL Cascading

LatticeECP3 devices have been designed to allow certain combinations of PLL and DLL cascading. The allowable

combinations are:

• PLL to PLL supported

• PLL to DLL supported

The DLLs in the LatticeECP3 are used to shift the clock in relation to the data for source synchronous inputs. PLLs

are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL

blocks allows applications to utilize the unique benefits of both DLLs and PLLs.

For further information about the DLL, please see the list of technical documentation at the end of this data sheet.

PLL/DLL PIO Input Pin Connections

All LatticeECP3 devices contains two DLLs and up to ten PLLs, arranged in quadrants. If a PLL and a DLL are next

to each other, they share input pins as shown in the Figure 2-7.

Figure 2-7. Sharing of PIO Pins by PLLs and DLLs in LatticeECP3 Devices

Clock Dividers

LatticeECP3 devices have two clock dividers, one on the left side and one on the right side of the device. These are

intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or

÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock

based on the release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, the Slave

Delay lines, routing or from an external clock input. The clock divider outputs serve as primary clock sources and

feed into the clock distribution network. The Reset (RST) control signal resets input and asynchronously forces all

outputs to low. The RELEASE signal releases outputs synchronously to the input clock. For further information on

clock dividers, please see TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide. Figure 2-8 shows

the clock divider connections.

PLL

DLL

DLL_PIO

PLL_PIO

Note: Not every PLL has an associated DLL.

2-11

Architecture

LatticeECP3 Family Data Sheet

Figure 2-8. Clock Divider Connections

Clock Distribution Network

LatticeECP3 devices have eight quadrant-based primary clocks and eight secondary clock/control sources. Two

high performance edge clocks are available on the top, left, and right edges of the device to support high speed

interfaces. These clock sources are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These clock

sources are fed throughout the chip via a clock distribution system.

Primary Clock Sources

LatticeECP3 devices derive clocks from six primary source types: PLL outputs, DLL outputs, CLKDIV outputs, ded-

icated clock inputs, routing and SERDES Quads. LatticeECP3 devices have two to ten sysCLOCK PLLs and two

DLLs, located on the left and right sides of the device. There are six dedicated clock inputs: two on the top side, two

on the left side and two on the right side of the device. Figures 2-9, 2-10 and 2-11 show the primary clock sources

for LatticeECP3 devices.

Figure 2-9. Primary Clock Sources for LatticeECP3-17

RST

RELEASE

÷1

÷2

÷4

÷8

ECLK2

CLKOP (PLL)

CLKOP (DLL)

ECLK1

CLKDIV

Primary Clock Sources

to Eight Quadrant Clock Selection

From Routing

PLL

DLL

PLL Input

Note: Clock inputs can be configured in differential or single-ended mode.

DLL Input

CLK

DIV

SERDES

Quad

Clock

Input

Clock

Input

PLL Input

DLL Input

Clock

Input

Clock

Input

Clock InputClock Input

PLL

DLL

CLK

DIV

2-12

Architecture

LatticeECP3 Family Data Sheet

Figure 2-10. Primary Clock Sources for LatticeECP3-35

Figure 2-11. Primary Clock Sources for LatticeECP3-70, -95, -150

Primary Clock Sources

to Eight Quadrant Clock Selection

From Routing

PLL

DLL

PLL Input

DLL Input

CLK

DIV

Clock

Input

Clock

Input

PLL Input

DLL Input

Clock

Input

Clock

Input

Clock InputClock Input

PLL

DLL

CLK

DIV

SERDES

Quad

Note: Clock inputs can be configured in differential or single-ended mode.

Primary Clock Sources

to Eight Quadrant Clock Selection

From Routing

PLL

DLL

PLL Input

DLL Input

CLK

DIV

Clock

Input

Clock

Input

PLL Input

DLL Input

Clock

Input

Clock

Input

Clock InputClock Input

PLL

PLL InputPLL Input

PLL

PLL InputPLL Input

PLL

PLL InputPLL Input

PLL

DLL

CLK

DIV

SERDES

Quad

SERDES

Quad

SERDES

Quad

SERDES

Quad

(ECP3-150 only)

Note: Clock inputs can be configured in differential or single-ended mode.

2-13

Architecture

LatticeECP3 Family Data Sheet

Primary Clock Routing

The purpose of the primary clock routing is to distribute primary clock sources to the destination quadrants of the

device. A global primary clock is a primary clock that is distributed to all quadrants. The clock routing structure in

LatticeECP3 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The pri-

mary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources

are connected to these muxes. Figure 2-12 shows the clock routing for one quadrant. Each quadrant mux is identi-

cal. If desired, any clock can be routed globally.

Figure 2-12. Per Quadrant Primary Clock Selection

Dynamic Clock Control (DCC)

The DCC (Quadrant Clock Enable/Disable) feature allows internal logic control of the quadrant primary clock net-

work. When a clock network is disabled, all the logic fed by that clock does not toggle, reducing the overall power

consumption of the device.

Dynamic Clock Select (DCS)

The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent

input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog-

gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the

DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7

(see Figure 2-12).

Figure 2-13 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed

to other modes. For more information about the DCS, please see the list of technical documentation at the end of

this data sheet.

Figure 2-13. DCS Waveforms

CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7

63:1 63:1 63:1 63:1 58:1 58:1 58:1 58:163:1 63:1

DCC DCC DCC DCC DCS DCSDCC DCC

8 Primary Clocks (CLK0 to CLK7) per Quadrant

PLLs + DLLs + CLKDIVs + PCLK PIOs + SERDES Quads

CLK0

SEL

DCSOUT

CLK1

2-14

Architecture

LatticeECP3 Family Data Sheet

Secondary Clock/Control Sources

LatticeECP3 devices derive eight secondary clock sources (SC0 through SC7) from six dedicated clock input pads

and the rest from routing. Figure 2-14 shows the secondary clock sources. All eight secondary clock sources are

defined as inputs to a per-region mux SC0-SC7. SC0-SC3 are primary for control signals (CE and/or LSR), and

SC4-SC7 are for the clock.

In an actual implementation, there is some overlap to maximize routability. In addition to SC0-SC3, SC7 is also an

input to the control signals (LSR or CE). SC0-SC2 are also inputs to clocks along with SC4-SC7.

Figure 2-14. Secondary Clock Sources

Secondary Clock/Control Routing

Global secondary clock is a secondary clock that is distributed to all regions. The purpose of the secondary clock

routing is to distribute the secondary clock sources to the secondary clock regions. Secondary clocks in the

LatticeECP3 devices are region-based resources. Certain EBR rows and special vertical routing channels bind the

secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP

slice in the DSP row or the center of the DSP row. Figure 2-15 shows this special vertical routing channel and the

20 secondary clock regions for the LatticeECP3 family of devices. All devices in the LatticeECP3 family have eight

secondary clock resources per region (SC0 to SC7). The same secondary clock routing can be used for control

signals.

Secondary Clock Sources

From Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From Routing

Clock Input

Clock

Input

Clock

Input

Clock Input

From Routing

Note: Clock inputs can be configured in differential or single-ended mode.

From Routing

Clock Input

From Routing

2-15

Architecture

LatticeECP3 Family Data Sheet

Table 2-6. Secondary Clock Regions

Figure 2-15. LatticeECP3-70 and LatticeECP3-95 Secondary Clock Regions

Device

Number of Secondary Clock

Regions

ECP3-17 16

ECP3-35 16

ECP3-70 20

ECP3-95 20

ECP3-150 36

sysIO Bank 0 sysIO Bank 1

SERDES

sysIO Bank 7

sysIO Bank 2

sysIO Bank 6

sysIO Bank 3 Configuration Bank

Secondary Clock

Region R1C1

Secondary Clock

Region R2C1

Secondary Clock

Region R3C1

Secondary Clock

Region R4C1

Secondary Clock

Region R5C1

Secondary Clock

Region R1C2

Secondary Clock

Region R2C2

Secondary Clock

Region R3C2

Secondary Clock

Region R4C2

Secondary Clock

Region R5C2

Secondary Clock

Region R1C3

Vertical Routing Channel

Regional Boundary

Secondary Clock

Region R2C3

Secondary Clock

Region R3C3

Secondary Clock

Region R4C3

Secondary Clock

Region R5C3

Secondary Clock

Region R1C4

Secondary Clock

Region R2C4

Secondary Clock

Region R3C4

Secondary Clock

Region R4C4

Secondary Clock

Region R5C4

EBR Row

Regional Boundar

EBR Row

Regional Boundar

Spine Repeaters

2-16

Architecture

LatticeECP3 Family Data Sheet

Figure 2-16. Per Region Secondary Clock Selection

Slice Clock Selection

Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All

the primary clocks and seven secondary clocks are routed to this clock selection mux. Other signals can be used

as a clock input to the slices via routing. Slice controls are generated from the secondary clocks/controls or other

signals connected via routing.

If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3

does not have any registers; therefore it does not have the clock or control muxes.

Figure 2-17. Slice0 through Slice2 Clock Selection

Figure 2-18. Slice0 through Slice2 Control Selection

SC0 SC1 SC2 SC3 SC4 SC5

8:1 8:1 8:1 8:1

SC6

8:1

SC7

8:18:1 8:1

8 Secondary Clocks (SC0 to SC7) per Region

Clock/Control

Secondary Clock Feedlines: 6 PIOs + 16 Routing

Clock to Slice

Primary Clock

Secondary Clock

Routing

Vcc

28:1

Slice Control

Secondary Control

Routing

Vcc

20:1

2-17

Architecture

LatticeECP3 Family Data Sheet

Edge Clock Sources

Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be

driven from adjacent edge clock PIOs, primary clock PIOs, PLLs, DLLs, Slave Delay and clock dividers as shown in

Figure 2-19.

Figure 2-19. Edge Clock Sources

Edge Clock Routing

LatticeECP3 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the

implementation of high-speed interfaces. There are six edge clocks per device: two edge clocks on each of the top,

left, and right edges. Different PLL and DLL outputs are routed to the two muxes on the left and right sides of the

device. In addition, the CLKINDEL signal (generated from the DLL Slave Delay Line block) is routed to all the edge

clock muxes on the left and right sides of the device. Figure 2-20 shows the selection muxes for these clocks.

Six Edge Clocks (ECLK)

Two Clocks per Edge

Sources for right edge clocks

Clock

Input

Clock

Input

From Routing

From

Routing

From

Routing

Clock Input Clock Input

From Routing

Clock

Input

Clock

Input

From Routing

Sources for left edge clocks

Notes:

1. Clock inputs can be configured in differential or single ended mode.

2. The two DLLs can also drive the two top edge clocks.

3. The top left and top right PLL can also drive the two top edge clocks.

Sources for top

edge clocks

DLL

Input

PLL

Input

DLL

Input

PLL

Input

Slave Delay

DLL

PLL

DLL

PLL

Slave Delay

2-18

Architecture

LatticeECP3 Family Data Sheet

Figure 2-20. Sources of Edge Clock (Left and Right Edges)

Figure 2-21. Sources of Edge Clock (Top Edge)

The edge clocks have low injection delay and low skew. They are used to clock the I/O registers and thus are ideal

for creating I/O interfaces with a single clock signal and a wide data bus. They are also used for DDR Memory or

Generic DDR interfaces.

Left and Right

Edge Clocks

ECLK1

Routing

Input Pad

PLL Input Pad

DLL Output CLKOP

PLL Output CLKOS

PLL Output CLKOP

CLKINDEL

from DLL Slave Delay

Left and Right

Edge Clocks

ECLK2

Routing

Input Pad

PLL Input Pad

DLL Output CLKOS

PLL Output CLKOS

CLKINDEL

from DLL Slave Delay

7:1

ECLK1

ECLK2

Input Pad

Top left PLL_CLKOP

Routing

CLKINDEL

Top Right PLL_CLKOS

Left DLL_CLKOP

Right DLL_CLKOS

(Left DLL_DEL)

Input Pad

Top Right PLL_CLKOP

Routing

CLKINDEL

Top Left PLL_CLKOS

Right DLL_CLKOP

Left DLL_CLKOS

(Right DLL_DEL)

7:1

2-19

Architecture

LatticeECP3 Family Data Sheet

The edge clocks on the top, left, and right sides of the device can drive the secondary clocks or general routing

resources of the device. The left and right side edge clocks also can drive the primary clock network through the

clock dividers (CLKDIV).

sysMEM Memory

LatticeECP3 devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-Kbit

RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Each

EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and FIFO buffers

(via external PFUs).

sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in

a variety of depths and widths as shown in Table 2-7. FIFOs can be implemented in sysMEM EBR blocks by imple-

menting support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for

each data byte. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. For

more information, please see TN1179, LatticeECP3 Memory Usage Guide.

Table 2-7. sysMEM Block Configurations

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block

during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on specific design inputs.

Memory Mode Configurations

Single Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

True Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

Pseudo Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

2-20

Architecture

LatticeECP3 Family Data Sheet

Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output.

EBR memory supports the following forms of write behavior for single port or dual port operation:

1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This

mode is supported for all data widths.

3. Read-Before-Write (EA devices only) – When new data is written, the old content of the address appears at

the output. This mode is supported for x9, x18, and x36 data widths.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A

and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and asso-

ciated resets for both ports are as shown in Figure 2-22.

Figure 2-22. Memory Core Reset

For further information on the sysMEM EBR block, please see the list of technical documentation at the end of this

data sheet.

sysDSP™ Slice

The LatticeECP3 family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, high-per-

formance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite

Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convo-

lution encoders and decoders. These complex signal processing functions use similar building blocks such as mul-

tiply-adders and multiply-accumulators.

sysDSP Slice Approach Compared to General DSP

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with

fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by

higher clock speeds. The LatticeECP3, on the other hand, has many DSP slices that support different data widths.

SET

CLR

Output Data

Latches

Memory Core

Port A[17:0]

SET

DPort B[17:0]

RSTB

GSRN

Programmable Disable

RSTA

CLR

2-21

Architecture

LatticeECP3 Family Data Sheet

This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP perfor-

mance vs. area by choosing appropriate levels of parallelism. Figure 2-23 compares the fully serial implementation

to the mixed parallel and serial implementation.

Figure 2-23. Comparison of General DSP and LatticeECP3 Approaches

LatticeECP3 sysDSP Slice Architecture Features

The LatticeECP3 sysDSP Slice has been significantly enhanced to provide functions needed for advanced pro-

cessing applications. These enhancements provide improved flexibility and resource utilization.

The LatticeECP3 sysDSP Slice supports many functions that include the following:

• Multiply (one 18x36, two 18x18 or four 9x9 Multiplies per Slice)

• Multiply (36x36 by cascading across two sysDSP slices)

• Multiply Accumulate (up to 18x36 Multipliers feeding an Accumulator that can have up to 54-bit resolution)

• Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18x18 Mul-

tiplies feed into an accumulator that can accumulate up to 52 bits)

• Flexible saturation and rounding options to satisfy a diverse set of applications situations

• Flexible cascading across DSP slices

– Minimizes fabric use for common DSP and ALU functions

– Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only

– Provides matching pipeline registers

– Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade

chains

• Flexible and Powerful Arithmetic Logic Unit (ALU) Supports:

– Dynamically selectable ALU OPCODE

– Ternary arithmetic (addition/subtraction of three inputs)

– Bit-wise two-input logic operations (AND, OR, NAND, NOR, XOR and XNOR)

– Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such

Multiplier

xx x

Multiplier

(k adds)

Output

Single

Multiplier x

Operand

Accumulator

M loops

Function Implemented in

General Purpose DSP

Function Implemented in

LatticeECP3

m/k

accumulate

m/k

loops

2-22

Architecture

LatticeECP3 Family Data Sheet

as, overflow, underflow and convergent rounding, etc.

– Flexible cascading across slices to get larger functions

• RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy

users

• Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require

processor-like flexibility that enables different functions for each clock cycle

For most cases, as shown in Figure 2-24, the LatticeECP3 DSP slice is backwards-compatible with the

LatticeECP2™ sysDSP block, such that, legacy applications can be targeted to the LatticeECP3 sysDSP slice. The

functionality of one LatticeECP2 sysDSP Block can be mapped into two adjacent LatticeECP3 sysDSP slices, as

shown in Figure 2-25.

Figure 2-24. Simplified sysDSP Slice Block Diagram

PR PR

MULTA MULTAMULTB MULTB

Mult18-0 Mult18-0 Mult18-1

One of

these

Mult18-1

OR OR

Input Registers

from SRO of

Left-side DSP

ALU Op-Codes

Slice 0 Slice 1

Cascade from

Left DSP Accumulator/ALU (54) Accumulator/ALU (54)

To FPGA Core

From FPGA Core

Cascade to

Right DSP

Intermediate Pipeline

Registers

Output Registers OR OR OR OR OR OR

Carry

Out

Reg.

Carry

Out

Reg.

9x9 9x9 9x9 9x9 9x9 9x9 9x9 9x9

Casc

A0 Casc

2-23

Architecture

LatticeECP3 Family Data Sheet

Figure 2-25. Detailed sysDSP Slice Diagram

The LatticeECP2 sysDSP block supports the following basic elements.

• MULT (Multiply)

• MAC (Multiply, Accumulate)

• MULTADDSUB (Multiply, Addition/Subtraction)

• MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)

Table 2-8 shows the capabilities of each of the LatticeECP3 slices versus the above functions.

Table 2-8. Maximum Number of Elements in a Slice

Some options are available in the four elements. The input register in all the elements can be directly loaded or can

be loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following opera-

tions are possible:

• In the Add/Sub option the Accumulator can be switched between addition and subtraction on every cycle.

• The loading of operands can switch between parallel and serial operations.

Width of Multiply x9 x18 x36

MULT 4 2 1/2

MAC 1 1 —

MULTADDSUB 2 1 —

MULTADDSUBSUM 111/2 —

1. One slice can implement 1/2 9x9 m9x9addsubsum and two m9x9addsubsum with two slices.

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PRPR

Rounding

A_ALU

OPCODEC

CINCOUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

Note: A_ALU, B_ALU and C_ALU are internal signals generated by combining bits from AA, AB, BA BB and C

inputs. See TN1182, LatticeECP3 sysDSP Usage Guide, for further information.

DSP Slice

IR IR IR IR

OROR FR

2-24

Architecture

LatticeECP3 Family Data Sheet

For further information, please refer to TN1182, LatticeECP3 sysDSP Usage Guide.

MULT DSP Element

This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, AA and

AB, are multiplied and the result is available at the output. The user can enable the input/output and pipeline regis-

ters. Figure 2-26 shows the MULT sysDSP element.

Figure 2-26. MULT sysDSP Element

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PRPR

Rounding

A_ALU

OPCODEC

CINCOUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR IR

OROR FR

2-25

Architecture

LatticeECP3 Family Data Sheet

MAC DSP Element

In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated

value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but

the output register is always enabled. The output register is used to store the accumulated value. The ALU is con-

figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically. A regis-

tered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-27

shows the MAC sysDSP element.

Figure 2-27. MAC DSP Element

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PR PR

Rounding

A_ALU

OPCODEC

CINCOUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR

OROR OR FR

2-26

Architecture

LatticeECP3 Family Data Sheet

MMAC DSP Element

The LatticeECP3 supports a MAC with two multipliers. This is called Multiply Multiply Accumulate or MMAC. In this

case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated value and

with the result of the multiplier operation of operands BA and BB. This accumulated value is available at the output.

The user can enable the input and pipeline registers, but the output register is always enabled. The output register

is used to store the accumulated value. The ALU is configured as the accumulator in the sysDSP slice. A registered

overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-28 shows the

MMAC sysDSP element.

Figure 2-28. MMAC sysDSP Element

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

Rounding

A_ALU

OPCODEC

CINCOUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR IR

OROR FR

2-27

Architecture

LatticeECP3 Family Data Sheet

MULTADDSUB DSP Element

In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands BA and BB. The user can enable the input, output and pipeline registers. Figure 2-29

shows the MULTADDSUB sysDSP element.

Figure 2-29. MULTADDSUB

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PRPR

Rounding

A_ALU

OPCODEC

CINCOUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR IR IR

ORFROR

2-28

Architecture

LatticeECP3 Family Data Sheet

MULTADDSUBSUM DSP Element

In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands BA and BB of Slice 0. Additionally, the operands AA and AB are multiplied and the

result is added/subtracted with the result of the multiplier operation of operands BA and BB of Slice 1. The results

of both addition/subtractions are added by the second ALU following the slice cascade path. The user can enable

the input, output and pipeline registers. Figure 2-30 and Figure 2-31 show the MULTADDSUBSUM sysDSP ele-

ment.

Figure 2-30. MULTADDSUBSUM Slice 0

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PR PR

Rounding

A_ALU

OPCODEC

CINCOUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR

OROR OR

2-29

Architecture

LatticeECP3 Family Data Sheet

Figure 2-31. MULTADDSUBSUM Slice 1

Advanced sysDSP Slice Features

Cascading

The LatticeECP3 sysDSP slice has been enhanced to allow cascading. Adder trees are implemented fully in sys-

DSP slices, improving the performance. Cascading of slices uses the signals CIN, COUT and C Mux of the slice.

Addition

The LatticeECP3 sysDSP slice allows for the bypassing of multipliers and cascading of adder logic. High perfor-

mance adder functions are implemented without the use of LUTs. The maximum width adders that can be imple-

mented are 54-bit.

Rounding

The rounding operation is implemented in the ALU and is done by adding a constant followed by a truncation oper-

ation. The rounding methods supported are:

• Rounding to zero (RTZ)

• Rounding to infinity (RTI)

• Dynamic rounding

• Random rounding

• Convergent rounding

R= A ± B ± C

R = Logic (B, C)

AA AB BA BB

MULTA MULTB

BMUX

AMUX

CMUX

ALU

A_ALU B_ALU

PR PR

Rounding

A_ALU

OPCODEC

CINCOUT

SROB

SROA

SRIB

SRIA

C_ALU

From FPGA Core

To FPGA Core

IR = Input Register

PR = Pipeline Register

OR = Output Register

FR = Flag Register

DSP Slice

IR IR

OROR

2-30

Architecture

LatticeECP3 Family Data Sheet

ALU Flags

The sysDSP slice provides a number of flags from the ALU including:

• Equal to zero (EQZ)

• Equal to zero with mask (EQZM)

• Equal to one with mask (EQOM)

• Equal to pattern with mask (EQPAT)

• Equal to bit inverted pattern with mask (EQPATB)

• Accumulator Overflow (OVER)

• Accumulator Underflow (UNDER)

• Either over or under flow supporting LatticeECP2 legacy designs (OVERUNDER)

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable and Reset signals from routing are available to every sysDSP slice. From four clock

sources (CLK0, CLK1, CLK2, and CLK3) one clock is selected for each input register, pipeline register and output

put register.

Resources Available in the LatticeECP3 Family

Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP3 family. Table 2-10 shows

the maximum available EBR RAM Blocks in each LatticeECP3 device. EBR blocks, together with Distributed RAM

can be used to store variables locally for fast DSP operations.

Table 2-9. Maximum Number of DSP Slices in the LatticeECP3 Family

Table 2-10. Embedded SRAM in the LatticeECP3 Family

Device DSP Slices 9x9 Multiplier 18x18 Multiplier 36x36 Multiplier

ECP3-17 12 48 24 6

ECP3-35 32 128 64 16

ECP3-70 64 256 128 32

ECP3-95 64 256 128 32

ECP3-150 160 640 320 80

Device EBR SRAM Block

Total EBR SRAM

(Kbits)

ECP3-17 38 700

ECP3-35 72 1327

ECP3-70 240 4420

ECP3-95 240 4420

ECP3-150 372 6850

2-31

Architecture

LatticeECP3 Family Data Sheet

Programmable I/O Cells (PIC)

Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-32. The PIO Block

supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the

buffer. Table 2-11 provides the PIO signal list.

Figure 2-32. PIC Diagram

ONEGB

INA

IPA

DEL[3:0]

ECLK1, ECLK2

SCLK

LSR

ECLK1

ECLK2

SCLK

READ

DCNTL[5:0]

DYNDEL[7:0]

DQSI

PRMDET

GSRN

DDRLAT*

DDRCLKPOL*

ECLKDQSR*

DQCLK0*

DQCLK1*

DQSW*

CLK

CEOT

CEI

sysIO

Buffer

PADA

“T”

PADB

“C”

LSR

GSR

* Signals are available on left/right/top edges only.

** Signals are available on the left and right sides only

*** Selected PIO.

IOLD0

Tristate

Block

Output

Block

(ISI)

Input

Block

Control

Muxes

Read Control

Write Control

PIOB

PIOA

OPOSA

OPOSB

ONEGA**

ONEGB**

IPB

INCK

INDD

INB

IOLT0

I/Os in a DQS-12 Group, Except DQSN (Complement of DQS) I/Os

DQS Control Block

(One per DQS Group of 12 I/Os)***

2-32

Architecture

LatticeECP3 Family Data Sheet

Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-32.

The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right

edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as LVDS inputs.

Table 2-11. PIO Signal List

PIO

The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic

block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec-

tion logic.

Input Register Block

The input register blocks for the PIOs, in the left, right and top edges, contain delay elements and registers that can

be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter-

faces, before they are passed to the device core. Figure 2-33 shows the input register block for the left, right and

top edges. The input register block for the bottom edge contains one element to register the input signal and no

DDR registers. The following description applies to the input register block for PIOs in the left, right and top edges

only.

Name Type Description

INDD Input Data Register bypassed input. This is not the same port as INCK.

IPA, INA, IPB, INB Input Data Ports to core for input data

OPOSA, ONEGA1,

OPOSB, ONEGB1

Output Data Output signals from core. An exception is the ONEGB port, used for tristate logic

at the DQS pad.

CE PIO Control Clock enables for input and output block flip-flops.

SCLK PIO Control System Clock (PCLK) for input and output/TS blocks. Connected from clock ISB.

LSR PIO Control Local Set/Reset

ECLK1, ECLK2 PIO Control Edge clock sources. Entire PIO selects one of two sources using mux.

ECLKDQSR1Read Control From DQS_STROBE, shifted strobe for memory interfaces only.

DDRCLKPOL1Read Control Ensures transfer from DQS domain to SCLK domain.

DDRLAT1Read Control Used to guarantee INDDRX2 gearing by selectively enabling a D-Flip-Flop in dat-

apath.

DEL[3:0] Read Control Dynamic input delay control bits.

INCK To Clock Distribution

and PLL

PIO treated as clock PIO, path to distribute to primary clocks and PLL.

TS Tristate Data Tristate signal from core (SDR)

DQCLK01, DQCLK11Write Control Two clocks edges, 90 degrees out of phase, used in output gearing.

DQSW2Write Control Used for output and tristate logic at DQS only.

DYNDEL[7:0] Write Control Shifting of write clocks for specific DQS group, using 6:0 each step is approxi-

mately 25ps, 128 steps. Bit 7 is an invert (timing depends on input frequency).

There is also a static control for this 8-bit setting, enabled with a memory cell.

DCNTL[6:0] PIO Control Original delay code from DDR DLL

DATAVALID1Output Data Status flag from DATAVALID logic, used to indicate when input data is captured in

IOLOGIC and valid to core.

READ For DQS_Strobe Read signal for DDR memory interface

DQSI For DQS_Strobe Unshifted DQS strobe from input pad

PRMBDET For DQS_Strobe DQSI biased to go high when DQSI is tristate, goes to input logic block as well as

core logic.

GSRN Control from routing Global Set/Reset

1. Signals available on left/right/top edges only.

2. Selected PIO.

2-33

Architecture

LatticeECP3 Family Data Sheet

Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,

in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed

delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when

using a global clock.

The input block allows three modes of operation. In single data rate (SDR) the data is registered with the system

clock by one of the registers in the single data rate sync register block.

In DDR mode, two registers are used to sample the data on the positive and negative edges of the modified DQS

(ECLKDQSR) in the DDR Memory mode or ECLK signal when using DDR Generic mode, creating two data

streams. Before entering the core, these two data streams are synchronized to the system clock to generate two

data streams.

A gearbox function can be implemented in each of the input registers on the left and right sides. The gearbox func-

tion takes a double data rate signal applied to PIOA and converts it as four data streams, INA, IPA, INB and IPB.

The two data streams from the first set of DDR registers are synchronized to the edge clock and then to the system

clock before entering the core. Figure 2-30 provides further information on the use of the gearbox function.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred to the system clock domain from the ECLKDQSR (DDR Memory Interface

mode) or ECLK (DDR Generic mode). The DDRLAT signal is used to ensure the data transfer from the synchroni-

zation registers to the clock transfer and gearbox registers.

The ECLKDQSR, DDRCLKPOL and DDRLAT signals are generated in the DQS Read Control Logic Block. See

Figure 2-37 for an overview of the DQS read control logic.

Further discussion about using the DQS strobe in this module is discussed in the DDR Memory section of this data

sheet.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on this topic.

2-34

Architecture

LatticeECP3 Family Data Sheet

Figure 2-33. Input Register Block for Left, Right and Top Edges

Output Register Block

The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.

The blocks on the left and right PIOs contain registers for SDR and full DDR operation. The topside PIO block is the

same as the left and right sides except it does not support ODDRX2 gearing of output logic. ODDRX2 gearing is

used in DDR3 memory interfaces.The PIO blocks on the bottom contain the SDR registers but do not support

generic DDR.

Figure 2-34 shows the Output Register Block for PIOs on the left and right edges.

In SDR mode, OPOSA feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a

Dtype or latch. In DDR mode, two of the inputs are fed into registers on the positive edge of the clock. At the next

clock cycle, one of the registered outputs is also latched.

A multiplexer running off the same clock is used to switch the mux between the 11 and 01 inputs that will then feed

the output.

A gearbox function can be implemented in the output register block that takes four data streams: OPOSA, ONEGA,

OPOSB and ONEGB. All four data inputs are registered on the positive edge of the system clock and two of them

are also latched. The data is then output at a high rate using a multiplexer that runs off the DQCLK0 and DQCLK1

clocks. DQCLK0 and DQCLK1 are used in this case to transfer data from the system clock to the edge clock

domain. These signals are generated in the DQS Write Control Logic block. See Figure 2-37 for an overview of the

DQS write control logic.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on this topic.

Further discussion on using the DQS strobe in this module is discussed in the DDR Memory section of this data

sheet.

(From sysIO

Buffer)

D Q

DDRCLKPOL

Dynamic Delay

Fixed Delay

D Q

SCLK

D Q

INA

INB

IPB

IPA

D Q

DDRLAT

Config bit

INCLK**

DEL[3:0]

INDD

D Q

DDR Registers

CLKP

ECLK2

Synch Registers

ECLKDQSR

ECLK1

ECLK2

Clock Transfer &

Gearing Registers*

* Only on the left and right sides.

** Selected PIO.

Note: Simplified diagram does not show CE/SET/REST details.

To DQSI**

1 0

2-35

Architecture

LatticeECP3 Family Data Sheet

Figure 2-34. Output and Tristate Block for Left and Right Edges

Tristate Register Block

The tristate register block registers tri-state control signals from the core of the device before they are passed to the

sysI/O buffers. The block contains a register for SDR operation and an additional register for DDR operation.

In SDR and non-gearing DDR modes, TS input feeds one of the flip-flops that then feeds the output. In DDRX2

mode, the register TS input is fed into another register that is clocked using the DQCLK0 and DQCLK1 signals. The

output of this register is used as a tristate control.

ISI Calibration

The setting for Inter-Symbol Interference (ISI) cancellation occurs in the output register block. ISI correction is only

available in the DDRX2 modes. ISI calibration settings exist once per output register block, so each I/O in a DQS-

12 group may have a different ISI calibration setting.

The ISI block extends output signals at certain times, as a function of recent signal history. So, if the output pattern

consists of a long strings of 0's to long strings of 1's, there are no delays on output signals. However, if there are

quick, successive transitions from 010, the block will stretch out the binary 1. This is because the long trail of 0's will

cause these symbols to interfere with the logic 1. Likewise, if there are quick, successive transitions from 101, the

block will stretch out the binary 0. This block is controlled by a 3-bit delay control that can be set in the DQS control

logic block.

For more information about this topic, please see the list of technical documentation at the end of this data sheet.

D Q

ONEGB

OPOSA

OPOSB

ONEGA

D Q

SCLK

DQCLK1

Config Bit

DQCLK0

ISI

D Q

Tristate Logic

Output Logic

Clock

Transfer

Registers

DDR Gearing &

ISI Correction

2-36

Architecture

LatticeECP3 Family Data Sheet

Control Logic Block

The control logic block allows the selection and modification of control signals for use in the PIO block.

DDR Memory Support

Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR,

DDR2 and DDR3 memory interfaces. The support varies by the edge of the device as detailed below.

Left and Right Edges

The left and right sides of the PIC have fully functional elements supporting DDR, DDR2, and DDR3 memory inter-

faces. One of every 12 PIOs supports the dedicated DQS pins with the DQS control logic block. Figure 2-35 shows

the DQS bus spanning 11 I/O pins. Two of every 12 PIOs support the dedicated DQS and DQS# pins with the DQS

control logic block.

Bottom Edge

PICs on the bottom edge of the device do not support DDR memory and Generic DDR interfaces.

Top Edge

PICs on the top side are similar to the PIO elements on the left and right sides but do not support gearing on the

output registers. Hence, the modes to support output/tristate DDR3 memory are removed on the top side.

The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-

tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR

data from the memory into input register blocks. Interfaces on the left, right and top edges are designed for DDR

memories that support 10 bits of data.

Figure 2-35. DQS Grouping on the Left, Right and Top Edges

DLL Calibrated DQS Delay Block

Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces, a PLL is used for this adjustment. However, in DDR memories the clock

PIO B

PIO A

PIO B

PIO A

Assigned

DQS Pin

DQS Delay

sysIO

Buffer PADA "T"

PADB "C"

LVDS Pair

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

2-37

Architecture

LatticeECP3 Family Data Sheet

(referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

The delay required for the DQS signal is generated by two dedicated DLLs (DDR DLL) on opposite side of the

device. Each DLL creates DQS delays in its half of the device as shown in Figure 2-36. The DDR DLL on the left

side will generate delays for all the DQS Strobe pins on Banks 0, 7 and 6 and DDR DLL on the right will generate

delays for all the DQS pins on Banks 1, 2 and 3. The DDR DLL loop compensates for temperature, voltage and pro-

cess variations by using the system clock and DLL feedback loop. DDR DLL communicates the required delay to

the DQS delay block using a 7-bit calibration bus (DCNTL[6:0])

The DQS signal (selected PIOs only, as shown in Figure 2-35) feeds from the PAD through a DQS control logic

block to a dedicated DQS routing resource. The DQS control logic block consists of DQS Read Control logic block

that generates control signals for the read side and DQS Write Control logic that generates the control signals

required for the write side. A more detailed DQS control diagram is shown in Figure 2-37, which shows how the

DQS control blocks interact with the data paths.

The DQS Read control logic receives the delay generated by the DDR DLL on its side and delays the incoming

DQS signal by 90 degrees. This delayed ECLKDQSR is routed to 10 or 11 DQ pads covered by that DQS signal.

This block also contains a polarity control logic that generates a DDRCLKPOL signal, which controls the polarity of

the clock to the sync registers in the input register blocks. The DQS Read control logic also generates a DDRLAT

signal that is in the input register block to transfer data from the first set of DDR register to the second set of DDR

registers when using the DDRX2 gearbox mode for DDR3 memory interface.

The DQS Write control logic block generates the DQCLK0 and DQCLK1 clocks used to control the output gearing

in the Output register block which generates the DDR data output and the DQS output. They are also used to con-

trol the generation of the DQS output through the DQS output register block. In addition to the DCNTL [6:0] input

from the DDR DLL, the DQS Write control block also uses a Dynamic Delay DYN DEL [7:0] attribute which is used

to further delay the DQS to accomplish the write leveling found in DDR3 memory. Write leveling is controlled by the

DDR memory controller implementation. The DYN DELAY can set 128 possible delay step settings. In addition, the

most significant bit will invert the clock for a 180-degree shift of the incoming clock. This will generate the DQSW

signal used to generate the DQS output in the DQS output register block.

Figure 2-36 and Figure 2-37 show how the DQS transition signals that are routed to the PIOs.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on this topic.

2-38

Architecture

LatticeECP3 Family Data Sheet

Figure 2-36. Edge Clock, DLL Calibration and DQS Local Bus Distribution

DQS DQS DQS DQS DQS DQS DQS DQS DQS

DQSDQSDQSDQS DQS DQS DQS

DQS DQS DQS DQS DQS DQS DQS

Bank 0 Bank 1 Configuration Bank

Bank 2

Bank 7Bank 6

Bank 3

DQS Strobe and Transition Detect Logic

I/O Ring

*Includes shared configuration I/Os and dedicated configuration I/Os.

SERDES

DDR DLL

(Left)

DDR DLL

(Right)

DQS Delay Control Bus

ECLK1

ECLK2

DQCLK0

DQCLK1

DDRLAT

DDRCLKPOL

ECLKDQSR

DATAVALID

2-39

Architecture

LatticeECP3 Family Data Sheet

Figure 2-37. DQS Local Bus

Polarity Control Logic

In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and

the internal system clock (during the READ cycle) is unknown. The LatticeECP3 family contains dedicated circuits

to transfer data between these domains. A clock polarity selector is used to prevent set-up and hold violations at

the domain transfer between DQS (delayed) and the system clock. This changes the edge on which the data is reg-

istered in the synchronizing registers in the input register block. This requires evaluation at the start of each READ

cycle for the correct clock polarity.

Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects the first DQS rising edge after the pre-

amble state. This signal is used to control the polarity of the clock to the synchronizing registers.

DDR3 Memory Support

LatticeECP3 supports the read and write leveling required for DDR3 memory interfaces.

Read leveling is supported by the use of the DDRCLKPOL and the DDRLAT signals generated in the DQS Read

Control logic block. These signals dynamically control the capture of the data with respect to the DQS at the input

DDR DLL

DQS Write Control Logic

DQS Read Control Logic

Data Output Register Block

DQCLK0

DQCLK1

DQSW

DDRLAT

DDRCLKPOL

ECLKDQSR

DCNTL[6:0]

Data Input Register Block

DQS

Pad

DDR Data

Pad

DQS Output Register Block

DQS Delay Block

2-40

Architecture

LatticeECP3 Family Data Sheet

To accomplish write leveling in DDR3, each DQS group has a slightly different delay that is set by DYN DELAY[7:0]

in the DQS Write Control logic block. The DYN DELAY can set 128 possible delay step settings. In addition, the

most significant bit will invert the clock for a 180-degree shift of the incoming clock.

LatticeECP3 input and output registers can also support DDR gearing that is used to receive and transmit the high

speed DDR data from and to the DDR3 Memory.

LatticeECP3 supports the 1.5V SSTL I/O standard required for the DDR3 memory interface. For more information,

refer to the sysIO section of this data sheet.

Please see TN1180, LatticeECP3 High-Speed I/O Interface for more information on DDR Memory interface imple-

mentation in LatticeECP3.

sysI/O Buffer

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the

periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety

of standards that are found in today’s systems including LVDS, BLVDS, HSTL, SSTL Class I & II, LVCMOS, LVTTL,

LVPECL, PCI.

sysI/O Buffer Banks

LatticeECP3 devices have six sysI/O buffer banks: six banks for user I/Os arranged two per side. The banks on the

bottom side are wraparounds of the banks on the lower right and left sides. The seventh sysI/O buffer bank (Config-

uration Bank) is located adjacent to Bank 2 and has dedicated/shared I/Os for configuration. When a shared pin is

not used for configuration it is available as a user I/O. Each bank is capable of supporting multiple I/O standards.

Each sysI/O bank has its own I/O supply voltage (VCCIO). In addition, each bank, except the Configuration Bank,

has voltage references, VREF1 and VREF2, which allow it to be completely independent from the others. Figure 2-38

shows the seven banks and their associated supplies.

In LatticeECP3 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-

ered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-

pendent of VCCIO.

Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the refer-

enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.

Each I/O is individually configurable based on the bank’s supply and reference voltages.

2-41

Architecture

LatticeECP3 Family Data Sheet

Figure 2-38. LatticeECP3 Banks

LatticeECP3 devices contain two types of sysI/O buffer pairs.

1. Top (Bank 0 and Bank 1) and Bottom sysIO Buffer Pairs (Single-Ended Outputs Only)

The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of

single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-

figured as a differential input. Only the top edge buffers have a programmable PCI clamp.



The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer. 



The top and bottom sides are ideal for general purpose I/O, PCI, and inputs for LVDS (LVDS outputs are only

allowed on the left and right sides). The top side can be used for the DDR3 ADDR/CMD signals. 



The I/O pins located on the top and bottom sides of the device (labeled PTxxA/B or PBxxA/B) are fully hot

socketable. Note that the pads in Banks 3, 6 and 8 are wrapped around the corner of the device. In these

banks, only the pads located on the top or bottom of the device are hot socketable. The top and bottom side

pads can be identified by the Lattice Diamond tool.

REF1(0)

GND

CCIO0

VREF2(0)

VREF1(1)

GND

CCIO1

REF2(1)

VREF1(7)

GND

VCCIO7

VREF2(7)

VREF1(2)

GND

VCCIO2

VREF2(2)

VREF1(3)

GND

VCCIO3

VREF2(3)

RIGHT

Bank 2

Configuration

Bank

Bank 3

Bank 7

Bank 6

VREF1(6)

GND

VCCIO6

VREF2(6)

Bank 0 Bank 1

BOTTOM

JTAG Bank

SERDES

Quads

LEFT

TOP

2-42

Architecture

LatticeECP3 Family Data Sheet

2. Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Out-

puts)

The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the

referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair

are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,

and the comp (complementary) pad is associated with the negative side of the differential I/O. 



In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on

these sides, which is required for DDR3 interface. However, there is no support for hot-socketing for the I/O

pins located on the left and right side of the device as the PCI clamp is always enabled on these pins.



LVDS, RSDS, PPLVDS and Mini-LVDS differential output drivers are available on 50% of the buffer pairs on the

left and right banks.

3. Configuration Bank sysI/O Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by

Configuration)

The sysI/O buffers in the Configuration Bank consist of ratioed single-ended output drivers and single-ended

input buffers. This bank does not support PCI clamp like the other banks on the top, left, and right sides. 



The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

Programmable PCI clamps are only available on the top banks. PCI clamps are used primarily on inputs and bi-

directional pads to reduce ringing on the receiving end.

Typical sysI/O I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory

levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to

ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of

all the I/O banks that are critical to the application. For more information about controlling the output logic state with

valid input logic levels during power-up in LatticeECP3 devices, see the list of technical documentation at the end

of this data sheet.

The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buf-

fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended

that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or

together with the VCC and VCCAUX supplies.

Supported sysI/O Standards

The LatticeECP3 sysI/O buffer supports both single-ended and differential standards. Single-ended standards can

be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V,

1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration

options for drive strength, slew rates, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and

open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported

include LVDS, BLVDS, LVPECL, MLVDS, RSDS, Mini-LVDS, PPLVDS (point-to-point LVDS), TRLVDS (Transition

Reduced LVDS), differential SSTL and differential HSTL. For further information on utilizing the sysI/O buffer to

support a variety of standards please see TN1177, LatticeECP3 sysIO Usage Guide.

2-43

Architecture

LatticeECP3 Family Data Sheet

On-Chip Programmable Termination

The LatticeECP3 supports a variety of programmable on-chip terminations options, including:

• Dynamically switchable Single-Ended Termination with programmable resistor values of 40, 50, or 60 ohms.

External termination to Vtt should be used for DDR2 and DDR3 memory controller implementation.

• Common mode termination of 80, 100, 120 ohms for differential inputs

Figure 2-39. On-Chip Termination

See Table 2-12 for termination options for input modes.

Table 2-12. On-Chip Termination Options for Input Modes

IO_TYPE TERMINATE to VTT1, 2 DIFFERENTIAL TERMINATION RESISTOR1

LVDS25 þ 80, 100, 120

BLVDS25 þ 80, 100, 120

MLVDS þ 80, 100, 120

HSTL18_I 40, 50, 60 þ

HSTL18_II 40, 50, 60 þ

HSTL18D_I 40, 50, 60 þ

HSTL18D_II 40, 50, 60 þ

HSTL15_I 40, 50, 60 þ

HSTL15D_I 40, 50, 60 þ

SSTL25_I 40, 50, 60 þ

SSTL25_II 40, 50, 60 þ

SSTL25D_I 40, 50, 60 þ

SSTL25D_II 40, 50, 60 þ

SSTL18_I 40, 50, 60 þ

SSTL18_II 40, 50, 60 þ

SSTL18D_I 40, 50, 60 þ

SSTL18D_II 40, 50, 60 þ

SSTL15 40, 50, 60 þ

SSTL15D 40, 50, 60 þ

1. TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have

one setting per bank. Only left and right banks have this feature.

Use of TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in

an I/O bank.

On-chip termination tolerance +/- 20%

2. External termination to VTT should be used when implementing DDR2 and DDR3 memory controller.

Parallel Single-Ended Input Differential Input

Vtt

Control Signal

Off-chip On-Chip

Programmable resistance (40, 50 and 60 Ohms)

Off-chip On-Chip

Vtt*

*Vtt must be left floating for this termination

2-44

Architecture

LatticeECP3 Family Data Sheet

Please see TN1177, LatticeECP3 sysIO Usage Guide for on-chip termination usage and value ranges.

Equalization Filter

Equalization filtering is available for single-ended inputs on both true and complementary I/Os, and for differential

inputs on the true I/Os on the left, right, and top sides. Equalization is required to compensate for the difficulty of

sampling alternating logic transitions with a relatively slow slew rate. It is considered the most useful for the Input

DDRX2 modes, used in DDR3 memory, LVDS, or TRLVDS signaling. Equalization filter acts as a tunable filter with

settings to determine the level of correction. In the LatticeECP3 devices, there are four settings available: 0 (none),

1, 2 and 3. The default setting is 0. The equalization logic resides in the sysI/O buffers, the two bits of setting is set

uniquely in each input IOLOGIC block. Therefore, each sysI/O can have a unique equalization setting within a

DQS-12 group.

Hot Socketing

LatticeECP3 devices have been carefully designed to ensure predictable behavior during power-up and power-

down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is

high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits.

Please refer to the Hot Socketing Specifications in the DC and Switching Characteristics in this data sheet.

SERDES and PCS (Physical Coding Sublayer)

LatticeECP3 devices feature up to 16 channels of embedded SERDES/PCS arranged in quads at the bottom of the

devices supporting up to 3.2Gbps data rate. Figure 2-40 shows the position of the quad blocks for the LatticeECP3-

150 devices. Table 2-14 shows the location of available SERDES Quads for all devices.

The LatticeECP3 SERDES/PCS supports a range of popular serial protocols, including:

• PCI Express 1.1

• Ethernet (XAUI, GbE - 1000 Base CS/SX/LX and SGMII)

• Serial RapidIO

• SMPTE SDI (3G, HD, SD)

•CPRI

• SONET/SDH (STS-3, STS-12, STS-48)

Each quad contains four dedicated SERDES for high speed, full duplex serial data transfer. Each quad also has a

PCS block that interfaces to the SERDES channels and contains protocol specific digital logic to support the stan-

dards listed above. The PCS block also contains interface logic to the FPGA fabric. All PCS logic for dedicated pro-

tocol support can also be bypassed to allow raw 8-bit or 10-bit interfaces to the FPGA fabric.

Even though the SERDES/PCS blocks are arranged in quads, multiple baud rates can be supported within a quad

with the use of dedicated, per channel 1, 2 and 11 rate dividers. Additionally, multiple quads can be arranged

together to form larger data pipes.

For information on how to use the SERDES/PCS blocks to support specific protocols, as well on how to combine

multiple protocols and baud rates within a device, please refer to TN1176, LatticeECP3 SERDES/PCS Usage

Guide.

2-45

Architecture

LatticeECP3 Family Data Sheet

Figure 2-40. SERDES/PCS Quads (LatticeECP3-150)

Table 2-13. LatticeECP3 SERDES Standard Support

Standard

Data Rate

(Mbps)

Number of

General/Link Width Encoding Style

PCI Express 1.1 2500 x1, x2, x4 8b10b

Gigabit Ethernet 1250, 2500 x1 8b10b

SGMII 1250 x1 8b10b

XAUI 3125 x4 8b10b

Serial RapidIO Type I,

Serial RapidIO Type II,

Serial RapidIO Type III

1250,

2500,

3125

x1, x4 8b10b

CPRI-1,

CPRI-2,

CPRI-3,

CPRI-4

614.4,

1228.8,

2457.6,

3072.0

x1 8b10b

SD-SDI

(259M, 344M)

1431,

1771,

270,

360,

540

x1 NRZI/Scrambled

HD-SDI

(292M)

1483.5,

1485 x1 NRZI/Scrambled

3G-SDI

(424M)

2967,

2970 x1 NRZI/Scrambled

SONET-STS-32155.52 x1 N/A

SONET-STS-122622.08 x1 N/A

SONET-STS-4822488 x1 N/A

1. For slower rates, the SERDES are bypassed and CML signals are directly connected to the FPGA routing.

2. The SONET protocol is supported in 8-bit SERDES mode. See TN1176 Lattice ECP3 SERDES/PCS Usage Guide for more information.

sysIO Bank 0 sysIO Bank 1

CH0

CH3

CH2

CH1

SERDES/PCS

Quad D

CH0

CH3

CH2

CH1

CH0

CH3

CH2

CH1

CH0

CH3

CH2

CH1

sysIO Bank 7

sysIO Bank 2

SERDES/PCS

Quad B

SERDES/PCS

Quad A

SERDES/PCS

Quad C

sysIO Bank 6

sysIO Bank 3

Configuration Bank

2-46

Architecture

LatticeECP3 Family Data Sheet

Table 2-14. Available SERDES Quads per LatticeECP3 Devices

SERDES Block

A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and

Data Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The

SERDES transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit

stream through the differential drivers. Figure 2-41 shows a single-channel SERDES/PCS block. Each SERDES

channel provides a recovered clock and a SERDES transmit clock to the PCS block and to the FPGA core logic.

Each transmit channel, receiver channel, and SERDES PLL shares the same power supply (VCCA). The output

and input buffers of each channel have their own independent power supplies (VCCOB and VCCIB).

Figure 2-41. Simplified Channel Block Diagram for SERDES/PCS Block

PCS

As shown in Figure 2-41, the PCS receives the parallel digital data from the deserializer and selects the polarity,

performs word alignment, decodes (8b/10b), provides Clock Tolerance Compensation and transfers the clock

domain from the recovered clock to the FPGA clock via the Down Sample FIFO.

For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b,

selects the polarity and passes the 8/10 bit data to the transmit SERDES channel.

The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA

logic. The PCS interface to the FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to

the FPGA logic.

SCI (SERDES Client Interface) Bus

The SERDES Client Interface (SCI) is an IP interface that allows the SERDES/PCS Quad block to be controlled by

registers rather than the configuration memory cells. It is a simple register configuration interface that allows

SERDES/PCS configuration without power cycling the device.

Package ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150

256 ftBGA 1 1 — — —

328 csBGA2 channels————

484 fpBGA1111

672 fpBGA—1222

1156 fpBGA — — 3 3 4

HDOUTP

HDOUTN

* 1/8 or 1/10 line rate

Deserializer

1:8/1:10 Word Alignment

8b10b Decoder

Serializer

8:1/10:1

8b10b

Encoder

SERDES PCS

Bypass

Transmitter

Receiver

Recovered Clock*

SERDES Transmit Clock*

Receive Clock

Transmit Clock

SERDES Transmit Clock

Receive Data

Transmit Data

Clock/Data

Recovery Clock

Data

RX_REFCLK

HDINP

HDINN

Equalizer

Bypass

Downsample

FIFO

Upsample

FIFO

Recovered Clock

TX PLL

TX REFCLK

Polarity

Adjust

Polarity

Adjust

CTC

FPGA Core

2-47

Architecture

LatticeECP3 Family Data Sheet

The Diamond and ispLEVER design tools support all modes of the PCS. Most modes are dedicated to applications

associated with a specific industry standard data protocol. Other more general purpose modes allow users to

define their own operation. With these tools, the user can define the mode for each quad in a design.

Popular standards such as 10Gb Ethernet, x4 PCI Express and 4x Serial RapidIO can be implemented using IP

(available through Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the

core.

The LatticeECP3 family also supports a wide range of primary and secondary protocols. Within the same quad, the

LatticeECP3 family can support mixed protocols with semi-independent clocking as long as the required clock fre-

quencies are integer x1, x2, or x11 multiples of each other. Table 2-15 lists the allowable combination of primary

and secondary protocol combinations.

Flexible Quad SERDES Architecture

The LatticeECP3 family SERDES architecture is a quad-based architecture. For most SERDES settings and stan-

dards, the whole quad (consisting of four SERDES) is treated as a unit. This helps in silicon area savings, better

utilization and overall lower cost.

However, for some specific standards, the LatticeECP3 quad architecture provides flexibility; more than one stan-

dard can be supported within the same quad.

Table 2-15 shows the standards can be mixed and matched within the same quad. In general, the SERDES stan-

dards whose nominal data rates are either the same or a defined subset of each other, can be supported within the

same quad. In Table 2-15, the Primary Protocol column refers to the standard that determines the reference clock

and PLL settings. The Secondary Protocol column shows the other standard that can be supported within the

same quad.

Furthermore, Table 2-15 also implies that more than two standards in the same quad can be supported, as long as

they conform to the data rate and reference clock requirements. For example, a quad may contain PCI Express 1.1,

SGMII, Serial RapidIO Type I and Serial RapidIO Type II, all in the same quad.

Table 2-15. LatticeECP3 Primary and Secondary Protocol Support

There are some restrictions to be aware of when using spread spectrum. When a quad shares a PCI Express x1

channel with a non-PCI Express channel, ensure that the reference clock for the quad is compatible with all proto-

cols within the quad. For example, a PCI Express spread spectrum reference clock is not compatible with most

Gigabit Ethernet applications because of tight CTC ppm requirements.

While the LatticeECP3 architecture will allow the mixing of a PCI Express channel and a Gigabit Ethernet, Serial

RapidIO or SGMII channel within the same quad, using a PCI Express spread spectrum clocking as the transmit

Primary Protocol Secondary Protocol

PCI Express 1.1 SGMII

PCI Express 1.1 Gigabit Ethernet

PCI Express 1.1 Serial RapidIO Type I

PCI Express 1.1 Serial RapidIO Type II

Serial RapidIO Type I SGMII

Serial RapidIO Type I Gigabit Ethernet

Serial RapidIO Type II SGMII

Serial RapidIO Type II Gigabit Ethernet

Serial RapidIO Type II Serial RapidIO Type I

CPRI-3 CPRI-2 and CPRI-1

3G-SDI HD-SDI and SD-SDI

2-48

Architecture

LatticeECP3 Family Data Sheet

reference clock will cause a violation of the Gigabit Ethernet, Serial RapidIO and SGMII transmit jitter specifica-

tions.

For further information on SERDES, please see TN1176, LatticeECP3 SERDES/PCS Usage Guide.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeECP3 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test

Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a

serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to

be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test

access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage

VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.

For more information, please see TN1169, LatticeECP3 sysCONFIG Usage Guide.

Device Configuration

All LatticeECP3 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),

which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration.

The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-

System Configuration specification. The sysCONFIG port includes seven I/Os used as dedicated pins with the

remaining pins used as dual-use pins. See TN1169, LatticeECP3 sysCONFIG Usage Guide for more information

about using the dual-use pins as general purpose I/Os.

There are various ways to configure a LatticeECP3 device:

1. JTAG

2. Standard Serial Peripheral Interface (SPI and SPIm modes) - interface to boot PROM memory

3. System microprocessor to drive a x8 CPU port (PCM mode)

4. System microprocessor to drive a serial slave SPI port (SSPI mode)

5. Generic byte wide flash with a MachXO™ device, providing control and addressing

On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration

port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any

time after power-up by sending the appropriate command through the TAP port.

LatticeECP3 devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device

(slave mode) with the SPI port of the FPGA to perform read-write operations.

Enhanced Configuration Options

LatticeECP3 devices have enhanced configuration features such as: decryption support, TransFR™ I/O and dual-

boot image support.

1. TransFR (Transparent Field Reconfiguration)

TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without

interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur-

ing device configuration. This allows the device to be field updated with a minimum of system disruption and

downtime. See TN1087, Minimizing System Interruption During Configuration Using TransFR Technology for

details.

2. Dual-Boot Image Support

Dual-boot images are supported for applications requiring reliable remote updates of configuration data for the

2-49

Architecture

LatticeECP3 Family Data Sheet

system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded

remotely and stored in a separate location in the configuration storage device. Any time after the update the

LatticeECP3 can be re-booted from this new configuration file. If there is a problem, such as corrupt data dur-

ing download or incorrect version number with this new boot image, the LatticeECP3 device can revert back to

the original backup golden configuration and try again. This all can be done without power cycling the system.

For more information, please see TN1169, LatticeECP3 sysCONFIG Usage Guide.

Soft Error Detect (SED) Support

LatticeECP3 devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configura-

tion, the configuration data bitstream can be checked with the CRC logic block. In addition, the LatticeECP3 device

can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration

SRAM. The SED operation can be run in the background during user mode. If a soft error occurs, during user

mode (normal operation) the device can be programmed to generate an error signal.

For further information on SED support, please see TN1184, LatticeECP3 Soft Error Detection (SED) Usage

Guide.

External Resistor

LatticeECP3 devices require a single external, 10K ohm ±1% value between the XRES pin and ground. Device

configuration will not be completed if this resistor is missing. There is no boundary scan register on the external

resistor pad.

On-Chip Oscillator

Every LatticeECP3 device has an internal CMOS oscillator which is used to derive a Master Clock (MCCLK) for

configuration. The oscillator and the MCCLK run continuously and are available to user logic after configuration is

completed. The software default value of the MCCLK is nominally 2.5MHz. Table 2-16 lists all the available MCCLK

frequencies. When a different Master Clock is selected during the design process, the following sequence takes

place:

1. Device powers up with a nominal Master Clock frequency of 3.1MHz.

2. During configuration, users select a different master clock frequency.

3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.

4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCCLK

frequency of 2.5MHz.

This internal 130 MHz +/- 15% CMOS oscillator is available to the user by routing it as an input clock to the clock

tree. For further information on the use of this oscillator for configuration or user mode, please see TN1169,

LatticeECP3 sysCONFIG Usage Guide.

Table 2-16. Selectable Master Clock (MCCLK) Frequencies During Configuration (Nominal)

MCCLK (MHz) MCCLK (MHz)

2.5113

4.3 152

5.4 20

6.9 26

8.1 333

9.2

1. Software default MCCLK frequency. Hardware default is 3.1MHz.

2. Maximum MCCLK with encryption enabled.

3. Maximum MCCLK without encryption.

2-50

Architecture

LatticeECP3 Family Data Sheet

Density Shifting

The LatticeECP3 family is designed to ensure that different density devices in the same family and in the same

package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design

migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-

lization design targeted for a high-density device to a lower density device. However, the exact details of the final

resource utilization will impact the likelihood of success in each case. An example is that some user I/Os may

become No Connects in smaller devices in the same package. Refer to the LatticeECP3 Pin Migration Tables and

Diamond software for specific restrictions and limitations.

www.latticesemi.com 3-1 DS1021 DC and Switching_02.5

June 2013 Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Recommended Operating Conditions1

Absolute Maximum Ratings1, 2, 3

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V

Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V

Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V

Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V

Input or I/O Tristate Voltage Applied4. . . . . . -0.5 to 3.75V

Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . +125°C

4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.

Symbol Parameter Min. Max. Units

VCC2Core Supply Voltage 1.14 1.26 V

VCCAUX2, 4 Auxiliary Supply Voltage, Terminating Resistor Switching Power

Supply (SERDES) 3.135 3.465 V

VCCPLL PLL Supply Voltage 3.135 3.465 V

VCCIO2, 3 I/O Driver Supply Voltage 1.14 3.465 V

VCCJ2Supply Voltage for IEEE 1149.1 Test Access Port 1.14 3.465 V

VREF1 and VREF2 Input Reference Voltage 0.5 1.7 V

VTT5Termination Voltage 0.5 1.3125 V

tJCOM Junction Temperature, Commercial Operation 0 85 °C

tJIND Junction Temperature, Industrial Operation -40 100 °C

SERDES External Power Supply6

VCCIB

Input Buffer Power Supply (1.2V) 1.14 1.26 V

Input Buffer Power Supply (1.5V) 1.425 1.575 V

VCCOB

Output Buffer Power Supply (1.2V) 1.14 1.26 V

Output Buffer Power Supply (1.5V) 1.425 1.575 V

VCCA Transmit, Receive, PLL and Reference Clock Buffer Power Supply 1.14 1.26 V

1. For correct operation, all supplies except VREF and VTT must be held in their valid operation range. This is true independent of feature

usage.

2. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be con-

nected to the same power supply as VCCAUX.

3. See recommended voltages by I/O standard in subsequent table.

4. VCCAUX ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.

5. If not used, VTT should be left floating.

6. See TN1176, LatticeECP3 SERDES/PCS Usage Guide for information on board considerations for SERDES power supplies.

LatticeECP3 Family Data Sheet

DC and Switching Characteristics

3-2

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

Hot Socketing Specifications1, 2, 3

Hot Socketing Requirements1, 2

ESD Performance

Please refer to the LatticeECP3 Product Family Qualification Summary for complete qualification data, including

ESD performance.

Symbol Parameter Condition Min. Typ. Max. Units

IDK_HS4Input or I/O Leakage Current 0 VIN  VIH (Max.) — — +/-1 mA

IDK5Input or I/O Leakage Current 0  VIN < VCCIO ——+/-1mA

VCCIO  VIN  VCCIO + 0.5V — 18 — mA

1. VCC, VCCAUX and VCCIO should rise/fall monotonically.

2. IDK is additive to IPU, IPW or IBH.

3. LVCMOS and LVTTL only.

4. Applicable to general purpose I/O pins located on the top and bottom sides of the device.

5. Applicable to general purpose I/O pins located on the left and right sides of the device.

Description Min. Typ. Max. Units

Input current per SERDES I/O pin when device is powered down and inputs

driven. —— 8mA

1. Assumes the device is powered down, all supplies grounded, both P and N inputs driven by CML driver with maximum allowed VCCOB

(1.575V), 8b10b data, internal AC coupling.

2. Each P and N input must have less than the specified maximum input current. For a 16-channel device, the total input current would be

8mA*16 channels *2 input pins per channel = 256mA

3-3

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

IIL, IIH1, 4 Input or I/O Low Leakage 0  VIN  (VCCIO - 0.2V) — — 10 µA

IIH1, 3 Input or I/O High Leakage (VCCIO - 0.2V) < VIN  3.6V — — 150 µA

IPU I/O Active Pull-up Current 0  VIN  0.7 VCCIO -30 — -210 µA

IPD I/O Active Pull-down Current VIL (MAX)  VIN  VCCIO 30 — 210 µA

IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA

IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCIO -30 — — µA

IBHLO Bus Hold Low Overdrive Current 0  VIN  VCCIO ——210µA

IBHHO Bus Hold High Overdrive Current 0  VIN  VCCIO ——-210µA

VBHT Bus Hold Trip Points 0  VIN  VIH (MAX) VIL (MAX) — VIH (MIN) V

C1 I/O Capacitance2 VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = 1.2V, VIO = 0 to VIH (MAX)

—58pf

C2 Dedicated Input Capacitance2VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = 1.2V, VIO = 0 to VIH (MAX)

—57pf

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. TA 25oC, f = 1.0MHz.

3. Applicable to general purpose I/Os in top and bottom banks.

4. When used as VREF

, maximum leakage= 25µA.

3-4

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

LatticeECP3 Supply Current (Standby)1, 2, 3, 4, 5, 6

Over Recommended Operating Conditions

Symbol Parameter Device

Typical

Units-6L, -7L, -8L -6, -7, -8, -9

ICC Core Power Supply Current

ECP-17EA 29.8 49.4 mA

ECP3-35EA 53.7 89.4 mA

ECP3-70EA 137.3 230.7 mA

ECP3-95EA 137.3 230.7 mA

ECP3-150EA 219.5 370.9 mA

ICCAUX Auxiliary Power Supply Current

ECP-17EA 18.3 19.4 mA

ECP3-35EA 19.6 23.1 mA

ECP3-70EA 26.5 32.4 mA

ECP3-95EA 26.5 32.4 mA

ECP3-150EA 37.0 45.7 mA

ICCPLL PLL Power Supply Current (Per PLL)

ECP-17EA 0.0 0.0 mA

ECP3-35EA 0.1 0.1 mA

ECP3-70EA 0.1 0.1 mA

ECP3-95EA 0.1 0.1 mA

ECP3-150EA 0.1 0.1 mA

ICCIO Bank Power Supply Current (Per Bank)

ECP-17EA 1.3 1.4 mA

ECP3-35EA 1.3 1.4 mA

ECP3-70EA 1.4 1.5 mA

ECP3-95EA 1.4 1.5 mA

ECP3-150EA 1.4 1.5 mA

ICCJ JTAG Power Supply Current All Devices 2.5 2.5 mA

ICCA Transmit, Receive, PLL and

Reference Clock Buffer Power Supply

ECP-17EA 6.1 6.1 mA

ECP3-35EA 6.1 6.1 mA

ECP3-70EA 18.3 18.3 mA

ECP3-95EA 18.3 18.3 mA

ECP3-150EA 24.4 24.4 mA

1. For further information on supply current, please see the list of technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.

3. Frequency 0 MHz.

4. Pattern represents a “blank” configuration data file.

5. TJ = 85°C, power supplies at nominal voltage.

6. To determine the LatticeECP3 peak start-up current data, use the Power Calculator tool.

3-5

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

SERDES Power Supply Requirements1, 2, 3

Over Recommended Operating Conditions

Symbol Description Typ. Max. Units

Standby (Power Down)

ICCA-SB VCCA current (per channel) 3 5 mA

ICCIB-SB Input buffer current (per channel) — — mA

ICCOB-SB Output buffer current (per channel) — — mA

Operating (Data Rate = 3.2 Gbps)

ICCA-OP VCCA current (per channel) 68 77 mA

ICCIB-OP Input buffer current (per channel) 5 7 mA

ICCOB-OP Output buffer current (per channel) 19 25 mA

Operating (Data Rate = 2.5 Gbps)

ICCA-OP VCCA current (per channel) 66 76 mA

ICCIB-OP Input buffer current (per channel) 4 5 mA

ICCOB-OP Output buffer current (per channel) 15 18 mA

Operating (Data Rate = 1.25 Gbps)

ICCA-OP VCCA current (per channel) 62 72 mA

ICCIB-OP Input buffer current (per channel) 4 5 mA

ICCOB-OP Output buffer current (per channel) 15 18 mA

Operating (Data Rate = 250 Mbps)

ICCA-OP VCCA current (per channel) 55 65 mA

ICCIB-OP Input buffer current (per channel) 4 5 mA

ICCOB-OP Output buffer current (per channel) 14 17 mA

Operating (Data Rate = 150 Mbps)

ICCA-OP VCCA current (per channel) 55 65 mA

ICCIB-OP Input buffer current (per channel) 4 5 mA

ICCOB-OP Output buffer current (per channel) 14 17 mA

1. Equalization enabled, pre-emphasis disabled.

2. One quarter of the total quad power (includes contribution from common circuits, all channels in the quad operating,

pre-emphasis disabled, equalization enabled).

3. Pre-emphasis adds 20mA to ICCA-OP data.

3-6

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

sysI/O Recommended Operating Conditions

Standard

VCCIO VREF (V)

Min. Typ. Max. Min. Typ. Max.

LVCMOS 3 3 2 3.135 3.3 3.465 — — —

LVCMOS33D 3.135 3.3 3.465 — — —

LVCMOS 2 5 2 2.375 2.5 2.625 — — —

LVCMOS18 1.71 1.8 1.89 — — —

LVCMOS15 1.425 1.5 1.575 — — —

LVCMOS 1 2 2 1.14 1.2 1.26 — — —

LVTTL3 3 2 3.135 3.3 3.465 — — —

PCI33 3.135 3.3 3.465 — — —

SSTL1531.43 1.5 1.57 0.68 0.75 0.9

SSTL18_I, II21.71 1.8 1.89 0.833 0.9 0.969

SSTL25_I, II22.375 2.5 2.625 1.15 1.25 1.35

SSTL33_I, II23.135 3.3 3.465 1.3 1.5 1.7

HSTL15_I21.425 1.5 1.575 0.68 0.75 0.9

HSTL18_I, II21.71 1.8 1.89 0.816 0.9 1.08

LVDS25 2 2.375 2.5 2.625 — — —

LVDS25E 2.375 2.5 2.625 — — —

MLVDS1 2.375 2.5 2.625 — — —

LVPECL331, 2 3.135 3.3 3.465 — — —

Mini LVDS 2.375 2.5 2.625 — — —

BLVDS251, 2 2.375 2.5 2.625 — — —

RSDS2 2.375 2.5 2.625 — — —

RSDSE1, 2 2.375 2.5 2.625 — — —

TRLVDS 3.14 3.3 3.47 — — —

PPLVDS 3.14/2.25 3.3/2.5 3.47/2.75 — — —

SSTL15D31.43 1.5 1.57 — — —

SSTL18D_I2, 3, II2, 3 1.71 1.8 1.89 — — —

SSTL25D_ I2, II22.375 2.5 2.625 — — —

SSTL33D_ I2, II23.135 3.3 3.465 — — —

HSTL15D_ I21.425 1.5 1.575 — — —

HSTL18D_ I2, II21.71 1.8 1.89 — — —

1. Inputs on chip. Outputs are implemented with the addition of external resistors.

2. For input voltage compatibility, see TN1177, LatticeECP3 sysIO Usage Guide.

3. VREF is required when using Differential SSTL to interface to DDR memory.

3-7

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

sysI/O Single-Ended DC Electrical Characteristics

Input/Output

Standard

VIL VIH VOL

Max. (V)

VOH

Min. (V) IOL1 (mA) IOH1 (mA)Min. (V) Max. (V) Min. (V) Max. (V)

LVCMOS33 -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS25 -0.3 0.7 1.7 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS18 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 16, 12,

8, 4

-16, -12,

-8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS15 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 8, 4 -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS12 -0.3 0.35 VCC 0.65 VCC 3.6 0.4 VCCIO - 0.4 6, 2 -6, -2

0.2 VCCIO - 0.2 0.1 -0.1

LVTTL33 -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

PCI33 -0.3 0.3 VCCIO 0.5 VCCIO 3.6 0.1 VCCIO 0.9 VCCIO 1.5 -0.5

SSTL18_I -0.3 VREF - 0.125 VREF + 0.125 3.6 0.4 VCCIO - 0.4 6.7 -6.7

SSTL18_II

(DDR2 Memory) -0.3 VREF - 0.125 VREF + 0.125 3.6 0.28 VCCIO - 0.28 8-8

11 -11

SSTL2_I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 7.6 -7.6

12 -12

SSTL2_II

(DDR Memory) -0.3 VREF - 0.18 VREF + 0.18 3.6 0.35 VCCIO - 0.43 15.2 -15.2

20 -20

SSTL3_I -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCIO - 1.1 8 -8

SSTL3_II -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 16 -16

SSTL15

(DDR3 Memory) -0.3 VREF - 0.1 VREF + 0.1 3.6 0.3 VCCIO - 0.3 7.5 -7.5

VCCIO * 0.8 9 -9

HSTL15_I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 4-4

8-8

HSTL18_I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 8-8

12 -12

HSTL18_II -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 16 -16

1. For electromigration, the average DC current drawn by I/O pads between two consecutive VCCIO or GND pad connections, or between the

last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping)

shall not exceed n * 8mA, where n is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the

last VCCIO and GND in a bank and the end of a bank.

3-8

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

sysI/O Differential Electrical Characteristics

LVD S25

Over Recommended Operating Conditions

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

Parameter Description Test Conditions Min. Typ. Max. Units

VINP1, VINM1Input Voltage 0 — 2.4 V

VCM1Input Common Mode Voltage Half the Sum of the Two Inputs 0.05 — 2.35 V

VTHD Differential Input Threshold Difference Between the Two Inputs +/-100 — — mV

IIN Input Current Power On or Power Off — — +/-10 µA

VOH Output High Voltage for VOP or VOM RT = 100 Ohm — 1.38 1.60 V

VOL Output Low Voltage for VOP or VOM RT = 100 Ohm 0.9V 1.03 — V

VOD Output Voltage Differential (VOP - VOM), RT = 100 Ohm 250 350 450 mV

VOD Change in VOD Between High and

Low ——50mV

VOS Output Voltage Offset (VOP + VOM)/2, RT = 100 Ohm 1.125 1.20 1.375 V

VOS Change in VOS Between H and L — — 50 mV

ISAB Output Short Circuit Current VOD = 0V Driver Outputs Shorted to

Each Other ——12mA

1, On the left and right sides of the device, this specification is valid only for VCCIO = 2.5V or 3.3V.

3-9

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

LVDS25E

The top and bottom sides of LatticeECP3 devices support LVDS outputs via emulated complementary LVCMOS

outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one

possible solution for point-to-point signals.

Figure 3-1. LVDS25E Output Termination Example

Table 3-1. LVDS25E DC Conditions

LVCMOS33D

All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external

resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V

VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to

4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 2.50 V

ZOUT Driver Impedance 20 

RSDriver Series Resistor (+/-1%) 158 

RPDriver Parallel Resistor (+/-1%) 140 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage 1.43 V

VOL Output Low Voltage 1.07 V

VOD Output Differential Voltage 0.35 V

VCM Output Common Mode Voltage 1.25 V

ZBACK Back Impedance 100.5 

IDC DC Output Current 6.03 mA

RS=158 ohms

(±1%)

RS=158 ohms

(±1%)

RP = 140 ohms

(±1%)

RT = 100 ohms

(±1%)

OFF-chip

Transmission line, Zo = 100 ohm differential

VCCIO = 2.5V (±5%)

8 mA

VCCIO = 2.5V (±5%)

ON-chip OFF-chip ON-chip

8 mA

3-10

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

BLVDS25

The LatticeECP3 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS

outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when

multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one

possible solution for bi-directional multi-point differential signals.

Figure 3-2. BLVDS25 Multi-point Output Example

Table 3-2. BLVDS25 DC Conditions1

Over Recommended Operating Conditions

Parameter Description

Typical

UnitsZo = 45Zo = 90

VCCIO Output Driver Supply (+/- 5%) 2.50 2.50 V

ZOUT Driver Impedance 10.00 10.00 

RSDriver Series Resistor (+/- 1%) 90.00 90.00 

RTL Driver Parallel Resistor (+/- 1%) 45.00 90.00 

RTR Receiver Termination (+/- 1%) 45.00 90.00 

VOH Output High Voltage 1.38 1.48 V

VOL Output Low Voltage 1.12 1.02 V

VOD Output Differential Voltage 0.25 0.46 V

VCM Output Common Mode Voltage 1.25 1.25 V

IDC DC Output Current 11.24 10.20 mA

1. For input buffer, see LVDS table.

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

RTL RTR

RS = 90 ohms

RS = 90 ohms RS =

90 ohms

RS =

90 ohms RS =

90 ohms

RS =

90 ohms

RS =

90 ohms

RS =

90 ohms

45-90

ohms

45-90

ohms

2.5V

2.5V 2.5V 2.5V 2.5V

2.5V

. . .

16mA

16mA 16mA 16mA 16mA

16mA

3-11

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

LVPECL33

The LatticeECP3 devices support the differential LVPECL standard. This standard is emulated using complemen-

tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard

is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for

point-to-point signals.

Figure 3-3. Differential LVPECL33

Table 3-3. LVPECL33 DC Conditions1

Over Recommended Operating Conditions

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 3.30 V

ZOUT Driver Impedance 10 

RSDriver Series Resistor (+/-1%) 93 

RPDriver Parallel Resistor (+/-1%) 196 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage 2.05 V

VOL Output Low Voltage 1.25 V

VOD Output Differential Voltage 0.80 V

VCM Output Common Mode Voltage 1.65 V

ZBACK Back Impedance 100.5 

IDC DC Output Current 12.11 mA

1. For input buffer, see LVDS table.

Transmission line,

Zo = 100 ohm differential

Off-chipOn-chip

VCCIO = 3.3V

(+/-5%)

VCCIO = 3.3V

(+/-5%)

RP = 196 ohms

(+/-1%) RT = 100 ohms

(+/-1%)

RS = 93.1 ohms

(+/-1%)

RS = 93.1 ohms

(+/-1%)

16mA

Off-chip On-chip

3-12

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

RSDS25E

The LatticeECP3 devices support differential RSDS and RSDSE standards. This standard is emulated using com-

plementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input stan-

dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for

RSDS standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.

Figure 3-4. RSDS25E (Reduced Swing Differential Signaling)

Table 3-4. RSDS25E DC Conditions1

Over Recommended Operating Conditions

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 2.50 V

ZOUT Driver Impedance 20 

RSDriver Series Resistor (+/-1%) 294 

RPDriver Parallel Resistor (+/-1%) 121 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage 1.35 V

VOL Output Low Voltage 1.15 V

VOD Output Differential Voltage 0.20 V

VCM Output Common Mode Voltage 1.25 V

ZBACK Back Impedance 101.5 

IDC DC Output Current 3.66 mA

1. For input buffer, see LVDS table.

= 294 ohms

(+/-1%)

= 294 ohms

(+/-1%)

= 121 ohms

(+/-1%)

= 100 ohms

(+/-1%)

On-chip On-chip

8mA

VCCIO = 2.5V

(+/-5%)

VCCIO = 2.5V

(+/-5%)

Transmission line,

Zo = 100 ohm differential

Off-chipOff-chip

3-13

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

MLVDS25

The LatticeECP3 devices support the differential MLVDS standard. This standard is emulated using complemen-

tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is

supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for

MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors.

Figure 3-5. MLVDS25 (Multipoint Low Voltage Differential Signaling)

Table 3-5. MLVDS25 DC Conditions1

Parameter Description

Typical

UnitsZo=50Zo=70

VCCIO Output Driver Supply (+/-5%) 2.50 2.50 V

ZOUT Driver Impedance 10.00 10.00 

RSDriver Series Resistor (+/-1%) 35.00 35.00 

RTL Driver Parallel Resistor (+/-1%) 50.00 70.00 

RTR Receiver Termination (+/-1%) 50.00 70.00 

VOH Output High Voltage 1.52 1.60 V

VOL Output Low Voltage 0.98 0.90 V

VOD Output Differential Voltage 0.54 0.70 V

VCM Output Common Mode Voltage 1.25 1.25 V

IDC DC Output Current 21.74 20.00 mA

1. For input buffer, see LVDS table.

16mA

2.5V

Am61

Heavily loaded backplace, effective Zo~50 to 70 ohms differential

50 to 70 ohms +/-1%

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RS =

35ohms

RTR

RTL

16mA

2.5V

Am61

2.5V

Am61

2.5V 2.5V

RS =

50 to 70 ohms +/-1%

35ohms

Am61

16mA

OE OE OE OE

3-14

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

Typical Building Block Function Performance

Pin-to-Pin Performance (LVCMOS25 12mA Drive)1, 2, 3

Function -9 Timing Units

Basic Functions

16-bit Decoder 3.8 ns

32-bit Decoder 3.8 ns

64-bit Decoder 5.4 ns

4:1 MUX 4.0 ns

8:1 MUX 4.2 ns

16:1 MUX 4.5 ns

32:1 MUX 4.7 ns

1. These functions were generated using the ispLEVER design tool. Exact performance may vary with device and tool version. The tool uses

internal parameters that have been characterized but are not tested on every device.

2. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond or ispLEVER soft-

ware.

Function -9 Timing Units

Basic Functions

16-bit Decoder 500 MHz

32-bit Decoder 500 MHz

64-bit Decoder 500 MHz

4:1 MUX 500 MHz

8:1 MUX 500 MHz

16:1 MUX 500 MHz

32:1 MUX 487 MHz

8-bit adder 500 MHz

16-bit adder 500 MHz

64-bit adder 336 MHz

16-bit counter 500 MHz

32-bit counter 500 MHz

64-bit counter 350 MHz

64-bit accumulator 326 MHz

Embedded Memory Functions

512x36 Single Port RAM, EBR Output Registers 358 MHz

1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers) 358 MHz

1024x18 True-Dual Port RAM (Read-Before-Write, EBR Output Registers 136 MHz

1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers) 260 MHz

Distributed Memory Functions

16x4 Pseudo-Dual Port RAM (One PFU) 500 MHz

32x4 Pseudo-Dual Port RAM 500 MHz

64x8 Pseudo-Dual Port RAM 442 MHz

DSP Function

18x18 Multiplier (All Registers) 420 MHz

9x9 Multiplier (All Registers) 420 MHz

36x36 Multiply (All Registers) 281 MHz

3-15

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

, 2

Derating Timing Tables

Logic timing provided in the following sections of this data sheet and the Diamond and ispLEVER design tools are

worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case pro-

cess, can be much better than the values given in the tables. The Diamond and ispLEVER design tools can provide

logic timing numbers at a particular temperature and voltage.

18x18 Multiply/Accumulate (Input & Output Registers) 229 MHz

18x18 Multiply-Add/Sub (All Registers) 420 MHz

1. These timing numbers were generated using ispLEVER tool. Exact performance may vary with device and tool version. The tool uses inter-

nal parameters that have been characterized but are not tested on every device.

2. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond or ispLEVER soft-

ware.

3. LatticeECP3-17EA is not available for the -9 speed grade. The data may vary slightly from -9. The fastest speed grade for LatticeECP3-

17EA is -8.

Function -9 Timing Units

3-16

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

LatticeECP3 External Switching Characteristics 1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-9 -8 -7 -6

UnitsMin. Max. Min. Max. Min. Max. Min. Max.

Clocks

Primary Clock6

fMAX_PRI Frequency for Primary Clock Tree ECP3-150EA —500 —500 —420 —375 MHz

tW_PRI Clock Pulse Width for Primary

Clock ECP3-150EA 0.8 —0.8 —0.9 —1.0 —ns

tSKEW_PRI Primary Clock Skew Within a

Device ECP3-150EA —300 —300 —330 —360 ps

tSKEW_PRIB Primary Clock Skew Within a Bank ECP3-150EA —250 —250 —280 —300 ps

fMAX_PRI Frequency for Primary Clock Tree ECP3-70EA/95EA — 500 — 500 — 420 — 375 MHz

tW_PRI Pulse Width for Primary Clock ECP3-70EA/95EA 0.8 — 0.8 — 0.9 — 1.0 — ns

tSKEW_PRI Primary Clock Skew Within a

Device ECP3-70EA/95EA — 360 — 360 — 370 — 380 ps

tSKEW_PRIB Primary Clock Skew Within a Bank ECP3-70EA/95EA — 310 — 310 — 320 — 330 ps

fMAX_PRI Frequency for Primary Clock Tree ECP3-35EA — 500 — 500 — 420 — 375 MHz

tW_PRI Pulse Width for Primary Clock ECP3-35EA 0. 8 — 0. 8 — 0.9 — 1.0 —ns

tSKEW_PRI Primary Clock Skew Within a

Device ECP3-35EA — 300 — 300 — 330 — 360 ps

tSKEW_PRIB Primary Clock Skew Within a Bank ECP3-35EA — 250 — 250 — 280 — 300 ps

fMAX_PRI Frequency for Primary Clock Tree ECP3-17EA — — — 500 — 420 — 375 MHz

tW_PRI Pulse Width for Primary Clock ECP3-17EA — — 0. 8 — 0.9 — 1.0 — ns

tSKEW_PRI Primary Clock Skew Within a

Device ECP3-17EA — — — 310 — 340 — 370 ps

tSKEW_PRIB Primary Clock Skew Within a Bank ECP3-17EA — — — 220 — 230 — 240 ps

Edge Clock6

fMAX_EDGE Frequency for Edge Clock ECP3-150EA —500 —500 —420 —375 MHz

tW_EDGE Clock Pulse Width for Edge Clock ECP3-150EA 0.9 —0.9 —1.0 —1.2 —ns

tSKEW_EDGE_DQS Edge Clock Skew Within an Edge

of the Device ECP3-150EA —200 —200 —210 —220 ps

fMAX_EDGE Frequency for Edge Clock ECP3-70EA/95EA — 500 — 500 — 420 — 375 MHz

tW_EDGE Clock Pulse Width for Edge Clock ECP3-70EA/95EA 0. 9 — 0. 9 — 1.0 — 1.2 — ns

tSKEW_EDGE_DQS Edge Clock Skew Within an Edge

of the Device ECP3-70EA/95EA — 200 — 200 — 210 — 220 ps

fMAX_EDGE Frequency for Edge Clock ECP3-35EA — 500 — 500 — 420 — 375 MHz

tW_EDGE Clock Pulse Width for Edge Clock ECP3-35EA 0. 9 — 0. 9 — 1.0 — 1.2 —ns

tSKEW_EDGE_DQS Edge Clock Skew Within an Edge

of the Device ECP3-35EA — 200 — 200 — 210 — 220 ps

fMAX_EDGE Frequency for Edge Clock ECP3-17EA — — — 500 — 420 — 375 MHz

tW_EDGE Clock Pulse Width for Edge Clock ECP3-17EA — — 0. 9 — 1.0 — 1.2 — ns

tSKEW_EDGE_DQS Edge Clock Skew Within an Edge

of the Device ECP3-17EA — — — 200 — 210 — 220 ps

Generic SDR

General I/O Pin Parameters Using Dedicated Clock Input Primary Clock Without PLL2

tCO Clock to Output - PIO Output

tSU Clock to Data Setup - PIO Input

tHClock to Data Hold - PIO Input

tSU_DEL Clock to Data Setup - PIO Input

3-17

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

tH_DEL Clock to Data Hold - PIO Input

fMAX_IO Clock Frequency of I/O and PFU

tCO Clock to Output - PIO Output

tSU Clock to Data Setup - PIO Input

tHClock to Data Hold - PIO Input

tSU_DEL Clock to Data Setup - PIO Input

tH_DEL Clock to Data Hold - PIO Input

fMAX_IO Clock Frequency of I/O and PFU

tCO Clock to Output - PIO Output

tSU Clock to Data Setup - PIO Input

tHClock to Data Hold - PIO Input

tSU_DEL Clock to Data Setup - PIO Input

tH_DEL Clock to Data Hold - PIO Input

fMAX_IO Clock Frequency of I/O and PFU

tCO Clock to Output - PIO Output

tSU Clock to Data Setup - PIO Input

tHClock to Data Hold - PIO Input

tSU_DEL Clock to Data Setup - PIO Input

tH_DEL Clock to Data Hold - PIO Input

fMAX_IO Clock Frequency of I/O and PFU

General I/O Pin Parameters Using Dedicated Clock Input Primary Clock with PLL with Clock Injection Removal Setting2

tCOPLL Clock to Output - PIO Output

tSUPLL Clock to Data Setup - PIO Input

tHPLL Clock to Data Hold - PIO Input

tSU_DELPLL Clock to Data Setup - PIO Input

tH_DELPLL Clock to Data Hold - PIO Input

tCOPLL Clock to Output - PIO Output

tSUPLL Clock to Data Setup - PIO Input

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-9 -8 -7 -6

UnitsMin. Max. Min. Max. Min. Max. Min. Max.

3-18

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

tHPLL Clock to Data Hold - PIO Input

tSU_DELPLL Clock to Data Setup - PIO Input

tH_DELPLL Clock to Data Hold - PIO Input

tCOPLL Clock to Output - PIO Output

tSUPLL Clock to Data Setup - PIO Input

tHPLL Clock to Data Hold - PIO Input

tSU_DELPLL Clock to Data Setup - PIO Input

tH_DELPLL Clock to Data Hold - PIO Input

tCOPLL Clock to Output - PIO Output

tSUPLL Clock to Data Setup - PIO Input

tHPLL Clock to Data Hold - PIO Input

tSU_DELPLL Clock to Data Setup - PIO Input

tH_DELPLL Clock to Data Hold - PIO Input

Generic DDR12

Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK Pin for Clock

Input

tSUGDDR Data Setup Before CLK All ECP3EA Devices 480 — 480 — 480 — 480 — ps

tHOGDDR Data Hold After CLK All ECP3EA Devices 480 — 480 — 480 — 480 —ps

fMAX_GDDR DDRX1 Clock Frequency All ECP3EA Devices — 250 — 250 — 250 — 250 MHz

Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.PLL.Aligned) Using PLLCLKIN Pin for

Clock Input

Data Left, Right, and Top Sides and Clock Left and Right Sides

tDVACLKGDDR Data Setup Before CLK All ECP3EA Devices — 0.225 — 0.225 — 0.225 — 0.225 UI

tDVECLKGDDR Data Hold After CLK All ECP3EA Devices 0.775 — 0.775 — 0.775 — 0.775 — UI

fMAX_GDDR DDRX1 Clock Frequency All ECP3EA Devices — 250 — 250 — 250 — 250 MHz

Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using DLL - CLKIN Pin for

Clock Input

Data Left, Right and Top Sides and Clock Left and Right Sides

tDVACLKGDDR Data Setup Before CLK All ECP3EA Devices — 0.225 — 0.225 — 0.225 — 0.225 UI

tDVECLKGDDR Data Hold After CLK All ECP3EA Devices 0.775 — 0.775 — 0.775 — 0.775 —UI

fMAX_GDDR DDRX1 Clock Frequency All ECP3EA Devices — 250 — 250 — 250 — 250 MHz

Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS Pin for Clock

Input

tSUGDDR Data Setup After CLK All ECP3EA Devices 535 — 535 — 535 — 535 — ps

tHOGDDR Data Hold After CLK All ECP3EA Devices 535 — 535 — 535 — 535 — ps

fMAX_GDDR DDRX1 Clock Frequency All ECP3EA Devices — 250 — 250 — 250 — 250 MHz

Generic DDRX1 Inputs with Clock and Data (<10bits wide) Aligned at Pin (GDDRX1_RX.DQS.Aligned) Using DQS Pin for Clock Input

Data and Clock Left and Right Sides

tDVACLKGDDR Data Setup Before CLK All ECP3EA Devices — 0.225 — 0.225 — 0.225 — 0.225 UI

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-9 -8 -7 -6

UnitsMin. Max. Min. Max. Min. Max. Min. Max.

3-19

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

tDVECLKGDDR Data Hold After CLK All ECP3EA Devices 0.775 — 0.775 — 0.775 — 0.775 —UI

fMAX_GDDR DDRX1 Clock Frequency All ECP3EA Devices — 250 — 250 — 250 — 250 MHz

Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Pin for Clock

Input

Left and Right Sides

tSUGDDR Data Setup Before CLK ECP3-150EA 321 — 321 — 403 — 471 — ps

tHOGDDR Data Hold After CLK ECP3-150EA 321 — 321 — 403 — 471 — ps

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA — 405 — 405 — 325 — 280 MHz

tSUGDDR Data Setup Before CLK ECP3-70EA/95EA 321 — 321 — 403 — 535 — ps

tHOGDDR Data Hold After CLK ECP3-70EA/95EA 321 — 321 — 403 — 535 —ps

fMAX_GDDR DDRX2 Clock Frequency ECP3-70EA/95EA — 405 — 405 — 325 — 250 MHz

tSUGDDR Data Setup Before CLK ECP3-35EA 335 — 335 — 425 — 535 — ps

tHOGDDR Data Hold After CLK ECP3-35EA 335 — 335 — 425 — 535 — ps

fMAX_GDDR DDRX2 Clock Frequency ECP3-35EA — 405 — 405 — 325 — 250 MHz

tSUGDDR Data Setup Before CLK ECP3-17EA — — 335 — 425 — 535 — ps

tHOGDDR Data Hold After CLK ECP3-17EA — — 335 — 425 — 535 — ps

fMAX_GDDR DDRX2 Clock Frequency ECP3-17EA — — — 405 — 325 — 250 MHz

Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX2_RX.ECLK.Aligned)

Left and Right Side Using DLLCLKIN Pin for Clock Input

tDVACLKGDDR Data Setup Before CLK ECP3-150EA — 0.225 — 0.225 — 0.225 — 0.225 UI

tDVECLKGDDR Data Hold After CLK ECP3-150EA 0.775 — 0.775 — 0.775 — 0.775 — UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA — 460 — 460 — 385 — 345 MHz

tDVACLKGDDR Data Setup Before CLK ECP3-70EA/95EA — 0.225 — 0.225 — 0.225 — 0.225 UI

tDVECLKGDDR Data Hold After CLK ECP3-70EA/95EA 0.775 — 0.775 — 0.775 — 0.775 —UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-70EA/95EA — 460 — 460 — 385 — 311 MHz

tDVACLKGDDR Data Setup Before CLK ECP3-35EA — 0.210 — 0.210 — 0.210 — 0.210 UI

tDVECLKGDDR Data Hold After CLK ECP3-35EA 0.790 — 0.790 — 0.790 — 0.790 — UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-35EA — 460 — 460 — 385 — 311 MHz

tDVACLKGDDR Data Setup Before CLK ECP3-17EA — — — 0.210 — 0.210 — 0.210 UI

tDVECLKGDDR Data Hold After CLK ECP3-17EA — — 0.790 — 0.790 — 0.790 —UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-17EA — — — 460 —385 —311 MHz

Top Side Using PCLK Pin for Clock Input

tDVACLKGDDR Data Setup Before CLK ECP3-150EA — 0.225 — 0.225 — 0.225 — 0.225 UI

tDVECLKGDDR Data Hold After CLK ECP3-150EA 0.775 — 0.775 — 0.775 — 0.775 — UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-150EA — 235 — 235 — 170 — 130 MHz

tDVACLKGDDR Data Setup Before CLK ECP3-70EA/95EA — 0.225 — 0.225 — 0.225 — 0.225 UI

tDVECLKGDDR Data Hold After CLK ECP3-70EA/95EA 0.775 — 0.775 — 0.775 — 0.775 —UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-70EA/95EA — 235 — 235 — 170 — 130 MHz

tDVACLKGDDR Data Setup Before CLK ECP3-35EA — 0.210 — 0.210 — 0.210 — 0.210 UI

tDVECLKGDDR Data Hold After CLK ECP3-35EA 0.790 — 0.790 — 0.790 — 0.790 — UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-35EA — 235 — 235 — 170 — 130 MHz

tDVACLKGDDR Data Setup Before CLK ECP3-17EA — — — 0.210 — 0.210 — 0.210 UI

tDVECLKGDDR Data Hold After CLK ECP3-17EA — — 0.790 — 0.790 — 0.790 —UI

fMAX_GDDR DDRX2 Clock Frequency ECP3-17EA — — — 235 —170 —130 MHz

LatticeECP3 External Switching Characteristics (Continued)1, 2

Over Recommended Commercial Operating Conditions

Parameter Description Device

-9 -8 -7 -6

UnitsMin. Max. Min. Max. Min. Max. Min. Max.

3-20

DC and Switching Characteristics

LatticeECP3 Family Data Sheet

Generic DDRX2 Inputs with Clock and Data (>10bits wide) are Aligned at Pin (GDDRX2_RX.ECLK.Aligned)

(No CLKDIV)

Left and Right Sides Using DLLCLKPIN for Clock Input