MM74HC245ASJX - Fairchild Semiconductor

September 1983

Revised May 2005

MM74HC245A Octal 3-STATE Transceiver

MM74HC245A

Octal 3-STATE Transceiver

General Descript ion

The MM74HC245A 3-STATE bidirectional buffer utilizes

advanced silicon-gate CMOS technology, and is intended

for two-way asynchronous communication between data

buses. It has hi gh drive current outputs wh ich enabl e high

speed operation even when driving large bus capaci-

tances. Thi s circuit pos sesses the l ow power consumpt ion

and high noise immunity usually associated with CMOS cir-

cuitry, yet has speeds comparable to low power Schottky

TTL circuits.

This device has an active LOW enable input G and a direc-

tion control in pu t, DIR. When DIR is HIGH, d ata flo ws fro m

the A inputs to the B outputs. When DIR is LOW, data flows

from the B inputs to the A outputs. The MM74HC245A

transfers true data from one bus to the other.

This device can drive up to 15 LS-TTL Loads, and does not

have Schmitt trigger inputs. All inputs are protected from

damage due to static discharge by diodes to VCC and

ground.

Features

■Typical propagation delay: 13 ns

■Wide power supply range: 2–6V

■Low quiescent current: 80

A maximum ( 74 HC)

■3-STATE outputs for connection to bus oriented systems

■High output drive: 6 mA (minimum)

■Same as the 645

Ordering Code:

Devices also available in Tape and R eel. Specify by appending th e s uffix let t er “X” to th e ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Truth Table

HIGH Level

LOW Le vel

Irrelevant

Order Number Package Number Package Description

MM74HC245AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC245ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC245AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC245AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Control

Inputs Operation

GDIR

L L B data to A bus

L H A data to B bus

HX Isolation

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MM74HC245A

Logic Diagram

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MM74HC245A

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Maximu m Ratings are those v alues beyo nd which damage to t he

device may occur.

Note 2: Unl es s ot herwise s pecified all v olt ages are ref erenced t o ground.

Note 3: Power Dis sipation tem perature d erating — plastic “N” package:



12 mW/

C from 65

C to 85

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V

10% the worst case output voltages (VOH, and V OL) occ ur for HC at 4.5V. Thus the 4. 5V valu es shoul d be use d when

designi ng with t his s upply. Worst c as e VIH and VIL occur at VCC

5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occur fo r C M OS at the h i gher voltag e and so the 6 .0 V v alues sho uld be used.

Supply Voltage (VCC)



0.5 to



7.0V

DC Input Voltage DIR and G pins (VIN)



1.5 to VCC



1.5V

DC Input/Output Voltage (VIN, VOUT)



0.5 to VCC



0.5V

Clamp Diode Current (ICD)

20 mA

DC Output Current, per pin (IOUT)

35 mA

DC VCC or GND Current, per pin (ICC)

70 mA

Storage Temperature Range (T STG)



C to



150

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 260

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN, VOUT)0V

CC V

Operati ng Temper atu re Ran ge (TA)





Input Rise/Fall Times

(tr, tf) V

2.0V 1000 ns

VCC

4.5V 500 ns

VCC

6.0V 400 ns

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V

Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V

Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level Output VIN

VIH or VIL

Voltage |IOUT|

A 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN

VIH or VIL

|IOUT|

6.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT|

7.8 mA 6.0V 5.7 5.48 5.34 5.2 V

VOL Maximum LOW Level Output VIN

VIH or VIL

Voltage |IOUT|

A 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN

VIH or VIL

|IOUT|

6.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT|

7.8 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Input Leakage VIN

VCC to GND 6.0V

0.1

1.0

Current (G and DIR)

IOZ Maximum 3-STATE Output VOUT

VCC or GND 6.0V

0.5

5.0

Leakage Current Enable G

VIH

ICC Maximum Quiescent Supply VIN

VCC or GND 6.0V 8.0 80 160

Current IOUT

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MM74HC245A

AC Electrical Characteristi cs

VCC

5V, TA

C, tr

6ns

AC Electrical Characteristi cs

VCC

2.0V to 6.0V, CL

50 pF, tr

6ns (unless otherwise specified)

Note 5: CPD determines the no load dynamic power consumption, PD

CPD VCC2 f



ICC VCC, and the no load dynamic current consumption, IS

CPDVCCf



ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

tPHL, tPLH Maximum Propagation Delay CL

45 pF 12 17 ns

tPZH, tPZL Maximum Output Enable RL

1 k

24 35 ns

Time CL

45 pF

tPHZ, tPLZ Maximum Output Disable RL

1 k

18 25 ns

Time CL

5 pF

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Guar ant eed Lim i ts

tPHL, Maximum Propagation CL

50 pF 2.0V 31 90 113 135 ns

tPLH Delay CL

150 pF 2.0V 41 96 116 128 ns

50 pF 4.5V 13 18 23 27 ns

150 pF 4.5V 17 22 28 33 ns

50 pF 6.0V 11 15 19 23 ns

150 pF 6.0V 14 19 23 28 ns

tPZH, Maximum Output Enable RL

1 k

tPZL Time CL

50 pF 2.0V 71 190 240 285 ns

150 pF 2.0V 81 240 300 360 ns

50 pF 4.5V 26 38 48 57 ns

150 pF 4.5V 31 48 60 72 ns

50 pF 6.0V 21 32 41 48 ns

150 pF 6.0V 25 41 51 61 ns

tPHZ, Maximum Output Disable RL

1 k

2.0V 39 135 169 203 ns

tPLZ Time CL

50 pF 4.5V 20 27 34 41 ns

6.0V 18 23 29 34 ns

tTLH, tTHL Output Rise and Fall Time CL

50 pF 2.0V 20 60 75 90 ns

4.5V 6 12 15 18 ns

6.0V 5 10 13 15 ns

CPD Power Dissipation G

VIL 50 pF

Capacitance (Note 5) G

VIH 5pF

CIN Maximum Input Capacitance 5 10 10 10 pF

CIN/OUT Maximum Input/Output 15 20 20 20 pF

Capacitance, A or B

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MM74HC245A

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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MM74HC245A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ T YPE II, 5.3mm Wide

Package Number M20D

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MM74HC245A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

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MM74HC245A Oct al 3-STATE Transceiver

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

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device or system, or to affect its safety or effectiveness.