SEMICONDUCTOR
3-1
November 1996
CA5160, CA5160A
4MHz, BiMOS Microprocessor Operational
Amplifiers with MOSFET Input/CMOS Output
Features
• MOSFET Input Stage
- Very High ZI; 1.5TΩ (1.5 x 1012Ω) (Typ)
- Very Low II; 5pA (Typ) at 15V Operation
2pA (Typ) at 5V Operation
• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be
Swung 0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails
• CA5160A, CA5160 Have Full Military Temperature
Range Guaranteed Specifications for V+ = 5V
• CA5160A, CA5160 Are Guaranteed to Operate Down
to 4.5V for AOL
• CA5160A, CA5160 Are Guaranteed Up to ±7.5V
Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long Duration Timers/Monostables
• Ideal Interface With Digital CMOS
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)
• Wien-Bridge Oscillators
• Voltage Controlled Oscillators
• Photo Diode Sensor Amplifiers
• 5V Logic Systems
• Microprocessor Interface
Description
CA5160A and CA5160 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA5160 series
circuits are frequency compensated versions of the popular
CA5130 series. They are designed and guar anteed to operate
in microprocessor or logic systems that use +5V supplies.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input impedance,
very low input current, and exceptional speed performance.
The use of PMOS field effect transistors in the input stage
results in common-mode input voltage capability do wn to 0.5V
below the negative supply terminal, an important attribute in
single supply applications.
A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is emplo yed as the output circuit.
The CA5160 Series circuits operate at supply voltages rang-
ing from +5V to +16V, or ±2.5V to ±8V when using split sup-
plies, and have terminals for adjustment of offset voltage for
applications requiring offset-null capability. Terminal provi-
sions are also made to permit strobing of the output stage.
They ha v e guaranteed specifications for 5V oper ation ov er the
full military temperature r ange of -55oC to 125oC.
Pinouts
Ordering Information
PART NUMBER
(BRAND) TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CA5160AE -55 to 125 8 Ld PDIP E8.3
CA5160AM (5160A) -55 to 125 8 Ld SOIC M8.15
CA5160M (5160) -55 to 125 8 Ld SOIC M8.15
CA5160E -55 to 125 8 Ld PDIP E8.3
CA5160T -55 to 125 8 Pin Metal Can T8.C
CA5160 (METAL CAN)
TOP VIEW CA5160A, CA5160 (PDIP, SOIC)
TOP VIEW
NOTE: CA5160 Series devices ha ve an on-chip frequency compensation netw ork. Supplementary phase-compensation or frequency roll-off (if desired) can be
connected e xternally between terminals 1 and 8.
OUTPUT
INV. INPUT
OFFSET NULL
NON INV. INPUT
V+
4
3
8
OFFSET NULL
V- AND CASE
TAB
2
1
5
7
STROBE
SUPPLEMENTARY
+
-
COMPENSATION
6NON INV. INPUT
V-
1
2
3
8
7
6
5
STROBE
V+
OUTPUT
OFFSET NULL
OFFSET NULL
4
INV. INPUT
+
-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996 File Number 1924.3
NOT RECOMMENDED FOR NEW DESIGNS
3-2
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA
Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A
SOIC Package. . . . . . . . . . . . . . . . . . . 165 N/A
Metal Can Package . . . . . . . . . . . . . . . 165 80
Maximum J unction Temperature (Metal Can Package). . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications TA = 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified
PARAMETER SYMBOL TEST
CONDITIONS
CA5160 CA5160A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage VIO VO = 2.5V - 2 10 - 1.5 4 mV
Input Offset Current IIO VO = 2.5V D- 0.1 10 - 0.1 5 pA
Input Current IIVO= 2.5V - 2 15 - 2 10 pA
Common Mode Rejection Ratio CMRR VCM = 0 to 1V 70 80 - 75 87 - dB
VCM = 0 to 2.5V 60 69 - 60 69 - dB
Common Mode Input Voltage Range VlCR+ 2.5 2.8 - 2.5 2.8 - V
VlCR- - -0.5 0 - -0.5 0 V
Power Supply Rejection Ratio PSRR ∆V+ = 1V; ∆V- = 1V 55 67 - 60 75 - dB
Large Signal Voltage
Gain (Note 3) VO = 0.1 to 4.1V AOL RL=∞95 117 - 100 117 - dB
VO = 0.1 to 3.6V RL=10kΩ85 102 - 90 102 - dB
Source Current ISOURCE VO = 0V 1.0 3.4 4.0 1.0 3.4 4.0 mA
Sink Current ISINK VO = 5V 1.0 2.2 4.0 1.0 2.2 4.0 mA
Maximum Output Voltage VOM+V
OUT RL = ∞4.99 5 - 4.99 5 - V
VOM- - 0 0.01 - 0 0.01 V
VOM+R
L
= 10kΩ4.4 4.7 - 4.4 4.7 - V
VOM- - 0 0.01 - 0 0.01 V
VOM+R
L
= 2kΩ2.5 3.3 - 2.5 3.3 - V
VOM- - 0 0.01 - 0 0.01 V
Supply Current ISUPPLY VO = 0V - 50 100 - 50 100 µA
ISUPPLY VO = 2.5V - 320 400 - 320 400 µA
NOTE:
3. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ.
Electrical Specifications TA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified
PARAMETER SYMBOL TEST
CONDITIONS
CA5160 CA5160A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage VIO VO= 2.5V - 3 15 - 2 10 mV
Input Offset Current IIO VO= 2.5 V - 0.1 10 - 0.1 5 nA
CA5160, CA5160A
3-3
Input Current IIVO= 2.5V - 2 15 - 2 10 nA
Common Mode Rejection Ratio CMRR VCM = 0 to 1V 60 80 - 60 80 - dB
VCM = 0 to 2.5V 50 75 - 55 80 - dB
Common Mode Input Voltage Range VlCR+ 2.5 2.8 - 2.5 2.8 - V
VlCR- - -0.5 0 - -0.5 0 V
Power Supply Rejection Ratio PSRR ∆V+ = 2V 40 60 - 45 65 - dB
Large Signal Voltage
Gain (Note 4) VO = 0.1 to 4.1V AOL RL=∞90 110 - 94 110 - dB
VO = 0.1 to 3.6V RL=10kΩ75 100 - 80 100 - dB
Source Current ISOURCE VO = 0V 0.6 - 5.0 0.6 2.2 5.0 mA
Sink Current ISINK VO = 5V 0.6 - 5.0 0.6 1.15 5.0 mA
Maximum Output Voltage VOM+V
OUT RL=∞4.99 5 - 4.99 5 - V
VOM- - 0 0.01 - 0 0.01 V
VOM+R
L
= 10kΩ4.0 4.3 - 4.0 4.3 - V
VOM- - 0 0.01 - 0 0.01 V
VOM+R
L
= 2kΩ2.0 2.5 - 2.0 2.5 - V
VOM- - 0 0.01 - 0 0.01 V
Supply Current VO = 0V ISUPPLY - 170 220 - 170 220 µA
VO = 2.5V ISUPPLY - 410 500 - 410 500 µA
NOTE:
4. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ.
Electrical Specifications TA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST
CONDITIONS
CA5160 CA5160A
UNITSMIN TYP MAX MIN TYP MAX
Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified
PARAMETER SYMBOL TEST
CONDITIONS
CA5160 CA5160A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage VIO VS=±7.5V - 6 15 - 2 5 mV
Input Offset Current IIO VS=±7.5V - 0.5 30 - 0.5 20 pA
Input Current IIVS=±7.5V - 5 50 - 5 30 pA
Large Signal Voltage Gain AOL VO = 10VP-P
RL = 2kΩ50 320 - 50 320 - kV/V
94 110 - 94 110 - dB
Common Mode Rejection Ratio CMRR 70 90 - 80 95 - dB
Common Mode Input Voltage Range VlCR 10 -0.5 to
12 0 10 -0.5 to
12 0V
Power Supply Rejection Ratio PSRR ∆V+ = 1V; ∆V- = 1V
VS = ±7.5V - 32 320 - 32 150 µV/V
Maximum Output
Voltage VOM+V
OUT RL = 2kΩ12 13.3 - 12 13.3 - V
VOM- - 0.002 0.01 - 0.002 0.01 V
VOM+R
L
= ∞14.99 15 - 14.99 15 - V
VOM- - 0 0.1 - 0 0.01 V
CA5160, CA5160A
3-4
Block Diagram
Maximum Output
Current IOM+ (Source) IOVO = 0V 12 22 45 12 22 45 mA
IOM- (Sink) VO = 15V 12 20 45 12 20 45 mA
Supply Current I+ RL = ∞, VO = 7.5V - 10 15 - 10 15 mA
RL = ∞, VO = 0V - 2 3 - 2 3 mA
Input Offset Voltage Temperature Drift ∆VIO/∆T -8--6-µV/oC
Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST
CONDITIONS
CA5160 CA5160A
UNITSMIN TYP MAX MIN TYP MAX
Electrical Specifications For Design Guidance, At TA = 25oC, VSUPPLY = ±7.5V, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
TYPICAL VALUES
UNITSCA5160 CA5160A
Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or 4 and 1 ±22 ±22 mV
Input Resistance RI1.5 1.5 TΩ
Input Capacitance CIf = 1MHz 4.3 4.3 pF
Equivalent Input Noise Voltage eNBW = 0.2MHz, RS = 1MΩ40 40 µV
BW = 0.2MHz, RS = 10MΩ50 50 µV
Equivalent Input Noise Voltage eNRS = 100Ω, 1kHz 72 72 nV/√Hz
RS = 100Ω, 10kHz 30 30 nV/√Hz
Unity Gain Crossov er F requency fT4 4 MHz
Slew Rate SR 10 10 V/µs
Transient Response Rise Time tRCC = 25pF, RL = 2kΩ(Voltage Follower) 0.09 0.09 µs
Overshoot OS 10 10 %
Settling Time (To <0.1%, VIN = 4VP-P)t
S
C
C
= 25pF, RL = 2kΩ, (Voltage Follower) 1.8 1.8 µs
BIAS CKT.
200µA 1.35mA 200µA
3
2
8
4
6
8mA
(NOTE 5)
OUTPUT
AV≈30X
AV≈
6000X
STROBE
V-
V+
OFFSET
NULL
COMPENSATION
(WHEN DESIRED)
+
-
INPUT AV≈5X
CC
NOTE:
5. Total supply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.
6. Total supply voltage (f or indicated voltage
gains) = 15V with output terminal driven to
either supply rail.
5 1
0mA
(NOTE 6)
7
CA5160, CA5160A
3-5
Schematic Diagram
Application Information
Circuit Description
Ref er to the b loc k diagr am of the CA5160 series CMOS Oper-
ational Amplifiers. The input terminals may be operated down
to 0.5V below the negative supply rail, and the output can be
swung very close to either supply rail in many applications.
Consequently, the CA5160 series circuits are ideal for single
supply operation. Three class A amplifier stages, having the
individual gain capability and current consumption shown in
the block diagram, provide the total gain of the CA5160. A
biasing circuit provides two potentials for common use in the
first and second stages. Terminals 8 and 1 can be used to
supplement the internal phase compensation network if addi-
tional phase compensation or frequency roll-off is desired.
Terminals 8 and 4 can also be used to strobe the output stage
into a low quiescent current state. When Ter minal 8 is tied to
the negative supply rail (Ter minal 4) by mechanical or electri-
cal means, the output potential at Terminal 6 essentially r ises
to the positive supply rail potential at Terminal 7. This condi-
tion of essentially zero current drain in the output stage under
the strobed “OFF” condition can only be achieved when the
ohmic load resistance presented to the amplifier is very high
(e.g., when the amplifier output is used to drive CMOS digital
circuits in comparator applications).
Input Stages
The circuit of the CA5160 is shown in the schematic diagram.
It consists of a differential input stage using PMOS field effect
transistors (Q6, Q7) working into a mirror pair of bipolar tran-
sistors (Q9, Q10) functioning as load resistors together with
resistors R3 through R6. The mirror pair transistors also func-
tion as a diff erential-to-single-ended con v erter to provide base
drive to the second-stage bipolar transistor (Q11). Offset null-
ing, when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the potentiome-
ter slider arm to Terminal 4.
Cascode-connected PMOS transistors Q2, Q4, are the
constant current source for the input stage. The biasing
circuit for the constant current source is subsequently
described. The small diodes D5 through D7 provide gate-
oxide protection against high voltage transients, including
static electricity during handling for Q6 and Q7.
Second Stage
Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascode-connected load resistance provided by
7
4815
2
3
BIAS CIRCUIT “CURRENT SOURCE
LOAD” FOR Q11
Q2
D1
D2
D3
D4
Z1
8.3V
Q1
R1
40kΩ
Q4
R2
5kΩ
INPUT STAGE
D5
NON-INV.
INPUT
INV. INPUT
+
-
Q6
R3
1kΩ
Q9Q10
R5
1kΩR6
1kΩ
R4
1kΩ
Q7
D6D7
Q3
OFFSET NULL
Q11
SUPPLEMENTARY
COMP IF DESIRED STROBING
SECOND
OUTPUT Q8
Q12
STAGE
STAGE
Q5
V+
2kΩ
30
pF
6
OUTPUT
CURRENT SOURCE
FOR Q6 AND Q7
NO TE: Diodes D5 through D7 pro vide gate o xide protection f or MOSFET Input Stage.
CA5160, CA5160A
3-6
PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is described later. Miller Effect
compensation (roll off) is accomplished by means of the
30pF capacitor and 2kΩ resistor connected between the
base and collector of transistor Q11. These internal compo-
nents provide sufficient compensation for unity gain opera-
tion in most applications. However, additional compensation,
if desired, may be used between Terminals 1 and 8.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2
and zener diode Z 1 serve to estab lish a v oltage of 8.3V across
the series connected circuit, consisting of resistor R1, diodes
D1 through D4, and PMOS transistor Q1. A tap at the junction
of resistor R1 and diode D4 provides a gate bias potential of
about 4.5V for PMOS transistors Q4 and Q5 with respect to
Terminal 7. A potential of about 2.2V is developed across
diode connected PMOS transistor Q1 with respect to Terminal
7 to provide gate bias for PMOS transistors Q2 and Q3. It
should be noted that Q1 is “mirror connected” to both Q2 and
Q3. Since transistors Q1, Q2 and Q3 are designed to be iden-
tical, the approximately 200µA current in Q1 establishes a
similar current in Q2 and Q3 as constant current sources for
both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z1 becomes non-conductive and the potential, developed
across series connected R1, D1-D4, and Q1 varies directly
with variations in supply voltage. Consequently, the gate bias
for Q4, Q5 and Q2, Q3 varies in accordance with supply
voltage variations. This variation results in deterioration of the
power supply rejection ration (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
Output Stage
The output stage consists of a drain loaded inver ting ampli-
fier using CMOS transistors operating in the Class A mode.
When operating into very high resistance loads, the output
can be swung within millivolts of either supply rail. Because
the output stage is a drain loaded amplifier, its gain is depen-
dent upon the load impedance. The transfer characteristics
of the output stage for a load returned to the negative supply
rail are shown in Figure 20. Typical op-amp loads are readily
driven by the output stage. Because large signal excursions
are nonlinear, requiring feedback for good waveform repro-
duction, transient delays may be encountered. As a voltage
follower, the amplifier can achieve 0.01% accuracy levels,
including the negative supply rail.
Offset Nulling
Offset voltage nulling is usually accomplished with a 100,000Ω
potentiometer connected across Terminals 1 and 5 and with the
potentiometer slider arm connected to Terminal 4. A fine offset
null adjustment usually can be aff ected with the slider arm posi-
tioned in the mid point of the potentiometer’s total range .
Input Current Variation with Common Mode Input Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA5160 Series Op Amps is typically 5pA at
TA = 25oC when Ter minals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal
4. Figure 1 contains data showing the variation of input
current as a function of common-mode input voltage at
TA=25
o
C. These data show that circuit designers can
advantageously exploit these characteristics to design
circuits which typically require an input current of less than
1pA, provided the common-mode input voltage does not
exceed 2V. As previously noted, the input current is
essentially the result of the leakage current through the gate-
protection diodes in the input circuit and, therefore, a
function of the applied voltage. Although the finite resistance
of the glass terminal-to-case insulator of the metal can
package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate-
protection network functions as if it is connected to Ter minal
4 potential, and the metal can case of the CA5160 is also
internally tied to Terminal 4, input terminal 3 is essentially
“guarded” from spurious leakage currents.
Input Current Variation with Temperature
The input current of the CA5160 series circuits is typically
5pA at 25oC . The major portion of this input current is due to
leakage current through the gate protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the
leakage current approximately doubles for every 10oC
increase in temperature. Figure 2 provides data on the
typical variation of input bias current as a function of
temperature in the CA5160.
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA5160. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat-
sinking can also very markedly reduce and stabilize input
current variations.
10
7.5
5
2.5
0-101234567
INPUT CURRENT (pA)
INPUT VOLTAGE (V)
TA = 25oC
15V
TO
5V
V+
V-
0V
TO
-10V
CA5160
2
3
6
7
8
4
PA
VIN
FIGURE 1. CA5160 INPUT CURRENT vs COMMON MODE
VOLTAGE
CA5160, CA5160A
3-7
Input Offset Voltage (VIO) Variation with DC Bias vs
Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magni-
tude of the change is increased at high temperatures. Users
of the CA5160 should be aler t to the possible impacts of this
effect if the application of the device involves extended opera-
tion at high temperatures with a significant differential DC bias
voltage applied across Terminals 2 and 3. Figure 3 shows typ-
ical data per tinent to shifts in offset voltage encountered with
CA5160 devices in metal can packages during life testing. At
lower temperatures (metal can and plastic) for example at
85oC , this change in v oltage is considerab ly less. In typical lin-
ear applications where the differential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
amplifier emplo ying a bipolar tr ansistor input stage . The 2VDC
differential voltage example represents conditions when the
amplifier output state is “toggled”, e.g., as in compar ator appli-
cations.
Power Supply Considerations
Because the CA5160 is very useful in single-supply applica-
tions, it is pertinent to review some considerations relating to
power-supply current consumption under both single-and
dual-supply service. Figures 4A and 4B show the CA5160
connected for both dual and single-supply operation.
Dual-supply Operation: When the output voltage at Ter mi-
nal 6 is 0V, the currents supplied by the two power supplies
are equal. When the gate terminals of Q8 and Q12 are
driven increasingly positive with respect to ground, current
flow through Q12 (from the negative supply) to the load is
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
Single Supply Operation: Initially, let it be assumed that the
value of RL is ver y high (or disconnected), and that the input-
terminal bias (Terminals 2 and 3) is such that the output termi-
nal (Number 6) voltage is at V+/2, i.e., the voltage-drops
across Q8 and Q12 are of equal magnitude. Figure 21 shows
typical quiescent supply-current vs supply-voltage for the
CA5160 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage transfer characteristics (see Figure 20). If either
Q8 or Q12 are swung out of their linear regions toward cutoff
(a nonlinear region), there will be a corresponding reduction in
supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
transistor Q12 is completely cut off and the supply-current to
series-connected transistors Q8, Q12 goes essentially to z ero.
The two preceding stages in the CA5160, however, continue
to draw modest supply-current (see the lower curve in Figure
21) even through the output stage is strobed off. Figure 4A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming RL = ∞, by pulling the
potential of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 4B. Let it further be assumed
again that the input terminal bias (Terminals 2 and 3) is such
that the output terminal (Number 6) voltage is V+/2. Since
PMOS transistor Q8 must now supply quiescent current to
both RL and transistor Q12, it should be apparent that under
these conditions the supply current must increase as an
inverse function of the RL magnitude. Figure 27 shows the
voltage drop across PMOS transistor Q8 as a function of
load current at several supply voltages. Figure 20 shows the
voltage transfer characteristics of the output stage for sev-
eral values of load resistance.
VS = ±7.5V
4000
1000
100
10
1-80 -60 -40 -20 0 20 40 60 80 100 120 140
INPUT CURRENT (pA)
TEMPERATURE (oC)
FIGURE 2. INPUT CURRENT vs TEMPERATURE
TA = 125oC FOR METAL CAN PACKAGES
7
6
5
4
3
2
1
0 500 1000 1500 2000 2500 3000 3500 4000
OFFSET VOLTAGE SHIFT (mV)
TIME (HOURS)
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+/2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
0
FIGURE 3. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
CA5160, CA5160A
3-8
Wideband Noise
From the standpoint of low-noise performance consider-
ations, the use of the CA5160 is most adv antageous in appli-
cations where in the source resistance of the input signal is
on the order of 1MΩ or more. In this case, the total input-
referred noise voltage is typically only 40µV when the test-
circuit amplifier of Figure 5 is operated at a total supply volt-
age of 15V. This value of total input-referred noise remains
essentially constant, even though the value of source resis-
tance is raised by an order of magnitude. This characteristic
is due to the fact that reactance of the input capacitance
becomes a significant factor in shunting the source resis-
tance. It should be noted, however, that for values of source
resistance very much greater than 1MΩ, the total noise volt-
age generated can be dominated by the ther mal noise con-
tributions of both the feedback and source resistors.
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like
the CA5160, are particularly suited to service as voltage
followers. Figure 6 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA5160 in a split supply-configuration.
A voltage follower, operated from a single-supply, is shown in
Figure 7 together with related waveforms. This follower circuit
is linear over a wide dynamic range, as illustrated by the
reproduction of the output waveform in Figure 7B with input
signal ramping. The waveforms in Figure 7C show that the
follower does not lose its input-to-output phase-sense, even
though the input is being swung 7.5V below ground potential.
This unique characteristic is an important attribute in both
operational amplifier and comparator applications. Figure 7C
also shows the manner in which the CMOS output stage
permits the output signal to swing down to the negative supply
rail potential (i.e., ground in the case shown). The digital-to-
analog converter (DAC) circuit, described in the following
section, illustrates the practical use of the CA5160 in a single-
supply voltage follo wer application.
3
2
8
4
7
6
RL
Q8
Q12
+
-
OUTPUT
STAGE
FIGURE 4A. DUAL POWER-SUPPLY OPERATION
V+
V-
3
2
8
4
7
6
RL
Q8
Q12
+
-
OUTPUT
STAGE
FIGURE 4B. SINGLE POWER-SUPPLY OPERATION
FIGURE 4. CA5160 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
V+
6
7
3
4
2
+7.5V
0.01µF
NOISE
VOLTAGE
OUTPUT
30.1kΩ
0.01
µF
1kΩ
-7.5V
RS
1MΩ+
-
BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE
(INPUT REFERRED) = 40µV (TYP)
FIGURE 5. TEST-CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENTS
6
7
3
4
2
+7.5V
0.01µF
0.01
µF
-7.5V
10kΩ+
-2kΩ
25pF
SIMULATED
LOAD
CAPACITANCE
0.1µF
BW (-3dB) = 4MHz
SR = 10V/µs
2kΩ
FIGURE 6A. DUAL SUPPLY FOLLOWER
CA5160, CA5160A
3-9
9 Bit CMOS DAC
A typical circuit of a 9 bit Digital-to-Analog Converter (DAC) (see
Note) is shown in Figure 8. This system combines the concepts
of multiple-switch CMOS ICs, a low cost ladder network of dis-
crete metal-oxide-film resistors , a CA5160 op amp connected as
a follower, and an inexpensive monolithic regulator in a simple
single power supply arrangement. An additional feature of the
DAC is that it is readily interfaced with CMOS input logic, e.g.,
10V logic levels are used in the circuit of Figure 8.
The circuit uses an R/2R voltage-ladder network, with the output-
potential obtained directly by terminating the ladder arms at either
the positive or the negative power-supply terminal. Each CD4007A
contains three “inverters”, each “inverter” functioning as a single-
pole double-throw switch to terminate an arm of the R/2R network
at either the positive or negative power-supply terminal. The resis-
tor ladder is an assembly of 1% tolerance metal-oxide film resis-
tors. The five arms requiring the highest accuracy are assembled
with series and parallel combinations of 806,000Ω resistors from
the same manuf acturing lot.
A single 15V supply provides a positive bus for the CA5160 fol-
lower amplifier and feeds the CA3085 voltage regulator. A “scale-
adjust” function is provided by the regulator output control, set to
a nominal 10V level in this system. The line-voltage regulation
(approximately 0.2%) permits a 9 bit accuracy to be maintained
with variations of se ver al volts in the supply. The flexibility aff orded
by the CMOS building blocks simplifies the design of DAC sys-
tems tailored to particular needs.
Error Amplifier in Regulated Power Supplies
The CA5160 is an ideal choice for error-amplifier service in regu-
lated power supplies since it can function as an error-amplifier
when the regulated output voltage is required to approach 0V.
The circuit shown in Figure 9 uses a CA5160 as an error ampli-
fier in a continuously adjustab le 1A pow er supply. One of the key
features of this circuit is its ability to regulate down to the vicinity
of zero with only one DC power supply input.
An RC network, connected between the base of the output drive
transistor and the input voltage, prevents “turn-on overshoot”, a
condition typical of many operational-amplifier regulator circuits.
As the amplifier becomes operational, this RC network ceases
to have influence on the regulator performance.
NOTE: “Digital-to-Analog Conversion Using the Harris
CD4007A CMOS IC”, Application Note AN6080.
FIGURE 6B. SMALL SIGNAL RESPONSE
Top Trace: Output
Bottom Trace: Input
Top Trace: Output Signal
Center Trace: Difference Signal 5mV/Div.
Bottom Trace: Input Signal
FIGURE 6C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
FIGURE 6. SPLIT SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS
6
7
3
4
2
+15V
0.01µF
10kΩ+
-
0.1µF
15
2kΩ
OFFSET
ADJUST
100kΩ
FIGURE 7A. SINGLE SUPPLY FOLLOWER
0
FIGURE 7B. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING
CA5160, CA5160A
3-10
Precision Voltage-Controlled Oscillator
The circuit diagram of a precision voltage-controlled oscillator is
shown in Figure 10. The oscillator operates with a tracking error
on the order of 0.02% and a temperature coefficient of
0.01%/oC. A multivibrator (A1) generates pulses of constant
amplitude (V) and width (T2). Since the output (Terminal 6) of A1
(a CA5130) can swing within about 10mV of either supply-rail,
the output pulse amplitude (V) is essentially equal to V+. The
average output voltage (EAVG =V T
2
/T1) is applied to the non-
inverting input terminal of comparator A2 (a CA5160) via an
integrating network R3, C2. Comparator A 2 operates to estab lish
circuit conditions such that EAVG = V1. This circuit condition is
accomplished by feeding an output signal from Ter minal 6 of A2
through R4, D4 to the inverting terminal (Terminal 2) of A1,
thereby adjusting the multivibrator interval, T3.
Voltmeter With High Input Resistance
The voltmeter circuit shown in Figure 11 illustrates an
application in which a number of the CA5160 characteristics are
exploited. Range-switch SW1 is ganged between input and
output circuitry to permit selection of the proper output voltage
for feedback to Terminal 2 via 10kΩ current-limiting resistor. The
circuit is powered by a single 8.4V mercury battery. With zero
input signal, the circuit consumes somewhat less than 500µA
plus the meter current required to indicate a given v oltage . Thus,
at full-scale input, the total supply current rises to slightly more
than 1500µA.
0
0
Top Trace: Output
Bottom Trace: Input
FIGURE 7C. OUTPUT-WAVEFORM WITH GROUND-REFERENCE
SINE-WAVE INPUT
FIGURE 7. SINGLE SUPPLY V OLT AGE FOLLOWER WITH
ASSOCIATED WAVEFORMS (e.g., FOR USE IN
SINGLE-SULLPL D/A CONVERTER; SEE FIGURE 9
IN AN6080)
CA3085
1
2
6
3
0.001µF
47
6
13
8
1
5
12
CD4007A
“SWITCHES”
103
14
11
2
9
4
7
806K
1% 402K
1% 200K
1%
806K
1%
6
13
8
1
5
12
CD4007A
“SWITCHES”
103
100K
1%
(2)
806K
6
13
8
12
CD4007A
“SWITCHES”
103
806K
1% 806K
1% 1%
(4)
806K
1%
(8)
806K
1%
1
5
806K
1% 750K
1%
10V LOGIC INPUTS
PARALLELED
RESISTORS
+10.010V
LSB MSB
987 654 321
8
+10.010V
22.1K
1%
1K
3.83K
1%
2µF
25V
+
-
+15V 62
VOLTAGE
REGULATOR
REGULATED
VOLTAGE
ADJUST
CA5160
3
42
0.1µF
+
-
1
5
6
2K
+15V
100K
VOLTAGE
FOLLOWER
7
OFFSET
NULL
OUTPUT
LOAD
10K
BIT REQUIRED RATIO-
MATCH
1 Standard
2±0.1%
3±0.2%
4±0.4%
5±0.8%
6 - 9 ±1% ABS.
FIGURE 8. 9 BIT DAC USING CMOS DIGITAL SWITCHES AND CA5160
CA5160, CA5160A
3-11
FIGURE 9. CA5160 VOLTAGE REGULATOR CIRCUIT (0.1 TO 35V AT 1A)
FIGURE 10. VOLTAGE CONTROLLED OSCILLATOR
5
4
1
6
7
8
+
-2
3
1
2
3
INPUT 40V
+
2.4kΩ
1W
100µF
25V CA3086
+
-
+
-
2.2kΩ
5µF
10 11 2 1
93
57
64
12 14
13
0.2µF
TURN
ON
DELAY
100kΩ1.5kΩ
1W
1kΩ
62kΩ
-
2N6385
POWER DARLINGTON SHORT-CIRCUIT CURRENT
LIMIT ADJUSTMENT
1Ω
10kΩ
1kΩ2N2102
1N914 56pF 43kΩ
10kΩ
-
+
OUTPUT
0V 35V
AT 1A
10kΩ
4.7kΩ
0.01µF
8.2
kΩ
100µF
100kΩ50kΩ
2kΩ
-
Hum and Noise Output <250µVRMS; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V
1kΩ
8
4
7
+
-
A1 MULTI-
R5
VIBRATOR
CA5130
2
6
+
-
A2 COM-
PARATOR
CA5160
34
1
27
6
+15V
100K
R6
100K C1
500pF
D1
D2
0.1
µF
R1
182K
100K
10K
fo
EAVG = V T2/T1
R3
1M
0.01µF
1M
R2
10K
VCO CONTROL VOLTAGE (VI)
(0V - 10V)
(SENSITIVITY = 1kHz/V)
C2
0.01µF
D1 - D5 = 1N914 R4 3K
R7
100K
0.01µF
D5
T2T3
V
T1
+15V
D3
D4
+15V
3
5
CA5160, CA5160A
3-12
FIGURE 11. CA5160A HIGH INPUT RESISTANCE DC VOLTMETER
FIGURE 12A. FUNCTION GENERATOR CIRCUIT
300V
100V
30V
10V
1V
300mV
100mV
30mV
10mV
3V
1V
300mV
100mV
30mV
10mV
3V
300V
100V
30V
10V
100MΩ
1.02
SW1A
INPUT
MΩ
CA5160
7
3
4
2
15
6
+
-
30V
10V
3V
1V
300mV
100V
300V
30mV
10mV
100mV
SW1B
SW1C SW1D
M
30V
10V
1V
100V
300V
3V
300mV
30mV
10mV
100mV
9kΩ
900Ω
100Ω
BATTERY
TEST
OFF ON
3 POSITION
SLIDE SWITCH
BATTERY
100kΩ
ZERO
ADJUST
10kΩ
9.1kΩ
1V CAL.
820Ω200Ω
2.7kΩ3V CAL.
500Ω
+9V
BATTERY
500
µF
0-1mA
+
-
0.001
µF
22MΩ
9.9
kΩ
1kΩ
3
7
5
CA3080A
+
-4
2
63
CA5160
+
-
2
7
4
62
CA3080
+
-
3
7
6
5
20pF
8.2kΩ
+7.5V
VOLTAGE-CONTROLLED
CURRENT SOURCE
1kΩ
2MΩ-7.5V
4.7kΩ
-7.5V
SYMMETRY
+7.5V
10kΩ
MAX FREQ
SET
500Ω
FREQ
ADJUST
MIN. FREQ.SET
-7.5V
EXTERNAL
SWEEPING INPUT
10-80pF
C2
100kΩ
7.5V
0.9 - 7pF
C1
6.2kΩ
HIGH
FREQ.
SHAPE
4 - 60pF
C3
BUFFER
VOLTAGE FOLLOWER
+7.5V
0.1µF
CENTERING
100kΩ
430pF
10kΩ
2kΩ
C4
4 - 60pF
HIGH FREQ
LEVEL
ADJUST
6.8MΩ
-7.5V +7.5V
30kΩ
10kΩ
50kΩ
C5
15 - 115pF
0.1
µF
-7.5V
THRESHOLD
DETECTOR
2-1N914
+7.5V
-7.5V
6.2kΩ
4
500Ω
CA5160, CA5160A
3-13
FIGURE 12B. TWO-TONE OUTPUT SIGNAL FROM THE
FUNCTION GENERATOR FIGURE 12C. TRIPLE-TRACE OF THE FUNCTION GENERATOR
SWEEPING TO 1MHz
FIGURE 12. CA5160 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR - 1MHz TO 1Hz
FIGURE 13A. STAIRCASE GENERATOR CIRCUIT
NOTE: A square wave signal modulates the external sweeping
input to produce 1Hz and 1MHz, showing the 1,000,000/1
frequency range of the function generator.
NOTE: The bottom tr ace is the sweeping signal and the top tr ace is
the actual generator output. The center trace displays the 1MHz signal
via delayed oscilloscope triggering of the upper swept output signal.
8
3
2
4
7
CA5130
+
-
62
3
4
7
CA5160
+
-6 3
2
4
7
CA5130
+
-8
6
+15V
100
kΩ1MΩ
+15V
15 - 115pF
FREQ
ADJUST
MULTIVIBRATOR RETRACE INHIBIT
100
kΩ
100
kΩ
MULTIVIBRATOR
STEP HEIGHT
ADJUST
4 - 60pF
8.2kΩ
CHARGE
COMMUTATING
NETWORK
470pF
+15V
INTEGRATOR
STAIRCASE
OUTPUT
10kΩ
2kΩ
1.5
HYSTERESIS SWITCH
+15V
+15V
+15mV TO +10V 51kΩ
100kΩ
5.1kΩ1N914
MΩ
1N914
CA5160, CA5160A
3-14
Function Generator
A function generator having a wide tuning range is shown in
Figure 12. The adjustment range, in excess of 1,000,000/1, is
accomplished by a single potentiometer. Three operational
amplifiers are utilized: a CA5160 as a v oltage f ollow er , a CA3080
as a high-speed comparator, and a second CA3080A as a
programmable current source. Three variable capacitors C1, C2,
and C3 shape the tr iangular signal between 500kHz and 1MHz.
Capacitors C4, C5, and the trimmer potentiometer in ser ies with
C5 maintain essentially constant ( ±10%) amplitude up to 1MHz.
Staircase Generator
Figure 13 shows a staircase generator circuit utilizing three
CMOS operational amplifiers. Two CA5130s are used; one as a
multivibrator, the other as a hysteresis switch. The third ampli-
fier, a CA5160, is used as a linear staircase generator.
STAIRCASE
OUTPUT
2V STEPS
COMPARATOR
OSCILLATOR
Top Trace: Staircase Output 2V Steps
Center Trace: Comparator
Bottom Trace: Oscillator
FIGURE 13B. STAIRCASE GENERATOR WAVEFORM
FIGURE 13. STAIRCASE GENERAT OR CIRCUIT UTILIZING
THREE CMOS OPERATIONAL AMPLIFIERS
4
1
7
CA5160
+
-
6
10MΩ
+15V
100kΩ
10kΩ
5
2
4
6
7
CA3140
+
-
3
1MΩ
M
9.9kΩ5.6kΩ
500-0-500µA
-15V
560kΩ
9.1kΩ
500Ω
100Ω
+15V
10GΩ
10pF
0.1µF
2
0.1µF
3
-15V
FIGURE 14. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH ±3pA FULL SCALE DEFLECTION
FIGURE 15A. SAMPLE AND HOLD CIRCUIT
4
1
7
CA5160
+
-
1MΩ
+15V
100kΩ
5
9.1kΩ
2
0.1µF
3
8
6
0.1µF
2
6
34
CA3080A
+
-
7
5
2
34
CA3140
+
-
7
6
+15V
0.1
µF
39kΩ
2200pF
8.2Ω
1MΩ
100kΩ
27kΩ
STROBE INPUT
500µA
DROOP
ZERO
ADJUST
SAMPLE -
HOLD - 15V
0V
100kΩ
30pF
39kΩ
0.1
µF
1N914
OFFSET
VOLTAGE
ADJUST
8.2kΩ
2kΩ
+15V
CA5160, CA5160A
3-15
Picoammeter Circuit
Figure 14 is a current-to-voltage conver ter configuration uti-
lizing a CA5160 and CA3140 to provide a picoampere meter
for ±3pA full-scale meter deflection. By placing Terminals 2
and 4 of the CA5160 at ground potential, the CA5160 input
is operated in the “guarded mode”. Under this operating con-
dition, even slight leakage resistance present between Ter-
minals 3 and 2 or between Terminals 3 and 4 would result in
0V across this leakage resistance, thus substantially reduc-
ing the leakage current.
If the CA5160 is operated with the same voltage on input
Terminals 3 and 2 as on Terminal 4, a further reduction in the
input current to the less than 1pA level can be achieved as
shown in Figure 1.
To further enhance the stability of this circuit, the CA5160
can be operated with its output (Terminal 6) near ground,
thus markedly reducing the dissipation by reducing the sup-
ply current to the device.
The CA3140 stage serves as a X100 gain stage to provide
the required plus and minus output swing for the meter and
feedback network. A 100-to-1 voltage divider network con-
sisting of a 9.9kΩ resistor in series with a 100Ω resistor sets
the voltage at the 10G Ω resistor (in series with Terminal 3) to
±30mV full-scale deflection. This 30mV signal results from
±3V appearing at the top of the voltage divider network
which also drives the meter circuitry.
By utilizing a switching technique in the meter circuit and in
the 9.9kΩ and 100Ω network similar to that used in the volt-
meter circuit shown in Figure 11, a current range of 3pA to
1nA full scale can be handled with the single 10GΩ resistor.
Single Supply Sample-and-Hold System
Figure 15 shows a single-supply sample-and-hold system
using a CA5160 to provide a high input impedance and an
input-voltage range of 0V to 10V. The output from the input
buffer integrator network is coupled to a CA3080A. The
CA3080A functions as a strobeable current source for the
CA3140 output integrator and storage capacitor. The CA3140
was chosen because of its low output impedance and con-
stant gain-bandwidth product. Pulse “droop” during the hold
inter val can be reduced to zero by adjusting the 100kΩ bias-
voltage potentiometer on the positive input of the CA3140.
This zero adjustment sets the CA3080A output voltage at its
zero current position. In this sample-and-hold circuit it is
essential that the amplifier bias current be reduced to zero to
minimize output signal current during the hold mode. Even
with 320mV at the amplifier bias circuit (Terminal 5) at least
±100pA of output current will be available.
Wien Bridge Oscillator
A simple, single-supply Wien Bridge oscillator using a CA5160
is shown in Figure 16. A pair of parallel-connected 1N914
diodes comprise the gain-setting network which standardizes
the output voltage at approximately 1.1V. The 500Ω potentiom-
eter is adjusted so that the oscillator will always start and the
oscillation will be maintained. Increasing the amplitude of the
FIGURE 15B. SAMPLE AND HOLD WAVEFORM FIGURE 15C. SAMPLE AND HOLD WAVEFORM
FIGURE 15. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V
SAMPLED
OUTPUT
INPUT
SIGNAL
SAMPLING
PULSES
Top Trace: Sampled Output
Center Trace: Input Signal
Bottom Trace: Sampling Pulses
SAMPLED
OUTPUT
0V-
INPUT
0V-
SAMPLING
PULSE
Top Trace: Sampled Output
Center Trace: Input
Bottom Trace: Sampling Pulses
4
CA5160
+
-
7
6
0.01µF
2kΩ
f = 1
2π√(R1 || R2) C1 R3 C2
R1
100kΩ
R3
51kΩ+15V
R2
100kΩC1
10-80pF
680Ω
500Ω
0.1
µF
C2
51pF OUTPUT
f = 100kHz
2% THD AT 1.1VP-P
2-1N914
3
2
+15V
FIGURE 16. SINGLE-SUPPLY WEIN BRIDGE OSCILLATOR
CA5160, CA5160A
3-16
voltage may lower the threshold level for starting and for sus-
taining the oscillation, but will introduce more distortion.
Operation with Output-Stage Power-Booster
The current sourcing and sinking capability of the CA5160 out-
put stage is easily supplemented to provide power-boost capa-
bility. In the circuit of Figure 17, three CMOS transistor-pairs in
a single CA3600 lC arra y are shown parallel-connected with the
output stage in the CA5160. In the Class A mode of CA3600E
shown, a typical device consumes 20mA of supply current at
15V operation. This arrangement boosts the current-handling
capability of the CA5160 output stage by about 2.5X.
The amplifier circuit in Figure 17 employs feedback to estab-
lish a closed-loop gain of 20dB. The typical large-signal-
bandwidth (-3dB) is 190kHz.
Typical Performance Curves
FIGURE 18. OPEN-LOOP V OLT AGE GAIN AND PHASE SHIFT
vs FREQUENCY FIGURE 19. OPEN-LOOP GAIN vs TEMPERATURE
8
CA5160
+
-6
1MΩ
26
3
7
13
3 10
7 4 9
8 5
1
214 11
12
0.01µF
1µF
680kΩ
2kΩ
INPUT
1µF
20kΩ
CA3600 (NOTE)
A = 20dB
LARGE SIGNAL
BW (-3dB) = 190kHz
QN1 QN2 QN3
QP1 QP2 QP3
4
+15V
500µF
50Ω
100mW
AT 10%
THD
-+
NO TE: See File Number 619.
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA5160.
120
100
80
60
40
20
0
OPEN-LOOP VOLTAGE GAIN (dB)
0
50
100
150
200
OPEN-LOOP PHASE (DEGREES)
101102103104105106107108
FREQUENCY (Hz)
VS = ±7.5V
TA = 25oC
CL = 30pF
RL = 2kΩ
φ OL
150
140
130
120
110
100
90
80
-100 -50 0 50 100
OPEN-LOOP VOLTAGE GAIN (dB)
TEMPERATURE (oC)
RL = 2kΩ
CA5160, CA5160A
3-17
FIGURE 20. V OLTA GE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
FIGURE 22. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE FIGURE 23. SUPPLY CURRENT vs OUTPUT VOLTAGE
FIGURE 24. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 25. OUTPUT SWING vs LOAD RESISTANCE
Typical Performance Curves
(Continued)
22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
OUTPUT VOLTAGE [TERMS 4 AND 6] (V)
17.5 2012.5 15107.52.5 50
2.5
7.5
5
10
15
12.5
17.5 SUPPLY VOLTAGE: V+ = 15V, V- = 0V
TA = 25oC
LOAD RESISTANCE = 5kΩ
500Ω
1kΩ2kΩ
0
LOAD RESISTANCE = ∞
TA = 25oC
V- = 0 OUTPUT VOLTAGE BALANCED = V+/2
OUTPUT VOLTAGE HIGH = V+
OR LOW = V-
15
12.5
10
7.5
5
2.5
06 8 10 12 14 16 18
POSITIVE SUPPLY VOLTAGE (V)
QUIESCENT SUPPLY CURRENT (mA)
OUTPUT VOLTAGE = V+/2
V- = 0
14
12
10
8
6
4
2
0 2 4 6 8 10 12 14 16
QUIESCENT SUPPLY CURRENT (mA)
POSITIVE SUPPLY VOLTAGE (V)
TA = -55oC
25oC
125oC
02 2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
1 1.50 0.5
SUPPLY CURRENT (µA)
0
75
150
225
300
375
525
450
600
25oC
125oC
-55oC
V+ = 5V, V- = 0V
567891011
LOAD RESISTANCE (kΩ)
3412
OUTPUT VOLTAGE SWING (V)
0
1
2
3
4
5
7
6
8
125oC
-55oC
V+ = 5V, V- = 0V
25oC
4 6 20 40 80 200 800
LOAD RESISTANCE (kΩ)
10.1
OUTPUT VOLTAGE SWING (V)
0
1
2
3
4
5
7
6
8V+ = 5V, V- = 0V
9
820.60.2
CA5160, CA5160A
3-18
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SEMICONDUCTOR
FIGURE 26. OUTPUT CURRENT vs TEMPERATURE FIGURE 27. V OLTA GE A CROSS PMOS OUTPUT TRANSIST OR
(Q8) vs LOAD CURRENT
FIGURE 28. V OLTA GE A CROSS NMOS OUTPUT TRANSIST OR
(Q12) vs LOAD CURRENT FIGURE 29. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
Typical Performance Curves
(Continued)
20 40 60 80 100 120 140
TEMPERATURE (oC)
-20 0-60 -40
OUTPUT CURRENT (mA)
0
1
2
3
4
5
7
6
8V+ = 5V, V- = 0V
SINK
SOURCE
V- = 0V
TA = 25oC
50
10
1
0.1
0.01
0.001
0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)
VOLTAGE DROP ACROSS PMOS OUTPUT
STAGE TRANSISTOR (Q8) (V)
15V
10V
V+= 5V
V- = 0V
TA = 25oCV+ = 15V
10V
5V
50
10
1
0.1
0.01
0.001
VOLTAGE DROP ACROSS NMOS OUTPUT - STAGE
TRANSISTOR (Q12) (V)
0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)
1000
100
10
INPUT NOISE VOLTAGE (nV/ √Hz)
110
1
102103104105
FREQUENCY (Hz)
TA = 25oC
VS = ±7.5V
1
CA5160, CA5160A
