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FEATURES
10 years minimu m data r et ent io n in the
absence o f exter na l po w er
Dat a is automatically pro tect ed d uring power
loss
D irectly replac es 2k x 8 volatile static RAM
or EEPRO M
Unlim ited write cycles
Low-po wer CMOS
JEDEC standard 24-pin DI P p ackage
Read and wr it e access times of 100 ns
Full ±10% operating range
Optional indust r ial temperatur e range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
24-Pin ENCAPSULAT ED PACK AGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10 - Address Inputs
DQ0-DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+5V)
GND - Ground
DESCRIPTION
The DS1220Y 16k Nonvolat ile SRAM is a 16,384-bit, fully static, nonvolat ile RAM organized as 2048
words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that
constantly monitor VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAM can be used in place of existing 2k x 8 SRAMs directly conforming to
t he popular bytewide 24-pin DIP standard. The DS1220Y a lso matches the pinout of the 2716 EPROM or
the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
micro p ro cesso r interfacing.
14
VCC
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
24
15
23
22
21
20
19
18
17
16
A8
A9
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
DS1220Y
16k Nonvolatile SRAM
NOT RECOMMENDED FOR NEW DESIGNS
www.maxim-ic.com
19-5579; Rev 10/10
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
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READ MODE
The DS1220Y executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
E na b le) a nd
OE
(Output Enable) are act ive ( low). The unique addre ss specified by the 11 address inputs
(A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the
e ig ht dat a out put dr ivers w it hin t ACC (Access T ime) after the la st ad dress input signa l is st able, pr ovid ing
that
CE
and
OE
access times are also satisfied. If
CE
and OE access times are not satisfied, then data
access must be measured fro m t he lat er-occu r r ing s ig nal a nd t he limiting para met er is e ither tCO for
CE
or
tOE for
OE
rather than address acces s.
WRITE MODE
The DS1220Y executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the start of the write
cycle. T he wr ite c ycle is t erminat ed by the ear lier r ising edge o f
CE
or
WE
. All address inputs must be
kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time
(tWR) before a not her c ycle can be initiated. The
OE
control signal should be kept inact ive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active)
then
WE
will disab le the outputs in tODW fro m it s fa lling edge.
DATA RETENTION MODE
The DS1220Y provides fu ll-fu nctio na l c a p a bi lity f o r VCC gr eat er than 4.5 vo lt s and wr ite pr otect s at 4.25
nominal. Data is maintained in the absence of VCC without any additional support circuitry. The
DS1220Y constant ly monit o rs VCC. Sho u ld t he su pp ly vo lt age decay, t he NV SRAM aut o mat ical ly wr it e
protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 3.0 volts, a power switching circuit connects the lit hium energy source to RAM to
ret ain dat a. Dur ing po wer-u p, w he n V CC r ises abo ve ap pro ximat ely 3. 0 vo lt s, t he po wer sw it ching circu it
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume a fter V CC exceeds 4.5 volts.
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pi n R elative to Grou nd -0.3V to +6.0V
Operating T emperature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e -40°C to +85°C
Lead Temperature ( soldering, 10s) +260°C
Note: EDIP is w ave or ha nd soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
speci ficati on is not im pli ed. Exposure to absolute m ax imum rating conditions for ex tended per iods of time may affec t reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Powe r S upply Vo lt age
VCC
4.5
5.0
5.5
V
Input Logic 1
VIH
2.2
VCC
V
Input Logic 0
VIL
0.0
+0.8
V
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC = 5V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage Cu r r ent
I
IL
-1.0
+1.0
µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC
I
IO
-1.0
+1.0
µA
Output Current @ 2.4V
IOH
-1.0
mA
Output Current @ 0.4V
IOL
2.0
mA
St andby Current
CE
=2.2V
I
CCS1
3.0
7.0
mA
St andby Current
CE
=VCC -0.5V
I
CCS2
2.0
4.0
mA
Operating Current t
CYC
= 200ns
(Commercial)
I
CCO1
75
mA
Operating Current t
CYC
=200ns
(Industrial)
I
CCO1
85
mA
Write Protection Voltage
V
TP
4.25
V
CAPACITANCE (TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
10
pF
I nput/O utput C a pacit a nce
CI/O
5
12
pF
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
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AC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC = 5.0V ± 10%)
PARAMETER SYM
DS1220Y-100
UNITS NOTES
MIN
MAX
Re a d Cycle Time
tRC
100
ns
Access Time
tACC
100
ns
OE
to O utp ut Valid
t
OE
50 ns
CE
to O utp ut Valid
t
CO
100
ns
OE
or
CE
to Output Active
tCOE 5 ns 5
Out put High-Z f rom Deselection
t
OD
35
ns
5
Output Hold fro m Address Change
tOH
5
ns
Write Cycle Time
tWC
100
ns
Writ e P ulse Width
t
WP
75
ns
3
A ddress Setup Time
tAW
0
ns
Writ e Recover y Ti me
t
WR1
tWR2
0
10
ns
ns
12
13
Out put High-Z fr om
WE
tODW
35
ns
5
Output Active from
WE
t
OEW
5
ns
5
Da ta Setu p Time
tDS
40
ns
4
Da ta Hold Time
t
DH1
tDH2
0
10
ns
ns
12
13
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
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POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
CE
at VIH before P ower-Down
t
PD
0
µs
11
V
CC
Slew from V
TP
to 0V
t
F
100
µ
s
V
CC
Slew f rom 0V to V
TP
t
R
0
µs
CE
at VIH after Power-Up
t
REC
2
ms
(TA = +25°C)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Expect ed Data Ret ent io n T ime
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a r ead cycle.
2.
OE
= VIH or VIL. If
OE
= VIH during a write cycle, the output buffers remain in a high impedanc e
state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
going high.
4. tDS are measured from the ear lier o f
CE
or
WE
going high.
5. T hese para met er s ar e samp led w ith a 5 pF load and are not 100% t ested.
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
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6. If the
CE
low transition occurs simultaneously with or later than the
WE
low transition in write
cycle 1, t he output buffers remain in a hig h impeda nce stat e during t his period.
7. If the
CE
hig h t rans it io n o ccur s p r ior to or simu lt a ne ou sly w it h t he
WE
high t ransitio n, t he out put
buffers remain in a high impedance st at e dur ing thi s per iod.
8. If
WE
is low or the
WE
low transit io n occurs prior to or simultaneously wit h the
CE
low transition,
the out put buffers re main in a high impedance state dur ing this period.
9. Each DS1220Y is marked with a 4-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected tDR is defined as starting at the date of
manufacture.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, t his rang e is 0°C to 70°C. For indust rial products (IND), this ra nge is -40°C to
+85°C.
11. In a power-dow n c onditio n the volt a ge on any p in may not exceed t he volt age o f VCC .
12. tWR1 , tDH1 ar e measured from
WE
going high.
13. tWR2 , tDH2 ar e measured from
CE
going high.
14. DS1220Y mo dules are reco gnized by Underwriters Laboratories (UL) under file E99151 (R).
DC TEST CONDITIONS
Outputs open.
All voltag es are r efer enced to grou nd.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0-3.0V
Timing Measur ement Referen ce Le vels
Input:1.5V
Output : 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART TEM P RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
DS1220Y-100+
0°C to +70°C
5V ± 10%
24 / 720 EDIP
DS1220Y-100IND+
-40°C to +85°C
5V ± 10%
24 / 720 EDIP
+De note s a lead(Pb)-free/RoHS-compliant package.
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
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PKG
24-PIN
DIM
MIN
MAX
A IN.
MM
1.320
33.53
1.340
34.04
B IN.
MM
0.695
17.65
0.720
18.29
C IN.
MM
0.390
9.91
0.415
10.54
D IN.
MM
0.100
2.54
0.130
3.30
E IN.
MM
0.017
0.43
0.030
0.76
F IN.
MM
0.120
3.05
0.160
4.06
G IN.
MM
0.090
2.29
0.110
2.79
H IN
MM
0.590
14.99
0.630
16.00
J IN.
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.38
0.021
0.53
PACKAGE INFORMATION
For the latest package outline infor mat ion and land patterns, go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
d ifferent suffix c haracter , but the drawing pertains to the package r egar dles s of RoHS stat us.
PACKAGE TYPE PACK AG E CODE OUTLINE NO.
LAND
PATTERN NO.
24 DIP MDT24+3
21-0245
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
Maximr cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim an d t h e D all as l og os are r egis tered trademarks of Maxim Integrated Products, Inc.
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907 Added the Package Inf ormation table; remov ed the DIP module
package drawing and dimens ion t able 7
072808
Added the DIP module package drawing and dimension table
8
10/10
Updated t he soldering in format ion in the Absolute Maximum Ratings
section, removed the unused AC timing specs in the AC Electrical
Characteristics table, updated the Ordering Information table,
updated the Package Information table
1, 3, 4, 7, 8