MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator General Description The MAX9376 is a fully differential, high-speed, LVDS/ anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/ anything-to-LVPECL translator and the other channel is LVDS/anything-to-LVDS translator. The MAX9376's extremely low propagation delay and high speed make it ideal for various high-speed network routing and backplane applications. The MAX9376 accepts any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling standards. LVPECL outputs have sufficient current to drive 50 transmission lines. LVDS outputs conform to the ANSI EIA/TIA-644 LVDS standard. Features Guaranteed 2GHz Switching Frequency Accepts LVDS/LVPECL/Anything Inputs 421ps (typ) Propagation Delays 30ps (max) Pulse Skew 2psRMS (max) Random Jitter Minimum 100mV Differential Input to Guarantee AC Specifications Temperature-Compensated LVPECL Output +3.0V to +3.6V Power-Supply Operating Range >2kV ESD Protection (Human Body Model) The MAX9376 is available in a 10-pin MAX(R) package and operates from a single +3.3V supply over the -40C to +85C temperature range. Ordering Information Applications +Denotes a lead(Pb)-free/RoHS-compliant package. Backplane Logic Standard Translation LVDS-to-LVPECL, LVPECL-to-LVDS Up/Downconverters LANs WANs DSLAMs DLCs PART MAX9376EUB+ TEMP RANGE -40C to +85C Pin Configuration MAX9376 TOP VIEW ANYTHING LVDS IN1 1 10 VCC IN1 2 9 OUT1 OUT2 3 8 OUT1 OUT2 4 7 IN2 GND 5 6 IN2 MAX MAX is a registered trademark of Maxim Integrated Products, Inc. 19-2809; Rev 1; 10/09 PIN-PACKAGE 10 MAX LVPECL ANYTHING MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator Absolute Maximum Ratings VCC to GND..........................................................-0.3V to +4.1V Junction Temperature.......................................................+150C Inputs (IN_, IN_)........................................ -0.3V to (VCC + 0.3V) Storage Temperature Range.............................-65?C to +150C IN to IN................................................................................3.0V ESD Protection Continuous Output Current.................................................50mA Human Body Model (IN_, IN_, OUT_, OUT_)..................2kV Surge Output Current .......................................................100mA Soldering Temperature (10s)............................................+300C Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C)...........444mW JA in Still Air (Note 1)..............................................+180C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Stresses beyond those listed under ?Absolute Maximum Ratings? may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 2, 3, 4) PARAMETER SYMBOL CONDITIONS -40C MIN TYP +25C MAX MIN -100 +100 VIN, VIN = VCC or 0V -20 +20 Figure 1 0.05 TYP +85C TYP MAX UNITS MAX MIN -100 +100 -100 +100 mV -20 +20 -20 +20 A VCC 0.05 V DIFFERENTIAL INPUTS (IN_, IN_) Differential Input Threshold VTHD IIN, IIN Input Current Input Common-Mode Voltage VCM VCC 0.05 0.05 VCC 0.05 0.05 LVPECL OUTPUTS (OUT1, OUT1) Single-Ended Output High Voltage VOH Figure 3 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.085 1.035 0.880 1.025 0.985 0.880 1.025 0.976 0.880 V Single-Ended Output Low Voltage VOL Figure 3 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.830 1.745 1.620 1.810 1.694 1.620 1.810 1.681 1.620 V Differential Output Voltage VOH VOL Figure 3 595 710 VOD Figure 2 250 366 450 Change in Magnitude of VOD Between Complementary Output States |DVOD| Figure 2 1.0 20 Offset Common-Mode Voltage VOS Figure 2 Change in Magnitude of VOS Between Complementary Output States |DVOS| Figure 2 595 710 250 352 450 1.0 20 595 710 mV 250 339 450 mV 1.0 20 mV 1.375 V 20 mV LVDS OUTPUTS (OUT2, OUT2) Differential Output Voltage www.maximintegrated.com 1.125 1.375 1.125 1.250 1.375 1.125 1.0 20 1.0 20 1.0 Maxim Integrated 2 MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator DC Electrical Characteristics (continined) (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 2, 3, 4) PARAMETER SYMBOL CONDITIONS |IOS| Output Short-Circuit Current, Either Output Shorted to GND Output Short-circuit Current, Outputs Shorted Together -40C MIN +25C TYP MAX VID = 100mV, one output GND, other output open or shorted to GND 19 |IOSAB| VID = 100mV, VOUT_+ = VOUT_- ICC All pins open except VCC and GND with LVDS outputs (OUT2, OUT2) loaded with differential 100 MIN +85C TYP MAX 24 18 4.0 12 24 40 MIN UNITS TYP MAX 24 18 24 mA 4.0 12 4.0 12 mA 29 40 31 40 mA SUPPLY Supply Current AC Electrical Characteristics (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, input frequency 1.34GHz, differential input transition time = 125ps (20% to 80%), input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage (VCM) = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVPECL OUTPUTS Switching Frequency fMAX VOH - VOL 250mV 2.0 2.5 Propagation Delay Low to High tPLH Figure 3 250 421 600 ps Propagation Delay High to Low tPHL Figure 3 250 421 600 ps 6 30 ps Pulse Skew |tPLH - tPHL| Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (20% to 80%) Added Random Jitter tSKEW Figure 3 (Note 6) GHz tR Figure 3 116 220 ps tF Figure 3 119 220 ps fIN = 1.34GHz (Note 7) 0.7 2 ps(RMS) tRJ LVDS OUTPUTS Switching Frequency fMAX VOD 250mV 2.0 2.5 Propagation Delay Low to High tPLH Figure 3 250 363 600 ps tPHL Figure 3 250 367 600 ps 5 30 ps Propagation Delay High to Low Pulse Skew |tPLH - tPHL| www.maximintegrated.com tSKEW Figure 3 (Note 6) GHz Maxim Integrated 3 MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator AC Electrical Characteristics (continued) (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, input frequency 1.34GHz, differential input transition time = 125ps (20% to 80%), input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage (VCM) = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (20% to 80%) Added Random Jitter CONDITIONS MIN TYP MAX UNITS tR Figure 2 93 220 ps tF Figure 2 91 220 ps fIN = 1.34GHz (Note 7) 0.8 2 ps(RMS) tRJ Note 2: Measurements are made with the device in thermal equilibrium. All voltages are referenced to ground except VTHD, VID, VOD, and VOD. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 4: DC parameters production tested at TA = +25C and guaranteed by design and characterization over the full operating temperature range. Note 5: Guaranteed by design and characterization, not production tested. Limits are set at 6 sigma. Note 6: tSKEW is the magnitude difference of differential propagation delays for the same output under same conditions; tSKEW = |tPHL - tPLH|. Note 7: Device jitter added to the input signal. Typical Operating Characteristics (VCC = +3.3V, differential input voltage |VID| = 0.2V, VCM = 1.2V, input frequency = 500MHz, LVPECL outputs terminated with 50 1% to VCC - 2.0V, LVDS outputs terminated with 100 1%, TA = +25C, unless otherwise noted.) OUTPUT AMPLITUDE vs. FREQUENCY 30 20 10 0 800 LVPECL 700 600 500 LVDS 400 0 500 1000 1500 300 2000 0 500 440 tPHL (LVPECL) 420 400 tPLH (LVDS) 380 360 tPHL (LVDS) 340 130 tF (LVPECL) -40 -15 10 35 TEMPERATURE (C) www.maximintegrated.com 2000 120 110 tR (LVPECL) tF (LVDS) 100 90 tR (LVPECL) 80 320 300 140 OUTPUT RISE/FALL TIME (ps) PROPAGATION DELAY (ps) 480 MAX9376 toc03 500 tPLH (LVPECL) 1500 OUTPUT RISE/FALL TIME vs. TEMPERATURE PROPAGATION DELAY vs. TEMPERATURE 460 1000 FREQUENCY (MHz) FREQUENCY (MHz) 60 85 MAX9376 toc04 40 900 MAX9376 toc02 LVPECL OUTPUTS UNLOADED OUTPUT AMPLITUDE (mV) SUPPLY CURRENT (mA) 50 MAX9376 toc01 SUPPLY CURRENT vs. FREQUENCY 70 -40 -15 10 35 60 85 TEMPERATURE (C) Maxim Integrated 4 MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator Pin Description PIN NAME FUNCTION 1 IN1 Differential LVDS/Anything Noninverting Input 1 2 IN1 Differential LVDS/Anything Inverting Input 1 3 OUT2 Differential LVDS Noninverting Output 2. Terminate with 100 1% to OUT2. 4 OUT2 Differential LVDS Inverting Output 2. Terminate with 100 1% to OUT2. 5 GND Ground 6 IN2 Differential LVDS/Anything Inverting Input 2 7 IN2 Differential LVDS/Anything Noninverting Input 2 8 OUT1 Differential LVPECL Inverting Output. Terminate with 50 1% to VCC - 2V. 9 OUT1 Differential LVPECL Noninverting Output. Terminate with 50 1% to VCC - 2V. 10 VCC Positive Supply. Bypass from VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Detailed Description LVPECL Outputs The MAX9376 is a fully differential, high-speed, LVDS/ anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/ anything-to-LVPECL translator and the other channel is LVDS/anything-to-LVDS translator. The MAX9376's extremely low propagation delay and high speed make it ideal for various high-speed network routing and backplane applications. The MAX9376 LVPECL outputs are emitter followers that require external resistive paths to a voltage source (VT = VCC - 2.0V typ) more negative than worst-case VOL for proper static and dynamic operation. When properly terminated, the outputs generate steady-state voltage levels, VOL or VOH with fast transition edges between state levels. Output current always flows into the termination during proper operation. The MAX9376 accepts any differential input signal within the supply rails and with a minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling standards. LVPECL outputs have sufficient current to drive 50 transmission lines. LVDS outputs conform to the ANSI EIA/TIA-644 LVDS standard. LVDS Outputs Inputs The MAX9376 LVDS outputs require a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor. With a 3.5mA typical output current, the MAX9376 produces an output voltage of 350mV when driving a 100 load. Inputs have a wide common-mode range of 0.05V to VCC - 0.05V, which accommodates any differential signals within rails, and requires a minimum of 100mV to switch the outputs. This allows the MAX9376 inputs to support virtually any differential signaling standard. www.maximintegrated.com Maxim Integrated 5 MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator Applications Information VCC LVPECL Output Termination VID VCM (MAX) VID VCM (MIN) Terminate the MAX9376 LVPECL outputs with 50 to (VCC - 2V) or use equivalent Thevenin terminations. Terminate OUT1 and OUT1 with identical termination on each for low output distortion. When a single-ended signal is taken from the differential output, terminate both OUT1 and OUT1. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings. Under all operating conditions, the device's total thermal limits should be observed. GND Figure 1. Input Definition LVDS Output Termination RL / 2 OUT2 DRV VOD OUT2 VOS RL / 2 CL CL GND VOD(+) 80% 80% 0V VOD(-) 20% 20% OUT2 - OUT2 tR tF Figure 2. LVDS Output Load and Transition Times Supply Bypassing Bypass VCC to ground with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins. Traces IN VID OR (VIH - VIL) 0V DIFFERENTIAL IN tPHL tPLH VOH OUT VOD OR (VOH - VOL) VOL OUT 80% DIFFERENTIAL OUTPUT WAVEFORM OUT - OUT The MAX9376 LVDS outputs are current-steering devices; no output voltage is generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels are dependent upon the value of the termination resistor. The MAX9376 is optimized for point-to-point interface with 100 termination resistors at the receiver inputs. Termination resistance values may range between 90 and132, depending on the characteristic impedance of the transmission medium. +VOD OR +(VOH - VOL) 80% 0V DIFFERENTIAL -VOD OR -(VOH - VOL) 20% tR 20% tF Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces. Figure 3. Differential Input-to-Output Propagation Delay Timing Diagram www.maximintegrated.com Maxim Integrated 6 MAX9376 Chip Information PROCESS: Bipolar www.maximintegrated.com LVDS/Anything-to-LVPECL/LVDS Dual Translator Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10MAX U10+2 21-0061 Maxim Integrated 7 MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator Revision History REVISION NUMBER REVISION DATE 0 4/03 Initial release 1 10/09 Updated Ordering Information and Absolute Maximum Ratings DESCRIPTION PAGES CHANGED -- 1, 2 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 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