MAX9376EUB+T - Maxim Integrated

General Description

The MAX9376 is a fully differential, high-speed, LVDS/

anything-to-LVPECL/LVDS dual translator designed

for signal rates up to 2GHz. One channel is LVDS/

anything-to-LVPECL translator and the other channel

is LVDS/anything-to-LVDS translator. The MAX9376’s

extremely low propagation delay and high speed make

it ideal for various high-speed network routing and back-

plane applications.

The MAX9376 accepts any differential input signal within

the supply rails and with minimum amplitude of 100mV.

Inputs are fully compatible with the LVDS, LVPECL,

HSTL, and CML differential signaling standards. LVPECL

outputs have sufficient current to drive 50Ω transmission

lines. LVDS outputs conform to the ANSI EIA/TIA-644

LVDS standard.

The MAX9376 is available in a 10-pin µMAX® package

and operates from a single +3.3V supply over the -40°C

to +85°C temperature range.

Applications

●Backplane Logic Standard Translation

●LVDS-to-LVPECL, LVPECL-to-LVDS

Up/Downconverters

●LANs

●WANs

●DSLAMs

●DLCs

Features

●Guaranteed 2GHz Switching Frequency

●Accepts LVDS/LVPECL/Anything Inputs

●421ps (typ) Propagation Delays

●30ps (max) Pulse Skew

●2psRMS (max) Random Jitter

●Minimum 100mV Differential Input to Guarantee AC

Specifications

●Temperature-Compensated LVPECL Output

●+3.0V to +3.6V Power-Supply Operating Range

●>2kV ESD Protection (Human Body Model)

19-2809; Rev 1; 10/09

µMAX is a registered trademark of Maxim Integrated Products, Inc.

+Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

MAX9376EUB+ -40°C to +85°C 10 µMAX

VCC

OUT1

IN2OUT2

OUT2

IN1

ANYTHING

LVDS

LVPECL

MAX9376

µMAX

TOP VIEW

IN2GND

Pin Conguration

Ordering Information

MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

DC Electrical Characteristics

(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage

VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50Ω ±1% to (VCC - 2.0V), LVDS outputs terminated with 100Ω ±1%,

TA = -40°C to +85°C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless

otherwise noted.) (Notes 2, 3, 4)

VCC to GND .........................................................-0.3V to +4.1V

Inputs (IN_, IN_) ....................................... -0.3V to (VCC + 0.3V)

IN to IN ...............................................................................±3.0V

Continuous Output Current ................................................50mA

Surge Output Current ...................................................... 100mA

Continuous Power Dissipation (TA = +70°C)

10-Pin µMAX (derate 5.6mW/°C above +70°C) ..........444mW

θJA in Still Air (Note 1) .............................................+180°C/W

Junction Temperature ...................................................... +150°C

Storage Temperature Range ............................ -65?C to +150°C

ESD Protection

Human Body Model (IN_, IN_, OUT_, OUT_) .................≥2kV

Soldering Temperature (10s) ...........................................+300°C

PARAMETER SYMBOL CONDITIONS -40°C +25°C +85°C UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

DIFFERENTIAL INPUTS (IN_, IN_)

Differential Input Threshold VTHD -100 +100 -100 +100 -100 +100 mV

Input Current IIN,

IIN

VIN, VIN =

VCC or 0V -20 +20 -20 +20 -20 +20 µA

Input Common-Mode

Voltage VCM Figure 1 0.05 VCC -

0.05 0.05 VCC -

0.05 V

LVPECL OUTPUTS (OUT1, OUT1)

Single-Ended Output High

Voltage VOH Figure 3 VCC -

1.085

VCC -

1.035

VCC -

0.880

VCC -

1.025

VCC -

0.985

VCC -

0.880

VCC -

1.025

VCC -

0.976

VCC -

0.880 V

Single-Ended Output Low

Voltage VOL Figure 3 VCC -

1.830

VCC -

1.745

VCC -

1.620

VCC -

1.810

VCC -

1.694

VCC -

1.620

VCC -

1.810

VCC -

1.681

VCC -

1.620 V

Differential Output Voltage VOH -

VOL

Figure 3 595 710 595 710 595 710 mV

LVDS OUTPUTS (OUT2, OUT2)

Differential Output Voltage VOD Figure 2 250 366 450 250 352 450 250 339 450 mV

Change in Magnitude

of VOD Between

Complementary Output

States

|DVOD| Figure 2 1.0 20 1.0 20 1.0 20 mV

Offset Common-Mode

Voltage VOS Figure 2 1.125 1.375 1.125 1.250 1.375 1.125 1.375 V

Change in Magnitude

of VOS Between

Complementary Output

States

|DVOS| Figure 2 1.0 20 1.0 20 1.0 20 mV

Stresses beyond those listed under ?Absolute Maximum Ratings? may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Absolute Maximum Ratings

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

AC Electrical Characteristics

(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, input frequency ≤ 1.34GHz, differential input transition time =

125ps (20% to 80%), input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage (VCM) = 0.05V to (VCC - 0.05V), LVPECL outputs

terminated with 50Ω ±1% to (VCC - 2.0V), LVDS outputs terminated with 100Ω ±1%, TA = -40°C to +85°C. Typical values are at VCC

= +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Note 5)

DC Electrical Characteristics (continined)

(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage

VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50Ω ±1% to (VCC - 2.0V), LVDS outputs terminated with 100Ω ±1%,

TA = -40°C to +85°C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless

otherwise noted.) (Notes 2, 3, 4)

PARAMETER SYMBOL CONDITIONS -40°C +25°C +85°C UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

Output Short-Circuit

Current, Either Output

Shorted to GND

|IOS|

VID = ±100mV,

one output GND,

other output open

or shorted to

GND

19 24 18 24 18 24 mA

Output Short-circuit Current,

Outputs Shorted Together |IOSAB|

VID = ±100mV,

VOUT_+ =

VOUT_-

4.0 12 4.0 12 4.0 12 mA

SUPPLY

Supply Current ICC

All pins open

except VCC and

GND with LVDS

outputs (OUT2,

OUT2) loaded

with differential

100Ω

24 40 29 40 31 40 mA

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LVPECL OUTPUTS

Switching Frequency fMAX VOH - VOL ≥ 250mV 2.0 2.5 GHz

Propagation Delay Low to High tPLH Figure 3 250 421 600 ps

Propagation Delay High to Low tPHL Figure 3 250 421 600 ps

Pulse Skew |tPLH - tPHL| tSKEW Figure 3 (Note 6) 6 30 ps

Output Low-to-High Transition

Time (20% to 80%) tRFigure 3 116 220 ps

Output High-to-Low Transition

Time (20% to 80%) tFFigure 3 119 220 ps

Added Random Jitter tRJ fIN = 1.34GHz (Note 7) 0.7 2 ps(RMS)

LVDS OUTPUTS

Switching Frequency fMAX VOD ≥ 250mV 2.0 2.5 GHz

Propagation Delay Low to High tPLH Figure 3 250 363 600 ps

Propagation Delay High to Low tPHL Figure 3 250 367 600 ps

Pulse Skew |tPLH - tPHL| tSKEW Figure 3 (Note 6) 5 30 ps

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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

AC Electrical Characteristics (continued)

(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, input frequency ≤ 1.34GHz, differential input transition time =

125ps (20% to 80%), input voltage (VIN, VIN) = 0 to VCC, input common-mode voltage (VCM) = 0.05V to (VCC - 0.05V), LVPECL outputs

terminated with 50Ω ±1% to (VCC - 2.0V), LVDS outputs terminated with 100Ω ±1%, TA = -40°C to +85°C. Typical values are at VCC

= +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Note 5)

Typical Operating Characteristics

(VCC = +3.3V, differential input voltage |VID| = 0.2V, VCM = 1.2V, input frequency = 500MHz, LVPECL outputs terminated with 50Ω ±1%

to VCC - 2.0V, LVDS outputs terminated with 100Ω ±1%, TA = +25°C, unless otherwise noted.)

Note 2: Measurements are made with the device in thermal equilibrium. All voltages are referenced to ground except VTHD, VID,

VOD, and ∆VOD.

Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative.

Note 4: DC parameters production tested at TA = +25°C and guaranteed by design and characterization over the full operating

temperature range.

Note 5: Guaranteed by design and characterization, not production tested. Limits are set at ±6 sigma.

Note 6: tSKEW is the magnitude difference of differential propagation delays for the same output under same conditions; tSKEW =

|tPHL - tPLH|.

Note 7: Device jitter added to the input signal.

SUPPLY CURRENT

vs. FREQUENCY

MAX9376 toc01

FREQUENCY (MHz)

SUPPLY CURRENT (mA)

15001000500

0 2000

LVPECL OUTPUTS

UNLOADED

OUTPUT AMPLITUDE

vs. FREQUENCY

MAX9376 toc02

FREQUENCY (MHz)

OUTPUT AMPLITUDE (mV)

15001000500

400

500

600

700

800

900

300

0 2000

LVPECL

LVDS

PROPAGATION DELAY

vs. TEMPERATURE

MAX9376 toc03

TEMPERATURE (C)

PROPAGATION DELAY (ps)

603510-15

320

340

360

380

400

420

440

460

480

500

300

-40 85

tPLH (LVPECL) tPHL (LVPECL)

tPLH (LVDS)

tPHL (LVDS)

OUTPUT RISE/FALL TIME

vs. TEMPERATURE

MAX9376 toc04

TEMPERATURE (C)

OUTPUT RISE/FALL TIME (ps)

603510-15

100

110

120

130

140

-40 85

tR (LVPECL)

tF (LVPECL)

tF (LVDS)

tR (LVPECL)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Low-to-High Transition

Time (20% to 80%) tRFigure 2 93 220 ps

Output High-to-Low Transition

Time (20% to 80%) tFFigure 2 91 220 ps

Added Random Jitter tRJ fIN = 1.34GHz (Note 7) 0.8 2 ps(RMS)

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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

Detailed Description

The MAX9376 is a fully differential, high-speed, LVDS/

anything-to-LVPECL/LVDS dual translator designed

for signal rates up to 2GHz. One channel is LVDS/

anything-to-LVPECL translator and the other channel

is LVDS/anything-to-LVDS translator. The MAX9376's

extremely low propagation delay and high speed make

it ideal for various high-speed network routing and back-

plane applications.

The MAX9376 accepts any differential input signal within

the supply rails and with a minimum amplitude of 100mV.

Inputs are fully compatible with the LVDS, LVPECL,

HSTL, and CML differential signaling standards. LVPECL

outputs have sufficient current to drive 50Ω transmission

lines. LVDS outputs conform to the ANSI EIA/TIA-644

LVDS standard.

Inputs

Inputs have a wide common-mode range of 0.05V to VCC

- 0.05V, which accommodates any differential signals

within rails, and requires a minimum of 100mV to switch

the outputs. This allows the MAX9376 inputs to support

virtually any differential signaling standard.

LVPECL Outputs

The MAX9376 LVPECL outputs are emitter followers that

require external resistive paths to a voltage source (VT =

VCC - 2.0V typ) more negative than worst-case VOL for

proper static and dynamic operation. When properly ter-

minated, the outputs generate steady-state voltage lev-

els, VOL or VOH with fast transition edges between state

levels. Output current always flows into the termination

during proper operation.

LVDS Outputs

The MAX9376 LVDS outputs require a resistive load to

terminate the signal and complete the transmission loop.

Because the device switches current and not voltage, the

actual output voltage swing is determined by the value of

the termination resistor. With a 3.5mA typical output cur-

rent, the MAX9376 produces an output voltage of 350mV

when driving a 100Ω load.

PIN NAME FUNCTION

1 IN1 Differential LVDS/Anything Noninverting Input 1

2IN1 Differential LVDS/Anything Inverting Input 1

3 OUT2 Differential LVDS Noninverting Output 2. Terminate with 100Ω ±1% to OUT2.

4OUT2 Differential LVDS Inverting Output 2. Terminate with 100Ω ±1% to OUT2.

5 GND Ground

6IN2 Differential LVDS/Anything Inverting Input 2

7 IN2 Differential LVDS/Anything Noninverting Input 2

8OUT1 Differential LVPECL Inverting Output. Terminate with 50Ω ±1% to VCC - 2V.

9 OUT1 Differential LVPECL Noninverting Output. Terminate with 50Ω ±1% to VCC - 2V.

10 VCC

Positive Supply. Bypass from VCC to GND with 0.1µF and 0.01µF ceramic capacitors. Place the

capacitors as close to the device as possible with the smaller value capacitor closest to the device.

Pin Description

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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

Applications Information

LVPECL Output Termination

Terminate the MAX9376 LVPECL outputs with 50Ω to

(VCC - 2V) or use equivalent Thevenin terminations.

Terminate OUT1 and OUT1 with identical termination on

each for low output distortion. When a single-ended signal

is taken from the differential output, terminate both OUT1

and OUT1.

Ensure that output currents do not exceed the current lim-

its as specified in the Absolute Maximum Ratings. Under

all operating conditions, the device's total thermal limits

should be observed.

LVDS Output Termination

The MAX9376 LVDS outputs are current-steering devic-

es; no output voltage is generated without a termination

resistor. The termination resistors should match the differ-

ential impedance of the transmission line. Output voltage

levels are dependent upon the value of the termination

resistor. The MAX9376 is optimized for point-to-point

interface with 100Ω termination resistors at the receiver

inputs. Termination resistance values may range between

90Ω and132Ω, depending on the characteristic imped-

ance of the transmission medium.

Supply Bypassing

Bypass VCC to ground with high-frequency surface-mount

ceramic 0.1µF and 0.01µF capacitors. Place the capaci-

tors as close to the device as possible with the 0.01µF

capacitor closest to the device pins.

Traces

Circuit board trace layout is very important to maintain

the signal integrity of high-speed differential signals.

Maintaining integrity is accomplished in part by reduc-

ing signal reflections and skew, and increasing com-

mon-mode noise immunity.

Signal reflections are caused by discontinuities in the 50Ω

characteristic impedance of the traces. Avoid discontinuities

by maintaining the distance between differential traces, not

using sharp corners or using vias. Maintaining distance

between the traces also increases common-mode noise

immunity. Reducing signal skew is accomplished by

matching the electrical length of the differential traces.

VCM (MAX)

VCC

GND

VID

VCM (MIN)

VID

80%

OUT2 - OUT2

20% 20%

80%

DRV OUT2

OUT2 RL / 2

RL / 2

VOD

VOD(+)

VOD(-)

VOS

GND

tPHL

tPLH

80%

20% 20%

80%

DIFFERENTIAL OUTPUT

WAVEFORM

VID OR (VIH - VIL)

VOD OR (VOH - VOL)

+VOD OR +(VOH - VOL)

-VOD OR -(VOH - VOL)

0V DIFFERENTIAL

VOH

VOL

0V DIFFERENTIAL

OUT

OUT - OUT

Figure 1. Input Definition

Figure 2. LVDS Output Load and Transition Times

Figure 3. Differential Input-to-Output Propagation Delay Timing

Diagram

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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

PACKAGE

TYPE PACKAGE CODE DOCUMENT NO.

10µMAX U10+2 21-0061

Chip Information

PROCESS: Bipolar

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 4/03 Initial release —

1 10/09 Updated Ordering Information and Absolute Maximum Ratings 1, 2

Revision History

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator

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