PEF2256 E V2.2-G - Infineon Technologies

Never stop thinking.

FALC®56

E1/T1/J1 Framer and Line Interface

Component for Long- and Short-Haul

Applications

PEF 2256 H/E, Version 2.1

Hardware Description

User’s Manual, DS1.1, Oct. 2003

Wired Communications

ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®,

FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®,

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The information in this document is subject to change without notice.

Edition 2003-10-23

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

PEF 2256 H/E

Revision History: 2003-10-23 DS1.1

Previous Version: ./.

Page Subjects (major changes since last revision)

FALC®56
PEF 2256 H/E
Table of Contents Page
User’s Manual 3 DS1.1, 2003-10-23
Hardware Description
Preface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
2 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
1 Logic Symbol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
2 Pin Diagram P-MQFP-80-1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
3 Pin Diagram P-LBGA-81-1   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
4.1 Input/Output Signals   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
Functional Description E1/T1/J1   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
1 Functional Overview   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
2 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
3 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51
3.1 Microprocessor Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51
3.1.1 Mixed Byte/Word Access to the FIFOs  . . . . . . . . . . . . . . . . . . . . . . .  51
3.1.2 FIFO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52
3.1.3 Interrupt Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  54
3.2 Boundary Scan Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
3.3 Master Clocking Unit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  59
4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  60
4.1 Power Supply Configuration   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  60
4.2 Power Supply De-Coupling  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61
Functional Description E1   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  63
1 Receive Path in E1 Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  63
1.1 Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  63
1.2 Receive Short and Long-Haul Interface . . . . . . . . . . . . . . . . . . . . . . . . .  63
1.3 Receive Equalization Network (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  64
1.4 Receive Line Attenuation Indication (E1) . . . . . . . . . . . . . . . . . . . . . . . .  64
1.5 Receive Clock and Data Recovery (E1)   . . . . . . . . . . . . . . . . . . . . . . . .  64
1.6 Receive Line Coding (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  65
1.7 Receive Line Termination (E1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  66
1.8 Receive Line Monitoring Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  66
1.9 Loss-of-Signal Detection (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  69
1.10 Receive Jitter Attenuator (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  70
1.11 Jitter Tolerance (E1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  73
1.12 Output Jitter (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  73
1.13 Framer/Synchronizer (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  74
1.14 Receive Elastic Buffer (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  74
1.15 Receive Signaling Controller (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77

FALC®56
PEF 2256 H/E
Table of Contents Page
User’s Manual 4 DS1.1, 2003-10-23
Hardware Description
1.15.1 HDLC or LAPD Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77
1.15.2 Support of Signaling System #7   . . . . . . . . . . . . . . . . . . . . . . . . . . . .  78
1.15.3 Sa-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  80
1.15.4 Channel Associated Signaling CAS (E1, serial mode)   . . . . . . . . . . .  80
1.15.5 Channel Associated Signaling CAS (E1, µP access mode)   . . . . . . .  81
2 Framer Operating Modes (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  82
2.1 General  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  82
2.2 Doubleframe Format (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  83
2.2.1 Transmit Transparent Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  84
2.2.2 Synchronization Procedure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  84
2.2.3 A-Bit Access   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  85
2.2.4 Sa-Bit Access   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  85
2.3 CRC-Multiframe (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  86
2.3.1 Synchronization Procedure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  87
2.3.2 Automatic Force Resynchronization (E1)   . . . . . . . . . . . . . . . . . . . . .  88
2.3.3 Floating Multiframe Alignment Window (E1)  . . . . . . . . . . . . . . . . . . .  88
2.3.4 CRC4 Performance Monitoring (E1)  . . . . . . . . . . . . . . . . . . . . . . . . .  88
2.3.5 Modified CRC4 Multiframe Alignment Algorithm (E1)  . . . . . . . . . . . .  88
2.3.6 A-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  89
2.3.7 Sa-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  90
2.3.8 E-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  91
3 Additional Receive Framer Functions (E1)   . . . . . . . . . . . . . . . . . . . . . . . .  93
3.1 Error Performance Monitoring and Alarm Handling . . . . . . . . . . . . . . . .  93
3.2 Auto Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  94
3.2.1 Automatic Remote Alarm Access   . . . . . . . . . . . . . . . . . . . . . . . . . . .  94
3.2.2 Automatic E-bit Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  94
3.2.3 Automatic AIS to System Interface  . . . . . . . . . . . . . . . . . . . . . . . . . .  94
3.2.4 Automatic Clock Source Switching  . . . . . . . . . . . . . . . . . . . . . . . . . .  95
3.2.5 Automatic Freeze Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  95
3.3 Error Counters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  95
3.4 Errored Second  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  95
3.5 One-Second Timer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  95
3.6 In-Band Loop Generation and Detection  . . . . . . . . . . . . . . . . . . . . . . . .  96
3.7 Time Slot 0 Transparent Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  96
4 Transmit Path in E1 Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
4.1 Transmitter (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
4.2 Transmit Line Interface (E1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  98
4.3 Transmit Jitter Attenuator (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  99
4.4 Transmit Elastic Buffer (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  100
4.5 Programmable Pulse Shaper (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  101
4.6 Transmit Line Monitor (E1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  101
4.7 Transmit Signaling Controller (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  102

FALC®56
PEF 2256 H/E
Table of Contents Page
User’s Manual 5 DS1.1, 2003-10-23
Hardware Description
4.7.1 HDLC or LAPD access   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  102
4.7.2 Support of Signaling System #7   . . . . . . . . . . . . . . . . . . . . . . . . . . .  103
4.7.3 Sa-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  103
4.7.4 Channel Associated Signaling CAS (E1, serial mode)   . . . . . . . . . .  104
4.7.5 Channel Associated Signaling CAS (E1, µP access mode)   . . . . . .  104
5 System Interface in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  105
5.1 Receive System Interface (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  108
5.1.1 Receive Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  109
5.2 Transmit System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  112
5.2.1 Transmit Offset Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  114
5.3 Time Slot Assigner (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  116
6 Test Functions (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  117
6.1 Pseudo-Random Binary Sequence Generation and Monitor . . . . . . . .  117
6.2 Remote Loop  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  117
6.3 Payload Loop-Back  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  118
6.4 Local Loop  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  119
6.5 Single Channel Loop-Back   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  120
6.6 Alarm Simulation (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  121
6.7 Single Bit Defect Insertion  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  121
Functional Description T1/J1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  122
1 Receive Path in T1/J1 Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  122
1.1 Receive Line Interface (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  122
1.2 Receive Short and Long-Haul Interface (T1/J1)   . . . . . . . . . . . . . . . . .  122
1.3 Receive Equalization Network (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . .  123
1.4 Receive Line Attenuation Indication (T1/J1)  . . . . . . . . . . . . . . . . . . . .  123
1.5 Receive Clock and Data Recovery (T1/J1)  . . . . . . . . . . . . . . . . . . . . .  123
1.6 Receive Line Coding (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  124
1.7 Receive Line Termination (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  125
1.8 Receive Line Monitoring Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  126
1.9 Loss-of-Signal Detection (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  128
1.10 Receive Jitter Attenuator (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  129
1.11 Jitter Tolerance (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  132
1.12 Output Jitter (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  133
1.13 Framer/Synchronizer (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  133
1.14 Receive Elastic Buffer (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  133
1.15 Receive Signaling Controller (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . .  138
1.15.1 HDLC or LAPD Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  138
1.15.2 Support of Signaling System #7   . . . . . . . . . . . . . . . . . . . . . . . . . . .  139
1.15.3 CAS Bit-Robbing (T1/J1, serial mode) . . . . . . . . . . . . . . . . . . . . . . .  141
1.15.4 CAS Bit-Robbing (T1/J1, µP access mode) . . . . . . . . . . . . . . . . . . .  141
1.15.5 Bit Oriented Messages in ESF-DL Channel (T1/J1)   . . . . . . . . . . . .  141
1.15.6 4 kbit/s Data Link Access in F72 Format (T1/J1) . . . . . . . . . . . . . . .  142

FALC®56
PEF 2256 H/E
Table of Contents Page
User’s Manual 6 DS1.1, 2003-10-23
Hardware Description
2 Framer Operating Modes (T1/J1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  142
2.1 General  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  142
2.2 General Aspects of Synchronization  . . . . . . . . . . . . . . . . . . . . . . . . . .  143
2.3 Addition for F12 and F72 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  143
2.4 4-Frame Multiframe (F4 Format, T1/J1)   . . . . . . . . . . . . . . . . . . . . . . .  146
2.4.1 Synchronization Procedure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  146
2.5 12-Frame Multiframe (D4 or SF Format, T1/J1)   . . . . . . . . . . . . . . . . .  147
2.5.1 Synchronization Procedure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  147
2.6 Extended Superframe (F24 or ESF Format, T1/J1) . . . . . . . . . . . . . . .  148
2.6.1 Synchronization Procedures  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  149
2.6.2 Remote Alarm (yellow alarm) Generation/Detection  . . . . . . . . . . . .  150
2.6.3 CRC6 Generation and Checking (T1/J1) . . . . . . . . . . . . . . . . . . . . .  150
2.7 72-Frame Multiframe (SLC96 Format, T1/J1)  . . . . . . . . . . . . . . . . . . .  151
2.7.1 Synchronization Procedure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  151
2.8 Summary of Frame Conditions (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . .  154
3 Additional Receive Framer Functions (T1/J1)  . . . . . . . . . . . . . . . . . . . . .  155
3.1 Error Performance Monitoring and Alarm Handling . . . . . . . . . . . . . . .  155
3.2 Auto Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  156
3.3 Error Counters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  157
3.4 Errored Second  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  157
3.5 One-Second Timer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  157
3.6 Clear Channel Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  158
3.7 In-Band Loop Generation and Detection  . . . . . . . . . . . . . . . . . . . . . . .  158
3.8 Transparent Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  158
3.9 Pulse-Density Detection   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  159
4 Transmit Path in T1/J1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  159
4.1 Transmitter (T1/J1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  159
4.2 Transmit Line Interface (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  160
4.3 Transmit Jitter Attenuator (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  161
4.4 Transmit Elastic Buffer (T1/J1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  163
4.5 Programmable Pulse Shaper and Line Build-Out (T1/J1)  . . . . . . . . . .  165
4.6 Transmit Line Monitor (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  166
4.7 Transmit Signaling Controller (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . .  167
4.7.1 HDLC or LAPD access   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  167
4.7.2 Support of Signaling System #7   . . . . . . . . . . . . . . . . . . . . . . . . . . .  167
4.7.3 CAS Bit-Robbing (T1/J1, serial mode) . . . . . . . . . . . . . . . . . . . . . . .  168
4.7.4 CAS Bit-Robbing (T1/J1, µP access mode) . . . . . . . . . . . . . . . . . . .  169
4.7.5 Data Link Access in ESF/F24 and F72 Format (T1/J1)  . . . . . . . . . .  169
4.7.6 Periodical Performance Report in ESF Format (T1/J1)  . . . . . . . . . .  169
5 System Interface in T1/J1 Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  171
5.1 Receive System Interface (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  174
5.1.1 Receive Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  175

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PEF 2256 H/E
Table of Contents Page
User’s Manual 7 DS1.1, 2003-10-23
Hardware Description
5.2 Transmit System Interface (T1/J1)   . . . . . . . . . . . . . . . . . . . . . . . . . . .  179
5.2.1 Transmit Offset Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  185
5.3 Time Slot Assigner (T1/J1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  187
6 Test Functions (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  188
6.1 Pseudo-Random Binary Sequence Generation and Monitor . . . . . . . .  188
6.2 Remote Loop  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  188
6.3 Payload Loop-Back  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  190
6.4 Local Loop  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  191
6.5 Single Channel Loop-Back (loop-back of time slots) . . . . . . . . . . . . . .  192
6.6 Alarm Simulation (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  193
6.7 Single Bit Defect Insertion  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  193
7 J1-Feature Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  193
Operational Description E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  195
1 Operational Overview E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  195
2 Device Reset E1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  195
3 Device Initialization in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  195
4 Digital Clock Interface Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  201
5 Output Signal Tristate Modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  202
Operational Description T1/J1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
1 Operational Overview T1/J1   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
2 Device Reset T1/J1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
3 Device Initialization in T1/J1 Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
4 Digital Clock Interface Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  210
5 Output Signal Tristate Modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  210
Signaling Controller Operating Modes  . . . . . . . . . . . . . . . . . . . . . . . .  211
1 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  211
1.1 Non-Auto Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  211
1.2 Transparent Mode 1   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
1.3 Transparent Mode 0   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
1.4 SS7 Support   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
1.5 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
1.6 Transmit Data Flow  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  214
2 Extended Transparent Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  214
3 Signaling Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  215
3.1 Transparent Transmission and Reception . . . . . . . . . . . . . . . . . . . . . .  215
3.2 CRC on/off Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  215
3.3 Receive Address Pushed to RFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . .  216
3.4 HDLC Data Transmission  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  216
3.5 HDLC Data Reception  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  218
3.6 Sa-bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  218
3.7 Bit Oriented Message Mode (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . .  219

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Table of Contents Page
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Hardware Description
3.8 Data Link Access in ESF/F72 Format (T1/J1)  . . . . . . . . . . . . . . . . . . .  221
Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  222
E1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  223
1 E1 Control Register Addresses  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  223
2 Detailed Description of E1 Control Registers   . . . . . . . . . . . . . . . . . . . . .  227
3 E1 Status Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  299
4 Detailed Description of E1 Status Registers  . . . . . . . . . . . . . . . . . . . . . .  301
T1/J1 Registers   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  344
1 T1/J1 Control Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  344
2 Detailed Description of T1/J1 Control Registers  . . . . . . . . . . . . . . . . . . .  348
3 T1/J1 Status Register Addresses   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  424
4 Detailed Description of T1/J1 Status Registers  . . . . . . . . . . . . . . . . . . . .  426
Electrical Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  464
1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  464
2 Operating Range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  465
3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  466
4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  469
4.1 Master Clock Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  469
4.2 JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  470
4.3 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  471
4.4 Microprocessor Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  471
4.4.1 Intel Bus Interface Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  471
4.4.2 Motorola Bus Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  475
4.5 Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  477
4.6 System Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  480
4.7 Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  492
4.7.1 Pulse Template E1 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . .  492
4.7.2 Pulse Template E1 Synchronization Interface . . . . . . . . . . . . . . . . .  493
4.7.3 Pulse Template T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  494
5 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  495
6 Package Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  495
7 Test Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  496
7.1 AC Tests  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  496
7.2 Power Supply Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  497
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  499
Appendix   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  501
1 Protection Circuitry   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  501
2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  501
3 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  501

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PEF 2256 H/E

Table of Contents Page

User’s Manual 9 DS1.1, 2003-10-23

Hardware Description

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

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List of Figures Page
User’s Manual 10 DS1.1, 2003-10-23
Hardware Description
Figure 1 GSM Base Station Aplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
Figure 2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
Figure 3 Pin Configuration P-MQFP-80-1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
Figure 4 Pin Configuration P-LBGA-81-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
Figure 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
Figure 6 FIFO Word Access (Intel Mode)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  53
Figure 7 FIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . .  53
Figure 8 Interrupt Status Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  54
Figure 9 Block Diagram of Test Access Port and Boundary Scan. . . . . . . . . . .  56
Figure 10 JTAG TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . .  58
Figure 11 Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  59
Figure 12 Single Voltage Power Supply Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .  60
Figure 13 Dual Voltage Power Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61
Figure 14 Decoupling Capacitor Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  62
Figure 15 Receive Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  63
Figure 16 Receiver Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  66
Figure 17 Receive Line Monitoring (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  67
Figure 18 Short Haul Protection Switching Application (E1)  . . . . . . . . . . . . . . . .  68
Figure 19 Long Haul Protection Switching Application (E1). . . . . . . . . . . . . . . . .  69
Figure 20 Jitter Attenuation Performance (E1). . . . . . . . . . . . . . . . . . . . . . . . . . .  72
Figure 21 Jitter Tolerance (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  73
Figure 22 The Receive Elastic Buffer as Circularly Organized Memory  . . . . . . .  76
Figure 23 Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . .  79
Figure 24 2.048 MHz Receive Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . .  81
Figure 25 CRC4 Multiframe Alignment Recovery Algorithms (E1). . . . . . . . . . . .  92
Figure 26 Transmitter Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  98
Figure 27 Transmit Clock System (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  100
Figure 28 Transmit Line Monitor Configuration (E1)  . . . . . . . . . . . . . . . . . . . . .  102
Figure 29 2.048 MHz Transmit Signaling Highway (E1)  . . . . . . . . . . . . . . . . . .  104
Figure 30 System Interface (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  107
Figure 31 Receive System Interface Clocking (E1) . . . . . . . . . . . . . . . . . . . . . .  108
Figure 32 SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . .  110
Figure 33 SYPR Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . .  110
Figure 34 RFM Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . .  111
Figure 35 RFM Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . .  111
Figure 36 Transmit System Interface Clocking: 2.048 MHz (E1) . . . . . . . . . . . .  112
Figure 37 Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1). .  113
Figure 38 SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . .  115
Figure 39 SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . .  115
Figure 40 Remote Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  117
Figure 41 Payload Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  118
Figure 42 Local Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  119

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PEF 2256 H/E
List of Figures Page
User’s Manual 11 DS1.1, 2003-10-23
Hardware Description
Figure 43 Single Channel Loop-Back (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . .  120
Figure 44 Receive Clock System (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  122
Figure 45 Receiver Configuration (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  125
Figure 46 Receive Line Monitoring  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  126
Figure 47 Protection Switching Application (T1/J1) . . . . . . . . . . . . . . . . . . . . . .  127
Figure 48 Long Haul Protection Switching Application (T1/J1)  . . . . . . . . . . . . .  128
Figure 49 Jitter Attenuation Performance (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . .  131
Figure 50 Jitter Tolerance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  132
Figure 51 The Receive Elastic Buffer as Circularly Organized Memory  . . . . . .  137
Figure 52 Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . .  140
Figure 53 Influences on Synchronization Status (T1/J1) . . . . . . . . . . . . . . . . . .  145
Figure 54 Transmitter Configuration (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . .  160
Figure 55 Clocking in Remote Loop Configuration (T1/J1)  . . . . . . . . . . . . . . . .  162
Figure 56 Transmit Clock System (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  163
Figure 57 Transmit Line Monitor Configuration (T1/J1) . . . . . . . . . . . . . . . . . . .  167
Figure 58 System Interface (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  173
Figure 59 Receive System Interface Clocking (T1/J1). . . . . . . . . . . . . . . . . . . .  174
Figure 60 SYPR Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . .  176
Figure 61 SYPR Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . .  176
Figure 62 RFM Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . . .  177
Figure 63 RFM Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . . .  177
Figure 64 2.048 MHz Receive Signaling Highway (T1/J1). . . . . . . . . . . . . . . . .  178
Figure 65 Receive FS/DL-Bits in Time Slot 0 on RDO (T1/J1)  . . . . . . . . . . . . .  178
Figure 66 1.544 MHz Receive Signaling Highway (T1/J1). . . . . . . . . . . . . . . . .  179
Figure 67 Transmit System Clocking: 1.544 MHz (T1/J1) . . . . . . . . . . . . . . . . .  180
Figure 68 Transmit System Clocking: 8.192 MHz/4.096 Mbit/s (T1/J1). . . . . . .  181
Figure 69 2.048 MHz Transmit Signaling Clocking (T1/J1) . . . . . . . . . . . . . . . .  182
Figure 70 1.544 MHz Transmit Signaling Highway (T1/J1) . . . . . . . . . . . . . . . .  182
Figure 71 Signaling Marker for CAS/CAS-CC Applications (T1/J1). . . . . . . . . .  183
Figure 72 Signaling Marker for CAS-BR Applications (T1/J1) . . . . . . . . . . . . . .  184
Figure 73 Transmit FS/DL Bits on XDI (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . .  185
Figure 74 SYPX Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . .  186
Figure 75 SYPX Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . .  186
Figure 76 Remote Loop (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  189
Figure 77 Payload Loop (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  190
Figure 78 Local Loop (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  191
Figure 79 Channel Loop-Back (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  192
Figure 80 HDLC Receive Data Flow  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  213
Figure 81 HDLC Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  214
Figure 82 Interrupt Driven Data Transmission (flow diagram) . . . . . . . . . . . . . .  217
Figure 83 Interrupt Driven Transmission Example. . . . . . . . . . . . . . . . . . . . . . .  217
Figure 84 Interrupt Driven Reception Sequence Example. . . . . . . . . . . . . . . . .  218

FALC®56
PEF 2256 H/E
List of Figures Page
User’s Manual 12 DS1.1, 2003-10-23
Hardware Description
Figure 85 MCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  469
Figure 86 JTAG Boundary Scan Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  470
Figure 87 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  471
Figure 88 Intel Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . .  471
Figure 89 Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .  472
Figure 90 Intel Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  472
Figure 91 Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  473
Figure 92 Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  475
Figure 93 Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  475
Figure 94 Digital Line Interface Receive Timing  . . . . . . . . . . . . . . . . . . . . . . . .  477
Figure 95 Digital Line Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . .  477
Figure 96 RCLK and RFSP Output Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  480
Figure 97 SCLKR/SCLKX Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  481
Figure 98 Receive System Interface Marker Timing  . . . . . . . . . . . . . . . . . . . . .  482
Figure 99 SYPR and SYPX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  483
Figure 100 Transmit System Interface Marker Timing . . . . . . . . . . . . . . . . . . . . .  485
Figure 101 XDI and XSIG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  486
Figure 102 TCLK Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  487
Figure 103 XCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  488
Figure 104 SEC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  489
Figure 105 FSC Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  490
Figure 106 SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  491
Figure 107 E1 Pulse Shape at Transmitter Output  . . . . . . . . . . . . . . . . . . . . . . .  492
Figure 108 DCIM Clock Pulse Shape at Transmitter Output . . . . . . . . . . . . . . . .  493
Figure 109 T1 Pulse Shape at the Cross Connect Point . . . . . . . . . . . . . . . . . . .  494
Figure 110 Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  495
Figure 111 Input/Output Waveforms for AC Testing  . . . . . . . . . . . . . . . . . . . . . .  496
Figure 112 Device Configuration for Power Supply Testing  . . . . . . . . . . . . . . . .  497
Figure 113 P-MQFP-80-1(Plastic Metric Quad Flat Package) . . . . . . . . . . . . . . .  499
Figure 114 P-LBGA-81-1(Plastic Ball Grid Array Package) . . . . . . . . . . . . . . . . .  500
Figure 115 Protection Circuitry Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  501
Figure 116 Master Clock Frequency Calculator. . . . . . . . . . . . . . . . . . . . . . . . . .  503
Figure 117 External Line Frontend Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . .  504

FALC®56
PEF 2256 H/E
List of Tables Page
User’s Manual 13 DS1.1, 2003-10-23
Hardware Description
Table 1 Pin Definitions - Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . .  26
Table 2 Pin Definitions - Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
Table 3 Pin Definitions - Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
Table 4 Pin Definitions - System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38
Table 5 Miscellaneous Pin Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  46
Table 6 Data Bus Access (16-Bit Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . .  51
Table 7 Data Bus Access (16-Bit Motorola Mode) . . . . . . . . . . . . . . . . . . . . . .  51
Table 8 Selectable Bus and Microprocessor Interface Configuration . . . . . . . .  52
Table 9 TAP Controller Instruction Codes  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
Table 10 Decoupling Capacitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61
Table 11 RCLK Output Selection (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  65
Table 12 Recommended Receiver Configuration Values (E1) . . . . . . . . . . . . . .  66
Table 13 External Component Recommendations (Monitoring) . . . . . . . . . . . . .  67
Table 14 System Clocking (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  71
Table 15 Output Jitter (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  73
Table 16 Receive Buffer Operating Modes (E1) . . . . . . . . . . . . . . . . . . . . . . . . .  75
Table 17 Allocation of Bits 1 to 8 of Time Slot 0 (E1) . . . . . . . . . . . . . . . . . . . . .  83
Table 18 Transmit Transparent Mode (Doubleframe E1) . . . . . . . . . . . . . . . . . .  84
Table 19 CRC-Multiframe Structure (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  86
Table 20 Transmit Transparent Mode (CRC Multiframe E1)  . . . . . . . . . . . . . . .  87
Table 21 Summary of Alarm Detection and Release (E1)  . . . . . . . . . . . . . . . . .  93
Table 22 Recommended Transmitter Configuration Values (E1) . . . . . . . . . . . .  98
Table 23 Transmit Buffer Operating Modes (E1)  . . . . . . . . . . . . . . . . . . . . . . .  101
Table 24 System Clocking and Data Rates (E1)  . . . . . . . . . . . . . . . . . . . . . . .  105
Table 25 Time Slot Assigner HDLC Channel 1 (E1). . . . . . . . . . . . . . . . . . . . .  116
Table 26 RCLK Output Selection (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  124
Table 27 Recommended Receiver Configuration Values (T1/J1). . . . . . . . . . .  125
Table 28 External Component Recommendations (Monitoring) . . . . . . . . . . . .  126
Table 29 System Clocking (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  130
Table 30 Output Jitter (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  133
Table 31 Channel Translation Modes (DS1/J1) . . . . . . . . . . . . . . . . . . . . . . . .  135
Table 32 Receive Buffer Operation Modes (T1/J1)  . . . . . . . . . . . . . . . . . . . . .  136
Table 33 Resynchronization Timing (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . .  144
Table 34 4-Frame Multiframe Structure (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . .  146
Table 35 12-Frame Multiframe Structure (T1/J1) . . . . . . . . . . . . . . . . . . . . . . .  147
Table 36 Extended Superframe Structure (F24, ESF; T1/J1). . . . . . . . . . . . . .  148
Table 37 72-Frame Multiframe Structure (T1/J1) . . . . . . . . . . . . . . . . . . . . . . .  152
Table 38 Summary Frame Recover/Out of Frame Conditions (T1/J1) . . . . . . .  154
Table 39 Summary of Alarm Detection and Release (T1/J1) . . . . . . . . . . . . . .  155
Table 40 Recommended Transmitter Configuration Values (T1/J1). . . . . . . . .  160
Table 41 Transmit Buffer Operating Modes (T1/J1) . . . . . . . . . . . . . . . . . . . . .  165
Table 42 Pulse Shaper Programming (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . .  165

FALC®56
PEF 2256 H/E
List of Tables Page
User’s Manual 14 DS1.1, 2003-10-23
Hardware Description
Table 43 Structure of Periodical Performance Report (T1/J1) . . . . . . . . . . . . .  170
Table 44 Bit Functions in Periodical Performance Report  . . . . . . . . . . . . . . . .  171
Table 45 System Clocking and Data Rates (T1/J1) . . . . . . . . . . . . . . . . . . . . .  172
Table 46 Time Slot Assigner HDLC Channel 1 (T1/J1)  . . . . . . . . . . . . . . . . . .  187
Table 47 Initial Values after Reset (E1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  195
Table 48 Initialization Parameters (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  197
Table 49 Line Interface Initialization (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  199
Table 50 Framer Initialization (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  199
Table 51 HDLC Controller Initialization (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . .  200
Table 52 CAS-CC Initialization (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  201
Table 53 Output Tristate Programming (E1). . . . . . . . . . . . . . . . . . . . . . . . . . .  202
Table 54 Initial Values after reset and FMR1.PMOD = 1 (T1/J1) . . . . . . . . . . .  203
Table 55 Initialization Parameters (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  206
Table 56 Line Interface Initialization (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . .  207
Table 57 Framer Initialization (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  208
Table 58 HDLC Controller Initialization (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . .  209
Table 59 Initialization of the CAS-BR Controller (T1/J1). . . . . . . . . . . . . . . . . .  209
Table 60 Output Tristate Programming (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . .  210
Table 61 E1 Control Register Address Arrangement . . . . . . . . . . . . . . . . . . . .  223
Table 62 DCO-R and DCO-X Corner Frequency Programing (E1)  . . . . . . . . .  274
Table 63 Transmit CAS Registers (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  276
Table 64 GCMx Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  293
Table 65 E1 Status Register Address Arrangement . . . . . . . . . . . . . . . . . . . . .  299
Table 66 Receive CAS Registers (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  336
Table 67 T1/J1 Control Register Address Arrangement . . . . . . . . . . . . . . . . . .  344
Table 68 Pulse Shaper Programming (T1/J1)  . . . . . . . . . . . . . . . . . . . . . . . . .  377
Table 69 DCO-R and DCO-X Corner Frequency Programing (T1/J1) . . . . . . .  400
Table 70 Transmit Signaling Registers (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . .  401
Table 71 GCMx Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  418
Table 72 T1/J1 Status Register Address Arrangement  . . . . . . . . . . . . . . . . . .  424
Table 73 Alarm Simulation States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  432
Table 74 Receive Signaling Registers (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . .  456
Table 75 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  464
Table 76 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  465
Table 77 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  466
Table 78 MCLK Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  469
Table 79 Boundary Scan Timing Parameter Values. . . . . . . . . . . . . . . . . . . . .  470
Table 80 Reset Timing Parameter Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  471
Table 81 Intel Bus Interface Timing Parameter Values  . . . . . . . . . . . . . . . . . .  474
Table 82 Motorola Bus Interface Timing Parameter Values . . . . . . . . . . . . . . .  476
Table 83 Digital Line Interface Timing Parameter Values. . . . . . . . . . . . . . . . .  478
Table 84 RCLK and RFSP Timing Parameter Values  . . . . . . . . . . . . . . . . . . .  480

FALC®56
PEF 2256 H/E
List of Tables Page
User’s Manual 15 DS1.1, 2003-10-23
Hardware Description
Table 85 SCLKR/SCLKX Timing Parameter Values. . . . . . . . . . . . . . . . . . . . .  481
Table 86 Receive System Interface Marker Timing Parameter Values  . . . . . .  482
Table 87 SYPR and SYPX Timing Parameter Values  . . . . . . . . . . . . . . . . . . .  483
Table 88 Transmit System Interface Marker Timing Parameter Values . . . . . .  485
Table 89 XDI and XSIG Timing Parameter Values. . . . . . . . . . . . . . . . . . . . . .  486
Table 90 TCLK Timing Parameter Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  487
Table 91 XCLK Timing Parameter Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  488
Table 92 SEC Timing Parameter Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  489
Table 93 FSC Timing Parameter Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  490
Table 94 SYNC Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .  491
Table 95 E1 Pulse Amplitude Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  492
Table 96 DCIM Pulse Output Amplitude Values . . . . . . . . . . . . . . . . . . . . . . . .  493
Table 97 T1 Pulse Template at Cross Connect Point (T1.102)  . . . . . . . . . . . .  494
Table 98 Capacitance Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  495
Table 99 Package Characteristic Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  495
Table 100 AC Test Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  496
Table 101 Power Supply Test Conditions E1 . . . . . . . . . . . . . . . . . . . . . . . . . . .  497
Table 102 Power Supply Test Conditions T1/J1. . . . . . . . . . . . . . . . . . . . . . . . .  498

FALC®56
PEF 2256 H/E
User’s Manual 16 DS1.1, 2003-10-23
Hardware Description
  
Preface
The FALC®56 framer and line interface component is designed to fulfill all required
interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100
bus.
The digital functions as well as the analog characteristics are configured via a flexible
microprocessor interface.
Organization of this Document
This User’s Manual is organized as follows:
•Chapter 1,  Introduction
Gives a general description of the product and its family, lists the key features, and
presents some typical applications.
•Chapter 2,  External Signals
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
•Chapter 3 to Chapter 5,  Functional Description E1/T1/J1
These chapters describe the functional blocks and principle operation modes,
organized into separate sections for E1 and T1/J1 operation
•Chapter 6 and Chapter 7,  Operational Description E1/T1/J1
Shows the operation modes and how they are to be initialized (separately for E1 and
T1/J1).
•Chapter 8,  Signaling Controller Operating Modes
Describes signaling controller functions for both E1 and T1/J1 operation.
•Chapter 9 and Chapter 10,  E1 Registers and  T1/J1 Registers
Gives a detailed description of all implemented registers and how to use them in
different applications/configurations.
•Chapter 11,  Electrical Characteristics
Specifies maximum ratings, DC and AC characteristics.
•Chapter 12,  Package Outlines
Shows the mechanical values of the device packages.
•Chapter 13,  Appendix
Gives an example for overvoltage protection and information about application notes
and other support.
•Terminology
•References
•Index

FALC®56

PEF 2256 H/E

Introduction

User’s Manual 17 DS1.1, 2003-10-23

Hardware Description

1 Introduction

The FALC®56 framer and line interface component is designed to fulfill all required

interfacing between analog E1/T1/J1 lines and the digital PCM system highway,

H.100/H.110 or H-MVIP bus for world market telecommunication systems.

Due to its multitude of implemented functions, it fits to a wide range of networking

applications and fulfills the according international standards. Three integrated signaling

controllers including Signaling System #7 (SS7) support reduces software overhead.

Crystal-less jitter attenuation with only one master clock source, integrated receive line

termination, and an analog switch reduce the amount of required external components.

Equipped with a flexible microprocessor interface, it connects to any control processor

environment. A standard boundary scan interface is provided to support board level

testing. Flat pack or BGA device packaging, minimum number of external components

and low power consumption lead to reduced overall system costs.

Type Package

PEF 2256 H P-MQFP-80-1

PEF 2256 E P-LBGA-81-1

E1/T1/J1 Framer and Line Interface Component for

Long- and Short-Haul Applications

FALC®56

PEF 2256 H/E

User’s Manual 18 DS1.1, 2003-10-23

Hardware Description

Version 2.1

1.1 Features

Line Interface

• High-density, generic interface for all

E1/T1/J1 applications

• Analog receive and transmit circuits for long-haul and

short-haul applications

• E1 or T1/J1 mode selectable

• Data and clock recovery using an integrated

digital phase-locked loop

• Maximum line attenuation up to -43 dB at 1024 kHz

(E1)

and up to -36 dB at 772 kHz (T1/J1)

• Programmable receive equalizer characteristic

• Software-selectable receive line termination

• Programmable transmit pulse shapes for E1 and

T1/J1 pulse masks

• Programmable line build-out for CSU signals

according to ANSI T1. 403 and FCC68: 0dB, -7.5 dB,

-15 dB, -22.5 dB (T1/J1)

• Low transmitter output impedances for high transmit return loss

• Tristate function of the analog transmit line outputs

• Analog switch for redundancy applications

• Transmit line monitor protecting the device from damage

• Receive line monitor mode

• Jitter specifications of ITU-T I.431, G.703, G.736 (E1), G.823 (E1) and AT&T

TR62411 (T1/J1) are met

• Crystal-less wander and jitter attenuation/compensation

P-MQFP-80-1

P-LBGA-81-1

FALC®56

PEF 2256 H/E

Introduction

User’s Manual 19 DS1.1, 2003-10-23

Hardware Description

• Common master clock reference for E1 and T1/J1

(any frequency within 1.02 and 20 MHz)

• Power-down function

• Support of automatic protection switching

• Dual-rail or single-rail digital inputs and outputs

• Unipolar NRZ or CMI for interfacing fiber-optical transmission routes

• Selectable line codes (E1: HDB3, AMI/T1: B8ZS, AMI with ZCS)

• Loss-of-signal indication with programmable thresholds according to ITU-T G.775,

ETS300233 (E1) and ANSI T1.403 (T1/J1)

• Optional data stream muting upon LOS detection

• Programmable receive slicer threshold

• Clock generator for jitter-free system/transmit clocks per channel

• Local loop and remote loop for diagnostic purposes

• Low power device

• Single power supply (3.3 V) or dual power supply (3.3 V and 1.8 V)

Frame Aligner

• Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704 (E1) and for

1544 kbit/s according to ITU-T G.704 and JT G.704 (T1/J1)

• Programmable frame formats:

E1: Doubleframe, CRC multiframe (E1)

T1: 4-frame multiframe (F4,FT), 12-frame multiframe (F12, D3/4), extended

superframe (F24, ESF), remote switch mode (F72, SLC96)

• Selectable conditions for recover/loss of frame alignment

•CRC4 to non-CRC4 interworking according to ITU-T G. 706 Annex B (E1)

•Error checking via CRC4 procedures according to ITU-T G. 706 (E1)

•Error checking via CRC6 procedures according to ITU-T G. 706 and JT G.706

(T1/J1)

•Performs synchronization in ESF format according to NTT requirements (J1)

• Alarm and performance monitoring per second

16 bit counter for CRC-errors, framing errors, code violations, error monitoring via

E-bit and SA6-bit (E1), errored blocks, PRBS bit errors

• Insertion and extraction of alarm indication signals (AIS, remote/yellow alarm,…)

• Remote alarm generation/checking according to ITU JT-G.704 in ESF-format (J1)

• IDLE code insertion for selectable channels

• Single-bit defect insertion

• Flexible system clock frequency for receiver and transmitter

• Supports programmable system data rates with independent receive/transmit shifts:

E1: 2.048, 4.096, 8.192 and 16.384 Mbit/s (according to H.100/H.110 bus)

T1/J1: 2.048, 4.096, 8.192, 16.384 Mbit/s and 1.544, 3.088, 6.176, 12.352 Mbit/s

• Elastic store for receive and transmit route clock wander and jitter compensation;

controlled slip capability and slip indication

FALC®56

PEF 2256 H/E

Introduction

User’s Manual 20 DS1.1, 2003-10-23

Hardware Description

• Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass

• Provides different time slot mapping modes

• Supports fractional E1 or T1/J1 access

• Flexible transparent modes

•Programmable in-band loop code detection and generation (TR62411)

•Channel loop back, line loop back or payload loop back capabilities (TR54016)

• Pseudo-random binary sequence generator and monitor

(framed or unframed)

• Clear channel capabilities (T1/J1)

• Loop-timed mode

Signaling Controller

• Three HDLC controllers

Bit stuffing, CRC check and generation, flag generation, flag and address

recognition, handling of bit oriented functions

• Each HDLC controller selectable to operate on either line or system side

• Supports signaling system #7

delimitation, alignment and error detection according to ITU-Q.703

processing of fill in signaling units, processing of errored signaling units

• CAS/CAS-BR controller with last look capability, enhanced CAS-register access and

freeze signaling indication

• DL-channel protocol for ESF format according to ANSI T1.403 specification or

according to AT&T TR54016 (T1/J1)

• DL-bit access for F72 (SLC96) format (T1/J1)

• Generates periodical performance report according to ANSI T1. 403

• Provides access to serial signaling data streams

• Multiframe synchronization and synthesis according to ITU-T G.732

• Alarm insertion and detection (AIS and LOS in time slot 16)

• Transparent mode

• FIFO buffers (64 bytes deep) for efficient transfer of data packets

• Time slot assignment

Any combination of time slots selectable for data transfer independent of signaling

mode (useful for fractional T1/J1 applications)

• Time-slot 0 Sa8...4-bit handling via FIFOs (E1)

• HDLC access to any Sa-bit combination (E1)

Microprocessor Interface

• 8/16-bit microprocessor bus interface (Intel or Motorola type)

• All registers directly accessible (byte or word access)

• Multiplexed and non-multiplexed address bus operations

• Hard/software reset options

• Extended interrupt capabilities

FALC®56

PEF 2256 H/E

Introduction

User’s Manual 21 DS1.1, 2003-10-23

Hardware Description

• One-second timer (internal or external timing reference)

General

• General input/output function included in multifunction ports

• Boundary scan standard IEEE 1149.1

• P-LBGA-81-1 package; body size 10 mm ×10 mm; ball pitch 1.0 mm or

• P-MQFP-80-1 package; body size 14 mm ×14 mm; lead pitch 0.5 mm

• Temperature range from -40 to +85 °C

• 3.3 V and 1.8 V power supply or 3.3 V-only operation

• Typical power consumption 250 mW

Applications

• Wireless basestations

• E1/T1/J1 ATM gateways, multiplexer

•E1/T1/J1 Channel & Data Service Units (CSU, DSU)

• E1/T1/J1 Internet access equipment

• LAN/WAN router

• ISDN PRI, PABX

•Digital Access Crossconnect Systems (DACS)

• SONET/SDH add/drop multiplexer

FALC®56

PEF 2256 H/E

Introduction

User’s Manual 22 DS1.1, 2003-10-23

Hardware Description

1.2 Typical Applications

Figure 1 shows a typical application used in GSM base stations.

Figure 1 GSM Base Station Aplication

F56V2_application_1

FALC56

Mi c ro-

processor

FALC56

EPI C

MUNICH

32/256

RS485RS485

E1/T1/J1

SEROCCO

2306+2312

DSP

RS485 RS485

SEROCCO

2306+2312

DSP

RS485 RS485

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 23 DS1.1, 2003-10-23

Hardware Description

2 External Signals

2.1 Logic Symbol

Figure 2 Logic Symbol

F56V2_logic_symbol

SCLKR

RDO

RPA

RPB

RPC

RPD

SCLKX

XDI

XPA

XPB

XPC

XPD

RL1/RDIP/ROID

RL2/RDIN/RCLKI

XL1/XDOP/XOID

XL2/XDON

TRS

TDI

TMS

TCK

TDO

RCLK

MCLK

SYNC

CLK1

CLK2

SEC/FSC

D(15:0)

A(7:0)

WR/RW

RD/DS

BHE/BLE

ALE

DBW

INT

RES

DDC

VSEL

AS1

AS2

FALC

PEF 2256

DDP

DDR

DDX

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 24 DS1.1, 2003-10-23

Hardware Description

2.2 Pin Diagram P-MQFP-80-1

Figure 3 Pin Configuration P-MQFP-80-1

F56V2_pin_configuration_pmqfp8

XPB

RPA

RDO

SCLKR

SCLKX

XPD

XPC

XPA

ALE

RD/ DS

WR/RW

BHE/BLE

XDI

INT

VDD

VSS

VDD

VSS

VDD

VSS

4144485256

VSEL

SYNC

SEC/FSC

D15

D14

D13

VSS

TMS

TD I

TRS

RES

DBW

VSS

VDDP

VSS

XL1/XDOP/XOID

VDDX

XL2/XDON

VDDR

RL1/RDIP/ROID

RL2/RDIN/RCLKI

AS2

AS1

TDO

TCK

2180

14 8 12 16 20

CLK1

RCLK

MCLK

VSS

VDD

RPD

RPC

RPB

CLK2

VSS

D12

D11

D10

VDD

VDDC

Top View

FALC®56

PEF 2256

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 25 DS1.1, 2003-10-23

Hardware Description

2.3 Pin Diagram P-LBGA-81-1

Figure 4 Pin Configuration P-LBGA-81-1

F56V2_pin_configuration_plbga8

21 3456789

SYNC RCLK V

RPB SCLKR XPC XPBV

SEC/

FSC CLK1 RPC RDO XPD XPA V

RL2/

RDIN

RL1/

RDIP CLK2 MC LK V

SCLKX INT V

BHE/

BLE

XL2/

XDON

DDX

DDR

XL1/

XDOP RPD RPA WR /R W XDI CSV

DDP

DBW V

N.C. A7 RD/DS A6 ALEIM

TMS RES D11 D8 A4 A1 A3 A5TRS

TDO TCK V

D6 D5 D3 A0 A2TDI

D13 D12 D9 D4 D2 D0 V

D14 D10 D7 D1 V

D15

Top View

DDC

VSEL

AS1 AS2

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 26 DS1.1, 2003-10-23

Hardware Description

2.4 Pin Description

This chapter describes the pin functions. There is no functional difference between

TQFP and BGA package. Pin numbers refer to the TQPP package while the ball

numbers refer to the BGA package.

2.4.1 Input/Output Signals

Table 1 Pin Definitions - Microprocessor Interface

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

50 (E6) A7 I PU Address Bus

These inputs interface with eight bits of the

system’s address bus to select one of the

internal registers for read or write.

49 (E8) A6

48 (F9) A5

47 (F6) A4

46 (F8) A3

45 (G9) A2

44 (F7) A1

43 (G8) A0

21 (J1) D15 I/O PU Data Bus

Bidirectional tristate data lines which

interface with the system’s data bus. Their

configuration is controlled by the level of pin

DBW (Data Bus Width), output drivers are

controlled by WR/RW (Write enable or

Read/Write selection).

22 (J2) D14

23 (H3) D13

26 (H4) D12

27 (F4) D11

28 (J4) D10

29 (H5) D9

30 (F5) D8

31 (J5) D7

32 (G5) D6

33 (G6) D5

36 (H6) D4

37 (G7) D3

38 (H7) D2

39 (J8) D1

40 (H8) D0

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 27 DS1.1, 2003-10-23

Hardware Description

51 (E9) ALE I PU Address Latch Enable

This signal allows the FALC®56 to be

connected to a multiplexed address/data bus

without the need for external latches. The

address information provided on lines A(7:0)

is internally latched with the falling edge of

ALE. In this application, pins A(7:0) must be

connected to the data bus pins externally.

In case of demultiplexed mode this pin can be

connected directly to VDD or can be left open.

52 (E7) RD IPURead Enable

Used in Intel bus mode. This signal indicates

a read operation. When the FALC®56 is

selected via CS, the RD signal enables the

bus drivers to output data from an internal

DS IPUData Strobe

Used in Motorola bus mode. This pin serves

as input to control read/write operations.

53 (D7) WR IPUWrite Enable

Used in Intel bus mode. This signal indicates

a write operation. When CS is active the

FALC®56 loads an internal register with data

provided on the data bus.

RW IPURead/Write Enable

Used in Motorola bus mode. This signal

distinguishes between read and write

operations.

Table 1 Pin Definitions - Microprocessor Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 28 DS1.1, 2003-10-23

Hardware Description

12 (E3) DBW I PU Data Bus Width

This input signal selects the bus interface

mode.

0BDBW_0, 8-bit mode, D(7:0) are active.

D(15:8) are internally pulled high and

can be left open.

1BDBW_1, 16-bit mode, D(15:0) are

active. Word transfer to/from the

internal registers is enabled. In case of

byte transfers, the active half of the bus

is determined by A0 and BHE/BLE and

the selected bus interface mode (via

pin IM). The unused half is internally

pulled high.

11 (E1) IM I PU Interface Mode

The level on this pin defines the bus interface

mode.

0BIM_0, Intel bus interface mode.

1BIM_1, Motorola bus interface mode.

54 (D9) CS IPUChip Select

A low signal selects the FALC®56 for read

and write operations. This allows to connect

multiple devices to a single data/address bus.

0BCS_0, device is selected for access.

1BCS_1, device is de-selected.

Table 1 Pin Definitions - Microprocessor Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 29 DS1.1, 2003-10-23

Hardware Description

55 (C9) BHE IPUBus High Enable

Used in Intel bus mode. If 16-bit bus interface

mode is enabled, this signal indicates a data

transfer on the upper byte of the data bus

D(15:8). In 8-bit bus interface mode this

signal has no function and should be tied to

VDD or left open.

BLE IPUBus Low Enable

Used in Motorola bus mode. If 16-bit bus

interface mode is enabled, this signal

indicates a data transfer on the lower byte of

the data bus D(7:0). In 8-bit bus interface

mode this signal has no function and should

be tied to VDD or left open

57 (C7) INT O oD/PP Interrupt Request

This signal serves as general interrupt

request for all interrupt sources. These

interrupt sources can be masked via registers

IMR(5:0). Interrupt status is reported via

registers GIS (Global Interrupt Status) and

ISR(5:0).

Output characteristics (push-pull active

low/high, open drain) are determined by

programming register IPC.

Table 1 Pin Definitions - Microprocessor Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 30 DS1.1, 2003-10-23

Hardware Description

Table 2 Pin Definitions - Line Interface

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

3 (C2) RL1 I analog Line Receiver Input 1

Analog input from the external transformer.

Selected by LIM1.DRS = 0.

RDIP I digital Receive Data Input Positive

Digital input for received dual-rail PCM(+)

route signal which is latched with the

internally recovered receive route clock. An

internal DPLL extracts the receive route clock

from the incoming data pulses. The duty cycle

of the received signal has to be close to 50%.

The dual-rail mode is selected if

LIM1.DRS = 1B and FMR0.RC1 = 1B.

Input polarity is selected by bit RC0.RDIS

(active low by default), line coding is selected

by FMR0.RC(1:0).

ROID I digital Receive Optical Interface Data

Unipolar data received from a fiber-optical

interface. Latching of data is done with the

falling edge of RCLKI. Input polarity is

selected by bit RC0.RDIS.

The single-rail mode is selected if

LIM1.DRS = 1B and FMR0.RC1 = 0B.

If CMI coding is selected

(FMR0.RC(1:0) = 01B), an internal DPLL

recovers clock and data, no clock signal on

RCLKI is required.

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 31 DS1.1, 2003-10-23

Hardware Description

2 (B1) RL2 I analog Line Receiver Input 2

Analog input from the external transformer.

Selected by LIM1.DRS = 0B.

RDIN I digital Receive Data Input Negative

Digital input for received dual-rail PCM(-)

route signal which is latched with the

internally recovered receive route clock. An

internal DPLL extracts the receive route clock

from the incoming data pulses. The duty cycle

of the received signal has to be close to 50%.

The dual-rail mode is selected if

LIM1.DRS = 1B and FMR0.RC1 = 1B.

Input polarity is selected by bit RC0.RDIS

(active low by default), line coding is selected

by FMR0.RC(1:0)

RCLKI I digital Receive Clock Input

Receive clock input for the optical interface if

LIM1.DRS = 1B and FMR0.RC(1:0) = 00B.

The clock frequency is 2.048 MHz (E1) or

1.544 MHz (T1/J1). RCLKI is ignored if CMI

coding is selected.

Table 2 Pin Definitions - Line Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 32 DS1.1, 2003-10-23

Hardware Description

7 (D4) XL1 O analog Transmit Line 1

Analog output to the external transformer.

Selected if LIM1.DRS = 0B. After reset this

pin is in high-impedance state until bit

FMR0.XC1 = 1B and XPM2.XLT = 0B.

More details about tristate modes are shown

in Table 53/Table 60.

XDOP O digital Transmit Data Output Positive

This digital output for transmitted dual-rail

PCM(+) route signals can provide

• half bauded signals with 50% duty cycle

(LIM0.XFB = 0B) or

• full bauded signals with 100% duty cycle

(LIM0.XFB = 1B)

The data is clocked with positive transitions of

XCLK in both cases. Output polarity is

selected by bit LIM0.XDOS (active low by

default). The dual-rail mode is selected if

LIM1.DRS = 1B and FMR0.XC1 = 1B. After

reset this pin is in high-impedance state until

XOID O digital Transmit Optical Interface Data

Unipolar data sent to a fiber-optical interface

with 2048 kbit/s (E1) or 1544 kbit/s (T1/J1)

which is clocked on the positive transitions of

XCLK. Clocking of NRZ-coded data is done

with 100% duty cycle. CMI-coded data is

shifted out with 50 % or 100 % duty cycle on

both transitions of XCLK according to the CMI

coding. Output polarity is selected by bit

LIM0.XDOS (active high by default). The

single-rail mode is selected if LIM1.DRS = 1B

and FMR0.XC1 = 0B. After reset this pin is in

high-impedance state until register

LIM1.DRS = 1B and XPM2.XLT = 0B.

Table 2 Pin Definitions - Line Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 33 DS1.1, 2003-10-23

Hardware Description

5 (C1) XL2 O analog Transmit Line 2

Analog output to the external transformer.

Selected if LIM1.DRS = 0B. After reset this

pin is in high-impedance state until bit

FMR0.XC1 = 1B and XPM2.XLT = 0B.

More details about tristate modes are shown

in Table 53/Table 60.

XDON O digital Transmit Data Output Negative

This digital output for transmitted dual-rail

PCM(-) route signals can provide

• half bauded signals with 50% duty cycle

(LIM0.XFB = 0B) or

• full bauded signals with 100% duty cycle

(LIM0.XFB = 1B)

The data is clocked with positive transitions of

XCLK in both cases. Output polarity is

selected by bit LIM0.XDOS (active low by

default). The dual-rail mode is selected if

LIM1.DRS = 1B and FMR0.XC1 = 1B. After

reset this pin is in high-impedance state until

XFM O digital Transmit Frame Marker

This digital output marks the first bit of every

frame transmitted on port XDOP. This

function is only available in the optical

interface mode (LIM1.DRS = 1B and

FMR0.XC1 = 0B). Data is clocked on positive

transitions of XCLK. After reset this pin is in

high-impedance state until register

LIM1.DRS = 1B and XPM2.XLT = 0B.

Note: In remote loop configuration the XFM

marker is not valid.

Table 2 Pin Definitions - Line Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 34 DS1.1, 2003-10-23

Hardware Description

Table 3 Pin Definitions - Clock Interface

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

73 (C4) MCLK I Master Clock

A reference clock of better than ± 32 ppm

accuracy in the range of 1.02 to 20 MHz must

be provided on this pin. The FALC®56

internally derives all necessary clocks from

this master (see registers GCM(8:1) for more

detail).

79 (A2) SYNC I PU Clock Synchronization of DCO-R

If a clock is detected on pin SYNC the DCO-R

circuitry of the FALC®56 synchronizes to this

1.544/2.048 MHz clock (see LIM0.MAS,

CMR1.DCS and CMR2.DCF). Additionally, in

master mode the FALC®56 is able to

synchronize to an 8-kHz reference clock

(IPC.SSYF = 1).

76 (B4) CLK1 O PU DCO-R Clock Output

Output of the de-jittered system clock

generated by the DCO-R circuit. Frequency

selection is done by setting control bits in

PC5/6. Selectable frequencies are:

E1: 16.384 MHz, 8.192 MHz, 4.096 MHz,

2.048 MHz or 8 kHz

T1/J1: 16.384 MHz, 12.352 MHz, 8.192 MHz,

6.176 MHz, 4.096 MHz, 3.088 MHz,

2.048 MHz, 1.544 MHz or 8 kHz

After reset this output is inactive and

internally pulled high.

Note: If DCO-R is not active

(SIC1.RBS(1:0) = 11B and

CMR1.RS1 = 0B), no clock is driven on

pin CLK1.

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 35 DS1.1, 2003-10-23

Hardware Description

77 (C3) CLK2 O PU DCO-X Clock Output

Output of the de-jittered system clock

generated by the DCO-X circuit. Frequency

selection is done by setting control bits in

PC5/6. Selectable frequencies are:

E1: 16.384 MHz, 8.192 MHz, 4.096 MHz or

2.048 MHz

T1/J1: 12.352 MHz, 6.176 MHz, 3.088 MHz

or 1.544 MHz

After reset this output is inactive and

internally pulled high.

Note: If DCO-X is not used, no clock is driven

on pin CLK2 (SIC1.XBS(1:0) = 00B and

CMR1.DXJA = 1B; buffer bypass and

no jitter attenuation)

Table 3 Pin Definitions - Clock Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 36 DS1.1, 2003-10-23

Hardware Description

78 (B3) SEC I PU One-Second Timer Reference Input

A pulse with logical high level for at least two

line clock cycles triggers the internal

one-second timer. After reset this pin is

configured to be an input. See register GPC1

for more detail.

OOne-Second Timer Output

Activated high once every second for the

duration of two line clock cycles.

FSC O Frame Synchronization Pulse

An 8-kHz Frame Synchronization Pulse is

output on this pin. The synchronization pulse

is active high or active low for one

2.048/1.544 MHz cycle ( E1 or T1/J1). FSC

can be switched into tri-state mode

(SIC3.FSCT)

Table 3 Pin Definitions - Clock Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 37 DS1.1, 2003-10-23

Hardware Description

75 (A3) RCLK O PU Receive Clock

After reset this port is configured to be

internally pulled up weakly. Setting of bit

PC5.CRP switches this port to be an active

output. Several output modes are provided,

selected by CMR1.RS(1:0).

CMR1.RS(1:0) = 00B:

Receive clock extracted from the incoming

data pulses. The clock frequency is

2.048 MHz (E1) or 1.544 MHz (T1/J1). In

case of Loss-Of-Signal (LOS) the output is

derived from the clock that is provided on

MCLK.

CMR1.RS(1:0) = 01B:

Receive clock extracted from the incoming

data pulses. The clock frequency is

2.048 MHz (E1) or 1.544 MHz (T1/J1). RCLK

remains high in case of LOS (as indicated by

FRS0.LOS = 1B).

CMR1.RS(1:0) = 10B:

Dejittered clock generated by the internal

DCO-R circuit. The clock frequency is

2.048 MHz (E1/T1/J1 and SIC2.SSC2 = 0B)

or 1.544 MHz (T1/J1 and SIC2.SSC2 = 1B).

CMR1.RS(1:0) = 11B:

Dejittered clock generated by the internal

DCO-R circuit. The clock frequency is

8.192 MHz (E1/T1/J1 and SIC2.SSC2 = 0B)

or 6.176 MHz (T1/J1 and SIC2.SSC2 = 1B).

Table 3 Pin Definitions - Clock Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 38 DS1.1, 2003-10-23

Hardware Description

Table 4 Pin Definitions - System Interface

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

66 (B6) RDO O Receive Data Output

Received data that is sent to the system

highway. Clocking of data is done with the

rising or falling edge (SIC3.RESR) of SCLKR

or RCLK, if the receive elastic store is

bypassed. The delay between the beginning

of time slot 0 and the initial edge of SCLKR

(after SYPR goes active) is determined by the

values of registers RC1 and RC0. If received

data is shifted out with higher data rates

(more than 2.048/1.544 Mbit/s), the active

channel phase is defined by bits

SIC2.SICS(2:0). During inactive channel

phases RDO is cleared (driven to low level or

tristate, see SIC3.RTRI on page 267/393).

65 (A7) SCLKR I/O PU Receive System Clock

Working clock for the receive system

interface with a frequency of

16.384/8.192/4.096/2.048 MHz in E1 mode

and 16.384/8.192/4.096/2.048 MHz

(SIC2.SSC2 = 0B) or

12.352/6.176/3.088/1.544 MHz

(SIC2.SSC2 = 1B) in T1/J1 mode. If the

receive elastic store is bypassed, the clock

supplied on this pin is ignored, because

RCLK is used to clock the receive system

interface. If SCLKR is configured to be an

output, the internal working clock of the

receive system interface sourced by DCO-R

or RCLK is output.

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 39 DS1.1, 2003-10-23

Hardware Description

67 (D6)

68 (A6)

69 (B5)

70 (D5)

RPA

RPB

RBC

RPD

Receive Multifunction Ports

Depending on programming of bits

PC(1:4).RPC(3:0) these multifunction ports

carry information to the system interface or

from the system to the FALC®56. After reset

these ports are configured to be inputs. With

the selection of the appropriate pin function,

the corresponding input/output configuration

is achieved automatically. Depending on bit

SIC3.RESR latching/transmission of data is

done with the rising or falling edge of SCLKR.

The same input function must not be selected

twice or more. Selectable pin functions are

described below.

IPUSynchronous Pulse Receive (SYPR)

PC(1:4).RPC(3:0) = 0000B

Together with the values of registers RC(1:0)

this signal defines the beginning of time slot 0

on system highway port RDO. Only one

multifunction port may be selected as SYPR

input. After reset, SYPR of port A is used, the

other lines are ignored. SYPR cannot be used

in combination with RFM. The pulse cycle is

an integer multiple of 125 µs.

Table 4 Pin Definitions - System Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 40 DS1.1, 2003-10-23

Hardware Description

67 (D6)

68 (A6)

69 (B5)

70 (D5)

RPA

RPB

RBC

RPD

OReceive Frame Marker (RFM)

PC(1:4).RPC(3:0) = 0010B

Two different modes are provided for this

signal, selected by CMR2.IRSP.

0BIRSP_0, The receive frame marker can

be active high for a 2.048 MHz (E1) or

1.544 MHz (T1/J1) period during any

bit position of the current frame. It is

clocked off with the rising or falling

edge of SCLKR or RCLK, depending

on SIC3.RESR. Offset programming is

done by using registers RC(1:0).

1BIRSP_1, Frame synchronization pulse

generated by the DCO-R circuitry

internally. Together with registers

RC(1:0) the frame begin on the receive

system interface is defined. This frame

synchronization pulse is active low for a

2.048 MHz (E1) or 1.544 MHz (T1/J1)

period.

OReceive Multiframe Begin (RMFB)

PC(1:4).RPC(3:0) = 0010B

In E1 mode RMFB marks the beginning of

every received multiframe (RDO). Optionally

the time slot 16 CAS multiframe begin can be

marked (SIC3.CASMF). Active high for one

2.048 MHz period.

In T1/J1 mode the function depends on bit

XC0.MFBS:

0BMFBS_0, RMFB marks the beginning

of every received multiframe (RDO).

1BMFBS_1, RMFB marks the beginning

of every received superframe.

Additional pulses are provided every 12

frames when using ESF/F24 or F72

format.

Table 4 Pin Definitions - System Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 41 DS1.1, 2003-10-23

Hardware Description

67 (D6)

68 (A6)

69 (B5)

70 (D5)

RPA

RPB

RBC

RPD

OReceive Signaling Marker (RSIGM)

PC(1:4).RPC(3:0) = 0011B

E1: Marks the time slots which are defined by

port RDO.

T1/J1: The function depend on the usage of

CAS-BR as selected by XC0.BRM.

0BBRM_0, marks the time slots which are

defined by register RTR(4:1) of every

received frame on port RDO.

1BBRM_1, the robbed bit of each channel

in every sixth frame is marked.

OReceive Signaling Data (RSIG)

PC(1:4).RPC(3:0) = 0100B

The received CAS signaling data is sourced

by this pin. Time slots on RSIG correlate

directly to the time slot assignment on RDO.

OData Link Bit Receive (DLR)

PC(1:4).RPC(3:0) = 0101B

E1: Marks the Sa(8:4)-bits within the data

stream on RDO. The Sa(8:4)-bit positions in

time slot 0 of every frame not containing the

frame alignment signal are selected by

T1/J1: Marks the DL-bit position within the

data stream on RDO.

OFrame Synchronous Pulse (RFSP)

PC(1:4).RPC(3:0) = 0111B

Active low framing pulse derived from the

received PCM route signal (line side, RCLK).

During loss of synchronization (bit

FRS0.LFA = 1B), this pulse is suppressed

(not influenced during alarm simulation).

Pulse frequency: 8 kHz

Pulse width: 488 ns (E1) or 648 ns (T1/J1).

Table 4 Pin Definitions - System Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 42 DS1.1, 2003-10-23

Hardware Description

67 (D6)

68 (A6)

69 (B5)

70 (D5)

RPA

RPB

RBC

RPD

OLoss of Signal Indication (LOS)

PC(1:4).RPC(3:0) = 1100B

The output signal reflects the Loss of Signal

status ss readable in FRS0.LOS

IPUGeneral Purpose Input (GPI)

PC(1:4).RPC(3:0) = 1001B

The digital signal level applied externally can

be read through a status register.

For unused RPAx pins this configuration is

recommended.

OGeneral Purpose Output High (GPOH)

PC(1:4).RPC(3:0) = 1010B

A fixed high output level is driven.

OGeneral Purpose Output Low (GPOL)

PC(1:4).RPC(3:0) = 1011B

A fixed low output level is driven.

56 (D8) XDI I Transmit Data Input

Transmit data received from the system

highway. Latching of data is done with rising

or falling transitions of SCLKX according to bit

SIC3.RESX. The delay between the

beginning of time slot 0 and the initial edge of

SCLKX (after SYPX goes active) is

determined by the registers XC(1:0). At

higher data rates (> 1.544/2.048 Mbit/s)

sampling of data is defined by bits

SIC2.SICS(2:0).

64 (C6) SCLKX I PU Transmit System Clock

Working clock for the transmit system

interface with a frequency of

16.384/8.192/4.096/2.048 in E1 mode and

16.384/8.192/4.096/2.048 MHz

(SIC2.SSC2 = 0) or

12.352/6.176/3.088/1.544 MHz

(SIC2.SSC2 = 1) in T1/J1 mode.

Table 4 Pin Definitions - System Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 43 DS1.1, 2003-10-23

Hardware Description

60 (B8)

61 (A9)

62 (A8)

63 (B7)

XPA

XPB

XBC

XPD

Transmit Multifunction Ports

Depending on programming of bits

PC(1:4).XPC(3:0) these multifunction ports

carry information to the system interface or

from the system to the FALC®56. After reset

the ports are configured to be inputs. With the

selection of the appropriate pin function, the

corresponding input/output configuration is

achieved automatically. Depending on bit

SIC3.RESX latching/transmission of data is

done with the rising or falling edge of SCLKX.

If not connected, an internal pullup transistor

ensures a high input level.

Each input function (SYPX, XMFS, XSIG or

TCLK) may only be selected once. SYPX and

XMFS must not be used in parallel.

Selectable pin functions are described below.

IPUSynchronous Pulse Transmit (SYPX)

PC(1:4).XPC(3:0) = 0000B

Together with the values of registers XC(0:1)

this signal defines the beginning of time slot 0

at system highway port XDI . The pulse cycle

is an integer multiple of 125 µs. SYPX must

not be used in parallel with XMFS.

IPUTransmit Multiframe Synchronization

(XMFS)

PC(1:4).XPC(3:0) = 0001B

This port defines the frame and multiframe

begin on the transmit system interface ports

XDI and XSIG. Depending on PC5.CXMFS

the signal on XMFS is active high or low.

XMFS must not be used in parallel with

SYPX.

Note: A new multiframe position has settled

at least one multiframe after pulse

XMFS has been supplied.

Table 4 Pin Definitions - System Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 44 DS1.1, 2003-10-23

Hardware Description

60 (B8)

61 (A9)

62 (A8)

63 (B7)

XPA

XPB

XBC

XPD

IPUTransmit Signaling Data (XSIG)

PC(1:4).XPC(3:0) = 0010B

Input for transmit signaling data received from

the signaling highway. Optionally,

(SIC3.TTRF = 1), sampling of XSIG data is

controlled by the active high XSIGM marker.

At higher data rates sampling of data is

defined by bits SIC2.SICS(2:0).

IPUTransmit Clock (TCLK)

PC(1:4).XPC(3:0) = 0011B

A 2.048/8.192-MHz (E1) or 1.544/6.176-MHz

(T1/J1) clock has to be sourced by the system

if the internally generated transmit clock

(generated by DCO-X) shall not be used.

Optionally this input is used as a

synchronization clock for the DCO-X circuitry

with a frequency of 2.048 (E1) or 1.544 MHz

(T1/J1).

OTransmit Multiframe Begin (XMFB)

PC(1:4).XPC(3:0) = 0100B

XMFB marks the beginning of every

transmitted multiframe on XDI. The signal is

active high for one 2.048 (E1) or 1.544 MHz

(T1/J1) period.

OTransmit Signaling Marker (XSIGM)

PC(1:4).XPC(3:0) = 0101B

E1: Marks the transmit time slots on XDI of

every frame which are defined by

T1/J1: Marks the transmit time slots on XDI of

every frame which are defined by

used). When using the CAS-BR

signaling scheme the robbed bit of

each channel in every sixth frame is

marked.

Table 4 Pin Definitions - System Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 45 DS1.1, 2003-10-23

Hardware Description

60 (B8)

61 (A9)

62 (A8)

63 (B7)

XPA

XPB

XBC

XPD

OData Link Bit Transmit (DLX)

PC(1:4).XPC(3:0) = 0110B

E1: Marks the Sa(8:4)-bits within the data

stream on XDI. The Sa(8:4)-bit

positions in time slot 0 of every frame

not containing the frame alignment

signal are selected by register

XC0.SA8E to XC0.SA4E.

T1/J1: This output provides a 4-kHz signal

which marks the DL-bit position within

the data stream on XDI (in ESF mode

only).

OTransmit Clock (XCLK)

PC(1:4).XPC(3:0) = 0111B

Transmit line clock of 2.048 MHz (E1) or

1.544 MHz (T1/J1) derived from SCLKX/R,

RCLK or generated internally by DCO

circuitries.

IPUTransmit Line Tristate (XLT)

PC(1:4).XPC(3:0) = 1000B

A high level on this port sets the transmit lines

XL1/2 or XDOP/N into tristate mode. This pin

function is logically ored with register bit

XPM2.XLT.

IPUGeneral Purpose Input (GPI)

PC(1:4).XPC(3:0) = 1001B

The digital signal level applied externally can

be read through a status register.

For unused XPAx pins this configuration is

recommended.

OGeneral Purpose Output High (GPOH)

PC(1:4).XPC(3:0) = 1010B

A fixed high output level is driven.

OGeneral Purpose Output Low (GPOL)

PC(1:4).XPC(3:0) = 1011B

A fixed low output level is driven.

Table 4 Pin Definitions - System Interface (cont’d)

Pin or

Ball No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 46 DS1.1, 2003-10-23

Hardware Description

Table 5 Miscellaneous Pin Definitions

Pin (Ball)

No.

Name Pin

Type

Buffer

Type

Function

Power Supply

80 (B2) VSEL I PU Voltage Selection for Digital Core

Selects between single and dual power

supply mode.

0BVSEL_0, dual power supply mode,

VDDC must be supplied with 1.8 V

while al other power supplies require

3.3 V.

1BVSEL_1, single power supply mode, all

power supply voltages are 3.3 V.

Note: Dual power supply mode is

recommended for lowest power

dissipation.

4 (D3) VDDR SPositive Power Supply - Analog Receiver

3.3 V ± 5%

6 (D2) VDDX SPositive Power Supply - Analog

Transmitter

3.3 V ± 5%

9 (E2) VDDP SPower Supply - System PLL

3.3 V ± 5%

74 (A4) VDDC SPower Supply - Digital Core

Connected to a 1.8-V ± 10% power supply in

dual supply mode.

Attention: This pin must not be used to

supply external devices.

9 (A5) VDD SPositive Power Supply - Digital Pads

3.3 V ± 5%

24 (C8)

34 (E2)

41 (G4)

58 (J6)

71 (J9)

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 47 DS1.1, 2003-10-23

Hardware Description

1 (A1) VSS SGround

All analog and digital circuits are connected to

a common ground within the device package.

8 (D1)

10 (E4)

10 (B9)

25 (C5)

35 (E4)

42 (H9)

59 (J3)

72 (J7)

Analog Switch

19 (H1) AS1 I/O analog Analog Switch

These pins provide the terminals for an

analog switch to be used in redundancy

applications.

20 (H2) AS2 I/O analog

Device Reset

13 (F3) RES IHardware Reset

During reset the FALC®56 needs an active

clock on pin MCLK. During reset all

bidirectional output stages are in input mode,

if signal RD is “high” (which disables the data

bus D(15:0) output drivers).

0BRES_0, device reset.

1BRES_1, operational mode.

JTAG Test Interface

14 (F1) TRS IPUTest Access Port (TAP) Reset

Initializes the boundary scan test logic. If the

boundary scan logic is not used, this pin must

be connected to RST or VSS

0BTRS_0, TAP controller reset.

1BTRS_1, TAP operational mode.

15 (G1) TDI IPUTest Data Input

Boundary scan input signal.

16 (F2) TMS IPUTest Mode Select

Boundary scan test mode select.

Table 5 Miscellaneous Pin Definitions (cont’d)

Pin (Ball)

No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

External Signals

User’s Manual 48 DS1.1, 2003-10-23

Hardware Description

Note: oD = open drain output

PP = push/pull output

PU = input or input/output comprising an internal pullup device

To override the internal pullup by an external pulldown, a resistor value of 22 k

Ω

is recommended.

The pullup devices are activated during reset, this means their state is undefined

until the reset signal has been applied.

Unused input pins containing pullups can be left open. Unused input pins without

pullups shall be connected to VDD or VSS level to prevent floating. Unused output

pins shall be left open.

17 (G3) TCK IPUTest Clock

Boundary scan test clock.

18 (G2) TDO OTest Data Output

Boundary scan output signal.

Unused Pins

- (E5) N.C. Reserved

This ball is not connected within the

P-LBGA-81-1 package but should be left

open for compatibility with future products.

There are no unused pins in the

P-MQFP-80-1 package.

Table 5 Miscellaneous Pin Definitions (cont’d)

Pin (Ball)

No.

Name Pin

Type

Buffer

Type

Function

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 49 DS1.1, 2003-10-23

Hardware Description

3 Functional Description E1/T1/J1

3.1 Functional Overview

The FALC®56 device contains analog and digital function blocks that are configured and

controlled by an external microprocessor or microcontroller. The functional block

diagram is shown in Figure 5.

The main interfaces are

• Receive and transmit line interface

• PCM system highway interface/H.100 bus

• Microprocessor interface

• Boundary scan interface

as well as several control lines for reset and clocking purpose.

The main internal functional blocks are

• Analog line receiver with equalizer network and clock/data recovery

• Analog line driver with programmable pulse shaper and line build out

• Central clock generation module

• Elastic buffers for receive and transmit direction

• Receive Framer, receive line decoding, alarm detection, PRBS and performance

monitoring

• Transmit framer, receive line encoding, alarm and PRBS generation

• Receive jitter attenuator

• Transmit jitter attenuator

• Three HDLC controllers (one of them including SS7 and BOM support) and CAS

signaling controller

• Test functions (loop switching local - remote - payload - single channel)

• Register access interface

• Boundary scan control

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 50 DS1.1, 2003-10-23

Hardware Description

3.2 Block Diagram

•

Figure 5 Block Diagram

F56V2_block_diagra

JTAG Boundary

Scan IEEE 1149 Clocking Unit

Microprocessor Interface

Intel/Motorola

Receive Jitter

Attenuator

Transmit Jitter

Attenuator

Long & Short Haul

Receive Line

Interface

Clock & Data

Recovery

Long & Short Haul

Line Transmit

Interface

Receive Framer

Alarm Detector

PRBS Monitor

Line Decoder

Pe rf o r m. Mo n i t o r

Receive

Elast ic

Bu f f er

Transmit

Elast ic

Bu f f er

Frame Generator

Alarm Generator

PRBS Generator

Line Coding

Signaling

Controller

HDLC/BOM/SS7

Signaling Controller

CAS-CC

CAS-BR

Receive

Syst e m

Interface

Transmit

Syst e m

Interface

TRS

TDI

TMS

TCK

TDO

D(15:0)

A(7:0)

WR/RW

RD/DS

AL E

BHE/ BL E

RES

INT

MCLK

SY NC

SE C/ FS C

CLK1

CLK2

RCLK

TCLK SC L KX

XPD

XPC

XPB

XPA

XDI

RPD

RPC

RPB

RPA

RDO

DBW

SCL KR

RL1

RDIP

ROID

RL2

RDIN

RCLKI

XL2

XDON

XFM

XL1

XDOP

XOI D

Re m ot e l o op + JATT

Local Loop

Payl oad Loop

RCLK

SCL KR

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 51 DS1.1, 2003-10-23

Hardware Description

3.3 Functional Blocks

3.3.1 Microprocessor Interface

The communication between the CPU and the FALC®56 is done using a set of directly

accessible registers. The interface can be configured as Intel or Motorola type with a

selectable data bus width of 8 or 16 bits.

The CPU transfers HDLC data to and from the FALC®56 (through 64-byte deep FIFOs

per direction), sets the operating modes, controls function sequences, and gets status

information by writing or reading control and status registers. All accesses can be done

as byte or word accesses if enabled. If 16-bit bus width is selected, access to

lower/upper part of the data bus is determined by address line A0 and signal BHE/BLE

as shown in Table 6 and Table 7.

Table 8 shows how the ALE (Address Latch Enable) line is used to control the bus

structure and interface type. The switching of ALE allows the FALC®56 to be directly

connected to a multiplexed address/data bus.

3.3.1.1 Mixed Byte/Word Access to the FIFOs

Reading from or writing to the internal FIFOs (RFIFO and XFIFO) can be done using a

8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode.

Randomly mixed byte/word access to the FIFOs is allowed without any restrictions.

Table 6 Data Bus Access (16-Bit Intel Mode)

BHE A0 Register Access FALC®56 Data Pins Used

0 0 FIFO word access

D(15:0)

0 1 Register byte access (odd addresses) D(15:8)

1 0 Register byte access (even addresses) D(7:0)

1 1 No transfer performed None

Table 7 Data Bus Access (16-Bit Motorola Mode)

BLE A0 Register Access FALC®56 Data Pins Used

0 0 FIFO word access

D(15:0)

0 1 Register byte access (odd addresses) D(7:0)

1 0 Register byte access (even addresses) D(15:8)

1 1 No transfer performed None

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 52 DS1.1, 2003-10-23

Hardware Description

The assignment of registers with even/odd addresses to the data lines in case of 16-bit

Intel (Address n + 1) (Address n)

Motorola (Address n) (Address n + 1)

↑↑

↓↓

n: even address

3.3.1.2 FIFO Structure

In transmit and receive direction of the signaling controller 64-byte deep FIFOs are

provided for the intermediate storage of data between the system internal highway and

the CPU interface. The FIFOs are divided into two halves of 32 bytes. Only one half is

accessible to the CPU at any time.

In case 16-bit data bus width is selected by fixing pin DBW to logical 1 word access to

the FIFOs is enabled. Data output to bus lines D(15:0) as a function of the selected

interface mode is shown in Figure 6 and Figure 7. Of course, byte access is also

allowed. The effective length of the accessible part of RFIFO can be changed from

32 bytes (reset value) down to 2 bytes.

Table 8 Selectable Bus and Microprocessor Interface Configuration

ALE IM Microprocessor interface Bus Structure

VSS/VDD 1 Motorola de-multiplexed

VSS/VDD 0 Intel de-multiplexed

switching 0 Intel multiplexed

Data Lines D15 D8 D7 D0

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 53 DS1.1, 2003-10-23

Hardware Description

Figure 6 FIFO Word Access (Intel Mode)

Figure 7 FIFO Word Access (Motorola Mode)

Byte 4

Byte 1

Byte 2

Byte 3

D15 D8 D7 D0

RFIFO

Byte 4

Byte 1

Byte 2

Byte 3

D15 D8 D7 D0

XFIFO

Byte 32 Byte 32

F0112

Byte 4

Byte 1

Byte 2

Byte 3

D15 D8 D7 D0

RFIFO

Byte 4

Byte 1

Byte 2

Byte 3

D15 D8 D7 D0

XFIFO

Byte 32 Byte 32

F0113

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 54 DS1.1, 2003-10-23

Hardware Description

3.3.1.3 Interrupt Interface

Special events in the FALC®56 are indicated by means of a single interrupt output with

programmable characteristics (open drain or push-pull, defined by register IPC), which

requests the CPU to read status information from the FALC®56, or to transfer data

from/to the FALC®56.

Since only one INT request output is provided, the cause of an interrupt must be

determined by the CPU by reading the FALC®56’s interrupt status registers (GIS,

ISR(5:0)). The interrupt on pin INT and the interrupt status bits are reset by reading the

interrupt status registers. Register ISR(5:0) are of type “clear on read“.

The structure of the interrupt status registers is shown in Figure 8.

Figure 8 Interrupt Status Registers

Each interrupt indication of registers ISR(5:0) can be selectively masked by setting the

according bit in the corresponding mask registers IMR(5:0). If the interrupt status bits are

masked they neither generate an interrupt at INT nor are they visible in ISR(5:0).

GIS, the non-maskable Global Interrupt Status Register, serves as pointer to pending

interrupts. After the FALC®56 has requested an interrupt by activating its INT pin, the

CPU should first read the Global Interrupt Status register GIS to identify the requesting

IMR0

F0127 V1.0

Global

Interrupt

Status

ISR0

ISR1

ISR2

ISR3

ISR4

ISR5

IMR1

ISR1

IMR2

ISR2

IMR3

ISR3

IMR4

ISR4

IMR5

ISR5

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 55 DS1.1, 2003-10-23

Hardware Description

interrupt source register. After reading the assigned interrupt status registers ISR(5:0),

the pointer in register GIS is cleared or updated if another interrupt requires service.

If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes

inactive. Updating of interrupt status registers ISR(5:0) and GIS is only prohibited during

read access.

Masked Interrupts Visible in Status Registers

Each interrupt source can be individually masked to prevent an interrupt to be generated.

Only unmasked interrupts trigger the interrupt line and are visible in their interrupt status

registers with active interrupt indications (GIS.ISR(5:0)).

An additional mode can be selected via bit GCR.VIS. In this mode, masked interrupt

status bits neither generate an interrupt on pin INT nor are they visible in GIS, but are

displayed in the corresponding interrupt status register(s) ISR(5:0).

This mode is useful when some interrupt status bits are to be polled in the individual

interrupt status registers.

Note: In the visible mode, all active interrupt status bits, whether the corresponding

actual interrupt is masked or not, are reset when the interrupt status register is

read. Thus, when polling of some interrupt status bits is desired, care must be

taken that unmasked interrupts are not lost in the process.

All unmasked interrupt statuses are treated as before.

Please note that whenever polling is used, all interrupt status registers concerned have

to be polled individually (no “hierarchical” polling possible), since GIS only contains

information on actually generated, which means unmasked interrupts.

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 56 DS1.1, 2003-10-23

Hardware Description

3.3.2 Boundary Scan Interface

In the FALC®56 a Test Access Port (TAP) controller is implemented. The essential part

of the TAP is a finite state machine (16 states) controlling the different operational modes

of the boundary scan. Both, TAP controller and boundary scan, meet the requirements

given by the JTAG standard IEEE 1149.1. Figure 9 gives an overview.

Figure 9 Block Diagram of Test Access Port and Boundary Scan

After switching on the device (power-on), a reset signal has to be applied to TRS, which

forces the TAP controller into test logic reset state.

For normal operation without boundary scan access, the boundary reset pin TRS can be

tied to the device reset pin RES.

If no boundary scan operation is used, TRS has to be connected to RST or VSS. TMS,

TCK and TDI do not need to be connected since pullup transistors ensure high input

levels in this case.

F0115

TRS

TCK

TMS

TDI

TDO

clock

test

control

data in

enable

data

out

Clock

Generation Reset

TAP Controller

finite state machine

instruction register

test signal generator

TAP controller reset

Identification Register

(32 bits)

control

bus

Boundary Scan

(n bits)

BD data in

BD data out

ID data out

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 57 DS1.1, 2003-10-23

Hardware Description

Test handling (boundary scan operation) is performed using the pins TCK (Test Clock),

TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the

TAP controller is not in its reset state, that means TRS is connected to VDD or it remains

unconnected due to its internal pull up. Test data at TDI is loaded with a clock signal

connected to TCK. "1" or "0" on TMS causes a transition from one controller state to

another; constant "1" on TMS leads to normal operation of the chip. The state machine

is shown in Figure 10.

An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells

(data out and enable) and an I/O-pin (I/O) uses three cells (data in, data out and enable).

Note that most functional output and input pins of the FALC®56 are tested as I/O pins in

boundary scan, hence using three cells. The desired test mode is selected by serially

loading a 8-bit instruction code into the instruction register through TDI (LSB first).

EXTEST is used to examine the interconnection of the devices on the board. In this test

mode at first all input pins capture the current level on the corresponding external

interconnection line, whereas all output pins are held at constant values ("0" or "1"). Then

the contents of the boundary scan is shifted to TDO. At the same time the next scan

vector is loaded from TDI. Subsequently all output pins are updated according to the new

boundary scan contents and all input pins again capture the current external level

afterwards, and so on.

SAMPLE is a test mode which provides a snapshot of pin levels during normal operation.

IDCODE: A 32-bit identification register is serially read out on pin TDO. It contains the

version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).

The LSB is fixed to "1".

The ID code field is set to: 0001 0000 0000 1011 1110 0000 1000 0011

Version = 3H, Part Number = 00BEH, Manufacturer = 083H (including LSB, fixed to "1")

BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.

An alphabetical overview of all TAP controller operation codes is given in Table 9.

Table 9 TAP Controller Instruction Codes

TAP Instruction Instruction Code

BYPASS 11111111

EXTEST 00000000

IDCODE 00000100

SAMPLE 00000001

reserved for device test 01010011

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 58 DS1.1, 2003-10-23

Hardware Description

Figure 10 JTAG TAP Controller State Machine

F56V2_JTAG_State_Machin

reset test logic

run test/idle select DR scan

capture data to DR

shift DR

exit1 DR

pause DR

exit2 DR

update DR

select IR scan

capture data to IR

shift IR

exit1 IR

pause IR

exit2 IR

update IR

01 1

TMS = 1

0 0

11 0 0

FALC®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual 59 DS1.1, 2003-10-23

Hardware Description

3.3.3 Master Clocking Unit

The FALC®56 provides a flexible clocking unit, which references to any clock in the

range of 1.02 to 20 MHz supplied on pin MCLK.

The clocking unit has to be tuned to the selected reference frequency by setting the

global clock mode registers GCM(8:1) accordingly.

The calculation formulas for the appropriate register settings can be found in

Chapter 9.2 on page 227 or Chapter 10.2 on page 348. A calculation tool is available

to evaluate the required register settings automatically (see Chapter 13.3 on page 501).

All required clocks for E1 or T1/J1 operation are generated by this circuit internally. The

global setting depends only on the selected master clock frequency and is the same for

E1 and T1/J1 because both clock rates are provided simultaneously.

To meet the E1 requirements the MCLK reference clock must have an accuracy of better

than ± 32 ppm. The synthesized clock can be controlled on pins CLK1, CLK2, RCLK,

SCLKR and XCLK.

Figure 11 Flexible Master Clock Unit

F56V2_clocking_1

Flexible Master Clock Unit

MCLK

E1 Clocks

T1/J1

Clocks

GCM1...GCM8

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PEF 2256 H/E

Functional Description E1/T1/J1

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Hardware Description

3.4 Power Supply

3.4.1 Power Supply Configuration

The FALC®56 uses two different supply voltages internally, which are 3.3 V and 1.8 V.

For compatibility reasons, it is possible to operate the device off a single 3.3 V power

supply. In this operation mode, the 1.8-V core voltage is generated internally using an

on-chip voltage regulator. In order to minimize the power consumption it is also possible

to operate the device using separate external 3.3-V and 1.8-V supplies. Suppl y voltage

selection is done by using control pin VSEL (Voltage SELect). See Figure 11 and

Figure 12 for more detail.

Note: The 1.8 V power supply requires de-coupling in either operation mode.

The voltage levels of VDD, VDDP, VDDX, and VDDR must always be above the VDDC

level, even during device power-up and power-down. Otherwise cross currents

through ESD protection diodes will occur.

Figure 12 Single Voltage Power Supply Mode

F56V2_power_supply_singl

DDP

DDX

DDR

SSP

SSX

SSR

DDC

VSEL

FALC

(can be left

open)

3.3 V

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PEF 2256 H/E

Functional Description E1/T1/J1

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Hardware Description

Figure 13 Dual Voltage Power Supply Mode

3.4.2 Power Supply De-Coupling

To gain best performance, the following values are recommended for the external

de-coupling between VDDC and VSS.

Table 10 Decoupling Capacitor Parameters

Parameter Value

Capacitance (CDEC) 470 nF ± 20 %, alternatively: 2 × 220 nF ± 20 %

Capacitor material Ceramic, type X7R or compatible

ESR < 30 mΩ

Loop inductance (LL)

between VDDC, capacitor

and next VSS pin

< 10 nH

F56V2_power_supply_du

DDX

DDR

DDP

DDC

3.3 V1.8 V

SSP

SSX

SSR

VSEL

FALC

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Functional Description E1/T1/J1

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Hardware Description

Figure 14 Decoupling Capacitor Placement

F56V2_power_supply_decouplin

DDC

DEC

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Hardware Description

4 Functional Description E1

4.1 Receive Path in E1 Mode

Figure 15 Receive Clock System (E1)

4.1.1 Receive Line Interface

For data input, three different data types are supported:

• Ternary coded signals received at multifunction ports RL1 and RL2 from a ternary

interface. The ternary interface is selected if LIM1.DRS is reset.

• Digital dual-rail signals received on ports RDIP and RDIN. The dual-rail interface is

selected if LIM1.DRS and FMR0.RC1 is set.

• Unipolar data on port ROID received from a fiber-optical interface. The optical

interface is selected if LIM1.DRS is set and FMR0.RC1 is reset.

4.1.2 Receive Short and Long-Haul Interface

The FALC®56 has an integrated short-haul and long-haul line interface, including a

receive equalization network and noise filtering. The line interface automatically adapts

Equalizer

Clock &

Data

Recovery

DPLL

Line

Decoder

Alarm

Detector

Analog

LOS

Detector

RDATA

RCLK

SYNC

RL1/RDIP/ROID

RL2/RDIN/RCLKI

DCO-R

Receive Jitter

Attenuator

MCLK

FSC

Receive

System

Interface

F0117

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Functional Description E1

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Hardware Description

to the received signal amplitude, no selection of long haul or short haul mode is

necessary.

4.1.3 Receive Equalization Network (E1)

The FALC®56 automatically recovers the signals received on pins RL1/2 in a range of

up to -43 dB. The maximum reachable length with a 22 AWG twisted pair cable is

1500 m. The integrated receive equalization network recovers signals with up to -43 dB

of cable attenuation. Noise filters eliminate the higher frequency part of the received

signals. The incoming data is peak-detected and sliced to produce the digital data

stream. The slicing level is software selectable in four steps (45%, 50%, 55%, 67%). For

typical E1 applications, a level of 50% is used. The received data is then forwarded to

the clock & data recovery unit.

The receive equalizer characteristic is programmable, for example to enable the use of

non-standard cable types or to adapt to specific receive conditions.

4.1.4 Receive Line Attenuation Indication (E1)

Status register RES reports the current receive line attenuation in a range from 0 to -43

dB in 25 steps of approximately 1.7 dB each. The least significant 5 bits of this register

indicate the cable attenuation in dB. These 5 bits are only valid in combination with the

most significant two bits (RES.EV1/0 = 01).

4.1.5 Receive Clock and Data Recovery (E1)

The analog received signal on port RL1/2 is equalized and then peak-detected to

produce a digital signal. The digital received signal on port RDIP/N is directly forwarded

to the DPLL. The receive clock and data recovery extracts the route clock from the data

stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data stream

into a single-rail, unipolar bit stream. The clock and data recovery uses an internally

generated high frequency clock based on MCLK.

The recovered route clock or a de-jittered clock can be output on pin RCLK as shown in

Table 11.

See also Table 14 on page 71 for details of master/slave clocking.

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Hardware Description

The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 UI.

In digital bipolar line interface mode the clock and data recovery requires HDB3 coded

signals with 50% duty cycle.

4.1.6 Receive Line Coding (E1)

The HDB3 line code or the AMI coding is provided for the data received from the ternary

or the dual rail interface. All code violations that do not correspond to zero substitution

rules are detected. If a bit error causes a code violation that leads to a valid substitution

pattern, this code violation is not detected and the substitution pattern is replaced by the

corresponding zero pattern. The detected errors increment the 16-bit code violation

counter. In case of the optical interface a selection between the NRZ code and the CMI

Code (1T2B) with HDB3 or AMI postprocessing is provided. If CMI code is selected the

receive route clock is recovered from the data stream. The CMI decoder does not correct

any errors. In case of NRZ coding data is latched with the falling edge of signal RCLKI.

The HDB3 code is used along with double violation detection or extended code violation

detection (selectable by FMR0.EXZE)). In AMI code all code violations are detected. The

detected errors increment the 16-bit code violation counter.

When using the optical interface with NRZ coding, the decoder is bypassed and no code

violations are detected.

Table 11 RCLK Output Selection (E1)

Clock Source RCLK Frequency CMR1.

DCS

CMR1.

RS1/0

Receive Data

(2.048 Mbit/s on RL1/RL2,

RDIP/RDIN or ROID)

2.048 MHz

(recovered clock) ×00

Receive Data

in case of LOS

Constant high 0 01

2.048 MHz

(generated by DCO-R,

synchronized on SYNC)

110

DCO-R 2.048 MHz ×10

8.192 MHz ×11

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Hardware Description

4.1.7 Receive Line Termination (E1)

The signal at the ternary interface is received at both ends of a transformer. A termination

resistor is used to achieve line impedance matching (see Figure 16 and Table 12).

The E1 operating modes 75 Ω or 120 Ω are selectable by switching an internal

termination resistor of 300 Ω (see LIM0.RTRS) in parallel. This selection does not require

the change of transformers.

Figure 16 Receiver Configuration (E1)

4.1.8 Receive Line Monitoring Mode

For short-haul applications like shown in Figure 17, the receive equalizer can be

switched into receive line monitoring mode (LIM0.RLM = 1). One device is used as a

short-haul receiver while the other is used as a short-haul monitor. In this mode the

receiver sensitivity is increased to detect an incoming signal of -20 dB resistive

attenuation. The required resistor values are given in Table 13.

Table 12 Recommended Receiver Configuration Values (E1)

Line Impedance External Resistor R2Internal Resistor R1 Transformer Ratio

t2:t

120 Ω120 Ω1)2)

1) This includes all parasitic effects caused by circuit board design.

2) Can be set to 100 Ω for common E1/T1 applications.

off (LIM0.RTRS = 0B)1 : 1

75 Ω75 Ω1) off (LIM0.RTRS = 0B)1 : 1

120 Ω1) 2) on (LIM0.RTRS = 1B)1 : 1

F56V2_Receiver_1

RL1

RL2

INT

Line

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Hardware Description

Figure 17 Receive Line Monitoring (E1)

Using the receive line monitor mode and the hardware tristate function of transmit lines

XL1/2, the FALC®56 now supports applications connecting two devices to one receive

and transmission line. In these kind of applications both devices are working in parallel

for redundancy purpose (see Figure 18). While one of them is driving the line, the other

one must be switched into transmit line tristate mode. If both channels are configured

identically and supplied with the same system data and clocks, the transmit path can be

switched from one channel to the other without causing a synchronization loss at the

remote end. Due to the use of the receive line monitor mode, this setup is limited to short

Table 13 External Component Recommendations (Monitoring)

Parameter1)

1) This includes all parasitic effects caused by circuit board design.

LIM0.RTRS Characteristic Impedance

75 Ω120 Ω

R1 0

B75 Ω± 1 % 120 Ω± 1 %

1B120 Ω± 1 % -

R20B75 Ω± 1 % 120 Ω± 1 %

1B120 Ω± 1 % -

R3xB330 Ω± 1 % 510 Ω± 1 %

t2 : t11 : 1 1 : 1

F56V2_Receiver_

Receiver

Monitor

RL1

E1/T1/J1

Receive

Line

LIM0.RLM=0

LIM0.RLM=1

R3R3

RL2

RL1

RL2

t2 : t1

resistive -20 dB network

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Hardware Description

haul applications. Switching between both devices can be done through the

microcontroller interface or by using the tristate hardware input pin as shown in the

figure.

Figure 18 Short Haul Protection Switching Application (E1)

For long haul redundancy requirements (see Figure 19), the analog switches can be

used to enable the line termination for the active device and to disable it for the stand-by

part. Switching between both devices is controled through the microcontroller interface.

F56V2_Receiver_2

E1/T1/J1

Receive

Line

RL1

RL2

RDO

RL1

RL2

RDO

XL1

XL2

E1/T1/J1

Transmit

Line

XDI

XL1

XL2

XDI

TRIST

active device

stand-by device

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Hardware Description

Figure 19 Long Haul Protection Switching Application (E1)

4.1.9 Loss-of-Signal Detection (E1)

There are different definitions for detecting Loss-Of-Signal (LOS) alarms in the ITU-T

G.775 and ETS 300233. The FALC®56 covers all these standards. The LOS indication

is performed by generating an interrupt (if not masked) and activating a status bit.

Additionally a LOS status change interrupt is programmable by using register GCR.SCI.

• Detection:

An alarm is generated if the incoming data stream has no pulses (no transitions) for

a certain number (N) of consecutive pulse periods. “No pulse” in the digital receive

interface means a logical zero on pins RDIP/RDIN/ROID. A pulse with an amplitude

less than Q dB below nominal is the criteria for “no pulse” in the analog receive

interface (LIM1.DRS = 0). The receive signal level Q is programmable by three

F56V2_Receiver_

E1/T1/J1

Receive

Line

RL1

RL2

RDO

RL1

RL2

RDO

XL1

XL2

E1/T1/J1

Transmit

Line

XDI

XL1

XL2

XDI

active device

stand-by device

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Hardware Description

control bits LIM1.RIL(2:0) (see Chapter 11.3 on page 466). The number N can be set

by an 8-bit register (PCD). The contents of the PCD register is multiplied by 16, which

results in the number of pulse periods, i.e. the time which has to suspend until the

alarm has to be detected. The programmable range is 16 to 4096 pulse periods.

ETS300233 requires detection intervals of at least 1 ms. This time period results

always in a LFA (Loss of Frame Alignment) before a LOS is detected.

• Recovery:

In general the recovery procedure starts after detecting a logical one (digital receive

interface) or a pulse (analog receive interface) with an amplitude more than Q dB

(defined by LIM1.RIL(2:0)) of the nominal pulse. The value in the 8-bit register PCR

defines the number of pulses (1 to 255) to clear the LOS alarm.

If a loss-of-signal condition is detected, the data stream can optionally be cleared

automatically to avoid bit errors before LOS is indicated. The selection is done by

LIM1.CLOS = 1.

4.1.10 Receive Jitter Attenuator (E1)

The receive jitter attenuator is placed in the receive path. The working clock is an

internally generated high frequency clock based on the clock provided on pin MCLK. The

jitter attenuator meets the requirements of ITU-T I.431, G. 736 to 739, G.823 and ETSI

TBR12/13.

The internal PLL circuitry DCO-R generates a "jitter-free" output clock which is directly

dependent on the phase difference of the incoming clock and the jitter attenuated

clock.The receive jitter attenuator can be synchronized either on the extracted receive

clock RCLK or on a 2.048-MHz/8-kHz clock provided on pin SYNC (8 kHz in master

mode only). The received data is written into the receive elastic buffer with RCLK and

are read out with the de-jittered clock sourced by DCO-R. The jitter attenuated clock can

be output on pins RCLK, CLK1 or SCLKR. Optionally an 8-kHz clock is provided on pin

SEC/FSC.

The DCO-R circuitry attenuates the incoming jittered clock starting at 2-Hz jitter

frequency with 20 dB per decade fall-off. Wander with a jitter frequency below 2 Hz is

bypassed unattenuatedly. The intrinsic jitter in the absence of any input jitter is < 0.02 UI.

For some applications it might be useful to start jitter attenuation at lower frequencies.

Therefore the corner frequency is switchable by the factor of ten down to 0.2 Hz

(LIM2.SCF).

The DCO-R circuitry is automatically centered to the nominal bit rate if the reference

clock on pin SYNC/RCLK is missed for 2, 3 or 4 of the 2.048-MHz clock periods. This

center function of DCO-R can be disabled (CMR2.DCF = 1) in order to accept a gapped

reference clock. In analog line interface mode RCLK is always running. Only in digital

line interface mode with single-rail data a gapped clock can occur.

The receive jitter attenuator works in two different modes:

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Hardware Description

•Slave mode

In slave mode (LIM0.MAS = 0) the DCO-R is synchronized with the recovered route

clock. In case of LOS the DCO-R switches automatically to Master mode. If bit

CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.

• Master mode

In master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no

clock is supplied on pin SYNC. If an external clock on the SYNC input is applied, the

DCO-R synchronizes to this input. The external frequency can be 2.048 MHz

(IPC.SSYF = 0) or 8.0 kHz (IPC.SSYF = 1).

The following table shows the clock modes with the corresponding synchronization

sources.

The jitter attenuator meets the jitter transfer requirements of the ITU-T I.431 and G.735

to 739 (refer to Figure 20)

Table 14 System Clocking (E1)

Mode Internal

LOS Active

SYNC

Input

System Clocks generated by DCO-R

Master independent Fixed to

VDD

DCO-R centered, if CMR2.DCF = 0.

(CMR2.DCF should not be set)

Master independent 2.048

MHz

Synchronized to SYNC input (external

2.048 MHz, IPC.SSYF = 0)

Master independent 8.0 kHz Synchronized to SYNC input (external 8.0 kHz,

IPC.SSYF = 1, CMR2.DCF = 0)

Slave no Fixed to

VDD

Synchronized to line RCLK

Slave no 2.048

MHz

Synchronized to line RCLK

Slave yes Fixed to

VDD

CMR1.DCS = 0:

DCO-R is centered, if CMR2.DCF = 0.

(CMR2.DCF should not be set)

CMR1.DCS = 1:

Synchronized on line RCLK

Slave yes 2.048

MHz

CMR1.DCS = 0:

Synchronized to SYNC input

(external 2.048 MHz)

CMR1.DCS = 1:

Synchronized on line clock RCLK

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Hardware Description

Figure 20 Jitter Attenuation Performance (E1)

Also the requirements of ETSI TBR 12/13 are satisfied. Insuring adequate margin

against TBR 12/13 output jitter limit with 15 UI input at 20 Hz the DCO-R circuitry starts

jitter attenuation at about 2 Hz.

ITD10312

-60

Frequency

Attenuation

10 100 1000 10000 100000Hz

ITU G.736 Template

-50

-40

-30

-20

-10

dB FALC

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Hardware Description

4.1.11 Jitter Tolerance (E1)

The FALC®56 receiver’s tolerance to input jitter complies with ITU requirements.

Figure 21 shows the curves of different input jitter specifications stated below as well as

the FALC®56 performance.

Figure 21 Jitter Tolerance (E1)

4.1.12 Output Jitter (E1)

In the absence of any input jitter the FALC®56 generates the output jitter which is

specified in theTable 15 below.

Table 15 Output Jitter (E1)

Specification Measurement Filter Bandwidth Output Jitter

(UI peak to peak)

Lower Cutoff Upper Cutoff

ITU-T I.431 20 Hz 100 kHz < 0.015

700 Hz 100 kHz < 0.015

ETSI TBR 12 40 Hz 100 kHz < 0.11

Jitter Amplitude

Jitter Frequency

1 10 100 1000 10000 100000Hz

0.1

100

1000

PUB 62411

TR-NWT 000499 Cat II

CCITT G.823

ITU-T I.431

FALC

F0025

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Hardware Description

4.1.13 Framer/Synchronizer (E1)

The following functions are performed:

• Synchronization on pulse frame and multiframe

• Error indication when synchronization is lost. In this case, AIS is sent automatically

to the system side and remote alarm is sent to the remote end if enabled.

• Initiating and controlling of resynchronization after reaching the asynchronous state.

This can be done automatically by the FALC®56 or user controlled using the

microprocessor interface.

• Detection of remote alarm indication from the incoming data stream.

• Separation of service bits and data link bits. This information is stored in status

registers.

• Generation of various maskable interrupt statuses of the receiver functions.

• Generation of control signals to synchronize the CRC checker, and the receive

elastic buffer.

If programmed and applicable to the selected multiframe format, CRC checking of the

incoming data stream is done by generating check bits for a CRC submultiframe

according to the CRC4 procedure (as defined in ITU-T G.704). These bits are compared

with those check bits that are received during the next CRC submultiframe. If there is at

least one mismatch, the 16-bit CRC error counter is incremented.

4.1.14 Receive Elastic Buffer (E1)

The received bit stream is stored in the receive elastic buffer. The memory is organized

as a two-frame elastic buffer with a maximum size of 64 ×8 bit. The size of the elastic

buffer can be configured independently for the receive and transmit direction.

Programming of the receive buffer size is done by SIC1.RBS1/0:

• RBS1/0 = 00: two frame buffer or 512 bits

Maximum of wander amplitude (peak-to-peak): 190 UI (1 UI = 488 ns)

average delay after performing a slip: 1 frame or 256 bits

• RBS1/0 = 01: one frame buffer or 256 bits

Maximum of wander amplitude: 100 UI

average delay after performing a slip: 128 bits, (SYPR = output)

• RBS1/0 = 10: short buffer or 96 bits

Maximum of wander amplitude: 38 UI

average delay after performing a slip: 48 bits, (SYPR = output)

• RBS1/0 = 11: Bypass of the receive elastic buffer

The buffer functions are:

• Clock adaption between system clock (SCLKR) and internally generated route clock

(RCLK).

• Compensation of input wander and jitter.

• Frame alignment between system frame and receive route frame

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Hardware Description

• Reporting and controlling of slips

Controlled by special signals generated by the receiver, the unipolar bit stream is

converted into bit-parallel data which is circularly written to the elastic buffer using

internally generated receive route clock (RCLK).

Reading of stored data is controlled by the system clock sourced by SCLKR or by the

receive jitter attenuator and the synchronization pulse (SYPR) together with the

programmed offset values for the receive time slot/clock slot counters. After conversion

into a serial data stream, the data is given out on port RDO. If the receive buffer is

bypassed, programming of the time slot offset is disabled and data is clocked off with

RCLK instead of SCLKR.

In one frame or short buffer mode the delay through the receive buffer is reduced to an

average delay of 128 or 46 bits. In bypass mode the time slot assigner is disabled. In this

case SYPR programmed as input is ignored. Slips are performed in all buffer modes

except bypass mode. After a slip is detected the read pointer is adjusted to one half of

the current buffer size.

Table 16 gives an overview of the receive buffer operating mode.

In single frame mode (SIC1.RBS), values of receive time slot offset (RC1/0) have to be

specified great enough to prevent too great approach of frame begin of line side and

frame begin of system side.

Figure 22 gives an idea of operation of the receive elastic buffer:

A slip condition is detected when the write pointer (W) and the read pointer (R) of the

memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a

slip condition is detected, a negative slip (one frame or one half of the current buffer size

Table 16 Receive Buffer Operating Modes (E1)

Buffer Size

(SIC1.RBS1/0)

TS Offset programming

(RC1/0) + SYPR = input

Slip performance

bypass1)

1) In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK.

disabled

recommended:

SYPR = output

short buffer not recommended,

recommended:

SYPR = output

yes

1 frame not recommended,

recommended:

SYPR = output

yes

2 frames enabled yes

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Hardware Description

is skipped) or a positive slip (one frame or one half of the current buffer size is read out

twice) is performed at the system interface, depending on the difference between RCLK

and the current working clock of the receive backplane interface. I.e. on the position of

pointer R and W within the memory. A positive/negative slip is indicated in the interrupt

status bits ISR3.RSP and ISR3.RSN.

Figure 22 The Receive Elastic Buffer as Circularly Organized Memory

Limits for Slip Detection (mode dependent)

Read Pointer (System Clock controlled)

Write Pointer (Route Clock controlled)

R’

S+, S-

Frame 2 Time Slots

S-

Frame 1 Time Slots

Moment of Slip Detection

ITD10952

WS+

Slip

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4.1.15 Receive Signaling Controller (E1)

The signaling controller can be programmed to operate in various signaling modes. The

FALC®56 performs the following signaling and data link methods.

4.1.15.1 HDLC or LAPD Access

The FALC®56 offers three independent HDLC channels. Any HDLC channel can be

attached either to the line side ("normal HDLC") or to the system side ("inverse HDLC").

Each of them provides the following features:

• 64 byte receive FIFO for each channel

• 64 byte transmit FIFO for each channel

• transmission in one of 31 time slots

(time slot number programmable for each channel individually)

• transmission in even frames only, odd frames only or both

(programmable for each channel individually)

• bit positions to be used in selected time slots are maskable

(any bit position can be enabled for each channel individually)

• HDLC or transparent mode

• flag detection

• CRC checking

• bit-stuffing

• flexible address recognition (1 byte, 2 bytes)

• C/R-bit processing (according to LAPD protocol)

In addition to this, HDLC channel 1 provides:

• SS7 support

• BOM (bit oriented message) support

• use of time slot 0 (up to 32 time slots)

•use of S

a-bits

• flexibility to insert and extract data during certain time slots, any combination of time

slots can be programmed independently for the receive and transmit direction

In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD

according to Q.921 is supported. The signaling controller of the FALC®56 performs the

flag detection, CRC checking, address comparison and zero-bit removing. The received

data flow and the address recognition features can be performed in very flexible way, to

satisfy almost any practical requirements. Depending on the selected address mode, the

FALC®56 performs a 1 or 2-byte address recognition. If a 2-byte address field is

selected, the high address byte is compared with the fixed value FEH or FCH (group

address) as well as with two individually programmable values in RAH1 and RAH2

registers. According to the ISDN LAPD protocol, bit 1 of the high byte address is

interpreted as command/response bit (C/R) and is excluded from the address

comparison. Buffering of receive data is done in a 64 byte deep RFIFO.

In signaling controller transparent mode, fully transparent data reception without HDLC

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framing is performed, i.e. without flag recognition, CRC checking or bit stuffing. This

allows user specific protocol variations.

4.1.15.2 Support of Signaling System #7

The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is

described in ITU-Q.703. The following description assumes, that the reader is familiar

with the SS7 protocol definition.

SS7 support must be activated by setting the MODE register. The SS7 protocol is

supported by the following hardware features in receive mode:

• All Signaling Units (SU) are stored in the receive FIFO (RFIFO)

• Detecting of flags from the incoming data stream

• Bit stuffing (zero deletion)

• Checking of seven or more consecutive ones in the receive data stream

• Checking if the received Signaling Unit is a multiple of eight bits and at least six octets

including the opening flag

• Calculation of the CRC16 checksum:

In receive direction the calculated checksum is compared to the received one; errors

are reported in register RSIS.

• Checking if the signal information field of a received signaling unit consists of more

than 272 octets, in this case the current signaling unit is discarded.

In order to reduce the microprocessor load, fill In signaling units (FISUs) are processed

automatically. By examining the length indicator of a received signal unit the FALC®56

decides whether a FISU has been received. Consecutively received FISUs are

compared and optionally not stored in the receive FIFO (RFIFO, 2×32 bytes), if the

contents is equal to the previous one. The same applies to link status signaling units, if

bit CCR5.CSF is set. The different types of signaling units as message signaling unit

(MSU), link status signaling unit (LSSU) and fill in signaling units (FISU) are indicated in

the RSIS register, which is automatically added to the RFIFO with each received

signaling unit. The complete signaling unit except start and end flags is stored in the

receive FIFO. The functions of bits CCR1.RCRC and CCR1.RADD are still valid in SS7

mode. Errored signaling units are handled automatically according to ITU-T Q.703 as

shown in Figure 23. SU counter (su) and errored SU counter (Cs) are reset by setting

CMDR2.RSUC. The error threshold T can be selected to be 64 (default) or 32 by

setting/clearing bit CCR5.SUET. If the defined error limit is exceeded, an interrupt

(ISR1.SUEX) is generated, if not masked by IMR1.SUEX = 1.

Note: If SUEX is caused by an aborted/invalid frame, the interrupt will be issued

regularly until a valid frame is received (e.g. a FISU).

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Hardware Description

Figure 23 Automatic Handling of Errored Signaling Units

Reset Counter values

:= 0

su := 0

[CMDR2.RSUC = 1]

Idle

in service

SU in error?

:= C

+ 1

su := su + 1 su := su + 1

= T

su = 256 ?

su := 0

= 0

:= C

-1

in service

Link failure

[ISR1.SUEX = 1]

Idle

Notes:

su: signaling units counter

: errored signaling units

counter

T: error threshold (64 or 32),

selectable by CCR5.SUET

F0071

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4.1.15.3 Sa-Bit Access (E1)

The FALC®56 supports the Sa-bit signaling of time slot 0 of every other frame as follows:

• The access through register RSW

• The access through registers RSA(8:4), capable of storing the information for a

complete multiframe

• The access through the 64 byte deep receive FIFO of the signaling controller of

HDLC channel 1. This Sa-bit access gives the opportunity to receive a transparent bit

stream as well as HDLC frames where the signaling controller automatically

processes the HDLC protocol. Any combination of Sa-bits which shall be extracted

and stored in the RFIFO is selected by XC0.SA(8:4). The access to the RFIFO is

supported by ISR0.RME/RPF.

4.1.15.4 Channel Associated Signaling CAS (E1, serial mode)

The signaling information is carried in time slot 16 (TS16). The signaling controller

samples the bit stream either on the receive line side or if external signaling is enabled

on the receive system side. External signaling is enabled by selecting the RSIG pin

function in registers PC(4:1) and setting XSP.CASEN = 1.

Optionally the complete CAS multiframe can be transmitted on pin RSIG. The signaling

data is clocked with the working clock of the receive highway (SCLKR) together with the

receive synchronization pulse (SYPR). Data on RSIG is transmitted in the last 4 bits per

time slot and is aligned to the data on RDO. The first 4 bits per time slot can be optionally

fixed high or low (SIC2.SSF), except for time slot 0 and 16 (bit 1 to 4 are always "0000"

in TS16). In time slot 0 the FAS/NFAS word is transmitted, in time slot 16 the CAS

multiframe pattern "0000XYXX". Data on RSIG is only valid if the freeze signaling status

is inactive. With FMR1.SAIS an all-ones data stream can be transmitted on RDO and

RSIG.

The signaling procedure is done as it is described in ITU-T G.704 and G.732.

The main functions are:

• Synchronization to a CAS multiframe

• Detection of AIS and remote alarm in CAS multiframes

• Separation of CAS service bits X1 to X3

Updating of the received signaling information is controlled by the freeze signaling

status. The freeze signaling status is automatically activated if a loss-of-signal

(FRS0.LOS = 1), or a loss of CAS multiframe alignment (FRS1.TSL16LFA = 1) or a

receive slip occurs. The current freeze status is output on port FREEZE (RP(A:D)) and

indicated by register SIS.SFS. Optionally automatic freeze signaling can be disabled by

setting bit SIC3.DAF.

After CAS resynchronization an interrupt is generated. Because at this time the signaling

is still frozen, CAS data is not valid yet. Readout of CAS data has to be delayed until the

next CAS multiframe is received.

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Because the CAS controller is working on the PCM highway side of the receive buffer,

slips disturb the CAS data.

Figure 24 2.048 MHz Receive Signaling Highway (E1)

4.1.15.5 Channel Associated Signaling CAS (E1, µP access mode)

The signaling information is carried in time slot 16 (TS16). Receive data is stored in

registers RS(16:1) aligned to the CAS multiframe boundary. The signaling controller

samples the bit stream either on the receive line side or if external signaling is enabled

on the receive system side.

The signaling procedure is done as it is described in ITU-T G.704 and G.732.

The main functions are:

• Synchronization to a CAS multiframe

• Detection of AIS and remote alarm in CAS multiframes

• Separation of CAS service bits X1 to X3

• Storing of received signaling data in registers RS(16:1) with last look capability

Updating of the received signaling information is controlled by the freeze signaling

status. The freeze signaling status is automatically activated if a loss-of-signal

(FRS0.LOS = 1), or a loss of CAS multiframe alignment (FRS1.TSL16LFA = 1) or a

receive slip occurs. The current freeze status is output on port FREEZE (RP(A:D)) and

indicated by register SIS.SFS. Optionally automatic freeze signaling can be disabled by

setting bit SIC3.DAF. If SIS.SFS is active, updating of the registers RS(16:1) is disabled.

To relieve the µP load from always reading the complete RS(16:1) buffer every 2 ms the

FALC®56 notifies the µP through interrupt ISR0.CASC only when signaling changes

F0133

A B C D A B C D

4 5 6 7 0 1 2 3 4 5 6 7

TS31 TS0 TS1

0 0 0 0 X Y X X

0 1 2 3 4 5 6 7

TS16

A B C D

0 1 2 3 4 5 6 7

TS31

RSIG

RDO

SCLKR

FAS/NFAS

SYPR

125 µs

T = Time slot offset (RC0, RC1)

FAS = Frame alignment signal

NFAS = TS0 not containing FAS

ABCD = Signaling bits for time slots 1...15 and 17...31 of CAS multiframe

0000XYXX = CAS multiframe alignment signal in TS16

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from one multiframe to the next. Additionally the FALC®56 generates a receive signaling

data change pointer (RSP1/2) which directly points to the updated RS(16:1) register.

Because the CAS controller is working on the PCM highway side of the receive buffer,

slips disturb the CAS data.

4.2 Framer Operating Modes (E1)

4.2.1 General

Bit: FMR1.PMOD = 0

PCM line bit rate : 2.048 Mbit/s

Single frame length : 256 bit, No. 1…256

Framing frequency : 8 kHz

HDLC controller : n ×64 kbit/s, n = 1 to 32 or n×4 kbit/s, n = 1 to 5

Organization : 32 time slots, No. 0…31

with 8 bits each, No. 1…8

The operating mode of the FALC®56 is selected by programming the carrier data rate

and characteristics, line code, multiframe structure, and signaling scheme.

The FALC®56 implements all of the standard framing structures for E1 or PCM 30

(CEPT, 2.048 Mbit/s) carriers. The internal HDLC or CAS controller supports all

signaling procedures including signaling frame synchronization/synthesis and signaling

alarm detection in all framing formats. The time slot assignment from the PCM line to the

system highway and vice versa is performed without any changes of numbering (TS0 ↔

TS0, …, TS31 ↔ TS31).

Summary of E1 Framing Modes

• Doubleframe format according to ITU-T G. 704

• Multiframe format according to ITU-T G. 704

• CRC4 processing according to ITU-T G. 706

• Multiframe format with CRC4 to non CRC4 interworking according to ITU-T G. 706

• Multiframe format with modified CRC4 to non CRC4 interworking

• Multiframe format with CRC4 performance monitoring

After reset, the FALC®56 is switched into doubleframe format automatically. Switching

between the framing formats is done by programming bits FMR2.RFS1/0 and

FMR3.EXTIW for the receiver and FMR1.XFS for the transmitter.

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4.2.2 Doubleframe Format (E1)

The framing structure is defined by the contents of time slot 0 (refer to Table 17).

Table 17 Allocation of Bits 1 to 8 of Time Slot 0 (E1)

Bit

AlternateNumber

Frames

12 345678

Frame Containing the

Frame Alignment Signal Si0 011011

Note 1) Frame Alignment Signal

Frame not Containing the

Frame Alignment Signal

Service Word

Si1AS

a4 Sa5 Sa6 Sa7 Sa8

Note 1)

1) Si-bits: reserved for international use. If not used, these bits should be fixed to "1". Access to received

information trough bits RSW.RSI and RSP.RSIF. Transmission is enabled by bits XSW.XSIS and XSP.XSIF.

Note 2)

2) Fixed to "1". Used for synchronization.

Note 3)

3) Remote alarm indication: In undisturbed operation "0"; in alarm condition "1".

Note 4)

4) Sa-bits: Reserved for national use. If not used, they should be fixed at "1". Access to received information

trough bits RSW.RY0…4. Transmission is enabled by bits XSW.XY0…4. HDLC signaling in bits Sa4 to 8 is

selectable. As a special extension for double frame format, the Sa-bit registers RSA4 to 8/XSA4 to 8 can be

used optionally.

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Hardware Description

4.2.2.1 Transmit Transparent Modes

In transmit direction, contents of time slot 0 frame alignment signal of the outgoing PCM

frame are normally generated by the FALC®56. However, transparency for the complete

time slot 0 can be achieved by selecting the transparent mode XSP.TT0. With the

Transparent Service Word Mask register TSWM the Si-bits, A-bit and the Sa-bits can be

selectively switched through transparently.

4.2.2.2 Synchronization Procedure

Synchronization status is reported by bit FRS0.LFA. Framing errors are counted by the

Framing Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4

consecutive incorrect FAS words or 3 or 4 consecutive incorrect service words (bit 2 = 0

in time slot 0 of every other frame not containing the frame alignment word), the selection

is done by bit RC0.ASY4. Additionally, the service word condition can be disabled. When

the framer lost its synchronization an interrupt status bit ISR2.LFA is generated.

In asynchronous state, counting of framing errors and detection of remote alarm is

stopped. AIS is automatically sent to the backplane interface (can be disabled by bit

FMR2.DAIS).

Further on the updating of the registers RSW, RSP, RSA(8:4), RSA6S and RS(16:1) is

halted (remote alarm indication, Sa/Si-Bit access).

The resynchronization procedure starts automatically after reaching the asynchronous

state. Additionally, it can be invoked user controlled by bit FMR0.FRS (force

resynchronization, the FAS word detection is interrupted until the framer is in the

asynchronous state. After that, resynchronization starts automatically).

Synchronous state is established after detecting:

• A correct FAS word in frame n,

Table 18 Transmit Transparent Mode (Doubleframe E1)

Enabled by Transmit Transparent Source for

Framing A-Bit Sa-Bits Si-Bits

–

XSP.TT0

TSWM.TSIF

TSWM.TSIS

TSWM.TRA

TSWM.TSA(8:4)

(int. gen.)

via pin XDI1)

(int. gen.)

1) pin XDI or XSIG or XFIFO buffer (signaling controller)

XSW.XRA2)

via pin XDI

XSW.XRA

via pin XDI

XSW.XRA

2) Additionally, automatic transmission of the A-bit is selectable.

XSW.XY0…4

via pin XDI

XSW.XY0…4

via pin XDI

3) As a special extension for double frame format, the Sa-bit register can be used optionally.

XSW.XSIS, XSP.XSIF

via pin XDI

XSW.XSIS, XSP.XSIF

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• The presence of the correct service word (bit 2 = 1) in frame n + 1,

• A correct FAS word in frame n + 2.

If the service word in frame n + 1 or the FAS word in frame n + 2 or both are not found

searching for the next FAS word starts in frame n + 2 just after the previous frame

alignment signal.

Reaching the synchronous state causes a frame alignment recovery interrupt status

ISR2.FAR if enabled. Undisturbed operation starts with the beginning of the next

doubleframe.

4.2.2.3 A-Bit Access

If the FALC®56 detects a remote alarm indication in the received data stream the

interrupt status bit ISR2.RA is set. With setting of bit XSW.XRA a remote alarm (RAI) is

sent to the far end.

By setting FMR2.AXRA the FALC®56 automatically transmit the remote alarm bit = 1 in

the outgoing data stream if the receiver detects a loss of frame alignment FRS0.LFA = 1.

If the receiver is in synchronous state FRS0.LFA = 0 the remote alarm bit is reset.

Note: The A-bit can be processed by the system interface. Setting bit TSWM.TRA

enables transparency for the A-bit in transmit direction (refer to Table 17).

4.2.2.4 Sa-Bit Access

As an extension for access to the Sa-bits through registers RSA(8:4)/XSA(8:4) an option

is implemented to allow the usage of internal Sa-bit registers RSA(8:4)/XSA(8:4) in

doubleframe format.

This function is enabled by setting FMR1.ENSA = 1 for the transmitter and

FMR1.RFS(1:0) = 01 for the receiver. In this case the FALC®56 internally works with a

16-frame structure but no CRC multiframe alignment/generation is performed.

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Hardware Description

4.2.3 CRC-Multiframe (E1)

The multiframe structure shown in Table 19 is enabled by setting bit: FMR2.RFS1/0 for

the receiver and FMR1.XFS for the transmitter.

Multiframe : 2 submultiframes = 2 × 8 frames

Frame alignment : refer to section Doubleframe Format

Multiframe alignment : bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern "001011"

CRC bits : bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14

CRC block size : 2048 bit (length of a submultiframe)

CRC procedure : CRC4, according to ITU-T G.704 and G.706

E: Spare bits for international use. Access to received information through bits

RSP.RS13 and RSP.RS15. Transmission is enabled by bits XSP.XS13 and

XSP.XS15. Additionally, automatic transmission for submultiframe error

indication is selectable.

Sa: Spare bits for national use. Additionally, Sa-bit access through registers

RSA4…8 and XSA4…8 is provided. HDLC-signaling in bits Sa4 to Sa8 is

selectable.

C1…C

4: Cyclic redundancy check bits.

A: Remote alarm indication. Additionally, automatic transmission of the A-bit is

selectable.

Table 19 CRC-Multiframe Structure (E1)

Sub-

Multiframe

Frame

Number

Bits 1 to 8 of the Frame

123456 78

Multiframe I 0

Sa4

Sa5

Sa61

Sa62

Sa63

Sa64

Sa7

Sa8

II 8

Sa4

Sa5

Sa61

Sa62

Sa63

Sa64

Sa7

Sa8

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Hardware Description

For transmit direction, contents of time slot 0 are additionally determined by the selected

transparent mode.

The CRC procedure is automatically invoked when the multiframe structure is enabled.

CRC errors in the received data stream are counted by the 16-bit CRC Error Counter

CEC (one error per submultiframe, maximum).

Additionally a CRC4 error interrupt status ISR0.CRC4 is generated if enabled by

IMR0.CRC4.

All CRC bits of one outgoing submultiframe are automatically inverted in case a CRC

error is flagged for the previous received submultiframe. This function is enabled by bit

RC0.CRCI. Setting of bit RC0.XCRCI inverts the CRC bits before transmission to the

distant end. The function of RC0.XCRCI and RC0.CRCI are logically ored.

4.2.3.1 Synchronization Procedure

Multiframe alignment is assumed to have been lost if doubleframe alignment has been

lost (flagged on status bit FRS0.LFA). The rising edge of this bit causes an interrupt.

The multiframe resynchronization procedure starts when Doubleframe alignment has

been regained which is indicated by an interrupt status bit ISR2.FAR. For Doubleframe

synchronization refer to section Doubleframe Format. It is also be invoked by the user

by setting

• Bit FMR0.FRS for complete doubleframe and multiframe resynchronization

• Bit FMR1.MFCS for multiframe resynchronization only.

The CRC checking mechanism is enabled after the first correct multiframe pattern has

been found. However, CRC errors are not counted in asynchronous state.

Table 20 Transmit Transparent Mode (CRC Multiframe E1)

enabled by Transmit Transparent Source for

Framing +

CRC

A-Bit Sa-Bits E-Bits

–

XSP.TT0

TSWM.TSIF

TSWM.TSIS

TSWM.TRA

TSWM.TSA(8:4)

(int. gen.)

via pin XDI1)

via pin XDI

(int. gen.)

1) pin XDI or XSIG or XFIFO buffer (signaling controller)

XSW.XRA2)

via pin XDI

XSW.XRA1)

via pin XDI

XSW.XRA1)

2) Automatic transmission of the A-bit is selectable

XSW.XY0 … 43)

via pin XDI

XSW.XY0 … 42)

via pin XDI

3) The Sa-bit register XSA(8:4) can be used optionally

XSP.XS13/XS154)

via pin XDI

(int. generated)

via pin XDI

XSP.XS13/XS153)

4) Additionally, automatic transmission of submultiframe error indication is selectable

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In doubleframe asynchronous state, counting of framing errors, CRC4 bit errors and

detection of remote alarm is stopped. AIS is automatically sent to the backplane interface

(can be disabled by bit FMR2.DAIS). Further on the updating of the registers RSW, RSP,

RSA(8:4), RSA6S and RS(16:1) is halted (remote alarm indication, Sa/Si-bit access).

The multiframe synchronous state is established after detecting two correct multiframe

alignment signals at an interval of n ×2 ms (n = 1, 2, 3 …). The loss of multiframe

alignment flag FRS0.LMFA is reset. Additionally an interrupt status multiframe alignment

recovery bit ISR2.MFAR is generated with the falling edge of bit FRS0.LMFA.

4.2.3.2 Automatic Force Resynchronization (E1)

In addition, a search for Doubleframe alignment is automatically initiated if two

multiframe pattern with a distance of n ×2 ms have not been found within a time interval

of 8 ms after doubleframe alignment has been regained (bit FMR1.AFR). A new search

for frame alignment is started just after the previous frame alignment signal.

4.2.3.3 Floating Multiframe Alignment Window (E1)

After reaching doubleframe synchronization a 8 ms timer is started. If a multiframe

alignment signal is found during the 8 ms time interval the internal timer is reset to

remaining 6 ms in order to find the next multiframe signal within this time. If the

multiframe signal is not found for a second time, the interrupt status bit ISR0.T8MS is

set. This interrupt usually occurs every 8 ms until multiframe synchronization is

achieved.

4.2.3.4 CRC4 Performance Monitoring (E1)

In the synchronous state checking of multiframe pattern is disabled. However, with bit

FMR2.ALMF an automatic multiframe resynchronization mode can be activated. If 915

out of 1000 errored CRC submultiframes are found then a false frame alignment is

assumed and a search for doubleframe and multiframe pattern is initiated. The new

search for frame alignment is started just after the previous basic frame alignment signal.

The internal CRC4 resynchronization counter is reset when the multiframe

synchronization has been regained.

4.2.3.5 Modified CRC4 Multiframe Alignment Algorithm (E1)

The modified CRC4 multiframe alignment algorithm allows an automatic interworking

between framers with and without a CRC4 capability. The interworking is realized as it

is described in ITU-T G.706 Appendix B.

If doubleframe synchronization is consistently present but CRC4 multiframe alignment is

not achieved within 400 ms it is assumed that the distant end is initialized to doubleframe

format. The CRC4/non-CRC4 interworking is enabled by FMR2.RFS1/0 = 11 and is

activated only if the receiver has lost its synchronization. If doubleframe alignment (basic

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frame alignment) is established, a 400-ms timer and searching for multiframe alignment

are started. A research for basic frame alignment is initiated if the CRC4 multiframe

synchronization cannot be achieved within 8 ms and is started just after the previous

frame alignment signal. The research of the basic frame alignment is done in parallel and

is independent of the synchronization procedure of the primary basic frame alignment

signal. During the parallel search all receiver functions are based on the primary frame

alignment signal, like framing errors, Sa-, Si-, A-bits, …). All subsequent multiframe

searches are associated with each basic framing sequence found during the parallel

search.

If the CRC4 multiframe alignment sequence was not found within the time interval of

400 ms, the receiver is switched into a non-CRC4 mode indicated by setting the bit

FRS0.NMF (No Multiframing Found) and ISR2.T400MS. In this mode checking of CRC

bits is disabled and the received E-bits are forced to low. The transmitter framing format

is not changed. Even if multiple basic FAS resynchronizations have been established

during the parallel search, the receiver is maintained to the initially determined primary

frame alignment signal location.

However, if the CRC4-multiframe alignment can be achieved within the 400 ms time

interval assuming a CRC4-to-CRC4 interworking, then the basic frame alignment

sequence associated to the CRC4 multiframe alignment signal is chosen. If necessary,

the primary frame alignment signal location is adjusted according to the multiframe

alignment signal. The CRC4 performance monitoring is started if enabled by

FMR2.ALMF and the received E-bits are processed in accordance to ITU-T G.704.

Switching into the doubleframe format (non-CRC4) mode after 400 ms can be disabled

by setting of FMR3.EXTIW. In this mode the FALC®56 continues to search for

multiframing. In the interworking mode setting of bit FMR1.AFR is not allowed.

4.2.3.6 A-Bit Access (E1)

If the FALC®56 detects a remote alarm indication (bit 2 in TS0 not containing the FAS

word) in the received data stream the interrupt status bit ISR2.RA is set. With the

deactivation of the remote alarm the interrupt status bit ISR2.RAR is generated.

By setting FMR2.AXRA the FALC®56 automatically transmits the remote alarm bit = 1 in

the outgoing data stream if the receiver detects a loss of frame alignment

(FRS0.LFA = 1). If the receiver is in synchronous state (FRS0.LFA = 0), the remote

alarm bit is reset in the outgoing data stream.

Additionally, if bit FMR3.EXTIW is set and the multiframe synchronous state cannot be

achieved within 400 ms after finding the primary basic framing, the A-bit is transmitted

active high to the remote end until the multiframing is found.

Note: The A-bit can be processed by the system interface. Setting bit TSWM.TRA

enables transparency for the A-bit in transmit direction (refer to Table 19).

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4.2.3.7 Sa-Bit Access (E1)

Due to signaling procedures using the five Sa-bits (Sa4…Sa8) of every other frame of the

CRC multiframe structure, three possibilities of access by the microprocessor are

implemented.

• The standard procedure allows reading/writing the Sa-bit registers RSW, XSW

without further support. The Sa-bit information is updated every other frame.

• The advanced procedure, enabled by bit FMR1.ENSA, allows reading/writing the

Sa-bit registers RSA4…8, XSA4…8.

A transmit or receive multiframe begin interrupt (ISR0.RMB or ISR1.XMB) is provided.

Registers RSA(8:4) contains the service word information of the previously received

CRC-multiframe or 8 doubleframes (bit slots 4 to 8 of every service word). These

registers are updated with every multiframe begin interrupt ISR0.RMB.

With the transmit multiframe begin an interrupt ISR1.XMB is generated and the contents

of the registers XSA(8:4) is copied into shadow registers. The contents is subsequently

sent out in the service words of the next outgoing CRC multiframe (or every

doubleframe) if none of the time slot 0 transparent modes is enabled. The transmit

multiframe begin interrupt XMB request that these registers issue should be serviced. If

requests for new information are ignored, the current contents is repeated.

• The extended access through the receive and transmit FIFOs of the signaling

controller. In this mode it is possible to transmit/receive a HDLC frame or a

transparent bit stream in any combination of the Sa-bits. Enabling is done by setting

of bit CCR1.EITS and the corresponding bits XC0.SA8E to SA4E/TSWM.TSA8 to

TSA4 and resetting of registers TTR(4:1), RTR(4:1) and FMR1.ENSA. The access to

and from the FIFOs is supported by ISR0.RME, RPF and ISR1.XPR, ALS.

Sa6-Bit Detection according to ETS 300233

Four consecutive received Sa6-bits are checked for the combinations defined by

ETS 300233. The FALC®56 detects the following fixed Sa6-bit combinations: SA61,

SA62, SA63, SA64 = 1000, 1010, 1100, 1110, 1111. All other possible 4-bit

combinations are grouped to status “X”.

A valid Sa6-bit combination must occur three times in a row. The corresponding status

bit in register RSA6S is set. Register RSA6S is of type “clear on read”. Any status change

of the Sa6-bit combinations causes an interrupt (ISR0.SA6SC).

During the basic frame asynchronous state update of register RSA6S and interrupt

status ISR0.SA6SC is disabled. In multiframe format the detection of the Sa6-bit

combinations can be done either synchronously or asynchronously to the submultiframe

(FMR3.SA6SY). In synchronous detection mode updating of register RSA6S is done in

the multiframe synchronous state (FRS0.LMFA = 0). In asynchronous detection mode

updating is independent of the multiframe synchronous state.

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Sa6-Bit Error Indication Counters

The Sa6-bit error indication counter CRC2L/H (16 bits) counts the received Sa6-bit

sequence 0001 or 0011 in every CRC submultiframe. In the primary rate access digital

section this counter option gives information about CRC errors reported from the TE by

the Sa6 bit. Incrementing is only possible in the multiframe synchronous state. The

Sa6-bit error indication counter CRC3L/H (16 bits) counts the received Sa6-bit sequence

0010 or 0011 in every CRC submultiframe. In the primary rate access digital section this

counter option gives information about CRC errors detected at T-reference point and

reporting them by the Sa6-bit. Incrementing is only possible in the multiframe

synchronous state.

4.2.3.8 E-Bit Access (E1)

Due to signaling requirements, the E-bits of frame 13 and frame 15 of the CRC

multiframe can be used to indicate received errored submultiframes:

Submultiframe I statusE-bit located in frame 13

Submultiframe II statusE-bit located in frame 15

no CRC error: E = 1; CRC error:E = 0

Standard Procedure

After reading the submultiframe error indication RSP.SI1 and RSP.SI2, the

microprocessor has to update the contents of register XSP (XS13, XS15). Access to

these registers has to be synchronized on transmit or receive multiframe begin interrupts

(ISR0.RMB or ISR1.XMB).

Automatic Mode

In the multiframe synchronous state the E-bits are processed according to ITU-T G.704

independently of bit XSP.EBP (E-bit polarity selection).

By setting bit XSP.AXS status information of received submultiframes is automatically

inserted in the E-bit position of the outgoing CRC multiframe without any further

interventions of the microprocessor.

In the doubleframe and multiframe asynchronous state the E-bits are set or cleared,

depending on the setting of bit XSP.EBP.

Submultiframe Error Indication Counter

The EBC (E-Bit) counter EBCL/H (16 bits) counts zeros in the E-bit position of frame 13

and 15 of every received CRC multiframe. This counter option gives information about

the outgoing transmit PCM line if the E-bits are used by the remote end for submultiframe

error indication. Incrementing is only possible in the multiframe synchronous state.

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Hardware Description

Note: E-bits can be processed by the system interface. Setting bit TSWM.TSIS enables

transparency for E-bits in transmit direction (refer to Table 19).

Figure 25 CRC4 Multiframe Alignment Recovery Algorithms (E1)

ITD10310

OUT of Primary BFA:

Inhibit Incoming CRC-4 Performance Monitoring

Reset all Timers

Set FRS0.LFA/LMFA/NMF = 110

No BFA Search ?

Primary

Yes

Reset Internal Frame Alignment Status

Start 400 ms Timer

IN Primary BFA:

Enable Primary BFA Loss Checking Process

(FRS0.LFA = 0)

Start 8 ms Timer

Can CRC-4

MFA be found

Yes

in 8 ms ?

400 ms

Timer

Elapsed ?

Yes

Parallel

BFA Search

Good ?

Assume CRC-4 to CRC-4 Interworking:

Confirm Primary BFA Associated with CRC-4 MFA

Reset Internal Multiframe Alignment Status

Adjust Primary BFA if Necessary

(FRS0.LMFA = 0)

Confirm Primary BFA

Set Internal 400 ms Timer Expiration Status Bit

Assume CRC-4 to non CRC-4 Interworking:

(FRS0.NMF = 1)

Start CRC-4 Performance Monitoring

Yes

or LFA ?

Error Count

CRC-4 No Continue CRC-4 Performance Monitoring

915

Yes

CRC-4 MFA Search

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4.3 Additional Receive Framer Functions (E1)

4.3.1 Error Performance Monitoring and Alarm Handling

Alarm Indication Signal: Detection and recovery is flagged by bit FRS0.AIS and

ISR2.AIS. Transmission is enabled by bit FMR1.XAIS.

Loss-Of-Signal: Detection and recovery is flagged by bit FRS0.LOS and ISR2.LOS.

Remote Alarm Indication: Detection and release is flagged by bit FRS0.RRA, RSW.RRA

and ISR2.RA/RAR. Transmission is enabled by bit XSW.XRA.

AIS in time slot 16: Detection and release is flagged by bit FRS1.TS16AIS and

ISR3.AIS16. Transmission is enabled by writing all ones in registers XS(16:1).

LOS in time slot 16: Detection and release is flagged by bit FRS1.TS16LOS.

Transmission is enabled by writing all zeros in registers XS(16:1).

Remote Alarm in time slot 16: Detection and release is flagged by bit FRS1.TS16RA and

ISR3.RA16. Transmission is enabled by bit XS1.2.

Transmit Line Shorted: Detection and release is flagged by bit FRS1.XLS and

ISR1.XLSC.

Transmit Ones-Density: Detection and release is flagged by bit FRS1.XLO and

ISR1.XLSC.

Table 21 Summary of Alarm Detection and Release (E1)

Alarm Detection Condition Clear Condition

Loss-Of-Signal

(LOS)

No transitions (logical

zeros) in a programmable

time interval of 16 to 4096

consecutive pulse periods.

Programmable receive

input signal threshold

Programmable number of ones (1

to 256) in a programmable time

interval of 16 to 4096 consecutive

pulse periods. A one is a signal

with a level above the

programmed threshold.

Alarm Indication

Signal (AIS)

FMR0.ALM = 0:

less than 3 zeros in

250 µs and loss of frame

alignment declared

FMR0.ALM = 1:

less than 3 zeros in

each of two consecutive

250-µs periods

FMR0.ALM = 0:

more than 2 zeros in

250 µs

FMR0.ALM = 1:

more than 2 zeros in each of two

500-µs periods

Remote Alarm

(RRA)

Bit 3 = 1 in time slot 0 not

containing the FAS word

Set conditions no longer

detected.

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4.3.2 Auto Modes

4.3.2.1 Automatic Remote Alarm Access

If the receiver has lost its synchronization a remote alarm can be sent automatically, if

enabled by bit FMR2.AXRA to the distant end. The remote alarm bit is set automatically

in the outgoing data stream, if the receiver is in asynchronous state (FRS0.LFA bit is set).

In synchronous state the remote alarm bit is removed.

4.3.2.2 Automatic E-bit Access

By setting bit XSP.AXS status information of received submultiframes is automatically

inserted at the E-bit position of the outgoing CRC Multiframe without any further

interventions of the microprocessor.

4.3.2.3 Automatic AIS to System Interface

In asynchronous state the synchronizer enforces an AIS to the receive system interface

automatically. However, received data can be switched through transparently, if bit

FMR2.DAIS is set.

Remote Alarm in

time slot 16 (TS16RA)

Y-bit = 1 received in CAS

multiframe alignment word

Y-bit = 0 received in CAS

multiframe alignment word

Loss-of-Signal in

time slot 16

(TS16LOS)

All zeros for at least 16

consecutively received time

slots 16

Receiving a one in

time slot 16

Alarm Indication

Signal in time slot 16

(TS16AIS)

Time slot 16 containing less

than 4 zeros in each of two

consecutive CAS

multiframes periods

Time slot 16 containing more than

3 zeros in one CAS multiframe

Transmit Line Short

(XLS)

More than 3 pulse periods

with highly increased

transmit line current on

XL1/2

Transmit line current limiter

inactive

Transmit

Ones-Density

(XLO)

32 consecutive zeros in the

transmit data stream on

XL1/2

Cleared with each transmitted

pulse

Table 21 Summary of Alarm Detection and Release (E1) (cont’d)

Alarm Detection Condition Clear Condition

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Hardware Description

4.3.2.4 Automatic Clock Source Switching

In slave mode (LIM0.MAS = 0) the DCO-R synchronizes to the recovered route clock. In

case of loss-of-signal (LOS) the DCO-R switches to Master mode automatically. If bit

CMR1.DCS is set, automatic switching from RCLK to SYNC is disabled.

4.3.2.5 Automatic Freeze Signaling

Updating of the received signaling information is controlled by the freeze signaling

status. The freeze signaling status is automatically activated if a loss-of-signal or a loss

of CAS multiframe alignment or a receive slip occurs. The internal signaling buffer

RS(16:1) is frozen. Optionally automatic freeze signaling is disabled by setting bit

SIC3.DAF.

4.3.3 Error Counters

The FALC®56 offers six error counters where each of them has a length of 16 bit. They

record code violations, framing bit errors, CRC4-bit errors and CRC4 error events which

are flagged in the different Sa6-bit combinations or the number of received multiframes

in asynchronous state or the Change Of Frame Alignment (COFA). Counting of the

multiframes in the asynchronous state and the COFA parameter is done in a 6/2 bit

counter and is shared with CEC3L/H. Each of the error counters is buffered. Buffer

updating is done in two modes:

• One-second accumulation

• On demand by handshake with writing to the DEC register

In the one-second mode an internal/external one-second timer updates these buffers

and resets the counter to accumulate the error events in the next one-second period.

The error counter cannot overflow. Error events occurring during an error counter reset

are not lost.

4.3.4 Errored Second

The FALC®56 supports the error performance monitoring by detecting the following

alarms or error events in the received data:

framing errors, CRC errors, code violations, loss of frame alignment, loss-of-signal,

alarm indication signal, E-bit error, receive and transmit slips.

With a programmable interrupt mask register ESM all these alarms or error events can

generate an errored second interrupt (ISR3.ES) if enabled.

4.3.5 One-Second Timer

Additionally, a one-second timer interrupt can be generated internally to indicate that the

enabled alarm status bits or the error counters have to be checked. The one-second

timer signal is output on port SEC/FSC (GPC1.CSFP1/0). Optionally synchronization to

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Hardware Description

an external second timer is possible which has to be provided on pin SEC/FSC.

Selecting the external second timer is done with GCR.SES. Refer also to register GPC1

for input/output selection.

4.3.6 In-Band Loop Generation and Detection

The FALC®56 generates and detects a framed or unframed in-band loop-up (activate)

and loop-down (deactivate) pattern with bit error rates up to 10-2. Framed or unframed

in-band loop code is selected by LCR1.FLLB. Replacing transmit data with the in-band

loop codes is done by programming FMR3.XLD/XLU.

The FALC®56 also offers the ability to generate and detect a flexible in-band loop-up and

loop-down pattern (LCR1.LLBP = 1). The loop-up and loop-down pattern is individually

programmable from 2 to 8 bits in length (LCR1.LAC1/0 and LCR1.LDC1/0).

Programming of loop codes is done in registers LCR2 and LCR3.

Status and interrupt status bits inform the user whether loop-up or loop-down code has

been detected.

4.3.7 Time Slot 0 Transparent Mode

The transparent modes are useful for loop-backs or for routing data unchanged through

the FALC®56.

In receive direction, transparency for ternary or dual-/single-rail unipolar data is always

achieved if the receiver is in the synchronous state. In asynchronous state data is

transparently switched through if bit FMR2.DAIS is set. However, correct time slot

assignment cannot be guaranteed due to missing frame alignment between line and

system side.

Setting of bit LOOP.RTM disconnects control of the internal elastic store from the

receiver. The elastic buffer is now in a “free running” mode without any possibility to

update the time slot assignment to a new frame position in case of resynchronization of

the receiver. Together with FMR2.DAIS this function can be used to realize undisturbed

transparent reception.

Transparency in transmit direction can be achieved by activating the time slot 0

transparent mode (bit XSP.TT0 or TSWM.(7:0)). If XSP.TT0 = 1 all internal information

of the FALC®56 (framing, CRC, Sa/Si-bit signaling, remote alarm) is ignored. With

transparently from port XDI to the far end. For complete transparency the internal

signaling controller, idle code generation and AIS alarm generation, single channel and

payload loop-back have to be disabled.

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Hardware Description

4.4 Transmit Path in E1 Mode

4.4.1 Transmitter (E1)

The serial bit stream is processed by the transmitter which has the following functions:

• Frame/multiframe synthesis of one of the two selectable framing formats

• Insertion of service and data link information

• AIS generation (Alarm indication signal)

• Remote alarm generation

• CRC generation and insertion of CRC bits

• CRC bits inversion in case of a previously received CRC error

• Idle code generation per DS0

The frame/multiframe boundaries of the transmitter can be externally synchronized by

using the SYPX/XMFS pin. Any change of the transmit time slot assignment

subsequently produces a change in the framing bit positions on the line side. This feature

is required if signaling and service bits are routed through the switching network and are

inserted in transmit direction by the system interface.

In loop-timed configuration (LIM2.ELT = 1) disconnecting the control of the transmit

system highway from the transmitter is done by setting XSW.XTM. The transmitter is

now in a free running mode without any possibility to update the multiframe position in

case of changing the transmit time slot assignment. The framing bits are generated

independently of the transmit system interface. For proper operation the transmit elastic

buffer size should be programmed to 2 frames.

The contents of selectable time slots can be overwritten by the pattern defined by

registers ICB1…ICB4.

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Hardware Description

4.4.2 Transmit Line Interface (E1)

The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar)

return to zero signals of the appropriate programmable shape. The unipolar data is

provided by the digital transmitter.

Figure 26 Transmitter Configuration (E1)

Similar to the receive line interface three different data types are supported:

• Ternary Signal

Single-rail data is converted into a ternary signal which is output on pins XL1 and

XL2. The HDB3 and AMI line code is employed. Selected by FMR0.XC1/0 and

LIM1.DRS = 0.

• Dual-rail data PCM(+), PCM(–) at multifunction ports XDOP/XDON with 50% or

100% duty cycle and with programmable polarity. Line coding is done in the same

way as in ternary interface mode. Selected by FMR0.XC1/0 and LIM1.DRS = 1.

• Unipolar data on port XOID is transmitted either in NRZ (Non Return to Zero) with

100% duty cycle or in CMI (Code Mark Inversion or known as 1T2B) Code with or

without (FMR3.CMI) preprocessed HDB3 coding to a fiber-optical interface. Clocking

off data is done with the rising edge of the transmit clock XCLK (2048 kHz) and with

a programmable polarity. Selection is done by FMR0.XC1 = 0 and LIM1.DRS = 1.

Table 22 Recommended Transmitter Configuration Values (E1)

Parameter Characteristic Impedance [Ω]

120 75

R1 (± 1%) [Ω]7.5

1) This value refers to an ideal transformer without any parasitics. Any transformer resistance or other parasitic

resistances have to be taken into account when calculating the final value of the output serial resistors.

7.51)

t2 : t1 1 : 2.4 1 : 2.4

F56V2_Transmitter_1

XL1

XL2

Line

t2t1

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Hardware Description

4.4.3 Transmit Jitter Attenuator (E1)

The transmit jitter attenuator DCO-X circuitry generates a "jitter-free" transmit clock and

meets the following requirements: ITU-T I.431, G. 703, G. 736 to 739, G.823 and ETSI

TBR12/13. The DCO-X circuitry works internally with the same high frequency clock as

the receive jitter attenuator. It synchronizes either to the working clock of the transmit

backplane interface or the clock provided on pin TCLK or the receive clock RCLK

(remote loop/loop-timed). The DCO-X attenuates the incoming clock jitter starting at

2 Hz with 20 dB per decade fall-off. With the jitter attenuated clock, which is directly

depending on the phase difference of the incoming clock and the jitter attenuated clock,

data is read from the transmit elastic buffer (2 frames) or from the JATT buffer (2 frames,

remote loop). Wander with a jitter frequency below 2 Hz is passed transparently.

The DCO-X accepts gapped clocks which are used in ATM or SDH/SONET applications.

The jitter attenuated clock is output on pin XCLK or optionally on pin CLK2.

In case of missing clock on pin SCLKX the DCO-X centers automatically, if selected by

bit CMR2.DCOXC = 1.

The transmit jitter attenuator can be disabled. In that case data is read from the transmit

elastic buffer with the clock sourced on pin TCLK (2.048 or 8.192 MHz). Synchronization

between SCLKX and TCLK has to be done externally.

In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a

transmit clock which is frequency synchronized on RCLK. In this configuration the

transmit elastic buffer has to be enabled.

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Hardware Description

Figure 27 Transmit Clock System (E1)

Note: DR = Dual-Rail interface

DCO-X Digital Controlled Oscillator transmit

4.4.4 Transmit Elastic Buffer (E1)

The received bit stream from pin XDI is optionally stored in the transmit elastic buffer.

The memory is organized as the receive elastic buffer. The functions are also equal to

the receive side. Programming of the transmit buffer size is done by SIC1.XBS1/0:

• XBS1/0 = 00: Bypass of the transmit elastic buffer

• XBS1/0 = 01: one frame buffer or 256 bits

Maximum of wander amplitude (peak-to-peak): 100 UI (1 UI = 488 ns)

average delay after performing a slip: 128 bits

• XBS1/0 = 10: two frame buffer or 512 bits

Maximum of wander amplitude: 190 UI

average delay after performing a slip: 1 frame or 256 bits

• XBS1/0 = 11: short buffer or 92 bits:

Maximum of wander amplitude: 18 µs

average delay after performing a slip: 46 bits

The functions of the transmit buffer are:

ITS10305

Pulse Shaper

Jitter

Framer

SCLKX

XL1/

XDOP/

XL2/

XDON

XCLK

XOID DR

DR Elastic

Store XDI

RCLK

TCLK

Transmit

Attenuator

DCO-X

SCLKR

Internal Clock of

Receive System

TCLK

÷ 4

Clocking

Unit

MCLK

(E1: 8MHz)

Interface

Transmit

(T1: 6MHz)

E1: 8MHz

T1: 6MHz

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Hardware Description

• Clock adaption between system clock (SCLKX) and internally generated transmit

route clock (XCLK).

• Compensation of input wander and jitter.

• Frame alignment between system frame and transmit route frame

• Reporting and controlling of slips

Writing of received data from XDI is controlled by SCLKX/R and SYPX/XMFS in

combination with the programmed offset values for the transmit time slot/clock slot

counters. Reading of stored data is controlled by the clock generated by DCO-X circuitry

or the externally generated TCLK and the transmit framer. With the de-jittered clock data

is read from the transmit elastic buffer and are forwarded to the transmitter. Reporting

and controlling of slips is done according to the receive direction. Positive/negative slips

are reported in interrupt status bits ISR4.XSP and ISR4.XSN. If the transmit buffer is

bypassed data is directly transferred to the transmitter.

The following table gives an overview of the transmit buffer operating modes.

4.4.5 Programmable Pulse Shaper (E1)

The analog transmitter includes a programmable pulse shaper to satisfy the

requirements of ITU-T I.431. The amplitude and shape of the transmit pulses are

completely programmable by registers XPM(2:0).

The transmitter requires an external step up transformer to drive the line.

Note: To achieve higher slew rates the pulse undershoot can be programmed in the 3rd

and 4th sub pulse fraction by setting LIM2.EOU and the corresponding bits in

registers XPM (2:0).

4.4.6 Transmit Line Monitor (E1)

The transmit line monitor compares the transmit line current on XL1 and XL2 with an

on-chip transmit line current limiter. The monitor detects faults on the primary side of the

transformer indicated by a highly increased transmit line current (more than 120 mA for

at least 3 consecutive pulses sourced by VDDX1)) and protects the device from damage

by setting the transmit line driver XL1/2 into high-impedance state automatically (if

enabled by XPM2.DAXLT = 0). The current limiter checks the actual current value of

Table 23 Transmit Buffer Operating Modes (E1)

SIC1.XBS(1:0) Buffer Size TS Offset

programming

Slip performance

00 bypass enabled no

11 short buffer enabled yes

01 1 frame enabled yes

10 2 frames enabled yes

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XL1/2 and if the transmit line current drops below the detection limit the high-impedance

state is cleared.

Two conditions are detected by the monitor: transmit line de-jitteredity (more than 31

consecutive zeros) indicated by FRS1.XLO and transmit line high current indicated by

FRS1.XLS. In both cases a transmit line monitor status change interrupt is provided.

Figure 28 Transmit Line Monitor Configuration (E1)

4.4.7 Transmit Signaling Controller (E1)

Similar to the receive signaling controller the same signaling methods and the same time

slot assignment is provided. The FALC®56 performs the following signaling and data link

methods.

4.4.7.1 HDLC or LAPD access

The transmit signaling controller of the FALC®56 performs the flag generation, CRC

generation, zero-bit stuffing and programmable idle code generation. Buffering of

transmit data is done in the 64 byte deep XFIFO. The signaling information is internally

multiplexed with the data applied to port XDI or XSIG.

In signaling controller transparent mode, fully transparent data transmission without

HDLC framing is performed. Optionally the FALC®56 supports the continuous

transmission of the XFIFO contents.

The FALC®56 offers the flexibility to insert data during certain time slots. Any

combinations of time slots can be programmed separately for the receive and transmit

direction if using HDLC channel 1. HDLC channel 2 and 3 support one programmable

time slot common for receive and transmit direction each.

1) shorts between XL1 or XL2 and VDDX are not detected

ITS10936

Pulse

Shaper

Monitor

Line

TRI

XDATA

XL1

XL2

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Hardware Description

Each HDLC controller can be used to operate on the line side (called "normal HDLC") or

on the system side (called "inverse HDLC").

4.4.7.2 Support of Signaling System #7

The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is

described in ITU-Q.703. The following description assumes, that the reader is familiar

with the SS7 protocol definition.

SS7 support must be activated by setting the MODE register. Data stored in the transmit

FIFO (XFIFO) is sent automatically. The SS7 protocol is supported by the following

hardware features in transmit direction:

• Transmission of flags at the beginning of each Signaling Unit

• Bit stuffing (zero insertion)

• Calculation of the CRC16 checksum:

The transmitter adds the checksum to each Signaling Unit.

Each Signaling Unit written to the transmit FIFO (XFIFO, 2×32 bytes) is sent once or

repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been

transmitted completely, the FALC®56 optionally starts sending of FISUs containing the

forward sequence number (FSN) and the backward sequence number (BSN) of the

previously transmitted Signaling Unit. Setting bit CCR5.AFX causes Fill In Signaling

Units (FISUs) to be sent continuously, if no HDLC or Signaling Unit (SU) is to be

transmitted from XFIFO. During update of XFIFO, automatic transmission is interrupted

and resumed after update is completed. The internally generated FISUs contain FSN

and BSN of the last transmitted Signaling Unit written to XFIFO.

Using CMDR.XREP = 1, the contents of XFIFO can be sent continuously. Clearing of

CMDR.XRES/SRES stops the automatic repetition of transmission. This function is also

available for HDLC frames, so no flag generation, CRC byte generation and bit stuffing

is necessary.

Example: After an MSU has been sent repetitively and XREP has been cleared, FISUs

are sent automatically.

4.4.7.3 Sa-Bit Access (E1)

The FALC®56 supports the Sa-bit signaling of time slot 0 of every other frame as follows:

• The access through register XSW

• The access through registers XSA(8:4), capable of storing the information for a

complete multiframe

• The access through the 64 byte deep XFIFO of the signaling controller (HDLC

channel 1 only)

This Sa-bit access gives the opportunity to transparent a bit stream as well as HDLC

frames where the signaling controller automatically processes the HDLC protocol. Any

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combination of Sa-bits which shall be inserted in the outgoing data stream can be

selected by XC0.SA(8:4).

4.4.7.4 Channel Associated Signaling CAS (E1, serial mode)

In external signaling mode (serial mode) the signaling data received on port XSIG is

sampled with the working clock of the transmit system interface (SCLKX) in combination

with the transmit synchronization pulse (SYPX). Data on XSIG is latched in the bit

positions 5 to 8 per time slot, bits 1 to 4 are ignored. Time slots 0 and 16 are sampled

completely (bit 1 to 8). The received CAS multiframe is inserted frame aligned into the

data stream on XDI and must be valid during the last frame of a multiframe if

CRC4/multiframe mode is selected. The CAS multiframe is aligned to the

CRC4-multiframe; other frames are ignored. Data sourced by the internal signaling

controller (µP access mode) overwrites the external signaling data.

If the FALC®56 is configured for no signaling, the system interface data stream passes

the FALC®56 undisturbedly.

Note: CAS data on XSIG is read in the last frame of a multiframe only and ignored in all

other frames.

Figure 29 2.048 MHz Transmit Signaling Highway (E1)

4.4.7.5 Channel Associated Signaling CAS (E1, µP access mode)

Transmit data stored in registers XS(16:1) is transmitted on a multiframe boundary in

time slot 16. The signaling controller inserts the bit stream either on the transmit line side

or, if external signaling is enabled, on the transmit system side using pin function XSIG.

Data sourced by the internal signaling controller overwrites the external signaling data.

F0132

A B C D A B C D

4 5 6 7 0 1 2 3 4 5 6 7

TS31 TS0 TS1

0 0 0 0 X Y X X

0 1 2 3 4 5 6 7

TS16

A B C D

0 1 2 3 4 5 6 7

TS31

XSIG

XDI

SCLKX

FAS/NFAS

SYPX

125 µs

T = Time slot offset (XC0, XC1)

FAS = Frame alignment signal, is taken from XSIG, not from XDI

NFAS = TS0 not containing FAS

ABCD = Signaling bits for time slots 1...15 and 17...31 of CAS multiframe

0000XYXX = CAS multiframe alignment signal, has to be provided in TS16

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Hardware Description

If the FALC®56 is configured for no signaling, the system interface data stream passes

the FALC®56 undisturbedly.

4.5 System Interface in E1 Mode

The FALC®56 offers a flexible feature for system designers where for transmit and

receive direction different system clocks and system pulses are necessary. The interface

to the receive system highway is realized by two data buses, one for the data RDO and

one for the signaling data RSIG. The receive highway is clocked on pin SCLKR, while

the interface to the transmit system highway is independently clocked on pin SCLKX.

The frequency of these working clocks and the data rate of

2.048/4.096/8.192/16.384 Mbit/s for the receive and transmit system interface is

programmable by SIC1.SSC1/0, and SIC1.SSD1, FMR1.SSD0. Selectable system clock

and data rates and their valid combinations are shown in the table below

×= valid, - = invalid

Generally the data or marker on the system interface are clocked off or latched on the

rising or falling edge (SIC3.RESR/X) of the SCLKR/X clock. Some clocking rates allow

transmission of time slots in different channel phases. Each channel phase which shall

be active on ports RDO, XDI, RP(A:D) and XP(A:D) is programmable by SIC2.SICS(2:0),

the remaining channel phases are cleared or ignored.

The signals on pin SYPR together with the assigned time slot offset in register RC0 and

RC1 define the beginning of a frame on the receive system highway.The signal on pin

SYPX or XMFS together with the assigned time slot offset in register XC0 and XC1

define the beginning of a frame on the transmit system highway.

Adjusting the frame begin (time slot 0, bit 0) relative to SYPR/X or XMFS is possible in

the range of 0 to 125 µs. The minimum shift of varying the time slot 0 begin can be

programmed between 1 bit and 1/8 bit depending of the system clocking and data rate,

e.g. with a clocking/data rate of 2.048 MHz shifting is done bit by bit, while running the

FALC®56 with 16.384 MHz and 2.048 Mbit/s data rate it is done by 1/8 bit.

A receive frame marker RFM can be activated during any bit position of the entire frame.

Programming is done with registers RC1/0. The pin function RFM is selected by

Table 24 System Clocking and Data Rates (E1)

System Data Rate Clock Rate

2.048 MHz

Clock Rate

4.096 MHz

Clock Rate

8.192 MHz

Clock Rate

16.384 MHz

2.048 Mbit/s ××××

4.096 Mbit/s - ×××

8.192 Mbit/s - - ××

16.384 Mbit/s - - - ×

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 106 DS1.1, 2003-10-23

Hardware Description

PC(4:1).RPC(2:0) = 001. The RFM selection disables the internal time slot assigner, no

offset programming is performed. The receive frame marker is active high for one

2.048 MHz cycle or one system clock cycle (see GPC1.SRFM) and is clocked off with

the rising or falling edge of the clock which is in/output on port SCLKR (see

SIC3.RESR/X).

Compared to the receive path the inverse functions are performed for the transmit

direction.

The interface to the transmit system highway is realized by two data buses, one for the

data XDI and one for the signaling data XSIG. The time slot assignment is equivalent to

the receive direction.

Latching of data is controlled by the system clock (SCLKX) and the synchronization

pulse (SYPX/XMFS) in combination with the programmed offset values for the transmit

time slot/clock slot counters XC1/0. The frequency of the working clock of

2.048/4.096/8.192/16.384 MHz for the transmit system interface is programmable by

SIC1.SSC1/0. Refer also toTable 24.

The received bit stream on ports XDI and XSIG can be multiplexed internally on a time

slot basis, if enabled by SIC3.TTRF = 1. The data received on port XSIG can be sampled

if the transmit signaling marker XSIGM is active high. Data on port XDI is sampled if

XSIGM is low for the corresponding time slot. Programming the XSIGM marker is done

with registers TTR(4:1).

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 107 DS1.1, 2003-10-23

Hardware Description

Figure 30 System Interface (E1)

F56V2_System_Interface

Receive

Signaling

Buffer

Receive

Elastic

Buffer

Receive

Backplane

Receive

Jitter

Attenuator

Transmit

Signaling

Buffer

Transmit

Elastic

Buffer

Transmit

Backplane

Transmit

Jitter

Attenuator

RSIGM

RSIG

RMFB

RFM

DLR

FREEZE

RFSP

SCLKR

DCO-R

RP(A...D)

DCO-R

SYPR

RDO

SCLKX

XP(A...D)

XDI

RCLK

TCLK

DCO-R

Receive

Data

Receive

Clock

Transmit

Data

Transmit

Clock

PLBBYP

BYP

XSIG

SYPX

XMFS

TCLK

XSIGM

XMFB

DLX

XCLK

XLT

LOS

GPI

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 108 DS1.1, 2003-10-23

Hardware Description

4.5.1 Receive System Interface (E1)

Figure 31 Receive System Interface Clocking (E1)

ITD10951

FRAME 1 FRAME 2 FRAME 3 FRAME 15 FRAME 16 FRAME 1 FRAME 2 FRAME 15

Bit 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Bit 2Bit 1Bit 0

Bit 255

Multi Frame 1 Multi Frame 2

4 Mbit Interface 2 Mbit Interface

Programmable via RC0/1

RDO

RMFB

SYPR

SCLKR

8.192 MHz

2.048 MHz

SCLKR

2 Mbit/s Data Rate

RDO/RSIG

TS0

RDO/RSIG

(SCLKR = 8.192 MHz)

4 Mbit/s Data Rate

DLR

Sa-Bit Marker

XC0 . SA8E-SA4E

Receive Frame Marker

RFM

RC0/1

RSIGM

Time-Slot Marker

RTR1...4

4 Mbit/s Data Rate

(SCLKR = 8.192 MHz)

RDO/RSIG

Trigger

Edge Edge

Sample

marks any

Sa Bit

bit position

marks any

Time-Slot

4 Mbit Interface

2 Mbit Interface

Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

only falling trigger edge shown, depending on Bit SIC3.RESR

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 109 DS1.1, 2003-10-23

Hardware Description

4.5.1.1 Receive Offset Programming

Depending on the selection of the synchronization signals (SYPR or RFM), different

calculation formulas are used to define the position of the synchronization pulses. These

formulas are given below, see Figure 32 to Figure 35 for explanation. The pulse length

of SYPR and RFM is always the basic E1 bit width (488 ns), independent of the selected

system highway clock and data frequency.

SYPR Offset Calculation

T: Time between beginning of SYPR pulse and beginning of next frame

(time slot 0, bit 0), measured in number of SCLKR clock intervals

maximum delay: Tmax =(256×SC/SD)-1

SD: Basic data rate; 2.048 Mbit/s

SC: System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz

X: Programming value to be written to registers RC0 and RC1 (see Page 249).

0≤T≤4: X = 4 - T

5≤T≤Tmax: X = 2052 - T

RFM Offset Calculation

MP: Marker position of RFM, counting in SCLKR clock cycles

(0 = bit 1, time slot 0, channel phase 0)

SC = 2.048 MHz: 0 ≤MP ≤255

SC = 4.096 MHz: 0 ≤MP ≤511

SC = 8.192 MHz: 0 ≤MP ≤1023

SC = 16.384 MHz: 0 ≤MP ≤2047

SD: Basic data rate; 2.048 Mbit/s

SC: System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz

X: Programming value to be written to registers RC0 and RC1 (see Page 249).

0≤ MP ≤2045: X = MP + 2

2046 ≤MP ≤2047: X = MP - 2046

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 110 DS1.1, 2003-10-23

Hardware Description

Figure 32 SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz)

Figure 33 SYPR Offset Programming (8.192 Mbit/s, 8.192 MHz)

F0221A

12345678 12345678

RDO

12345678 12345678 12345678

TS0 TS1 TS31 TS0 TS1

SYPR

SCLKR

SIC3.RESR = 0

(falling edge)

SCLKR

SIC3.RESR = 1

(rising edge)

T = 0

SYPR

256 - T

F0221B

SYPR

SCLKR

SIC3.RESR = 0

(falling edge)

SCLKR

SIC3.RESR = 1

(rising edge)

T = 0

SYPR

SC/SD x 256 - T

RDO

(CP0)

(TS = time slot, CP = channel phase)

1234

TS31-CP3

5 6 7 8

TS0 - CP0 TS0 - CP1

12345678

TS0 - CP0 TS0 - CP1

RDO

(CP1) 12345678 12345678

RDO

(CP3) 12345678

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 111 DS1.1, 2003-10-23

Hardware Description

Figure 34 RFM Offset Programming (2.048 Mbit/s, 2.048 MHz)

Figure 35 RFM Offset Programming (8.192 Mbit/s, 8.192 MHz)

F0221C

12345678 12345678

RDO

12345678 12345678 12345678

TS0 TS1 TS31 TS0 TS1

RFM

SCLKR

SIC3.RESR = 0

(falling edge)

SCLKR

SIC3.RESR = 1

(rising edge)

BP = 0

RFM

BP = 12

BP = 251

F0221D

RDO

(CP0)

SCLKR

SIC3.RESR = 0

(falling edge)

SCLKR

SIC3.RESR = 1

(rising edge)

byte-interleaved (TS = time slot, CP = channel phase)

1234

TS31-CP3

RFM

BP = 0

RFM

BP = 12

BP = 1020

5 6 7 8

TS0 - CP0 TS0 - CP1

12345678

TS0 - CP0 TS0 - CP1

RDO

(CP1) 12345678 12345678

RDO

(CP3) 12345678

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 112 DS1.1, 2003-10-23

Hardware Description

4.5.2 Transmit System Interface (E1)

Figure 36 Transmit System Interface Clocking: 2.048 MHz (E1)

FRAME0 FRAME1 FRAME2 FRAME15 FRAME0 FRAME1 FRAME2

Multi Frame 1 Multi Frame 2

XDI

XMFB

XMFS

SYPX

Trigger Edge

Bit 0 Sample Edge

SCLKX

XDI/XSIG Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8

DLX

Sa-Bit Marker

XC0.SA8E-SA4E

Bit 4

marked

only falling edge mode shown

delay T is programmable by XC0/1;

SYPX

XSIGM

TS0

F0003

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 113 DS1.1, 2003-10-23

Hardware Description

Figure 37 Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1)

FRAME0 FRAME1 FRAME2 FRAME15 FRAME0 FRAME1 FRAME2

Multi Frame 1 Multi Frame 2

XDI

XMFB

XMFS

SYPX

Trigger Edge

Bit 0 Sample Edge

SCLKX

XDI/XSIG

SIC2.SICS2-0=000

DLX

Sa-Bit Marker

XC0.SA8E-SA4E

SIC2.SICS2-0=000

Bit 4

marked

only falling edge mode shown

delay T is programmable by XC0/1;

data 4.096 Mbit/s, clock 8.192 MHz

SYPX

1 2 3 4 5 6 7 8

Bit 4

marked

DLX

Sa-Bit Marker

XC0.SA8E-SA4E

SIC2.SICS2-0=000

XDI/XSIG

SIC2.SICS2-0=001

XSIGM

Time-Slot Marker

TTR1...4

SIC2.SICS2-0=000

F0004

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 114 DS1.1, 2003-10-23

Hardware Description

4.5.2.1 Transmit Offset Programming

The pulse length of SYPX is always the basic E1 bit width (488 ns), independent of the

selected system highway clock and data frequency.

SYPX Offset Calculation

T: Time between beginning of SYPX pulse and beginning of next frame

(time slot 0, bit 0), measured in number of SCLKX clock intervals

maximum delay: Tmax =(256×SC/SD)-1

SD: Basic data rate; 2.048 Mbit/s

SC: System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz

X: Programming value to be written to registers XC0 and XC1 (see Page 247).

0≤T≤4: X = 4 - T

5≤T≤Tmax: X = 256 ×SC/SD - T + 4

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 115 DS1.1, 2003-10-23

Hardware Description

Figure 38 SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz)

Figure 39 SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz)

F0223A

12345678 12345678

XDI

12345678 12345678 12345678

TS0 TS1 TS31 TS0 TS1

SYPX

SCLKX

SIC3.RESX = 1

(rising edge)

SCLKX

SIC3.RESX = 0

(falling edge)

T = 0

SYPX

256 - T

F0223B

SYPX

SCLKX

SIC3.RESX = 1

(rising edge)

SCLKX

SIC3.RESX = 0

(falling edge)

T = 0

SYPX

SC/SD x 256 - T

XDI

(CP0)

(TS = time slot, CP = channel phase)

1 2 3 4

TS31-CP3

5 6 7 8

TS0 - CP0 TS0 - CP1

12345678

TS0 - CP0 TS0 - CP1

XDI

(CP1) 12345678 12345678

XDI

(CP3) 12345678

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 116 DS1.1, 2003-10-23

Hardware Description

4.5.3 Time Slot Assigner (E1)

HDLC channel 1 offers the flexibility to connect data during certain time slots, as defined

by registers RTR(4:1) and TTR(4:1), to the RFIFO and XFIFO, respectively. Any

combinations of time slots can be programmed for the receive and transmit directions. If

CCR1.EITS = 1 the selected time slots (RTR(4:1)) are stored in the RFIFO of the

signaling controller and the XFIFO contents is inserted into the transmit path as

controlled by registers TTR(4:1).

For HDLC channels 2 and 3, one out of 31 time slots can be selected for each channel,

but in common for transmit and receive direction.

Within selected time slots single bit positions can be masked to be used/not used for

HDLC transmission for all HDLC channels. Additionally, the use of even, odd or both

frames can be selected for each HDLC channel individually.

Table 25 Time Slot Assigner HDLC Channel 1 (E1)

Receive

Time Slot

Transmit

Time Slot

Time Slot Receive

Time Slot

Transmit

Time Slot

RTR 1.7 TTR 1.7 0 RTR 3.7 TTR 3.7 16

RTR 1.6 TTR 1.6 1 RTR 3.6 TTR 3.6 17

RTR 1.5 TTR 1.5 2 RTR 3.5 TTR 3.5 18

RTR 1.4 TTR 1.4 3 RTR 3.4 TTR 3.4 19

RTR 1.3 TTR 1.3 4 RTR 3.3 TTR 3.3 20

RTR 1.2 TTR 1.2 5 RTR 3.2 TTR 3.2 21

RTR 1.1 TTR 1.1 6 RTR 3.1 TTR 3.1 22

RTR 1.0 TTR 1.0 7 RTR 3.0 TTR 3.0 23

RTR 2.7 TTR 2.7 8 RTR 4.7 TTR 4.7 24

RTR 2.6 TTR 2.6 9 RTR 4.6 TTR 4.6 25

RTR 2.5 TTR 2.5 10 RTR 4.5 TTR 4.5 26

RTR 2.4 TTR 2.4 11 RTR 4.4 TTR 4.4 27

RTR 2.3 TTR 2.3 12 RTR 4.3 TTR 4.3 28

RTR 2.2 TTR 2.2 13 RTR 4.2 TTR 4.2 29

RTR 2.1 TTR 2.1 14 RTR 4.1 TTR 4.1 30

RTR 2.0 TTR 2.0 15 RTR 4.0 TTR 4.0 31

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 117 DS1.1, 2003-10-23

Hardware Description

4.6 Test Functions (E1)

4.6.1 Pseudo-Random Binary Sequence Generation and Monitor

The FALC®56 has the ability to generate and monitor 215-1 and 220-1 pseudo-random

binary sequences (PRBS). The generated PRBS pattern is transmitted to the remote end

on pins XL1/2 or XDOP/N and can be inverted optionally. Generating and monitoring of

PRBS pattern is done according to ITU-T O.151.

The PRBS monitor senses the PRBS pattern in the incoming data stream.

Synchronization is done on the inverted and non-inverted PRBS pattern. The current

synchronization status is reported in status and interrupt status registers. Enabled by bit

LCR1.EPRM each PRBS bit error increments an error counter (CEC2). Synchronization

is reached within 400 ms with a probability of 99.9% at a bit error rate of up to 10-1.

The PRBS generator and monitor can be used to handle either a framed

(TPC0.FRA = 1) or an unframed (TPC0.FRA = 0) data stream.

4.6.2 Remote Loop

In the remote loop-back mode the clock and data recovered from the line inputs RL1/2

or RDIP/RDIN are routed back to the line outputs XL1/2 or XDOP/XDON through the

analog or digital transmitter. As in normal mode they are also processed by the

synchronizer and then sent to the system interface. The remote loop-back mode is

selected by setting the corresponding control bits LIM1.RL and LIM1.JATT. Received

data can be looped with or without the transmit jitter attenuator (FIFO).

Figure 40 Remote Loop (E1)

ITS09750

RDO

XDI

RCLK

RL1

RL2

XL1

XL2

FIFO

XCLK RCLK

DCO-R/X

Framer

Rec.

Framer

Trans. Store

Elast.

Store

Recovery

Data

Clock +

MUX

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 118 DS1.1, 2003-10-23

Hardware Description

4.6.3 Payload Loop-Back

To perform an effective circuit test a payload loop is implemented. The payload

loop-back (FMR2.PLB) loops the data stream from the receiver section back to

transmitter section. The looped data passes the complete receiver including the wander

and jitter compensation in the receive elastic store and is output on pin RDO. Instead of

the data an AIS signal (FMR2.SAIS) can be sent to the system interface.

The framing bits, CRC4 and spare bits are not looped, if XSP.TT0 = 0. They are

generated by the FALC®56 transmitter. If the PLB is enabled the transmitter and the data

on pins XL1/2 or XDOP/XDON are clocked with SCLKR instead of SCLKX. If

XSP.TT0 = 1 the received time slot 0 is sent back transparently to the line interface. Data

on the following pins is ignored: XDI, XSIG, SCLKX, SYPX and XMFS. All the received

data is processed normally.

Figure 41 Payload Loop (E1)

ITS09748

Clock +

Data Rec.

Framer Elast.

Store

Trans.

Framer

RDO

XDI

RCLK

RL1

RL2

XL1

XL2

Recovery

SCLKX

SCLKR

MUX

AIS-GEN

Elast.

Store

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 119 DS1.1, 2003-10-23

Hardware Description

4.6.4 Local Loop

The local loop-back mode selected by LIM0.LL = 1 disconnects the receive lines RL1/2

or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data

provided by the system interface is routed through the analog receiver back to the

system interface. However, the bit stream is transmitted undisturbedly on the line.

However, an AIS to the distant end can be enabled by setting FMR1.XAIS = 1 without

influencing the data looped back to the system interface.

Note that enabling the local loop usually invokes an out-of-frame error until the receiver

resynchronizes to the new framing. The serial codes for transmitter and receiver have to

be identical.

Figure 42 Local Loop (E1)

ITS09749

RDO

XDI

RCLK

AIS-GEN

RL1

RL2

XL1

XL2

Framer

Rec.

Framer

Trans.

Store

Elast.

Recovery

Data

Clock +

MUX Elast.

Store

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 120 DS1.1, 2003-10-23

Hardware Description

4.6.5 Single Channel Loop-Back

Each of the 32 time slots can be selected for loop-back from the system PCM input (XDI)

to the system PCM output (RDO). This loop-back is programmed for one time slot at a

time selected by register LOOP. During loop-back, an idle channel code programmed in

For the time slot test, sending sequences of test patterns like a 1-kHz check signal shall

be avoided. Otherwise an increased occurrence of slips in the tested time slot disturbs

testing. These slips do not influence the other time slots and the function of the receive

memory. The usage of a quasi-static test pattern is recommended.

Figure 43 Single Channel Loop-Back (E1)

ITS09747

RDO

XDI

RCLK

RL1

RL2

XL1

XL2

IDLE Code

Framer

Trans.

Framer

Rec. Store

Elast.

Store

Elast.

MUX

Recovery

Data

Clock +

FALC®56

PEF 2256 H/E

Functional Description E1

User’s Manual 121 DS1.1, 2003-10-23

Hardware Description

4.6.6 Alarm Simulation (E1)

Alarm simulation does not affect the normal operation of the device, i.e. all time slots

remain available for transmission. However, possible real alarm conditions are not

reported to the processor or to the remote end when the device is in the alarm simulation

mode.

The alarm simulation is initiated by setting the bit FMR0.SIM. The following alarms are

simulated:

• Loss-Of-Signal (LOS)

• Alarm Indication Signal (AIS)

• Loss of pulse frame

• Remote alarm indication

• Receive and transmit slip indication

• Framing error counter

• Code violation counter (HDB3 Code)

• CRC4 error counter

• E-Bit error counter

• CEC2 counter

• CEC3 counter

Some of the above indications are only simulated if the FALC®56 is configured to a mode

where the alarm is applicable (e.g. no CRC4 error simulation when doubleframe format

is enabled).

Setting of the bit FMR0.SIM initiates alarm simulation, interrupt status bits are set. Error

counting and indication occurs while this bit is set. After it is reset all simulated error

conditions disappear, but the generated interrupt statuses are still pending until the

corresponding interrupt status register is read. Alarms like AIS and LOS are cleared

automatically. Interrupt status registers and error counters are automatically cleared on

read.

4.6.7 Single Bit Defect Insertion

Single bit defects can be inserted into the transmit data stream for the following

functions:

FAS defect, multiframe defect, CRC defect, CAS defect, PRBS defect and bipolar

violation.

Defect insertion is controlled by register IERR.

FALC®56

PEF 2256 H/E

Functional Description T1/J1

User’s Manual 122 DS1.1, 2003-10-23

Hardware Description

5 Functional Description T1/J1

5.1 Receive Path in T1/J1 Mode

Figure 44 Receive Clock System (T1/J1)

5.1.1 Receive Line Interface (T1/J1)

For data input, three different data types are supported:

• Ternary coded signals received at multifunction ports RL1 and RL2 from a -36 dB

ternary interface. The ternary interface is selected if LIM1.DRS is reset.

• Digital dual-rail signals received on ports RDIP and RDIN. The dual-rail interface is

selected if LIM1.DRS and FMR0.RC1 is set.

• Unipolar data on port ROID received from a fiber-optical interface. The optical

interface is selected if LIM1.DRS is set and FMR0.RC1 is reset.

5.1.2 Receive Short and Long-Haul Interface (T1/J1)

The FALC®56 has an integrated short-haul and long-haul line interface, including a

receive equalization network, noise filtering and programmable line build-outs (LBO).

Equalizer

Clock &

Data

Recovery

DPLL

Line

Decoder

Alarm

Detector

Analog

LOS

Detector

RDATA

RCLK

SYNC

RL1/RDIP/ROID

RL2/RDIN/RCLKI

DCO-R

Receive Jitter

Attenuator

MCLK

FSC

Receive

System

Interface

F0117

FALC®56

PEF 2256 H/E

Functional Description T1/J1

User’s Manual 123 DS1.1, 2003-10-23

Hardware Description

5.1.3 Receive Equalization Network (T1/J1)

The FALC®56 automatically recovers the signals received on pins RL1/2. The maximum

reachable length with a 22 AWG twisted-pair cable is 2000 m (~6560 ft.). The integrated

receive equalization network recovers signals with up to -36 dB of cable attenuation in

long-haul mode. Noise filters eliminate the higher frequency part of the received signals.

The incoming data is peak-detected and sliced to produce the digital data stream. The

slicing level is software selectable in four steps (45%, 50%, 55%, 67%). The received

data is then forwarded to the clock and data recovery unit. The receive equalizer

characteristics are programmable to enable the use of non-standard cable types or to

adapt to special receive conditions.

5.1.4 Receive Line Attenuation Indication (T1/J1)

Status register RES reports the current receive line attenuation in a range from 0 to

-36 dB in 25 steps of approximately 1.4 dB each. The least significant 5 bits of this

with the most significant two bits (RES.EV1/0 = 01).

5.1.5 Receive Clock and Data Recovery (T1/J1)

The analog received signal on port RL1/2 is equalized and then peak-detected to

produce a digital signal. The digital received signal on port RDIP/N is directly forwarded

to the DPLL. The receive clock and data recovery extracts the route clock RCLK from

the data stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data

stream into a single-rail, unipolar bit stream. The clock and data recovery uses an

internally generated high frequency clock based on MCLK.

The recovered route clock or a de-jittered clock can be output on pin RCLK as shown in

Table 26.

See also Table 29 on page 130 for details of master/slave clocking.

FALC®56

PEF 2256 H/E

Functional Description T1/J1

User’s Manual 124 DS1.1, 2003-10-23

Hardware Description

The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 UI.

In digital bipolar line interface mode the clock and data recovery requires HDB3 coded

signals with 50% duty cycle.

5.1.6 Receive Line Coding (T1/J1)

The B8ZS line code or the AMI (ZCS, zero code suppression) coding is provided for the

data received from the ternary or the dual rail interface. All code violations that do not

correspond to zero substitution rules are detected. If a bit error causes a code violation

that leads to a valid substitution pattern, this code violation is not detected and the

substitution pattern is replaced by the corresponding zero pattern. The detected errors

increment the 16-bit code violation counter. In case of the optical interface a selection

between the NRZ code and the CMI Code (1T2B) with B8ZS or AMI postprocessing is

provided. If CMI code is selected the receive route clock is recovered from the data

stream. The CMI decoder does not correct any errors. In case of NRZ coding data is

latched with the falling edge RCLKI.

When using the optical interface with NRZ coding, the decoder is bypassed and no code

violations are detected.

Additionally, the receive line interface contains the alarm detection for Alarm Indication

Signal AIS (Blue Alarm) and the loss-of-signal LOS (Red Alarm).

Table 26 RCLK Output Selection (T1/J1)

Clock Source RCLK Frequency CMR1.

DCS

CMR1.

RS1/0

SIC2.

SSC2

Receive Data

(1.544 Mbit/s on RL1/RL2,

RDIP/RDIN or ROID)

1.544 MHz ×00 ×

Receive Data

in case of LOS

constant high ×01 ×

1.544 MHz

(generated by DCO-R,

synchronized on SYNC)

1101

DCO-R 1.544 MHz ×10 1

2.048 MHz ×10 0

6.176 MHz ×11 1

8.192 MHz ×11 0

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Functional Description T1/J1

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Hardware Description

5.1.7 Receive Line Termination (T1/J1)

The signal at the ternary interface is received at both ends of a transformer. A termination

resistor is used to achieve line impedance matching (see Figure 45 and Table 27).

Figure 45 Receiver Configuration (T1/J1)

Table 27 Recommended Receiver Configuration Values (T1/J1)

Line Impedance External Resistor R2Transformer Ratio t2:t

120 Ω120 Ω1)

1) This includes all parasitic effects caused by circuit board design.

1 : 1

110 Ω110 Ω1) 1 : 1

F56V2_Receiver_

RL1

RL2

Line

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Hardware Description

5.1.8 Receive Line Monitoring Mode

For short-haul applications like shown in Figure 46, the receive equalizer can be

switched into receive line monitoring mode (LIM0.RLM = 1). One device is used as a

short-haul receiver while the other is used as a short-haul monitor. In this mode the

receiver sensitivity is increased to detect an incoming signal of -20 dB resistive

attenuation. The required resistor values are given in Table 28.

Figure 46 Receive Line Monitoring

Using the receive line monitor mode and the hardware tristate function of transmit lines

XL1/2, the FALC®56 now supports applications connecting two devices to one receive

and transmission line. In these kind of applications both devices are working in parallel

Table 28 External Component Recommendations (Monitoring)

Parameter1)

1) This includes all parasitic effects caused by circuit board design.

Characteristic Impedance [Ω]

T1 J1

R1 (± 1 %) [Ω] 100 110

R2 (± 1 %) [Ω] 100 110

R3 (± 1 %) [Ω] 430 470

t2 : t11 : 1 1 : 1

F56V2_Receiver_

Receiver

Monitor

RL1

E1/T1/J1

Receive

Line

LIM0.RLM=0

LIM0.RLM=1

R3R3

RL2

RL1

RL2

t2 : t1

resistive -20 dB network

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Functional Description T1/J1

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Hardware Description

for redundancy purpose (see Figure 47). While one of them is driving the line, the other

one must be switched into transmit line tristate mode. If both channels are configured

identically and supplied with the same system data and clocks, the transmit path can be

switched from one channel to the other without causing a synchronization loss at the

remote end. Due to the use of the receive line monitor mode, this setup is limited to short

haul applications. Switching between both devices can be done through the

microcontroller interface or by using the tristate hardware input pin as shown in the

figure.

Figure 47 Protection Switching Application (T1/J1)

For long haul redundancy requirements (see Figure 48), the analog switches can be

used to enable the line termination for the active device and to disable it for the stand-by

part. Switching between both devices is controled through the microcontroller interface.

F56V2_Receiver_2

E1/T1/J1

Receive

Line

RL1

RL2

RDO

RL1

RL2

RDO

XL1

XL2

E1/T1/J1

Transmit

Line

XDI

XL1

XL2

XDI

TRIST

active device

stand-by device

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Hardware Description

Figure 48 Long Haul Protection Switching Application (T1/J1)

5.1.9 Loss-of-Signal Detection (T1/J1)

There are different definitions for detecting Loss-Of-Signal alarms (LOS) in the ITU-T

G.775 and AT&T TR 54016. The FALC®56 covers all these standards. The LOS

indication is performed by generating an interrupt (if not masked) and activating a status

bit. Additionally a LOS status change interrupt is programmable by register GCR.SCI.

• Detection:

An alarm is generated if the incoming data stream has no pulses (no transitions) for

a certain number (N) of consecutive pulse periods. “No pulse” in the digital receive

interface means a logical zero on pins RDIP/RDIN or ROID. A pulse with an

amplitude less than Q dB below nominal is the criteria for “no pulse” in the analog

receive interface (LIM1.DRS = 0). The receive signal level Q is programmable by

F56V2_Receiver_

E1/T1/J1

Receive

Line

RL1

RL2

RDO

RL1

RL2

RDO

XL1

XL2

E1/T1/J1

Transmit

Line

XDI

XL1

XL2

XDI

active device

stand-by device

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Functional Description T1/J1

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Hardware Description

three control bits LIM1.RIL(2:0) (see Chapter 11.3 on page 466). The number N is

set by an 8-bit register (PCD). The contents of the PCD register is multiplied by 16,

which results in the number of pulse periods, i.e. the time which has to suspend until

the alarm has to be detected. The programmable range is 16 to 4096 pulse periods.

• Recovery:

In general the recovery procedure starts after detecting a logical "1" (digital receive

interface) or a pulse (analog receive interface) with an amplitude more than Q dB

(defined by LIM1.RIL(2:0)) of the nominal pulse. The value in the 8-bit register PCR

defines the number of pulses (1 to 255) to clear the LOS alarm. Additional recovery

conditions are programmed by register LIM2.

If a loss-of-signal condition is detected in long-haul mode, the data stream can optionally

be cleared automatically to avoid bit errors before LOS is indicated. The selection is

done by LIM1.CLOS = 1.

5.1.10 Receive Jitter Attenuator (T1/J1)

The receive jitter attenuator is placed in the receive path. The working clock is an

internally generated high frequency clock based on the clock provided on pin MCLK. The

jitter attenuator meets the requirements of PUB 62411, PUB 43802,

TR-TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431, G.703 and G. 824.

The internal PLL circuitry DCO-R generates a "jitter-free" output clock which is directly

depending on the phase difference of the incoming clock and the jitter attenuated

clock.The receive jitter attenuator can be synchronized either on the extracted receive

clock RCLK or on a 1.544-, 2.048-MHz or 8-kHz clock provided on pin SYNC (8 kHz in

master mode only). The received data is written into the receive elastic buffer with RCLK

and are read out with the de-jittered clock sourced by DCO-R. The jitter attenuated clock

can be output on pins RCLK, CLK1 or SCLKR. Optionally an 8-kHz clock is provided on

pin SEC/FSC.

The DCO-R circuitry attenuates the incoming jittered clock starting at 6-Hz jitter

frequency with 20 dB per decade fall-off. Wander with a jitter frequency below 6 Hz is

passed unattenuated. The intrinsic jitter in the absence of any input jitter is < 0.02 UI.

For some applications it might be useful to start jitter attenuation at lower frequencies.

Therefore the corner frequency is switchable by the factor of ten down to 0.6 Hz

(LIM2.SCF).

The DCO-R circuitry is automatically centered to the nominal bit rate if the reference

clock on pin SYNC/RCLK is missed for 2, 3 or 4 of the 2.048-MHz or 1.544-MHz clock

periods. This center function of DCO-R can be optionally disabled (CMR2.DCF = 1) in

order to accept a gapped reference clock.

In analog line interface mode the RCLK is always running. Only in digital line interface

mode with single-rail data (NRZ) a gapped clock on pin RCLK can occur.

The receive jitter attenuator works in two different modes:

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Hardware Description

•Slave mode

In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route

clock. In case of LOS the DCO-R switches automatically to master mode. If bit

CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.

• Master mode

In master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no

clock is supplied on pin SYNC. If an external clock on the SYNC input is applied, the

DCO-R synchronizes to this input. The external frequency can be 1.544 MHz

(LIM1.DCOC = 0; IPC.SSYF = 0), 2.048 MHz (LIM1.DCOC = 1; IPC.SSYF = 0) or

8.0 kHz (IPC.SSYF = 1; LIM1.DCOC = don’t care).

The following table shows the clock modes with the corresponding synchronization

sources.

Table 29 System Clocking (T1/J1)

Mode Internal

LOS Active

SYNC

Input

System Clocks

Master independent Fixed to

VDD

DCO-R centered, if CMR2.DCF = 0.

(CMR2.DCF should not be set)

Master independent 1.544 MHz Synchronized on SYNC input (external

1.544 MHz, IPC.SSYF = 0, LIM1.DCOC = 0)

Master independent 2.048 MHz Synchronized on SYNC input (external

2.048 MHz, IPC.SSYF = 0, LIM1.DCOC = 1)

Master independent 8.0 kHz Synchronized on SYNC input (external 8.0 kHz,

IPC.SSYF = 1, CMR2.DCF = 0)

Slave no Fixed to

VDD

Synchronized on line RCLK

Slave no 1.544 or

2.048 MHz

Synchronized on line RCLK

Slave yes Fixed to

VDD

CMR1.DCS = 0:

DCO-R is centered, if CMR2.DCF = 0.

(CMR2.DCF should not be set)

CMR1.DCS = 1:

Synchronized on line RCLK

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Functional Description T1/J1

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Hardware Description

The jitter attenuator meets the jitter transfer requirements of the PUB 62411,

PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431 and G.703 (refer

to Figure 49).

Figure 49 Jitter Attenuation Performance (T1/J1)

Slave yes 1.544 or

2.048 MHz

CMR1.DCS = 0:

Synchronized on SYNC input (external 1.544 or

2.048 MHz)

CMR1.DCS = 1:

Synchronized on line clock RCLK

Table 29 System Clocking (T1/J1) (cont’d)

Mode Internal

LOS Active

SYNC

Input

System Clocks

ITD10314

-70

Frequency

Attenuation

-60

-50

-40

-30

-20

-10

10 100 1000 10000 100000

Slope

Slope -

dB/Decade

FALC

PUB 62411_H

PUB 62411_L

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Hardware Description

5.1.11 Jitter Tolerance (T1/J1)

The FALC®56 receiver’s tolerance to input jitter complies with ITU, AT&T and Telcordia

requirements for T1 applications.

Figure 50 shows the curves of different input jitter specifications stated below as well as

the FALC®56 performance.

Figure 50 Jitter Tolerance (T1/J1)

Jitter Amplitude

Jitter Frequency

1 10 100 1000 10000 100000Hz

0.1

100

1000

PUB 62411

TR-NWT 000499 Cat II

CCITT G.823

ITU-T I.431

FALC

F0025

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Hardware Description

5.1.12 Output Jitter (T1/J1)

According to the input jitter defined by PUB62411 the FALC®56 generates the output

jitter which is specified in Table 30 below.

5.1.13 Framer/Synchronizer (T1/J1)

The following functions are performed:

• Synchronization on pulse frame and multiframe

• Error indication when synchronization is lost. In this case, AIS is sent to the system

side automatically and remote alarm to the remote end if enabled.

• Initiating and controlling of resynchronization after reaching the asynchronous state.

This is done automatically by the FALC®56 or user controlled by the microprocessor

interface.

• Detection of remote alarm (yellow alarm) indication from the incoming data stream.

• Separation of service bits and data link bits. This information is stored in special

status registers.

• Detection of framed or unframed in-band loop-up/-down code

• Generation of various maskable interrupt statuses of the receiver functions.

• Generation of control signals to synchronize the CRC checker, and the receive

elastic buffer.

If programmed and applicable to the selected multiframe format, CRC checking of the

incoming data stream is done by generating check bits for a CRC multiframe according

to the CRC6 procedure (as defined in ITU-T G.704). These bits are compared with those

check bits that are received during the next CRC multiframe. If there is at least one

mismatch, the 16-bit CRC error counter is incremented.

5.1.14 Receive Elastic Buffer (T1/J1)

The received bit stream is stored in the receive elastic buffer. The memory is organized

as a two-frame elastic buffer with a maximum size of 2 ×193 bit. The size of the elastic

buffer is configured independently for the receive and transmit direction. Programming

of the receive buffer size is done by SIC1.RBS1/0:

Table 30 Output Jitter (T1/J1)

Specification Measurement Filter Bandwidth Output Jitter

(UI peak to peak)

Lower Cutoff Upper Cutoff

PUB 62411 10 Hz 8 kHz < 0.015

8 kHz 40 kHz < 0.015

10 Hz 40 kHz < 0.015

Broadband < 0.02

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Functional Description T1/J1

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Hardware Description

• RBS1/0 = 00: two frame buffer or 386 bits

Maximum of wander amplitude (peak-to-peak): (1 UI = 648 ns)

System interface clocking rate: modulo 2.048 MHz:

142 UI in channel translation mode 0

78 UI in channel translation mode 1

System interface clocking rate: modulo 1.544 MHz:

Maximum of wander: 140 UI

average delay after performing a slip: 1 frame or 193 bits

• RBS1/0 = 01: one frame buffer or 193 bits

System interface clocking rate: modulo 2.048 MHz:

Maximum of wander: 70 UI in channel translation mode 0

Maximum of wander: 50 UI in channel translation mode 1

System interface clocking rate: modulo 1.544 MHz:

Maximum of wander: 74 UI

average delay after performing a slip: 96 bits

• RBS1/0 = 10: short buffer or 96 bits

System interface clocking rate: modulo 2.048 MHz:

Maximum of wander: 28 UI in channel translation mode 0; channel translation mode

1 not supported

System interface clocking rate: modulo 1.544 MHz:

Maximum of wander: 38 UI

average delay after performing a slip: 48 bits

• RBS1/0 = 11: Bypass of the receive elastic buffer

The buffer functions are:

• Clock adaption between system clock (SCLKR) and internally generated route clock

(RCLK).

• Compensation of input wander and jitter.

• Frame alignment between system frame and receive route frame

• Reporting and controlling of slips

Controlled by special signals generated by the receiver, the unipolar bit stream is

converted into bit-parallel, time slot serial data which is circularly written to the elastic

buffer using internally generated Receive Route Clock (RCLK).

Reading of stored data is controlled by the system clock sourced by SCLKR or by the

receive jitter attenuator and the synchronization pulse (SYPR) together with the

programmed offset values for the receive time slot/clock slot counters. After conversion

into a serial data stream, the data is sent out on port RDO. If the receive buffer is

bypassed programming of the time slot offset is disabled and data is clocked off with

RCLK instead of SCLKR.

The 24 received time slots (T1/J1) can be translated into the 32 system time slots (E1)

in two different channel translation modes (FMR1.CTM). Unequipped time slots are set

to FFH. See Table 31.

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Functional Description T1/J1

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Hardware Description

– : FFH

In one frame or short buffer mode the delay through the receive buffer is reduced to an

average delay of 96 or 48 bits. In bypass mode the time slot assigner is disabled. In this

case SYPR programmed as input is ignored. Slips are performed in all buffer modes

except bypass mode. After a slip is detected the read pointer is adjusted to one half of

the current buffer size.

Table 32 gives an overview of the receive buffer operating mode.

Table 31 Channel Translation Modes (DS1/J1)

Channels Time Slots Channels Time Slots

Channel

Translation

Mode 0

Channel

Translation

Mode 1

Channel

Translation

Mode 0

Channel

Translation

Mode 1

FS/DLFS/DL0–1616

111131717

222141818

333151919

– 44–2020

455162121

566172222

677182323

– 88–2424

79919–25

8 101020– 26

9 111121– 27

–1212––28

10 13 13 22 – 29

11 14 14 23 – 30

12 15 15 24 – 31

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Hardware Description

Figure 51 gives an idea of operation of the receive elastic buffer:

A slip condition is detected when the write pointer (W) and the read pointer (R) of the

memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a

slip condition is detected, a negative slip (one frame or one half of the current buffer size

is skipped) or a positive slip (one frame or one half of the current buffer size is read out

twice) is performed at the system interface, depending on the difference between RCLK

and the current working clock of the receive backplane interface, i.e. on the position of

pointer R and W within the memory. A positive/negative slip is indicated by the interrupt

status bits ISR3.RSP and ISR3.RSN.

Table 32 Receive Buffer Operation Modes (T1/J1)

Buffer Size

(SIC1.RBS1/0)

TS Offset program.

(RC1/0) + SYPR = input

Slip perform.

Bypass1)

1) In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK.

Disabled No

Short buffer Not recommended,

recommended:

SYPR = output

Yes

1 frame Not recommended,

recommended:

SYPR = output

Yes

2 frames enabled Yes

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Hardware Description

Figure 51 The Receive Elastic Buffer as Circularly Organized Memory

Limits for Slip Detection (mode dependent)

Read Pointer (System Clock controlled)

Write Pointer (Route Clock controlled)

R’

S+, S-

Frame 2 Time Slots

S-

Frame 1 Time Slots

Moment of Slip Detection

ITD10952

WS+

Slip

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Hardware Description

5.1.15 Receive Signaling Controller (T1/J1)

The signaling controller can be programmed to operate in various signaling modes. The

FALC®56 performs the following signaling and data link methods.

5.1.15.1 HDLC or LAPD Access

The FALC®56 offers three independent HDLC channels. Any HDLC channel can be

attached either to the line side ("normal HDLC") or to the system side ("inverse HDLC").

Each of them provides the following features:

• 64 byte receive FIFO for each channel

• 64 byte transmit FIFO for each channel

• Transmission in one of 24 time slots

(time slot number programmable for each channel individually)

• Transmission in even frames only, odd frames only or both

(programmable for each channel individually)

• Bit positions to be used in selected time slots are maskable

(any bit position can be enabled for each channel individually)

• HDLC or transparent mode

• Flag detection

• CRC checking

• Bit-stuffing

• Flexible address recognition (1 byte, 2 bytes)

• C/R bit processing (according to LAPD protocol)

In addition to this, HDLC channel 1 provides:

• SS7 support

• BOM (bit oriented message) support

• Flexibility to insert and extract data during certain time slots, any combination of time

slots can be programmed independently for the receive and transmit direction

In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD

according to Q.921 is supported. The signaling controller of the FALC®56 performs the

flag detection, CRC checking, address comparison and zero bit removing. The received