JUNE. 2001 Ver 1.00 HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS81C2012 GMS81C2020 User's Manual HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS81C2012 GMS81C2020 User's Manual (Ver. 1.00) Version 1.00 Published by MCU Application Team 2001 HYNIX Semiconductor All right reserved. Additional information of this manual may be served by HYNIX Semiconductor offices in Korea or Distributors and Representatives listed at address directory. HYNIX Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, HYNIX Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. Table of Contents 1. OVERVIEW............................................1 Description .........................................................1 Features .............................................................1 Development Tools ............................................2 Ordering Information 2. BLOCK DIAGRAM .................................3 3. PIN ASSIGNMENT ................................4 4. PACKAGE DIAGRAM ............................6 5. PIN FUNCTION......................................8 6. PORT STRUCTURES..........................11 7. ELECTRICAL CHARACTERISTICS ....14 Absolute Maximum Ratings .............................14 Recommended Operating Conditions ..............14 A/D Converter Characteristics .........................14 DC Electrical Characteristics for Standard Pins(5V) 15 DC Electrical Characteristics for High-Voltage Pins 16 AC Characteristics ...........................................17 AC Characteristics ...........................................18 Typical Characteristics .....................................19 8. MEMORY ORGANIZATION.................21 8-bit Capture Mode ......................................... 51 16-bit Capture Mode ....................................... 54 PWM Mode ..................................................... 55 13. ANALOG DIGITAL CONVERTER .....58 14. SERIAL PERIPHERAL INTERFACE .61 Transmission/Receiving Timing ...................... 63 The method of Serial I/O ................................. 64 The Method to Test Correct Transmission ...... 64 15. BUZZER FUNCTION .........................65 16. INTERRUPTS ....................................67 Interrupt Sequence .......................................... 69 Multi Interrupt .................................................. 71 External Interrupt ............................................. 72 17. Power Saving Mode...........................74 Operating Mode .............................................. 75 Stop Mode ....................................................... 76 Wake-up Timer Mode ...................................... 77 Internal RC-Oscillated Watchdog Timer Mode 78 Minimizing Current Consumption .................... 79 18. OSCILLATOR CIRCUIT.....................81 19. RESET ...............................................82 External Reset Input ........................................ 82 Watchdog Timer Reset ................................... 82 Registers ..........................................................21 Program Memory .............................................24 Data Memory ...................................................27 Addressing Mode .............................................31 20. POWER FAIL PROCESSOR.............83 9. I/O PORTS ...........................................35 DEVICE CONFIGURATION AREA ................. 85 21. OTP PROGRAMMING.......................85 10. BASIC INTERVAL TIMER..................39 A. CONTROL REGISTER LIST .................. i 11. WATCHDOG TIMER..........................41 B. INSTRUCTION ..................................... iii 12. TIMER/EVENT COUNTER ................44 8-bit Timer / Counter Mode ..............................46 16-bit Timer / Counter Mode ............................50 8-bit Compare Output (16-bit) ..........................51 Terminology List ................................................ iii Instruction Map ..................................................iv Instruction Set ....................................................v C. MASK ORDER SHEET ........................ xi GMS81C2012/GMS81C2020 GMS81C2012/GMS81C2020 CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver 1. OVERVIEW 1.1 Description The GMS81C2012 and GMS81C2020 are advanced CMOS 8-bit microcontroller with 12K/20K bytes of ROM. These are a powerful microcontroller which provides a highly flexible and cost effective solution to many VFD applications. These provide the following standard features: 12K/20K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit High Speed PWM Output, Programmable Buzzer Driving Port, 8-bit Basic Interval Timer, 7-bit Watch dog Timer, Serial Peripheral Interface, on-chip oscillator and clock circuitry. They also come with high voltage I/O pins that can directly drive a VFD (Vacuum Fluorescent Display). In addition, the GMS81C2012 and GMS81C2020 support power saving modes to reduce power consumption. Device name ROM Size GMS81C2012 12K bytes GMS81C2020 20K bytes RAM Size 448 bytes OTP Package - 64SDIP, 64MQFP, 64LQFP GMS87C2020 1.2 Features * 20K/12K bytes ROM(EPROM) * 448 Bytes of On-Chip Data RAM (Including STACK Area) * Minimum Instruction Execution time: - 1uS at 4MHz (2cycle NOP Instruction) * One 8-bit Basic Interval Timer * 12-Channel 8-bit On-Chip Analog to Digital Converter * Oscillator: - Crystal - Ceramic Resonator - External R Oscillator * One 8-bit Serial Peripheral Interface * Low Power Dissipation Modes - STOP mode - Wake-up Timer Mode - Standby Mode - Watch Mode - Sub-active Mode * Two External Interrupt Ports * Operating Voltage: 2.7V ~ 5.5V (at 4.5MHz) * One Programmable 6-bit Buzzer Driving Port * Operating Frequency: 1MHz ~ 4.5MHz * 60 I/O Lines - 56 Programmable I/O pins (Included 30 high-voltage pins Max. 40V) - Three Input Only pins: 1 high-voltage pin - One Output Only pin * Sub-clock: 32.768KHz Crystal Oscillator * One 7-bit Watch Dog Timer * Two 8-bit Timer/Counters * 10-bit High Speed PWM Output * Enhanced EMS Improvement Power Fail Processor (Noise Immunity Circuit) * Eight Interrupt Sources - Two External Sources (INT0, INT1) - Two Timer/Counter Sources (Timer0, Timer1) - Four Functional Sources (SPI,ADC,WDT,BIT) JUNE. 2001 Ver 1.00 1 GMS81C2012/GMS81C2020 1.3 Development Tools The GMS81C20xx are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are third different type programmers such as emulator add-on board type, single type, gang type. For mode detail, Refer to "21. OTP PROGRAMMING" on page 85. Macro assembler operates under the MS-Windows 95/98TM. Please contact sales part of Hynix Semiconductor. In Circuit Emulators CHOICE-Dr. Socket Adapter for OTP OA87C20XX-64SD (64SDIP) OA87C20XX-64QF (64MQFP) OA87C20XX-64QT (64LQFP) POD CHPOD81C20D-64SD (64SDIP) Assembler HYNIX Macro Assembler 1.4 Ordering Information Device name ROM Size RAM size Package Mask version GMS81C2012 K GMS81C2012 Q GMS81C2012 LQ GMS81C2020 K GMS81C2020 Q GMS81C2020 LQ 12K bytes 12K bytes 12K bytes 20K bytes 20K bytes 20K bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 64SDIP 64MQFP 64LQFP 64SDIP 64MQFP 64LQFP OTP version GMS87C2020 K GMS87C2020 Q GMS87C2020 LQ 20K bytes OTP 20K bytes OTP 20K bytes OTP 448 bytes 448 bytes 448 bytes 64SDIP 64MQFP 64LQFP 2 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 2. BLOCK DIAGRAM R07 R06 R05 R04 R03/BUZO R02/EC0 R01/INT1 R00/INT0 AVDD AVSS ADC Power Supply Driver Buzzer PSW ALU R0 A X R10~R17 R20~R27 R30~R35 R1 R2 R3 Y Stack Pointer Vdisp/RA RA PC Data Memory (448 bytes) Program Memory Interrupt Controller Data Table 8-b it B a sic In terval Tim er S ystem controller S ystem C lock C ontroller S ub S ystem C lock C ontroller Watchdog Timer 8-bit Timer/ Counter 8-bit serial Interface 10-bit PWM PC 8-bit ADC Tim ing generator C lock G enerator VDD VSS SXIN SXOUT XOUT XIN RESET R4 Power Supply R40 / T0O R41 R42 R43 R5 R50 R51 R52 R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57 R6 R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7 R7 R70 / AN8 R71 / AN9 R72 / AN10 R73 / AN11 High Voltage Port JUNE. 2001 Ver 1.00 3 GMS81C2012/GMS81C2020 3. PIN ASSIGNMENT 64SDIP T0O SCLK SIN SOUT PWM1O/T1O AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GMS81C2012/20 SXIN SXOUT R40 R41 R42 R43 R50 R51 R52 R53 R54 R55 R56 R57 RESET XI XO VSS R74 R75 AVSS R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73 AVDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD Vdisp BUZO EC0 INT1 INT0 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 GMS81C2012/20 32 31 30 29 28 27 26 25 24 23 22 21 20 R04 R03 R02 R01 R00 VDD AVDD R73 R72 R71 R70 R67 R66 BUZO EC0 INT1 INT0 AN11 AN10 AN9 AN8 AN7 AN6 SCLK SIN SOUT PWM1O/T1O R52 R53 R54 R55 R56 R57 RESET XI XO VSS SXI R74 SXO R75 AVSS AN0 R60 AN1 R61 AN2 R62 AN3 R63 AN4 R64 AN5 R65 Vdisp T0O R30 R31 R32 R33 R34 R35 RA R40 R41 R42 R43 R50 R51 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 64MQFP High Voltage Port 4 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 64LQFP Vdisp T0O 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GMS81C2012/20 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 R06 R05 R04 R03 R02 R01 R00 VDD AVDD R73 R72 R71 R70 R67 R66 R65 BUZO EC0 INT1 INT0 AN11 AN10 AN9 AN8 AN7 AN6 AN5 SIN SOUT PWM1O/T1O R54 R55 R56 R57 RESET XIN XOUT VSS R74 SXIN R75 SXOUT AVSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK R27 R30 R31 R32 R33 R34 R35 RA R40 R41 R42 R43 R50 R51 R52 R53 High Voltage Port JUNE. 2001 Ver 1.00 5 GMS81C2012/GMS81C2020 4. PACKAGE DIAGRAM 64SDIP UNIT: INCH 0.750 BSC min. 0.015 0.205 max. 2.280 2.260 0.070 BSC 0.140 0.120 0.050 0.030 0.022 0.016 0.680 0.660 0.012 0.008 0-15 64MQFP 24.15 23.65 20.10 19.90 18.15 17.65 14.10 13.90 UNIT: MM 0.36 0.10 SEE DETAIL "A" 3.18 max. 1.95 REF 0.50 0.35 6 1.03 0.73 0.23 0.13 0-7 1.00 BSC DETAIL "A" JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 64LQFP 12.00 BSC 10.00 BSC 1.45 1.35 10.00 BSC 12.00 BSC UNIT: MM 0-7 0.15 0.05 SEE DETAIL "A" 1.60 max. 0.38 0.22 JUNE. 2001 Ver 1.00 0.50 BSC 0.75 0.45 1.00 REF DETAIL "A" 7 GMS81C2012/GMS81C2020 5. PIN FUNCTION VDD: Supply voltage. tions of the following special features. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. AVSS: ADC circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XOUT: Output from the inverting oscillator amplifier. RA(Vdisp): RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option. Port pin RA Alternate function Vdisp (High-voltage input power supply) R00~R07: R0 is an 8-bit high-voltage CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features. Port pin R00 R01 R02 R03 Alternate function INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output) R10~R17: R1 is an 8-bit high-voltage CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R20~R27: R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R30~R35: R3 is a 6-bit high-voltage CMOS bidirectional I/O port. R3 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R40~R43: R4 is a 4-bit CMOS bidirectional I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R4 serves the func- 8 Port pin R40 Alternate function T0O (Timer/Counter 0 output) R50~R57: R5 is an 8-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features. Port pin R53 R54 R55 R56 Alternate function SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output) R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input. Port pin R60 R61 R62 R63 R64 R66 R66 R67 Alternate function AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7) R70~R73: R7 is a 4-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R7 is shared with the ADC input. Port pin R70 R71 R72 R73 Alternate function AN8 (Analog Input 8) AN9 (Analog Input 9) AN10 (Analog Input 10) AN11 (Analog Input 11) SXIN: Input to the internal subsystem clock operating circuit. In addition, SXIN serves the R74 pin when selected by the code option. *R74 has a Pull-up circuit. SXOUT: Output from the inverting subsystem oscillator amplifier. In addition, SXOUT serves the R75 pin when JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 selected by the code option. *R75 has a Pull-up circuit. Port pin Alternate function SXI SXO R74(Included Internal Pull-up Resister) R75(Included Internal Pull-up Resister) JUNE. 2001 Ver 1.00 9 GMS81C2012/GMS81C2020 Function PIN NAME In/Out Basic VDD - Supply voltage VSS - Circuit ground RA (Vdisp) I(I) 1-bit high-voltage Input only port RESET I Reset signal input XIN I Oscillation input XOUT O Oscillation output SXIN(R74) I Sub Oscillation input SXOUT(R75) O Sub Oscillation output Alternate High-voltage input power supply pin General I/O ports R00 (INT0) I/O (I) External interrupt 0 input R01 (INT1) I/O (I) External interrupt 1 input R02 (EC0) I/O (I) R03 (BUZO) I/O (O) 8-bit high-voltage I/O ports Buzzer driving output R04~R07 I/O R10~R17 I/O 8-bit high-voltage I/O ports R20~R27 I/O 8-bit high-voltage I/O ports R30~R35 I/O 6-bit high-voltage I/O ports R40 (T0O) I/O (O) R41~R43 I/O R50~R52 I/O R53 (SCLK) R54 (SIN) R56 (PWM1O/T1O) I/O (O) Timer/Counter 0 output Serial clock source I/O (I) I/O (O) R57 4-bit general I/O ports I/O (I/O) R55 (SOUT) Timer/Counter 0 external input Serial data input 8-bit general I/O ports Serial data output PWM 1 pulse output /Timer/Counter 1 output I/O R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports R70~R73 (AN8~AN11) I/O (I) 4-bit general I/O ports AVDD - Supply voltage input pin for ADC AVSS - Ground level input pin for ADC VDD - Supply voltage VSS - Circuit ground Analog voltage input Table 5-1 GMS81C2020 Port Function Description 10 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 6. PORT STRUCTURES R53/SCLK R41~R43, R50~R52, R57 VDD Pull-up Tr. VDD Selection Mask Option N-MOS Open Drain Select VDD Pull-up Tr. SCLK Output MUX Data Reg. Data Bus Mask Option VDD Data Reg. Pin Data Bus Dir. Reg. VSS Direction Reg. Pin Rd M UX VSS Rd R00/INT0, R01/INT1, R02/EC0 SCLK Input Selection VDD Data Bus Data Reg. R54/SIN Mask Option Dir. Reg. Pin Selection VDD Pull-up Tr. N-MOS Open Drain Select Rd Vdisp VDD Data Reg. Mask Option Data Bus EX) INT0 Alternate Function R40/T0O Direction Reg. Pin Rd VSS VDD Selection VDD Secondary Function Pull-up Tr. Mask Option SIN Input MUX Pin Data Bus Data Reg. VSS Direction Reg. MUX Rd JUNE. 2001 Ver 1.00 11 GMS81C2012/GMS81C2020 R55/SOUT RESET Selection N-MOS Open Drain Select VDD Pull-up Tr. SOUT output Mask Option MUX OTP :disconnected Main :connected RESET VDD Data Reg. VSS Direction Reg. Data Bus VDD Pin IOSWB VSS SXIN, SXOUT Rd IOSWIN Input VDD SXOUT RA/Vdisp VDD SXIN Data bus Rd Stop Subclk Off Mask Option Vdisp XIN, XOUT R04~R07, R10~R17, R20~R27, R30~R35 VDD Data Bus Data Reg. VDD Mask Option Dir. Reg. XOUT Pin Stop Mainclk Off XIN Vdisp MUX Rd VSS 12 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 R74, R75 R60~R67/AN0~AN7, R70~R73/AN8~AN11 VDD VDD Pull-up Tr. Data Reg. Data Bus VDD Data Reg. Pin Dir. Reg. VDD Direction Reg. Data Bus VSS MUX Mask Option Pin VSS Rd Rd R03/BUZO Selection Secondary Function MUX Data Reg. Data Bus A/D Converter Analog Input Mode A/D Ch. Selection VDD Mask Option Dir. Reg. Pin Vdisp M UX Rd R56/PWM1O/T1O Selection N-MOS Open Drain Select VDD Pull-up Tr. SOUT output MUX VDD Data Bus Data Reg. Direction Reg. Mask Option Pin VSS Rd JUNE. 2001 Ver 1.00 13 GMS81C2012/GMS81C2020 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Maximum output current sourced by (IOH per I/O Pin) ................................................................................... 8 mA Supply voltage ............................................. -0.3 to +7.0 V Storage Temperature .................................... -40 to +85 C Maximum current (IOL) ...................................... 100 mA Voltage on Normal voltage pin with respect to Ground (VSS) ..............................................................-0.3 to VDD+0.3 V Maximum current (IOH)........................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on High voltage pin with respect to Ground (VSS) ............................................................ -45V to VDD+0.3 V Maximum current out of VSS pin .......................... 150 mA Maximum current into VDD pin .............................. 80 mA Maximum current sunk by (IOL per I/O Pin) .......... 20 mA 7.2 Recommended Operating Conditions Specifications Parameter Symbol Condition Unit Min. Max. Supply Voltage VDD fXI = 4.5 MHz 2.7 5.5 V Operating Frequency fXIN VDD = VDD 1 4.5 MHz Operating Temperature TOPR -40 85 C 7.3 A/D Converter Characteristics (TA=25C, VDD=5V, VSS=0V, AVDD=5.12V, AVSS=0V @fXIN =4MHz) Specifications Parameter Symbol Condition Unit Min. Typ.1 Max. AVDD AVSS - AVDD V VAN AVSS-0.3 AVDD+0.3 V Current Following Between AVDD and AVSS IAVDD - - 200 uA Overall Accuracy CAIN - - 2 LSB Non-Linearity Error NNLE - - 2 LSB Differential Non-Linearity Error NDNLE - - 2 LSB Zero Offset Error NZOE - - 2 LSB Full Scale Error NFSE - - 2 LSB Gain Error NNLE - - 2 LSB - - 20 us Analog Power Supply Input Voltage Range Analog Input Voltage Range Conversion Time TCONV fXIN=4MHz 1. Data in "Typ" column is at 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 14 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 7.4 DC Electrical Characteristics for Standard Pins(5V) (VDD = 5.0V 10%, VSS = 0V, TA = -40 ~ 85C, fXIN = 4 MHz, Vdisp = VDD-40V to VDD), Specification Parameter Pin Symbol Test Condition XIN, SXIN VIH1 External Clock RESET,SIN,R55,SCLK, INT0&1,EC0 Min Typ.1 Max 0.9VDD VDD+0.3 VIH2 0.8VDD VDD+0.3 R40~R43,R5,R6,R70~R73 VIH3 0.7VDD VDD+0.3 XIN, SXIN VIL1 -0.3 0.1VDD RESET,SIN,R55,SCLK, INT0&1,EC0 VIL2 -0.3 0.2VDD R40~R43,R5,R6,R70~R73 VIL3 -0.3 0.3VDD Output High Voltage R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT VOH IOH = -0.5mA Output Low Voltage R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT VOL1 VOL2 IOL = 1.6mA IOL = 10mA Input High Leakage Current R40~R43,R5,R6,R70~R73 IIH1 Input Low Leakage Current R40~R43,R5,R6,R70~R73 IIL1 -1 Input Pull-up Current(*Option) R40~R43,R5,R6,R70~R73 IPU 50 Input High Voltage Input Low Voltage External Clock Unit V V VDD-0.5 V 0.4 2 V 1 uA uA 100 180 uA Power Fail Detect Voltage VDD VPFD Current dissipation in active mode VDD IDD fXIN=4.5MHz 8 mA Current dissipation in standby mode VDD ISTBY fXIN=4.5MHz 3 mA Current dissipation in sub-active mode VDD ISUB fXIN = Off fSXIN=32.7KHz 100 uA Current dissipation in watch mode VDD IWTC fXIN=Off fSXNI=32.7KHz 20 uA Current dissipation in stop mode VDD ISTOP fXIN=Off fSXIN=32.7KHz 10 uA 2.7 RESET,SIN,R55,SCLK, INT0,INT1,EC0 VT+~VT- 0.4 Internal RC WDT Frequency XOUT TRCWDT 8 RC Oscillation Frequency XOUT fRCOSC Hysteresis R= 120K 1.5 V V 2 30 KHz 2.5 MHz 1. Data in "Typ." column is at 4.5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. JUNE. 2001 Ver 1.00 15 GMS81C2012/GMS81C2020 7.5 DC Electrical Characteristics for High-Voltage Pins (VDD = 5.0V 10%, VSS = 0V, TA = -40 ~ 85C, fXIN = 4 MHz, Vdisp = VDD-40V to VDD) Specification Parameter Pin Symbol Test Condition Min Typ.1 Max Unit Input High Voltage R0,R1,R2,R30~R35,RA VIH 0.7VDD VDD+0.3 V Input Low Voltage R0,R1,R2,R30~R35,RA VIL VDD-40 0.3VDD V Output High Voltage R0,R1,R2,R30~R35 VOH IOH = -15mA IOH = -10mA IOH = - 4mA Output Low Voltage R0,R1,R2,R30~R35 VOL Vdisp = VDD-40 150K atVDD40 VDD-37 VDD-37 V 20 uA 1000 uA VDD+0.3 V Input High Leakage Current R0,R1,R2,R30~R35,RA IIH VIN=VDD-40V to VDD Input Pull-down Current(*Option) R0,R1,R2,R30~R35 IPD Vdisp=VDD-35V VIN=VDD R0,R1,R2,R30~R35,RA VIH Input High Voltage VDD-3.0 VDD-2.0 VDD-1.0 200 0.7VDD V 600 1. Data in "Typ." column is at 4.5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 16 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 7.6 AC Characteristics (TA=-40~ 85C, VDD=5V10%, VSS=0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. fCP XIN 1 - 8 MHz tCPW XIN 80 - - nS tRCP,tFCP XIN - - 20 nS Oscillation Stabilizing Time tST XIN, XOUT - - 20 mS External Input Pulse Width tEPW INT0, INT1, EC0 2 - - tSYS External Input Pulse Transition Time tREP,tFEP INT0, INT1, EC0 - - 20 nS tRST RESET 8 - - tSYS Operating Frequency External Clock Pulse Width External Clock Transition Time RESET Input Width tCPW 1/fCP tCPW VDD-0.5V XI 0.5V tRCP tSYS tFCP tRST RESETB 0.2VDD tEPW tEPW INT0, INT1 EC0 0.8VDD 0.2VDD tREP tFEP Figure 7-1 Timing Chart JUNE. 2001 Ver 1.00 17 GMS81C2012/GMS81C2020 7.7 AC Characteristics (TA=-40~+85C, VDD=5V10%, VSS=0V, fXIN=4MHz) Specifications Parameter Symbol Pins Unit Min. Typ. Max. Serial Input Clock Pulse tSCYC SCLK 2tSYS+200 - 8 ns Serial Input Clock Pulse Width tSCKW SCLK tSYS+70 - 8 ns Serial Input Clock Pulse Transition Time tFSCK tRSCK SCLK - - 30 ns SIN Input Pulse Transition Time tFSIN tRSIN SIN - - 30 ns SIN Input Setup Time (External SCLK) tSUS SIN 100 - - ns SIN Input Setup Time (Internal SCLK) tSUS SIN 200 - ns SIN Input Hold Time tHS SIN tSYS+70 - ns Serial Output Clock Cycle Time tSCYC SCLK 4tSYS - Serial Output Clock Pulse Width tSCKW SCLK tSYS-30 Serial Output Clock Pulse Transition Time tFSCK tRSCK SCLK 30 ns Serial Output Delay Time sOUT SOUT 100 ns tSCKW ns tSCKW 0.8VDD 0.2VDD tSUS tHS 0.8VDD 0.2VDD SIN tDS SOUT ns tSCYC tRSCK tFSCK SCLK 16tSYS tFSIN tRSIN 0.8VDD 0.2VDD Figure 7-2 Serial I/O Timing Chart 18 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 7.8 Typical Characteristics This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. IOH-VOH IOH (mA) VDD=5.0V Ta=25C -1.6 R40~R43, R5, R6, R70~R73 BUZO, T0O, PWM1O/T1O SCLK, SOUT pins IOH-VOH IOH-VOH IOH (mA) VDD=4.0V Ta=25C -1.6 IOH (mA) VDD=3.0V Ta=25C -1.6 -1.2 -1.2 -1.2 -0.8 -0.8 -0.8 -0.4 -0.4 -0.4 0 4.6 4.7 IOL-VOL IOL (mA) VDD=5.0V Ta=25C 16 4.8 4.9 VOH 5.0 (V) R40~R43, R5, R6, R70~R73 BUZO, T0O, PWM1O/T1O SCLK, SOUT pins 0 3.6 3.7 3.8 3.9 VOH 4.0 (V) IOL-VOL 2.6 12 8 8 8 4 4 4 0.8 IOH-VOH IOH (mA) VDD=5.0V Ta=25C -16 1.0 1.2 VOL 1.4 (V) R0, R1, R2,RA R30~R35 pins 0 0.6 0.8 1.0 1.2 VOL 1.4 (V) IOH-VOH 0.6 -8 -8 -8 -4 -4 -4 3.0 4.0 JUNE. 2001 Ver 1.00 VOH 5.0 (V) 0 1.0 2.0 1.0 1.2 VOL 1.4 (V) 3.0 4.0 VOH 5.0 (V) IOH (mA) VDD=3.0V Ta=25C -16 -12 2.0 0.8 IOH-VOH IOH (mA) VDD=4.0V Ta=25C -16 -12 1.0 VOH 3.0 (V) 0 -12 0 2.9 IOL (mA) VDD=3.0V Ta=25C 16 12 0.6 2.7 IOL-VOL IOL (mA) VDD=4.0V Ta=25C 16 12 0 2.8 0 3.0 4.0 VOH 5.0 (V) 0 1.0 2.0 19 GMS81C2012/GMS81C2020 VIH1 (V) 4 VDD-VIH1 XIN, SXIN pins fXIN=4.5MHz Ta=25C VIH2 (V) VDD-VIH2 RESET, R55, SIN, SCLK INT0, INT1, EC0 pins fXIN=4.5MHz Ta=25C VIH3 (V) 4 4 3 3 3 2 2 2 1 1 1 0 2 VIL1 (V) 4 3 VDD-VIL1 4 5 VDD 6 (V) XIN, SXIN pins fXIN=4.5MHz Ta=25C 0 1 VIL2 (V) 2 3 VDD-VIL2 4 5 VDD 6 (V) RESET, R55, SIN, SCLK INT0, INT1, EC0 pins fXIN=4.5MHz Ta=25C VIL3 (V) 3 3 3 2 2 2 1 1 1 3 IDD-VDD IDD (mA) 4 5 VDD 6 (V) 1 IDD (mA) Ta=25C 3.0 fXIN = 4.5MHz 2 3 ISBY-VDD Normal Operation 4.0 2.0 0 4 5 VDD 6 (V) fXIN=4.5MHz Ta=25C 1 4 2 R40~R43, R5 R6, R70~R73 pins 0 4 0 VDD-VIH3 2 3 VDD-VIL3 4 5 R40~R43, R5 R6, R70~R73 pins fXIN=4.5MHz Ta=25C 0 1 2 3 4 ISTOP-VDD Stand-by Mode 5 VDD 6 (V) Stop Mode IDD (A) Ta=25C 4.0 2.0 3.0 1.5 2.0 1.0 85C 25C -20C fXIN = 4.5MHz 2.5MHz 1.0 VDD 6 (V) 1.0 0.5 2.5MHz 0 2 20 3 4 5 VDD 6 (V) 0 2 3 4 5 VDD 6 (V) 0 2 3 4 5 VDD 6 (V) JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 8. MEMORY ORGANIZATION The GMS81C2012 and GMS81C2020 have separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 12K/20K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area. 8.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. PCH A ACCUMULATOR X X REGISTER Y Y REGISTER SP STACK POINTER PCL PROGRAM COUNTER PSW PROGRAM STATUS WORD Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 100H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used. Bit 15 00H~FFH Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Y Y A A Two 8-bit Registers can be used as a "YA" 16-bit Register Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be access (save or restore). JUNE. 2001 Ver 1.00 Stack Address ( 100H ~ 1FEH ) 8 7 Bit 0 01H SP Hardware fixed Note: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP ; SP FFH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. 21 GMS81C2012/GMS81C2020 PSW MSB N V G B H NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when G=1, page is selected to "page 1" BRK FLAG I Z LSB C RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] 22 This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100H to 1FFH. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 At execution of a CALL/TCALL/PCALL 01FE At acceptance of interrupt Push down 01FE PCH 01FD PCL 01FC 01FC PSW 01FB 01FB 01FD PCH PCL At execution of RET instruction Push down 01FE PCH 01FD PCL At execution of RET instruction 01FE PCH 01FD PCL 01FC 01FC PSW 01FB 01FB Pop up SP before execution 01FE 01FE 01FC 01FB SP after execution 01FC 01FB 01FE 01FE At execution of PUSH instruction PUSH A (X,Y,PSW) 01FE A 01FD Push down Pop up At execution of POP instruction POP A (X,Y,PSW) 01FE A 01FD 01FC 01FC 01FB 01FB Pop up 0100H Stack depth 01FEH SP before execution 01FE 01FD SP after execution 01FD 01FE Figure 8-4 Stack Operation JUNE. 2001 Ver 1.00 23 GMS81C2012/GMS81C2020 8.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 20K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Example: Usage of TCALL Figure 8-5, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6. ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. B000H LDA #5 TCALL 0FH : : ;1BYTE INSTR UCTIO N ;INSTEAD OF 3 BYTES ;NOR M AL C ALL 1 ;TCALL ADDRESS AREA FFC0H FFDFH FFE0H FFFFH TCALL area Interrupt Vector Area GMS81C2020, 20K ROM GMS81C2012, 12K ROM FEFFH FF00H PCALL area D000H The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory. Address Vector Area Memory 0FFE0H Figure 8-5 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7. - E2 - E4 Serial Communication Interface E6 Basic Interval Timer E8 Watchdog Timer Interrupt EA A/D Converter - EC - EE - F0 - F2 - F4 Timer/Counter 1 Interrupt F6 Timer/Counter 0 Interrupt F8 External Interrupt 1 FA External Interrupt 0 FC - FE RESET Vector Area NOTE: "-" means reserved area. Figure 8-6 Interrupt Vector Area 24 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 Address 0FF00H PCALL Area Memory Address PCALL Area (256 Bytes) 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF 0FFFFH Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0. Figure 8-7 PCALL and TCALL Memory Area PCALL rel TCALL n 4F35 4A PCALL 35H TCALL 4 4A 4F 01001010 35 ~ ~ ~ ~ ~ ~ 0D125H ~ ~ NEXT Reverse PC: 11111111 11010110 FH FH DH 6H 0FF00H 0FF35H NEXT 0FFFFH JUNE. 2001 Ver 1.00 0FF00H 0FFD6H 25 0FFD7H D1 0FFFFH 25 GMS81C2012/GMS81C2020 Example: The usage software example of Vector address for GMS81C2020. ; ORG 0FFE0H DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW NOT_USED NOT_USED SIO BIT_TIMER WD_TIMER ADC NOT_USED NOT_USED NOT_USED NOT_USED TIMER1 TIMER0 INT1 INT0 NOT_USED RESET ORG ORG 0B000H 0D000H ; ; ; ; Serial Interface Basic Interval Timer Watchdog Timer ADC ; ; ; ; ; ; Timer-1 Timer-0 Int.1 Int.0 Reset ; GMS81C2020(20K)ROM Start address ; GMS81C2012(12K)ROM Start address ;******************************************* ; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts CLRG LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #0FFH ;Stack Pointer Initialize TXSP ; LDM R0, #0 ;Normal Port 0 LDM R0IO,#82H ;Normal Port Direction : : : LDM TDR0,#125 ;8us x 125 = 1mS LDM TM0,#0FH ;Start Timer0, 8us at 4MHz LDM IRQH,#0 LDM IRQL,#0 LDM IENH,#0E0H ;Enable Timer0, INT0, INT1 LDM IENL,#0 LDM IEDS,#05H ;Select falling edge detect on INT pin LDM R0FUNC,#03H ;Set external interrupt pin(INT0, INT1) EI : : : ;Enable master interrupt : : NOT_USED:NOP RETI 26 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 8.3 Data Memory Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM (including Stack) and control registers. 0000H PAGE0 00FFH 0100H Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. User Memory 00BFH 00C0H digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. When "G-flag=0", this page is selected Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example "LDM". Control Registers Example; To write at CKCTLR LDM User Memory or Stack Area PAGE1 CLCTLR,#09H ;Divide ratio(/16) When "G-flag=1" 01FFH Figure 8-8 Data Memory Map Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. User Memory The GMS81C20xx have 448 x 8 bits for the user memory (RAM). When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 23. JUNE. 2001 Ver 1.00 27 GMS81C2012/GMS81C2020 Address Symbol R/W RESET Value Addressing mode 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH R0 R0IO R1 R1IO R2 R2IO R3 R3IO R4 R4IO R5 R5IO R6 R6IO R7 R7IO R/W W R/W W R/W W R/W W R/W W R/W W R/W W R/W W Undefined 0000_0000 Undefined 00000000 Undefined 0000_0000 Undefined --00_0000 Undefined ----_0000 Undefined 0000_0000 Undefined 0000_0000 Undefined --00_0000 byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte 0D0H 0D1H TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM1HR BUR R/W R W R R/W W W R R R/W W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte 0EFH SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0001 Undefined 0000_---0000_---0000_---0000_-------_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH R0FUNC R4FUNC R5FUNC R6FUNC R7FUNC R5NODR SCMR RA W W W W W W R/W R ----_0000 ----_---0 -0--_---0000_0000 ----_0000 0000_0000 ---0_0000 Undefined byte byte byte byte byte byte byte -3 0D1H 0D1H 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H 0DEH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH Note: Several names are given at same address. Refer to below table. When read When write Addr. Timer Mode Capture Mode PWM Mode Timer Mode PWM Mode D1H T0 CDR0 - TDR0 - TDR1 T1PPR - T1PDR D3H D4H ECH T1 CDR1 BITR T1PDR CKCTLR Table 8-2 Various Register Name in Same Address Table 8-1 Control Registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. 3. RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option. 28 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0CK2 T0CK1 T0CK0 T0CN T0ST T1CN T1ST C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C2H R1 R1 Port Data Register (Bit[7:0]) C3H R1IO R1 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register (Bit[5:0]) C7H R3IO R3 Port Direction Register (Bit[5:0]) C8H R4 R4 Port Data Register (Bit[3:0]) C9H R4IO R4 Port Direction Register (Bit[3:0]) CAH R5 R5 Port Data Register (Bit[7:0]) CBH R5IO R5 Port Direction Register (Bit[7:0]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0]) CEH R7 R7 Port Data Register (Bit[5:0]) CFH R7IO R7 Port Direction Register (Bit[5:0]) D0H TM0 D1H T0/TDR0/ CDR0 D2H TM1 D3H TDR1/ T1PPR Timer1 Data Register / PWM1 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM1 Duty Register D5H PWM1HR PWM1 High Register(Bit[3:0]) DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - - E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM ADS1 ADS0 ADST ADSF EBH ADCR - - CAP0 Timer0 Register / Timer0 Data Register / Capture0 Data Register POL 16BIT PWM1E CAP1 T1CK1 T1CK0 SPI DATA REGISTER - ADEN ADS3 ADS2 ADC Result Data Register Table 8-3 Control Registers of GMS81C2020 These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by register operation instruction as " LDM dp,#imm ". JUNE. 2001 Ver 1.00 29 GMS81C2012/GMS81C2020 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTON BTCL BTS2 BTS1 BTS0 ECH BITR1 ECH CKCTLR1 EDH WDTR WDTCL EFH PFDR2 - - - - - PFDIS PFDM PFDS F4H R0FUNC - - - - BUZO EC0 INT1 INT0 F5H R4FUNC - - - - - - - T0O F6H R5FUNC - PWM1O/ T1O - - - - - - F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F8H R7FUNC - - - - AN11 AN10 AN9 AN8 F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 NODR2 NODR1 NODR0 FAH SCMR - - - CS1 CS0 SUBON CLKSEL MAINOFF FBH RA - - - - - - - RA0 Basic Interval Timer Data Register - WAKEUP RCWDT 7-bit Watchdog Counter Register Table 8-3 Control Registers of GMS81C2020 These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by register operation instruction as " LDM dp,#imm ". 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. 30 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 8.4 Addressing Mode The GMS800 series MCU uses six addressing modes; (3) Direct Page Addressing dp * Register addressing In this mode, a address is specified within direct page. * Immediate addressing Example; G=0 * Direct page addressing C535 LDA ;A RAM[35H] 35H * Absolute addressing * Indexed addressing * Register-indirect addressing 35H data ~ ~ (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. ~ ~ 0E550H C5 0E551H 35 data A (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. (4) Absolute Addressing !abs Example: 0435 ADC Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. #35H MEMORY 04 A+35H+C A 35 ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC ;A ROM[0F035H] !0F035H When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. data 0F035H Example: G=1 E45535 LDM ~ ~ 35H,#55H 0F100H data 0135H 0F100H ~ ~ E4 55 0F102H 35 JUNE. 2001 Ver 1.00 A+data+C A 07 0F101H 35 0F102H F0 address: 0F035 data 55H ~ ~ 0F101H ~ ~ The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag. 31 GMS81C2012/GMS81C2020 983501 INC ;A ROM[135H] !0135H 35H data 135H ~ ~ ~ ~ data ~ ~ ~ ~ data+1 data 0F100H 98 0F101H 35 address: 0135 0F102H 01 data AE A 36H AE X DB X indexed direct page (8 bit offset) dp+X (5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=15H, G=1 Example; G=0, X=0F5H D4 LDA 115H {X} ;ACCRAM[X]. data ~ ~ 45H+X data data A D4 0E550H LDA 3AH ~ ~ C645 ~ ~ ~ ~ 0E550H C6 0E551H 45 data A 45H+0F5H=13AH X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H DB LDA {X}+ Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole area. Example; Y=55H 32 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 D500FA LDA !0FA00H+Y 0F100H D5 0F101H 00 0F102H FA 1625 ADC 35H 05 36H E0 ~ ~ 0E005H ~ ~ ~ ~ 0FA00H+55H=0FA55H ~ ~ [25H+X] 0E005H 25 + X(10) = 35H data ~ ~ data 0FA55H ~ ~ data A 0FA00H 16 25 A + data + C A (6) Indirect Addressing Y indexed indirect [dp]+Y Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. ADC, AND, CMP, EOR, LDA, OR, SBC, STA JMP, CALL Example; G=0, Y=10H Example; G=0 3F35 Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data. JMP 1725 [35H] ADC [25H]+Y 35H 0A 25H 05 36H E3 26H E0 ~ ~ 0E30AH ~ ~ ~ ~ NEXT ~ ~ 0FA00H jump to address 0E30AH 0E015H ~ ~ 3F ~ ~ ~ ~ 0FA00H 35 0E005H + Y(10) = 0E015H data ~ ~ 17 25 A + data + C A X indexed indirect [dp+X] Absolute indirect [!abs] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. The program jumps to address specified by 16-bit absolute address. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0 JMP Example; G=0, X=10H JUNE. 2001 Ver 1.00 33 GMS81C2012/GMS81C2020 1F25E0 JMP [!0C025H] PROGRAM MEMORY 0E025H 25 0E026H E7 ~ ~ 0E725H ~ ~ NEXT ~ ~ 0FA00H jump to address 0E30AH ~ ~ 1F 25 E0 34 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 9. I/O PORTS The GMS81C20xx has eight ports (R0, R1, R2, R3, R4, R5, R6 and R7).These ports pins may be multiplexed with an alternate function for the peripheral features on the device. All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1. All the port direction registers in the GMS81C2020 have 0 written to them by reset function. On the other hand, its initial status is input. WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H R0 data 0C1H R0 direction 0C2H R1 data 0C3H R1 direction 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 BIT I O I O I O I O PORT 7 6 5 4 3 2 1 0 R0 and R0IO register: R0 is an 8-bit high-voltage CMOS bidirectional I/O port (address 0C0H). Each port can be set individually as input and output through the R0IO register (address 0C1H). Each port can directly drive a vacuum fluorescent display. R03 port is multiplexed with Buzzer Output Port(BUZO), R02 port is multiplexed with Event Counter Input Port (EC0), and R01~R00 are multiplexed with External Interrupt Input Port(INT1, INT0) Alternate Function Port Pin R00 R01 R02 R03 INT0 (External interrupt 0 Input Port) INT1 (External interrupt 1 Input Port) EC0 (Event Counter Input Port) BUZO (Buzzer Output Port) .The control register R0FUNC (address F4H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Buzzer Output, External Event Counter Input and External Interrupt Input, write "1" to the corresponding bit of R0FUNC. Regardless of the direction register R0IO, R0FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (BUZO, EC0, INT1, INT0) I : INPUT PORT O : OUTPUT PORT ADDRESS: 0C0H RESET VALUE: Undefined R0 Data Register R0 R07 R06 R05 R04 R03 R02 R01 R00 Figure 9-1 Example of Port I/O Assignment Input / Output data RA(Vdisp) register: RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option. ADDRESS : 0C1H RESET VALUE : 00H R0 Direction Register R0IO ADDRESS: 0FBH RESET VALUE: Undefined RA Data Register RA Port Direction 0: Input 1: Output RA0 Input data ADDRESS : 0F4 R0 Function Selection Register RESET VALUE :H----0000 B R0FUNC Port pin RA Alternate function Vdisp (High-voltage input power supply) JUNE. 2001 Ver 1.00 - - - - 0: R02 1: BUZO 0: R03 1: EC0 3 2 1 0 0: R00 1: INT0 0: R01 1: INT1 35 GMS81C2012/GMS81C2020 R1 and R0IO register: R1 is an 8-bit high-voltage CMOS bidirectional I/O port (address 0C2H). Each port can be set individually as input and output through the R1IO register (address 0C3H). Each port can directly drive a vacuum fluorescent display. R1 Data Register R1 (address 0C7H). ADDRESS: 0C6H RESET VALUE: Undefined R3 Data Register R3 - - R35 R34 R33 R32 R31 R30 Input / Output data ADDRESS: 0C2H RESET VALUE: Undefined R17 R16 R15 R14 R13 R12 R11 R10 ADDRESS : 0C7H RESET VALUE : --000000B R3 Direction Register Input / Output data R1 Direction Register - R3IO - Port Direction 0: Input 1: Output ADDRESS : 0C3H RESET VALUE : 00H R1IO Port Direction 0: Input 1: Output R2 and R2IO register: R2 is an 8-bit high-voltage CMOS bidirectional I/O port (address 0C4H). Each port can be set individually as input and output through the R2IO register (address 0C5H). Each port can directly drive a vacuum fluorescent display. R2 Data Register R2 ADDRESS: 0C4H RESET VALUE: Undefined R27 R26 R25 R24 R23 R22 R21 R20 Input / Output data R2 Direction Register ADDRESS : 0C5H RESET VALUE : 00H R2IO R4 and R4IO register: R4 is a 4-bit bidirectional I/O port (address 0C8H). Each port can be set individually as input and output through the R4IO register (address 0C9H). R40 port is multiplexed with Timer 0 Output Port (T0O). Alternate Function Port Pin R40 T0O (Timer 0 Compare Output Port) The control register R4FUNC (address 0F5H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Timer 0 Output, write "1" to the corresponding bit of R4FUNC. Regardless of the direction register R4IO, R4FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (T0O) ADDRESS: 0C8H RESET VALUE: Undefined R4 Data Register R4 - - - - R43 R42 R41 R40 Port Direction 0: Input 1: Output R3 and R3IO register: R3 is a 6-bit high-voltage CMOS bidirectional I/O port (address 0C6H). Each port can be set individually as input and output through the R3IO register Input / Output data ADDRESS : 0C9H RESET VALUE : ----0000B R4 Direction Register R4IO - - - - Port Direction 0: Input 1: Output ADDRESS : 0F5 R4 Function Selection Register RESET VALUE :H-------0 R4FUNC - - - - - - - B T0O 0: R40 1: T0O 36 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 R5 and R5IO register: R5 is an 8-bit bidirectional I/O port (address 0CAH). Each pin can be set individually as input and output through the R5IO register (address 0CB H).In addition, Port R5 is multiplexed with Pulse Width Modulator (PWM). Alternate Function Port Pin The control register R5FUNC (address 0F6H) controls to select PWM function.After reset, the R5IO register value is "0", port may be used as general I/O ports. To select PWM function, write "1" to the corresponding bit of R5FUNC. The control register R5NODR (address 0F9H) controls to select N-MOS open drain port. To select N-MOS open drain port, write "1" to the corresponding bit of R5FUNC. ADDRESS: 0CAH RESET VALUE: Undefined R5 Data Register R57 R56 R55 R54 R53 R52 R51 R50 Alternate Function Port Pin PWM1 Data Output Timer 1 Data Output R56 R5 R6 and R6IO register: R6 is an 8-bit bidirectional I/O port (address 0CCH). Each port can be set individually as input and output through the R6IO register (address 0CDH). R67~R60 ports are multiplexed with Analog Input Port. R60 R61 R62 R63 R64 R65 R66 R67 AN0 (ADC input 0) AN1 (ADC input 1) AN2 (ADC input 2) AN3 (ADC input 3) AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7) The control register R6FUNC (address 0F7H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input, write "1" to the corresponding bit of R6FUNC. Regardless of the direction register R6IO, R6FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (AN7~AN0) Input / Output data ADDRESS: 0CCH RESET VALUE: Undefined R6 Data Register ADDRESS : 0CBH RESET VALUE : 00H R5 Direction Register R6 R67 R66 R65 R64 R63 R62 R61 R60 R5IO Input / Output data Port Direction 0: Input 1: Output ADDRESS : 0CDH RESET VALUE : 00H R6 Direction Register R6IO R5 Function Selection ADDRESS : 0F6 Register RESET VALUE :H-0-----B R5FUNC - - 6 - - - - Port Direction 0: Input 1: Output - 0: R56 1: PWM1O/T1O ADDRESS : 0F7 R6 Function Selection Register RESET VALUE :H00 R5 N-MOS Open Drain Selection Register H ADDRESS: 0F9H RESET VALUE: 00H R5NODR N-MOS Open Drain Selection 0: Disable 1: Enable JUNE. 2001 Ver 1.00 R6FUNC 7 6 5 0: R67 1: AN7 0: R66 1: AN6 0: R65 1: AN5 0: R64 1: AN4 4 3 2 1 0 0: R60 1: AN0 0: R61 1: AN1 0: R62 1: AN2 0: R63 1: AN3 37 GMS81C2012/GMS81C2020 R7 and R7IO register: R7 is a 4-bit bidirectional I/O port (address 0CEH). Each port can be set individually as input and output through the R7IO register (address 0CFH). R73~R70 ports are multiplexed with Analog Input Port AN8~AN11). R74, R75 ports are alternate function of SXI, SXO ports. R74, R75 ports can be set individually as input and output through the R7IO register. Port Pin Alternate Function R70 R71 R72 R73 SXI SXO AN8 (ADC input 8) AN9 (ADC input 9) AN10 (ADC input 10) AN11 (ADC input 11) R74(included Internal Pull-up Resister) R75(included Internal Pull-up Resister) can be used as a corresponding alternate features. ADDRESS: 0CEH RESET VALUE: Undefined R7 Data Register R7 - - R75 R74 R73 R72 R71 R70 Input / Output data ADDRESS : 0CFH RESET VALUE : --000000B R7 Direction Register R7IO - - Port Direction 0: Input 1: Output ADDRESS : 0F8 The control register R7FUNC (address 0F8H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input, write "1" to the corresponding bit of R7FUNC. Regardless of the direction register R7IO, R7FUNC is selected to use as alternate functions, port pin 38 R7 Function Selection Register RESET VALUE :H----0000 B R7FUNC - - - - 3 2 1 0 0: R70 1: AN8 0: R71 1: AN9 0: R72 1: AN10 0: R73 1: AN11 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 10. BASIC INTERVAL TIMER comes "0" after one machine cycle by hardware. The GMS81C20xx has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 10-1. In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF). If the STOP instruction executed after writing "1" to bit WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the oscillator, prescaler (only fXIN/2048) and Timer0. The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflows from FFH to 00H, this overflow causes to generate the Basic interval timer interrupt. The BITIF is interrupt request flag of Basic interval timer. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 10-2. If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer. Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0ECH is read as a BITR, and written to CKCTLR. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL be- Internal RC OSC WAKEUP STOP /8 /16 Prescaler /32 XIN PIN 1 /64 /128 MUX source clock 8-bit up-counter BITIF BITR /256 Basic Interval Timer Interrupt overflow 0 /512 [0ECH] /1024 To Watchdog timer (WDTCK) clear Select Input clock 3 BTS[2:0] [0ECH] RCWDT BTCL CKCTLR Basic Interval Timer clock control register Read Internal bus line Figure 10-1 Block Diagram of Basic Interval Timer JUNE. 2001 Ver 1.00 39 GMS81C2012/GMS81C2020 CKCTLR [2:0] Interrupt (overflow) Period (ms) @ fXIN = 4MHz Source clock fXIN/8 fXIN/16 fXIN/32 fXIN/64 fXIN/128 fXIN/256 fXIN/512 fXIN/1024 000 001 010 011 100 101 110 111 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536 Table 10-1 Basic Interval Timer Interrupt Time CKCTLR 7 - 6 5 WAKEUP RCWDT 4 WDTON 3 2 1 0 BTCL BTCL BTS2 BTS1 BTS0 ADDRESS: 0ECH INITIAL VALUE: -001 0111B Basic Interval Timer source clock select 000: fXIN / 8 001: fXIN / 16 010: fXIN / 32 011: fXIN / 64 100: fXIN / 128 101: fXIN / 256 110: fXIN / 512 111: fXIN / 1024 Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically after one machine cycle, and starts counting. Caution: Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. 0: Operate as a 7-bit general timer 1: Enable Watchdog Timer operation See the section "Watchdog Timer". 0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer 0: Disable Wake-up Timer 1: Enable Wake-up Timer 7 6 BITR 5 4 3 BTCL 2 1 0 ADDRESS: 0ECH INITIAL VALUE: Undefined 8-BIT FREE-RUN BINARY COUNTER Figure 10-2 BITR: Basic Interval Timer Mode Register Example 1: Example 2: Basic Interval Timer Interrupt request flag is generated every 4.096ms at 4MHz. Basic Interval Timer Interrupt request flag is generated every 1.024ms at 4MHz. : LDM SET1 EI : 40 CKCTLR,#03H BITE : LDM SET1 EI : CKCTLR,#01H BITE JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 11. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the operation to the normal condition. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. LDM LDM STOP NOP NOP : The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for example, by entering the STOP mode. CKCTLR,#3FH; enable the RC-osc WDT WDTR,#0FFH; set the WDT period ; enter the STOP mode ; RC-osc WDT running The RCWDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 40~120uS). The following equation shows the RCWDT oscillated watchdog timer time-out. T R C W D T = C L K R C W D T x28x[W D T R .6~ 0 ]+ (C L K R C W D T x28)/2 The other type is a prescaled system clock. w h ere, C L K R C W D T = 40~ 1 20u S The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON. In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = [WDTR.6~0] x Interval of BIT clear Watchdog Counter (7-bit) BASIC INTERVAL TIMER Count OVERFLOW source clear "0" WDTCL WDTON in CKCTLR [0ECH] 7-bit compare data WDTIF 7 WDTR to reset CPU "1" enable comparator Watchdog Timer interrupt Watchdog Timer Register [0EDH] Internal bus line Figure 11-1 Block Diagram of Watchdog Timer JUNE. 2001 Ver 1.00 41 GMS81C2012/GMS81C2020 Watchdog Timer Control the binary counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (WDTIF) is generated. Figure 11-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time. The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it automatically restarts (continues counting). If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from W 7 WDTR W 6 W 5 W 4 W 3 W 2 W 1 W 0 WDTCL ADDRESS: 0EDH INITIAL VALUE: 0111_1111B 7-bit compare data Clear count flag 0: Free-run count 1: When the WDTCL is set to "1", binary counter is cleared to "0". And the WDTCL becomes "0" automatically after one machine cycle. Counter count up again. NOTE: The WDTON bit is in register CKCTLR. Figure 11-2 WDTR: Watchdog Timer Data Register Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz Within WDT detection time Within WDT detection time 42 LDM LDM CKCTLR,#3FH WDTR,#04FH ;Select 1/2048 clock source, WDTON 1, Clear Counter LDM : : : : LDM : : : : LDM WDTR,#04FH ;Clear counter WDTR,#04FH ;Clear counter WDTR,#04FH ;Clear counter JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 Enable and Disable Watchdog Watchdog Timer Interrupt Watchdog timer is enabled by setting WDTON (bit 4 in CKCTLR) to "1". WDTON is initialized to "0" during reset and it should be set to "1" to operate after reset is released. The watchdog timer can be also used as a simple 7-bit timer by clearing bit5 of CKCTLR to "0". The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below. Example: Enables watchdog timer for Reset : LDM : : T = WDTR x Interval of BIT CKCTLR,#xx1x_xxxxB;WDTON 1 The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source. Example: 7-bit timer interrupt set up. The watchdog timer is disabled by clearing bit 5 (WDTON) of CKCTLR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released. LDM LDM CKCTLR,#xx0xxxxxB;WDTON 0 WDTR,#7FH ;WDTCL 1 : Source clock BIT overflow Binary-counter 2 1 3 0 1 2 3 0 Counter Clear WDTR 3 n Match Detect WDTIF interrupt WDTR "0100_0011B" WDT reset reset Figure 11-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. JUNE. 2001 Ver 1.00 The main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode. 43 GMS81C2012/GMS81C2020 12. TIMER/EVENT COUNTER sponse to a 1-to-0 (falling edge) or 0-to-1(rising edge) transition at its corresponding external input pin, EC0. The GMS81C20xx has two Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). In addition the "capture" function, the register is increased in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into capture data register CDRx. Timer 0 and Timer 1 are can be used either two 8-bit Timer/Counter or one 16-bit Timer/Counter with combine them. In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source (1/1 to 1/8). Timer1 is shared with "PWM" function and "Compare output" function It has seven operating modes: "8-bit timer/counter", "16bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer mode register TM0 and TM1 as shown in Figure 12-1 and Table 12-1. In the "counter" function, the register is increased in re16BIT CAP0 CAP1 PWM1E T0CK [2:0] T1CK [1:0] PWM1O 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture (internal clock) 8-bit Compare Output 0 X 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event counter 1 1 X 0 XXX 11 0 16-bit Capture (internal clock) 1 0 0 0 XXX 11 1 16-bit Compare Output TIMER 0 TIMER 1 Table 12-1 Operating Modes of Timer0 and Timer1 44 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 R/W 5 TM0 - - R/W 3 R/W 2 R/W 1 R/W 0 CA P0 T0Ck2 T0C BTCL K1 T0C k0 T0C N T0ST ADD RES S: 0D0 H INITIAL V ALUE: --000000 B Bit Name Bit Position Description CAP0 TM0.5 0: Timer/Counter mode 1: Capture mode selection flag T0CK2 T0CK1 T0CK0 TM0.4 TM0.3 TM0.2 000: 8-bit Timer, Clock source is fXIN / 2 001: 8-bit Timer, Clock source is fXIN / 4 010: 8-bit Timer, Clock source is fXIN / 8 011: 8-bit Timer, Clock source is fXIN / 32 100: 8-bit Timer, Clock source is fXIN / 128 101: 8-bit Timer, Clock source is fXIN / 512 110: 8-bit Timer, Clock source is fXIN / 2048 111: EC0 (External clock) T0CN TM0.1 0: Stop the timer 1: A logic 1 starts the timer. T0ST TM0.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. R/W 7 TM1 R/W 4 POL R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 16BIT PWM1E CAP1 T1CK1 BTCL T1CK0 T1CN T1ST ADDRESS: 0D2H INITIAL VALUE: 00H Bit Name Bit Position Description POL TM1.7 0: PWM Duty Active Low 1: PWM Duty Active High 16BIT TM1.6 0: 8-bit Mode 1: 16-bit Mode PWMIE TM1.5 0: Disable PWM 1: Enable PWM CAP1 TM1.4 0: Timer/Counter mode 1: Capture mode selection flag T1CK1 T1CK0 TM1.3 TM1.2 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN / 2 10: 8-bit Timer, Clock source is fXIN / 8 11: 8-bit Timer, Clock source is Using the the Timer 0 Clock T0CN TM1.1 0: Stop the timer 1: A logic 1 starts the timer. T0ST TM1.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR1 ADDRESS: 0D1H INITIAL VALUE: Undefined ADDRESS: 0D3H INITIAL VALUE: Undefined Read: Count value read Write: Compare data write Figure 12-1 TM0, TM1 Registers JUNE. 2001 Ver 1.00 45 GMS81C2012/GMS81C2020 12.1 8-bit Timer / Counter Mode as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to "0"(Table 12-1). The GMS81C20xx has two 8-bit Timer/Counters, Timer 0, Timer 1 as shown in Figure 12-2. The "timer" or "counter" function is selected by mode registers TMx as shown in Figure 12-1 and Table 12-1. To use TM0 7 6 - - - - 5 4 3 2 1 0 ADDRESS: 0D0H INITIAL VALUE: --000000B CAP0 T0CK2 BTCL T0CK1 T0CK0 T0CN T0ST 0 X X X X X X means don't care 7 TM1 6 5 4 3 2 1 0 POL 16BIT PWM1E CAP1 BTCL T1CK1 T1CK0 T1CN T1ST X 0 0 0 X X X ADDRESS: 0D2H INITIAL VALUE: 00H X X means don't care T0CK[2:0] EDGE DETECTOR EC0 PIN 111 T0ST /2 000 /4 Prescaler XIN PIN 0: Stop 1: Clear and start 001 /8 010 / T0 (8-bit) clear 011 / 100 /512 /2048 101 T0CN T0IF Comparator TIMER 0 INTERRUPT 110 MUX TIMER 0 TDR0 (8-bit) F/F T0O PIN T1CK[1:0] T1ST /1 /2 /8 0: Stop 1: Clear and start 11 00 T1 (8-bit) 01 clear 10 T1CN T1IF MUX Comparator TIMER 1 TDR1 (8-bit) F/F TIMER 1 INTERRUPT T1O PIN Figure 12-2 8-bit Timer/Counter 0, 1 46 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 Example 1: Timer0 = 2ms 8-bit timer mode at 4MHz Timer1 = 0.5ms 8-bit timer mode at 4MHz LDM LDM LDM LDM SET1 SET1 EI TDR0,#250 TDR1,#250 TM0,#0000_1111B TM1,#0000_1011B T0E T1E Example 2: Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz LDM LDM LDM LDM SET1 SET1 EI TDR0,#250 TDR1,#250 TM0,#0001_1111B TM1,#0000_1011B T0E T1E JUNE. 2001 Ver 1.00 Note: The contents of Timer data register TDRx should be initialized 1H~FFH, not 0H, because it is undefined after reset. These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 selected by control bits T0CK[2:0] of register (TM0) and 1, 2, 8 selected by control bits T1CK[1:0] of register (TM1). In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit). As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. In counter function, the counter is increased every 0-to1(1-to-0) (rising & falling edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the R0 Function Selection Register (R0FUNC.2) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. 47 GMS81C2012/GMS81C2020 8-bit Timer Mode Counting up is resumed after the up-counter is cleared. In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents of up-counter, Tn. If match is found, a timer 1 interrupt (T1IF) is generated and the up-counter is cleared to 0. As the value of TDRn is changeable by software, time interval is set as you want Start count ~ ~ Source clock ~ ~ Up-counter 0 2 1 n-2 3 n-1 n 0 2 1 3 4 ~ ~ TDR1 n ~ ~ Match Detect Counter Clear ~ ~ T1IF interrupt Figure 12-3 Timer Mode Timing Chart Example: Make 2msinterrupt using by Timer0 at 4MHz LDM LDM SET1 EI TM0,#0FH TDR0,#125 T0E ; ; ; ; divide by 32 8us x 125= 1ms Enable Timer 0 Interrupt Enable Master Interrupt When TM0 = 0000 1111B (8-bit Timer mode, Prescaler divide ratio = 32) TDR0 = 125D = 7DH fXIN = 4 MHz 1 INTERRUPT PERIOD = x 32 x 125 = 1 ms 4 x 106 Hz TDR1 MATCH (TDR0 = T0) t un -c o 8 s ~~ ~~ up ~~ 7B 7A 6 Count Pulse Period 7D 7C 7D 5 4 3 2 1 0 0 TIME Interrupt period = 8 s x 125 Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 12-4 Timer Count Example 48 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 8-bit Event Counter Mode In order to use event counter function, the bit 2 of the R5 function register (R5FUNC.2) is required to be set to "1". In this mode, counting up is started by an external trigger. This trigger means falling edge or rising edge of the EC0 pin input. Source clock is used as an internal clock selected with timer mode register TM0. The contents of timer data register TDR0 is compared with the contents of the upcounter T0. If a match is found, an timer interrupt request flag T0IF is generated, and the counter is cleared to "0". The counter is restart and count up continuously by every falling edge or rising edge of the EC0 pin input. After reset, the value of timer data register TDR0 is undefined, it should be initialized to between 1H~FFHnot to "0"The interval period of Timer is calculated as below equation. 1 Period (sec) = ----------- x 2 x Divide Ratio x TDR0 f XIN The maximum frequency applied to the EC0 pin is fXIN/2 [Hz]. Start count ~ ~ ECn pin input ~ ~ 1 0 2 ~ ~ Up-counter n-1 n 1 0 2 ~ ~ n ~ ~ TDR1 ~ ~ T1IF interrupt Figure 12-5 Event Counter Mode Timing Chart TDR1 disable ~~ clear & start enable up - co u nt stop ~~ TIME Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt T1ST Start & Stop T1ST = 1 T1ST = 0 T1CN Control count T1CN = 1 T1CN = 0 Figure 12-6 Count Operation of Timer / Event counter JUNE. 2001 Ver 1.00 49 GMS81C2012/GMS81C2020 12.2 16-bit Timer / Counter Mode The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000H until it matches TDR0, TDR1 and then resets to 0000 H . The match output generates Timer 0 interrupt not Timer 1 interrupt. 7 6 - - - - TM0 5 4 3 In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively. 2 1 0 ADDRESS: 0D0H INITIAL VALUE: --000000B CAP0 T0CK2 BTCL T0CK1 T0CK0 T0CN T0ST 0 X X X X X X means don't care 7 TM1 6 5 4 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H POL 16BIT PWM1E CAP1 BTCL T1CK1 T1CK0 T1CN T1ST X 1 0 0 1 1 X X X means don't care T0CK[2:0] EDGE DETECTOR EC0 PIN 111 /2 /4 Prescaler XIN PIN /8 / / /512 /2048 T0ST 0: Stop 1: Clear and start 000 001 0 010 1 011 100 T1 + T0 (16-bit) clear T0CN 101 T0IF Comparator 110 TDR1 + TDR0 (16-bit) MUX F/F TIMER 0 INTERRUPT (Not Timer 1 interrupt) T0O PIN Higher byte Lower byte COMPARE DATA TIMER 0 + TIMER 1 TIMER 0 (16-bit) Figure 12-7 16-bit Timer/Counter 50 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 12.3 8-bit Compare Output (16-bit) The GMS81C20xx has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(T0O, T1O) as shown in Figure 12-2 and Figure 12-7. Thus, pulse out is generated by the timer match. These operation is implemented to pin, T0O, PWM1O/T1O. In this mode, the bit PWM1O/T1O of R5 function register (R5FUNC.6) should be set to "1", and the bit PWM1E of timer1 mode register (TM1) should be set to "0". In addi- tion, 16-bit Compare output mode is available, also. This pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. Oscillation Frequency f COMP = --------------------------------------------------------------------------------2 x Prescaler Value x ( TDR + 1 ) 12.4 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 12-8. As mentioned above, not only Timer 0 but Timer 1 can also be used as a capture mode. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 12-10, the pulse width of captured signal is wider than the timer data value (FFH) over 2 times. When external interrupt is occurred, the captured value (13H) is more little than wanted value. It can be ob- JUNE. 2001 Ver 1.00 tained correct value by counting the number of timer overflow occurrence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be captured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware. Note: The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt. 51 GMS81C2012/GMS81C2020 . TM0 7 6 - - - - 5 4 3 2 1 0 ADDRESS: 0D0H INITIAL VALUE: --000000B CAP0 T0CK2 BTCL T0CK1T0CK0 T0CN T0ST 1 X X X X X X means don't care 7 TM1 6 5 4 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H POL 16BIT PWM1E CAP1 BTCL T1CK1T1CK0 T1CN T1ST X 0 0 1 X X X X X means don't care T0CK[2:0] Edge Detector EC0 PIN 111 T0ST /2 000 /4 Prescaler XIN PIN 0: Stop 1: Clear and start 001 /8 T0 (8-bit) 010 / 011 / clear 100 /512 /2048 T0CN 101 Capture 110 CDR0 (8-bit) MUX IEDS[1:0] "01" "10" INT0 PIN INT0IF T1CK[1:0] INT0 INTERRUPT "11" T1ST /1 /2 /8 0: Stop 1: Clear and start 11 00 T1 (8-bit) 01 clear 10 MUX T1CN Capture CDR1 (8-bit) IEDS[1:0] "01" INT1 PIN "10" INT1IF INT1 INTERRUPT "11" Figure 12-8 8-bit Capture Mode 52 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 This value is loaded to CDR0 n T0 n-1 nt ou ~~ ~~ 9 up -c 8 7 6 5 4 ~~ 3 2 1 0 TIME Ext. INT0 Pin Interrupt Request ( INT0F ) Interrupt Interval Period Ext. INT0 Pin Interrupt Request ( INT0F ) Delay Capture ( Timer Stop ) Clear & Start Figure 12-9 Input Capture Operation Ext. INT0 Pin Interrupt Request ( INT0F ) Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H Interrupt Request ( T0F ) FFH FFH T0 13H 00H 00H Figure 12-10 Excess Timer Overflow in Capture Mode JUNE. 2001 Ver 1.00 53 GMS81C2012/GMS81C2020 12.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. or external clock by bit T0CK2, T0CK1 and T0CK0. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively. The clock source of the Timer 0 is selected either internal TM0 7 6 - - - - 5 4 3 2 1 0 ADDRESS: 0D0H INITIAL VALUE: --000000B CAP0 T0CK2 BTCL T0CK1 T0CK0 T0CN T0ST 1 X X X X X X means don't care 7 TM1 6 5 4 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00 H POL 16BIT PWM1E CAP1 BTCL T1CK1 T1CK0 T1CN T1ST X 1 0 X 1 1 X X X means don't care T0CK[2:0] Edge Detector EC0 PIN 111 T0ST /2 /4 Prescaler XIN PIN /8 / / /512 /2048 0: Stop 1: Clear and start 000 001 TDR1 + TDR0 (16-bit) 010 011 100 clear T0CN 101 Capture 110 CDR1 + CDR0 (16-bit) MUX IEDS[1:0] Higher byte Lower byte CAPTURE DATA "01" INT0 PIN "10" INT0IF INT0 INTERRUPT "11" Figure 12-11 16-bit Capture Mode 54 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 Example 1: Example 3: Timer0 = 16-bit timer mode, 0.5s at 4MHz Timer0 = 16-bit capture mode LDM LDM LDM LDM SET1 EI : : TM0,#0000_1111B;8uS TM1,#0100_1100B;16bit Mode TDR0,#<62500 ;8uS X 62500 TDR1,#>62500 ;=0.5s T0E LDM LDM LDM LDM LDM LDM SET1 EI : : Example 2: R0FUNC,#0000_0001B;INT0 set TM0,#0010_1111B;Capture Mode TM1,#0100_1100B;16bit Mode TDR0,#<0FFH ; TDR1,#>0FFH ; IEDS,#01H;Falling Edge T0E Timer0 = 16-bit event counter mode LDM LDM LDM LDM LDM SET1 EI : : R0FUNC,#0000_0100B;EC0 Set TM0,#0001_1111B;Counter Mode TM1,#0100_1100B;16bit Mode TDR0,#<0FFH ; TDR1,#>0FFH ; T0E 12.6 PWM Mode The GMS81C2020 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1. And writes duty value to the T1PDR and the PWM1HR[1:0] same way. In PWM mode, pin R56/PWM1O/T1O outputs up to a 10bit resolution PWM output. This pin should be configured as a PWM output by setting "1" bit PWM1O in R5FUNC.6 register. The T1PDR is configured as a double buffering for glitchless PWM output. In Figure 12-12, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) The period of the PWM output is determined by the T1PPR (PWM1 Period Register) and PWM1HR[3:2] (bit3,2 of PWM1 High Register) and the duty of the PWM output is determined by the T1PDR (PWM1 Duty Register) and PWM1HR[1:0] (bit1,0 of PWM1 High Register). The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM1HR[3:2]. JUNE. 2001 Ver 1.00 PWM Period = [PWM1HR[3:2]T1PPR] X Source Clock PWM Duty = [PWM1HR[1:0]T1PDR] X Source Clock The relation of frequency and resolution is in inverse proportion. Table 12-2 shows the relation of PWM frequency vs. resolution. 55 GMS81C2012/GMS81C2020 If it needed more higher frequency of PWM, it should be reduced resolution. The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High). Frequency Resolution T1CK[1:0] = 00(250nS) T1CK[1:0] = 01(500nS) T1CK[1:0] = 10(2uS) 10-bit 3.9KHz 0.98KHZ 0.49KHZ 9-bit 7.8KHz 1.95KHz 0.97KHz 8-bit 15.6KHz 3.90KHz 1.95KHz 7-bit 31.2KHz 7.81KHz 3.90KHz It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 12-14. As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value. Table 12-2 PWM Frequency vs. Resolution at 4MHz TM1 PWM1HR POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 1 0 X X X X - - - - - - - - ADDRESS : D5H RESET VALUE : ----0000 Bit Manipulation Not Available PWM1HR3PWM1HR2PWM1HR1PWM1HR0 X X X Period High T1ST X Duty High X : The value "0" or "1" corresponding your operation. PWM1HR[3:2] T0 clock source [T0CK] ADDRESS : D2H RESET VALUE : 00000000 T1PPR(8-bit) 0 : Stop 1 : Clear and Start R56/ PWM1O/T1O COMPARATOR S Q CLEAR 1 fXI /1 /2 /8 (2-bit) MUX R T1 ( 8-bit ) POL PWM1O [R5FUNC.6] COMPARATOR T1CK[1:0] T1CN Slave T1PDR(8-bit) PWM1HR[1:0] Master T1PDR(8-bit) Figure 12-12 PWM Mode 56 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 02 03 04 05 PWM1E 7F 80 ~ ~ ~ ~ 00 01 ~ ~ ~ ~ ~ ~ T1 ~ ~ ~ ~ Source clock 81 3FF 00 01 02 03 ~ ~ T1ST ~ ~ T1CN ~ ~ ~ ~ ~ ~ PWM1O [POL=1] ~ ~ PWM1O [POL=0] Duty Cycle [ 80H x 250nS = 32uS ] Period Cycle [ 3FFH x 250nS = 255.75uS, 3.9KHz ] T1CK[1:0] = 00 ( fXI ) PWM1HR = 0CH Period PWM1HR3 PWM1HR2 1 T1PPR (8-bit) 1 FFH T1PPR = FFH T1PDR = 80H Duty PWM1HR1 PWM1HR0 0 T1PDR (8-bit) 0 80H Figure 12-13 Example of PWM at 4MHz T 1 C K [1:0 ] = 10 ( 1 u S ) P W M 1 H R = 0 0H T1PPR = 0EH Write T1PPR to 0AH T 1 P D R = 0 5H Period changed Source clock T1 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05 PWM1O POL=1 Duty Cycle [ 05H x 2uS = 10uS ] Period Cycle [ 0EH x 2uS = 28uS, 35.5KHz ] Duty Cycle [ 05H x 2uS = 10uS ] Duty Cycle [ 05H x 2uS = 10uS ] Period Cycle [ 0AH x 2uS = 20uS, 50KHz ] Figure 12-14 Example of Changing the Period in Absolute Duty Cycle (@4MHz) JUNE. 2001 Ver 1.00 57 GMS81C2012/GMS81C2020 13. ANALOG DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AVDD of ladder resistance of A/D module. The A/D module has two registers which are the control register ADCM and A/D result register ADR. The register ADCM, shown in Figure 13-1, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in R6FUNC register. Also it is assigned analog input port by setting the bit AN- ADCM 7 - R/W 5 How to Use A/D Converter The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 13-2. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 20 uS (at fXI=4 MHz) R/W R/W R/W R 3 2 1 0 ADS1 ADS0 ADST ADSF ADEN ADS3 ADS2 BTCL 6 R/W 4 SEL[11:8] in R7FUNC register. And selected the corresponding channel to be converted by setting ADS[3:0]. ADDRESS: 0EAH INITIAL VALUE: -000 0001B A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to "0" by hardware. Analog input channel select 0000: Channel 0 (AN0) 0001: Channel 1 (AN1) 0010: Channel 2 (AN2) 0011: Channel 3 (AN3) 0100: Channel 4 (AN4) 0101: Channel 5 (AN5) 0110: Channel 6 (AN6) 0111: Channel 7 (AN7) 1000: Channel 8 (AN8) 1001: Channel 9 (AN9) 1010: Channel 10 (AN10) 1011: Channel 11 (AN11) A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter R 7 ADCR R 6 R 5 R 4 R 3 BTCL R 2 R 1 R 0 ADDRESS: 0EBH INITIAL VALUE: Undefined A/D Conversion Data Figure 13-1 A/D Converter Control Register 58 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 . R6FUNC[7:0] ADS[3:0] 0000 R60/AN0 ANSEL0 0001 R61/AN1 "0" ANSEL1 0010 R62/AN2 "1" AVDD ADEN ANSEL2 0011 R63/AN3 ANSEL3 0100 R64/AN4 LADDER RESISTOR ANSEL4 0101 R65/AN5 8-bit DAC ANSEL5 0110 R66/AN6 ANSEL6 0111 R67/AN7 S/H SUCCESSIVE APPROXIMATION CIRCUIT A/D INTERRUPT ADIF Sample & Hold ANSEL7 ADR (8-bit) R7FUNC[3:0] ADDRESS: E9H RESET VALUE: Undefined A/D result register 1000 R70/AN8 ANSEL8 1001 R71/AN9 ANSEL9 1010 R72/AN10 ANSEL10 1011 R73/AN11 ANSEL11 Figure 13-2 A/D Block Diagram JUNE. 2001 Ver 1.00 59 GMS81C2012/GMS81C2020 (2) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVDD and AN11 to AN0. Since the effect in- ENABLE A/D CONVERTER creases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 13-4 in order to reduce noise. A/D INPUT CHANNEL SELECT Analog Input ANALOG REFERENCE SELECT AN11~AN0 100~1000pF A/D START ( ADST = 1 ) Figure 13-4 Analog Input Pin Connecting Capacitor (3) Pins AN11/R73 to AN8/R70 and AN7/R67 to AN0/ R60 NOP ADSF = 1 NO YES READ ADCR Figure 13-3 A/D Converter Operation Flow A/D Converter Cautions (1) Input range of AN11 to AN0 The input voltage of AN11 to AN0 should be within the specification range. In particular, if a voltage above AVDD or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. 60 The analog input pins AN11 to AN0 also function as input/ output port (PORT R7 and R6) pins. When A/D conversion is performed with any of pins AN11 to AN0 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AVDD pin input impedance A series resistor string of approximately 10K is connected between the AVDD pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large reference voltage error. JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 14. SERIAL PERIPHERAL INTERFACE clock synchronous type and consists of serial I/O register, serial I/O mode register, clock selection circuit octal counter and control circuit. The SOUT pin is designed to input and output. So Serial Peripheral Interface(SPI) can be operated with minimum two pin The Serial Peripheral Interface (SPI) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The Serial Peripheral Interface(SPI) is 8-bit SIOST SIOSF Start Complete XIN PIN Prescaler SCK[1:0] /4 / 16 Timer0 Overflow POL 00 01 "0" 10 "1" Clock SPI CONTROL CIRCUIT Clock 11 "11" SCLK PIN overflow Octal Counter SIOIF Serial communication Interrupt MUX not "11" SCK[1:0] SOUT PIN IOSWIN IOSW SOUT IOSWIN 1 Input shift register SIN PIN 0 Shift SIOR Internal Bus Figure 14-1 SPI Block Diagram JUNE. 2001 Ver 1.00 61 GMS81C2012/GMS81C2020 Serial I/O Mode Register(SIOM) controls serial I/O function. According to SCK1 and SCK0, the internal clock or external clock can be selected. The serial transmission operation mode is decided by setting the SM1 and SM0, and the polarity of transfer clock is selected by setting the POL. Serial I/O Data Register(SIOR) is a 8-bit shift register. First LSB is send or is received. When receiving mode, serial input pin is selected by IOSW. The SPI allows 8-bits of data to be synchronously transmitted and received. R/W 7 SIOM R/W 6 POL IOSW R/W 5 SM1 R/W 4 To accomplish communication, typically three pins are used: - Serial Data In - Serial Data Out - Serial Clock R54/SIN R55/SOUT R53/SCLK . R/W R/W R/W R 3 2 1 0 SCK1 SCK0 SIOST SIOSF SM0 BTCL ADDRESS: 0E0H INITIAL VALUE: 0000 0001B Serial transmission status bit 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to "0" by hardware. Serial transmission Clock selection 00: fXIN / 4 01: fXIN / 16 10: TMR0OV(Timer0 Overflow) 11: External Clock Serial transmission Operation Mode 00: Normal Port(R55,R54,R53) 01: Sending Mode(SOUT,R54,SCLK) 10: Receiving Mode(R55,SIN,SCLK) 11: Sending & Receiving Mode(SOUT,SIN,SCLK) Serial Input Pin Selection bit 0: SIN Pin Selection 1: IOSWIN Pin Selection Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge Received Data Latch at Falling Edge SIOR R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BTCL ADDRESS: 0E1H INITIAL VALUE: Undefined Sending Data at Sending Mode Receiving Data at Receiving Mode Figure 14-2 SPI Control Register 62 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 14.1 Transmission/Receiving Timing is latched at rising edge of SCLK pin. When transmission clock is counted 8 times, serial I/O counter is cleared as `0". Transmission clock is halted in "H" state and serial I/ O interrupt(IFSIO) occurred. The serial transmission is started by setting SIOST(bit1 of SIOM) to "1". After one cycle of SCK, SIOST is cleared automatically to "0". The serial output data from 8-bit shift register is output at falling edge of SCLK. And input data SIOST SCLK [R53] (POL=0) SOUT [R55] D0 D1 D2 D3 D4 D5 D6 D7 SIN [R54] (IOSW=0) D0 D1 D2 D3 D4 D5 D6 D7 IOSWIN [R55] (IOSW=1) D0 D1 D2 D3 D4 D5 D6 D7 SIOSF (SPI Status) SPIIF (SPI Int. Req) Figure 14-3 SPI Timing Diagram at POL=0 SIOST SCLK [R53] (POL=1) SOUT [R55] D0 D1 D2 D3 D4 D5 D6 D7 SIN [R54] (IOSW=0) D0 D1 D2 D3 D4 D5 D6 D7 IOSWIN [R55] (IOSW=1) D0 D1 D2 D3 D4 D5 D6 D7 SIOSF (SPI Status) SPIIF (SPI Int. Req) Figure 14-4 SPI Timing Diagram at POL=1 JUNE. 2001 Ver 1.00 63 GMS81C2012/GMS81C2020 14.2 The method of Serial I/O Select transmission/receiving mode The SIO interrupt is generated at the completion of SIO and SIOSF is set to "1". In SIO interrupt service routine, correct transmission should be tested. Note: When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. In case of receiving mode, the received data is acquired by reading the SIOR. In case of sending mode, write data to be send to SIOR. Set SIOST to "1" to start serial transmission. Note: If both transmission mode is selected and transmission is performed simultaneously it would be made error. 14.3 The Method to Test Correct Transmission Serial I/O Interrupt Service Routine SIOSF 0 1 Abnormal SE = 0 Write SIOM SR 0 1 Normal Operation Overrun Error - SE : Interrupt Enable Register Low IENL(Bit3) - SR : Interrupt Request Flag Register Low IRQL(Bit3) Figure 14-5 Serial Method to Test Transmission 64 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 15. BUZZER FUNCTION The buzzer driver block consists of 6-bit binary counter, buzzer register BUR, and clock source selector. It generates square-wave which has very wide range frequency (480Hz ~ 250kHz at fXIN= 4MHz) by user software. The bit 0 to 5 of BUR determines output frequency for buzzer driving. A 50% duty pulse can be output to R03/BUZO pin to use for piezo-electric buzzer drive. Pin R03 is assigned for output f XIN f BUZ = ---------------------------------------------------------------------------2 x DivideRatio x ( BUR + 1 ) Equation of frequency calculation is shown below. port of Buzzer driver by setting the bit 3 of R0FUNC(address 0F4H) to "1". At this time, the pin R03 must be defined as fBUZ: Buzzer frequency output mode (the bit 3 of R0IO=1). fXIN: Oscillator frequency Example: 5kHz output at 4MHz. Divide Ratio: Prescaler divide ratio by BUCK[1:0] BUR: Lower 6-bit value of BUR. Buzzer period value. LDM LDM R0IO,#XXXX_1XXXB BUR,#0011_0010B LDM R0FUNC,#XXXX_1XXXB The frequency of output signal is controlled by the buzzer control register BUR.The bit 0 to bit 5 of BUR determine output frequency for buzzer driving. X means don't care R03 port data 6-bit binary /8 Prescaler XIN PIN 00 /16 6-BIT COUNTER 01 /32 /64 0 /2 10 R03/BUZO PIN 1 F/F 11 Comparator MUX 2 Compare data 3 6 R0FUNC Port selection BUR [0F4H] [0DEH] Internal bus line Figure 15-1 Block Diagram of Buzzer Driver ADDRESS : 0F4H RESET VALUE : ---- 0000B W R0FUNC - - - - BUZO W W EC0 INT1 ADDRESS: 0DEH RESET VALUE: Undefined W INT0 W BUR W W W W W W W BUCK1 BUCK0 BUR[5:0] Buzzer Period Data R03/BUZO Selection 0: R03 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) Source clock select 00: / 8 01: / 16 10: / 32 11: / 64 Figure 15-2 R0FUNC and Buzzer Register JUNE. 2001 Ver 1.00 65 GMS81C2012/GMS81C2020 Note: BUR is undefined after reset, so it must be initialized to between 1H and 3FH by software. Note that BUR is a write-only register. The 6-bit counter is cleared and starts the counting by writing signal at BUR register. It is incremental from 00H until it matches 6-bit BUR value. When main-frequency is 4MHz, buzzer frequency is shown as below table. BUR [5:0] 66 BUR[7:6] 00 01 10 11 BUR [5:0] BUR[7:6] 00 01 10 11 00 01 02 03 04 05 06 07 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 20 21 22 23 24 25 26 27 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 08 09 0A 0B 0C 0D 0E 0F 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 28 29 2A 2B 2C 2D 2E 2F 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 10 11 12 13 14 15 16 17 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 30 31 32 33 34 35 36 37 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 18 19 1A 1B 1C 1D 1E 1F 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 38 39 3A 3B 3C 3D 3E 3F 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 16. INTERRUPTS register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. Below table shows the Interrupt priority. The GMS81C20xx interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag ("I" flag of PSW). Nine interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 16-2. The External Interrupts INT0 and INT1 each can be transition-activated (1-to-0 or 0-to-1 transition) by selection IEDS. The flags that actually generate these interrupts are bit INT0F and INT1F in register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 ~ Timer 1 Interrupts are generated by TxIF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Watchdog timer Interrupt is generated by WDTIF which set by a match in Watchdog timer register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer counter register. R/W R/W INT0IF INT1IF Symbol Priority Hardware Reset External Interrupt 0 External Interrupt 1 Timer/Counter 0 Timer/Counter 1 ADC Interrupt Watchdog Timer Basic Interval Timer Serial Communication RESET INT0 INT1 TIMER0 TIMER1 ADC WDT BIT SCI 1 2 3 4 5 6 7 8 Vector addresses are shown in Figure 8-6 on page 24. Interrupt enable registers are shown in Figure 16-3. These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on page 22), the interrupt enable IRQH Reset/Interrupt R/W R/W - - - - T0IF T1IF - - - - ADDRESS: 0E4H INITIAL VALUE: 0000 ----B LSB MSB Timer/Counter 1 interrupt request flag Timer/Counter 0 interrupt request flag External interrupt 1 request flag External interrupt 0 request flag R/W IRQL ADIF MSB R/W R/W - - - - WDTIF BITIF SPIF - - - - R/W ADDRESS: 0E5H INITIAL VALUE: 0000 ----B LSB Serial Communication interrupt request flag Basic Interval imer interrupt request flag Watchdog timer interrupt request flag A/D Conver interrupt request flag Figure 16-1 Interrupt Request Flag JUNE. 2001 Ver 1.00 67 GMS81C2012/GMS81C2020 . Internal bus line [0E2H] Interrupt Enable Register (Higher byte) IENH IRQH [0E4H] INT0 INT0IF INT1 INT1IF Timer 0 T0IF Timer 1 T1IF I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware. Priority Control Release STOP To CPU I-flag Interrupt Master Enable Flag IRQL [0E5H] A/D Converter ADIF Watchdog Timer Interrupt Vector Address Generator WDTIF BIT BITIF Serial Communication SIOIF [0E3H] IENL Interrupt Enable Register (Lower byte) Internal bus line Figure 16-2 Block Diagram of Interrupt IENH R/W R/W R/W R/W - - - - INT0E INT1E T0E T1E - - - - MSB ADDRESS: 0E2H INITIAL VALUE: 0000 ----B LSB Timer/Counter 1 interrupt enable flag Timer/Counter 0 interrupt enable flag External interrupt 1 enable flag External interrupt 0 enable flag IENL R/W R/W R/W R/W - - - - ADE WDTE BITE SPIE - - - - MSB VALUE 0: Disable 1: Enable ADDRESS: 0E3H INITIAL VALUE: 0000 ----B LSB Serial Communication interrupt enable flag Basic Interval imer interrupt enable flag Watchdog timer interrupt enable flag A/D Convert interrupt enable flag Figure 16-3 Interrupt Enable Flag 68 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 16.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fXIN (2 s at fMAIN=4.19MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. System clock Instruction Fetch SP Address Bus PC Data Bus Not used SP-1 PCH PCL SP-2 PSW V.L. V.L. ADL V.H. ADH New PC OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 16-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Basic Interval Timer Vector Table Address 0FFE6H 0FFE7H 012H 0E3H Entry Address 0E312H 0E313H When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. 0EH 2EH Saving/Restoring General-purpose Register Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. JUNE. 2001 Ver 1.00 During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory 69 GMS81C2012/GMS81C2020 area for saving registers. 16.2 BRK Interrupt The following method is used to save/restore the generalpurpose registers. Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Example: Register save using push and pop instructions Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. INTxx: PUSH PUSH PUSH A X Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. Each processing step is determined by B-flag as shown in Figure 16-5. interrupt processing POP POP POP RETI Y X A ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN =0 General-purpose register save/restore using push and pop instructions; main task acceptance of interrupt B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE TCALL0 ROUTINE RETI RET interrupt service task saving registers restoring registers Figure 16-5 Execution of BRK/TCALL0 interrupt return 70 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 16.3 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. Main Program service TIMER 1 service enable INT0 disable other INT0 service EI Occur TIMER1 interrupt However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Occur INT0 enable INT0 enable other TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI A X Y IENH,#80H IENL,#0 ;Enable INT0 only ;Disable other ;Enable Interrupt IENH,#0F0H ;Enable all interrupts IENL,#0F0H Y X A In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine. Figure 16-6 Execution of Multi Interrupt JUNE. 2001 Ver 1.00 71 GMS81C2012/GMS81C2020 16.4 External Interrupt The external interrupt on INT0 and INT1 pins are edge triggered depending on the edge selection register IEDS (address 0F8H) as shown in Figure 16-7. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. INT1 pin INT1IF INT1 INTERRUPT INT0 pin Example: To use as an INT0 and INT1 : : ;**** Set port as an input port R00,R01 LDM R0IO,#1111_1100B ; ;**** Set port as an interrupt port LDM R0FUNC,#0000_0011B ; ;**** Set Falling-edge Detection LDM IEDS,#0000_0101B : : : INT0IF Response Time INT0 INTERRUPT 2 IEDS 2 Edge selection Register [0E6H] Figure 16-7 External Interrupt Block Diagram INT0 and INT1 are multiplexed with general I/O ports (R00 and R01). To use as an external interrupt pin, the bit of R4 port mode register R0FUNC should be set to "1" correspondingly. max. 12 fXIN Interrupt Interrupt goes latched active The INT0 and INT1 edge are latched into INT0IF and INT1IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 16-8shows interrupt response timings. 8 fXIN Interrupt processing Interrupt routine Figure 16-8 Interrupt Response Timing Diagram 72 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 W W W W - - - - R0FUNC W W BUZO BTCL EC0 W W INT1 INT0 MSB ADDRESS: 0F4H INITIAL VALUE: ---- 0000B LSB 0: R00 1: INT0 0: R01 1: INT1 0: R02 1: EC0 0: R03 1: BUZO MSB R/W IEDS - - - - R/W R/W LSB R/W BTCL IED1L IED0H IED0L IED1H INT1 ADDRESS: 0E6H INITIAL VALUE: ---- 0000B INT0 Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) Figure 16-9 R0FUNC and IEDS Registers JUNE. 2001 Ver 1.00 73 GMS81C2012/GMS81C2020 17. Power Saving Mode For applications where power consumption is a critical factor, device provides four kinds of power saving functions, STOP mode, Sub-active mode and Wake-up Timer Peripheral STOP Mode mode (Stand-by mode, Watch mode). Table 17-1 shows the status of each Power Saving Mode. Wake-up Timer Mode Sub-active Mode Stand-by Mode Watch Mode RAM Retain Retain Retain Retain Control Registers Retain Retain Retain Retain I/O Ports Retain Retain Retain Retain CPU Stop Operation Stop Stop Timer0 Stop Operation Operation Operation Oscillation Stop Stop Oscillation Stop Sub Oscillation Stop Oscillation Stop Oscillation Prescaler Stop Operation / 2048 only / 2048 only Entering Condition [WAKEUP] 0 0 1 1 Table 17-1 Power Saving Mode The power saving function is activated by execution of STOP instruction and by execution of STOP instruction after setting the corresponding status (WAKEUP) of Release Source STOP Mode CKCTLR. We shows the release sources from each Power Saving Mode Wake-up Timer Mode Sub-active Mode Stand-by Mode Watch Mode RESET O O O O RCWDT O O O O O O O O X X O O EXT.INT0 EXT.INT1 Timer0 Table 17-2 Release Sources from Power Saving Mode 74 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 17.1 Operating Mode SUB-ACTIVE Mode SCMR.1 = 1 SCMR.0 = 0/1 fXI : Main clock frequency fSXI : sub clock frequency fSYS : fXI,fXI/4,fXI/8,fXI/32 fSUB : fSXI,fSXI/4,fSXI/8,fSXI/32 cpu : system clock tmr : timer0 clock peri : peripheral clock fXI : stop fSXI : oscillation cpu : fSUB tmr : fSUB peri : fSUB CKCTLR[10] + STOP CKCTLR = CKCTLR[6:5] SCMR.0 = 0 + SCMR.1 = 0 STANDBY Mode CKCTLR[10] + STOP SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : stop tmr : ps11(fXI) peri : stop TIMER0 EXT_INT RESET RC_WDT TIMER0 EXT_INT RESET RC_WDT SCMR.1 = 1 ACTIVE Mode WATCH Mode SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : fSYS tmr : fSYS peri : fSYS SCMR.1 = 1 fXI : stop fSXI : oscillation cpu : stop tmr : ps11(fSXI) peri : stop CKCTLR[00] + STOP EXT_INT RESET RC_WDT STOP Mode SCMR.2 = 1 (SUB_CLK OFF) CKCTLR[00] + STOP EXT_INT RESET RC_WDT fXI : stop fSXI : stop cpu : stop tmr : stop peri : stop System Clock Mode Register SCMR CS[1:0] - - CS1 CS0 SUBON CLKSEL MAINOFF ADDRESS : FAH RESET VALUE : ---00000 Clock selection enable bits 00 : fXI 10 : fXI / 8 CLKSEL Clock selection bit 0 : Main clock selection 1 : Sub clock selection Sub clock control bit 0: Off sub clock 1: On sub clock MAINOFF Main clock control bit 0: On main clock 1: Off main clock 01 : fXI / 4 SUBON - JUNE. 2001 Ver 1.00 11 : fXI / 32 75 GMS81C2012/GMS81C2020 17.2 Stop Mode In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up. * The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. * The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode. The Stop mode is activated by execution of STOP instruction after clearing the bit WAKEUP of CKCTLR to "0". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. Release the STOP mode The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 17-1) When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 17-2 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure . STOP INSTRUCTION STOP Mode The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM CKCTLR,#0000_1110B STOP NOP NOP Interrupt Request Corresponding Interrupt Enable Bit (IENH, IENL) =1 STOP Mode Release Master Interrupt Enable Bit PSW[2] In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. 76 =0 IEXX I-FLAG =0 =1 Interrupt Service Routine Next INSTRUCTION Figure 17-1 STOP Releasing Flow by Interrupts JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 . ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) ~ ~ ~ ~ Internal Clock ~ ~ STOP Instruction Executed n+1 n+2 n+3 0 1 ~ ~ ~ ~ n ~ ~ ~ ~ BIT Counter ~ ~ External Interrupt FE FF 0 1 2 Clear Normal Operation Stop Operation tST > 20ms by software Normal Operation Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms. Figure 17-2 STOP Mode Release Timing by External Interrupt STOP Mode ~ ~ ~~ ~ ~ ~ ~ Oscillator (XI pin) ~ ~ ~ ~ ~ ~ Internal Clock RESETB ~ ~ Internal RESETB ~ ~ STOP Instruction Execution Time can not be control by software Stabilization Time tST = 64mS @4MHz Figure 17-3 Timing of STOP Mode Release by RESET 17.3 Wake-up Timer Mode In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler(only 2048 divided ratio) and Timer0, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to "1". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) struction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP In addition, the clock source of timer0 should be selected to 2048 divided ratio. Otherwise, the wake-up function can not work. And the timer0 can be operated as 16-bit timer with timer1. (refer to timer function)The period of wakeup function is varied by setting the timer data register 0, TDR0. Note: After STOP instruction, at least two or more NOP in- JUNE. 2001 Ver 1.00 77 GMS81C2012/GMS81C2020 Release the Wake-up Timer mode The exit from Wake-up Timer mode is hardware reset, Timer0 overflow or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts and Timer0 overflow allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I- When exit from Wake-up Timer mode by external interrupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 17-4. ~ ~ ~ ~ ~ ~ Oscillator (XI pin) CPU Clock STOP Instruction Execution ~ ~ Interrupt Request flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 17-1) Normal Operation Wake-up Timer Mode ( stop the CPU clock ) Normal Operation Do not need Stabilization Time Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt 17.4 Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP and RCWDT of CKCTLR to " 01 ". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) Note: Caution: After STOP instruction, at least two or more NOP instruction should be written LDM WDTR,#1111_1111B Ex) LDM CKCTLR,#0010_1110B STOP NOP NOP The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM 78 and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine.(Figure 17-5) However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal RESET signal and execute the reset processing. (Figure 17-6) If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 17-1) When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 17-5 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 17-6. JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 ~ ~ ~ ~ ~ ~ Oscillator (XI pin) Internal RC Clock ~ ~ ~ ~ Internal Clock ~ ~ External Interrupt ( or WDT Interrupt ) ~ ~ Clear Basic Interval Timer STOP Instruction Execution ~ ~ BIT Counter N-2 N-1 N N+1 N+2 00 01 FE FF 00 00 ~ ~ Normal Operation Stabilization Time tST > 20mS RCWDT Mode Normal Operation Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt RCWDT Mode ~ ~ ~ ~ ~ ~ Oscillator (XI pin) Internal RC Clock ~ ~ ~ ~ Internal Clock ~ ~ ~ ~ RESET RESET by WDT ~ ~ ~ ~ Internal RESET STOP Instruction Execution Time can not be control by software Stabilization Time tST = 64mS @4MHz Figure 17-6 Internal RCWDT Mode Releasing by RESET 17.5 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Note: In the STOP operation, the power dissipation asso- JUNE. 2001 Ver 1.00 ciated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher 79 GMS81C2012/GMS81C2020 than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. It should be set properly in order that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if unfirmed voltage level (not VSSor VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. VDD INPUT PIN INPUT PIN VDD VDD internal pull-up VDD i=0 O OPEN O i i GND Very weak current flows VDD X X i=0 O OPEN Weak pull-up current flows GND O When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 17-7 Application Example of Unused Input Port OUTPUT PIN OUTPUT PIN VDD ON OPEN OFF ON OFF OFF i VDD GND X ON O ON OFF L OFF ON i GND X O VDD L i=0 GND O In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port . In the left case, much current flows from port to GND. Figure 17-8 Application Example of Unused Output Port 80 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 18. OSCILLATOR CIRCUIT The GMS81C20xx has two oscillation circuits internally. XIN and XOUT are input and output for main frequency and SXIN and SXOUT are input and output for sub frequency, C1 respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 18-1. C1 SXOUT XOUT C2 4.19MHz C2 XIN 32.768KHz VSS SXIN VSS Recommend C1,C2 = 100~120pF Recommend Crystal Oscillator C1,C2 = 20pF Ceramic Resonator C1,C2 = 30pF Crystal or Ceramic Oscillator Open XOUT XOUT REXT External Clock XIN XIN External Oscillator For selection R value, Refer to AC Characteristics RC Oscillator (mask option) Figure 18-1 Oscillation Circuit Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. XOUT XIN In addition, see Figure 18-2 for the layout of the crystal. Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator. JUNE. 2001 Ver 1.00 Figure 18-2 Layout of Oscillator PCB circuit 81 GMS81C2012/GMS81C2020 19. RESET The GMS81C20xx have two types of reset generation procedures; one is an external reset input, the other is a watchOn-chip Hardware Program counter RAM page register G-flag Initial Value dog timer reset. Table 19-1 shows on-chip hardware initialization by reset action. On-chip Hardware Initial Value (FFFFH) - (FFFEH) Peripheral clock Off (RPR) 0 Watchdog timer Disable (G) 0 Control registers Refer to Table 8-1 on page 28 (PC) Operation mode Main-frequency clock Power fail detector Disable Table 19-1 Initializing Internal Status by Reset Action 19.1 External Reset Input The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 19-2. A connection for simple power-on-reset is shown in Figure 19-1. VCC 10k Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it. + 10uF When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. Figure 19-1 Simple Power-on-Reset Circuit 1 3 ? ? 4 5 6 7 ~ ~ RESET ~ ~ ? ? FFFE FFFF Start ~ ~ ~ ~ ? ? ? ? FE ADL ADH OP ~ ~ DATA BUS 2 ~ ~ Oscillator (XIN pin) ADDRESS BUS to the RESET pin 7036P Stabilization Time tST = 62.5mS at 4.19MHz RESET Process Step tST = 1 fMAIN /1024 MAIN PROGRAM x 256 Figure 19-2 Timing Diagram after RESET 19.2 Watchdog Timer Reset Refer to "11. WATCHDOG TIMER" on page 41. 82 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 20. POWER FAIL PROCESSOR The GMS81C20xx has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the power fail detect circuitry. Whenever VDD falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze MCU according to PFDM bit of PFDR. Refer to "7.4 DC Electrical Characteristics for Standard Pins(5V)" on page 15. Note: If power fail voltage is selected to 3.0V on 3V operation, MCU is freezed at all the times. In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may be experimented or evaluated. Note: User can select power fail voltage level according to PFD0, PFD1 bit of CONFIG register(703FH) at the OTP (GMS87C20xx) but must select the power fail voltage level to define PFD option of "Mask Order & Verification Sheet" at the mask chip(GMS81C20xx). Because the power fail voltage level of mask chip (GMS81C20xx) is determined according to mask option. 7 PFDR 6 5 4 3 Power FailFunction OTP MASK Enable/Disable PFDIS flag PFDIS flag Level Selection PFS0 bit PFS1 bit Mask option Table 20-1 Power fail processor . R/W 2 R/W R/W 1 0 PFDIS PFDM PFS ADDRESS: 0EFH INITIAL VALUE: ---- -100B Power Fail Status 0: Normal operate 1: Set to "1" if power fail is detected Operation Mode 0 : Normal operation regardless of power fail 1 : MCU will be reset by power fail detection Disable Flag 0: Power fail detection enable 1: Power fail detection disable Figure 20-1 Power Fail Voltage Detector Register JUNE. 2001 Ver 1.00 83 GMS81C2012/GMS81C2020 RESET VECTOR YES PFS =1 NO RAM CLEAR INITIALIZE RAM DATA PFS = 0 Skip the initial routine INITIALIZE ALL PORTS INITIALIZE REGISTERS FUNTION EXECUTION Figure 20-2 Example S/W of RESET flow by Power fail VDD VPFDMAX VPFDMIN 64mS Internal RESET VDD When PFR = 1 Internal RESET 64mS t <64mS VDD Internal RESET VPFDMAX VPFDMIN 64mS VPFDMAX VPFDMIN Figure 20-3 Power Fail Processor Situations 84 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 21. OTP PROGRAMMING 21.1 DEVICE CONFIGURATION AREA as Customer ID recording locations where the user can store check-sum or other customer identification numbers. This area is not accessible during normal execution but is readable and writable during program / verify. The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as security bit. Sixteen memory locations (7030H ~ 703FH) are designated 7030H ID 7030H ID 7031H ID 7032H ID 7033H ID 7034H ID 7035H ID 7036H ID 7037H ID 7038H ID 7039H ID 703AH ID 703BH ID 703CH ID 703DH ID 703EH CONFIG 703FH DEVICE CONFIGURATION AREA 703FH 7 CONFIG 6 R7X 5 4 PFS1 PFS0 3 2 LOCK 1 0 RCO ADDRESS: 703FH INITIAL VALUE: -000 -0-0B External RC OSC Selection 0: Crystal or Resonator Oscillator 1: External RC Oscillator Code Protect 0 : Allow Code Read Out 1 : Lock Code Read Out PFD Level Selection 00: PFD = 2.7V 01: PFD = 2.7V 10: PFD = 3.0V 11: PFD = 2.4V R74, R75 Port Selection 0 : Sub Clock 1 : R74, R75 Figure 21-1 Device Configuration Area JUNE. 2001 Ver 1.00 85 GMS81C2012/GMS81C2020 64SDIP R40 R41 R42 R43 R50 R51 R52 R53 R54 R55 R56 R57 RESET XI XO VSS SXI SXO AVSS R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73 AVDD CTL3 CTL2 CTL1 CTL0 VPP EPROM Enable VSS A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA/Vdisp R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD VDD Figure 21-2 Pin Assignment (64SDIP) User Mode EPROM MODE Pin No. Pin Name Pin Name Description 8 R53 CTL3 Read/Write Control P_Vb 9 R54 CTL2 Address/Data Control D_Ab 10 R55 CTL1 Write Control 1 11 R56 CTL0 Write Control 0 13 RESET VPP Programming Power (0V, 12V) 14 XIN EPROM Enable High Active, Latch Address in falling edge 15 XOUT NC No connection 16 VSS VSS Connect to VSS (0V) 20 R60 A_D0 21 R61 A_D1 22 R62 A_D2 23 R63 A_D3 24 R64 A_D4 25 R65 A_D5 26 R66 A_D6 27 R67 A_D7 33 VDD VDD Address Input Data Input/Output Address Input Data Input/Output A8 A0 D0 A9 A1 D1 A10 A2 D2 A11 A3 D3 A12 A4 D4 A13 A5 D5 A14 A6 D6 A15 A7 D7 Connect to VDD (6.0V) Table 21-1 Pin Description in EPROM Mode (GMS81C2020) 86 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 TSET1 THLD1 TDLY1 THLD2 TDLY2 ~ ~ VIHP ~ ~ TVPPS ~ ~ ~ ~ EPROM Enable VPP TVDDS CTL3 0V VDD1H HA LA DATA IN TCD1 LA DATA IN ~ ~ ~~ DATA OUT ~ ~ ~ ~ A_D7~ A_D0 VDD TCD1 TCD1 ~ ~ 0V VDD1H TCD1 ~ ~ CTL2 ~ ~ ~ ~ 0V ~ ~ ~ ~ CTL0/1 TVPPR DATA OUT VDD1H High 8bit Address Input Low 8bit Address Input Write Mode Verify Low 8bit Address Input Write Mode Verify Figure 21-3 Timing Diagram in Program (Write & Verify) Mode JUNE. 2001 Ver 1.00 87 GMS81C2012/GMS81C2020 After input a high address, output data following low address input TSET1 THLD1 TDLY1 THLD2 Anothe high address step TDLY2 EPROM Enable TVPPS VIHP VPP TVDDS CTL0/1 0V TVPPR VDD2H CTL2 0V CTL3 0V TCD2 VDD2H TCD1 A_D7~ A_D0 VDD TCD2 TCD1 HA LA DATA LA DATA HA LA DATA High 8bit Address Input Low 8bit Address Input DATA Output Low 8bit Address Input DATA Output High 8bit Address Input Low 8bit Address Input DATA Output VDD2H Figure 21-4 Timing Diagram in READ Mode Parameter Symbol MIN TYP MAX Unit Programming Supply Current IVPP - - 50 mA Supply Current in EPROM Mode IVDDP - - 20 mA VPP Level during Programming VIHP 11.5 12.0 12.5 V VDD Level in Program Mode VDD1H 5 6 6.5 V VDD Level in Read Mode VDD2H - 2.7 - V CTL3~0 High Level in EPROM Mode VIHC 0.8VDD - - V CTL3~0 Low Level in EPROM Mode VILC - - 0.2VDD V A_D7~A_D0 High Level in EPROM Mode VIHAD 0.9VDD - - V A_D7~A_D0 Low Level in EPROM Mode VILAD - - 0.1VDD V VDD Saturation Time TVDDS 1 - - mS VPP Setup Time TVPPR - - 1 mS VPP Saturation Time TVPPS 1 - - mS EPROM Enable Setup Time after Data Input TSET1 200 nS EPROM Enable Hold Time after TSET1 THLD1 500 nS Table 21-2 AC/DC Requirements for Program/Read Mode 88 JUNE. 2001 Ver 1.00 GMS81C2012/GMS81C2020 EPROM Enable Delay Time after THLD1 TDLY1 200 nS EPROM Enable Hold Time in Write Mode THLD2 100 nS EPROM Enable Delay Time after THLD2 TDLY2 200 nS CTL2,1 Setup Time after Low Address input and Data input TCD1 100 nS CTL1 Setup Time before Data output in Read and Verify Mode TCD2 100 nS Table 21-2 AC/DC Requirements for Program/Read Mode START Set VDD=VDD1H Report Programming failure Set VPP=VIHP VDD=6V & 2.7V Verify FAIL Verify blank Report Verify failure Verify of all address FAIL PASS PASS Report Programming OK First Address Location Next address location VPP=0V N=1 VDD=0V N=N+1 YES EPROM Write 100uS program time N END NO FAIL Verify PASS Apply 3x program cycle NO Last address ? YES Figure 21-5 Programming Flow Chart JUNE. 2001 Ver 1.00 89 GMS81C2012/GMS81C2020 90 JUNE. 2001 Ver 1.00 APPENDIX GMS800 Series A. CONTROL REGISTER LIST Address Register Name Symbol R/W Initial Value Page 7 6 5 4 3 2 1 0 00C0 R0 port data register R0 R/W Undefined 35 00C1 R0 port I/O direction register R0IO W 00000000 35 00C2 R1 port data register R1 R/W Undefined 36 00C3 R1 port I/O direction register R1IO W 00000000 36 00C4 R2 port data register R2 R/W Undefined 36 00C5 R2 port I/O direction register R2IO W 00000000 36 00C6 R3 port data register R3 R/W Undefined 36 00C7 R3 port I/O direction register R3IO W - - 000000 36 00C8 R4 port data register R4 R/W Undefined 36 00C9 R4 port I/O direction register R4IO W - - - - 0000 36 00CA R5 port data register R5 R/W Undefined 37 00CB R5 port I/O direction register R5IO W 00000000 37 00CC R6 port data register R6 R/W Undefined 37 00CD R6 port I/O direction register R6IO W 00000000 37 00CE R7 port data register R7 R/W Undefined 38 00CF R7 port I/O direction register R7IO W - - 000000 38 00D0 Timer mode register 0 TM0 R/W - - 000000 45 T0 R 00000000 46 Timer 0 data register TDR0 W 11111111 45 Capture 0 data register CDR0 R 00000000 52 Timer mode register 1 TM1 R/W 00000000 45 Timer 1 data register TDR1 W 11111111 45 T1PPR W 11111111 57 T1 R 00000000 46 PWM 1 duty register T1PDR R/W 00000000 57 Capture 1 data register CDR1 R 00000000 52 Timer 0 register 00D1 00D2 00D3 PWM 1 period register Timer 1 register 00D4 00D5 PWM 1 High register PWM1HR W - - - - 0000 56 00DE Buzzer driver register BUR W 11111111 65 00E0 Serial I/O mode register SIOM R/W 00000001 62 00E1 Serial I/O data register SIOR R/W Undefined 62 00E2 Interrupt enable register high IENH R/W 0000 - - - - 68 00E3 Interrupt enable register low IENL R/W 0000 - - - - 68 00E4 Interrupt request flag register high IRQH R/W 0000 - - - - 67 00E5 Interrupt request flag register low IRQL R/W 0000 - - - - 67 00E6 External interrupt edge selection register IEDS R/W - - - - 0000 73 00EA A/D converter mode register ADCM R/W - 0000001 58 JUNE. 2001 i GMS800 Series Address Register Name Symbol R/W Initial Value Page 7 6 5 4 3 2 1 0 00EB ADCR R Undefined 58 BITR R 00000000 40 CKCTLR W - 0010111 40 Watchdog Timer Register WDTR R 00000000 42 Watchdog Timer Register WDTR W 01111111 42 00EF Power fail detection register PFDR R/W - - - - - 100 83 00F4 R0 Function selection register R0FUNC W - - - - 0000 35 00F5 R4 Function selection register R4FUNC W - - - - - - - 0 36 00F6 R5 Function selection register R5FUNC W - 0 - - - - - - 37 00F7 R6 Function selection register R6FUNC W 00000000 37 00F8 R7 Function selection register R7FUNC W - - - - 0000 38 00F9 R5 N-MOS open drain selection register R5MPDR W 00000000 37 00FA System clock mode register SCMR R/W - - - 00000 75 00FB RA port data register RA R Undefined 35 00EC 00ED ii A/D converter data register Basic interval timer mode register Clock control register JUNE. 2001 GMS800 Series B. INSTRUCTION B.1 Terminology List Terminology Description A Accumulator X X - register Y Y - register PSW Program Status Word #imm 8-bit Immediate data dp !abs Direct Page Offset Address Absolute Address [] Indirect expression {} Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit Bit Position A.bit Bit Position of Accumulator dp.bit Bit Position of Direct Page Memory M.bit Bit Position of Memory Data (000H~0FFFH) rel upage Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address n Table CALL Number (0~15) + Addition Upper Nibble Expression in Opcode 0 x Bit Position Upper Nibble Expression in Opcode 1 y Bit Position - Subtraction x Multiplication / Division () Contents Expression AND OR Exclusive OR ~ NOT Assignment / Transfer / Shift Left Shift Right Exchange = Equal Not Equal JUNE. 2001 iii GMS800 Series B.2 Instruction Map LOW 00000 HIGH 00 SET1 dp.bit 00010 02 00011 03 BBS BBS A.bit,rel dp.bit,rel 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp 01010 0A 01011 0B 01100 0C 01101 0D 01110 0E 01111 0F TCALL SETA1 0 .bit BIT dp POP A PUSH A BRK 000 - 001 CLRC SBC #imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCALL CLRA1 2 .bit COM dp POP X PUSH X BRA rel 010 CLRG CMP #imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCALL 4 NOT1 M.bit TST dp POP Y PUSH Y PCALL Upage 011 DI OR #imm OR dp OR dp+X OR !abs ROR A ROR dp TCALL 6 OR1 OR1B CMPX dp POP PSW PUSH PSW RET 100 CLRV AND #imm AND dp AND dp+X AND !abs INC A INC dp TCALL AND1 8 AND1B CMPY dp CBNE dp+X TXSP INC X 101 SETC EOR #imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 10 EOR1B DBNE dp XMA dp+X TSPX DEC X 110 SETG LDA #imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL 12 LDC LDCB LDX dp LDX dp+Y XCN DAS 111 EI LDM dp,#imm STA dp STA dp+X STA !abs TAX STY dp TCALL 14 STC M.bit STX dp STX dp+Y XAX STOP 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1A 11011 1B 11100 1C 11101 1D 11110 1E 11111 1F ADC {X} ADC !abs+Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCALL 1 JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs] TEST !abs SUBW dp LDY #imm JMP [dp] TCLR1 CMPW !abs dp CMPX #imm CALL [dp] LOW 10000 HIGH iv 00001 01 10 10001 11 10010 12 000 BPL rel 001 BVC rel SBC {X} SBC !abs+Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCALL 3 CALL !abs 010 BCC rel CMP {X} CMP !abs+Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCALL 5 MUL 011 BNE rel OR {X} OR !abs+Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCALL 7 DBNE Y CMPX !abs LDYA dp CMPY #imm RETI 100 BMI rel AND {X} AND !abs+Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCALL 9 DIV CMPY !abs INCW dp INC Y TAY 101 BVS rel EOR {X} EOR !abs+Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCALL 11 XMA {X} XMA dp DECW dp DEC Y TYA 110 BCS rel LDA {X} LDA !abs+Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCALL 13 LDA {X}+ LDX !abs STYA dp XAY DAA 111 BEQ rel STA {X} STA !abs+Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCALL 15 STA {X}+ STX !abs CBNE dp XYX NOP CLR1 BBC BBC dp.bit A.bit,rel dp.bit,rel JUNE. 2001 GMS800 Series B.3 Instruction Set Arithmetic / Logic Operation No. Mnemonic Op Code Byte No Cycle No Operation 1 ADC #imm 04 2 2 Add with carry. 2 ADC dp 05 2 3 A(A)+(M)+C 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs + Y 15 3 5 NV--H-ZC 6 ADC [ dp + X ] 16 2 6 7 ADC [ dp ] + Y 17 2 6 8 ADC { X } 14 1 3 9 AND #imm 84 2 2 Logical AND 10 AND dp 85 2 3 A (A)(M) 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs + Y 95 3 5 14 AND [ dp + X ] 96 2 6 15 AND [ dp ] + Y 97 2 6 16 AND { X } 94 1 3 17 ASL A 08 1 2 18 ASL dp 09 2 4 19 ASL dp + X 19 2 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp + X 46 2 4 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [ dp + X ] 56 2 6 27 CMP [ dp ] + Y 57 2 6 28 CMP { X } 54 1 3 29 CMPX #imm 5E 2 2 30 CMPX dp 6C 2 3 31 CMPX !abs 7C 3 4 Flag NVGBHIZC N-----Z- Arithmetic shift left C 7 6 5 4 3 2 1 0 N-----ZC "0" Compare accumulator contents with memory contents (A) -(M) N-----ZC Compare X contents with memory contents (X)-(M) N-----ZC 32 CMPY #imm 7E 2 2 33 CMPY dp 8C 2 3 Compare Y contents with memory contents 34 CMPY !abs 9C 3 4 35 COM dp 2C 2 4 1'S Complement : ( dp ) ~( dp ) N-----Z- 36 DAA DF 1 3 Decimal adjust for addition N-----ZC 37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC Decrement N-----Z- (Y)-(M) N-----ZC 38 DEC A A8 1 2 39 DEC dp A9 2 4 40 DEC dp + X B9 2 5 N-----Z- 41 DEC !abs B8 3 5 N-----Z- 42 DEC X AF 1 2 N-----Z- 43 DEC Y BE 1 2 N-----Z- JUNE. 2001 M (M)-1 N-----Z- v GMS800 Series No. Op Code Byte No Cycle No Operation 44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y 45 EOR #imm A4 2 2 Exclusive OR Flag NVGBHIZC NV--H-Z- A (A)(M) 46 EOR dp A5 2 3 47 EOR dp + X A6 2 4 48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5 50 EOR [ dp + X ] B6 2 6 51 EOR [ dp ] + Y B7 2 6 52 EOR { X } B4 1 3 53 INC A 88 1 2 54 INC dp 89 2 4 55 INC dp + X 99 2 5 N-----Z- 56 INC !abs 98 3 5 N-----Z- 57 INC X 8F 1 2 N-----Z- 58 INC Y 9E 1 2 N-----Z- 59 LSR A 48 1 2 60 LSR dp 49 2 4 61 LSR dp + X 59 2 5 62 LSR !abs 58 3 5 63 MUL 5B 1 9 Multiply : YA Y x A 64 OR #imm 64 2 2 Logical OR 65 OR dp 65 2 3 66 OR dp + X 66 2 4 67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5 69 OR [ dp + X ] 76 2 6 70 OR [ dp ] + Y 77 2 6 71 OR { X } 74 1 3 72 ROL A 28 1 2 73 ROL dp 29 2 4 74 ROL dp + X 39 2 5 75 ROL !abs 38 3 5 76 ROR A 68 1 2 Rotate right through Carry 77 ROR dp 69 2 4 78 ROR dp + X 79 2 5 7 6 5 4 3 2 1 0 79 ROR !abs 78 3 5 80 SBC #imm 24 2 2 81 SBC dp 25 2 3 82 SBC dp + X 26 2 4 83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5 85 SBC [ dp + X ] 36 2 6 86 SBC [ dp ] + Y 37 2 6 87 SBC { X } 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero, ( dp ) - 00H N-----Z- 5 Exchange nibbles within the accumulator A7~A4 A3~A0 N-----Z- 89 vi Mnemonic XCN CE 1 N-----Z- Increment N-----ZC M (M)+1 N-----Z- Logical shift right 7 6 5 4 3 2 1 0 C "0" N-----ZC N-----Z- A (A)(M) N-----Z- Rotate left through Carry C 7 6 5 4 3 2 1 0 C N-----ZC N-----ZC Subtract with Carry A ( A ) - ( M ) - ~( C ) NV--HZC JUNE. 2001 GMS800 Series Register / Memory Operation No. Mnemonic Op Code Byte No Cycle No 1 LDA #imm C4 2 2 2 LDA dp C5 2 3 3 LDA dp + X C6 2 4 4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 6 LDA [ dp + X ] D6 2 6 7 LDA [ dp ] + Y D7 2 6 8 LDA { X } D4 1 3 Operation Load accumulator A(M) N-----Z- 9 LDA { X }+ DB 1 4 X- register auto-increment : A ( M ) , X X + 1 10 LDM dp,#imm E4 3 5 Load memory with immediate data : ( M ) imm 11 LDX #imm 1E 2 2 Load X-register 12 LDX dp CC 2 3 13 LDX dp + Y CD 2 4 14 LDX !abs DC 3 4 15 LDY #imm 3E 2 2 16 LDY dp C9 2 3 17 LDY dp + X D9 2 4 18 LDY !abs D8 3 4 19 STA dp E5 2 4 20 STA dp + X E6 2 5 21 STA !abs E7 3 5 22 STA !abs + Y F5 3 6 23 STA [ dp + X ] F6 2 7 24 STA [ dp ] + Y F7 2 7 Flag NVGBHIZC X (M) -------N-----Z- Load Y-register Y(M) N-----Z- Store accumulator contents in memory (M)A -------- 25 STA { X } F4 1 4 26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) A, X X + 1 27 STX dp EC 2 4 Store X-register contents in memory 28 STX dp + Y ED 2 5 29 STX !abs FC 3 5 30 STY dp E9 2 4 31 STY dp + X F9 2 5 32 STY !abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X-register : X A N-----Z- 34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y A N-----Z- 35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X sp N-----Z- 36 TXA C8 1 2 Transfer X-register contents to accumulator: A X N-----Z- 37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp X N-----Z- 38 TYA BF 1 2 Transfer Y-register contents to accumulator: A Y N-----Z- 39 XAX EE 1 4 Exchange X-register contents with accumulator :X A -------- 40 XAY DE 1 4 Exchange Y-register contents with accumulator :Y A -------- 41 XMA dp BC 2 5 Exchange memory contents with accumulator 42 XMA dp+X AD 2 6 43 XMA {X} BB 1 5 44 XYX FE 1 4 JUNE. 2001 (M) X -------- Store Y-register contents in memory (M) Y (M)A Exchange X-register contents with Y-register : X Y -------- N-----Z-------- vii GMS800 Series 16-BIT operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1 ADDW dp 1D 2 5 16-Bits add without Carry YA ( YA ) + ( dp +1 ) ( dp ) NV--H-ZC 2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents : (YA) - (dp+1)(dp) N-----ZC 3 DECW dp BD 2 6 Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 N-----Z- 4 INCW dp 9D 2 6 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 N-----Z- 5 LDYA dp 7D 2 5 Load YA YA ( dp +1 ) ( dp ) N-----Z- 6 STYA dp DD 2 5 Store YA ( dp +1 ) ( dp ) YA -------- 7 SUBW dp 3D 2 5 16-Bits subtract without carry YA ( YA ) - ( dp +1) ( dp) NV--H-ZC Op Code Byte No Cycle No Bit Manipulation No. Mnemonic Operation Flag NVGBHIZC 1 AND1 M.bit 8B 3 4 Bit AND C-flag : C ( C ) ( M .bit ) -------C 2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ( C ) ~( M .bit ) -------C 3 BIT dp 0C 2 4 Bit test A with memory : MM----Z- 4 BIT !abs 1C 3 5 Z ( A ) ( M ) , N ( M 7 ) , V ( M6 ) 5 CLR1 dp.bit y1 2 4 Clear bit : ( M.bit ) "0" -------- 6 CLRA1 A.bit 2B 2 2 Clear A bit : ( A.bit ) "0" -------- 7 CLRC 20 1 2 Clear C-flag : C "0" -------0 8 CLRG 40 1 2 Clear G-flag : G "0" --0----- 9 CLRV 80 1 2 Clear V-flag : V "0" -0--0--- 10 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ( C ) ( M .bit ) -------C 11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) -------C 12 LDC M.bit CB 3 4 Load C-flag : C ( M .bit ) -------C 13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ~( M .bit ) -------C 14 NOT1 M.bit 4B 3 5 Bit complement : ( M .bit ) ~( M .bit ) -------- 15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ( C ) ( M .bit ) -------C 16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ( C ) ~( M .bit ) -------C 17 SET1 dp.bit x1 2 4 Set bit : ( M.bit ) "1" -------- 18 SETA1 A.bit 0B 2 2 Set A bit : ( A.bit ) "1" -------- 19 SETC A0 1 2 Set C-flag : C "1" -------1 20 SETG C0 1 2 Set G-flag : G "1" --1----- 21 STC M.bit EB 3 6 Store C-flag : ( M .bit ) C -------- 22 TCLR1 !abs 5C 3 6 Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) N-----Z- 23 TSET1 !abs 3C 3 6 Test and set bits with A : A-(M), (M) (M)(A) N-----Z- viii JUNE. 2001 GMS800 Series Branch / Jump Operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1 BBC A.bit,rel y2 2 4/6 Branch if bit clear : 2 BBC dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ( pc ) + rel 3 BBS A.bit,rel x2 2 4/6 Branch if bit set : 4 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ( pc ) + rel 5 BCC rel 50 2 2/4 Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel -------- 6 BCS rel D0 2 2/4 Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel -------- 7 BEQ rel F0 2 2/4 Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel -------- 8 BMI rel 90 2 2/4 Branch if minus if ( N ) = 1 , then pc ( pc ) + rel -------- 9 BNE rel 70 2 2/4 Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel -------- 10 BPL rel 10 2 2/4 Branch if minus if ( N ) = 0 , then pc ( pc ) + rel -------- 11 BRA rel 2F 2 4 Branch always pc ( pc ) + rel -------- 12 BVC rel 30 2 2/4 Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel -------- 13 BVS rel B0 2 2/4 Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel -------- 14 CALL !abs 3B 3 8 Subroutine call 15 CALL [dp] 5F 2 8 M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, if !abs, pc abs ; if [dp], pcL ( dp ), pcH ( dp+1 ) . -------- 16 CBNE dp,rel FD 3 5/7 Compare and branch if not equal : -------- 17 CBNE dp+X,rel 8D 3 6/8 18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 19 DBNE Y,rel 7B 2 4/6 if ( M ) 0 , then pc ( pc ) + rel. 20 JMP !abs 1B 3 3 21 JMP [!abs] 1F 3 5 22 JMP [dp] 3F 2 4 23 PCALL upage 4F 2 6 U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . -------- 24 TCALL n nA 1 8 Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H) -------- JUNE. 2001 --------------- if ( A ) ( M ) , then pc ( pc ) + rel. -------- Unconditional jump pc jump address -------- ix GMS800 Series Control Operation & Etc. No. 1 x Mnemonic BRK Op Code Byte No Cycle No Operation 0F 1 8 Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp -1, pcL ( 0FFDE H ) , pcH ( 0FFDFH) . ---1-0-- Flag NVGBHIZC 2 DI 60 1 3 Disable all interrupts : I "0" -----0-- 3 EI E0 1 3 Enable all interrupt : I "1" -----1-- 4 NOP FF 1 2 No operation -------- 5 POP A 0D 1 4 sp sp + 1, A M( sp ) 6 POP X 2D 1 4 sp sp + 1, X M( sp ) 7 POP Y 4D 1 4 sp sp + 1, Y M( sp ) 8 POP PSW 6D 1 4 sp sp + 1, PSW M( sp ) -------restored 9 PUSH A 0E 1 4 M( sp ) A , sp sp - 1 10 PUSH X 2E 1 4 M( sp ) X , sp sp - 1 11 PUSH Y 4E 1 4 M( sp ) Y , sp sp - 1 12 PUSH PSW 6E 1 4 M( sp ) PSW , sp sp - 1 13 RET 6F 1 5 Return from subroutine sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) -------- 14 RETI 7F 1 6 Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pcL M( sp ), sp sp + 1, pcH M( sp ) restored 15 STOP EF 1 3 Stop mode ( halt CPU, stop oscillator ) -------- -------- JUNE. 2001 C. MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81C20XX-HI Customer should write inside thick line box. 2. Device Information 1. Customer Information Company Name Package 64SDIP Internet Application Tel: MM Fax: E-mail address: 64LQFP Hitel Chollian ( File Name DD Mask Data YYYY Order Date 64MQFP ) .OTP ROM Size (bytes) Check Sum 12K 20K ( ) (20K) 3000 H (12K) 5000 H Name & Signature: Set "00 H" in blanked area .O TP file 7FFF H (Please check mark into 3. Marking Specification 12 or 20 Customer's logo GMS81C20XX-HI YYWW GMS81C20XX-HI YYWW KOREA KOREA Customer logo is not required. If the customer logo must be used in the special mark, please submit a clean original of the logo. Customer's part number 4. Delivery Schedule Date Customer sample Risk order Quantity YYYY MM DD YYYY MM DD HYNIX Confirmation pcs pcs 5. ROM Code Verification Please confirm out verification data. YYYY Verification date: Check sum: Tel: E-mail address: Name & Signature: MM DD YYYY Approval date: MM DD I agree with your verification data and confirm you to make mask set. Fax: Tel: E-mail address: Name & Signature: Fax: ) GMS81C20XX MASK OPTION LIST Customer should write inside thick line box. 1. RA/Vdisp RA without pull-down resistor Vdisp (Please check mark into ) 2. CONFIG OPTION Check X X 7 CONFIG 6 R7X X 5 4 PFS1 PFS0 CONFIG Default Value : X000X0X0 3 2 LOCK 1 0 ADDRESS: 703FH INITIAL VALUE: -000 -0-0B RCO R74, R75 Selection 0 : Sub Clock 1 : R74, R75 External RC OSC Selection 0: Crystal or Resonator Oscillator 1: External RC Oscillator PFD Level Selection 00: PFD = 2.7V 01: PFD = 2.7V 10: PFD = 3.0V 11: PFD = 2.4V Code Protect 0 : Allow Code Read Out 1 : Lock Code Read Out 3. H/V Port OPTION Check (Pull-down Option Check ) Port Option ON OFF Port Option ON OFF Port Option ON OFF Port R00/INT0 R10 R20 R30 R01/INT1 R11 R21 R31 R02/EC0 R12 R22 R32 R03/BUZO R13 R23 R33 R04 R14 R24 R34 R05 R15 R25 R35 R06 R16 R26 R07 R17 R27 Option ON OFF ON : with pull-down resistor OFF : without pull-down resistor 4. Normal Port OPTION Check ( Pull-up Option Check ) Port Option ON OFF Port Option ON OFF Port Option ON OFF Port R40/T0O R50 R60/AN0 R41 R51 R61/AN1 R71/AN9 R42 R52 R62/AN2 R72/AN10 R43 R53/SCLK R63/AN3 R73/AN11 R54/SIN R64/AN4 R55/SOUT R65/AN5 R56/PWM R66/AN6 R57 R67/AN7 Option ON OFF R70/AN8 ON : with pull-up resistor OFF : without pull-up resistor