PRELIMINARY DATA SHEET AC104L 3.3V 4-Port 10/100-TX Ethernet Transceiver GENERAL DESCRIPTION FEATURES The AC104L is a highly integrated, 3.3V, low power, four port, 10BASE-T/100BASE-TX, Ethernet transceiver implemented in 0.35m CMOS technology. Multiple modes of operation, including normal operation, test mode and power saving mode, are available through either hardware or software control. * * 4 ports with RMII MAC interface 4 ports with 10/100 TX media interface * * Full-duplex or half-duplex Very small package * * 100PQFP Very low power - TYP < 280mW per port * Cable detect mode - TYP < 40mW per port Features include ENDECs, Scrambler/Descrambler, and Auto-Negotiation (ANeg) with support for parallel detection. The transmitter includes a dual-speed clock synthesizer that only needs one external clock source. The chip has built-in wave shaping driver circuit for both 10 Mbps and 100 Mbps, eliminating the need for an external hybrid filter. The receiver has an adaptive equalizer/DC restoration circuit for accurate clock/data recovery for the 100BASE-TX signal. It also provides an on-chip low pass filer/Squelch circuit for the 10BASE-T signal. * Power Down mode - TYP < 3.3mW per port * Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction 3.3V .35 micron CMOS Fully compliant with * * * IEEE 802.3 / 802.3u * RMII Baseline wander compensation Multi-function LED outputs Cable length indicator Reverse polarity detection and correction with register bit indication - automatic or forced 8 programmable interrupts * * * * * Port A TXOP/N(A) Port B RXIP/N(A) Port C Port D MHs 10BASE-T Control/Status RXIP/N(B) TXOP/N(C) RXIP/N(C) Mux 25 MDIO/MDC TXOP/N(B) 100TX TP_PMD .MLT-3 .BLW .Stream Cipher 100RX PMA .Clock Recov. .Link Monitor .Signal Detect Interface RMI PCS .Framer .Carrier Detect .4B/5B TXOP/N(D) RXIP/N(D) 10TX 10RX 20 RX MHs MII Serial Management Interface and Registers PLL Clk Gen. Test/LED Control 25 FLP AutoNegotiation MHs PHYAD[4:0] CKIN TEST[3:0] LED Drivers Figure 1: Functional Block Diagram AC104L-DS01-R 16215 Alton Parkway * P.O. Box 57013 * Irvine, CA 92619-7013 * Phone: 949-450-8700 * Fax: 949-450-8710 06/26/01 REVISION HISTORY Revision Date Change Description DS00-R 01/11/01 Initial Release AC104L-DS01-R 06/26/01 Added description of Pin 42 to Table 6; changed product name and number from AC104L-QF to AC104L Altima Communications, Inc. A Wholly Owned Subsidiary of Broadcom Corporation P.O. Box 57013 16215 Alton Parkway Irvine, CA 92619-7013 (c) 2001 Altima Communications, Inc. All rights reserved Printed in the U.S.A. Broadcom(R), the pulse logo(R), and QAMLink(R) are registered trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners. AC104L Preliminary Data Sheet 06/26/01 TABLE OF CONTENTS Section 1: Functional Description...................................................................................... 1 MAC Interface ............................................................................................................................................... 1 RMII ........................................................................................................................................................ 1 SMI.......................................................................................................................................................... 1 Interrupt................................................................................................................................................... 2 Media Interface ............................................................................................................................................. 2 10BASE-T ............................................................................................................................................... 2 Transmit Function ................................................................................................................................... 2 Receive Function .................................................................................................................................... 2 Link Monitor ............................................................................................................................................ 2 100BASE-TX........................................................................................................................................... 2 Transmit Function ................................................................................................................................... 2 Parallel to Serial, NRZ to NRZI, and MLT3 Conversion.......................................................................... 3 Receive Function .................................................................................................................................... 3 Baseline Wander Compensation ............................................................................................................ 3 Clock/Data Recovery .............................................................................................................................. 4 Decoder/De-Scrambler ........................................................................................................................... 4 Link Monitor ............................................................................................................................................ 4 10BASE-T/100BASE-TX ............................................................................................................................... 4 Multi-Mode Transmit Driver..................................................................................................................... 4 Adaptive Equalizer .................................................................................................................................. 5 PLL Clock Synthesizer............................................................................................................................ 5 Jabber and SQE (Heartbeat) .................................................................................................................. 5 Reverse Polarity Detection and Correction ............................................................................................. 5 Initialization and Setup ................................................................................................................................ 6 Hardware Configuration .......................................................................................................................... 6 Software Configuration ........................................................................................................................... 6 LEDs ....................................................................................................................................................... 6 Auto-Negotiation ..................................................................................................................................... 6 Parallel Detection.................................................................................................................................... 7 Diagnostics ............................................................................................................................................. 7 Loopback Operation................................................................................................................................ 7 B roa dcom Document AC104L-DS01-R Page iii AC104L Preliminary Data Sheet 06/26/01 Cable Length Indicator ............................................................................................................................ 7 Reset and Power........................................................................................................................................... 8 Clock .............................................................................................................................................................. 8 Section 2: Pin Description.................................................................................................. 9 Pin Diagram................................................................................................................................................... 9 Pin Descriptions .........................................................................................................................................10 Section 3: Register Descriptions ..................................................................................... 14 Legend...................................................................................................................................................14 Section 4: Electrical Characteristics ............................................................................... 25 Absolute Maximum Ratings.......................................................................................................................25 Operating Range.........................................................................................................................................25 Recommended Termination ......................................................................................................................32 Power and Ground Filtering ......................................................................................................................33 Section 5: Package Drawing ............................................................................................ 34 Section 6: Ordering Information ..................................................................................... 35 B roa dcom Page iv Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 LIST OF FIGURES Figure 1: Functional Block Diagram .................................................................................................. Cover Page Figure 2: AC104L 100-pin .................................................................................................................................. 9 Figure 3: LED Configurations ........................................................................................................................... 24 Figure 4: MDC/MDIO Timing Diagram 1 .......................................................................................................... 31 Figure 5: MDC/MDIO Timing Diagram 2 .......................................................................................................... 31 Figure 6: Termination Figure ............................................................................................................................ 32 Figure 7: Power and Ground ............................................................................................................................ 33 Figure 8: Package Drawing .............................................................................................................................. 34 B roa dcom Document AC104L-DS01-R Page v AC104L Preliminary Data Sheet 06/26/01 B roa dcom Page vi Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 LIST OF TABLES Table 1: MDI (Media Dependent Interface) Pins .............................................................................................. 10 Table 2: RMII (Reduced Media Independent Interface) Pins ........................................................................... 11 Table 3: SMI ( Serial Management Interface) Pins........................................................................................... 11 Table 4: PHY Address Pins .............................................................................................................................. 12 Table 5: Mode Pins........................................................................................................................................... 12 Table 6: LED Pins............................................................................................................................................. 13 Table 7: Miscellaneous Pins............................................................................................................................. 13 Table 8: Power and Ground Pins ..................................................................................................................... 13 Table 9: Registers 0-7 ...................................................................................................................................... 14 Table 10: Registers 8-31 .................................................................................................................................. 15 Table 11: Register 0: Control............................................................................................................................ 15 Table 12: Register 1: Status ............................................................................................................................. 16 Table 13: Register 2: PHY Identifier 1 .............................................................................................................. 16 Table 14: Register 3: PHY Identifier 2 .............................................................................................................. 17 Table 15: Register 4: Auto-Negotiation Advertisement .................................................................................... 17 Table 16: Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message ......... 18 Table 17: Register 6: Auto-Negotiation Expansion........................................................................................... 18 Table 18: Register 7: Auto-Negotiation Next Page Transmit............................................................................ 19 Table 19: Register 16: BT and Interrupt Level Control ..................................................................................... 19 Table 20: Register 17: Interrupt Control/Status ................................................................................................ 20 Table 21: Register 19: Power/Loopback .......................................................................................................... 21 Table 22: Register 20: Cable Measurement Capability .................................................................................... 21 Table 23: Register 21: Receive Error Counter ................................................................................................. 21 Table 24: 4B/5B Code-Group Table ................................................................................................................. 22 Table 25: SMI Read/Write Sequence ............................................................................................................... 23 Table 26: LED Configurations .......................................................................................................................... 24 Table 27: DC Characteristics (0oC < Ta < 70oC, 2.97V < VCC < 3.63V, unless otherwise noted) ................. 25 Table 28: AC Characteristics (0oC < Ta < 70oC, 2.97V < VCC < 3.63V, unless otherwise noted) ................. 27 Table 29: AC Characteristics (0oC < Ta < 70oC, 2.97V < VCC < 3.63V, unless otherwise noted) ................. 28 Table 30: Digital Timing Characteristics (0oC <Ta <70oC, 2.97V < Vdd < 3.63V)........................................... 29 Table 31: Digital Timing Characteristics (0oC <Ta <70oC, 2.97V < Vdd < 3.63V)........................................... 30 Table 32: MDC/MDIO Timing ........................................................................................................................... 31 B roa dcom Document AC104L-DS01-R Page vii AC104L Preliminary Data Sheet 06/26/01 Table 33: Package Drawing ..............................................................................................................................34 B roa dcom Page viii Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 S e c ti o n 1 : Fu nc t io na l D e s c r i pt i on The AC104L physical layer device (PHY) integrates the 100BASE-TX and 10BASE-T functions in a single four-port chip that is used in Fast Ethernet 10/100 Mbps applications. The 100BASE-TX section consists of PCS, PMA, and PMD functions and the 10BASE-T section consists of Manchester ENDEC and transceiver functions. The device performs the following functions: * 4B/5B * MLT3 * NRZI * Manchester encoding and decoding * Clock and data recovery * Stream cipher scrambling/de-scrambling * Adaptive equalization * Line transmission * Carrier sense * Link integrity monitor * Auto-negotiation (ANeg) * RMII MAC connectivity * MII management function It also provides an RMII consortium compatible Reduced Media Independent Interface (RMII) to communicate with an Ethernet Media Access Controller (MAC). Selection of 10 or 100 Mbps operation is based on the settings of internal Serial Management Interface registers or determined by the on-chip ANeg logic. The device operates in 10 or 100 Mbps with full-duplex or half-duplex mode on a per-port basis. MAC INTERFACE RMII The Reduced Media Independent Interface (RMII) is used to connect the PHY with the MAC. The PHY and MAC obtain their clock from a common 50 MHz source, such as a clock oscillator. This clock is shared by all ports within the PHY for transmitting and receiving data on two individual 2-bit data buses. In 100M mode, RXD[1:0] is sampled on every cycle of REFCLK. In 10M mode, RXD[1:0] is sampled on every 10th cycle of REFCLK. RXER is generated by the PHY to indicate a receive error to the MAC. TX_EN is generated by the MAC to indicate to the PHY when there is valid data on the transmit bus. In 100M mode, the PHY reads 2 bits from TXD[1:0] for each cycle of REFCLK. In 10M mode, the PHY reads 2 bits of data from TXD[1:0] every 10th cycle of REFCLK. The Serial Management Interface (SMI) is shared between all ports in the PHY. This totals 7 pins per port plus 3 per PHY. SMI The PHY's internal registers are accessible only through the MII two-wire Serial Management Interface (SMI). MDC is a clock input to the PHY, which is used to latch in or out data and instructions for the PHY. The clock runs from 2.5 MHz to 25 MHz. MDIO is a bi-directional connection used to write instructions to, write data to, or read data from the PHY. Each data bit is latched either in or out on the rising edge of MDC. MDC is not required to maintain any speed or duty cycle, provided no half cycle is less than 20 ns and that data is presented synchronous to MDC. MDC/MDIO are a common signal pair to all ports on a design. Therefore, each port needs to have its own unique Physical Address. The Physical Address of the PHY is set using the pins defined as PHYAD[4:2]. These input signals are strapped B roa dcom Document AC104L-DS01-R Section 1: Functional Description Page 1 AC104L Preliminary Data Sheet 06/26/01 externally and sampled as reset is negated. PHYAD[1:0] are addressed for each port internal to the PHY. Internal addresses are either 00, 01, 10, 11 or 01, 10, 11, 00 depending on the polarity of PHYAD_ST during reset. When idle, the PHY is responsible to pull MDIO line to a high state. Therefore, a 1.5K Ohm resistor is used to pull the MDIO signal high. The PHYAD can be reprogrammed via software. At the beginning of a read or write cycle, the MAC sends a continuous 32 bits of one at the MDC clock rate to indicate preamble. A zero and a one follows to indicate start of frame. A read OP code is a one and a zero, while a write OP code is a zero and a one. These follow by 5 bits to indicate PHY address and 5 bits to indicate register address. Then 2 bits follow to allow for turn around time. For a read operation, the first bit is high impedance. Neither the PHY nor the station asserts this bit. During the second bit time, the PHY asserts this bit to a zero. For a write operation, the station drives a one for the first bit time, and a zero for the second bit time. The 16 bits data field is then presented. The first bit that is transmitted is bit 15 of the register content. INTERRUPT The INTR pin on the PHY is asserted when one of eight selectable interrupt events occur. Selection is made by setting the appropriate bit in the upper half of the Interrupt Control/Status register. When the INTR bit goes active, the MAC interface is required to read the Interrupt Control/Status register to determine which event caused the interrupt. The Status bits are read only and clear on read. When INTR is not asserted, the pin is held in a high impedance state. MEDIA INTERFACE 10BASE-T When configured to run in 10BASE-T mode through hardware configuration, software configuration or ANeg, the PHY supports all the features and parameters of the industry standards. TRANSMIT FUNCTION Parallel-to-Serial logic is used to convert the 2-bit data into the serial stream. The serialized data goes directly to the Manchester encoder, where it is synthesized through the output waveshaping driver. The waveshaper reduces any EMI emission by filtering out the harmonics, therefore eliminating the need for an external filter. RECEIVE FUNCTION The received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. This eliminates the need for a 10BASE-T external filter. A Manchester decoder converts the incoming serial stream. Serial-toParallel logic is used to generate the 2-bit data. LINK MONITOR The 10BASE-T link-pulse detection circuit constantly monitors the RXIP/RXIN pins for the presence of valid link pulses. In the absence of valid link pules, the Link Status bit is cleared and the Link LED de-asserts. 100BASE-TX Configured to run in 100BASE-TX mode, either through hardware configuration, software configuration or Aneg. TRANSMIT FUNCTION In 100BASE-TX mode, the PHY transmit function converts synchronous 2-bit data to a pair of 125-Mbps differential serial data streams. The serial data is transmitted over network twisted pair cables via an isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel to serial, NRZ to NRZI, and MLT-3 encoding. The entire operation is synchronous to 25 MHz and 125 MHz clock. Both clocks are generated by an on-chip PLL clock synthesizer that is locked on to an Bro adco m C orp or atio n Page 2 Section 1: Functional Description Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 external 25 MHz clock source. The transmit data is transmitted from the MAC to the PHY via the TXD[1:0] signals. The 4B/5B encoder replaces the first two nibbles of the preamble from the MAC frame with a /J/K/ code-group pair Start-of-Stream Delimiter (SSD), following the onset of TX_EN signal. The 4B/5B encoder appends a /T/R/ code-group pair End-of-Stream Delimiter (ESD) to the end of transmission in place of the first two IDLE code-groups that follow the negation of the TX_EN signal. The encapsulated data stream is converted from 4-bit nibbles to 5-bit code groups. During the inter-packet gap, when there is no data present, a continuous stream of IDLE code groups are transmitted. When TX_ER is asserted while TX_EN is active, the Transmit Error code-group /H/ is substituted for the translated 5B code word. The 4B/5B encoding is bypassed when Reg. 21.1 is set to 1, or the PCSBP pin is strapped high. In 100BASE-TX mode, the 5-bit transmit data stream is scrambled as defined by the TP-PMD Stream Cipher function in order to reduce radiated emissions on the twisted pair cable. The scrambler encodes a plain text NRZ bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function: X[n] = X[n-11] + X[n-9] (modulo 2) The scrambler reduces peak emissions by randomly spreading the signal energy over the transmitted frequency range, thus eliminating peaks at any single frequency. For repeater applications, where all ports transmit the same data simultaneously, signal energy is spread further by using a non-repeating sequence for each PHY, i.e., the scrambled seed is unique for each different PHY based on the PHY address. PARALLEL TO SERIAL, NRZ TO NRZI, AND MLT3 CONVERSION The 5-bit NRZ data is clocked into PHY's shift register with a 25 MHz clock, and clocked out with a 125 MHz clock to convert it into a serial bit stream. The serial data is converted from NRZ to NRZI format, which produces a transition on Logic 1 and no transition on Logic 0. To further reduce EMI emissions, the NRZI data is converted to an MLT-3 signal. The conversion offers a 3dB to 6dB reduction in EMI emissions. This allows system designers to meet the FCC Class B limit. When there is a transition occurring in NRZI data, there is a corresponding transition occurring in the MLT-3 data. For NRZI data, it changes the count up/down direction after every single transition. For MLT-3 data, it changes the count up/down direction after every two transitions.The NRZI to MLT-3 data conversion is implemented without reference to the bit timing or clock information. The conversion requires detecting the transitions of the incoming NRZI data and setting the count up/down direction for the MLT-3 data. The slew rate of the transmitted MLT-3 signal can be controlled to reduce EMI emissions. The MLT-3 signal after the magnetic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the ANSI TP- PMD standard. This is guaranteed with either 1:1 or 1.25:1 transformer. RECEIVE FUNCTION The 100BASE-TX receive path functions as the inverse of the transmit path. The receive path includes a receiver with adaptive equalization and DC restoration in the front end. It also includes a MLT-3 to NRZI converter, 125 MHz data and clock recovery, NRZI/NRZ conversion, Serial-to-Parallel conversion, de-scrambler, and 5B/4B decoder. The receiver circuit starts with a DC bias for the differential RX+/- inputs, followed with a low-pass filter to filter out high frequency noise from the transmission channel media. An energy detect circuit is also added to determine whether there is any signal energy on the media. This is useful in the power-saving mode. The amplification ratio and slicer's threshold is set by the on-chip bandgap reference. BASELINE WANDER COMPENSATION The 100BASE-TX data stream is not always DC balanced. The transformer blocks the DC components of the incoming signal, thus the DC offset of the differential receive inputs can drift. The shifting of the signal level, coupled with non-zero rise and fall times of the serial stream can cause pulse-width distortion. This creates jitter and possible increase in the bit error rates. Therefore, a DC restoration circuit is needed to compensate for the attenuation of the DC component. This PHY implements a patent-pending DC restoration circuit. Unlike the traditional implementation, the circuit does not need the feedback information from the slicer or the clock recovery circuit. This design simplifies the circuit design and eliminates any B roa dcom Document AC104L-DS01-R Section 1: Functional Description Page 3 AC104L Preliminary Data Sheet 06/26/01 random/systematic offset on the receive path. In the 10BASE-T, the baseline wander correction circuit is not required, and therefore is disabled. CLOCK/DATA RECOVERY The equalized MLT-3 signal passes through the slicer circuit, and gets converted to NRZI format. The PHY uses a proprietary mixed-signal phase locked loop (PLL) to extract clock information from the incoming NRZI data. The extracted clock is used to re-time the data stream and set the data boundaries. The transmit clock is locked to the 50 MHz clock input while the receive clock is locked to the incoming data streams. When initial lock is achieved, the PLL switches to the data stream, extracts the 125 MHz clock, and uses it for the bit framing for the recovered data. The PLL requires no external components for its operation and has high noise immunity and low jitter. It provides fast phase alignment and locks to data in one transition. Its data/clock acquisition time after power-on is less than 60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. When no valid data is present, i.e. when the SD is de-asserted, the PLL switches and locks on to REFCLK. At the PCS interface, the 5 bit data RXD[4:0] is synchronized to the 25 MHz RX_CLK. DECODER/DE-SCRAMBLER The de-scrambler detects the state of the transmit Linear Feedback Shift Register (LFSR) by looking for a sequence representing consecutive idle codes. The de-scrambler acquires lock on the data stream by recognizing IDLE bursts of 30 or more bits and locks its frequency to its de-ciphering LFSR. Once lock is acquired, the device operates with an inter-packet-gap (IPG) as low as 40 nS. However, before lock is acquired, the de-scrambler needs a minimum of 270 ns of consecutive idles in between packets in order to acquire lock. The de-ciphering logic also tracks the number of consecutive errors received while the CRS_DV is asserted. When the error counter exceeds its limit currently set to 64 consecutive errors, the logic assumes that the lock has been lost, and the decipher circuit resets itself. The process of regaining lock starts again. Stream cipher de-scrambler is not used in the 10BASE-T modes. LINK MONITOR Signal level is detected through a squelch detection circuitry. A signal detect (SD) circuit allows the equalizer to assert high whenever the peak detector detects a post-equalized signal with peak to ground voltage greater than 400 mV. This is approximately 40% of a normal signal voltage level. In addition, the energy level must be sustained for longer than 2~3 S in order for the signal detect signal to stay on. The SD gets de-asserted approximately 1~2 s after the energy level drops consistently below 300 mV from peak to ground. The link signal is forced low during a local loopback operation (Loopback register bit is set) and forced to high when a remote loopback is taking place (EN_RPBK is set). In forced 100BASE-TX mode, when a cable is unplugged or no valid signal is detected on the receive pair, the link monitor enters in the link fail state and NLPs are transmitted. When a valid signal is detected for a minimum period of time, the link monitor enters Link Pass State and transmits MLT-3 signal. 10BASE-T/100BASE-TX MULTI-MODE TRANSMIT DRIVER The multi-mode driver transmits the MLT-3 coded signal in 100BASE-TX mode and Manchester coded signal in 10BASE-T mode. In 10BASE-T mode, high frequency pre-emphasis is performed to extend the cable-driving distance without the external filter. The FLP and NLP pulses are also drive out through the 10BASE-T driver. The 10BASE-T and 100BASE-TX transmit signals are multiplexed to the transmit output driver. This arrangement results in Bro adco m C orp or atio n Page 4 Section 1: Functional Description Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 using the same external transformer for both the 10BASE-T and the 100BASE-TX. The driver output level is set by a builtin bandgap reference and an external resistor connected to the IBREF pin. The resistor sets the output current for all modes of operation. The TXOP/N outputs are open drain devices with a serial source to I/O pad resistance of 10 max. When the 1:1 transformer is used, the current rating is 40 mA for the 2Vp-p MLT-3 signal, and 100 mA for the 5Vp-p Manchester signal. One can use a 1.25:1 transmit transformer for a 20% output driver power reduction. This decreases the drive current to 32 mA for 100BASE-TX operation, and 80 mA for 10BASE-T operation. ADAPTIVE EQUALIZER The PHY is designed to accommodate a maximum of 150 meters UTP Cat 5 cable. An AT&T 1061 Cat 5 cable of this length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-meter cable is 21 dB. The worst case cable attenuation is around 24-26 dB as defined by TP-PMD specification. The amplitude and phase distortion from the cable cause inter-symbol interference (ISI), which makes clock and data recovery difficult. The adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable. The equalizer has the ability to changes its equalizer frequency response according to the cable length. The equalizer tunes itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable. PLL CLOCK SYNTHESIZER The PHY includes an on-chip PLL clock synthesizer that generates a 125 MHz clocks for the 100BASE-TX circuitry. It also generates 20 MHz and 100 MHz clocks for the 10BASE-T and ANeg circuitry. The PLL clock generator uses a fully differential VCO cell that introduces very low jitter. The Zero Dead Zone Phase Detection method implemented in the PHY design provides excellent phase tracking. A charge pump with charge sharing compensation is also included to further reduce jitter at different loop filter voltages. The on-chip loop filter eliminates the need for external components and minimizes the external noise sensitivity. Only one external 50 MHz crystal or clock source is required as a reference clock. After power-on or reset, the PLL clock synthesizer generates the 20 MHz clock output until the 100BASE-X operation mode is selected. JABBER AND SQE (HEARTBEAT) After the MAC transmitter exceeds the jabber timer (46 ms), the transmit and loopback functions disable and COL signals assert. After TX_EN goes low for more than 500 ms, the TP transmitter reactivates and COL gets de-asserted. Setting Jabber Disable disables the jabber function. When the SQE test is enabled, a COL pulse with 5-15BT is asserted after each transmitted packet. SQE is enabled in 10BASE-T by default, and can be disabled via SQE Test Inhibit. REVERSE POLARITY DETECTION AND CORRECTION Certain cable plants have crossed wiring on the twisted pairs; the reversal of TXIN and TXIP. Under normal circumstances this would cause the receive circuitry to reject all data. When the Auto Polarity Disable bit is cleared, the PHY has the ability to detect the fact that either 8 NLPs or a burst of FLPs are inverted and automatically reverse the receiver's polarity. The polarity state is stored in the Reverse Polarity bit. If the Auto Polarity Disable bit is set, then the Reverse Polarity bit can be written to force the polarity reversal of the receiver. B roa dcom Document AC104L-DS01-R Section 1: Functional Description Page 5 AC104L Preliminary Data Sheet 06/26/01 INITIALIZATION AND SETUP HARDWARE CONFIGURATION Several different states of operation can be chosen through hardware configuration. External pins may be pulled either high or low at reset time. The combination of high and low values determines the power on state of the device. Many of these pins are multi-function pins that change their meaning when reset ends. SOFTWARE CONFIGURATION Several different states of operation can be chosen through software configuration. LEDS Each of the four ports has three individual LED outputs available to indicate Speed, Duplex/Collision, and Link/Activity. These multi-function pins are inputs during reset and LED output pins thereafter. The level of these pins during reset determines their active output states. If a multi-function pin is pulled up during reset to select a particular function, then that LED output would become active low, and the LED circuit must be designed accordingly, and vice versa. AUTO-NEGOTIATION By definition the 10/100 Transceiver is able to run at either 10 Mbps or 100 Mbps. In addition the PHY is able to run in either half-duplex or full-duplex. To determine the operational state, the PHY has hardware selects and software selects while also supporting Auto- Negotiation and Parallel Detection. Legitimate operating states are: * 10BASE-T half-duplex * 10BASE-T full-duplex * 100BASE-TX half-duplex * 100BASE-TX full-duplex The PHY can be hardware configured to force any one of the above modes. By forcing the mode, the PHY only runs in that mode, hence limiting the locations where the product operates. The PHY is able to negotiate its mode of operation using the auto-negotiation mechanism defined in the clause 28 of IEEE 802.3u specification. ANeg can be enabled or disabled by hardware (ANEGA pin) or software (Reg. 0.12) control. When the ANeg is enabled, the PHY chooses its mode of operation by advertising its abilities and comparing them with the ability received from its link partner. It can be configured to advertise 100BASE-TX or 10BASE-T operating in either full-or half-duplex mode. Register 4 contains the current capabilities, speed and duplex, of the PHY, determined through hardware selects or chip defaults. The contents of Register 4 is sent to its link partner during the ANeg process using Fast Link Pulses (FLPs). An FLP is a string of 1s and 0s, each of which has a particular meaning, the total of which is called a link code word. After reset, software can change any of these bits from 1 to 0 and back to 1, but not from 0 to 1. Therefore, the hardware has priority over software. When ANeg is enabled, the PHY sends out FLPs during the following conditions: * Power on * Link loss * Restart ANeg command by software During this period, the PHY continually sends out FLPs while monitoring the incoming FLPs from the link partner to deter- Bro adco m C orp or atio n Page 6 Section 1: Functional Description Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 mine their optimal mode of operation. If FLPs are not detected during this phase of operation, Parallel Detection mode is entered (see below). When the PHY receives three identical link code words (ignoring acknowledge bit) from its link partner, it stores these code words in Register 5, sets the acknowledge bit it the generated FLPs, and waits to receive three identical code word with the acknowledge bit set from the link partner. When this occurs, the PHY configures itself to the highest technology that is common to both ends. The technology priorities are: 1 100BASE-TX, full-duplex 2 100BASE-TX, half-duplex 3 10BASE-T, full-duplex 4 10BASE-T half-duplex. When the ANeg is complete, Register 1.5 is set, Register 1.[14:11] reflects negotiated speed and duplex mode, and the PHY enters the negotiated transmission and reception state. This state does not change until link is lost or the PHY is reset through either hardware or software, or the restart negotiation bit (Reg. 0.9) is set. PARALLEL DETECTION Because there are many devices in the field that do not support the ANeg process, but must still be communicated with, it is necessary to detect and link through the Parallel Detection process. The parallel detection circuit is enabled in the absence of FLPs. The circuit is able to detect: * Normal Link Pulse (NLP) * 10BASE-T receive data * 100BASE-TX idle The mode of operation is configured based on the technology of the incoming signal. If any of the above is detected, the device automatically configures to match the detected operating speed in the half duplex mode. This ability allows the device to communicate with legacy 10BASE-T and 100BASE-TX systems, while maintaining the flexibility of auto-negotiation. DIAGNOSTICS LOOPBACK OPERATION Local loopback is provided for testing purposes. It is enabled by writing to Register 0.14. The local loopback routes transmit data through the transmit path back to the receiving path's clock and data recovery module. The loopback data is presented to the PCS in 5-bit symbol format. This loopback is used to check the operation of the 5-bit symbol decoder and the phase locked loop circuitry. In local loopback, the SD output is forced to logic one and TXOP/ N outputs are tri-stated. CABLE LENGTH INDICATOR In 100BT mode, the PHY can detect the approximate length of the attached cable and display the result in Register 20.[7:4]. A reading of [0000] translates to <10m cable used, [0001] translates to ~10 meter of cable, and [1111] translates to 150m cable. The cable length value can be used by the network manage to determine the proper connectivity of the cable and to manage the cable plant distribution. B roa dcom Document AC104L-DS01-R Section 1: Functional Description Page 7 AC104L Preliminary Data Sheet 06/26/01 RESET AND POWER The PHY can be reset in three ways: * During initial power on. * Hardware Reset: A logic low signal of 150 s pulse width is applied to RST* pin. * Software Reset: Write a one to SMI Reg. 0.15. The power consumption of the device is significantly reduced due to its built-in power management features. Separate power supply lines are used to power the 10BASE-T circuitry and the 100BASE-TX circuitry. Therefore, the two circuits can be turned on and turned off independently. When the PHY is set to operate in 100BASE-TX mode, the 10BASE-T circuitry is powered down, and vice versa. The following power management features are supported: * Power down mode: This can be achieved by writing to Register 0.11 or pulling PWRDN pin high. During power down mode, the device is still be able to interface through the MDC/MDIO management interface. * Energy detect/power saving mode: Energy detect mode turns off the power to select internal circuitry when there is no live network connected. Energy Detect (ED) circuit is always turned on to monitor if there is a signal energy present on the media. The SMI circuitry is also powered on and ready to respond to any management transaction. The transmit circuit still send out link pulses with minimum power consumption. If a valid signal is received from the media, the device powers up and resumes normal transmit/receive operation. (Patent Pending) * Reduced Transmit Drive Strength mode: Additional power saving can be gained at the PHY level by designing with 1.25:1 turns magnetic ratio and asserting the TP125 pin at reset. CLOCK The clock input must have a TTL clock oscillator measured at 50 MHz-100PPM . Bro adco m C orp or atio n Page 8 Section 1: Functional Description Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Section 2: Pin D esc ription CVDD RXD[0](A) RXD[1](A) OVDD TXEN(B) TXD[0](B) TXD[1](B) CGND OGND CRSDV(B) RXER(B) RXD[0](B) RXD[1](B) CVDD REFCLK MDC MDIO TXEN(C) OVDD TXD[0](C) TXD[1](C) OGND CRSDV(C) RXER(C) RXD[0](C) RXD[1](C) CVDD TXEN(D) CGND TXD[0](D) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PIN DIAGRAM Figure 2: 28 29 30 AGND RXIP(D) RXIN(D) AVDD 27 31 AGND 100 26 NC AVDD TXOP(D) 32 25 99 TXON(D) NC GAVDD 24 33 AVDD 98 23 NC GAVDD AVDD 34 22 97 TXON(C) NC IBREF 21 35 TXOP(C) 96 20 NC GAGND AGND NC 36 19 37 95 AGND 94 RST 18 INTR RXIP(C) DPX(D)/SCRAM_EN 17 38 RXIN(C) 93 16 ACT(D)/ANEGA SPD(A)/TP1_1 AVDD SPD(D)/BURN-IN 39 15 40 92 AVDD 91 ACT(A)/CIM_DIS 14 DPX(A)/COL_DIS RXIN(B) DPX(C)/DPLX 13 41 RXIP(B) 90 12 ACT(C) SPD(B)/PHYAD[2] AGND 42 11 89 AGND SPD(C)/FORCE100 ACT(B)/PHYAD[3] 10 43 TXOP(B) 88 9 OVDD DPX(B)/PHYAD[4] TXON(B) RXD[1](D) 44 8 45 87 AVDD 86 OGND 7 TXEN(A) AVDD RXD[0](D) 6 RXER(D)/PHYAD_ST 46 TXON(A) 47 85 5 84 TXD[0](A) TXOP(A) TXD[1](A) 4 CRSDV(D) AGND 48 3 83 AGND CGND CGND 2 49 1 50 82 RXIP(A) 81 RXIN(A) RXER(A) CRSDV(A) TXD[1](D) AC104L 100-pin B roa dcom Document AC104L-DS01-R Section 2: Pin Description Page 9 AC104L Preliminary Data Sheet 06/26/01 PIN DESCRIPTIONS Many of the pins of these devices have multiple functions. Designate the multi-function pins by bolding the pin number. Designers must assure that they have identified all modes of operation prior to final design. The pin assignment shown below and in the pin description table is subject to change without notice. Contact Altima Communications Inc. before implementing any design based on the information provided in this data sheet. Signal types: * I = inputs * O = outputs * Z = high impedance * U = pull up * D = pull down * A = analog signal * * = Active Low Signal * NC = No Connect pin Table 1: MDI (Media Dependent Interface) Pins Pin Name Pin # Type Description RXIN(A) RXIN(B) RXIN(C) RXIN(D) 1 14 17 30 AI AI AI AI Receiver input negative for both 10BASE-T and 100BASE-TX. RXIP(A) RXIP(B) RXIP(C) RXIP(D) 2 13 18 29 AI AI AI AI Receiver input positive for both 10BASE-T and 100BASE-TX. TXON(A) TXON(B) TXON(C) TXON(D) 6 9 22 25 AO AO AO AO Transmitter output negative for both 10BASE-T and 100BASE-TX. TXOP(A) TXOP(B) TXOP(C) TXOP(D) 5 10 21 26 AO AO AO AO Transmitter output positive for both 10BASE-T and 100BASE-TX. Bro adco m C orp or atio n Page 10 Section 2: Pin Description Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 2: RMII (Reduced Media Independent Interface) Pins Pin Name Pin # Type Description TXD[1:0](A) TXD[1:0](B) TXD[1:0](C) TXD[1:0](D) 84, 85 74, 75 60, 61 50, 51 I/O, D I/O, D I/O, D I/O, D RMII Transmit Data. The MAC sources the TXD[1:0](n) synchronous with REFCLK when TX_EN(n) is asserted. TX_EN(A) TX_EN(B) TX_EN(C) TX_EN(D) 86 76 63 53 I/O,D I/O,D I/O,D I/O,D RMII Transmit Enable. TX_EN(n) is asserted high by the MAC to indicate that valid data for transmission is presented on the TXD[1:0](n). RXD[1:0](A) RXD[1:0](B) RXD[1:0](C) RXD[1:0](D) 78,79 68,69 55,56 45,46 I/O, D I/O, D I/O, D I/O, D RMII Receive Data. The PHY sources the RXD[1:0](n) synchronous with REFCLK when CRS_DV(n) is asserted. CRS_DV(A) CRS_DV(B) CRS_DV(C) CRS_DV(D) 82 71 58 48 I/O, D I/O, D I/O, D I/O, D CRS_DV(n) is asserted high when media is non-idle. RX_ER(A) RX_ER(B) RX_ER(C) RX_ER(D) 81 70 57 47 I/O,D O O I/O,D RMII Receive Error. When RX_ER is asserted high, it indicates an error has been detected during frame reception. REFCLK 66 I Reference Clock Input - 50 MHz-100PPM TTL Table 3: SMI ( Serial Management Interface) Pins Pin Name Pin # Type Description MDIO 64 I/O, D Management Data Input/Output. Bi-directional data interface. 1.5K pull up resistor required (as specified in IEEE-802.3). MDC 65 I, D Management Data Clock. 0 to 25 MHz clock sourced by the MAC for transfer of MDIO data. INTR 94 Z Interrupt. See Register 17. The INTR pin has a high impedance output. A 1K Resister pull-up is required for this active low signal. B roa dcom Document AC104L-DS01-R Section 2: Pin Description Page 11 AC104L Preliminary Data Sheet 06/26/01 Table 4: PHY Address Pins Pin Name Pin # Type Description PHYAD_ST 47 I/O,D This pin sets the two least significant digits of the PHY address for all four ports according to the two options below: 1 at reset = A-XXX00, B-XXX01, C-XXX10, D-XXX11 0 at reset = A-XXX01, B-XXX10, C-XXX11, D-XXX00 PHYAD [4] PHYAD [3] PHYAD [2] 88 89 90 I/O I/O I/O PHY Address [4:2]. These pins set the three most significant digits for the PHY address. PHYAD [4] sets the most significant digit. PHYAD [1:0] are internally set according to the status of PHYAD_ST. The PHYAD determines the scramble seed, and helps to reduce EMI when there are multiple ports switching at the same time. Table 5: Mode Pins Pin Name Pin # Type Description TP125 93 I/O Transformer Ratio. Pulled low upon resets the select transmit transformer ratio to be 1.25:1. Pulled high is 1:1 transformer. DPLX 41 I/O Full Duplex Mode. When asserted high, the PHY operates in full-duplex mode as determined through Auto-Negotiation or software. When asserted low, the internal control bit (Reg.0.8) will determine the full-duplex operating mode. FORCE100 43 I/O FORCE100: Force 100BASE-TX Operation. When this signal is pulled high and ANEGA is low upon reset, all ports are forced to 100BASE-TX operation. When asserted low and ANEGA is low, all ports are forced to 10BASE-T operation. When ANEGA is high, FORCE100 has no effect on operation. SCRAM_EN 38 I/O Scrambler Enable. Pulled high under normal circumstances to enable scrambler and de-scrambler. If pulled low upon reset, scrambling functions will be disabled. ANEGA 39 I/O Auto-Negotiation Ability. Asserted high means auto-negotiation enable while low means manual selection through DPLX, FORCE100. BURN_IN* 40 I/O Burn-In mode. Burn-in mode for reliability assurance control. This is reserved for factory testing only. CIM_DIS 92 I/O Carrier Integrity Monitor Disable.Pulled low upon reset enables the CIM function. This function may be overwritten under software control. COL_DIS 91 I/O If pulled high with 10k, LEDDPX pins toggles when there is a Collision detected in half duplex. If pulled low, LEDDPX pins does not toggle. Bro adco m C orp or atio n Page 12 Section 2: Pin Description Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 6: LED Pins Pin Name Pin # Type Description LEDDPX[A] LEDDPX[B] LEDDPX[C] LEDDPX[D] 91 88 41 38 I/O I/O I/O I/O Port[n] Duplex LED. Active state indicates Full Duplex. In half duplex, this pin is designed to blink to indicate collision. However, this feature can be masked by pulling the LED_MASK pin low. LEDACT_LNK[A] LEDACT_LNK[B] LEDACT_LNK[C] LEDACT_LNK[D] 92 89 42 39 I/O I/O I/O I/O Port[n] Activity/Link LED. Active state indicates a valid link. When there is receive or transmit activity, LED toggles between high and low for 30 ms interval. Pin 42 must be pulled high via an external resistor of value between 1k to 10k ohm. LEDSPD[A] LEDSPD[B] LEDSPD[C] LEDSPD[D] 93 90 43 40 I/O I/O I/O I/O Port[n] Speed LED. Active state indicates 100BASE-TX mode. Polarity of LEDs is determined by polarity of mode pins. Table 7: Miscellaneous Pins Pin Name Pin # Type Description RST* 95 I, U Reset. An active low input forces a known initialization state. The reset pulse duration must be > 100 us. Setting MII Reg. 0.15 asserts software reset, which has the same functionality as the hardware reset. IBREF 97 A Reference Bias Resistor. Must be tied to analog ground through an external 10K (1%) resistor. Table 8: Power and Ground Pins Pin Name Pin # Type Description OVDD 44, 62, 77 P Digital +3.3V power supply for I/O. OGND 52, 72, 87 G Digital ground for I/O. CVDD 54, 67, 80 P Digital +3.3V power supply for core logic. CGND 49, 59, 73, 83 G Digital ground for core logic. AVDD 7, 8, 15, 16, 23, 24, 31, 100 P +3.3V power supply for analog circuit. AGND 3, 4, 11, 12, 19, 20, 27, 28 G Ground for analog circuit. GAVDD 98,99 P +3.3V power supply for common analog circuits. GAGND 96 G Ground for common analog circuits. B roa dcom Document AC104L-DS01-R Section 2: Pin Description Page 13 AC104L Preliminary Data Sheet 06/26/01 Section 3 : R egis ter De scr iptions The first seven registers of the MII register set are defined by the MII specification. In addition to these required registers are several Altima Communications Inc. specific registers. There are reserved registers and/or bits that are for Altima internal use only. The following standard registers are supported. Register numbers are in decimal format; the values are in hex format. When writing to registers it is recommended that a read/modify/write operation be performed, as unintended bits may get to unwanted states. This applies to all registers, including those with reserved bits. LEGEND RW Read and Write Access SC Self Clearing LL Latch Low until cleared by reading RO Read Only RC Cleared on Read LH Latch High until cleared by reading Table 9: Registers 0-7 Register Description Default 0 Control Register 3000 1 Status Register 7849 2 PHY Identifier 1 Register 0022 3 PHY Identifier 2 Register 5523 4 Auto-Negotiation Advertisement Register 01E1 5 Auto-Negotiation Link Partner Ability Register 0001 6 Auto-Negotiation Expansion Register 0004 7 Next Page Advertisement Register 2001 Bro adco m C orp or atio n Page 14 Section 3: Register Descriptions Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 10: Registers 8-31 Register Description Default 8-15 Reserved XXXX 16 BT and Interrupt Level Control Register 03C0 17 Interrupt Control/Status Register 0000 18,19 Reserved XXXX 20 Cable measurement capability Register XXXX 21 Receive Error Counter Register 0304 22-31 Reserved XXXX Table 11: Register 0: Control Bit Name Description Mode Default 0.15 Reset 1 = PHY reset. This bit is self-clearing. RW/SC 0 0.14 Loopback 1 = Enable loopback mode. This loopbacks the TXD to RXD and ig- RW nores all the activity on the cable media. 0 = Normal operation. 0 0.13 Speed Select 1 = 100 Mbps 0 = 10 Mbps. RW Set by a mode pin 0.12 ANeg Enable 1 = Enable Auto-Negotiate process (overrides 0.13 and 0.8) 0 = Disable Auto-Negotiate process. Mode selection is controlled via bit 0.8, 0.13 or through the mode pins. RW Set by ANEGA 0.11 Power Down 1 = Power down. All blocks except for SMI turns off. Setting PWRDN pin to high achieves the same result. 0 = Normal operation. RW 0 0.10 Isolate 1 = Electrically isolate the PHY from MII. PHY is still able to response to SMI. 0 = Normal operation. RW 0.9 Restart ANeg 1 = Restart Auto-Negotiation process. 0 = Normal operation. RW/SC 0 0.8 Duplex Mode 1 = Full duplex. 0 = Half duplex. RW Set by a mode pin 0.7 Collision Test 1 = Enable collision test, which issues the COL signal in response RW to the assertion of TX_EN signal. Collision test is disabled if PCSBP pin is high. Collision test is enabled regardless of the duplex mode. 0 = Disable COL test. 0.[6:0] Reserved RW 0 0000000 B roa dcom Document AC104L-DS01-R Section 3: Register Descriptions Page 15 AC104L Preliminary Data Sheet 06/26/01 Table 12: Register 1: Status Bit Name Description Mode Default 1.15 100BASE-T4 Permanently tied to zero indicates no 100BASE-T4 capability. RO 0 1.14 100BASE-TX Full Duplex 1 = 100BASE-TX full-duplex capable. 0 = Not 100BASE-TX full-duplex capable. RO Set by a mode pin 1.13 100BASE-TX Half Duplex 1 = 100BASE-TX half-duplex capable. 0 = Not TX half-duplex capable. RO Set by a mode pin 1.12 10BASE-T Full Duplex 1 = 10BASE-T full-duplex capable. 0 = Not 10BASE-T full-duplex capable. RO Set by a mode pin 1.11 10BASE-T Half Duplex 1 = 10BASE-T half-duplex capable. 0 = Not 10BASE-T half-duplex capable. RO Set by a mode pin 1.[10:7] Reserved RO 0000 1.6 MF Preamble Suppression The PHY is able to perform management transaction without MDIO preamble. The management interface needs minimum of 32 bits of preamble after reset. RO 1 1.5 ANeg Complete 1 = Auto-negotiate process completed. Reg. 4, 5, 6 are valid after this bit is set. 0 = Auto-negotiate process not completed. RO 0 1.4 Remote Fault 1 = Remote fault condition detected. 0 = No remote fault. This bit remains set until it is cleared by reading register 1. RO/LH 0 1.3 ANeg Ability 1 = Able to perform Auto-Negotiation function, default value determined by ANEGA pin. 0 = Unable to perform Auto-Negotiation function. RO ANEGA 1.2 Link Status 1 = Link is established. If link fails, this bit clears and remains at 0 until register is read again. 0 = Link has gone down. RO/LL 0 1.1 Jabber Detect 1 = Jabber condition detect. 0 = No Jabber condition detected. RO/LH 0 1.0 Extended Capability 1 = Extended register capable. This bit is tied permanently to one. RO Table 13: 1 Register 2: PHY Identifier 1 Reg.bit Name Description Mode Default 2.[15:0] OUI* Composed of the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. RO 0022(H) * = Based on an OUI is 0010A9 (Hex) Bro adco m C orp or atio n Page 16 Section 3: Register Descriptions Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 14: Register 3: PHY Identifier 2 Bit Name Description Mode Default 3.[15:10] OUI Assigned to the 19th through 24th bits of the OUI. RO 010101 3.[9:4] Model Number 6-bit manufacturer's model number. RO 010100 3.[3:0] Revision Number 4-bit manufacturer's revision number. RO 0010 * = Based on an OUI of 0010A9 (Hex) Table 15: Register 4: Auto-Negotiation Advertisement Bit Name Description Mode Default 4.15 Next Page 1 = Next Page enabled. 0 = Next Page disabled. RW 0 4.14 Acknowledge This bit will be set internally after receiving 3 consecutive and consistent FLP bursts. RO 0 4.[13:11] Reserved 4.10 FDFC Full-Duplex Flow Control 1= Advertise that the DTE(MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0= MAC does not support flow control 4.9 100BASE-T4 Technology not supported. This bit always 0 RO 0 4.8 100BASE-TX Full Duplex 1 = 100BASE-TX full-duplex capable. 0 = Not 100BASETX full-duplex capable. RW Set by a mode pin 4.7 100BASE-TX 1 = 100BASE-TX half-duplex capable. 0 = Not TX half-duplex capable. RW Set by a mode pin 4.6 10BASE-T Full Duplex 1 = 10BASE-T full-duplex capable. 0 = Not 10BASE-T full-duplex capable. RW Set by a mode pin 4.5 10BASE-T 1 = 10BASE-T half-duplex capable. 0 = Not 10BASE-T half-duplex capable. RW Set by a mode pin 4.[4:0] Selector Field Protocol Selection [00001] = IEEE 802.3. RO 00001 0 B roa dcom Document AC104L-DS01-R Section 3: Register Descriptions Page 17 AC104L Preliminary Data Sheet 06/26/01 Table 16: Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Bit Name Description Mode Default 5.15 Next Page 1 = Link partner desires Next Page transfer. 0 = Link partner does not desire Next Page transfer. RO 0 5.14 Acknowledge 1 = Link Partner acknowledges reception of FLP words. 0 = Not acknowledged by Link Partner. RO 0 5.[13:10] Reserved 5.9 100BASE-T4 1 = 100BASE-T4 supported by Link Partner. 0 = 100BASE-T4 not supported by Link Partner. RO 0 5.8 100BASE-TX Full Duplex 1 = 100BASE -X full-duplex supported by Link Partner. 0 = 100BASE-TX full-duplex not supported by Link Partner. RO 0 5.7 100BASE-TX 1 = 100BASE-TX half-duplex supported by Link Partner. 0 = 100BASE-TX half-duplex not supported by Link Partner. RO 0 5.6 10BASE-T Full Duplex 1 = 10 Mbps full-duplex supported by Link Partner. 0 = 10 Mbps full-duplex not supported by Link Partner. RO 0 5.5 10BASE-T 1 = 10 Mbps half-duplex supported by Link Partner. 0 = 10 Mbps half-duplex not supported by Link Partner. RO 0 5.[4:0] Selector Field Protocol Selection [00001] = IEEE 802.3. RO 00001 Mode Default RO 0 *When this register is used as Next Page Message, the bit definition is the same as Register 7. Table 17: Register 6: Auto-Negotiation Expansion Bit Name Description 6.[15:5] Reserved 6.4 Parallel Detection Fault 1 = Fault detected by parallel detection logic, this fault is due to RO/LH more than one technology detecting concurrent link up condition. This bit can only be cleared by reading Register 6, using the management interface. 0 = No fault detected by parallel detection logic. 0 6.3 Link Partner Next Page Able 1 = Link partner supports next page function. 0 = Link partner does not support next page function. RO 0 6.2 Next Page Able Next Page is supported. RO 1 6.1 Page Received This bit is set when a new link code word has been received into the Auto-Negotiation Link Partner Ability Register. This bit is cleared upon a read of this register. RC 0 6.0 Link Partner ANeg-Able 1 = Link partner is Auto-Negotiation capable. 0 = Link partner is not Auto-Negotiation capable. RO 0 Bro adco m C orp or atio n Page 18 Section 3: Register Descriptions Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 18: Register 7: Auto-Negotiation Next Page Transmit Bit Name Description Mode Default 7.15 NP 1 = Another Next Page desired. 0 = No other Next Page Transfer desired. RW 0 7.14 Reserved RO 0 7.13 MP 1 = Message page. 0 = Un-formatted page. RW 1 7.12 ACK2 1 = Will comply with message. 0 = Can not comply with message. RW 0 7.11 TOG_TX 1 = Previous value of transmitted link code word equals to 0. 0 = Previous value of transmitted link code word equals to 1. RW 0 17.[10:0] CODE Message/Un-formatted Code Field. RW 001 Mode Default RW 0 RW 0 Table 19: Register 16: BT and Interrupt Level Control Bit Name Description 16.15 Reserved 16.14 INTR_LEVL 16.13 Reserved RW 0 16.12 Reserved RW 0 16.11 SQE Test Inhibit RW 0 16.[10:6] Reserved RO 0 16.5 Auto Polarity Disable 1 = Disable Auto Polarity detection/correction. 0 = Enable Auto Polarity detection/correction. RW 0 16.4 Reverse Polarity 1= Reverse Polarity when Register 16.5 = 0 0= Normal Polarity when Register 16.5 = 0 If Register 16.5 is set to 1, writing a one to this bit will reverse the polarity of the transmitter. RW 0 16.[3:0] Reserved RO 0 1=INTR pin will be active high. 0=INTR pin will be active low. 1 = Disable 10BASE-T SQE testing. 0 = Enable 10BASE-T SQE testing, which generates a COL pulse following the completion of a packet transmission. B roa dcom Document AC104L-DS01-R Section 3: Register Descriptions Page 19 AC104L Preliminary Data Sheet 06/26/01 Table 20: Register 17: Interrupt Control/Status Bit Name Description Mode Default 17.15 Jabber_IE Jabber Interrupt Enable. RW 0 17.14 Rx_Er_IE Receive Error Interrupt Enable. RW 0 17.13 Page_Rx_IE Page Received Interrupt Enable. RW 0 17.12 PD_Fault_IE Parallel Detection Fault Interrupt Enable. RW 0 17.11 LP_Ack_IE Link Partner Acknowledge Interrupt Enable. RW 0 17.10 Link_Status_Change_IE Link Status Change Interrupt Enable. RW 0 17.9 R_Fault_IE Remote Fault Interrupt Enable. RW 0 17.8 ANeg_Comp_IE Auto-Negotiation Complete Interrupt Enable. RW 0 17.7 Jabber_Int This bit is set when a jabber event is detected. RC 0 17.6 Rx_Er_Int This bit is set when RX_ER transitions high. RC 0 17.5 Page_Rx_Int This bit is set when a new page is received during ANeg. RC 0 17.4 PD_Fault_Int This bit is set when parallel detect fault is detected. RC 0 17.3 LP_Ack_Int This bit is set when the FLP with acknowledge bit set is received. RC 0 17.2 Link_Not_OK Int This bit is set when link status switches from OK status to Non-OK status (Fail or Ready). RC 0 17.1 R_Fault_Int This bit is set when remote fault is detected. RC 0 17.0 ANeg _Comp Int This bit is set when ANeg is complete. RC 0 Bro adco m C orp or atio n Page 20 Section 3: Register Descriptions Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 21: Register 19: Power/Loopback Bit Name Description Mode Default 19.[14:7] Reserved Reserved RW 00 19.6 TP125 Transmit transformer ratio selection. 1 = 1.25:1 0 = 1:1 The default value of this bit is controlled by the TP125 pin. RW 0 19.5 Disable watch dog timer for decipher. 1 = Disable watch dog timer. 0 = Enable advanced power saving mode. RW 0 19.4 Low power mode disable. 1 = Disable advanced power saving mode. 0 = Enable advanced power saving mode. RW 0 19.3 Enable digital loopback. RW 1 19.2 Reserved RW 0 19.1 Reserved RW 0 19.0 Jabber disable. RW 0 Reserved 1 = disable jabber. Table 22: Register 20: Cable Measurement Capability Bit Name Description Mode Default 20.15 Reserved Reserved RW 1 20.14 Reserved RW 1 20.[13:9] Reserved RO 0 20.8 Adaptation disable 1 = Disable adaptation RW 0 20.[7:4] Cable measurement capability These bits can be used as cable length indicator. The bits in- RW crement from 0000 to 1111, with an increment of approximately 10 meters. The equivalent is 0 to 32 dB with an increment of 2 dB @ 100 MHz. The value is a read back from the equalizer, and the measured value is not absolute. X 20.[3:0] Adaptation low limit value. RO X Table 23: Register 21: Receive Error Counter Bit Name Description Mode Default 21.[15:0] RX_ER Counter Count Receive Error Events. RO 0 B roa dcom Document AC104L-DS01-R Section 3: Register Descriptions Page 21 AC104L Preliminary Data Sheet 06/26/01 Table 24: 4B/5B Code-Group Table PCS Code Group[4:0] Symbol Name MII (TXD/RXD [3:0]) Description 11110 0 0000 Data 0 01001 1 0001 Data 1 10100 2 0010 Data 2 10101 3 0011 Data 3 01010 4 0100 Data 4 01011 5 0101 Data 5 01110 6 0110 Data 6 01111 7 0111 Data 7 10010 8 1000 Data 8 10011 9 1001 Data 9 10110 A 1010 Data A 10111 B 1011 Data B 11010 C 1100 Data C 11011 D 1101 Data D 11100 E 1110 Data E 11101 F 1111 Data F 11111 I 0000 Inter-Packet Idle; used as inter-stream fill code. 11000 J 0101 Start of stream delimiter, part 1 of 2; always use in pair with K symbol. 10001 K 0101 Start of stream delimiter, part 2 of 2; always use in pair with J symbol. 01101 T Undefined End of stream delimiter, part 1 of 2; always use in pair with R symbol. 00111 R Undefined End of stream delimiter, part 2 of 2; always use in pair with T symbol. 00100 H Undefined Transmit Error; used to send HALT code group 00000 V Undefined Invalid code 00001 V Undefined Invalid code 00010 V Undefined Invalid code Page 22 Section 3: Register Descriptions Idle and Control Code Invalid Code Bro adco m C orp or atio n Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 24: 4B/5B Code-Group Table (Cont.) PCS Code Group[4:0] Symbol Name MII (TXD/RXD [3:0]) Description 00011 V Undefined Invalid code 00101 V Undefined Invalid code 00110 V Undefined Invalid code 01000 V Undefined Invalid code 01100 V Undefined Invalid code 10000 V Undefined Invalid code 11001 V Undefined Invalid code Table 25: SMI Read/Write Sequence SMI Read/Write Sequence Pream (32 bits) Start (2 bits) OpCode (2 bits) PHYAD (5 bits) REGAD (5 bits) TurnAround (2 bits) Data (16 bits) Idle Read 1...1 01 10 AAAAA RRRRR Z0 D...D Z Write 1...1 01 01 AAAAA RRRRR 10 D...D Z B roa dcom Document AC104L-DS01-R Section 3: Register Descriptions Page 23 AC104L Preliminary Data Sheet 06/26/01 Table 26: Mode LEDDPX 10M Link LED Configurations LEDACT LEDSPD ON OFF 10M HDX Transmit OFF TOGGLE OFF 10M HDX Receive OFF TOGGLE OFF 10 HDX Collision ON during collision TOGGLE OFF 10M FDX Transmit ON TOGGLE OFF 10M FDX Receive ON TOGGLE OFF ON ON 100M Link 100M HDX Transmit OFF TOGGLE ON 100M HDX Receive OFF TOGGLE ON 100 HDX Collision ON during collision TOGGLE ON 100M FDX Transmit ON TOGGLE ON 100M FDX Receive ON TOGGLE ON Vcc 300 10K Multi Function LED pin pulled high for reset. 300 Multi Function LED pin pulled low for reset. 10K Figure 3: LED Configurations Bro adco m C orp or atio n Page 24 Section 3: Register Descriptions Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Se ction 4: Electr ic al C ha rac te ristics NOTE: The following electrical characteristics are design goal rather than characterized numbers. ABSOLUTE MAXIMUM RATINGS Storage Temperature...............................-55oC to +150oC Vcc Supply Referenced to GND............. -0.5V to +5.0V Digital Input Voltage................................. -0.5V to Vcc DC Output Voltage.................................. ..-0.5V to Vcc OPERATING RANGE Operating Temperature (Ta) ............................ 0oC to +70oC Vcc Supply Voltage Range (Vcc) ......................2.97V to 3.63V Table 27: DC Characteristics (0oC < Ta < 70oC, 2.97V < VCC < 3.63V, unless otherwise noted) Parameter SYM Conditions Power Supply Current for all 4 ports Icc Power Consumption for all 4 ports PS Min Typ Max Units 10 BASE-T, idle 10 BASE-T, normal activity traffic ~50% util. 10 BASE-T, Peak continuous 100% utilization 100 BASE-TX 10/100 BASE-TX, low power without cable Auto-Negotiation Power down 95 290 115 310 520 360 85 80 1 mA 10BASE-T, idle 10BASE-T, normal activity 10BASE-T, Peak 100BASE-TX 10/100BASE-TX, low power with out cable Auto-Negotiation Power down 314 693 380 1040 1683 1188 280 264 3.3 mW TTL Input High Voltage Vih TTL Input Low Voltage Vil TTL Input Current Iin TTL Input Capacitance CIin Output High Voltage Voh 3.15V < Vcc < 3.45V, IoH = 8 mA Output Low Voltage Vol 3.15V < Vcc < 3.45V, IoL = 2 mA 348 75 68 1148 248 224 2.0 Vcc = 3.45V V -10 0.8 V 10 A 10 pF Vcc-0.4 V 0.4 V B roa dcom Document AC104L-DS01-R Section 4: Electrical Characteristics Page 25 AC104L Preliminary Data Sheet 06/26/01 Table 27: DC Characteristics (0oC < Ta < 70oC, 2.97V < VCC < 3.63V, unless otherwise noted) (Cont.) Parameter SYM Conditions Min Typ Max Output Transition Time T r, T f . 3.15V < Vcc < 3.45V LED Output Current IOH 16 mA Output Tristate Leakage Current |Ioz| 10 A 40 mA 5 Units ns Transmitter, 100BASE-TX (1:1 Transformer Ratio) TX+/- Output Current High IOH TX+/- Output Current Low IOL A 0 Transmitter, 10BASE-T (1:1 Transformer Ratio) TX+/- Output Current High IOH TX+/- Output Current Low IOL 100 mA A 0 Transmitter, 100BASE-TX (1.25:1 Transformer Ratio) TX+/- Output Current High IOH TX+/- Output Current Low IOL 32 mA A 0 Transmitter, 10BASE-T (1.25:1 Transformer Ratio) TX+/- Output Current High IOH TX+/- Output Current Low IOL 80 mA A 0 Receiver, 100BASE-TX RX+/- Common-mode input voltage 1.8 V RX+/- Differential input resistance 20 k RX+/- Common-mode input current 10 A Receiver, 10BASE-T Differential Input Resistance 20 k Bro adco m C orp or atio n Page 26 Section 4: Electrical Characteristics Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 28: AC Characteristics (0oC < Ta < 70oC, 2.97V < VCC < 3.63V, unless otherwise noted) Parameter SYM Conditions Min Typ Max Units Differential Output Voltage, peak-to-peak VOD 50 from each output to Vcc, Best-fit over 14 bit times 1.9 2.0V 2.1 V Differential Output Voltage Symmetry VOS 50 from each output to Vcc, |Vp+|/|Vp-| 0.98 1.02 mV Differential Output Overshoot VOO Percent of Vp+ or Vp- 5 % Rise/Fall time tr, tf 10 - 90% of Vp+ or Vp- 5 ns Rise/Fall time imbalance |tr, - tf| 500 ps Transmitter, 100BASE-TX 3 4 Duty Cycle Distortion Deviation from best-fit time-grid, 010101 ... Sequence +250 ps Timing jitter Unscrambled Idle 1.4 ns 5.5 V Transmitter, 10BASE-T Differential Output Voltage, peak-to-peak VOD 50 from each output to Vcc, all pattern 4.5 THD VHD dB below fundamental, all ones data 27 5 dB Start-of-idle Pulse Width 350 ns 2.1 V Receiver, 100BASE-TX RXOP/N Differential input voltage, peak-to-peak 1.9 2 Baseline Wander Tracking 500 mV Clock Recovery Pull-in time 5 s Jitter Tolerance (pk-to-pk) 2 ns 300 mV Signal Detect Turn-on Threshold (Post equalized) SDon Signal Detect Assertion Time 200 s Signal Detect Deassertion Time 1.4 s B roa dcom Document AC104L-DS01-R Section 4: Electrical Characteristics Page 27 AC104L Preliminary Data Sheet 06/26/01 Table 29: AC Characteristics (0oC < Ta < 70oC, 2.97V < VCC < 3.63V, unless otherwise noted) Parameter SYM Conditions Min Typ Max Units Receiver, 10BASE-T Clock Recovery Pullin time 2 s Jitter Tolerance (pkto-pk) 32 ns Input Squelched Threshold 300 400 500 mV Input Un-squelched Threshold 100 150 200 mV Programmable Equalizer, 100BASE-TX Equalizer Output Voltage <1% THD 2 Equalizer Output Offset Noise Feed-through Vp-p 5 mV 10 mVrms 50 55 % 50 100 PPM 100 MHz bandwidth Frequency Synthesizer Input clock duty cycle From input reference oscillator. Input Clock Jitter PPM Clk_125 Frequency fclk125 45 Required jitter tolerance from reference oscillator. 125 TX_CLK, Clock Duty Cycle 45 PLL Acquisition Time 50 MHz 55 % 50 s Bro adco m C orp or atio n Page 28 Section 4: Electrical Characteristics Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 Table 30: Digital Timing Characteristics (0oC <Ta <70oC, 2.97V < Vdd < 3.63V) Parameter SYM Conditions Min Typ Max Units Active TX_EN Sampled to first bit of "J" on MDI output 4 18 bits Inactive TX_EN Sampled to first bit of "T" on MDI output 4 bits 100BASE-TX Transmit System Timing TX_EN sampled to CRSDV assert RPTR is logic low 4 bits TX_EN sampled to CRSDV de-assert RPTR is logic low 4 bits From TXD[3:0] to TXOP/N 4 bits TX Propagation Delay tTXpd 100BASE-TX Receive System Timing First bit of "J" on MDI input to CRSDV assert 14 22 bits First bit of "T" on MDI input to CRSDV de-assert 20 First bit of "J" on MDI input to COL assert 14 First bit of "T" on MDI input to COL de-assert 20 bits bits 22 bits RX Propagation Delay tRXpd From RXIP/N to RDTX[3:0] 12 bits RXD[1:0] Output Delay tRXd RSC25 rise to RDTX[3:0] valid time 25 ns RST Low Period tRSTl 10 s B roa dcom Document AC104L-DS01-R Section 4: Electrical Characteristics Page 29 AC104L Preliminary Data Sheet 06/26/01 Table 31: Digital Timing Characteristics (0oC <Ta <70oC, 2.97V < Vdd < 3.63V) Parameter SYM Conditions Min Typ Max Units 10BASE-T System Timing Carrier Sense Turn-on Delay tCSON 300 ns Carrier Sense Turn-off Delay tCSOFF 160 ns Decoder Acquisition Time tDAT 950 ns Differential Inputs Rejection Pulse Width tDREJ 30 ns Collision Turn-on Delay tCOLON 900 ns Collision Turn-off Delay tCOLOFF 160 ns SQE Test Start Delay tSQEON 0.6 1.0 1.6 ms SQE Test Duration tSQED 0.5 1.0 1.5 ms Setup time relative to the rising edge of REFCLK. 4 - - ns Hold time relative to the rising edge of REFCLK. - 0 2 ns RXD data output delay relative to rising edge of REFCLK - - 12 ns Setup time relative to the rising edge of REFCLK. 4 - - ns Hold time relative to the rising edge of REFCLK. - 0 2 ns RXD data output delay relative to rising edge of REFCLK - - 12 ns 8 20 100BASE-TX System Timing 10BASE-T System Timing Bro adco m C orp or atio n Page 30 Section 4: Electrical Characteristics Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 W rite C y c le MDC 2 .5 M H z T10 T9 M D IO D A T A Figure 4: MDC/MDIO Timing Diagram 1 R e a d C y c le MDC 2 .5 M H z T11 M D IO D A T A Figure 5: MDC/MDIO Timing Diagram 2 Table 32: MDC/MDIO Timing Parameter SYM Conditions Min Typ Max Unit Setup time relative to the rising edge of MDC. T9 MDC is a 2.5 MHz output clock from the MAC controller. 10 - - ns Hold time relative to the rising edge of MDC. T10 MDC is a 2.5 MHz output clock from the MAC controller. - - 10 ns Output delay relative to the rising edge of MDC. T11 MDC is a 2.5 MHz output clock from the MAC controller. 0 20 300 ns B roa dcom Document AC104L-DS01-R Section 4: Electrical Characteristics Page 31 AC104L Preliminary Data Sheet 06/26/01 RECOMMENDED TERMINATION Contact Altima Communications Inc. for the latest component value recommendations. 0.1 F 49.9 AC104L 49.9 3.3V RJ45 Transformer TXON TXOP TXC_P TX+_P TX-_P TXC_S TX+_S TX-_S IBREF RX+_P RX-_P RXC_P RX+_S RX-_S RXC_S 10 K 1% RXIP 1 TX+ 2 TX3 RX+ 4 Unused 5 Unused 6 RX7 Unused 8 Unused 0.1 F 49.9 1% 49.9 1% 75 X 4 0.1 F 1000 pF 3 KV RXIN Chassis GND Figure 6: Termination Figure Bro adco m C orp or atio n Page 32 Section 4: Electrical Characteristics Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 POWER AND GROUND FILTERING Contact Altima Communications Inc. for the latest component value recommendations. Ground Power .1uf Cap Components placed < 3mm from pin 83 87 96 98 99 100 80 3 4 77 7 8 73 72 AC104L-QF AC104LKQM 11 12 15 16 19 20 62 23 24 59 27 28 54 52 49 44 31 Figure 7: Power and Ground B roa dcom Document AC104L-DS01-R Section 4: Electrical Characteristics Page 33 AC104L Preliminary Data Sheet 06/26/01 Section 5: Packag e Drawing Table 33: Package Drawing N A A1 A2 B D D1 E E1 e L L1 100 3.40 max 0.25 min 2.70 + 0.2 0.3 + 0.1 23.20 + 0.25 20.00 + 0.10 17.20 + 0.25 14.00 + 0.10 0.65 0.88 + 0.2 1.60 + 0.12 AC104LKQM Figure 8: Package Drawing Bro adco m C orp or atio n Page 34 Section 5: Package Drawing Document AC104L-DS01-R AC104L Preliminary Data Sheet 06/26/01 S e c t i on 6: O rd e r i n g I nfo r m a t io n Part Number Package Ambient Temperature AC104LKQM 100 pin PQFP 0C to 70C B roa dcom Document AC104L-DS01-R Section 6: Ordering Information Page 35 AC104L Preliminary Data Sheet 06/26/01 Altima Communications, Inc. A Wholly Owned Subsidiary of Broadcom Corporation 16215 Alton Parkway P.O. Box 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710 Broadcom Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. Document AC104L-DS01-R