THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER WITH RAIL-TO-RAIL OUTPUTS FEATURES * * * * * * * * * * * * DESCRIPTION Fully Differential Architecture With Rail-to-Rail Outputs Centered Input Common-mode Range Minimum Gain of 1 V/V (0 dB) Bandwidth: 620 MHz Slew Rate: 570 V/s 0.1% Settling Time: 7 ns HD2: -115 dBc at 100 kHz, VOD = 8 VPP HD3: -123 dBc at 100 kHz, VOD = 8 VPP Input Voltage Noise: 2 nV/Hz (f >10 kHz) Output Common-Mode Control Power Supply: - Voltage: 3.3 V (1.65 V) to 5 V (2.5 V) - Current: 14.2 mA Power-Down Capability: 15 A APPLICATIONS * * * * * 5-V and 3.3-V Data Acquisition Systems High Linearity ADC Amplifier Wireless Communication Test and Measurement Voice Processing Systems The THS4520 is a wideband, fully differential operational amplifier designed for 5-V data acquisition systems. It has very low noise at 2 nV/Hz, and low harmonic distortion of -115 dBc HD2 and -123 dBc HD3 at 100 kHz with 8 VPP, and 1-k load. The slew rate is 570 V/s, and with a settling time of 7 ns to 0.1% (2-V step), it is ideal for data acquisition applications. It is designed for unity gain stability. To allow for dc coupling to ADCs, its unique output common-mode control circuit maintains the output common-mode voltage within 0.25 mV offset (typical) from the set voltage. The common-mode set point defaults to mid-supply by internal circuitry, which may be over-driven from an external source. The input and output are optimized for best performance with their common-mode voltages set to mid-supply. Along with high performance at low power supply voltage, this makes for extremely high performance single supply 5-V and 3.3-V data acquisition systems. The THS4520 is offered in a Quad 16-pin leadless QFN package (RGT), and is characterized for operation over the full industrial temperature range from -40C to 85C. THS4520 HARMONIC DISTORTION vs FREQUENCY RELATED PRODUCTS BW (MHZ) Slew Rate (V/sec) THD (dBc) VN (nV/Hz) -60 THS4509 2000 6600 -102 at 10 MHz 1.9 -70 THS4500 370 2800 -82 at 8 MHz 7 THS4130 150 52 -97 at 250 kHz 1.3 499 W 2.5 V 499 W + Differential Input - VID Differential 1 kW Output - V OD - Harmonic Distortion - dBc Device VOD = 8 VPP, G = -1, RL = 1 KW, VS = 2.5 V -80 -90 -100 -110 HD3 -120 HD2 -130 + 499 W -140 -2.5 V VOCM = open 499 W 1 100 10 f - Frequency - kHz 1000 Measured HD2/HD3 for G = -1, VOD = 8 VPP, RL = 1 K (circuit shown on the left) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2007, Texas Instruments Incorporated THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) UNIT VS- to VS+ Supply voltage 6V VI Input voltage VS VID Differential input voltage IO Output current 4V (1) 200 mA Continuous power dissipation TJ See Dissipation Rating Table Maximum junction temperature 150C Maximum junction temperature, continuous operation, long term reliability 125C TA Operating free-air temperature range -40C to 85C Tstg Storage temperature range -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ESD ratings (1) 300C HBM 2000 CDM 1500 MM 100 The THS4520 incorporates a (QFN) exposed thermal pad on the underside of the chip. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the QFN thermally enhanced package. DISSIPATION RATINGS TABLE PER PACKAGE (1) 2 PACKAGE (1) JC JA RGT (16) 2.4C/W 39.5C/W POWER RATING TA 25C TA = 85C 2.3 W 225 mW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Submit Documentation Feedback THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 DEVICE INFORMATION RGT Package (TOP VIEW) VS- 16 15 14 13 NC 1 12 PD VIN- 2 11 VIN+ VOUT+ 3 10 VOUT- CM 4 9 5 7 6 CM 8 VS+ TERMINAL FUNCTIONS TERMINAL (RGT PACKAGE) NO. DESCRIPTION NAME 1 NC No internal connection 2 VIN- Inverting amplifier input 3 VOUT+ Non-inverted amplifier output 4, 9 CM Common-mode voltage input 5, 6, 7, 8 VS+ Positive amplifier power supply input 10 VOUT- Inverted amplifier output 11 VIN+ Non-inverting amplifier input 12 PD Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation. If the PD pin is open (unterminated) the device will default to the enabled state. 13, 14, 15, 16 VS- Negative amplifier power supply input Submit Documentation Feedback 3 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 SPECIFICATIONS; VS+ - VS- = 5 V: Test conditions unless otherwise noted: VS+ = +2.5 V, VS- = -2.5 V, G = 0 dB, CM = open, VO = 2 VPP, RF = 499 , RL = 200 Differential, TA = 25C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Small-Signal Bandwidth G = 0 dB, VO = 100 mVPP 620 MHz G = 6 dB, VO = 100 mVPP 450 MHz G = 10 dB, VO = 100 mVPP 330 MHz G = 20 dB, VO = 100 mVPP 120 MHz 1200 MHz Gain-Bandwidth Product G = 20 dB Bandwidth for 0.1 dB flatness G = 6 dB, VO = 2 VPP 30 MHz Large-Signal Bandwidth G = 6 dB, VO = 2 VPP 132 MHz 570 V/s Slew Rate (Differential) Rise Time Fall Time 4 2-V Step 4 Settling Time to 1% 6.2 Settling Time to 0.1% ns C 7 f = 100 kHz (3) f = 1 MHz (4) RL = 1 k VOD = 8 VPP -115 RL = 200 VOD = 2 VPP -100 RL = 1 k 2nd Order Harmonic Distortion (2) RL = 200 f = 8 MHz (3) f = 100 kHz -93 VOD = 2 VPP -101 VOD = 4 VPP -101 VOD = 2 VPP -103 -97 VOD = 2 VPP -100 VOD = 4 VPP -95 RL = 1 k VOD = 8 VPP -123 RL = 200 VOD = 2 VPP -105 f = 1 MHz (4) RL = 1 k 3rd Order Harmonic Distortion (2) VOD = 4 VPP VOD = 4 VPP (4) RL = 1 k RL = 200 f = 8 MHz (4) RL = 1 k VOD = 4 VPP -93 VOD = 2 VPP -101 VOD = 4 VPP -96 VOD = 2 VPP -92 VOD = 4 VPP -88 VOD = 2 VPP -102 VOD = 4 VPP -91 fC = 100 kHz (3), 10-kHz Tone Spacing, RL = 1k , VOD = 8 VPP envelope, G = 0dB 3rd Order Intermodulation Distortion C fC = 1 MHz (4), 100-kHz Tone Spacing, RL = 200 , VOD = 4 VPP envelope, G = 10dB dBc C dBc C dBc C -135 -82 (4) fC = 10 MHz , 100-kHz Tone Spacing, RL = 200 , VOD = 4 VPP envelope, G = 10dB Input Voltage Noise f > 10 kHz 2 nV/Hz Input Current Noise f > 10 kHz 2 pA/Hz (1) (2) (3) (4) 4 -82 Test levels: (A) 100% tested at 25C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. For additional information, see the Typical Characteristics section and the Apllications section. Data collected with applied differential input signal and measured differential output signal. Data collected with applied single-ended input signal and measured differential output signal. See Figure 55 in the Applications/Test Circuits section for additional information. Submit Documentation Feedback THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 SPECIFICATIONS; VS+ - VS- = 5 V: (continued) Test conditions unless otherwise noted: VS+ = +2.5 V, VS- = -2.5 V, G = 0 dB, CM = open, VO = 2 VPP, RF = 499 , RL = 200 Differential, TA = 25C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) dB C DC PERFORMANCE Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift Input Offset Current Average Offset Current Drift 112 TA = 25C 0.25 2.5 mV TA = -40C to 85C 0.25 3 mV TA = -40C to 85C 1 TA = 25C 6.5 10 TA = -40C to 85C 6.4 11 TA = -40C to 85C 1.9 TA = 25C 0.2 2.5 TA = -40C to 85C 0.2 3 TA = -40C to 85C 1.6 A V/C B A A nA/C B A A nA/C B INPUT Common-Mode Input Range High 1.75 Common-Mode Input Range Low -1.3 Common-Mode Rejection Ratio V 84 B dB Differential Input Impedance 7.5||0.31 k||pF C Common-Mode Input Impedance 2.67||0.7 7 M||pF C OUTPUT TA = 25C Maximum Output Voltage High Each output with 100 to mid-supply Minimum Output Voltage Low TA = -40C to 85C 1.95 2.16 1.9 2.16 TA = 25C -2.16 TA = -40C to 85C -2.16 7.8 V -1.95 -1.9 A V Differential Output Voltage Swing TA = -40C to 85C 8.64 V Differential Output Current Drive RL = 10 105 mA Output Balance Error VO = 100 mV, f = 1 MHz -80 dB 230 MHz 1 V/V C OUTPUT COMMON-MODE VOLTAGE CONTROL Small-Signal Bandwidth Gain Output Common-Mode Offset from CM input 1.25 V < CM < 3.5 V 0.25 mV CM Input Bias Current 1.25 V < CM < 3.5 V 0.6 A CM Input Voltage CM Default Voltage -1.5 CM = 0.5 (VS+ + VS- ) 1.5 0 C V V POWER SUPPLY Specified Operating Voltage Maximum Quiescent Current Minimum Quiescent Current 5 5.25 TA = 25C 3 14.2 15.3 TA = -40C to 85C 14.2 15.5 TA = 25C TA = -40C to 85C Power Supply Rejection (PSRR) POWERDOWN Referenced to Vs- Enable Voltage Threshold For additional information, see the Application Information section of this data sheet. Disable Voltage Threshold Powerdown Quiescent Current 13.1 14.2 12.75 14.2 94 dB >1.5 V <-1.5 V 15 70 TA = -40C to 85C 15 75 C mA mA TA = 25C Submit Documentation Feedback V A A C A 5 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 SPECIFICATIONS; VS+ - VS- = 3.3 V: Test conditions unless otherwise noted: VS+ = +1.65 V, VS- = -1.65 V, G = 0 dB, CM = open, VO = 1 VPP, RF = 499 , RL = 200 Differential, TA = 25C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Small-Signal Bandwidth G = 0 dB, VO = 100 mVPP 600 MHz G = 6 dB, VO = 100 mVPP 400 MHz G = 10 dB, VO = 100 mVPP 310 MHz G = 20 dB, VO = 100 mVPP 120 MHz 1200 MHz Gain-Bandwidth Product G = 20 dB Bandwidth for 0.1 dB flatness G = 6 dB, VO = 1 VPP 30 MHz Large-Signal Bandwidth G = 0 dB, VO = 1 VPP 210 MHz 320 V/s Slew Rate (Differential) Rise Time Fall Time 4 2-V Step 4 Settling Time to 1% 6.6 Settling Time to 0.1% RL = 1 k RL = 200 f = 1 MHz (4) RL = 1 k 2nd Order Harmonic Distortion (2) RL = 200 f = 8 MHz (4) RL = 1 k (3) f = 100 kHz RL = 1 k RL = 200 f = 1 MHz (4) RL = 1 k 3rd Order Harmonic Distortion (2) RL = 200 f = 8 MHz (4) RL = 1 k 3 Order Intermodulation Distortion VOD = 4 VPP -135 VOD = 1 VPP -107 VOD = 2 VPP -101 VOD = 1 VPP -97 VOD = 2 VPP -103 VOD = 1 VPP -108 VOD = 2 VPP -106 VOD = 1 VPP -98 VOD = 2 VPP -99 VOD = 4 VPP -146 VOD = 1 VPP -112 VOD = 2 VPP -105 VOD = 1 VPP -94 VOD = 2 VPP -103 VOD = 1 VPP -95 VOD = 2 VPP -90 VOD = 1 VPP -95 VOD = 2 VPP -102 fC = 1 MHz (4), 100-kHz Tone Spacing, RL = 200 , VOD = 4 VPP envelope, G = 10dB -80 fC = 10 MHz (4), 100-kHz Tone Spacing, RL = 200 , VOD = 4 VPP envelope, G = 10dB -80 C dBc C dBc C f > 10 kHz 2 nV/Hz Input Current Noise f > 10 kHz 2 pA/Hz (2) (3) (4) C dBc Input Voltage Noise (1) 6 ns 7.1 f = 100 kHz (3) rd C Test levels: (A) 100% tested at 25C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. For additional information, see the Typical Characteristics section and the Apllications section. Data collected with applied differential input signal and measured differential output signal. Data collected with applied single-ended input signal and measured differential output signal. See Figure 55 in the Applications/Test Circuits section for additional information. Submit Documentation Feedback THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 SPECIFICATIONS; VS+ - VS- = 3.3 V: (continued) Test conditions unless otherwise noted: VS+ = +1.65 V, VS- = -1.65 V, G = 0 dB, CM = open, VO = 1 VPP, RF = 499 , RL = 200 Differential, TA = 25C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) DC PERFORMANCE Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift Input Offset Current Average Offset Current Drift 104 dB TA = 25C 0.25 mV TA = -40C to 85C 0.25 mV TA = -40C to 85C 1 TA = 25C 6.5 TA = -40C to 85C 6.4 TA = -40C to 85C 1.9 TA = 25C 0.2 TA = -40C to 85C 0.2 TA = -40C to 85C 1.6 C V/C A C nA/C A C nA/C INPUT Common-Mode Input Range High 1.4 Common-Mode Input Range Low -0.45 Common-Mode Rejection Ratio 84 V C dB OUTPUT Maximum Output Voltage High Minimum Output Voltage Low Each output with 100 to mid-supply TA = 25C 1.4 TA = 25C -1.4 Differential Output Voltage Swing Differential Output Current Drive RL = 10 Output Balance Error VO = 100 mV, f = 1 MHz V 5.6 V 78 mA -80 dB 224 MHz 1 V/V C C OUTPUT COMMON-MODE VOLTAGE CONTROL Small-Signal Bandwidth Gain Output Common-Mode Offset from CM input 1.25 V < CM < 3.5 V 0.25 mV CM Input Bias Current 1.25 V < CM < 3.5 V 0.6 A CM Default Voltage CM = 0.5 (VS+ + VS- ) 0 V C POWER SUPPLY Specified Operating Voltage Quiescent Current TA = 25C Power Supply Rejection (PSRR) POWERDOWN Referenced to Vs- Enable Voltage Threshold For additional information, see the Application Information section of this data sheet. Disable Voltage Threshold Powerdown Quiescent Current Submit Documentation Feedback 3.3 V 13 mA 94 dB >1 V <-1 V 10 A C C C 7 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 TYPICAL CHARACTERISTICS TYPICAL AC PERFORMANCE: VS+ - VS- = 5 V Test conditions unless otherwise noted: VS+ = +2.5 V, VS- = -2.5 V, CM = open, VO = 2 VPP, RF = 499 , RL = 200 Differential, G = 0 dB, Single-Ended Input, Input and Output Referenced to Midrail Small-Signal Frequency Response Figure 1 Large Signal Frequency Response Harmonic Distortion (1) Figure 2 HD2 vs Frequency, VO = 2 VPP Figure 3 HD3 vs Frequency, VO = 2 VPP Figure 4 HD2 vs Frequency, VO = 4 VPP Figure 5 HD3 vs Frequency, VO = 4 VPP Figure 6 HD2 vs Output Voltage Swing, f = 1 MHz Figure 7 HD3 vs Output Voltage Swing, f = 1 MHz Figure 8 HD2 vs Output Voltage Swing, f = 8 MHz Figure 9 HD3 vs Output Voltage Swing, f = 8 MHz Figure 10 HD2 vs Load Resistance, f = 1 MHz Figure 11 HD3 vs Load Resistance, f = 1 MHz Figure 12 HD2 vs Load Resistance, f = 8 MHz Figure 13 HD3 vs Load Resistance, f = 8 MHz Figure 14 HD2 vs Output common-mode voltage Figure 15 HD3 vs Output common-mode voltage Figure 16 0.1 dB Flatness Figure 17 S-Parameters vs Frequency Figure 18 Slew Rate vs Output Voltage Figure 19 Gain = 6 dB, VO = 4 VPP Figure 20 Transient Response Gain = 6 dB, VO = 2 VPP Figure 21 Output Voltage Swing vs Load Resistance Figure 22 Input Offset Voltage vs Input Common-Mode Voltage Figure 23 Input Bias Current vs Supply Voltage Figure 24 Open Loop Gain and Phase vs Frequency Figure 25 Input Referred Noise vs Frequency Figure 26 Quiescent Current vs Supply Voltage Figure 27 Power Supply Current vs Supply Voltage in Powerdown Mode Figure 28 Output Balance Error vs Frequency Figure 29 CM Small-Signal Frequency Response CM Input Bias Current vs CM Input Voltage Figure 31 Differential Output Offset Voltage vs CM Input Voltage Figure 32 Output Common-Mode Offset vs CM Input Voltage Figure 33 (1) 8 Figure 30 For additional plots, see the Applications section. Submit Documentation Feedback THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 SMALL-SIGNAL FREQUENCY RESPONSE 22 RF = 499 W 20 G = 20 dB 18 Signal Gain - dB 10 G = 10 dB 6 G = 6 dB 4 2 -2 G = 14 dB 12 10 G = 10 dB 8 6 G = 6 dB 2 G = 0 dB G = 0 dB 0 0.1 1 10 f - Frequency - MHz 100 -2 1000 0.1 1 10 f - Frequency - MHz Figure 2. HD2 vs FREQUENCY VO = 2VPP HD3 vs FREQUENCY VO = 2VPP 1000 -50 -60 3rd Order Harmonic Distortion - dBc RF = 499 W, VO = 2 VPP, VS = 2.5 V -70 -80 RL = 2 kW RL = 500 W -90 RL = 1 kW -100 RF = 499 W, VO = 2 VPP, VS = 2.5 V -60 RL = 200 W -70 -80 RL = 2 kW RL = 1 kW -90 -100 RL = 200 W RL = 500 W -110 -110 10 f - Frequency - MHz 1 1 100 10 f - Frequency - MHz Figure 3. Figure 4. HD2 vs FREQUENCY VO = 4VPP HD3 vs FREQUENCY VO = 4VPP 100 -50 -50 RF = 499 W, VO = 4 VPP, VS = 2.5 V -60 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc 100 Figure 1. -50 2nd Order Harmonic Distortion - dBc 14 4 0 RL = 200 W VO = 2 VPP VS = 2.5 V 16 G = 14 dB 8 G = 20 dB 18 14 12 RF = 499 W 20 RL = 200 W VO = 100 mVPP VS = 2.5 V 16 Signal Gain - dB LARGE-SIGNAL FREQUENCY RESPONSE 22 -70 RL = 200 W -80 RL = 2 kW RL = 500 W -90 -100 RF = 499 W, VO = 4 VPP, VS = 2.5 V -60 -70 RL = 2 kW RL = 500 W -80 RL = 1 kW -90 -100 RL = 200 W RL = 1 kW -110 -110 1 10 f - Frequency - MHz 100 1 Figure 5. 10 f - Frequency - MHz 100 Figure 6. Submit Documentation Feedback 9 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 HD2 vs OUTPUT VOLTAGE SWING FREQUENCY = 1MHz HD3 vs OUTPUT VOLTAGE SWING FREQUENCY = 1MHz -50 RF = 499 W, VS = 2.5 V, f = 1 MHz -60 RL = 100 W -70 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -50 RL = 500 W -80 RL = 2 kW RL = 1 kW -90 RL = 200 W -100 -110 -120 2 3 4 5 6 VO - Output Voltage Swing - VPP 7 -80 RL = 2 kW R = 1 kW L -90 -100 RL = 500 W -110 8 RL = 100 W RL = 200 W 1 2 3 4 5 6 VO - Output Voltage Swing - VPP 7 Figure 7. Figure 8. HD2 vs OUTPUT VOLTAGE SWING FREQUENCY = 8MHz HD3 vs OUTPUT VOLTAGE SWING FREQUENCY = 8MHz 8 -75 -75 RF = 499 W, VS = 2.5 V, f = 8 MHz -80 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -70 -120 1 -85 RL = 1 kW -90 RL = 2 kW RL = 100 W -95 -100 RL = 500 W -105 RL = 200 W -110 RF = 499 W, VS = 2.5 V, f = 8 MHz -80 -85 RL = 100 W RL = 2 kW RL = 200 W -90 -95 RL = 500 W -100 RL = 1 kW -105 -110 1 2 3 4 5 VO - Output Voltage Swing - VPP 6 1 2 3 4 5 VO - Output Voltage Swing - VPP Figure 9. Figure 10. HD2 vs LOAD RESISTANCE FREQUENCY = 1MHz HD3 vs LOAD RESISTANCE FREQUENCY = 1MHz -85 6 -85 -90 VO = 4 VPP -95 -100 -105 VO = 6 VPP 3rd Order Harmonic Distortion - dBc RF = 499 W, VS = 2.5 V, f = 1 MHz VO = 6 VPP 2nd Order Harmonic Distortion - dBc RF = 499 W, VS = 2.5 V, f = 1 MHz -60 -90 VO = 4 VPP RF = 499 W, VS = 2.5 V, f = 1 MHz -95 -100 VO = 2 VPP -105 -110 VO = 2 VPP -115 -110 0 500 1000 1500 RL - Load Resistance - W 2000 0 1000 RL - Load Resistance - W Figure 11. 10 500 Figure 12. Submit Documentation Feedback 1500 2000 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 HD2 vs LOAD RESISTANCE FREQUENCY = 8MHz HD3 vs LOAD RESISTANCE FREQUENCY = 8MHz -80 VO = 6 VPP RF = 499 W, VS = 2.5 V, f = 8 MHz -85 VO = 4 VPP VO = 6 VPP 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -80 -90 -95 -100 VO = 2 VPP -105 -110 VO = 4 VPP -90 VO = 2 VPP -95 RF = 499 W, VS = 2.5 V, f = 8 MHz -100 -105 0 500 1000 1500 RL - Load Resistance - W 0 2000 HD3 vs OUTPUT COMMON-MODE VOLTAGE -70 RL = 200 W, VO = 2 VPP, VS = 2.5 V 16 MHz 8 MHz -90 2 MHz -95 4 MHz -100 1 MHz -1.25 -0.75 -0.25 0.25 0.75 1.25 RF = 499 W, -75 RL = 200 W, VO = 2 VPP, -80 VS = 2.5 V 8 MHz -90 -95 4 MHz -105 1 MHz -1.25 -0.75 0.1-dB FLATNESS 1.25 1.75 S-PARAMETERS vs FREQUENCY Gain = 6 dB, RF = 499 W, RL = 200 W, VO = 2 VPP, VS = 2.5 V 0 S21 -10 S-Parameters - dB Signal Gain - dB 0.75 10 6.1 6 5.9 5.8 -20 -30 -40 S11 -50 -60 5.7 S22 Gain = 0 dB RF = 499 W S12 RL = 200 W VO = 100 mVPP VS = 2.5 V -70 5.6 5.5 0.1 0.25 Figure 16. 6.5 6.2 -0.25 VOCM - Output Common-Mode Voltage - V Figure 15. 6.3 2 MHz -100 -110 -1.75 1.75 16 MHz -85 VOCM - Output Common-Mode Voltage - V 6.4 2000 HD2 vs OUTPUT COMMON-MODE VOLTAGE -85 -105 -1.75 1500 Figure 14. 3rd Order Harmonic Distortion - dBc -80 1000 Figure 13. RF = 499 W, -75 500 RL - Load Resistance - W -70 2nd Order Harmonic Distortion - dBc -85 -80 1 10 f - Frequency - MHz 100 1000 -90 1 10 100 1000 f - Frequency - MHz Figure 17. Figure 18. Submit Documentation Feedback 11 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 SLEW RATE vs OUTPUT VOLTAGE TRANSIENT RESPONSE 2.5 V OD - Differential Output V oltage - V 600 550 Slew Rate - V/ms 500 450 400 350 Gain = 6 dB RF = 499 W 300 RL = 200 W VS = 2.5 V 250 200 2 1.5 1 VOD = 4 VPP VS = 2.5 V Gain = 6 dB RL = 200 W -0.5 0 -0.5 -1 -1.5 -2 -2.5 0 1 3 5 6 7 2 4 VOD - Differential Output Voltage - VPP 8 t - Time - 5 ns/div Figure 19. Figure 20. TRANSIENT RESPONSE OUTPUT VOLTAGE SWING vs LOAD RESISTANCE 10 VOD - Differential Output Voltage - V V OD - Differential Output V oltage - V 1.5 1 VOD = 2 VPP VS = 2.5 V Gain = 6 dB RL = 200 W -0.5 0 -0.5 -1 -1.5 9 VS = 5 V 8 7 6 5 4 3 2 1 0 10 t -Time - 5 ns/div 100 RL - Load Resistance - W Figure 21. Figure 22. INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE INPUT BIAS CURRENT vs SUPPLY VOLTAGE 1000 7.5 0 o -0.05 IIB - Input Bias Voltage - mA VIO - Input Offset Voltage - mV 7 o TA = 85 C -0.1 -0.15 o TA = 25 C -0.2 o TA = -40 C -0.25 TA = 25oC TA = 85 C 6.5 6 5.5 o TA = -40 C 5 4.5 4 3.5 -0.3 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 VS - Supply Voltage - V 2.3 2.4 2.5 3 1.5 Figure 23. 12 1.6 1.7 1.8 1.9 2 2.1 2.2 VS - Supply Voltage - V Figure 24. Submit Documentation Feedback 2.3 2.4 2.5 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 OPEN LOOP GAIN AND PHASE vs FREQUENCY 120 40 -80 60 40 -120 20 -160 100 1 10 k 10 In Vn -200 10 G 100 M 1M Vn - Voltage Noise - nV/ Hz -40 I n - Current Noise - pA/ Hz Phase Open Loop Phase - degrees 0 Gain 80 1 10 1k 100 100 k 1M Figure 25. Figure 26. QUIESCENT CURRENT vs SUPPLY VOLTAGE POWER SUPPLY CURRENT vs SUPPLY VOLTAGE IN POWER-DOWN MODE 15 10 14.5 9 o TA = 85 C 14 TA = 25oC Power Supply Current - mA IQ - Quiescent Current - mA 10 k f - Frequency - Hz f - Frequency - Hz 13.5 13 12.5 o TA = -40 C 12 11.5 11 10.5 8 TA = 85oC 7 6 TA = 25oC 5 4 o TA = -40 C 3 2 1 10 1.5 1.75 2 2.25 VS - Supply Voltage - V 0 1.5 2.5 1.75 2 2.25 VS - Supply Voltage - V Figure 27. OUTPUT BALANCE ERROR vs FREQUENCY CM SMALL SIGNAL FREQUENCY RESPONSE -40 RL = 200 W VO = 1 VPP VS = 2.5 V Gain = 6 dB -50 -60 Gain = 0 dB -70 -80 -90 0.1 1 10 f - Frequency - MHz 100 1000 VOCM - Signal Gain - dB RF = 499 W -30 2.5 Figure 28. -20 Balance Error - dB Open Loop Gain - dB 100 0 INPUT REFERRED NOISE vs FREQUENCY 100 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 RF = 499 W RL = 200 W Gain = 0 dB VO = 100 mVPP VS = 2.5 V 0.1 1 10 100 1000 f - Frequency - MHz Figure 29. Figure 30. Submit Documentation Feedback 13 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs CM INPUT VOLTAGE CM INPUT BIAS CURRENT vs CM INPUT VOLTAGE 4 Differential Output Offset Voltage - mV Common-Mode Input Bias Current - mA 200 150 100 50 0 -50 -100 -150 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 VICR - Common-Mode Input Voltage - V 2 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -2.5 2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 VICR - Common-Mode Input Voltage - V Figure 31. Figure 32. OUTPUT COMMON-MODE OFFSET vs CM INPUT VOLTAGE Output Common-Mode Offset - mV 50 40 30 20 10 0 -10 -20 -30 -40 -50 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 VICR - Common-Mode Input Voltage - V Figure 33. 14 Submit Documentation Feedback 2 2.5 2 2.5 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 TYPICAL AC PERFORMANCE: VS+ - VS- = 3.3 V Test conditions unless otherwise noted: VS+ = 1.65 V, VS- = -1.65 V, CM = open, VOD = 1 VPP, RF = 499 , RL = 200 Differential, G = 0 dB, Single-Ended Input, Input and Output Referenced to Midrail Small-Signal Frequency Response Figure 34 Large Signal Frequency Response Harmonic Distortion (1) Figure 35 HD2 vs Frequency Figure 36 HD3 vs Frequency Figure 37 HD2 vs Output Voltage Swing, f = 1 MHz Figure 38 HD3 vs Output Voltage Swing, f = 1 MHz Figure 39 HD2 vs Output Voltage Swing, f = 8 MHz Figure 40 HD3 vs Output Voltage Swing, f = 8 MHz Figure 41 HD2 vs Load Resistance, f = 1 MHz Figure 42 HD3 vs Load Resistance, f = 1 MHz Figure 43 HD2 vs Load Resistance, f = 8 MHz Figure 44 HD3 vs Load Resistance, f = 8 MHz Figure 45 HD2 vs Output common-mode voltage, VO = 2 Vpp Figure 46 HD3 vs Output common-mode voltage, VO = 2 Vpp Figure 47 0.1 dB Flatness Figure 48 S-Parameters vs Frequency Figure 49 Slew Rate vs Output Voltage Figure 50 Gain = 6 dB, VO = 4 Vpp Figure 51 Gain = 6 dB, VO = 2 Vpp Figure 52 Output Balance Error vs Frequency Figure 53 CM Input Impedance vs Frequency Figure 54 Transient Response For additional plots, see the Applications section. SMALL-SIGNAL FREQUENCY RESPONSE 22 18 G = 20 dB VO = 100 mVPP VS = 1.65 V 16 Signal Gain - dB G = 14 dB G = 10 dB 6 4 2 G = 6 dB G = 20 dB VO = 1 VPP VS = 1.65 V 12 G = 14 dB 10 8 G = 10 dB 6 2 G = 0 dB RL = 200 W 14 4 0 -2 18 16 10 8 RF = 499 W 20 RL = 200 W 14 12 LARGE-SIGNAL FREQUENCY RESPONSE 22 RF = 499 W 20 Signal Gain - dB (1) G = 6 dB G = 0 dB 0 0.1 1 10 f - Frequency - MHz 100 1000 -2 0.1 Figure 34. 1 10 100 f - Frequency - MHz 1000 Figure 35. Submit Documentation Feedback 15 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 HD2 vs FREQUENCY VO = 2VPP HD3 vs FREQUENCY VO = 2VPP -50 RF = 499 W, VO = 2 VPP, VS = 1.65 V -60 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -50 -70 -80 RL = 1 kW RL = 2 kW -90 RL = 500 W -100 RF = 499 W, VO = 2 VPP, VS = 1.65 V -60 -70 RL = 200 W -80 RL = 2 kW -90 RL = 500 W -100 RL = 1 kW RL = 200 W -110 -110 10 f - Frequency - MHz 1 1 100 Figure 37. HD2 vs OUTPUT VOLTAGE SWING FREQUENCY = 1MHz HD3 vs OUTPUT VOLTAGE SWING FREQUENCY = 1MHz -70 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -60 RF = 499 W, VS = 1.65 V, f = 1 MHz RL = 200 W -80 RL = 2 kW -90 RL = 500 W RL = 1 kW -100 RL = 100 W -110 RL = 200 W RF = 499 W, VS = 1.65 V, f = 1 MHz -70 RL = 500 W RL = 1 kW RL = 2 kW -80 -90 RL = 100 W -100 -110 -120 -120 1 2 3 4 5 VO - Output Voltage Swing - VPP 6 1 2 3 4 5 VO - Output Voltage Swing - VPP Figure 38. Figure 39. HD2 vs OUTPUT VOLTAGE SWING FREQUENCY = 8MHz HD3 vs OUTPUT VOLTAGE SWING FREQUENCY = 8MHz -60 6 -60 -70 RL = 200 W RL = 500 W RL = 1 kW 3rd Order Harmonic Distortion - dBc RF = 499 W, VS = 1.65 V, f = 8 MHz -65 RL = 2 kW -75 -80 -85 -90 RL = 100 W -95 -100 RF = 499 W, VS = 1.65 V, f = 8 MHz -65 -70 -75 RL = 200 W RL = 500 W RL = 1 kW RL = 2 kW -80 -85 RL = 100 W -90 -95 -100 -105 -105 -110 -110 1 2 3 4 5 VO - Output Voltage Swing - VPP 6 1 Figure 40. 16 100 Figure 36. -60 2nd Order Harmonic Distortion - dBc 10 f - Frequency - MHz 2 3 4 5 VO - Output Voltage Swing - VPP Figure 41. Submit Documentation Feedback 6 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 HD2 vs LOAD RESISTANCE FREQUENCY = 1MHZ HD3 vs LOAD RESISTANCE FREQUENCY = 1MHZ -40 RF = 499 W, VS = 1.65 V, f = 1 MHz -50 -60 -70 -80 VO = 4 VPP VO = 1 VPP -90 -100 -110 VO = 2 VPP -60 -70 VO = 4 VPP -80 VO = 1 VPP -90 -100 VO = 2 VPP -110 -120 -120 0 500 1000 1500 RL - Load Resistance - W 0 2000 500 1000 1500 RL - Load Resistance - W Figure 42. Figure 43. HD2 vs LOAD RESISTANCE FREQUENCY = 8MHZ HD3 vs LOAD RESISTANCE FREQUENCY = 8MHZ -40 2000 -40 RF = 499 W, VS = 1.65 V, f = 8 MHz -50 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc RF = 499 W, VS = 1.65 V, f = 1 MHz -50 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc -40 -60 -70 VO = 4 VPP -80 -90 VO = 2 VPP -100 VO = 1 VPP -110 RF = 499 W, VS = 1.65 V, f = 8 MHz -50 -60 -70 VO = 4 VPP -80 -90 VO = 1 VPP -100 VO = 2 VPP -110 -120 0 500 1000 1500 RL - Load Resistance - W 2000 0 Figure 45. HD2 vs OUTPUT COMMON-MODE VOLTAGE HD3 vs OUTPUT COMMON-MODE VOLTAGE -45 3rd Order Harmonic Distortion - dBc 2nd Order Harmonic Distortion - dBc 2000 -40 16 MHz 8 MHz -50 4 MHz -60 2 MHz 1 MHz -70 -80 -100 1000 1500 RL - Load Resistance - W Figure 44. -40 -90 500 RF = 499 W, RL = 200 W, VO = 2 VPP, VS = 1.65 V -110 -1.25 -1 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 VOCM - Output Common-Mode Voltage - V 1 1.25 16 MHz -50 -55 -60 -65 -70 8 MHz 4 MHz 2 MHz 1 MHz -75 -80 -85 -90 R = 499 W, F -95 R = 200 W, L -100 V = 2 V , O PP -105 VS = 1.65 V -110 -1.25 -0.75 -0.25 0.25 0.75 VOCM - Output Common-Mode Voltage - V Figure 46. 1.25 Figure 47. Submit Documentation Feedback 17 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 0.1 dB FLATNESS S-PARAMETERS vs FREQUENCY 10 Gain = 6 dB, RF = 499 W, RL = 200 W, VO = 1 VPP, VS = 1.65 V 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6 5.9 5.8 5.7 5.6 5.5 0.1 0 S21 -10 S-Parameters - dB Signal Gain - dB 7 6.9 6.8 -20 -30 -40 S11 -50 -60 S22 Gain = 0 dB RF = 499 W S12 RL = 200 W VO = 100 mVPP VS = 1.65 V -70 1 10 f - Frequency - MHz 100 -80 1000 -90 10 1 100 1000 f - Frequency - MHz Figure 48. Figure 49. TRANSITION RATE vs OUTPUT VOLTAGE TRANSIENT RESPONSE 600 V OD - Differential Output V oltage - V 2.5 550 500 Fall 400 350 300 Gain = 6 dB RF = 499 W 250 RL = 200 W VS = 1.65 V V OD - Differential Output V oltage - V 200 1.5 1 VOD = 4 VPP VS = 1.65 V Gain = 6 dB RL = 200 W -0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.5 1.5 2.5 3 3.5 1 2 VOD - Differential Output Voltage - VPP 4 t - Time - 5 ns/div Figure 50. Figure 51. TRANSIENT RESPONSE OUTPUT BALANCE ERROR vs FREQUENCY 1.5 -20 1 -30 RF = 499 W VOD = 2 VPP VS = 1.65 V Gain = 6 dB RL = 200 W -0.5 0 -0.5 -1 Balance Error - dB Slew Rate - V/ms Rise 450 2 -40 RL = 200 W VO = 1 VPP VS = 1.65 V Gain = 0 dB -50 -60 -70 -80 -1.5 t -Time - 5 ns/div -90 0.1 Figure 52. 18 Gain = 6 dB 1 10 f - Frequency - MHz Figure 53. Submit Documentation Feedback 100 1000 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 VOCM - Signal Gain - dB CM SMALL SIGNAL FREQUENCY RESPONSE 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 RF = 499 W RL = 200 W Gain = 0 dB VO = 100 mVPP VS = 1.65 V 0.1 1 10 100 1000 f - Frequency - MHz Figure 54. TEST CIRCUITS The THS4520 is tested with the following test circuits built on the EVM. For simplicity, power supply decoupling is not shown - see layout in the applications section for recommendations. From 50 W Source VIN RG RIT RF RO 0.22 mF 49.9 W CM RIT RF RG RIT 499 34.8 115 Note: The gain setting includes 50- source impedance. Components are chosen to achieve gain and 50- input termination. Table 2. Load Component Values RL VS+ THS4520 GAIN 20 dB RO 1:1 ROT VOUT To 50 W Test Equipment Open VSRF Figure 55. General Test Circuit for Device Testing and Characterization Depending on the test conditions, component values are changed per the following tables, or as otherwise noted. The signal generators used are ac coupled 50- sources and a 0.22-F capacitor and a 49.9- resistor to ground are inserted across RIT on the alternate input to balance the circuit. A split power supply is used to ease the interface to common test equipment, but the amplifier can be operated single-supply as described in the applications section with no impact on performance. Table 1. Gain Component Values GAIN RF RG RIT 0 dB 499 487 53.6 6 dB 499 243 57.6 10 dB 499 147 63.4 14 dB 499 88.7 71.5 RO ROT Atten. 100 25 open 6 dB 200 86.6 69.8 16.8 dB 499 237 56.2 25.5 dB 1 k 487 52.3 31.8 dB 2k 976 51.1 -37.86 Note: The total load includes 50- termination by the test equipment. Components are chosen to achieve load and 50- line termination through a 1:1 transformer. Due to the voltage divider on the output formed by the load component values, the amplifier's output is attenuated in test. The column Atten in Table 2 shows the attenuation expected from the resistor divider. When using a transformer at the output the signal will have slightly more loss, and the numbers will be approximate. Frequency Response The general circit shown in Figure 55 is modified as shown in Figure 56, and is used to measure the frequency response of the device. A network analyzer is used as the signal source and as the measurement device. The output impedance Submit Documentation Feedback 19 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 of the network analyzer is 50 . RIT and RG are chosen to impedance match to 50 , and to maintain the proper gain. To balance the amplifier, a 0.22-F capacitor and 49.9- resistor to ground are inserted across RIT on the alternate input. The output is probed using a high-impedance differential probe across the 100- resistor. The gain is referred to the amplifier output by adding back the 6-dB loss due to the voltage divider on the output. From V IN 50 Source RG R IT RF VS+ 49.9 W RG 0.22 mF THS4520 CM R IT VS- 49.9 W 49.9 W VOUT+ To 50 W Test VOUT- Equipment Open 0.22 mF RF From 50 W Source VIN RF RG R IT Figure 57. S-Parameter, SR, Transient Response, Settling Time, VOUT Swing VS+ 49.9 W RG 0.22 mF 49.9 W THS4520 CM R IT VS- 49.9 W 100 W Output Measured Here With High Impedance Differential Probe Open 0.22 mF RF Figure 56. Frequency Response Test Circuit CM Input The circuit shown in Figure 58 is used to measure the frequency response of the CM input. Frequency response is measured single-ended at VOUT+ or VOUT- with the input injected at VIN, RCM = 0 and RCMT = 49.9 . RF RG S-Parameter, Slew Rate, Transient Response, Settling Time, Output Voltage The circuit shown in Figure 57 is used to measure s-parameters, slew rate, transient response, settling time, and output voltage swing. Because S21 is measured single-ended at the load with 50- double termination, add 12 dB to see the amplifier's output as a differential signal. 0.22 mF RIT VS+ 49.9 W 49.9 W VOUT- RG 0.22 mF THS4520 49.9 W VOUT+ CM RIT RCM VIN VS- 49.9 W RF RCMT Figure 58. CM Input Test Circuit 20 Submit Documentation Feedback To 50-W Test Equipment From 50-W Source THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 APPLICATION INFORMATION APPLICATIONS The following circuits show application information for the THS4520. For simplicity, power supply decoupling capacitors are not shown in these diagrams. For more detail on the use and operation of fully differential op amps see application report Fully-Differential Amplifiers (SLOA054) . Single-Ended Input RF RG VS Differential Output + - VOUT- THS4520 RG - + VOUT+ Differential Input to Differential Output Amplifier The THS4520 is a fully differential op amp, and can be used to amplify differential input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 59 (CM input not shown). The gain of the circuit is set by RF divided by RG. RF Differential Input RG + - VOUT- THS4520 VIN- RG RF Figure 60. Single-Ended Input to Differential Output Amplifier Input Common-Mode Voltage Range Differential Output VS+ V IN+ VS - + VOUT+ VS- The input common-model voltage of a fully differential op amp is the voltage at the '+' and '-' input pins of the op amp. It is important to not violate the input common-mode voltage range (VICR) of the op amp. Assuming the op amp is in linear operation, the differential voltage across the input pins is only a few millivolts at most. So finding the voltage at one input pin determines the input common-mode voltage of the op amp. Figure 59. Differential Input to Differential Output Amplifier Treating the negative input as a summing node, the voltage is given by Equation 1: o ae ae o RG RF / + c VIN- / VIC = cc VOUT + / c R G + R F /o R G + RF o e e (1) Depending on the source and load, input and output termination can be accomplished by adding RIT and RO. To determine the VICR of the op amp, the voltage at the negative input is evaluated at the extremes of VOUT+. Single-Ended Amplifier As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input common-mode voltage of the source. RF Input to Differential Output The THS4520 can be used to amplify and convert single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 60 (CM input not shown). The gain of the circuit is again set by RF divided by RG. Setting the Output Common-Mode Voltage The output common-mode voltage is set by the voltage at the CM pin. The internal common-mode control circuit maintains the output common-mode voltage within 0.25-mV offset (typical) from the set voltage, when set within 0.5 V of mid-supply. If left unconnected, the common-mode set point is set to mid-supply by internal circuitry, which may be over-driven from an external source. Figure 61 is representative of the CM input. The internal CM circuit has about 230 MHz of bandwidth, which is Submit Documentation Feedback 21 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 required for best performance, but it is intended to be a DC bias input pin. Bypass capacitors are recommended on this pin to reduce noise at the output. The external current required to overdrive the internal resistor divider is given by Equation 2: IEXT = 2VCM - (VS + - VS - ) 50 kW (2) where VCM is the voltage applied to the CM pin. VS+ 50 kW I EXT to internal CM circuit CM 50 kW Single-Supply Operation (3 V to 5 V) To facilitate testing with common lab equipment, the THS4520 EVM allows split-supply operation, and the characterization data presented in this data sheet was taken with split-supply power inputs. The device can easily be used with a single-supply power input without degrading the performance. Figure 62, Figure 63, and Figure 64 show DC and AC-coupled single-supply circuits with single-ended inputs. These configurations all allow the input and output common-mode voltage to be set to mid-supply allowing for optimum performance. The information presented here can also be applied to differential input sources. In Figure 62, the source is referenced to the same voltage as the CM pin (VCM). VCM is set by the internal circuit to mid-supply. RT along with the input impedance of the amplifier circuit provides input termination, which is also referenced to VCM. Note RS and RT are added to the alternate input from the signal input to balance the amplifier. Alternately, one resistor can be used equal to the combined value RG+ RS||RT on this input. This is also true of the circuits shown in Figure 63 and Figure 64. V S- Figure 61. CM Input Circuit Powerdown Operation: Device Enable/Disable Thresholds The enable/disable thresholds of the THS4520 are dependent upon the power supplies, and the thresholds are always referenced to the lower power supply rail. The device is enabled or disabled for the following conditions: * Device enabled: VPD > VS- + 0.8 x (VS+ - VS-) * Device disabled: VPD < VS- + 0.2 x (VS+ - VS-) RS RG RT VSignal RF VS+ RO VCM VBias= VCM THS4520 RG RS RT RO VOUTVOUT+ CM VS- VCM If the PD pin is left open, the device will default to the enabled state. VCM VCM RF Table 3 shows the thresholds for some common power supply configurations: Figure 62. THS4520 DC Coupled Single-Supply with Input Biased to VCM Table 3. Power Supply Configurations In Figure 63 the source is referenced to ground and so is the input termination resistor. RPU is added to the circuit to avoid violating the VICR of the op amp. The proper value of resistor to add can be calculated from Equation 3: Power Supply (VS+, VS-) Enable Threshold (V) Disable Threshold (V) 2.5 V 1.5 -1.5 Shown in data table 1.65 V 1 -1 Shown in data table 22 Comment (4 V , -1 V) 3 0 Split, unbalanced supplies (5 V, gnd) 4 1 Single-sided supply (3.3 V, gnd) 2.64 0.66 Single-sided supply (3 V, gnd) 2.4 0.6 Single-sided supply R PU = (VIC - VS+ ) ae 1 VCM cc e RF ae 1 o 1 // - VIC cc + e R IN R F o o // o (3) VIC is the desired input common-mode voltage, VCM = CM, and RIN = RG+ RS||RT. To set to mid-supply, make the value of RPU = RG+ RS||RT. Submit Documentation Feedback THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 Table 4 is a modification of Table 1 to add the proper values with RPU assuming a 50- source impedance and setting the input and output common-mode voltage to mid-supply. There are two drawbacks to this configuration. One is it requires additional current from the power supply. Using the values shown for a gain of 0 dB requires 10 mA more current with 5-V supply, and 6.5 mA more current with 3.3-V supply. The other drawback is this configuration also increases the noise gain of the circuit. In the 10-dB gain case, noise gain increases by a factor of 1.7. Table 4. RPU Values for Various Gains Gain RF RG RIT RPU 0 dB 499 487 54.9 511 6 dB 499 243 59 270 10 dB 499 150 68.1 178 14 dB 499 93.1 82.5 124 20 dB 499 40.2 221 80.6 FULLY DIFFERENTIAL AMPLIFIER WITH REDUCED PEAKING Figure 65 shows a fully differential amplifier that reduces peaking at low gains. The resistor RC compensates the THS4520 to have higher noise gain (NG), which reduces the AC response peaking (typically 3.8dB at G = +1 without RC) without changing the DC forward gain. The input signal, VIN, is assumed to be from a low impedance source, such as an op amp. When the two feedback paths are symmetrical, the noise gain is given by the expression: R 2RF NG + 1 ) F ) RG RC (4) RG RF VIN VS+ - V S+ RC THS4520 R PU RS RT V Signal + RF RG RG V S+ V S+ CM VS- RO V OUT- R PU THS4520 RG RO RF V OUT+ RS V S- RT VOUT CM Figure 65. THS4520 with Noise Gain Compensation RF Figure 63. THS4520 DC Coupled Single-Supply with RPU Used to Set VIC Figure 64 shows AC coupling to the source. Using capacitors in series with the termination resistors allows the amplifier to self-bias both input and output to mid-supply. C RS V Signal RF RG RT V S+ = 3 V to 5 V RO C V OUTTHS4520 RG RO V OUT+ RS RT C C CM V S- RF Figure 64. THS4520 AC Coupled Single-Supply A unity-gain buffer can be designed by selecting RF = 499 , RG = 499 and RC = open. The resulting forward gain response is similar to the characteristics plots with G = 0dB (see Figure 1), and the noise gain equal to 2. If RC is then made equal to 200 the noise gain increases to 7, which typically gives a frequency response with less peaking and with less bandwidth, and the forward gain remains equal to unity. The plot in Figure 66 shows the measured small-signal AC response of a THS4520 EVM in the default unity-gain configuration (see Figure 72). When the termination resistors present on the EVM (R1, R2, and R12 in Figure 72) and the source resistance of the signal generator (RS = 50 ) are taken into account, the calculated noise gain of the default EVM is NG = 1.97. Also included in the plot are two curves which represent the measured response of the same board with two values of RC, one with RC = 200 (NG = 6.96) and one with RC =487 (NG = 4.02). The low-frequency roll-off of the AC response is due to the transformer (T1 in Figure 72). The curves illustrate the reduced peaking Submit Documentation Feedback 23 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 and the reduced bandwidth due to increased noise gain when the circuit is configured for low forward gain. Note that using noise gain compensation increases the circuit output noise and decreases the circuit bandwidth. Compared to the default configuration (no RC) using RC = 200 and RC = 487 increases the circuit output noise by approximately 10.9dB and 6dB respectively. 4 RC = open 2 0 Gain - dB DV OD I IO + I IORF -6 RC = RG = 487 W NG = 4 -12 DV ODI IB, I IO + 2 -14 1 10 f - Frequency - MHz 100 VIN+ RG2 RF2 VS+ + VIO/2 - + + VIO/2 VOUT+ VN + VIN- RG1 VOD Ideal FDA IIB+ - VOUT- VOCM IIB- VS+ RF1 24 V OCM * V ICM b 1 * b 2 b 1 ) b 2 (9) Note that this source of output error will be negligible if the two feedback paths are well matched. The analysis that leads to the results shown above is beyond the scope of this section. An applications note that shows the detailed analysis will be available in the near future. DEPENDENCE OF HARMONIC DISTORTION ON DEVICE OUTPUT SWING AND SIGNAL FREQUENCY Typical plots of HD2 or HD3 usually show the dependence of these parameters upon a single variable, like frequency, output swing, load, or circuit gain. Operating conditions of interest are usually dependent on several variables that are often spread across several different plots. This forces the designer to interpolate across several plots in an attempt to capture the parameters and operating conditions for his/her application. - VID/2 VP + - DV OD VOCM, V ICM + 2 A DC error model of a fully differential voltage feedback amplifier shown in the following circuit diagram. The output error has four contributing factors in this model: 1. Input offset voltage (VIO). 2. Input offset current (IIO). 3. Input bias currents (IIB+, IIB-) interacting with mismatched feedback networks. 4. Mismatch between input and output common-mode voltages interacting with the mismatched feedback networks. + Where IIB = (IIB+ + IIB-)/2, REQ1,2 = RF1,2 || RG1,2 and 1,2 = RG1,2/(RG1,2 + RF1,2). There is an additional contribution to the output error if the input and output common-mode voltages are mismatched: Summary VI b1 ) b2 (8) DC ERRORS IN A FULLY DIFFERENTIAL AMPLIFIER VID/2 I IBR EQ1 * REQ2 ) I IOR EQ1 ) R EQ2 1000 Figure 66. THS4520 EVM Small Signal Response With and Without Noise Gain Compensation Source (7) If there is mismatch (RF1 RF2 or RG1 RG2), then the output error due to the input bias currents is: -10 -16 0.1 (6) The output error due to the input offset current is given by: RC = 200 W NG = 7 -8 where is often called the feedback factor. RG b+ RG ) RF For additional information, see the applications note Fully Differential Amplifiers (SLOA054). -2 -4 When there is no mismatch between the feedback networks (RF1 = RF2 and RG1 = RG2) the output error due to the input offset voltage is given by: DV ODVIO + V IO RG ) RF + V IOb RG (5) Unlike typical plots where HD2 or HD3 is plotted against a single variable, the plots below show constant contours of THS4520 HD2 and HD3 plotted against the joint parameters of device output swing and signal frequency. These two parameters are of Submit Documentation Feedback THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 particular interest because their joint interaction reflects the usable slewing and bandwidth limits of a device. Output swing and frequency limits are often prime consideration when picking a device and quantifying their joint impact on HD allows a more precise judgment on the ability of a device to meet the need for speed. The curves that separate each colored region represent the value of HD2,3 indicated on the plot. Following a curve over the ranges of output swing and frequency show the conditions over which that value of HD2,3 occurs. Note that the horizontal axis represents the base-10 logarithm of frequency in units of MHz. So on the horizontal axis the value of `2' represents 100 MHz, `1' represents 10 MHz and `0' represents 1 MHz, respectively. This strategy was chosen to provide spacing between curves that allowed the viewer to easily resolve the individual curves. Plotting frequency on a linear scale caused the curves to be crowded and difficult to distinguish. Unfortunately a semilog axis format was not possible because of the plotting function. The measured data in the plots represent measurements of a THS4520 evaluation board in the default unity-gain configuration with RL = 200. For more information on the circuit configuration, see the information on the THS4520 evaluation board later in this section. The first two plots (Figure 67 andFigure 68) are for HD2 and HD3 respectively, with a power supply of 2.5 V. The line labeled Large Signal BW in each of the two plots represents the measured large signal bandwidth over the range of output signal swing in the plot (Vout = 1 Vpp to 8 Vpp). The BW lines fall in the shaded region that represents very poor distortion performance: HD2 > -45dBc or HD3 > -40dBc. The intent in plotting the bandwidth was to provide a realistic comparison between the reported large signal bandwidth and useful distortion performance. The areas between the plots are shaded to help illustrate the 10dB changes in HD2 or HD3 between the adjacent curves. The third and fourth plots (Figure 69andFigure 70) are the constant contours of HD2 and HD3 respectively for a power supply of 1.65 V. Figure 67. Constant HD2 Contours vs Output Swing and log10 (Frequency - MHz) Vs = 2.5 V, Gain = 1, RL = 200 Submit Documentation Feedback 25 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 Figure 68. Constant HD3 Contours vs Output Swing and log10 (Frequency - MHz) Vs = 2.5 V, Gain = 1, RL = 200 Figure 69. Constant HD2 Contours vs Output Swing and log10 (Frequency - MHz) Vs = 1.65 V, Gain = 1, RL = 200 26 Submit Documentation Feedback THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 6 RL=200ohms Vs = 3.3V 5.5 -80dBc -70dBc 5 -60dBc 4.5 -50dBc Vout (Vpp) 4 -40dBc -90dBc 3.5 3 -100dBc 2.5 2 1.5 1 -110dBc 0 0.2 0.4 0.6 0.8 1 1.2 log [Frequency(MHz)] 1.4 1.6 1.8 2 10 Figure 70. Constant HD2 Contours vs Output Swing and log10 (Frequency - MHz) Vs = 1.65 V, Gain = 1, RL = 200 Layout Recommendations It is recommended to follow the layout of the external components near the amplifier, ground plane construction, and power routing of the EVM as closely as possible. General guidelines are: 1. Signal routing should be direct and as short as possible into and out of the op amp circuit. 2. The feedback path should be short and direct avoiding vias. 3. Ground or power planes should be removed from directly under the amplifier's input and output pins. 4. An output resistor is recommended on each output, as near to the output pin as possible. 5. Two 10-F and two 0.1-F power-supply decoupling capacitors should be placed as near to the power-supply pins as possible. 6. Two 0.1-F capacitors should be placed between the CM input pins and ground. This limits noise coupled into the pins. One each should be placed to ground near pin 4 and pin 9. 7. It is recommended to split the ground pane on layer 2 (L2) as shown below and to use a solid ground on layer 3 (L3). A single-point connection should be used between each split section on L2 and L3. 8. A single-point connection to ground on L2 is recommended for the input termination resistors R1 and R2. This should be applied to the input gain resistors if termination is not used. 9. The THS4520 recommended PCB footprint is shown in Figure 71. 0.144 0.049 0.012 Pin 1 0.0095 0.015 0.144 0.0195 0.0705 0.010 vias 0.032 0.030 0.0245 Top View Figure 71. QFN Etch and Via Pattern Submit Documentation Feedback 27 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 THS4520 EVM Figure 72 is the THS4520 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown Figure 73, and Table 5 is the bill of material for the EVM as supplied from TI. GND VS- J4 VS+ J5 J6 VEE 0.1 mF TP1 C9 C10 0.1 mF VCC 10 mF C4 10 mF R3 C15 R12 49.9 W 12 2 3 VO+ - U1 11 0.22 mF + J2 R4 4 487 W R2 53.6 W R9 open 7 PD 487 W VO- PwrPad 10 R7 86.6 W R8 86.6 W 15 13 14 16 VEE R6 J3 T1 R11 69.8 W 6 5 4 R10 open 3 C14 0.1 mF C11 0.1 mF THS4520RGT 6481529 Figure 72. THS4520 EVAL1 EVM Schematic Figure 73. THS4520 EVAL1 EVM Layer 1 through 4 28 C8 open C7 open C2 open J7 499 W TP3 TP2 C1 open 1 XFMR_ADT1-1WT Vocm 9 0.1 mF C12 VCC VCC 8 6 5 0.1 mF C5 J8 499 W R1 53.6 W 10 mF C3 R5 J1 10 mF C6 Submit Documentation Feedback VEE C13 THS4520 www.ti.com SLOS503B - SEPTEMBER 2006 - REVISED JULY 2007 Table 5. THS4520 EVAL1 EVM Bill of Materials ITEM DESCRIPTION SMD SIZE REFERENCE DESIGNATOR PCB QTY MANUFACTURER'S PART NUMBER 1 CAP, 10.0 F, Ceramic, X5R, 6.3V 0805 C3, C4, C5, C6 4 (AVX) 08056D106KAT2A 2 CAP, 0.1 F, Ceramic, X5R, 10V 0402 C9, C10, C11, C12, C13, C14 6 (AVX) 0402ZD104KAT2A 3 CAP, 0.22 F, Ceramic, X5R, 6.3V 0402 C15 1 (AVX) 04026D224KAT2A 4 OPEN 0402 C1, C2, C7, C8 4 5 OPEN 0402 R9, R10 2 6 Resistor, 49.9 , 1/16W, 1% 0402 R12 1 (KOA) RK73H1ETTP49R9F 7 Resistor, 53.6 , 1/16W, 1% 0402 R1, R2 2 (KOA) RK73H1ETTP53R6F 8 Resistor, 69.8 , 1/16W, 1% 0402 R11 1 (KOA) RK73H1ETTP69R8F 9 Resistor, 86.6 , 1/16W, 1% 0402 R7, R8 2 (KOA) RK73H1ETTP86R6F 10 Resistor, 487 , 1/16W, 1% 0402 R3, R4 2 (KOA) RK73H1ETTP4870F 11 Resistor, 499 , 1/16W, 1% 0402 R5, R6 2 (KOA) RK73H1ETTP4990F 12 Transformer, RF T1 1 (MINI-CIRCUITS) ADT1-1WT 13 Jack, banana receptance, 0.25" diameter hole J4, J5, J6 3 (HH SMITH) 101 14 OPEN J1, J7, J8 3 15 Connector, edge, SMA PCB Jack J2, J3 2 (JOHNSON) 142-0701-801 16 Test point, Red TP1, TP2, TP3 3 (KEYSTONE) 5000 17 IC, THS4520 U1 1 (TI) THS4520RGT 18 Standoff, 4-40 HEX, 0.625" length 4 (KEYSTONE) 1808 19 SCREW, PHILLIPS, 4-40, 0.250" 4 SHR-0440-016-SN 20 Printed circuit board 1 (TI) EDGE# 6481529 EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 3 V to 5 V and the output voltage range of 3 V to 5 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 85C. The EVM is designed to operate properly with certain components above 85C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2007, Texas Instruments Incorporated Submit Documentation Feedback 29 PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS4520RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS4520RGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS4520RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS4520RGTTG4 ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS4520RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 THS4520RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4520RGTR QFN RGT 16 3000 367.0 367.0 35.0 THS4520RGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated