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FEATURES DESCRIPTION
APPLICATIONS
RELATED PRODUCTS
THS4520
HARMONICDISTORTION
vs
FREQUENCY
-140
-130
-120
-110
-100
-90
-80
-70
-60
110 100 1000
f-Frequency-kHz
HarmonicDistortion-dBc
HD3
HD2
V =8V ,
G=-1,
R =1K ,
V = 2.5V
OD PP
L
S
W
±
V =open
OCM
+
-
499 W
Differential
Input-VID
+
-
499 W
499 W
499 W
-2.5V
2.5V
1kWDifferential
Output-VOD
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIERWITH RAIL-TO-RAIL OUTPUTS
•Fully Differential Architecture With Rail-to-Rail
The THS4520 is a wideband, fully differentialOutputs
operational amplifier designed for 5-V dataacquisition systems. It has very low noise at•Centered Input Common-mode Range
2 nV/ √Hz, and low harmonic distortion of –115 dBc•Minimum Gain of 1 V/V (0 dB)
HD
2
and –123 dBc HD
3
at 100 kHz with 8 V
PP
, and•Bandwidth: 620 MHz
1-k Ωload. The slew rate is 570 V/ μs, and with asettling time of 7 ns to 0.1% (2-V step), it is ideal for•Slew Rate: 570 V/ μs
data acquisition applications. It is designed for unity•0.1% Settling Time: 7 ns
gain stability.•HD
2
: –115 dBc at 100 kHz, V
OD
= 8 V
PP
To allow for dc coupling to ADCs, its unique output•HD
3
: –123 dBc at 100 kHz, V
OD
= 8 V
PP
common-mode control circuit maintains the output•Input Voltage Noise: 2 nV/ √Hz (f >10 kHz)
common-mode voltage within 0.25 mV offset (typical)from the set voltage. The common-mode set point•Output Common-Mode Control
defaults to mid-supply by internal circuitry, which•Power Supply:
may be over-driven from an external source.– Voltage: 3.3 V ( ±1.65 V) to 5 V ( ±2.5 V)
The input and output are optimized for best– Current: 14.2 mA
performance with their common-mode voltages set to•Power-Down Capability: 15 μA
mid-supply. Along with high performance at lowpower supply voltage, this makes for extremely highperformance single supply 5-V and 3.3-V dataacquisition systems.•5-V and 3.3-V Data Acquisition Systems•High Linearity ADC Amplifier
The THS4520 is offered in a Quad 16-pin leadlessQFN package (RGT), and is characterized for•Wireless Communication
operation over the full industrial temperature range•Test and Measurement
from –40 °C to 85 °C.•Voice Processing Systems
BW Slew Rate THD V
NDevice
(MHZ) (V/ μsec) (dBc) (nV/Hz)
THS4509 2000 6600 -102 at 10 MHz 1.9THS4500 370 2800 -82 at 8 MHz 7THS4130 150 52 -97 at 250 kHz 1.3
Measured HD2/HD3 for G = -1, V
OD
= 8V
PP
, R
L
= 1 K Ω(circuit shown on the left)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS TABLE PER PACKAGE
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
over operating free-air temperature range (unless otherwise noted)
UNIT
V
S–
to V
S+
Supply voltage 6 VV
I
Input voltage ±V
S
V
ID
Differential input voltage 4 VI
O
Output current
(1)
200 mAContinuous power dissipation See Dissipation Rating TableMaximum junction temperature 150 °CT
J
Maximum junction temperature, continuous operation, long term reliability 125 °CT
A
Operating free-air temperature range –40 °C to 85 °CT
stg
Storage temperature range –65 °C to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °CHBM 2000ESD ratings CDM 1500MM 100
(1) The THS4520 incorporates a (QFN) exposed thermal pad on the underside of the chip. See TI technical brief SLMA002 and SLMA004for more information about utilizing the QFN thermally enhanced package.
POWER RATINGPACKAGE
(1)
θ
JC
θ
JA
T
A
≤25 °C T
A
= 85 °C
RGT (16) 2.4 °C/W 39.5 °C/W 2.3 W 225 mW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
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DEVICE INFORMATION
1315 1416
8
67
5
1
3
2
4
12
10
11
9
NC
VIN−
VOUT+
CM
PD
VIN+
VOUT−
CM
VS−
VS+
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
RGT Package
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
(RGT PACKAGE)
DESCRIPTIONNO. NAME
1 NC No internal connection2 V
IN–
Inverting amplifier input3 V
OUT+
Non-inverted amplifier output4, 9 CM Common-mode voltage input5, 6, 7, 8 V
S+
Positive amplifier power supply input10 V
OUT–
Inverted amplifier output11 V
IN+
Non-inverting amplifier inputPowerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation.12 PD
If the PD pin is open (unterminated) the device will default to the enabled state.13, 14, 15, 16 V
S–
Negative amplifier power supply input
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SPECIFICATIONS; V
S+
– V
S–
= 5 V:
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Test conditions unless otherwise noted: V
S+
= +2.5 V, V
S–
= –2.5 V, G = 0 dB, CM = open, V
O
= 2 V
PP
, R
F
= 499 Ω,R
L
= 200 ΩDifferential, T
A
= 25 °C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL
(1)
AC PERFORMANCE
G = 0 dB, V
O
= 100 mV
PP
620 MHz
G = 6 dB, V
O
= 100 mV
PP
450 MHzSmall-Signal Bandwidth
G = 10 dB, V
O
= 100 mV
PP
330 MHz
G = 20 dB, V
O
= 100 mV
PP
120 MHz C
Gain-Bandwidth Product G = 20 dB 1200 MHz
Bandwidth for 0.1 dB flatness G = 6 dB, V
O
= 2 V
PP
30 MHz
Large-Signal Bandwidth G = 6 dB, V
O
= 2 V
PP
132 MHz
Slew Rate (Differential) 570 V/ μs
Rise Time 4
Fall Time 2-V Step 4 CnsSettling Time to 1% 6.2
Settling Time to 0.1% 7
f = 100 kHz
(3)
R
L
= 1 k ΩV
OD
= 8 V
PP
–115
V
OD
= 2 V
PP
–100R
L
= 200Ω
V
OD
= 4 V
PP
–93f = 1 MHz
(4)
V
OD
= 2 V
PP
–101R
L
= 1 k Ω
V
OD
= 4 V
PP
–101 dBc C2
nd
Order Harmonic Distortion
(2)
V
OD
= 2 V
PP
–103R
L
= 200Ω
V
OD
= 4 V
PP
–97f = 8 MHz
(4)
V
OD
= 2 V
PP
–100R
L
= 1 k Ω
V
OD
= 4 V
PP
–95
R
L
= 1 k ΩV
OD
= 8 V
PP
–123f = 100 kHz
(3)
V
OD
= 2 V
PP
–105R
L
= 200Ω
V
OD
= 4 V
PP
–93f = 1 MHz
(4)
V
OD
= 2 V
PP
–101R
L
= 1 k Ω
dBc C3
rd
Order Harmonic Distortion
(2)
V
OD
= 4 V
PP
–96
V
OD
= 2 V
PP
–92R
L
= 200Ω
V
OD
= 4 V
PP
–88f = 8 MHz
(4)
V
OD
= 2 V
PP
–102R
L
= 1 k Ω
V
OD
= 4 V
PP
–91
f
C
= 100 kHz
(3)
, 10-kHz Tone Spacing,
–135R
L
= 1k Ω, V
OD
= 8 V
PP
envelope, G = 0dB
f
C
= 1 MHz
(4)
, 100-kHz Tone Spacing,
-82 dBc C3
rd
Order Intermodulation Distortion
R
L
= 200 Ω, V
OD
= 4 V
PP
envelope, G = 10dB
f
C
= 10 MHz
(4)
, 100-kHz Tone Spacing,
-82R
L
= 200 Ω, V
OD
= 4 V
PP
envelope, G = 10dB
Input Voltage Noise f > 10 kHz 2 nV/ √Hz
Input Current Noise f > 10 kHz 2 pA/ √Hz
(1) Test levels: (A) 100% tested at 25 °C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value only for information.(2) For additional information, see the Typical Characteristics section and the Apllications section.(3) Data collected with applied differential input signal and measured differential output signal.(4) Data collected with applied single-ended input signal and measured differential output signal. See Figure 55 in the Applications/TestCircuits section for additional information.
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THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
SPECIFICATIONS; V
S+
– V
S–
= 5 V: (continued)Test conditions unless otherwise noted: V
S+
= +2.5 V, V
S–
= –2.5 V, G = 0 dB, CM = open, V
O
= 2 V
PP
, R
F
= 499 Ω,R
L
= 200 ΩDifferential, T
A
= 25 °C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL
(1)
DC PERFORMANCE
Open-Loop Voltage Gain (A
OL
) 112 dB C
T
A
= 25 °C±0.25 ±2.5 mVInput Offset Voltage AT
A
= –40 °C to 85 °C±0.25 ±3 mV
Average Offset Voltage Drift T
A
= –40 °C to 85 °C 1 μV/ °C B
T
A
= 25 °C 6.5 10Input Bias Current μA AT
A
= –40 °C to 85 °C 6.4 11
Average Bias Current Drift T
A
= –40 °C to 85 °C 1.9 nA/ °C B
T
A
= 25 °C±0.2 ±2.5Input Offset Current μA AT
A
= –40 °C to 85 °C±0.2 ±3
Average Offset Current Drift T
A
= –40 °C to 85 °C 1.6 nA/ °C B
INPUT
Common-Mode Input Range High 1.75
VCommon-Mode Input Range Low –1.3 B
Common-Mode Rejection Ratio 84 dB
Differential Input Impedance 7.5||0.31 k Ω||pF C
2.67||0.7Common-Mode Input Impedance M Ω||pF C7
OUTPUT
T
A
= 25 °C 1.95 2.16Maximum Output Voltage High VT
A
= –40C to
1.9 2.1685 °CEach output with 100 Ωto mid-supply
T
A
= 25 °C –2.16 –1.95 AMinimum Output Voltage Low VT
A
= –40C to
–2.16 –1.985 °C
Differential Output Voltage Swing T
A
= –40C to 85 °C 7.8 8.64 V
Differential Output Current Drive R
L
= 10 Ω105 mA
COutput Balance Error V
O
= 100 mV, f = 1 MHz –80 dB
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth 230 MHz
Gain 1 V/V
Output Common-Mode Offset from CM input 1.25 V < CM < 3.5 V ±0.25 mV
CCM Input Bias Current 1.25 V < CM < 3.5 V 0.6 μA
CM Input Voltage –1.5 1.5 V
CM Default Voltage CM = 0.5 (V
S+
+ V
S-
) 0 V
POWER SUPPLY
Specified Operating Voltage 3 5 5.25 V C
T
A
= 25 °C 14.2 15.3Maximum Quiescent Current mAT
A
= –40C to 85 °C 14.2 15.5
T
A
= 25 °C 13.1 14.2 AMinimum Quiescent Current mAT
A
= –40C to 85 °C 12.75 14.2
Power Supply Rejection ( ±PSRR) 94 dB
POWERDOWN Referenced to V
s–
Enable Voltage Threshold >1.5 VFor additional information, see the Application
CInformation section of this data sheet.Disable Voltage Threshold <–1.5 V
T
A
= 25 °C 15 70Powerdown Quiescent Current μA AT
A
= –40C to 85 °C 15 75
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SPECIFICATIONS; V
S+
– V
S–
= 3.3 V:
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Test conditions unless otherwise noted: V
S+
= +1.65 V, V
S–
= –1.65 V, G = 0 dB, CM = open, V
O
= 1 V
PP
, R
F
= 499 Ω,R
L
= 200 ΩDifferential, T
A
= 25 °C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL
(1)
AC PERFORMANCE
G = 0 dB, V
O
= 100 mV
PP
600 MHz
G = 6 dB, V
O
= 100 mV
PP
400 MHzSmall-Signal Bandwidth
G = 10 dB, V
O
= 100 mV
PP
310 MHz
G = 20 dB, V
O
= 100 mV
PP
120 MHz C
Gain-Bandwidth Product G = 20 dB 1200 MHz
Bandwidth for 0.1 dB flatness G = 6 dB, V
O
= 1 V
PP
30 MHz
Large-Signal Bandwidth G = 0 dB, V
O
= 1 V
PP
210 MHz
Slew Rate (Differential) 320 V/ μs
Rise Time 4
Fall Time 2-V Step 4 CnsSettling Time to 1% 6.6
Settling Time to 0.1% 7.1
f = 100 kHz
(3)
R
L
= 1 k ΩV
OD
= 4 V
PP
–135
V
OD
= 1 V
PP
–107R
L
= 200 Ω
V
OD
= 2 V
PP
–101f = 1 MHz
(4)
V
OD
= 1 V
PP
–97R
L
= 1 k Ω
V
OD
= 2 V
PP
–103 dBc C2
nd
Order Harmonic Distortion
(2)
V
OD
= 1 V
PP
–108R
L
= 200 Ω
V
OD
= 2 V
PP
–106f = 8 MHz
(4)
V
OD
= 1 V
PP
–98R
L
= 1 k Ω
V
OD
= 2 V
PP
–99
R
L
= 1 k ΩV
OD
= 4 V
PP
–146f = 100 kHz
(3)
V
OD
= 1 V
PP
–112R
L
= 200 Ω
V
OD
= 2 V
PP
–105f = 1 MHz
(4)
V
OD
= 1 V
PP
–94R
L
= 1 k Ω
dBc C3
rd
Order Harmonic Distortion
(2)
V
OD
= 2 V
PP
–103
V
OD
= 1 V
PP
–95R
L
= 200 Ω
V
OD
= 2 V
PP
–90f = 8 MHz
(4)
V
OD
= 1 V
PP
–95R
L
= 1 k Ω
V
OD
= 2 V
PP
–102
f
C
= 1 MHz
(4)
, 100-kHz Tone Spacing,
-80R
L
= 200 Ω, V
OD
= 4 V
PP
envelope, G = 10dB
dBc C3
rd
Order Intermodulation Distortion
f
C
= 10 MHz
(4)
, 100-kHz Tone Spacing,
-80R
L
= 200 Ω, V
OD
= 4 V
PP
envelope, G = 10dB
Input Voltage Noise f > 10 kHz 2 nV/ √Hz
Input Current Noise f > 10 kHz 2 pA/ √Hz
(1) Test levels: (A) 100% tested at 25 °C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value only for information.(2) For additional information, see the Typical Characteristics section and the Apllications section.(3) Data collected with applied differential input signal and measured differential output signal.(4) Data collected with applied single-ended input signal and measured differential output signal. See Figure 55 in the Applications/TestCircuits section for additional information.
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THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
SPECIFICATIONS; V
S+
– V
S–
= 3.3 V: (continued)Test conditions unless otherwise noted: V
S+
= +1.65 V, V
S–
= –1.65 V, G = 0 dB, CM = open, V
O
= 1 V
PP
, R
F
= 499 Ω,R
L
= 200 ΩDifferential, T
A
= 25 °C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL
(1)
DC PERFORMANCE
Open-Loop Voltage Gain (A
OL
) 104 dB
T
A
= 25 °C±0.25 mVInput Offset Voltage CT
A
= –40 °C to 85 °C±0.25 mV
Average Offset Voltage Drift T
A
= –40 °C to 85 °C 1 μV/ °C
T
A
= 25 °C 6.5Input Bias Current μAT
A
= –40 °C to 85 °C 6.4 C
Average Bias Current Drift T
A
= –40 °C to 85 °C 1.9 nA/ °C
T
A
= 25 °C±0.2Input Offset Current μAT
A
= –40 °C to 85 °C±0.2 C
Average Offset Current Drift T
A
= –40 °C to 85 °C 1.6 nA/ °C
INPUT
Common-Mode Input Range High 1.4
V CCommon-Mode Input Range Low –0.45
Common-Mode Rejection Ratio 84 dB
OUTPUT
Maximum Output Voltage High T
A
= 25 °C 1.4Each output with 100 Ωto mid-supply VMinimum Output Voltage Low T
A
= 25 °C –1.4 C
Differential Output Voltage Swing 5.6 V
Differential Output Current Drive R
L
= 10 Ω78 mA
COutput Balance Error V
O
= 100 mV, f = 1 MHz –80 dB
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth 224 MHz
Gain 1 V/V
Output Common-Mode Offset
1.25 V < CM < 3.5 V ±0.25 mV Cfrom CM input
CM Input Bias Current 1.25 V < CM < 3.5 V 0.6 μA
CM Default Voltage CM = 0.5 (V
S+
+ V
S-
) 0 V
POWER SUPPLY
Specified Operating Voltage 3.3 V
Quiescent Current T
A
= 25 °C 13 mA C
Power Supply Rejection ( ±PSRR) 94 dB
POWERDOWN Referenced to V
s–
Enable Voltage Threshold >1 VFor additional information, see the Application Information
Csection of this data sheet.Disable Voltage Threshold <-1 V
Powerdown Quiescent Current 10 μA C
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TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: V
S+
– V
S–
= 5 V
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Test conditions unless otherwise noted: V
S+
= +2.5 V, V
S–
= –2.5 V, CM = open, V
O
= 2 V
PP
, R
F
= 499 Ω, R
L
= 200 ΩDifferential, G = 0 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequency Response Figure 1Large Signal Frequency Response Figure 2HD2 vs Frequency, V
O
= 2 V
PP
Figure 3HD3 vs Frequency, V
O
= 2 V
PP
Figure 4HD2 vs Frequency, V
O
= 4 V
PP
Figure 5HD3 vs Frequency, V
O
= 4 V
PP
Figure 6HD2 vs Output Voltage Swing, f = 1 MHz Figure 7HD3 vs Output Voltage Swing, f = 1 MHz Figure 8HD2 vs Output Voltage Swing, f = 8 MHz Figure 9Harmonic Distortion
(1)
HD3 vs Output Voltage Swing, f = 8 MHz Figure 10HD2 vs Load Resistance, f = 1 MHz Figure 11HD3 vs Load Resistance, f = 1 MHz Figure 12HD2 vs Load Resistance, f = 8 MHz Figure 13HD3 vs Load Resistance, f = 8 MHz Figure 14HD2 vs Output common-mode voltage Figure 15HD3 vs Output common-mode voltage Figure 160.1 dB Flatness Figure 17S-Parameters vs Frequency Figure 18Slew Rate vs Output Voltage Figure 19Gain = 6 dB, V
O
= 4 V
PP
Figure 20Transient Response
Gain = 6 dB, V
O
= 2 V
PP
Figure 21Output Voltage Swing vs Load Resistance Figure 22Input Offset Voltage vs Input Common-Mode Voltage Figure 23Input Bias Current vs Supply Voltage Figure 24Open Loop Gain and Phase vs Frequency Figure 25Input Referred Noise vs Frequency Figure 26Quiescent Current vs Supply Voltage Figure 27Power Supply Current vs Supply Voltage in Powerdown Mode Figure 28Output Balance Error vs Frequency Figure 29CM Small-Signal Frequency Response Figure 30CM Input Bias Current vs CM Input Voltage Figure 31Differential Output Offset Voltage vs CM Input Voltage Figure 32Output Common-Mode Offset vs CM Input Voltage Figure 33
(1) For additional plots, see the Applications section.
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-2
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f-Frequency-MHz
SignalGain-dB
R =499
R =200
F
L
W
W
VO=100mV
V = 2.5V
PP
S±
0
G=20dB
G=14dB
G=10dB
G=0dB
G=6dB
-2
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f-Frequency-MHz
SignalGain-dB
R =499
R =200
F
L
W
W
VO=2V
V = 2.5V
PP
S±
0
G=20dB
G=14dB
G=10dB
G=0dB
G=6dB
-110
-100
-90
-80
-70
-60
-50
f-Frequency-MHz
3rdOrderHarmonicDistortion-dBc
10 100
1
R =2k
LW
R =499 ,
V =2V ,
V =±2.5V
F
O PP
S
W
R =200
LW
R =1k
LW
R =500
LW
-110
-100
-90
-80
-70
-60
-50
1
f-Frequency-MHz
2ndOrderHarmonicDistortion-dBc
10 100
R =499 ,
V =2V ,
V =±2.5V
F
O PP
S
W
R =1k
LW
R =500
LWR =2k
LW
R =200
LW
-110
-100
-90
-80
-70
-60
-50
f-Frequency-MHz
3rdOrderHarmonicDistortion-dBc
1 100
R =200
LW
R =500
LW
R =1k
LW
R =2k
LW
10
R =499 ,
V =4V ,
V =±2.5V
F
O PP
S
W
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
SMALL-SIGNAL
FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE
Figure 1. Figure 2.
HD2 vs FREQUENCY HD3 vs FREQUENCYV
O
= 2V
PP
V
O
= 2V
PP
Figure 3. Figure 4.
HD2 vs FREQUENCY HD3 vs FREQUENCYV
O
= 4V
PP
V
O
= 4V
PP
Figure 5. Figure 6.
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-120
-110
-100
-90
-80
-70
-60
-50
1 2 3 4 5 6 7 8
V -OutputVoltageSwing-V
O PP
2ndOrderHarmonicDistortion-dBc
R =499 ,
V =±2.5V,
f=1MHz
F
S
W
R =100
LW
R =500
LW
R =2k
LW
R =1k
LW
R =200
LW
-120
-110
-100
-90
-80
-70
-60
-50
1 2 3 4 5 6 7 8
V -OutputVoltageSwing-V
O PP
3rdOrderHarmonicDistortion-dBc
R =499 ,
V =±2.5V,
f=1MHz
F
S
W
R =2k
LWR =1k
LW
R =200
LW
R =500
LW
R =100
LW
-110
-105
-100
-95
-90
-85
-80
-75
1 2 3 4 5 6
V -OutputVoltageSwing-V
O PP
2ndOrderHarmonicDistortion-dBc
R =500
LW
R =1k
LW
R =499 ,
V =±2.5V,
f=8MHz
F
S
W
R =2k
LW
R =100
LW
R =200
LW
-110
-105
-100
-95
-90
-85
-80
-75
1 2 3 4 5 6
V -OutputVoltageSwing-V
O PP
3rdOrderHarmonicDistortion-dBc
R =200
LW
R =500
LW
R =1k
LW
R =100
LW
R =2k
LW
R =499 ,
V = 2.5V,
f=8MHz
F
S
W
±
-115
-110
-105
-100
-95
-90
-85
0 500 1000 1500 2000
R -LoadResistance-
LW
3rdOrderHarmonicDistortion-dBc
V =6V
O PP R =499 ,
V =±2.5V,
f=1MHz
F
S
W
V =4V
O PP
V =2V
O PP
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
HD2 vs OUTPUT VOLTAGE SWING HD3 vs OUTPUT VOLTAGE SWINGFREQUENCY = 1MHz FREQUENCY = 1MHz
Figure 7. Figure 8.
HD2 vs OUTPUT VOLTAGE SWING HD3 vs OUTPUT VOLTAGE SWINGFREQUENCY = 8MHz FREQUENCY = 8MHz
Figure 9. Figure 10.
HD2 vs LOAD RESISTANCE HD3 vs LOAD RESISTANCEFREQUENCY = 1MHz FREQUENCY = 1MHz
Figure 11. Figure 12.
10
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-110
-105
-100
-95
-90
-85
-80
0 500 1000 1500 2000
R -LoadResistance-
LW
2ndOrderHarmonicDistortion-dBc
V =2V
O PP
V =4V
O PP
V =6V
O PP
R =499 ,
V =±2.5V,
f=8MHz
F
S
W
-105
-100
-95
-90
-85
-80
0 500 1000 1500 2000
R -LoadResistance-
LW
3rdOrderHarmonicDistortion-dBc
V =2V
O PP
V =6V
O PP
R =499 ,
V =±2.5V,
f=8MHz
F
S
W
V =4V
O PP
-110
-105
-100
-95
-90
-85
-80
-75
-70
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
3rdOrderHarmonicDistortion-dBc
V -OutputCommon-ModeVoltage-V
OCM
R =499 ,
R =200 ,
V =2V ,
V =±2.5V
F
L
O PP
S
W
W
4MHz
8MHz
16MHz
1MHz
2MHz
-105
-100
-95
-90
-85
-80
-75
-70
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
V -OutputCommon-ModeVoltage-V
OCM
2ndOrderHarmonicDistortion-dBc
1MHz
2MHz
4MHz
16MHz
R =499 ,
R =200 ,
V =2V ,
V =±2.5V
F
L
O PP
S
W
W
8MHz
5.5
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
6.5
0.1 1 10 100 1000
f-Frequency-MHz
SignalGain-dB
Gain=6dB,
R =499 ,
R =200 ,
V =2V ,
V = 2.5V
F
L
O PP
S
W
W
±
110 100
-90
-80
-60
-40
-30
-20
-10
10
S-Parameters-dB
1000
S21
S11
S22
S12
f-Frequency-MHz
Gain=0dB
R =499
R =200
F
L
W
W
V =100mV
V = 2.5V
OPP
S±
-70
-50
0
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
HD2 vs LOAD RESISTANCE HD3 vs LOAD RESISTANCEFREQUENCY = 8MHz FREQUENCY = 8MHz
Figure 13. Figure 14.
HD2 vs HD3 vsOUTPUT COMMON-MODE VOLTAGE OUTPUT COMMON-MODE VOLTAGE
Figure 15. Figure 16.
0.1-dB FLATNESS S-PARAMETERS vs FREQUENCY
Figure 17. Figure 18.
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-2
t − Time − 5ns/div
VOD − DifferentialOutputVoltage − V
-1.5
-1
2
0
-2.5
-0.5
-0.5
1
2.5
1.5
OD PP
S
L
V = V
V = 5V
Gain=6dB
R =200 W
4
2.±
SlewRate-V/ sm
200
250
300
350
400
450
500
550
600
0 1 2345 6 7 8
V -DifferentialOutputVoltage-V
OD PP
Gain=6dB
R =499
R =200
F
L
W
W
S
V = 2.5V±
t −Time − 5ns/div
VOD − DifferentialOutputVoltage − V
-1.5
-1
0
-0.5
-0.5
1
1.5
OD PP
S
L
V = V
V = 5V
Gain=6dB
R =200 W
2
2.±
0
1
2
4
7
9
10
10 100 1000
R -LoadResistance-
LW
V Voltage-V
OD -DifferentialOutput
3
5
6
8
V =5V
S
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
1.5 1.7 2 2.4 2.5
V -SupplyVoltage- V
S±
V InputOffsetVoltage- V
IO -m
1.6 1.8 2.11.9 2.2 2.3
T =85 C
A
o
T =25 C
A
o
T =-40 C
A
o
3
3.5
5.5
7
6
6.5
7.5
1.5 1.7 2 2.4 2.5
V -SupplyVoltage- V
S±
I InputBiasVoltage- A
IB -m
1.6 1.8 2.11.9 2.2 2.3
T =85 C
A
o
T =25 C
A
o
T =-40 C
A
o
4
4.5
5
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
SLEW RATE vs OUTPUT VOLTAGE TRANSIENT RESPONSE
Figure 19. Figure 20.
TRANSIENT RESPONSE OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
Figure 21. Figure 22.
INPUT BIAS CURRENTINPUT OFFSET VOLTAGE vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 23. Figure 24.
12
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nV/ Hz
− VoltageNoise −
Vn
In− CurrentNoise −pA/ Hz
1
10
100
10 100 1k 10k 100k 1M
f − Frequency − Hz
Vn
In
1100 10k 1M 100M 10G
OpenLoopGain − dB
OpenLoopPhase − degrees
f − Frequency − Hz
0
20
40
60
80
120
-200
-160
-120
-80
-40
0
40
100 Gain
Phase
10
10.5
12.5
14.5
14
13.5
15
1.5 1.75 2 2.5
V -SupplyVoltage- V
S±
I -mA
Q-QuiescentCurrent
2.25
11
11.5
12
13
T =25 C
A
o
T =-40 C
A
o
T =85 C
A
o
0
1
5
9
8
7
10
1.5 1.75 2 2.5
V -SupplyVoltage- V
S±
PowerSupply - ACurrent m
2.25
2
3
4
6
T =25 C
A
o
T =-40 C
A
o
T =85 C
A
o
-90
-80
-40
-30
-20
0.1 1 1000
f-Frequency-MHz
BalanceError -dB
-60
-50
10 100
-70
Gain=6dB
Gain=0dB
R =499
R =200
F
L
W
W
V =1V
V = 2.5V
OPP
S±
-20
-17
-15
-13
-11
-7
-5
-3
-1
0
1
3
0.1 1 10 100 1000
f-Frequency-MHz
V -SignalGain-dB
OCM
-19
VO=100mV
V = 2.5V
PP
S
R =499
R =200
Gain=0dB
F
L
W
W
±
2
-2
-4
-6
-9
-8
-10
-12
-14
-16
-18
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
OPEN LOOP GAIN AND PHASE vs FREQUENCY INPUT REFERRED NOISE vs FREQUENCY
Figure 25. Figure 26.
POWER SUPPLY CURRENT vs SUPPLY VOLTAGE INQUIESCENT CURRENT vs SUPPLY VOLTAGE POWER-DOWN MODE
Figure 27. Figure 28.
OUTPUT BALANCE ERROR vs FREQUENCY CM SMALL SIGNAL FREQUENCY RESPONSE
Figure 29. Figure 30.
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-150
-100
150
100
200
-2.5 0.50 2.5
V -Common-ModeInputVoltage-V
ICR
Common-ModeInputBias - A
Current m
2
-50
0
50
-2 -1.5 -1 -0.5 1 1.5
-2.5 0.50 2.5
V -Common-ModeInputVoltage-V
ICR
DifferentialOutputOffsetVoltage-mV
2-2 -1.5 -1 -0.5 1 1.5
-7
-6
3
2
4
-5
-2
-1
-4
-3
1
0
-2.5 0.50 2.5
V -Common-ModeInputVoltage-V
ICR
OutputCommon-ModeOffset-mV
2-2 -1.5 -1 -0.5 1 1.5
-50
-40
40
30
50
-30
0
10
-20
-10
20
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
DIFFERENTIAL OUTPUT OFFSET VOLTAGE vsCM INPUT BIAS CURRENT vs CM INPUT VOLTAGE CM INPUT VOLTAGE
Figure 31. Figure 32.
OUTPUT COMMON-MODE OFFSET vsCM INPUT VOLTAGE
Figure 33.
14
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TYPICAL AC PERFORMANCE: V
S+
– V
S–
= 3.3 V
-2
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f-Frequency-MHz
SignalGain-dB
R =499
R =200
F
L
W
W
VO=100mV
V = 1.65V
PP
S±
0
G=20dB
G=14dB
G=10dB
G=0dB
G=6dB
-2
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f-Frequency-MHz
SignalGain-dB
R =499
R =200
F
L
W
W
VO=1V
V = 1.65V
PP
S±
0
G=20dB
G=14dB
G=10dB
G=0dB
G=6dB
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Test conditions unless otherwise noted: V
S+
= 1.65 V, V
S–
= –1.65 V, CM = open, V
OD
= 1 V
PP
, R
F
= 499 Ω, R
L
= 200 ΩDifferential, G = 0 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequency Response Figure 34Large Signal Frequency Response Figure 35HD2 vs Frequency Figure 36HD3 vs Frequency Figure 37HD2 vs Output Voltage Swing, f = 1 MHz Figure 38HD3 vs Output Voltage Swing, f = 1 MHz Figure 39HD2 vs Output Voltage Swing, f = 8 MHz Figure 40HD3 vs Output Voltage Swing, f = 8 MHz Figure 41Harmonic Distortion
(1)
HD2 vs Load Resistance, f = 1 MHz Figure 42HD3 vs Load Resistance, f = 1 MHz Figure 43HD2 vs Load Resistance, f = 8 MHz Figure 44HD3 vs Load Resistance, f = 8 MHz Figure 45HD2 vs Output common-mode voltage, V
O
= 2 V
pp
Figure 46HD3 vs Output common-mode voltage, V
O
= 2 V
pp
Figure 470.1 dB Flatness Figure 48S-Parameters vs Frequency Figure 49Slew Rate vs Output Voltage Figure 50Gain = 6 dB, V
O
= 4 V
pp
Figure 51Transient Response
Gain = 6 dB, V
O
= 2 V
pp
Figure 52Output Balance Error vs Frequency Figure 53CM Input Impedance vs Frequency Figure 54
(1) For additional plots, see the Applications section.
SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE
Figure 34. Figure 35.
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-110
-100
-90
-80
-70
-60
-50
1 100
f-Frequency-MHz
2ndOrderHarmonicDistortion-dBc
10
R =1k
LW
R =2k
LW
R =499 ,
V =2V ,
V =±1.65V
F
O PP
S
W
R =500
LW
R =200
LW
-110
-100
-90
-80
-70
-60
-50
1 10
f-Frequency-MHz
3rdOrderHarmonicDistortion-dBc
100
R =200
LW
R =500
LW
R =1k
LW
R =2k
LW
R =499 ,
V =2V ,
V =±1.65V
F
O PP
S
W
-120
-110
-100
-90
-80
-70
-60
1 2 3 4 5 6
V -OutputVoltageSwing-V
O PP
3rdOrderHarmonicDistortion-dBc
R =200
LW
R =500
LW
R =1k
LW
R =100
LW
R =499 ,
V =±1.65V,
f=1MHz
F
S
W
R =2k
LW
-120
-110
-100
-90
-80
-70
-60
1 2 3 4 5 6
V -OutputVoltageSwing-V
O PP
2ndOrderHarmonicDistortion-dBc
R =200
LW
R =2k
LW
R =1k
LW
R =500
LW
R =100
LW
R =499 ,
V =±1.65V,
f=1MHz
F
S
W
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
1 2 3 4 5 6
V -OutputVoltageSwing-V
O PP
2ndOrderHarmonicDistortion-dBc
R =200
LW
R =2k
LW
R =100
LW
R =499 ,
V =±1.65V,
f=8MHz
F
S
W
R =500
LW
R =1k
LW
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
1 2 3 4 5 6
V -OutputVoltageSwing-V
O PP
3rdOrderHarmonicDistortion-dBc
R =100
LW
R =499 ,
V =±1.65V,
f=8MHz
F
S
W
R =500
LW
R =200
LW
R =1k
LWR =2k
LW
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
HD2 vs FREQUENCY HD3 vs FREQUENCYV
O
= 2V
PP
V
O
= 2V
PP
Figure 36. Figure 37.
HD2 vs OUTPUT VOLTAGE SWING HD3 vs OUTPUT VOLTAGE SWINGFREQUENCY = 1MHz FREQUENCY = 1MHz
Figure 38. Figure 39.
HD2 vs OUTPUT VOLTAGE SWING HD3 vs OUTPUT VOLTAGE SWINGFREQUENCY = 8MHz FREQUENCY = 8MHz
Figure 40. Figure 41.
16
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-120
-110
-100
-90
-80
-70
-60
-50
-40
0 500 1000 1500 2000
R -LoadResistance-
LW
3rdOrderHarmonicDistortion-dBc
V =1V
O PP
V =2V
O PP
V =4V
O PP
R =499 ,
V =±1.65V,
f=1MHz
F
S
W
-120
-110
-100
-90
-80
-70
-60
-50
-40
0 500 1000 1500 2000
R -LoadResistance-
LW
2ndOrderHarmonicDistortion-dBc
V =1V
O PP
V =2V
O PP
V =4V
O PP
R =499 ,
V =±1.65V,
f=8MHz
F
S
W
-110
-100
-90
-80
-70
-60
-50
-40
0 500 1000 1500 2000
R -LoadResistance-
LW
3rdOrderHarmonicDistortion-dBc
V =1V
O PP
V =2V
O PP
V =4V
O PP
R =499 ,
V =±1.65V,
f=8MHz
F
S
W
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-1.25 -0.75 -0.25 0.25 0.75 1.25
V -OutputCommon-ModeVoltage-V
OCM
3rdOrderHarmonicDistortion-dBc
R =499 ,
R =200 ,
V =2V ,
V =±1.65V
F
L
O PP
S
W
W
1MHz
2MHz
16MHz
8MHz
4MHz
-110
-100
-90
-80
-70
-60
-50
-40
-1.25 -1 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1 1.25
V -OutputCommon-ModeVoltage-V
OCM
2ndOrderHarmonicDistortion-dBc
R =499 ,
R =200 ,
V =2V ,
V =±1.65V
F
L
O PP
S
W
W
16MHz
8MHz
4MHz
1MHz
2MHz
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
HD2 vs LOAD RESISTANCE HD3 vs LOAD RESISTANCEFREQUENCY = 1MHZ FREQUENCY = 1MHZ
Figure 42. Figure 43.
HD2 vs LOAD RESISTANCE HD3 vs LOAD RESISTANCEFREQUENCY = 8MHZ FREQUENCY = 8MHZ
Figure 44. Figure 45.
HD2 vs HD3 vsOUTPUT COMMON-MODE VOLTAGE OUTPUT COMMON-MODE VOLTAGE
Figure 46. Figure 47.
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5.5
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
0.1 1 10 100 1000
f-Frequency-MHz
SignalGain-dB
Gain=6dB,
R =499 ,
R =200 ,
V =1V ,
V = 1.65V
F
L
O PP
S
W
W
±
110 100
-90
-80
-60
-40
-30
-20
-10
10
S-Parameters-dB
1000
S21
S11
S22
S12
f-Frequency-MHz
Gain=0dB
R =499
R =200
F
L
W
W
V =100mV
V = .65V
OPP
S±1
-70
-50
0
-2
t − Time − 5ns/div
VOD − DifferentialOutputVoltage − V
-1.5
-1
2
0
-2.5
-0.5
-0.5
1
2.5
1.5
V = V
V = V
OD PP
S
Gain=6dB
R =200
LW
4
1.65±
SlewRate-V/ sm
200
250
300
350
400
450
500
550
600
0 0.5 11.5 22.5 3 3.5 4
V -DifferentialOutputVoltage-V
OD PP
Gain=6dB
R =499
R =200
F
L
W
W
S
V = .65V±1
Fall
Rise
t −Time − 5ns/div
VOD − DifferentialOutputVoltage − V
-1.5
-1
0
-0.5
-0.5
1
1.5
OD PP
S
L
V = V
V = 5V
Gain=6dB
R =200 W
2
1.6±
-90
-80
-40
-30
-20
0.1 1 1000
f-Frequency-MHz
BalanceError -dB
-60
-50
10 100
-70
Gain=6dB
Gain=0dB
R =499
R =200
F
L
W
W
V =1V
V = 1.65V
OPP
S±
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
0.1 dB FLATNESS S-PARAMETERS vs FREQUENCY
Figure 48. Figure 49.
TRANSITION RATE vs OUTPUT VOLTAGE TRANSIENT RESPONSE
Figure 50. Figure 51.
TRANSIENT RESPONSE OUTPUT BALANCE ERROR vs FREQUENCY
Figure 52. Figure 53.
18
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-20
-17
-15
-13
-11
-7
-5
-3
-1
0
1
3
0.1 1 10 100 1000
f-Frequency-MHz
V -SignalGain-dB
OCM
-19
V
R =499
R =200
Gain=0dB
=100mV
V = 1.65V
F
L
PP
S
W
W
O
±
2
-2
-4
-6
-9
-8
-10
-12
-14
-16
-18
TEST CIRCUITS
THS4520
CM
From
50
Source
W
VIN
0.22 Fm
49.9 W
RF
RIT
VS+
VS-
1:1 VOUT
Open
To50 W
Test
Equipment
RG
RIT
RF
ROROT
RO
Frequency Response
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
CM SMALL SIGNAL FREQUENCY RESPONSE
Figure 54.
GAIN R
F
R
G
R
IT
20 dB 499 Ω34.8 Ω115 Ω
Note: The gain setting includes 50- ΩsourceThe THS4520 is tested with the following test circuits
impedance. Components are chosen to achieve gainbuilt on the EVM. For simplicity, power supply
and 50- Ωinput termination.decoupling is not shown – see layout in theapplications section for recommendations.
Table 2. Load Component Values
R
L
R
O
R
OT
Atten.
100 Ω25 Ωopen 6 dB200 Ω86.6 Ω69.8 Ω16.8 dB499 Ω237 Ω56.2 Ω25.5 dB1 k Ω487 Ω52.3 Ω31.8 dB2 k 976 51.1 –37.86
Note: The total load includes 50- Ωtermination by thetest equipment. Components are chosen to achieveFigure 55. General Test Circuit for Device Testing
load and 50- Ωline termination through a 1:1and Characterization
transformer.
Due to the voltage divider on the output formed byDepending on the test conditions, component values
the load component values, the amplifier's output isare changed per the following tables, or as otherwise
attenuated in test. The column Atten in Table 2noted. The signal generators used are ac coupled
shows the attenuation expected from the resistor50- Ωsources and a 0.22- μF capacitor and a 49.9- Ω
divider. When using a transformer at the output theresistor to ground are inserted across R
IT
on the
signal will have slightly more loss, and the numbersalternate input to balance the circuit. A split power
will be approximate.supply is used to ease the interface to common testequipment, but the amplifier can be operatedsingle-supply as described in the applications sectionwith no impact on performance.
The general circit shown in Figure 55 is modified asshown in Figure 56 , and is used to measure theTable 1. Gain Component Values
frequency response of the device.GAIN R
F
R
G
R
IT
A network analyzer is used as the signal source and0 dB 499 Ω487 Ω53.6 Ω
as the measurement device. The output impedance6 dB 499 Ω243 Ω57.6 Ω10 dB 499 Ω147 Ω63.4 Ω14 dB 499 Ω88.7 Ω71.5 Ω
19Submit Documentation Feedback
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THS4520
CM
VIN RF
RF
RG
RG
RIT
RIT
From
50 Ω
Source
0.22 Fm
49.9 W
VOUT+
Open
To50 W
Test
Equipment
VS+
VS− 0.22 Fm
VOUT−
49.9 W
49.9 W
CM Input
OutputMeasured
HereWithHigh
Impedance
DifferentialProbe
THS4520
CM
VIN RF
RF
RG
RG
RIT
RIT
From
50
Source
WVS+
VS−
49.9 W
49.9 W100 W
0.22 Fm
49.9 W0.22 Fm
Open
S-Parameter, Slew Rate, Transient Response,
VS+
CM
VIN From
50-
Source
W
VS–
49.9 W
0.22 Fm
RF
RF
RG
RG
RIT
RIT
VOUT+
V
OUT–
To
50-
Test
Equipment
W
RCMT
RCM
THS4520
49.9 W
0.22 Fm
49.9 W
49.9 W
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
of the network analyzer is 50 Ω. R
IT
and R
G
arechosen to impedance match to 50 Ω, and to maintainthe proper gain. To balance the amplifier, a 0.22- μFcapacitor and 49.9- Ωresistor to ground are insertedacross R
IT
on the alternate input.
The output is probed using a high-impedancedifferential probe across the 100- Ωresistor. The gainis referred to the amplifier output by adding back the6-dB loss due to the voltage divider on the output.
Figure 57. S-Parameter, SR, Transient Response,Settling Time, V
OUT
Swing
The circuit shown in Figure 58 is used to measurethe frequency response of the CM input. Frequencyresponse is measured single-ended at V
OUT+
orV
OUT–
with the input injected at V
IN
, R
CM
= 0 ΩandR
CMT
= 49.9 Ω.Figure 56. Frequency Response Test Circuit
Settling Time, Output Voltage
The circuit shown in Figure 57 is used to measures-parameters, slew rate, transient response, settlingtime, and output voltage swing.
Because S21 is measured single-ended at the loadwith 50- Ωdouble termination, add 12 dB to see theamplifier’s output as a differential signal.
Figure 58. CM Input Test Circuit
20
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APPLICATION INFORMATIONAPPLICATIONS
Differential Input to Differential Output Amplifier
VS
Single-Ended
Input
VS
RF
RF
RG
RGTHS4520
Differential
Output
VOUT+
VOUT–
+
–
–
+
Input Common-Mode Voltage Range
RF
VOUT+
VOUT–
VS+
V
IN–
VS–
RF
RG
RG
VIN+
THS4520
Differential
Input
Differential
Output
+–
–+
÷
÷
ø
ö
ç
ç
è
æ
+
´+
÷
÷
ø
ö
ç
ç
è
æ
+
´= -+
FG
F
IN
FG
G
OUT
IC RR
R
V
RR
R
V
V
(1)
Single-Ended Input to Differential Output
Setting the Output Common-Mode Voltage
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
The following circuits show application informationfor the THS4520. For simplicity, power supplydecoupling capacitors are not shown in thesediagrams. For more detail on the use and operationof fully differential op amps see application reportFully-Differential Amplifiers (SLOA054 ) .
The THS4520 is a fully differential op amp, and canbe used to amplify differential input signals todifferential output signals. A basic block diagram ofthe circuit is shown in Figure 59 (CM input not
Figure 60. Single-Ended Input to Differentialshown). The gain of the circuit is set by R
F
divided by
Output AmplifierR
G
.
The input common-model voltage of a fullydifferential op amp is the voltage at the '+' and '–'input pins of the op amp.
It is important to not violate the input common-modevoltage range (V
ICR
) of the op amp. Assuming the opamp is in linear operation, the differential voltageacross the input pins is only a few millivolts at most.So finding the voltage at one input pin determinesthe input common-mode voltage of the op amp.
Treating the negative input as a summing node, thevoltage is given by Equation 1 :
Figure 59. Differential Input to Differential OutputAmplifier
To determine the V
ICR
of the op amp, the voltage atDepending on the source and load, input and output
the negative input is evaluated at the extremes oftermination can be accomplished by adding R
IT
and
V
OUT+
.R
O
.
As the gain of the op amp increases, the inputcommon-mode voltage becomes closer and closer toAmplifier
the input common-mode voltage of the source.The THS4520 can be used to amplify and convertsingle-ended input signals to differential outputsignals. A basic block diagram of the circuit is shown
The output common-mode voltage is set by thein Figure 60 (CM input not shown). The gain of the
voltage at the CM pin. The internal common-modecircuit is again set by R
F
divided by R
G
.
control circuit maintains the output common-modevoltage within 0.25-mV offset (typical) from the setvoltage, when set within ±0.5 V of mid-supply. If leftunconnected, the common-mode set point is set tomid-supply by internal circuitry, which may beover-driven from an external source. Figure 61 isrepresentative of the CM input. The internal CMcircuit has about 230 MHz of bandwidth, which is
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Single-Supply Operation (3 V to 5 V)
( )
W
--
=-+
k50
VVV2
ISSCM
EXT
(2)
VS+
CM
VS–
50kW
tointernal
CMcircuit
IEXT
50kW
Powerdown Operation: Device
VS+
CM
VSignal
VS–
RF
RF
RG
RG
RT
RO
ROVOUT+
VOUT-
THS4520
VBias= VCM
RS
RT
VCM
VCM
VCM
VCM
RS
( )
÷
÷
ø
ö
ç
ç
è
æ+-
÷
÷
ø
ö
ç
ç
è
æ
-
=+
FIN
IC
F
CM
SIC
PU
R
1
R
1
V
R
1
V
VV
R
(3)
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
required for best performance, but it is intended to bea DC bias input pin. Bypass capacitors are
To facilitate testing with common lab equipment, therecommended on this pin to reduce noise at the
THS4520 EVM allows split-supply operation, and theoutput. The external current required to overdrive the
characterization data presented in this data sheetinternal resistor divider is given by Equation 2 :
was taken with split-supply power inputs. The devicecan easily be used with a single-supply power inputwithout degrading the performance. Figure 62 ,Figure 63 , and Figure 64 show DC and AC-coupledsingle-supply circuits with single-ended inputs. Thesewhere V
CM
is the voltage applied to the CM pin.
configurations all allow the input and outputcommon-mode voltage to be set to mid-supplyallowing for optimum performance. The informationpresented here can also be applied to differentialinput sources.
In Figure 62 , the source is referenced to the samevoltage as the CM pin (V
CM
). V
CM
is set by theinternal circuit to mid-supply. R
T
along with the inputimpedance of the amplifier circuit provides inputtermination, which is also referenced to V
CM
.
Note R
S
and R
T
are added to the alternate input fromthe signal input to balance the amplifier. Alternately,Figure 61. CM Input Circuit
one resistor can be used equal to the combinedvalue R
G
+ R
S
||R
T
on this input. This is also true ofthe circuits shown in Figure 63 and Figure 64 .Enable/Disable ThresholdsThe enable/disable thresholds of the THS4520 aredependent upon the power supplies, and thethresholds are always referenced to the lower powersupply rail. The device is enabled or disabled for thefollowing conditions:
•Device enabled: V
PD
> V
S-
+ 0.8 x (V
S+
- V
S-
)•Device disabled: V
PD
< V
S-
+ 0.2 x (V
S+
- V
S-
)
If the PD pin is left open, the device will default to theenabled state.
Table 3 shows the thresholds for some common
Figure 62. THS4520 DC Coupled Single-Supplypower supply configurations:
with Input Biased to V
CM
Table 3. Power Supply Configurations
In Figure 63 the source is referenced to ground andso is the input termination resistor. R
PU
is added toEnable DisablePower Supply
Threshold Threshold Comment
the circuit to avoid violating the V
ICR
of the op amp.(V
S+
, V
S-
)
(V) (V)
The proper value of resistor to add can be calculatedShown in data
from Equation 3 :±2.5 V 1.5 -1.5
table
Shown in data±1.65 V 1 -1
table
Split, unbalanced(4 V , -1 V) 3 0
supplies
Single-sided
V
IC
is the desired input common-mode voltage,(5 V, gnd) 4 1
supply
V
CM
= CM, and R
IN
= R
G
+ R
S
||R
T
. To set toSingle-sided
mid-supply, make the value of R
PU
= R
G
+ R
S
||R
T
.(3.3 V, gnd) 2.64 0.66
supply
Single-sided(3 V, gnd) 2.4 0.6
supply
22
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FULLY DIFFERENTIAL AMPLIFIER WITH
NG +1)RF
RG)2RF
RC
(4)
CM
-
+
VIN
RGRF
VS+
RC
RG
VOUT
VS-
RF
THS4520
VS+
CM
VSignal
VS-
RF
RF
RG
RG
RT
RO
RO
VOUT+
VOUT-
THS4520
RS
RT
RS
VS+
VS+
RPU
RPU
VS+ =3Vto5V
CM
VSignal
VS-
RF
RF
RG
RG
RT
RO
RO
VOUT+
VOUT-
THS4520
C
RS
RT
C
C
RS
C
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Table 4 is a modification of Table 1 to add the propervalues with R
PU
assuming a 50- Ωsource impedance REDUCED PEAKINGand setting the input and output common-mode
Figure 65 shows a fully differential amplifier thatvoltage to mid-supply.
reduces peaking at low gains. The resistor R
CThere are two drawbacks to this configuration. One compensates the THS4520 to have higher noise gainis it requires additional current from the power (NG), which reduces the AC response peakingsupply. Using the values shown for a gain of 0 dB (typically 3.8dB at G = +1 without R
C
) withoutrequires 10 mA more current with 5-V supply, and changing the DC forward gain. The input signal, V
IN
,6.5 mA more current with 3.3-V supply. is assumed to be from a low impedance source,such as an op amp.The other drawback is this configuration alsoincreases the noise gain of the circuit. In the 10-dB When the two feedback paths are symmetrical, thegain case, noise gain increases by a factor of 1.7. noise gain is given by the expression:
Table 4. RPU Values for Various Gains
Gain R
F
R
G
R
IT
R
PU
0 dB 499 Ω487 Ω54.9 Ω511 Ω6 dB 499 Ω243 Ω59 Ω270 Ω10 dB 499 Ω150 Ω68.1 Ω178 Ω14 dB 499 Ω93.1 Ω82.5 Ω124 Ω20 dB 499 Ω40.2 Ω221 Ω80.6 Ω
Figure 65. THS4520 with Noise GainCompensation
A unity-gain buffer can be designed by selecting R
FFigure 63. THS4520 DC Coupled Single-Supply
= 499 Ω, R
G
= 499 Ωand R
C
= open. The resultingwith R
PU
Used to Set V
IC
forward gain response is similar to the characteristicsplots with G = 0dB (see Figure 1 ), and the noise gainFigure 64 shows AC coupling to the source. Using
equal to 2. If R
C
is then made equal to 200 Ωthecapacitors in series with the termination resistors
noise gain increases to 7, which typically gives aallows the amplifier to self-bias both input and output
frequency response with less peaking and with lessto mid-supply.
bandwidth, and the forward gain remains equal tounity.
The plot in Figure 66 shows the measuredsmall-signal AC response of a THS4520 EVM in thedefault unity-gain configuration (see Figure 72 ).When the termination resistors present on the EVM(R1, R2, and R12 in Figure 72 ) and the sourceresistance of the signal generator (R
S
= 50 Ω) aretaken into account, the calculated noise gain of thedefault EVM is NG = 1.97. Also included in the plotare two curves which represent the measuredresponse of the same board with two values of R
C
,one with R
C
= 200 Ω(NG = 6.96) and one with R
CFigure 64. THS4520 AC Coupled Single-Supply
=487 Ω(NG = 4.02). The low-frequency roll-off of theAC response is due to the transformer (T1 inFigure 72 ). The curves illustrate the reduced peaking
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DVODǒVIOǓ+VIORG )RF
RG +VIOńb
(5)
b+RG
RG )RF
(6)
DVODǒIIOǓ+IIORF
(7)
DVODǒIIB, IIOǓ+2IIBǒREQ1 *REQ2Ǔ)IIOǒREQ1 )REQ2Ǔ
ǒb1)b2Ǔ
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
0.1 1 10 100 1000
f-Frequency-MHz
Gain-dB
R =open
C
R =200
NG=7
CW
R =R =487
NG=4
C G W
DC ERRORS IN A FULLY DIFFERENTIAL
Summary
DVODǒVOCM, VICMǓ+2 ǒVOCM *VICMǓǒb1*b2Ǔ
ǒb1)b2Ǔ
DEPENDENCE OF HARMONIC DISTORTION
RF1
RG2
VOUT-
Source
+
-
+
-
+
-
+
-
+
-
-
+
VI
V /2
ID
V /2
ID
VIN+
VIN-
RG1
V /2
IO
V /2
IO
IIB+
VP
VN
IIB-
VS+
VS+
VOCM
RF2
VOD
VOUT+
Ideal
FDA
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
and the reduced bandwidth due to increased noise When there is no mismatch between the feedbackgain when the circuit is configured for low forward networks (RF
1
= RF
2
and RG
1
= RG
2
) the outputgain. Note that using noise gain compensation error due to the input offset voltage is given by:increases the circuit output noise and decreases thecircuit bandwidth. Compared to the defaultconfiguration (no R
C
) using R
C
= 200 Ωand R
C
=
where βis often called the feedback factor.487 Ωincreases the circuit output noise byapproximately 10.9dB and 6dB respectively.
For additional information, see the applications noteFully Differential Amplifiers (SLOA054 ).
The output error due to the input offset current isgiven by:
If there is mismatch (RF
1
≠RF
2
or RG
1
≠RG
2
), thenthe output error due to the input bias currents is:
(8)
Where I
IB
= (I
IB+
+ I
IB–
)/2, R
EQ1,2
= RF
1,2
|| RG
1,2
andFigure 66. THS4520 EVM Small Signal Response
β
1,2
= RG
1,2
/(RG
1,2
+ RF
1,2
).With and Without Noise Gain Compensation
There is an additional contribution to the output errorif the input and output common-mode voltages aremismatched:AMPLIFIER
A DC error model of a fully differential voltage
(9)feedback amplifier shown in the following circuit
Note that this source of output error will be negligiblediagram. The output error has four contributing
if the two feedback paths are well matched. Thefactors in this model:
analysis that leads to the results shown above is1. Input offset voltage (V
IO
).
beyond the scope of this section. An applications2. Input offset current (I
IO
).
note that shows the detailed analysis will beavailable in the near future.3. Input bias currents (I
IB+
, I
IB–
) interacting withmismatched feedback networks.4. Mismatch between input and output
ON DEVICE OUTPUT SWING AND SIGNALcommon-mode voltages interacting with the
FREQUENCYmismatched feedback networks.
Typical plots of HD2 or HD3 usually show thedependence of these parameters upon a singlevariable, like frequency, output swing, load, or circuitgain. Operating conditions of interest are usuallydependent on several variables that are often spreadacross several different plots. This forces thedesigner to interpolate across several plots in anattempt to capture the parameters and operatingconditions for his/her application.
Unlike typical plots where HD2 or HD3 is plottedagainst a single variable, the plots below showconstant contours of THS4520 HD2 and HD3 plottedagainst the joint parameters of device output swingand signal frequency. These two parameters are of
24
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THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
particular interest because their joint interaction represent measurements of a THS4520 evaluationreflects the usable slewing and bandwidth limits of a board in the default unity-gain configuration with R
L
=device. Output swing and frequency limits are often 200 Ω. For more information on the circuitprime consideration when picking a device and configuration, see the information on the THS4520quantifying their joint impact on HD allows a more evaluation board later in this section.precise judgment on the ability of a device to meet
The first two plots (Figure 67 andFigure 68 ) are forthe need for speed. The curves that separate each
HD2 and HD3 respectively, with a power supply ofcolored region represent the value of HD2,3
±2.5 V. The line labeled Large Signal BW in each ofindicated on the plot. Following a curve over the
the two plots represents the measured large signalranges of output swing and frequency show the
bandwidth over the range of output signal swing inconditions over which that value of HD2,3 occurs.
the plot (V
out
= 1 V
pp
to 8 V
pp
). The BW lines fall inNote that the horizontal axis represents the base-10 the shaded region that represents very poorlogarithm of frequency in units of MHz. So on the distortion performance: HD2 > –45dBc or HD3 >horizontal axis the value of ‘2’ represents 100 MHz, –40dBc. The intent in plotting the bandwidth was to‘1’ represents 10 MHz and ‘0’ represents 1 MHz, provide a realistic comparison between the reportedrespectively. This strategy was chosen to provide large signal bandwidth and useful distortionspacing between curves that allowed the viewer to performance. The areas between the plots areeasily resolve the individual curves. Plotting shaded to help illustrate the 10dB changes in HD2 orfrequency on a linear scale caused the curves to be HD3 between the adjacent curves. The third andcrowded and difficult to distinguish. Unfortunately a fourth plots (Figure 69 andFigure 70 ) are the constantsemilog axis format was not possible because of the contours of HD2 and HD3 respectively for a powerplotting function. The measured data in the plots supply of ±1.65 V.
Figure 67. Constant HD2 Contours vs Output Swing and log
10
(Frequency - MHz)V
s
= 2.5 V, Gain = 1, R
L
= 200 Ω
25Submit Documentation Feedback
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THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Figure 68. Constant HD3 Contours vs Output Swing and log
10
(Frequency - MHz)V
s
= 2.5 V, Gain = 1, R
L
= 200 Ω
Figure 69. Constant HD2 Contours vs Output Swing and log
10
(Frequency - MHz)V
s
= 1.65 V, Gain = 1, R
L
= 200 Ω
26
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log
10[Frequency(MHz)]
Vout(Vpp)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-110dBc
-100dBc
-90dBc
-80dBc
-60dBc
-50dBc
-40dBc
-70dBc
RL=200ohms
Vs=3.3V
Layout Recommendations
0.144 0.0195
0.144
0.010
vias
Pin 1
Top View
0.012
0.030
0.0705
0.015
0.0095
0.049
0.032
0.0245
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Figure 70. Constant HD2 Contours vs Output Swing and log
10
(Frequency - MHz)V
s
= 1.65 V, Gain = 1, R
L
= 200 Ω
8. A single-point connection to ground on L2 isrecommended for the input terminationresistors R1 and R2. This should be applied toIt is recommended to follow the layout of the external
the input gain resistors if termination is notcomponents near the amplifier, ground plane
used.construction, and power routing of the EVM as
9. The THS4520 recommended PCB footprint isclosely as possible. General guidelines are:
shown in Figure 71 .1. Signal routing should be direct and as shortas possible into and out of the op amp circuit.2. The feedback path should be short and directavoiding vias.3. Ground or power planes should be removedfrom directly under the amplifier’s input andoutput pins.4. An output resistor is recommended on eachoutput, as near to the output pin as possible.5. Two 10- μF and two 0.1- μF power-supplydecoupling capacitors should be placed asnear to the power-supply pins as possible.6. Two 0.1- μF capacitors should be placedbetween the CM input pins and ground. Thislimits noise coupled into the pins. One eachshould be placed to ground near pin 4 and pin9.7. It is recommended to split the ground pane onlayer 2 (L2) as shown below and to use a
Figure 71. QFN Etch and Via Patternsolid ground on layer 3 (L3). A single-pointconnection should be used between each splitsection on L2 and L3.
27Submit Documentation Feedback
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THS4520 EVM
49.9 W
−
+
J1
R12 C15
0.22 Fm
R1
53.6 W
R3
487 W
R4
487 W
R2
53.6 W
J2
TP2
C14
0.1 mFC11
0.1 mF
TP1
U1 11
2
12
4
Vocm
9
TP3
R6
499 W
1315
14 16
PwrPad 10
VO−
VO+
3
75
86
VCC
499 W
VCC
R5
PD
C9
0.1 mF
C10
0.1 mF
C4
10 mF 10 mF
C6
VEE
VS−
J4 J5
GND
VEE
VS+
J6
C3
10 mF 10 mF
C5
0.1 mF 0.1 mF
C12 C13
J8
J3
T1
16
5
4
R9
open
R7
86.6 W
R8
86.6 W
R10
open
XFMR_ADT1−1WT
3
R11
69.8 W
J7
C8
open
C7
open
C1
open
C2
open
VCC
VEE
6481529
THS4520RGT
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Figure 72 is the THS4520 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown Figure 73 , andTable 5 is the bill of material for the EVM as supplied from TI.
Figure 72. THS4520 EVAL1 EVM Schematic
Figure 73. THS4520 EVAL1 EVM Layer 1 through 4
28
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THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Table 5. THS4520 EVAL1 EVM Bill of Materials
ITEM DESCRIPTION SMD REFERENCE PCB MANUFACTURER'SSIZE DESIGNATOR QTY PART NUMBER
1 CAP, 10.0 μF, Ceramic, X5R, 6.3V 0805 C3, C4, C5, C6 4 (AVX) 08056D106KAT2A2 CAP, 0.1 μF, Ceramic, X5R, 10V 0402 C9, C10, C11, C12, C13, C14 6 (AVX) 0402ZD104KAT2A3 CAP, 0.22 ΩF, Ceramic, X5R, 6.3V 0402 C15 1 (AVX) 04026D224KAT2A4 OPEN 0402 C1, C2, C7, C8 45 OPEN 0402 R9, R10 26 Resistor, 49.9 Ω, 1/16W, 1% 0402 R12 1 (KOA) RK73H1ETTP49R9F7 Resistor, 53.6 Ω, 1/16W, 1% 0402 R1, R2 2 (KOA) RK73H1ETTP53R6F8 Resistor, 69.8 Ω, 1/16W, 1% 0402 R11 1 (KOA) RK73H1ETTP69R8F9 Resistor, 86.6 Ω, 1/16W, 1% 0402 R7, R8 2 (KOA) RK73H1ETTP86R6F10 Resistor, 487 Ω, 1/16W, 1% 0402 R3, R4 2 (KOA) RK73H1ETTP4870F11 Resistor, 499 Ω, 1/16W, 1% 0402 R5, R6 2 (KOA) RK73H1ETTP4990F12 Transformer, RF T1 1 (MINI-CIRCUITS) ADT1-1WT13 Jack, banana receptance, 0.25" diameter J4, J5, J6 3 (HH SMITH) 101hole14 OPEN J1, J7, J8 315 Connector, edge, SMA PCB Jack J2, J3 2 (JOHNSON) 142-0701-80116 Test point, Red TP1, TP2, TP3 3 (KEYSTONE) 500017 IC, THS4520 U1 1 (TI) THS4520RGT18 Standoff, 4-40 HEX, 0.625" length 4 (KEYSTONE) 180819 SCREW, PHILLIPS, 4-40, 0.250" 4 SHR-0440-016-SN20 Printed circuit board 1 (TI) EDGE# 6481529
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 3 V to 5 V and the output voltage range of3 V to 5 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.If there are questions concerning the input range, please contact a TI field representative prior to connectingthe input power.Applying loads outside of the specified output range may result in unintended operation and/or possiblepermanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVMoutput. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 85 ＝C. The EVMis designed to operate properly with certain components above 85 ＝C as long as the input and output rangesare maintained. These components include but are not limited to linear regulators, switching transistors, passtransistors, and current sense resistors. These types of devices can be identified using the EVM schematiclocated in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2007, Texas Instruments Incorporated
29Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS4520RGTR ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4520RGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4520RGTT ACTIVE QFN RGT 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4520RGTTG4 ACTIVE QFN RGT 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Feb-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4520RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
THS4520RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4520RGTR QFN RGT 16 3000 367.0 367.0 35.0
THS4520RGTT QFN RGT 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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